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-rw-r--r--drivers/net/smc911x.c406
-rw-r--r--drivers/net/smc911x.h351
2 files changed, 369 insertions, 388 deletions
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 4e2800205189..2ca4db85f938 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -106,56 +106,6 @@ MODULE_ALIAS("platform:smc911x");
106 */ 106 */
107#define POWER_DOWN 1 107#define POWER_DOWN 1
108 108
109
110/* store this information for the driver.. */
111struct smc911x_local {
112 /*
113 * If I have to wait until the DMA is finished and ready to reload a
114 * packet, I will store the skbuff here. Then, the DMA will send it
115 * out and free it.
116 */
117 struct sk_buff *pending_tx_skb;
118
119 /* version/revision of the SMC911x chip */
120 u16 version;
121 u16 revision;
122
123 /* FIFO sizes */
124 int tx_fifo_kb;
125 int tx_fifo_size;
126 int rx_fifo_size;
127 int afc_cfg;
128
129 /* Contains the current active receive/phy mode */
130 int ctl_rfduplx;
131 int ctl_rspeed;
132
133 u32 msg_enable;
134 u32 phy_type;
135 struct mii_if_info mii;
136
137 /* work queue */
138 struct work_struct phy_configure;
139 int work_pending;
140
141 int tx_throttle;
142 spinlock_t lock;
143
144 struct net_device *netdev;
145
146#ifdef SMC_USE_DMA
147 /* DMA needs the physical address of the chip */
148 u_long physaddr;
149 int rxdma;
150 int txdma;
151 int rxdma_active;
152 int txdma_active;
153 struct sk_buff *current_rx_skb;
154 struct sk_buff *current_tx_skb;
155 struct device *dev;
156#endif
157};
158
159#if SMC_DEBUG > 0 109#if SMC_DEBUG > 0
160#define DBG(n, args...) \ 110#define DBG(n, args...) \
161 do { \ 111 do { \
@@ -203,24 +153,24 @@ static void PRINT_PKT(u_char *buf, int length)
203 153
204 154
205/* this enables an interrupt in the interrupt mask register */ 155/* this enables an interrupt in the interrupt mask register */
206#define SMC_ENABLE_INT(x) do { \ 156#define SMC_ENABLE_INT(lp, x) do { \
207 unsigned int __mask; \ 157 unsigned int __mask; \
208 unsigned long __flags; \ 158 unsigned long __flags; \
209 spin_lock_irqsave(&lp->lock, __flags); \ 159 spin_lock_irqsave(&lp->lock, __flags); \
210 __mask = SMC_GET_INT_EN(); \ 160 __mask = SMC_GET_INT_EN((lp)); \
211 __mask |= (x); \ 161 __mask |= (x); \
212 SMC_SET_INT_EN(__mask); \ 162 SMC_SET_INT_EN((lp), __mask); \
213 spin_unlock_irqrestore(&lp->lock, __flags); \ 163 spin_unlock_irqrestore(&lp->lock, __flags); \
214} while (0) 164} while (0)
215 165
216/* this disables an interrupt from the interrupt mask register */ 166/* this disables an interrupt from the interrupt mask register */
217#define SMC_DISABLE_INT(x) do { \ 167#define SMC_DISABLE_INT(lp, x) do { \
218 unsigned int __mask; \ 168 unsigned int __mask; \
219 unsigned long __flags; \ 169 unsigned long __flags; \
220 spin_lock_irqsave(&lp->lock, __flags); \ 170 spin_lock_irqsave(&lp->lock, __flags); \
221 __mask = SMC_GET_INT_EN(); \ 171 __mask = SMC_GET_INT_EN((lp)); \
222 __mask &= ~(x); \ 172 __mask &= ~(x); \
223 SMC_SET_INT_EN(__mask); \ 173 SMC_SET_INT_EN((lp), __mask); \
224 spin_unlock_irqrestore(&lp->lock, __flags); \ 174 spin_unlock_irqrestore(&lp->lock, __flags); \
225} while (0) 175} while (0)
226 176
@@ -229,7 +179,6 @@ static void PRINT_PKT(u_char *buf, int length)
229 */ 179 */
230static void smc911x_reset(struct net_device *dev) 180static void smc911x_reset(struct net_device *dev)
231{ 181{
232 unsigned long ioaddr = dev->base_addr;
233 struct smc911x_local *lp = netdev_priv(dev); 182 struct smc911x_local *lp = netdev_priv(dev);
234 unsigned int reg, timeout=0, resets=1; 183 unsigned int reg, timeout=0, resets=1;
235 unsigned long flags; 184 unsigned long flags;
@@ -237,13 +186,13 @@ static void smc911x_reset(struct net_device *dev)
237 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__); 186 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
238 187
239 /* Take out of PM setting first */ 188 /* Take out of PM setting first */
240 if ((SMC_GET_PMT_CTRL() & PMT_CTRL_READY_) == 0) { 189 if ((SMC_GET_PMT_CTRL(lp) & PMT_CTRL_READY_) == 0) {
241 /* Write to the bytetest will take out of powerdown */ 190 /* Write to the bytetest will take out of powerdown */
242 SMC_SET_BYTE_TEST(0); 191 SMC_SET_BYTE_TEST(lp, 0);
243 timeout=10; 192 timeout=10;
244 do { 193 do {
245 udelay(10); 194 udelay(10);
246 reg = SMC_GET_PMT_CTRL() & PMT_CTRL_READY_; 195 reg = SMC_GET_PMT_CTRL(lp) & PMT_CTRL_READY_;
247 } while (--timeout && !reg); 196 } while (--timeout && !reg);
248 if (timeout == 0) { 197 if (timeout == 0) {
249 PRINTK("%s: smc911x_reset timeout waiting for PM restore\n", dev->name); 198 PRINTK("%s: smc911x_reset timeout waiting for PM restore\n", dev->name);
@@ -253,15 +202,15 @@ static void smc911x_reset(struct net_device *dev)
253 202
254 /* Disable all interrupts */ 203 /* Disable all interrupts */
255 spin_lock_irqsave(&lp->lock, flags); 204 spin_lock_irqsave(&lp->lock, flags);
256 SMC_SET_INT_EN(0); 205 SMC_SET_INT_EN(lp, 0);
257 spin_unlock_irqrestore(&lp->lock, flags); 206 spin_unlock_irqrestore(&lp->lock, flags);
258 207
259 while (resets--) { 208 while (resets--) {
260 SMC_SET_HW_CFG(HW_CFG_SRST_); 209 SMC_SET_HW_CFG(lp, HW_CFG_SRST_);
261 timeout=10; 210 timeout=10;
262 do { 211 do {
263 udelay(10); 212 udelay(10);
264 reg = SMC_GET_HW_CFG(); 213 reg = SMC_GET_HW_CFG(lp);
265 /* If chip indicates reset timeout then try again */ 214 /* If chip indicates reset timeout then try again */
266 if (reg & HW_CFG_SRST_TO_) { 215 if (reg & HW_CFG_SRST_TO_) {
267 PRINTK("%s: chip reset timeout, retrying...\n", dev->name); 216 PRINTK("%s: chip reset timeout, retrying...\n", dev->name);
@@ -277,7 +226,7 @@ static void smc911x_reset(struct net_device *dev)
277 226
278 /* make sure EEPROM has finished loading before setting GPIO_CFG */ 227 /* make sure EEPROM has finished loading before setting GPIO_CFG */
279 timeout=1000; 228 timeout=1000;
280 while ( timeout-- && (SMC_GET_E2P_CMD() & E2P_CMD_EPC_BUSY_)) { 229 while ( timeout-- && (SMC_GET_E2P_CMD(lp) & E2P_CMD_EPC_BUSY_)) {
281 udelay(10); 230 udelay(10);
282 } 231 }
283 if (timeout == 0){ 232 if (timeout == 0){
@@ -286,24 +235,24 @@ static void smc911x_reset(struct net_device *dev)
286 } 235 }
287 236
288 /* Initialize interrupts */ 237 /* Initialize interrupts */
289 SMC_SET_INT_EN(0); 238 SMC_SET_INT_EN(lp, 0);
290 SMC_ACK_INT(-1); 239 SMC_ACK_INT(lp, -1);
291 240
292 /* Reset the FIFO level and flow control settings */ 241 /* Reset the FIFO level and flow control settings */
293 SMC_SET_HW_CFG((lp->tx_fifo_kb & 0xF) << 16); 242 SMC_SET_HW_CFG(lp, (lp->tx_fifo_kb & 0xF) << 16);
294//TODO: Figure out what appropriate pause time is 243//TODO: Figure out what appropriate pause time is
295 SMC_SET_FLOW(FLOW_FCPT_ | FLOW_FCEN_); 244 SMC_SET_FLOW(lp, FLOW_FCPT_ | FLOW_FCEN_);
296 SMC_SET_AFC_CFG(lp->afc_cfg); 245 SMC_SET_AFC_CFG(lp, lp->afc_cfg);
297 246
298 247
299 /* Set to LED outputs */ 248 /* Set to LED outputs */
300 SMC_SET_GPIO_CFG(0x70070000); 249 SMC_SET_GPIO_CFG(lp, 0x70070000);
301 250
302 /* 251 /*
303 * Deassert IRQ for 1*10us for edge type interrupts 252 * Deassert IRQ for 1*10us for edge type interrupts
304 * and drive IRQ pin push-pull 253 * and drive IRQ pin push-pull
305 */ 254 */
306 SMC_SET_IRQ_CFG( (1 << 24) | INT_CFG_IRQ_EN_ | INT_CFG_IRQ_TYPE_ ); 255 SMC_SET_IRQ_CFG(lp, (1 << 24) | INT_CFG_IRQ_EN_ | INT_CFG_IRQ_TYPE_);
307 256
308 /* clear anything saved */ 257 /* clear anything saved */
309 if (lp->pending_tx_skb != NULL) { 258 if (lp->pending_tx_skb != NULL) {
@@ -319,46 +268,45 @@ static void smc911x_reset(struct net_device *dev)
319 */ 268 */
320static void smc911x_enable(struct net_device *dev) 269static void smc911x_enable(struct net_device *dev)
321{ 270{
322 unsigned long ioaddr = dev->base_addr;
323 struct smc911x_local *lp = netdev_priv(dev); 271 struct smc911x_local *lp = netdev_priv(dev);
324 unsigned mask, cfg, cr; 272 unsigned mask, cfg, cr;
325 unsigned long flags; 273 unsigned long flags;
326 274
327 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__); 275 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
328 276
329 SMC_SET_MAC_ADDR(dev->dev_addr); 277 SMC_SET_MAC_ADDR(lp, dev->dev_addr);
330 278
331 /* Enable TX */ 279 /* Enable TX */
332 cfg = SMC_GET_HW_CFG(); 280 cfg = SMC_GET_HW_CFG(lp);
333 cfg &= HW_CFG_TX_FIF_SZ_ | 0xFFF; 281 cfg &= HW_CFG_TX_FIF_SZ_ | 0xFFF;
334 cfg |= HW_CFG_SF_; 282 cfg |= HW_CFG_SF_;
335 SMC_SET_HW_CFG(cfg); 283 SMC_SET_HW_CFG(lp, cfg);
336 SMC_SET_FIFO_TDA(0xFF); 284 SMC_SET_FIFO_TDA(lp, 0xFF);
337 /* Update TX stats on every 64 packets received or every 1 sec */ 285 /* Update TX stats on every 64 packets received or every 1 sec */
338 SMC_SET_FIFO_TSL(64); 286 SMC_SET_FIFO_TSL(lp, 64);
339 SMC_SET_GPT_CFG(GPT_CFG_TIMER_EN_ | 10000); 287 SMC_SET_GPT_CFG(lp, GPT_CFG_TIMER_EN_ | 10000);
340 288
341 spin_lock_irqsave(&lp->lock, flags); 289 spin_lock_irqsave(&lp->lock, flags);
342 SMC_GET_MAC_CR(cr); 290 SMC_GET_MAC_CR(lp, cr);
343 cr |= MAC_CR_TXEN_ | MAC_CR_HBDIS_; 291 cr |= MAC_CR_TXEN_ | MAC_CR_HBDIS_;
344 SMC_SET_MAC_CR(cr); 292 SMC_SET_MAC_CR(lp, cr);
345 SMC_SET_TX_CFG(TX_CFG_TX_ON_); 293 SMC_SET_TX_CFG(lp, TX_CFG_TX_ON_);
346 spin_unlock_irqrestore(&lp->lock, flags); 294 spin_unlock_irqrestore(&lp->lock, flags);
347 295
348 /* Add 2 byte padding to start of packets */ 296 /* Add 2 byte padding to start of packets */
349 SMC_SET_RX_CFG((2<<8) & RX_CFG_RXDOFF_); 297 SMC_SET_RX_CFG(lp, (2<<8) & RX_CFG_RXDOFF_);
350 298
351 /* Turn on receiver and enable RX */ 299 /* Turn on receiver and enable RX */
352 if (cr & MAC_CR_RXEN_) 300 if (cr & MAC_CR_RXEN_)
353 DBG(SMC_DEBUG_RX, "%s: Receiver already enabled\n", dev->name); 301 DBG(SMC_DEBUG_RX, "%s: Receiver already enabled\n", dev->name);
354 302
355 spin_lock_irqsave(&lp->lock, flags); 303 spin_lock_irqsave(&lp->lock, flags);
356 SMC_SET_MAC_CR( cr | MAC_CR_RXEN_ ); 304 SMC_SET_MAC_CR(lp, cr | MAC_CR_RXEN_);
357 spin_unlock_irqrestore(&lp->lock, flags); 305 spin_unlock_irqrestore(&lp->lock, flags);
358 306
359 /* Interrupt on every received packet */ 307 /* Interrupt on every received packet */
360 SMC_SET_FIFO_RSA(0x01); 308 SMC_SET_FIFO_RSA(lp, 0x01);
361 SMC_SET_FIFO_RSL(0x00); 309 SMC_SET_FIFO_RSL(lp, 0x00);
362 310
363 /* now, enable interrupts */ 311 /* now, enable interrupts */
364 mask = INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_ | INT_EN_RSFL_EN_ | 312 mask = INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_ | INT_EN_RSFL_EN_ |
@@ -369,7 +317,7 @@ static void smc911x_enable(struct net_device *dev)
369 else { 317 else {
370 mask|=INT_EN_RDFO_EN_; 318 mask|=INT_EN_RDFO_EN_;
371 } 319 }
372 SMC_ENABLE_INT(mask); 320 SMC_ENABLE_INT(lp, mask);
373} 321}
374 322
375/* 323/*
@@ -377,7 +325,6 @@ static void smc911x_enable(struct net_device *dev)
377 */ 325 */
378static void smc911x_shutdown(struct net_device *dev) 326static void smc911x_shutdown(struct net_device *dev)
379{ 327{
380 unsigned long ioaddr = dev->base_addr;
381 struct smc911x_local *lp = netdev_priv(dev); 328 struct smc911x_local *lp = netdev_priv(dev);
382 unsigned cr; 329 unsigned cr;
383 unsigned long flags; 330 unsigned long flags;
@@ -385,35 +332,35 @@ static void smc911x_shutdown(struct net_device *dev)
385 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", CARDNAME, __FUNCTION__); 332 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", CARDNAME, __FUNCTION__);
386 333
387 /* Disable IRQ's */ 334 /* Disable IRQ's */
388 SMC_SET_INT_EN(0); 335 SMC_SET_INT_EN(lp, 0);
389 336
390 /* Turn of Rx and TX */ 337 /* Turn of Rx and TX */
391 spin_lock_irqsave(&lp->lock, flags); 338 spin_lock_irqsave(&lp->lock, flags);
392 SMC_GET_MAC_CR(cr); 339 SMC_GET_MAC_CR(lp, cr);
393 cr &= ~(MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_); 340 cr &= ~(MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
394 SMC_SET_MAC_CR(cr); 341 SMC_SET_MAC_CR(lp, cr);
395 SMC_SET_TX_CFG(TX_CFG_STOP_TX_); 342 SMC_SET_TX_CFG(lp, TX_CFG_STOP_TX_);
396 spin_unlock_irqrestore(&lp->lock, flags); 343 spin_unlock_irqrestore(&lp->lock, flags);
397} 344}
398 345
399static inline void smc911x_drop_pkt(struct net_device *dev) 346static inline void smc911x_drop_pkt(struct net_device *dev)
400{ 347{
401 unsigned long ioaddr = dev->base_addr; 348 struct smc911x_local *lp = netdev_priv(dev);
402 unsigned int fifo_count, timeout, reg; 349 unsigned int fifo_count, timeout, reg;
403 350
404 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_RX, "%s: --> %s\n", CARDNAME, __FUNCTION__); 351 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_RX, "%s: --> %s\n", CARDNAME, __FUNCTION__);
405 fifo_count = SMC_GET_RX_FIFO_INF() & 0xFFFF; 352 fifo_count = SMC_GET_RX_FIFO_INF(lp) & 0xFFFF;
406 if (fifo_count <= 4) { 353 if (fifo_count <= 4) {
407 /* Manually dump the packet data */ 354 /* Manually dump the packet data */
408 while (fifo_count--) 355 while (fifo_count--)
409 SMC_GET_RX_FIFO(); 356 SMC_GET_RX_FIFO(lp);
410 } else { 357 } else {
411 /* Fast forward through the bad packet */ 358 /* Fast forward through the bad packet */
412 SMC_SET_RX_DP_CTRL(RX_DP_CTRL_FFWD_BUSY_); 359 SMC_SET_RX_DP_CTRL(lp, RX_DP_CTRL_FFWD_BUSY_);
413 timeout=50; 360 timeout=50;
414 do { 361 do {
415 udelay(10); 362 udelay(10);
416 reg = SMC_GET_RX_DP_CTRL() & RX_DP_CTRL_FFWD_BUSY_; 363 reg = SMC_GET_RX_DP_CTRL(lp) & RX_DP_CTRL_FFWD_BUSY_;
417 } while (--timeout && reg); 364 } while (--timeout && reg);
418 if (timeout == 0) { 365 if (timeout == 0) {
419 PRINTK("%s: timeout waiting for RX fast forward\n", dev->name); 366 PRINTK("%s: timeout waiting for RX fast forward\n", dev->name);
@@ -429,14 +376,14 @@ static inline void smc911x_drop_pkt(struct net_device *dev)
429 */ 376 */
430static inline void smc911x_rcv(struct net_device *dev) 377static inline void smc911x_rcv(struct net_device *dev)
431{ 378{
432 unsigned long ioaddr = dev->base_addr; 379 struct smc911x_local *lp = netdev_priv(dev);
433 unsigned int pkt_len, status; 380 unsigned int pkt_len, status;
434 struct sk_buff *skb; 381 struct sk_buff *skb;
435 unsigned char *data; 382 unsigned char *data;
436 383
437 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_RX, "%s: --> %s\n", 384 DBG(SMC_DEBUG_FUNC | SMC_DEBUG_RX, "%s: --> %s\n",
438 dev->name, __FUNCTION__); 385 dev->name, __FUNCTION__);
439 status = SMC_GET_RX_STS_FIFO(); 386 status = SMC_GET_RX_STS_FIFO(lp);
440 DBG(SMC_DEBUG_RX, "%s: Rx pkt len %d status 0x%08x \n", 387 DBG(SMC_DEBUG_RX, "%s: Rx pkt len %d status 0x%08x \n",
441 dev->name, (status & 0x3fff0000) >> 16, status & 0xc000ffff); 388 dev->name, (status & 0x3fff0000) >> 16, status & 0xc000ffff);
442 pkt_len = (status & RX_STS_PKT_LEN_) >> 16; 389 pkt_len = (status & RX_STS_PKT_LEN_) >> 16;
@@ -473,24 +420,23 @@ static inline void smc911x_rcv(struct net_device *dev)
473 skb_put(skb,pkt_len-4); 420 skb_put(skb,pkt_len-4);
474#ifdef SMC_USE_DMA 421#ifdef SMC_USE_DMA
475 { 422 {
476 struct smc911x_local *lp = netdev_priv(dev);
477 unsigned int fifo; 423 unsigned int fifo;
478 /* Lower the FIFO threshold if possible */ 424 /* Lower the FIFO threshold if possible */
479 fifo = SMC_GET_FIFO_INT(); 425 fifo = SMC_GET_FIFO_INT(lp);
480 if (fifo & 0xFF) fifo--; 426 if (fifo & 0xFF) fifo--;
481 DBG(SMC_DEBUG_RX, "%s: Setting RX stat FIFO threshold to %d\n", 427 DBG(SMC_DEBUG_RX, "%s: Setting RX stat FIFO threshold to %d\n",
482 dev->name, fifo & 0xff); 428 dev->name, fifo & 0xff);
483 SMC_SET_FIFO_INT(fifo); 429 SMC_SET_FIFO_INT(lp, fifo);
484 /* Setup RX DMA */ 430 /* Setup RX DMA */
485 SMC_SET_RX_CFG(RX_CFG_RX_END_ALGN16_ | ((2<<8) & RX_CFG_RXDOFF_)); 431 SMC_SET_RX_CFG(lp, RX_CFG_RX_END_ALGN16_ | ((2<<8) & RX_CFG_RXDOFF_));
486 lp->rxdma_active = 1; 432 lp->rxdma_active = 1;
487 lp->current_rx_skb = skb; 433 lp->current_rx_skb = skb;
488 SMC_PULL_DATA(data, (pkt_len+2+15) & ~15); 434 SMC_PULL_DATA(lp, data, (pkt_len+2+15) & ~15);
489 /* Packet processing deferred to DMA RX interrupt */ 435 /* Packet processing deferred to DMA RX interrupt */
490 } 436 }
491#else 437#else
492 SMC_SET_RX_CFG(RX_CFG_RX_END_ALGN4_ | ((2<<8) & RX_CFG_RXDOFF_)); 438 SMC_SET_RX_CFG(lp, RX_CFG_RX_END_ALGN4_ | ((2<<8) & RX_CFG_RXDOFF_));
493 SMC_PULL_DATA(data, pkt_len+2+3); 439 SMC_PULL_DATA(lp, data, pkt_len+2+3);
494 440
495 DBG(SMC_DEBUG_PKTS, "%s: Received packet\n", dev->name); 441 DBG(SMC_DEBUG_PKTS, "%s: Received packet\n", dev->name);
496 PRINT_PKT(data, ((pkt_len - 4) <= 64) ? pkt_len - 4 : 64); 442 PRINT_PKT(data, ((pkt_len - 4) <= 64) ? pkt_len - 4 : 64);
@@ -509,7 +455,6 @@ static inline void smc911x_rcv(struct net_device *dev)
509static void smc911x_hardware_send_pkt(struct net_device *dev) 455static void smc911x_hardware_send_pkt(struct net_device *dev)
510{ 456{
511 struct smc911x_local *lp = netdev_priv(dev); 457 struct smc911x_local *lp = netdev_priv(dev);
512 unsigned long ioaddr = dev->base_addr;
513 struct sk_buff *skb; 458 struct sk_buff *skb;
514 unsigned int cmdA, cmdB, len; 459 unsigned int cmdA, cmdB, len;
515 unsigned char *buf; 460 unsigned char *buf;
@@ -542,8 +487,8 @@ static void smc911x_hardware_send_pkt(struct net_device *dev)
542 487
543 DBG(SMC_DEBUG_TX, "%s: TX PKT LENGTH 0x%04x (%d) BUF 0x%p CMDA 0x%08x CMDB 0x%08x\n", 488 DBG(SMC_DEBUG_TX, "%s: TX PKT LENGTH 0x%04x (%d) BUF 0x%p CMDA 0x%08x CMDB 0x%08x\n",
544 dev->name, len, len, buf, cmdA, cmdB); 489 dev->name, len, len, buf, cmdA, cmdB);
545 SMC_SET_TX_FIFO(cmdA); 490 SMC_SET_TX_FIFO(lp, cmdA);
546 SMC_SET_TX_FIFO(cmdB); 491 SMC_SET_TX_FIFO(lp, cmdB);
547 492
548 DBG(SMC_DEBUG_PKTS, "%s: Transmitted packet\n", dev->name); 493 DBG(SMC_DEBUG_PKTS, "%s: Transmitted packet\n", dev->name);
549 PRINT_PKT(buf, len <= 64 ? len : 64); 494 PRINT_PKT(buf, len <= 64 ? len : 64);
@@ -551,10 +496,10 @@ static void smc911x_hardware_send_pkt(struct net_device *dev)
551 /* Send pkt via PIO or DMA */ 496 /* Send pkt via PIO or DMA */
552#ifdef SMC_USE_DMA 497#ifdef SMC_USE_DMA
553 lp->current_tx_skb = skb; 498 lp->current_tx_skb = skb;
554 SMC_PUSH_DATA(buf, len); 499 SMC_PUSH_DATA(lp, buf, len);
555 /* DMA complete IRQ will free buffer and set jiffies */ 500 /* DMA complete IRQ will free buffer and set jiffies */
556#else 501#else
557 SMC_PUSH_DATA(buf, len); 502 SMC_PUSH_DATA(lp, buf, len);
558 dev->trans_start = jiffies; 503 dev->trans_start = jiffies;
559 dev_kfree_skb(skb); 504 dev_kfree_skb(skb);
560#endif 505#endif
@@ -563,7 +508,7 @@ static void smc911x_hardware_send_pkt(struct net_device *dev)
563 netif_wake_queue(dev); 508 netif_wake_queue(dev);
564 } 509 }
565 spin_unlock_irqrestore(&lp->lock, flags); 510 spin_unlock_irqrestore(&lp->lock, flags);
566 SMC_ENABLE_INT(INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_); 511 SMC_ENABLE_INT(lp, INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_);
567} 512}
568 513
569/* 514/*
@@ -575,7 +520,6 @@ static void smc911x_hardware_send_pkt(struct net_device *dev)
575static int smc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) 520static int smc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
576{ 521{
577 struct smc911x_local *lp = netdev_priv(dev); 522 struct smc911x_local *lp = netdev_priv(dev);
578 unsigned long ioaddr = dev->base_addr;
579 unsigned int free; 523 unsigned int free;
580 unsigned long flags; 524 unsigned long flags;
581 525
@@ -584,7 +528,7 @@ static int smc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
584 528
585 BUG_ON(lp->pending_tx_skb != NULL); 529 BUG_ON(lp->pending_tx_skb != NULL);
586 530
587 free = SMC_GET_TX_FIFO_INF() & TX_FIFO_INF_TDFREE_; 531 free = SMC_GET_TX_FIFO_INF(lp) & TX_FIFO_INF_TDFREE_;
588 DBG(SMC_DEBUG_TX, "%s: TX free space %d\n", dev->name, free); 532 DBG(SMC_DEBUG_TX, "%s: TX free space %d\n", dev->name, free);
589 533
590 /* Turn off the flow when running out of space in FIFO */ 534 /* Turn off the flow when running out of space in FIFO */
@@ -593,7 +537,7 @@ static int smc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
593 dev->name, free); 537 dev->name, free);
594 spin_lock_irqsave(&lp->lock, flags); 538 spin_lock_irqsave(&lp->lock, flags);
595 /* Reenable when at least 1 packet of size MTU present */ 539 /* Reenable when at least 1 packet of size MTU present */
596 SMC_SET_FIFO_TDA((SMC911X_TX_FIFO_LOW_THRESHOLD)/64); 540 SMC_SET_FIFO_TDA(lp, (SMC911X_TX_FIFO_LOW_THRESHOLD)/64);
597 lp->tx_throttle = 1; 541 lp->tx_throttle = 1;
598 netif_stop_queue(dev); 542 netif_stop_queue(dev);
599 spin_unlock_irqrestore(&lp->lock, flags); 543 spin_unlock_irqrestore(&lp->lock, flags);
@@ -648,7 +592,6 @@ static int smc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
648 */ 592 */
649static void smc911x_tx(struct net_device *dev) 593static void smc911x_tx(struct net_device *dev)
650{ 594{
651 unsigned long ioaddr = dev->base_addr;
652 struct smc911x_local *lp = netdev_priv(dev); 595 struct smc911x_local *lp = netdev_priv(dev);
653 unsigned int tx_status; 596 unsigned int tx_status;
654 597
@@ -656,11 +599,11 @@ static void smc911x_tx(struct net_device *dev)
656 dev->name, __FUNCTION__); 599 dev->name, __FUNCTION__);
657 600
658 /* Collect the TX status */ 601 /* Collect the TX status */
659 while (((SMC_GET_TX_FIFO_INF() & TX_FIFO_INF_TSUSED_) >> 16) != 0) { 602 while (((SMC_GET_TX_FIFO_INF(lp) & TX_FIFO_INF_TSUSED_) >> 16) != 0) {
660 DBG(SMC_DEBUG_TX, "%s: Tx stat FIFO used 0x%04x\n", 603 DBG(SMC_DEBUG_TX, "%s: Tx stat FIFO used 0x%04x\n",
661 dev->name, 604 dev->name,
662 (SMC_GET_TX_FIFO_INF() & TX_FIFO_INF_TSUSED_) >> 16); 605 (SMC_GET_TX_FIFO_INF(lp) & TX_FIFO_INF_TSUSED_) >> 16);
663 tx_status = SMC_GET_TX_STS_FIFO(); 606 tx_status = SMC_GET_TX_STS_FIFO(lp);
664 dev->stats.tx_packets++; 607 dev->stats.tx_packets++;
665 dev->stats.tx_bytes+=tx_status>>16; 608 dev->stats.tx_bytes+=tx_status>>16;
666 DBG(SMC_DEBUG_TX, "%s: Tx FIFO tag 0x%04x status 0x%04x\n", 609 DBG(SMC_DEBUG_TX, "%s: Tx FIFO tag 0x%04x status 0x%04x\n",
@@ -698,10 +641,10 @@ static void smc911x_tx(struct net_device *dev)
698 641
699static int smc911x_phy_read(struct net_device *dev, int phyaddr, int phyreg) 642static int smc911x_phy_read(struct net_device *dev, int phyaddr, int phyreg)
700{ 643{
701 unsigned long ioaddr = dev->base_addr; 644 struct smc911x_local *lp = netdev_priv(dev);
702 unsigned int phydata; 645 unsigned int phydata;
703 646
704 SMC_GET_MII(phyreg, phyaddr, phydata); 647 SMC_GET_MII(lp, phyreg, phyaddr, phydata);
705 648
706 DBG(SMC_DEBUG_MISC, "%s: phyaddr=0x%x, phyreg=0x%02x, phydata=0x%04x\n", 649 DBG(SMC_DEBUG_MISC, "%s: phyaddr=0x%x, phyreg=0x%02x, phydata=0x%04x\n",
707 __FUNCTION__, phyaddr, phyreg, phydata); 650 __FUNCTION__, phyaddr, phyreg, phydata);
@@ -715,12 +658,12 @@ static int smc911x_phy_read(struct net_device *dev, int phyaddr, int phyreg)
715static void smc911x_phy_write(struct net_device *dev, int phyaddr, int phyreg, 658static void smc911x_phy_write(struct net_device *dev, int phyaddr, int phyreg,
716 int phydata) 659 int phydata)
717{ 660{
718 unsigned long ioaddr = dev->base_addr; 661 struct smc911x_local *lp = netdev_priv(dev);
719 662
720 DBG(SMC_DEBUG_MISC, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", 663 DBG(SMC_DEBUG_MISC, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
721 __FUNCTION__, phyaddr, phyreg, phydata); 664 __FUNCTION__, phyaddr, phyreg, phydata);
722 665
723 SMC_SET_MII(phyreg, phyaddr, phydata); 666 SMC_SET_MII(lp, phyreg, phyaddr, phydata);
724} 667}
725 668
726/* 669/*
@@ -729,7 +672,6 @@ static void smc911x_phy_write(struct net_device *dev, int phyaddr, int phyreg,
729 */ 672 */
730static void smc911x_phy_detect(struct net_device *dev) 673static void smc911x_phy_detect(struct net_device *dev)
731{ 674{
732 unsigned long ioaddr = dev->base_addr;
733 struct smc911x_local *lp = netdev_priv(dev); 675 struct smc911x_local *lp = netdev_priv(dev);
734 int phyaddr; 676 int phyaddr;
735 unsigned int cfg, id1, id2; 677 unsigned int cfg, id1, id2;
@@ -745,30 +687,30 @@ static void smc911x_phy_detect(struct net_device *dev)
745 switch(lp->version) { 687 switch(lp->version) {
746 case 0x115: 688 case 0x115:
747 case 0x117: 689 case 0x117:
748 cfg = SMC_GET_HW_CFG(); 690 cfg = SMC_GET_HW_CFG(lp);
749 if (cfg & HW_CFG_EXT_PHY_DET_) { 691 if (cfg & HW_CFG_EXT_PHY_DET_) {
750 cfg &= ~HW_CFG_PHY_CLK_SEL_; 692 cfg &= ~HW_CFG_PHY_CLK_SEL_;
751 cfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_; 693 cfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
752 SMC_SET_HW_CFG(cfg); 694 SMC_SET_HW_CFG(lp, cfg);
753 udelay(10); /* Wait for clocks to stop */ 695 udelay(10); /* Wait for clocks to stop */
754 696
755 cfg |= HW_CFG_EXT_PHY_EN_; 697 cfg |= HW_CFG_EXT_PHY_EN_;
756 SMC_SET_HW_CFG(cfg); 698 SMC_SET_HW_CFG(lp, cfg);
757 udelay(10); /* Wait for clocks to stop */ 699 udelay(10); /* Wait for clocks to stop */
758 700
759 cfg &= ~HW_CFG_PHY_CLK_SEL_; 701 cfg &= ~HW_CFG_PHY_CLK_SEL_;
760 cfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_; 702 cfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
761 SMC_SET_HW_CFG(cfg); 703 SMC_SET_HW_CFG(lp, cfg);
762 udelay(10); /* Wait for clocks to stop */ 704 udelay(10); /* Wait for clocks to stop */
763 705
764 cfg |= HW_CFG_SMI_SEL_; 706 cfg |= HW_CFG_SMI_SEL_;
765 SMC_SET_HW_CFG(cfg); 707 SMC_SET_HW_CFG(lp, cfg);
766 708
767 for (phyaddr = 1; phyaddr < 32; ++phyaddr) { 709 for (phyaddr = 1; phyaddr < 32; ++phyaddr) {
768 710
769 /* Read the PHY identifiers */ 711 /* Read the PHY identifiers */
770 SMC_GET_PHY_ID1(phyaddr & 31, id1); 712 SMC_GET_PHY_ID1(lp, phyaddr & 31, id1);
771 SMC_GET_PHY_ID2(phyaddr & 31, id2); 713 SMC_GET_PHY_ID2(lp, phyaddr & 31, id2);
772 714
773 /* Make sure it is a valid identifier */ 715 /* Make sure it is a valid identifier */
774 if (id1 != 0x0000 && id1 != 0xffff && 716 if (id1 != 0x0000 && id1 != 0xffff &&
@@ -783,8 +725,8 @@ static void smc911x_phy_detect(struct net_device *dev)
783 } 725 }
784 default: 726 default:
785 /* Internal media only */ 727 /* Internal media only */
786 SMC_GET_PHY_ID1(1, id1); 728 SMC_GET_PHY_ID1(lp, 1, id1);
787 SMC_GET_PHY_ID2(1, id2); 729 SMC_GET_PHY_ID2(lp, 1, id2);
788 /* Save the PHY's address */ 730 /* Save the PHY's address */
789 lp->mii.phy_id = 1; 731 lp->mii.phy_id = 1;
790 lp->phy_type = id1 << 16 | id2; 732 lp->phy_type = id1 << 16 | id2;
@@ -801,16 +743,15 @@ static void smc911x_phy_detect(struct net_device *dev)
801static int smc911x_phy_fixed(struct net_device *dev) 743static int smc911x_phy_fixed(struct net_device *dev)
802{ 744{
803 struct smc911x_local *lp = netdev_priv(dev); 745 struct smc911x_local *lp = netdev_priv(dev);
804 unsigned long ioaddr = dev->base_addr;
805 int phyaddr = lp->mii.phy_id; 746 int phyaddr = lp->mii.phy_id;
806 int bmcr; 747 int bmcr;
807 748
808 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__); 749 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
809 750
810 /* Enter Link Disable state */ 751 /* Enter Link Disable state */
811 SMC_GET_PHY_BMCR(phyaddr, bmcr); 752 SMC_GET_PHY_BMCR(lp, phyaddr, bmcr);
812 bmcr |= BMCR_PDOWN; 753 bmcr |= BMCR_PDOWN;
813 SMC_SET_PHY_BMCR(phyaddr, bmcr); 754 SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
814 755
815 /* 756 /*
816 * Set our fixed capabilities 757 * Set our fixed capabilities
@@ -824,11 +765,11 @@ static int smc911x_phy_fixed(struct net_device *dev)
824 bmcr |= BMCR_SPEED100; 765 bmcr |= BMCR_SPEED100;
825 766
826 /* Write our capabilities to the phy control register */ 767 /* Write our capabilities to the phy control register */
827 SMC_SET_PHY_BMCR(phyaddr, bmcr); 768 SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
828 769
829 /* Re-Configure the Receive/Phy Control register */ 770 /* Re-Configure the Receive/Phy Control register */
830 bmcr &= ~BMCR_PDOWN; 771 bmcr &= ~BMCR_PDOWN;
831 SMC_SET_PHY_BMCR(phyaddr, bmcr); 772 SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
832 773
833 return 1; 774 return 1;
834} 775}
@@ -848,7 +789,6 @@ static int smc911x_phy_fixed(struct net_device *dev)
848static int smc911x_phy_reset(struct net_device *dev, int phy) 789static int smc911x_phy_reset(struct net_device *dev, int phy)
849{ 790{
850 struct smc911x_local *lp = netdev_priv(dev); 791 struct smc911x_local *lp = netdev_priv(dev);
851 unsigned long ioaddr = dev->base_addr;
852 int timeout; 792 int timeout;
853 unsigned long flags; 793 unsigned long flags;
854 unsigned int reg; 794 unsigned int reg;
@@ -856,15 +796,15 @@ static int smc911x_phy_reset(struct net_device *dev, int phy)
856 DBG(SMC_DEBUG_FUNC, "%s: --> %s()\n", dev->name, __FUNCTION__); 796 DBG(SMC_DEBUG_FUNC, "%s: --> %s()\n", dev->name, __FUNCTION__);
857 797
858 spin_lock_irqsave(&lp->lock, flags); 798 spin_lock_irqsave(&lp->lock, flags);
859 reg = SMC_GET_PMT_CTRL(); 799 reg = SMC_GET_PMT_CTRL(lp);
860 reg &= ~0xfffff030; 800 reg &= ~0xfffff030;
861 reg |= PMT_CTRL_PHY_RST_; 801 reg |= PMT_CTRL_PHY_RST_;
862 SMC_SET_PMT_CTRL(reg); 802 SMC_SET_PMT_CTRL(lp, reg);
863 spin_unlock_irqrestore(&lp->lock, flags); 803 spin_unlock_irqrestore(&lp->lock, flags);
864 for (timeout = 2; timeout; timeout--) { 804 for (timeout = 2; timeout; timeout--) {
865 msleep(50); 805 msleep(50);
866 spin_lock_irqsave(&lp->lock, flags); 806 spin_lock_irqsave(&lp->lock, flags);
867 reg = SMC_GET_PMT_CTRL(); 807 reg = SMC_GET_PMT_CTRL(lp);
868 spin_unlock_irqrestore(&lp->lock, flags); 808 spin_unlock_irqrestore(&lp->lock, flags);
869 if (!(reg & PMT_CTRL_PHY_RST_)) { 809 if (!(reg & PMT_CTRL_PHY_RST_)) {
870 /* extra delay required because the phy may 810 /* extra delay required because the phy may
@@ -889,13 +829,13 @@ static int smc911x_phy_reset(struct net_device *dev, int phy)
889 */ 829 */
890static void smc911x_phy_powerdown(struct net_device *dev, int phy) 830static void smc911x_phy_powerdown(struct net_device *dev, int phy)
891{ 831{
892 unsigned long ioaddr = dev->base_addr; 832 struct smc911x_local *lp = netdev_priv(dev);
893 unsigned int bmcr; 833 unsigned int bmcr;
894 834
895 /* Enter Link Disable state */ 835 /* Enter Link Disable state */
896 SMC_GET_PHY_BMCR(phy, bmcr); 836 SMC_GET_PHY_BMCR(lp, phy, bmcr);
897 bmcr |= BMCR_PDOWN; 837 bmcr |= BMCR_PDOWN;
898 SMC_SET_PHY_BMCR(phy, bmcr); 838 SMC_SET_PHY_BMCR(lp, phy, bmcr);
899} 839}
900 840
901/* 841/*
@@ -909,7 +849,6 @@ static void smc911x_phy_powerdown(struct net_device *dev, int phy)
909static void smc911x_phy_check_media(struct net_device *dev, int init) 849static void smc911x_phy_check_media(struct net_device *dev, int init)
910{ 850{
911 struct smc911x_local *lp = netdev_priv(dev); 851 struct smc911x_local *lp = netdev_priv(dev);
912 unsigned long ioaddr = dev->base_addr;
913 int phyaddr = lp->mii.phy_id; 852 int phyaddr = lp->mii.phy_id;
914 unsigned int bmcr, cr; 853 unsigned int bmcr, cr;
915 854
@@ -917,8 +856,8 @@ static void smc911x_phy_check_media(struct net_device *dev, int init)
917 856
918 if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) { 857 if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) {
919 /* duplex state has changed */ 858 /* duplex state has changed */
920 SMC_GET_PHY_BMCR(phyaddr, bmcr); 859 SMC_GET_PHY_BMCR(lp, phyaddr, bmcr);
921 SMC_GET_MAC_CR(cr); 860 SMC_GET_MAC_CR(lp, cr);
922 if (lp->mii.full_duplex) { 861 if (lp->mii.full_duplex) {
923 DBG(SMC_DEBUG_MISC, "%s: Configuring for full-duplex mode\n", dev->name); 862 DBG(SMC_DEBUG_MISC, "%s: Configuring for full-duplex mode\n", dev->name);
924 bmcr |= BMCR_FULLDPLX; 863 bmcr |= BMCR_FULLDPLX;
@@ -928,8 +867,8 @@ static void smc911x_phy_check_media(struct net_device *dev, int init)
928 bmcr &= ~BMCR_FULLDPLX; 867 bmcr &= ~BMCR_FULLDPLX;
929 cr &= ~MAC_CR_RCVOWN_; 868 cr &= ~MAC_CR_RCVOWN_;
930 } 869 }
931 SMC_SET_PHY_BMCR(phyaddr, bmcr); 870 SMC_SET_PHY_BMCR(lp, phyaddr, bmcr);
932 SMC_SET_MAC_CR(cr); 871 SMC_SET_MAC_CR(lp, cr);
933 } 872 }
934} 873}
935 874
@@ -947,7 +886,6 @@ static void smc911x_phy_configure(struct work_struct *work)
947 struct smc911x_local *lp = container_of(work, struct smc911x_local, 886 struct smc911x_local *lp = container_of(work, struct smc911x_local,
948 phy_configure); 887 phy_configure);
949 struct net_device *dev = lp->netdev; 888 struct net_device *dev = lp->netdev;
950 unsigned long ioaddr = dev->base_addr;
951 int phyaddr = lp->mii.phy_id; 889 int phyaddr = lp->mii.phy_id;
952 int my_phy_caps; /* My PHY capabilities */ 890 int my_phy_caps; /* My PHY capabilities */
953 int my_ad_caps; /* My Advertised capabilities */ 891 int my_ad_caps; /* My Advertised capabilities */
@@ -972,7 +910,7 @@ static void smc911x_phy_configure(struct work_struct *work)
972 * Enable PHY Interrupts (for register 18) 910 * Enable PHY Interrupts (for register 18)
973 * Interrupts listed here are enabled 911 * Interrupts listed here are enabled
974 */ 912 */
975 SMC_SET_PHY_INT_MASK(phyaddr, PHY_INT_MASK_ENERGY_ON_ | 913 SMC_SET_PHY_INT_MASK(lp, phyaddr, PHY_INT_MASK_ENERGY_ON_ |
976 PHY_INT_MASK_ANEG_COMP_ | PHY_INT_MASK_REMOTE_FAULT_ | 914 PHY_INT_MASK_ANEG_COMP_ | PHY_INT_MASK_REMOTE_FAULT_ |
977 PHY_INT_MASK_LINK_DOWN_); 915 PHY_INT_MASK_LINK_DOWN_);
978 916
@@ -983,7 +921,7 @@ static void smc911x_phy_configure(struct work_struct *work)
983 } 921 }
984 922
985 /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */ 923 /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */
986 SMC_GET_PHY_BMSR(phyaddr, my_phy_caps); 924 SMC_GET_PHY_BMSR(lp, phyaddr, my_phy_caps);
987 if (!(my_phy_caps & BMSR_ANEGCAPABLE)) { 925 if (!(my_phy_caps & BMSR_ANEGCAPABLE)) {
988 printk(KERN_INFO "Auto negotiation NOT supported\n"); 926 printk(KERN_INFO "Auto negotiation NOT supported\n");
989 smc911x_phy_fixed(dev); 927 smc911x_phy_fixed(dev);
@@ -1012,7 +950,7 @@ static void smc911x_phy_configure(struct work_struct *work)
1012 my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL); 950 my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL);
1013 951
1014 /* Update our Auto-Neg Advertisement Register */ 952 /* Update our Auto-Neg Advertisement Register */
1015 SMC_SET_PHY_MII_ADV(phyaddr, my_ad_caps); 953 SMC_SET_PHY_MII_ADV(lp, phyaddr, my_ad_caps);
1016 lp->mii.advertising = my_ad_caps; 954 lp->mii.advertising = my_ad_caps;
1017 955
1018 /* 956 /*
@@ -1021,13 +959,13 @@ static void smc911x_phy_configure(struct work_struct *work)
1021 * the link does not come up. 959 * the link does not come up.
1022 */ 960 */
1023 udelay(10); 961 udelay(10);
1024 SMC_GET_PHY_MII_ADV(phyaddr, status); 962 SMC_GET_PHY_MII_ADV(lp, phyaddr, status);
1025 963
1026 DBG(SMC_DEBUG_MISC, "%s: phy caps=0x%04x\n", dev->name, my_phy_caps); 964 DBG(SMC_DEBUG_MISC, "%s: phy caps=0x%04x\n", dev->name, my_phy_caps);
1027 DBG(SMC_DEBUG_MISC, "%s: phy advertised caps=0x%04x\n", dev->name, my_ad_caps); 965 DBG(SMC_DEBUG_MISC, "%s: phy advertised caps=0x%04x\n", dev->name, my_ad_caps);
1028 966
1029 /* Restart auto-negotiation process in order to advertise my caps */ 967 /* Restart auto-negotiation process in order to advertise my caps */
1030 SMC_SET_PHY_BMCR(phyaddr, BMCR_ANENABLE | BMCR_ANRESTART); 968 SMC_SET_PHY_BMCR(lp, phyaddr, BMCR_ANENABLE | BMCR_ANRESTART);
1031 969
1032 smc911x_phy_check_media(dev, 1); 970 smc911x_phy_check_media(dev, 1);
1033 971
@@ -1046,7 +984,6 @@ smc911x_phy_configure_exit_nolock:
1046static void smc911x_phy_interrupt(struct net_device *dev) 984static void smc911x_phy_interrupt(struct net_device *dev)
1047{ 985{
1048 struct smc911x_local *lp = netdev_priv(dev); 986 struct smc911x_local *lp = netdev_priv(dev);
1049 unsigned long ioaddr = dev->base_addr;
1050 int phyaddr = lp->mii.phy_id; 987 int phyaddr = lp->mii.phy_id;
1051 int status; 988 int status;
1052 989
@@ -1057,11 +994,11 @@ static void smc911x_phy_interrupt(struct net_device *dev)
1057 994
1058 smc911x_phy_check_media(dev, 0); 995 smc911x_phy_check_media(dev, 0);
1059 /* read to clear status bits */ 996 /* read to clear status bits */
1060 SMC_GET_PHY_INT_SRC(phyaddr,status); 997 SMC_GET_PHY_INT_SRC(lp, phyaddr,status);
1061 DBG(SMC_DEBUG_MISC, "%s: PHY interrupt status 0x%04x\n", 998 DBG(SMC_DEBUG_MISC, "%s: PHY interrupt status 0x%04x\n",
1062 dev->name, status & 0xffff); 999 dev->name, status & 0xffff);
1063 DBG(SMC_DEBUG_MISC, "%s: AFC_CFG 0x%08x\n", 1000 DBG(SMC_DEBUG_MISC, "%s: AFC_CFG 0x%08x\n",
1064 dev->name, SMC_GET_AFC_CFG()); 1001 dev->name, SMC_GET_AFC_CFG(lp));
1065} 1002}
1066 1003
1067/*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/ 1004/*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/
@@ -1073,7 +1010,6 @@ static void smc911x_phy_interrupt(struct net_device *dev)
1073static irqreturn_t smc911x_interrupt(int irq, void *dev_id) 1010static irqreturn_t smc911x_interrupt(int irq, void *dev_id)
1074{ 1011{
1075 struct net_device *dev = dev_id; 1012 struct net_device *dev = dev_id;
1076 unsigned long ioaddr = dev->base_addr;
1077 struct smc911x_local *lp = netdev_priv(dev); 1013 struct smc911x_local *lp = netdev_priv(dev);
1078 unsigned int status, mask, timeout; 1014 unsigned int status, mask, timeout;
1079 unsigned int rx_overrun=0, cr, pkts; 1015 unsigned int rx_overrun=0, cr, pkts;
@@ -1084,21 +1020,21 @@ static irqreturn_t smc911x_interrupt(int irq, void *dev_id)
1084 spin_lock_irqsave(&lp->lock, flags); 1020 spin_lock_irqsave(&lp->lock, flags);
1085 1021
1086 /* Spurious interrupt check */ 1022 /* Spurious interrupt check */
1087 if ((SMC_GET_IRQ_CFG() & (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) != 1023 if ((SMC_GET_IRQ_CFG(lp) & (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) !=
1088 (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) { 1024 (INT_CFG_IRQ_INT_ | INT_CFG_IRQ_EN_)) {
1089 spin_unlock_irqrestore(&lp->lock, flags); 1025 spin_unlock_irqrestore(&lp->lock, flags);
1090 return IRQ_NONE; 1026 return IRQ_NONE;
1091 } 1027 }
1092 1028
1093 mask = SMC_GET_INT_EN(); 1029 mask = SMC_GET_INT_EN(lp);
1094 SMC_SET_INT_EN(0); 1030 SMC_SET_INT_EN(lp, 0);
1095 1031
1096 /* set a timeout value, so I don't stay here forever */ 1032 /* set a timeout value, so I don't stay here forever */
1097 timeout = 8; 1033 timeout = 8;
1098 1034
1099 1035
1100 do { 1036 do {
1101 status = SMC_GET_INT(); 1037 status = SMC_GET_INT(lp);
1102 1038
1103 DBG(SMC_DEBUG_MISC, "%s: INT 0x%08x MASK 0x%08x OUTSIDE MASK 0x%08x\n", 1039 DBG(SMC_DEBUG_MISC, "%s: INT 0x%08x MASK 0x%08x OUTSIDE MASK 0x%08x\n",
1104 dev->name, status, mask, status & ~mask); 1040 dev->name, status, mask, status & ~mask);
@@ -1109,53 +1045,53 @@ static irqreturn_t smc911x_interrupt(int irq, void *dev_id)
1109 1045
1110 /* Handle SW interrupt condition */ 1046 /* Handle SW interrupt condition */
1111 if (status & INT_STS_SW_INT_) { 1047 if (status & INT_STS_SW_INT_) {
1112 SMC_ACK_INT(INT_STS_SW_INT_); 1048 SMC_ACK_INT(lp, INT_STS_SW_INT_);
1113 mask &= ~INT_EN_SW_INT_EN_; 1049 mask &= ~INT_EN_SW_INT_EN_;
1114 } 1050 }
1115 /* Handle various error conditions */ 1051 /* Handle various error conditions */
1116 if (status & INT_STS_RXE_) { 1052 if (status & INT_STS_RXE_) {
1117 SMC_ACK_INT(INT_STS_RXE_); 1053 SMC_ACK_INT(lp, INT_STS_RXE_);
1118 dev->stats.rx_errors++; 1054 dev->stats.rx_errors++;
1119 } 1055 }
1120 if (status & INT_STS_RXDFH_INT_) { 1056 if (status & INT_STS_RXDFH_INT_) {
1121 SMC_ACK_INT(INT_STS_RXDFH_INT_); 1057 SMC_ACK_INT(lp, INT_STS_RXDFH_INT_);
1122 dev->stats.rx_dropped+=SMC_GET_RX_DROP(); 1058 dev->stats.rx_dropped+=SMC_GET_RX_DROP(lp);
1123 } 1059 }
1124 /* Undocumented interrupt-what is the right thing to do here? */ 1060 /* Undocumented interrupt-what is the right thing to do here? */
1125 if (status & INT_STS_RXDF_INT_) { 1061 if (status & INT_STS_RXDF_INT_) {
1126 SMC_ACK_INT(INT_STS_RXDF_INT_); 1062 SMC_ACK_INT(lp, INT_STS_RXDF_INT_);
1127 } 1063 }
1128 1064
1129 /* Rx Data FIFO exceeds set level */ 1065 /* Rx Data FIFO exceeds set level */
1130 if (status & INT_STS_RDFL_) { 1066 if (status & INT_STS_RDFL_) {
1131 if (IS_REV_A(lp->revision)) { 1067 if (IS_REV_A(lp->revision)) {
1132 rx_overrun=1; 1068 rx_overrun=1;
1133 SMC_GET_MAC_CR(cr); 1069 SMC_GET_MAC_CR(lp, cr);
1134 cr &= ~MAC_CR_RXEN_; 1070 cr &= ~MAC_CR_RXEN_;
1135 SMC_SET_MAC_CR(cr); 1071 SMC_SET_MAC_CR(lp, cr);
1136 DBG(SMC_DEBUG_RX, "%s: RX overrun\n", dev->name); 1072 DBG(SMC_DEBUG_RX, "%s: RX overrun\n", dev->name);
1137 dev->stats.rx_errors++; 1073 dev->stats.rx_errors++;
1138 dev->stats.rx_fifo_errors++; 1074 dev->stats.rx_fifo_errors++;
1139 } 1075 }
1140 SMC_ACK_INT(INT_STS_RDFL_); 1076 SMC_ACK_INT(lp, INT_STS_RDFL_);
1141 } 1077 }
1142 if (status & INT_STS_RDFO_) { 1078 if (status & INT_STS_RDFO_) {
1143 if (!IS_REV_A(lp->revision)) { 1079 if (!IS_REV_A(lp->revision)) {
1144 SMC_GET_MAC_CR(cr); 1080 SMC_GET_MAC_CR(lp, cr);
1145 cr &= ~MAC_CR_RXEN_; 1081 cr &= ~MAC_CR_RXEN_;
1146 SMC_SET_MAC_CR(cr); 1082 SMC_SET_MAC_CR(lp, cr);
1147 rx_overrun=1; 1083 rx_overrun=1;
1148 DBG(SMC_DEBUG_RX, "%s: RX overrun\n", dev->name); 1084 DBG(SMC_DEBUG_RX, "%s: RX overrun\n", dev->name);
1149 dev->stats.rx_errors++; 1085 dev->stats.rx_errors++;
1150 dev->stats.rx_fifo_errors++; 1086 dev->stats.rx_fifo_errors++;
1151 } 1087 }
1152 SMC_ACK_INT(INT_STS_RDFO_); 1088 SMC_ACK_INT(lp, INT_STS_RDFO_);
1153 } 1089 }
1154 /* Handle receive condition */ 1090 /* Handle receive condition */
1155 if ((status & INT_STS_RSFL_) || rx_overrun) { 1091 if ((status & INT_STS_RSFL_) || rx_overrun) {
1156 unsigned int fifo; 1092 unsigned int fifo;
1157 DBG(SMC_DEBUG_RX, "%s: RX irq\n", dev->name); 1093 DBG(SMC_DEBUG_RX, "%s: RX irq\n", dev->name);
1158 fifo = SMC_GET_RX_FIFO_INF(); 1094 fifo = SMC_GET_RX_FIFO_INF(lp);
1159 pkts = (fifo & RX_FIFO_INF_RXSUSED_) >> 16; 1095 pkts = (fifo & RX_FIFO_INF_RXSUSED_) >> 16;
1160 DBG(SMC_DEBUG_RX, "%s: Rx FIFO pkts %d, bytes %d\n", 1096 DBG(SMC_DEBUG_RX, "%s: Rx FIFO pkts %d, bytes %d\n",
1161 dev->name, pkts, fifo & 0xFFFF ); 1097 dev->name, pkts, fifo & 0xFFFF );
@@ -1166,61 +1102,61 @@ static irqreturn_t smc911x_interrupt(int irq, void *dev_id)
1166 DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA, 1102 DBG(SMC_DEBUG_RX | SMC_DEBUG_DMA,
1167 "%s: RX DMA active\n", dev->name); 1103 "%s: RX DMA active\n", dev->name);
1168 /* The DMA is already running so up the IRQ threshold */ 1104 /* The DMA is already running so up the IRQ threshold */
1169 fifo = SMC_GET_FIFO_INT() & ~0xFF; 1105 fifo = SMC_GET_FIFO_INT(lp) & ~0xFF;
1170 fifo |= pkts & 0xFF; 1106 fifo |= pkts & 0xFF;
1171 DBG(SMC_DEBUG_RX, 1107 DBG(SMC_DEBUG_RX,
1172 "%s: Setting RX stat FIFO threshold to %d\n", 1108 "%s: Setting RX stat FIFO threshold to %d\n",
1173 dev->name, fifo & 0xff); 1109 dev->name, fifo & 0xff);
1174 SMC_SET_FIFO_INT(fifo); 1110 SMC_SET_FIFO_INT(lp, fifo);
1175 } else 1111 } else
1176#endif 1112#endif
1177 smc911x_rcv(dev); 1113 smc911x_rcv(dev);
1178 } 1114 }
1179 SMC_ACK_INT(INT_STS_RSFL_); 1115 SMC_ACK_INT(lp, INT_STS_RSFL_);
1180 } 1116 }
1181 /* Handle transmit FIFO available */ 1117 /* Handle transmit FIFO available */
1182 if (status & INT_STS_TDFA_) { 1118 if (status & INT_STS_TDFA_) {
1183 DBG(SMC_DEBUG_TX, "%s: TX data FIFO space available irq\n", dev->name); 1119 DBG(SMC_DEBUG_TX, "%s: TX data FIFO space available irq\n", dev->name);
1184 SMC_SET_FIFO_TDA(0xFF); 1120 SMC_SET_FIFO_TDA(lp, 0xFF);
1185 lp->tx_throttle = 0; 1121 lp->tx_throttle = 0;
1186#ifdef SMC_USE_DMA 1122#ifdef SMC_USE_DMA
1187 if (!lp->txdma_active) 1123 if (!lp->txdma_active)
1188#endif 1124#endif
1189 netif_wake_queue(dev); 1125 netif_wake_queue(dev);
1190 SMC_ACK_INT(INT_STS_TDFA_); 1126 SMC_ACK_INT(lp, INT_STS_TDFA_);
1191 } 1127 }
1192 /* Handle transmit done condition */ 1128 /* Handle transmit done condition */
1193#if 1 1129#if 1
1194 if (status & (INT_STS_TSFL_ | INT_STS_GPT_INT_)) { 1130 if (status & (INT_STS_TSFL_ | INT_STS_GPT_INT_)) {
1195 DBG(SMC_DEBUG_TX | SMC_DEBUG_MISC, 1131 DBG(SMC_DEBUG_TX | SMC_DEBUG_MISC,
1196 "%s: Tx stat FIFO limit (%d) /GPT irq\n", 1132 "%s: Tx stat FIFO limit (%d) /GPT irq\n",
1197 dev->name, (SMC_GET_FIFO_INT() & 0x00ff0000) >> 16); 1133 dev->name, (SMC_GET_FIFO_INT(lp) & 0x00ff0000) >> 16);
1198 smc911x_tx(dev); 1134 smc911x_tx(dev);
1199 SMC_SET_GPT_CFG(GPT_CFG_TIMER_EN_ | 10000); 1135 SMC_SET_GPT_CFG(lp, GPT_CFG_TIMER_EN_ | 10000);
1200 SMC_ACK_INT(INT_STS_TSFL_); 1136 SMC_ACK_INT(lp, INT_STS_TSFL_);
1201 SMC_ACK_INT(INT_STS_TSFL_ | INT_STS_GPT_INT_); 1137 SMC_ACK_INT(lp, INT_STS_TSFL_ | INT_STS_GPT_INT_);
1202 } 1138 }
1203#else 1139#else
1204 if (status & INT_STS_TSFL_) { 1140 if (status & INT_STS_TSFL_) {
1205 DBG(SMC_DEBUG_TX, "%s: TX status FIFO limit (%d) irq \n", dev->name, ); 1141 DBG(SMC_DEBUG_TX, "%s: TX status FIFO limit (%d) irq \n", dev->name, );
1206 smc911x_tx(dev); 1142 smc911x_tx(dev);
1207 SMC_ACK_INT(INT_STS_TSFL_); 1143 SMC_ACK_INT(lp, INT_STS_TSFL_);
1208 } 1144 }
1209 1145
1210 if (status & INT_STS_GPT_INT_) { 1146 if (status & INT_STS_GPT_INT_) {
1211 DBG(SMC_DEBUG_RX, "%s: IRQ_CFG 0x%08x FIFO_INT 0x%08x RX_CFG 0x%08x\n", 1147 DBG(SMC_DEBUG_RX, "%s: IRQ_CFG 0x%08x FIFO_INT 0x%08x RX_CFG 0x%08x\n",
1212 dev->name, 1148 dev->name,
1213 SMC_GET_IRQ_CFG(), 1149 SMC_GET_IRQ_CFG(lp),
1214 SMC_GET_FIFO_INT(), 1150 SMC_GET_FIFO_INT(lp),
1215 SMC_GET_RX_CFG()); 1151 SMC_GET_RX_CFG(lp));
1216 DBG(SMC_DEBUG_RX, "%s: Rx Stat FIFO Used 0x%02x " 1152 DBG(SMC_DEBUG_RX, "%s: Rx Stat FIFO Used 0x%02x "
1217 "Data FIFO Used 0x%04x Stat FIFO 0x%08x\n", 1153 "Data FIFO Used 0x%04x Stat FIFO 0x%08x\n",
1218 dev->name, 1154 dev->name,
1219 (SMC_GET_RX_FIFO_INF() & 0x00ff0000) >> 16, 1155 (SMC_GET_RX_FIFO_INF(lp) & 0x00ff0000) >> 16,
1220 SMC_GET_RX_FIFO_INF() & 0xffff, 1156 SMC_GET_RX_FIFO_INF(lp) & 0xffff,
1221 SMC_GET_RX_STS_FIFO_PEEK()); 1157 SMC_GET_RX_STS_FIFO_PEEK(lp));
1222 SMC_SET_GPT_CFG(GPT_CFG_TIMER_EN_ | 10000); 1158 SMC_SET_GPT_CFG(lp, GPT_CFG_TIMER_EN_ | 10000);
1223 SMC_ACK_INT(INT_STS_GPT_INT_); 1159 SMC_ACK_INT(lp, INT_STS_GPT_INT_);
1224 } 1160 }
1225#endif 1161#endif
1226 1162
@@ -1228,12 +1164,12 @@ static irqreturn_t smc911x_interrupt(int irq, void *dev_id)
1228 if (status & INT_STS_PHY_INT_) { 1164 if (status & INT_STS_PHY_INT_) {
1229 DBG(SMC_DEBUG_MISC, "%s: PHY irq\n", dev->name); 1165 DBG(SMC_DEBUG_MISC, "%s: PHY irq\n", dev->name);
1230 smc911x_phy_interrupt(dev); 1166 smc911x_phy_interrupt(dev);
1231 SMC_ACK_INT(INT_STS_PHY_INT_); 1167 SMC_ACK_INT(lp, INT_STS_PHY_INT_);
1232 } 1168 }
1233 } while (--timeout); 1169 } while (--timeout);
1234 1170
1235 /* restore mask state */ 1171 /* restore mask state */
1236 SMC_SET_INT_EN(mask); 1172 SMC_SET_INT_EN(lp, mask);
1237 1173
1238 DBG(SMC_DEBUG_MISC, "%s: Interrupt done (%d loops)\n", 1174 DBG(SMC_DEBUG_MISC, "%s: Interrupt done (%d loops)\n",
1239 dev->name, 8-timeout); 1175 dev->name, 8-timeout);
@@ -1335,22 +1271,21 @@ static void smc911x_poll_controller(struct net_device *dev)
1335static void smc911x_timeout(struct net_device *dev) 1271static void smc911x_timeout(struct net_device *dev)
1336{ 1272{
1337 struct smc911x_local *lp = netdev_priv(dev); 1273 struct smc911x_local *lp = netdev_priv(dev);
1338 unsigned long ioaddr = dev->base_addr;
1339 int status, mask; 1274 int status, mask;
1340 unsigned long flags; 1275 unsigned long flags;
1341 1276
1342 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__); 1277 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
1343 1278
1344 spin_lock_irqsave(&lp->lock, flags); 1279 spin_lock_irqsave(&lp->lock, flags);
1345 status = SMC_GET_INT(); 1280 status = SMC_GET_INT(lp);
1346 mask = SMC_GET_INT_EN(); 1281 mask = SMC_GET_INT_EN(lp);
1347 spin_unlock_irqrestore(&lp->lock, flags); 1282 spin_unlock_irqrestore(&lp->lock, flags);
1348 DBG(SMC_DEBUG_MISC, "%s: INT 0x%02x MASK 0x%02x \n", 1283 DBG(SMC_DEBUG_MISC, "%s: INT 0x%02x MASK 0x%02x \n",
1349 dev->name, status, mask); 1284 dev->name, status, mask);
1350 1285
1351 /* Dump the current TX FIFO contents and restart */ 1286 /* Dump the current TX FIFO contents and restart */
1352 mask = SMC_GET_TX_CFG(); 1287 mask = SMC_GET_TX_CFG(lp);
1353 SMC_SET_TX_CFG(mask | TX_CFG_TXS_DUMP_ | TX_CFG_TXD_DUMP_); 1288 SMC_SET_TX_CFG(lp, mask | TX_CFG_TXS_DUMP_ | TX_CFG_TXD_DUMP_);
1354 /* 1289 /*
1355 * Reconfiguring the PHY doesn't seem like a bad idea here, but 1290 * Reconfiguring the PHY doesn't seem like a bad idea here, but
1356 * smc911x_phy_configure() calls msleep() which calls schedule_timeout() 1291 * smc911x_phy_configure() calls msleep() which calls schedule_timeout()
@@ -1376,7 +1311,6 @@ static void smc911x_timeout(struct net_device *dev)
1376static void smc911x_set_multicast_list(struct net_device *dev) 1311static void smc911x_set_multicast_list(struct net_device *dev)
1377{ 1312{
1378 struct smc911x_local *lp = netdev_priv(dev); 1313 struct smc911x_local *lp = netdev_priv(dev);
1379 unsigned long ioaddr = dev->base_addr;
1380 unsigned int multicast_table[2]; 1314 unsigned int multicast_table[2];
1381 unsigned int mcr, update_multicast = 0; 1315 unsigned int mcr, update_multicast = 0;
1382 unsigned long flags; 1316 unsigned long flags;
@@ -1384,7 +1318,7 @@ static void smc911x_set_multicast_list(struct net_device *dev)
1384 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__); 1318 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
1385 1319
1386 spin_lock_irqsave(&lp->lock, flags); 1320 spin_lock_irqsave(&lp->lock, flags);
1387 SMC_GET_MAC_CR(mcr); 1321 SMC_GET_MAC_CR(lp, mcr);
1388 spin_unlock_irqrestore(&lp->lock, flags); 1322 spin_unlock_irqrestore(&lp->lock, flags);
1389 1323
1390 if (dev->flags & IFF_PROMISC) { 1324 if (dev->flags & IFF_PROMISC) {
@@ -1461,13 +1395,13 @@ static void smc911x_set_multicast_list(struct net_device *dev)
1461 } 1395 }
1462 1396
1463 spin_lock_irqsave(&lp->lock, flags); 1397 spin_lock_irqsave(&lp->lock, flags);
1464 SMC_SET_MAC_CR(mcr); 1398 SMC_SET_MAC_CR(lp, mcr);
1465 if (update_multicast) { 1399 if (update_multicast) {
1466 DBG(SMC_DEBUG_MISC, 1400 DBG(SMC_DEBUG_MISC,
1467 "%s: update mcast hash table 0x%08x 0x%08x\n", 1401 "%s: update mcast hash table 0x%08x 0x%08x\n",
1468 dev->name, multicast_table[0], multicast_table[1]); 1402 dev->name, multicast_table[0], multicast_table[1]);
1469 SMC_SET_HASHL(multicast_table[0]); 1403 SMC_SET_HASHL(lp, multicast_table[0]);
1470 SMC_SET_HASHH(multicast_table[1]); 1404 SMC_SET_HASHH(lp, multicast_table[1]);
1471 } 1405 }
1472 spin_unlock_irqrestore(&lp->lock, flags); 1406 spin_unlock_irqrestore(&lp->lock, flags);
1473} 1407}
@@ -1559,7 +1493,6 @@ static int
1559smc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) 1493smc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1560{ 1494{
1561 struct smc911x_local *lp = netdev_priv(dev); 1495 struct smc911x_local *lp = netdev_priv(dev);
1562 unsigned long ioaddr = dev->base_addr;
1563 int ret, status; 1496 int ret, status;
1564 unsigned long flags; 1497 unsigned long flags;
1565 1498
@@ -1587,7 +1520,7 @@ smc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1587 else 1520 else
1588 cmd->transceiver = XCVR_EXTERNAL; 1521 cmd->transceiver = XCVR_EXTERNAL;
1589 cmd->port = 0; 1522 cmd->port = 0;
1590 SMC_GET_PHY_SPECIAL(lp->mii.phy_id, status); 1523 SMC_GET_PHY_SPECIAL(lp, lp->mii.phy_id, status);
1591 cmd->duplex = 1524 cmd->duplex =
1592 (status & (PHY_SPECIAL_SPD_10FULL_ | PHY_SPECIAL_SPD_100FULL_)) ? 1525 (status & (PHY_SPECIAL_SPD_10FULL_ | PHY_SPECIAL_SPD_100FULL_)) ?
1593 DUPLEX_FULL : DUPLEX_HALF; 1526 DUPLEX_FULL : DUPLEX_HALF;
@@ -1668,7 +1601,6 @@ static int smc911x_ethtool_getregslen(struct net_device *dev)
1668static void smc911x_ethtool_getregs(struct net_device *dev, 1601static void smc911x_ethtool_getregs(struct net_device *dev,
1669 struct ethtool_regs* regs, void *buf) 1602 struct ethtool_regs* regs, void *buf)
1670{ 1603{
1671 unsigned long ioaddr = dev->base_addr;
1672 struct smc911x_local *lp = netdev_priv(dev); 1604 struct smc911x_local *lp = netdev_priv(dev);
1673 unsigned long flags; 1605 unsigned long flags;
1674 u32 reg,i,j=0; 1606 u32 reg,i,j=0;
@@ -1676,17 +1608,17 @@ static void smc911x_ethtool_getregs(struct net_device *dev,
1676 1608
1677 regs->version = lp->version; 1609 regs->version = lp->version;
1678 for(i=ID_REV;i<=E2P_CMD;i+=4) { 1610 for(i=ID_REV;i<=E2P_CMD;i+=4) {
1679 data[j++] = SMC_inl(ioaddr,i); 1611 data[j++] = SMC_inl(lp, i);
1680 } 1612 }
1681 for(i=MAC_CR;i<=WUCSR;i++) { 1613 for(i=MAC_CR;i<=WUCSR;i++) {
1682 spin_lock_irqsave(&lp->lock, flags); 1614 spin_lock_irqsave(&lp->lock, flags);
1683 SMC_GET_MAC_CSR(i, reg); 1615 SMC_GET_MAC_CSR(lp, i, reg);
1684 spin_unlock_irqrestore(&lp->lock, flags); 1616 spin_unlock_irqrestore(&lp->lock, flags);
1685 data[j++] = reg; 1617 data[j++] = reg;
1686 } 1618 }
1687 for(i=0;i<=31;i++) { 1619 for(i=0;i<=31;i++) {
1688 spin_lock_irqsave(&lp->lock, flags); 1620 spin_lock_irqsave(&lp->lock, flags);
1689 SMC_GET_MII(i, lp->mii.phy_id, reg); 1621 SMC_GET_MII(lp, i, lp->mii.phy_id, reg);
1690 spin_unlock_irqrestore(&lp->lock, flags); 1622 spin_unlock_irqrestore(&lp->lock, flags);
1691 data[j++] = reg & 0xFFFF; 1623 data[j++] = reg & 0xFFFF;
1692 } 1624 }
@@ -1694,11 +1626,11 @@ static void smc911x_ethtool_getregs(struct net_device *dev,
1694 1626
1695static int smc911x_ethtool_wait_eeprom_ready(struct net_device *dev) 1627static int smc911x_ethtool_wait_eeprom_ready(struct net_device *dev)
1696{ 1628{
1697 unsigned long ioaddr = dev->base_addr; 1629 struct smc911x_local *lp = netdev_priv(dev);
1698 unsigned int timeout; 1630 unsigned int timeout;
1699 int e2p_cmd; 1631 int e2p_cmd;
1700 1632
1701 e2p_cmd = SMC_GET_E2P_CMD(); 1633 e2p_cmd = SMC_GET_E2P_CMD(lp);
1702 for(timeout=10;(e2p_cmd & E2P_CMD_EPC_BUSY_) && timeout; timeout--) { 1634 for(timeout=10;(e2p_cmd & E2P_CMD_EPC_BUSY_) && timeout; timeout--) {
1703 if (e2p_cmd & E2P_CMD_EPC_TIMEOUT_) { 1635 if (e2p_cmd & E2P_CMD_EPC_TIMEOUT_) {
1704 PRINTK("%s: %s timeout waiting for EEPROM to respond\n", 1636 PRINTK("%s: %s timeout waiting for EEPROM to respond\n",
@@ -1706,7 +1638,7 @@ static int smc911x_ethtool_wait_eeprom_ready(struct net_device *dev)
1706 return -EFAULT; 1638 return -EFAULT;
1707 } 1639 }
1708 mdelay(1); 1640 mdelay(1);
1709 e2p_cmd = SMC_GET_E2P_CMD(); 1641 e2p_cmd = SMC_GET_E2P_CMD(lp);
1710 } 1642 }
1711 if (timeout == 0) { 1643 if (timeout == 0) {
1712 PRINTK("%s: %s timeout waiting for EEPROM CMD not busy\n", 1644 PRINTK("%s: %s timeout waiting for EEPROM CMD not busy\n",
@@ -1719,12 +1651,12 @@ static int smc911x_ethtool_wait_eeprom_ready(struct net_device *dev)
1719static inline int smc911x_ethtool_write_eeprom_cmd(struct net_device *dev, 1651static inline int smc911x_ethtool_write_eeprom_cmd(struct net_device *dev,
1720 int cmd, int addr) 1652 int cmd, int addr)
1721{ 1653{
1722 unsigned long ioaddr = dev->base_addr; 1654 struct smc911x_local *lp = netdev_priv(dev);
1723 int ret; 1655 int ret;
1724 1656
1725 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0) 1657 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
1726 return ret; 1658 return ret;
1727 SMC_SET_E2P_CMD(E2P_CMD_EPC_BUSY_ | 1659 SMC_SET_E2P_CMD(lp, E2P_CMD_EPC_BUSY_ |
1728 ((cmd) & (0x7<<28)) | 1660 ((cmd) & (0x7<<28)) |
1729 ((addr) & 0xFF)); 1661 ((addr) & 0xFF));
1730 return 0; 1662 return 0;
@@ -1733,24 +1665,24 @@ static inline int smc911x_ethtool_write_eeprom_cmd(struct net_device *dev,
1733static inline int smc911x_ethtool_read_eeprom_byte(struct net_device *dev, 1665static inline int smc911x_ethtool_read_eeprom_byte(struct net_device *dev,
1734 u8 *data) 1666 u8 *data)
1735{ 1667{
1736 unsigned long ioaddr = dev->base_addr; 1668 struct smc911x_local *lp = netdev_priv(dev);
1737 int ret; 1669 int ret;
1738 1670
1739 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0) 1671 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
1740 return ret; 1672 return ret;
1741 *data = SMC_GET_E2P_DATA(); 1673 *data = SMC_GET_E2P_DATA(lp);
1742 return 0; 1674 return 0;
1743} 1675}
1744 1676
1745static inline int smc911x_ethtool_write_eeprom_byte(struct net_device *dev, 1677static inline int smc911x_ethtool_write_eeprom_byte(struct net_device *dev,
1746 u8 data) 1678 u8 data)
1747{ 1679{
1748 unsigned long ioaddr = dev->base_addr; 1680 struct smc911x_local *lp = netdev_priv(dev);
1749 int ret; 1681 int ret;
1750 1682
1751 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0) 1683 if ((ret = smc911x_ethtool_wait_eeprom_ready(dev))!=0)
1752 return ret; 1684 return ret;
1753 SMC_SET_E2P_DATA(data); 1685 SMC_SET_E2P_DATA(lp, data);
1754 return 0; 1686 return 0;
1755} 1687}
1756 1688
@@ -1817,8 +1749,9 @@ static const struct ethtool_ops smc911x_ethtool_ops = {
1817 * This routine has a simple purpose -- make the SMC chip generate an 1749 * This routine has a simple purpose -- make the SMC chip generate an
1818 * interrupt, so an auto-detect routine can detect it, and find the IRQ, 1750 * interrupt, so an auto-detect routine can detect it, and find the IRQ,
1819 */ 1751 */
1820static int __init smc911x_findirq(unsigned long ioaddr) 1752static int __init smc911x_findirq(struct net_device *dev)
1821{ 1753{
1754 struct smc911x_local *lp = netdev_priv(dev);
1822 int timeout = 20; 1755 int timeout = 20;
1823 unsigned long cookie; 1756 unsigned long cookie;
1824 1757
@@ -1830,7 +1763,7 @@ static int __init smc911x_findirq(unsigned long ioaddr)
1830 * Force a SW interrupt 1763 * Force a SW interrupt
1831 */ 1764 */
1832 1765
1833 SMC_SET_INT_EN(INT_EN_SW_INT_EN_); 1766 SMC_SET_INT_EN(lp, INT_EN_SW_INT_EN_);
1834 1767
1835 /* 1768 /*
1836 * Wait until positive that the interrupt has been generated 1769 * Wait until positive that the interrupt has been generated
@@ -1838,7 +1771,7 @@ static int __init smc911x_findirq(unsigned long ioaddr)
1838 do { 1771 do {
1839 int int_status; 1772 int int_status;
1840 udelay(10); 1773 udelay(10);
1841 int_status = SMC_GET_INT_EN(); 1774 int_status = SMC_GET_INT_EN(lp);
1842 if (int_status & INT_EN_SW_INT_EN_) 1775 if (int_status & INT_EN_SW_INT_EN_)
1843 break; /* got the interrupt */ 1776 break; /* got the interrupt */
1844 } while (--timeout); 1777 } while (--timeout);
@@ -1851,7 +1784,7 @@ static int __init smc911x_findirq(unsigned long ioaddr)
1851 */ 1784 */
1852 1785
1853 /* and disable all interrupts again */ 1786 /* and disable all interrupts again */
1854 SMC_SET_INT_EN(0); 1787 SMC_SET_INT_EN(lp, 0);
1855 1788
1856 /* and return what I found */ 1789 /* and return what I found */
1857 return probe_irq_off(cookie); 1790 return probe_irq_off(cookie);
@@ -1880,7 +1813,7 @@ static int __init smc911x_findirq(unsigned long ioaddr)
1880 * o actually GRAB the irq. 1813 * o actually GRAB the irq.
1881 * o GRAB the region 1814 * o GRAB the region
1882 */ 1815 */
1883static int __init smc911x_probe(struct net_device *dev, unsigned long ioaddr) 1816static int __init smc911x_probe(struct net_device *dev)
1884{ 1817{
1885 struct smc911x_local *lp = netdev_priv(dev); 1818 struct smc911x_local *lp = netdev_priv(dev);
1886 int i, retval; 1819 int i, retval;
@@ -1890,7 +1823,7 @@ static int __init smc911x_probe(struct net_device *dev, unsigned long ioaddr)
1890 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__); 1823 DBG(SMC_DEBUG_FUNC, "%s: --> %s\n", dev->name, __FUNCTION__);
1891 1824
1892 /* First, see if the endian word is recognized */ 1825 /* First, see if the endian word is recognized */
1893 val = SMC_GET_BYTE_TEST(); 1826 val = SMC_GET_BYTE_TEST(lp);
1894 DBG(SMC_DEBUG_MISC, "%s: endian probe returned 0x%04x\n", CARDNAME, val); 1827 DBG(SMC_DEBUG_MISC, "%s: endian probe returned 0x%04x\n", CARDNAME, val);
1895 if (val != 0x87654321) { 1828 if (val != 0x87654321) {
1896 printk(KERN_ERR "Invalid chip endian 0x08%x\n",val); 1829 printk(KERN_ERR "Invalid chip endian 0x08%x\n",val);
@@ -1903,7 +1836,7 @@ static int __init smc911x_probe(struct net_device *dev, unsigned long ioaddr)
1903 * recognize. These might need to be added to later, 1836 * recognize. These might need to be added to later,
1904 * as future revisions could be added. 1837 * as future revisions could be added.
1905 */ 1838 */
1906 chip_id = SMC_GET_PN(); 1839 chip_id = SMC_GET_PN(lp);
1907 DBG(SMC_DEBUG_MISC, "%s: id probe returned 0x%04x\n", CARDNAME, chip_id); 1840 DBG(SMC_DEBUG_MISC, "%s: id probe returned 0x%04x\n", CARDNAME, chip_id);
1908 for(i=0;chip_ids[i].id != 0; i++) { 1841 for(i=0;chip_ids[i].id != 0; i++) {
1909 if (chip_ids[i].id == chip_id) break; 1842 if (chip_ids[i].id == chip_id) break;
@@ -1915,7 +1848,7 @@ static int __init smc911x_probe(struct net_device *dev, unsigned long ioaddr)
1915 } 1848 }
1916 version_string = chip_ids[i].name; 1849 version_string = chip_ids[i].name;
1917 1850
1918 revision = SMC_GET_REV(); 1851 revision = SMC_GET_REV(lp);
1919 DBG(SMC_DEBUG_MISC, "%s: revision = 0x%04x\n", CARDNAME, revision); 1852 DBG(SMC_DEBUG_MISC, "%s: revision = 0x%04x\n", CARDNAME, revision);
1920 1853
1921 /* At this point I'll assume that the chip is an SMC911x. */ 1854 /* At this point I'll assume that the chip is an SMC911x. */
@@ -1929,7 +1862,6 @@ static int __init smc911x_probe(struct net_device *dev, unsigned long ioaddr)
1929 } 1862 }
1930 1863
1931 /* fill in some of the fields */ 1864 /* fill in some of the fields */
1932 dev->base_addr = ioaddr;
1933 lp->version = chip_ids[i].id; 1865 lp->version = chip_ids[i].id;
1934 lp->revision = revision; 1866 lp->revision = revision;
1935 lp->tx_fifo_kb = tx_fifo_kb; 1867 lp->tx_fifo_kb = tx_fifo_kb;
@@ -1988,7 +1920,7 @@ static int __init smc911x_probe(struct net_device *dev, unsigned long ioaddr)
1988 spin_lock_init(&lp->lock); 1920 spin_lock_init(&lp->lock);
1989 1921
1990 /* Get the MAC address */ 1922 /* Get the MAC address */
1991 SMC_GET_MAC_ADDR(dev->dev_addr); 1923 SMC_GET_MAC_ADDR(lp, dev->dev_addr);
1992 1924
1993 /* now, reset the chip, and put it into a known state */ 1925 /* now, reset the chip, and put it into a known state */
1994 smc911x_reset(dev); 1926 smc911x_reset(dev);
@@ -2005,7 +1937,7 @@ static int __init smc911x_probe(struct net_device *dev, unsigned long ioaddr)
2005 1937
2006 trials = 3; 1938 trials = 3;
2007 while (trials--) { 1939 while (trials--) {
2008 dev->irq = smc911x_findirq(ioaddr); 1940 dev->irq = smc911x_findirq(dev);
2009 if (dev->irq) 1941 if (dev->irq)
2010 break; 1942 break;
2011 /* kick the card and try again */ 1943 /* kick the card and try again */
@@ -2166,7 +2098,9 @@ static int smc911x_drv_probe(struct platform_device *pdev)
2166 } 2098 }
2167 2099
2168 platform_set_drvdata(pdev, ndev); 2100 platform_set_drvdata(pdev, ndev);
2169 ret = smc911x_probe(ndev, (unsigned long)addr); 2101 lp->base = addr;
2102 ndev->base_addr = res->start;
2103 ret = smc911x_probe(ndev);
2170 if (ret != 0) { 2104 if (ret != 0) {
2171 platform_set_drvdata(pdev, NULL); 2105 platform_set_drvdata(pdev, NULL);
2172 iounmap(addr); 2106 iounmap(addr);
@@ -2190,6 +2124,7 @@ out:
2190static int smc911x_drv_remove(struct platform_device *pdev) 2124static int smc911x_drv_remove(struct platform_device *pdev)
2191{ 2125{
2192 struct net_device *ndev = platform_get_drvdata(pdev); 2126 struct net_device *ndev = platform_get_drvdata(pdev);
2127 struct smc911x_local *lp = netdev_priv(ndev);
2193 struct resource *res; 2128 struct resource *res;
2194 2129
2195 DBG(SMC_DEBUG_FUNC, "--> %s\n", __FUNCTION__); 2130 DBG(SMC_DEBUG_FUNC, "--> %s\n", __FUNCTION__);
@@ -2201,7 +2136,6 @@ static int smc911x_drv_remove(struct platform_device *pdev)
2201 2136
2202#ifdef SMC_USE_DMA 2137#ifdef SMC_USE_DMA
2203 { 2138 {
2204 struct smc911x_local *lp = netdev_priv(ndev);
2205 if (lp->rxdma != -1) { 2139 if (lp->rxdma != -1) {
2206 SMC_DMA_FREE(dev, lp->rxdma); 2140 SMC_DMA_FREE(dev, lp->rxdma);
2207 } 2141 }
@@ -2210,7 +2144,7 @@ static int smc911x_drv_remove(struct platform_device *pdev)
2210 } 2144 }
2211 } 2145 }
2212#endif 2146#endif
2213 iounmap((void *)ndev->base_addr); 2147 iounmap(lp->base);
2214 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2148 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2215 release_mem_region(res->start, SMC911X_IO_EXTENT); 2149 release_mem_region(res->start, SMC911X_IO_EXTENT);
2216 2150
@@ -2221,7 +2155,7 @@ static int smc911x_drv_remove(struct platform_device *pdev)
2221static int smc911x_drv_suspend(struct platform_device *dev, pm_message_t state) 2155static int smc911x_drv_suspend(struct platform_device *dev, pm_message_t state)
2222{ 2156{
2223 struct net_device *ndev = platform_get_drvdata(dev); 2157 struct net_device *ndev = platform_get_drvdata(dev);
2224 unsigned long ioaddr = ndev->base_addr; 2158 struct smc911x_local *lp = netdev_priv(ndev);
2225 2159
2226 DBG(SMC_DEBUG_FUNC, "--> %s\n", __FUNCTION__); 2160 DBG(SMC_DEBUG_FUNC, "--> %s\n", __FUNCTION__);
2227 if (ndev) { 2161 if (ndev) {
@@ -2230,7 +2164,7 @@ static int smc911x_drv_suspend(struct platform_device *dev, pm_message_t state)
2230 smc911x_shutdown(ndev); 2164 smc911x_shutdown(ndev);
2231#if POWER_DOWN 2165#if POWER_DOWN
2232 /* Set D2 - Energy detect only setting */ 2166 /* Set D2 - Energy detect only setting */
2233 SMC_SET_PMT_CTRL(2<<12); 2167 SMC_SET_PMT_CTRL(lp, 2<<12);
2234#endif 2168#endif
2235 } 2169 }
2236 } 2170 }
diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index 2b06e5087e36..271a3e8cf683 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -44,31 +44,78 @@
44 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW 44 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
45#endif 45#endif
46 46
47/* store this information for the driver.. */
48struct smc911x_local {
49 /*
50 * If I have to wait until the DMA is finished and ready to reload a
51 * packet, I will store the skbuff here. Then, the DMA will send it
52 * out and free it.
53 */
54 struct sk_buff *pending_tx_skb;
55
56 /* version/revision of the SMC911x chip */
57 u16 version;
58 u16 revision;
59
60 /* FIFO sizes */
61 int tx_fifo_kb;
62 int tx_fifo_size;
63 int rx_fifo_size;
64 int afc_cfg;
65
66 /* Contains the current active receive/phy mode */
67 int ctl_rfduplx;
68 int ctl_rspeed;
69
70 u32 msg_enable;
71 u32 phy_type;
72 struct mii_if_info mii;
73
74 /* work queue */
75 struct work_struct phy_configure;
76 int work_pending;
77
78 int tx_throttle;
79 spinlock_t lock;
80
81 struct net_device *netdev;
82
83#ifdef SMC_USE_DMA
84 /* DMA needs the physical address of the chip */
85 u_long physaddr;
86 int rxdma;
87 int txdma;
88 int rxdma_active;
89 int txdma_active;
90 struct sk_buff *current_rx_skb;
91 struct sk_buff *current_tx_skb;
92 struct device *dev;
93#endif
94 void __iomem *base;
95};
47 96
48/* 97/*
49 * Define the bus width specific IO macros 98 * Define the bus width specific IO macros
50 */ 99 */
51 100
52#if SMC_USE_16BIT 101#if SMC_USE_16BIT
53#define SMC_inl(a, r) (readw((a) + (r)) & 0xFFFF) + (readw((a) + (r) + 2) << 16)) 102#define SMC_inl(lp, r) ((readw((lp)->base + (r)) & 0xFFFF) + (readw((lp)->base + (r) + 2) << 16))
54#define SMC_outl(v, a, r) \ 103#define SMC_outl(v, lp, r) \
55 do{ \ 104 do{ \
56 writew(v & 0xFFFF, (a) + (r)); \ 105 writew(v & 0xFFFF, (lp)->base + (r)); \
57 writew(v >> 16, (a) + (r) + 2); \ 106 writew(v >> 16, (lp)->base + (r) + 2); \
58 } while (0) 107 } while (0)
59#define SMC_insl(a, r, p, l) readsw((short*)((a) + (r)), p, l*2) 108#define SMC_insl(lp, r, p, l) readsw((short*)((lp)->base + (r)), p, l*2)
60#define SMC_outsl(a, r, p, l) writesw((short*)((a) + (r)), p, l*2) 109#define SMC_outsl(lp, r, p, l) writesw((short*)((lp)->base + (r)), p, l*2)
61 110
62#elif SMC_USE_32BIT 111#elif SMC_USE_32BIT
63#define SMC_inl(a, r) readl((a) + (r)) 112#define SMC_inl(lp, r) readl((lp)->base + (r))
64#define SMC_outl(v, a, r) writel(v, (a) + (r)) 113#define SMC_outl(v, lp, r) writel(v, (lp)->base + (r))
65#define SMC_insl(a, r, p, l) readsl((int*)((a) + (r)), p, l) 114#define SMC_insl(lp, r, p, l) readsl((int*)((lp)->base + (r)), p, l)
66#define SMC_outsl(a, r, p, l) writesl((int*)((a) + (r)), p, l) 115#define SMC_outsl(lp, r, p, l) writesl((int*)((lp)->base + (r)), p, l)
67 116
68#endif /* SMC_USE_16BIT */ 117#endif /* SMC_USE_16BIT */
69 118
70
71
72#ifdef SMC_USE_PXA_DMA 119#ifdef SMC_USE_PXA_DMA
73#define SMC_USE_DMA 120#define SMC_USE_DMA
74 121
@@ -103,22 +150,22 @@ static int rx_dmalen, tx_dmalen;
103 150
104#ifdef SMC_insl 151#ifdef SMC_insl
105#undef SMC_insl 152#undef SMC_insl
106#define SMC_insl(a, r, p, l) \ 153#define SMC_insl(lp, r, p, l) \
107 smc_pxa_dma_insl(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l) 154 smc_pxa_dma_insl(lp, lp->physaddr, r, lp->rxdma, p, l)
108 155
109static inline void 156static inline void
110smc_pxa_dma_insl(struct device *dev, u_long ioaddr, u_long physaddr, 157smc_pxa_dma_insl(struct smc911x_local *lp, u_long physaddr,
111 int reg, int dma, u_char *buf, int len) 158 int reg, int dma, u_char *buf, int len)
112{ 159{
113 /* 64 bit alignment is required for memory to memory DMA */ 160 /* 64 bit alignment is required for memory to memory DMA */
114 if ((long)buf & 4) { 161 if ((long)buf & 4) {
115 *((u32 *)buf) = SMC_inl(ioaddr, reg); 162 *((u32 *)buf) = SMC_inl(lp, reg);
116 buf += 4; 163 buf += 4;
117 len--; 164 len--;
118 } 165 }
119 166
120 len *= 4; 167 len *= 4;
121 rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE); 168 rx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_FROM_DEVICE);
122 rx_dmalen = len; 169 rx_dmalen = len;
123 DCSR(dma) = DCSR_NODESC; 170 DCSR(dma) = DCSR_NODESC;
124 DTADR(dma) = rx_dmabuf; 171 DTADR(dma) = rx_dmabuf;
@@ -131,22 +178,22 @@ smc_pxa_dma_insl(struct device *dev, u_long ioaddr, u_long physaddr,
131 178
132#ifdef SMC_outsl 179#ifdef SMC_outsl
133#undef SMC_outsl 180#undef SMC_outsl
134#define SMC_outsl(a, r, p, l) \ 181#define SMC_outsl(lp, r, p, l) \
135 smc_pxa_dma_outsl(lp->dev, a, lp->physaddr, r, lp->txdma, p, l) 182 smc_pxa_dma_outsl(lp, lp->physaddr, r, lp->txdma, p, l)
136 183
137static inline void 184static inline void
138smc_pxa_dma_outsl(struct device *dev, u_long ioaddr, u_long physaddr, 185smc_pxa_dma_outsl(struct smc911x_local *lp, u_long physaddr,
139 int reg, int dma, u_char *buf, int len) 186 int reg, int dma, u_char *buf, int len)
140{ 187{
141 /* 64 bit alignment is required for memory to memory DMA */ 188 /* 64 bit alignment is required for memory to memory DMA */
142 if ((long)buf & 4) { 189 if ((long)buf & 4) {
143 SMC_outl(*((u32 *)buf), ioaddr, reg); 190 SMC_outl(*((u32 *)buf), lp, reg);
144 buf += 4; 191 buf += 4;
145 len--; 192 len--;
146 } 193 }
147 194
148 len *= 4; 195 len *= 4;
149 tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE); 196 tx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_TO_DEVICE);
150 tx_dmalen = len; 197 tx_dmalen = len;
151 DCSR(dma) = DCSR_NODESC; 198 DCSR(dma) = DCSR_NODESC;
152 DSADR(dma) = tx_dmabuf; 199 DSADR(dma) = tx_dmabuf;
@@ -565,213 +612,213 @@ static const struct chip_id chip_ids[] = {
565 * capabilities. Please use those and not the in/out primitives. 612 * capabilities. Please use those and not the in/out primitives.
566 */ 613 */
567/* FIFO read/write macros */ 614/* FIFO read/write macros */
568#define SMC_PUSH_DATA(p, l) SMC_outsl( ioaddr, TX_DATA_FIFO, p, (l) >> 2 ) 615#define SMC_PUSH_DATA(lp, p, l) SMC_outsl( lp, TX_DATA_FIFO, p, (l) >> 2 )
569#define SMC_PULL_DATA(p, l) SMC_insl ( ioaddr, RX_DATA_FIFO, p, (l) >> 2 ) 616#define SMC_PULL_DATA(lp, p, l) SMC_insl ( lp, RX_DATA_FIFO, p, (l) >> 2 )
570#define SMC_SET_TX_FIFO(x) SMC_outl( x, ioaddr, TX_DATA_FIFO ) 617#define SMC_SET_TX_FIFO(lp, x) SMC_outl( x, lp, TX_DATA_FIFO )
571#define SMC_GET_RX_FIFO() SMC_inl( ioaddr, RX_DATA_FIFO ) 618#define SMC_GET_RX_FIFO(lp) SMC_inl( lp, RX_DATA_FIFO )
572 619
573 620
574/* I/O mapped register read/write macros */ 621/* I/O mapped register read/write macros */
575#define SMC_GET_TX_STS_FIFO() SMC_inl( ioaddr, TX_STATUS_FIFO ) 622#define SMC_GET_TX_STS_FIFO(lp) SMC_inl( lp, TX_STATUS_FIFO )
576#define SMC_GET_RX_STS_FIFO() SMC_inl( ioaddr, RX_STATUS_FIFO ) 623#define SMC_GET_RX_STS_FIFO(lp) SMC_inl( lp, RX_STATUS_FIFO )
577#define SMC_GET_RX_STS_FIFO_PEEK() SMC_inl( ioaddr, RX_STATUS_FIFO_PEEK ) 624#define SMC_GET_RX_STS_FIFO_PEEK(lp) SMC_inl( lp, RX_STATUS_FIFO_PEEK )
578#define SMC_GET_PN() (SMC_inl( ioaddr, ID_REV ) >> 16) 625#define SMC_GET_PN(lp) (SMC_inl( lp, ID_REV ) >> 16)
579#define SMC_GET_REV() (SMC_inl( ioaddr, ID_REV ) & 0xFFFF) 626#define SMC_GET_REV(lp) (SMC_inl( lp, ID_REV ) & 0xFFFF)
580#define SMC_GET_IRQ_CFG() SMC_inl( ioaddr, INT_CFG ) 627#define SMC_GET_IRQ_CFG(lp) SMC_inl( lp, INT_CFG )
581#define SMC_SET_IRQ_CFG(x) SMC_outl( x, ioaddr, INT_CFG ) 628#define SMC_SET_IRQ_CFG(lp, x) SMC_outl( x, lp, INT_CFG )
582#define SMC_GET_INT() SMC_inl( ioaddr, INT_STS ) 629#define SMC_GET_INT(lp) SMC_inl( lp, INT_STS )
583#define SMC_ACK_INT(x) SMC_outl( x, ioaddr, INT_STS ) 630#define SMC_ACK_INT(lp, x) SMC_outl( x, lp, INT_STS )
584#define SMC_GET_INT_EN() SMC_inl( ioaddr, INT_EN ) 631#define SMC_GET_INT_EN(lp) SMC_inl( lp, INT_EN )
585#define SMC_SET_INT_EN(x) SMC_outl( x, ioaddr, INT_EN ) 632#define SMC_SET_INT_EN(lp, x) SMC_outl( x, lp, INT_EN )
586#define SMC_GET_BYTE_TEST() SMC_inl( ioaddr, BYTE_TEST ) 633#define SMC_GET_BYTE_TEST(lp) SMC_inl( lp, BYTE_TEST )
587#define SMC_SET_BYTE_TEST(x) SMC_outl( x, ioaddr, BYTE_TEST ) 634#define SMC_SET_BYTE_TEST(lp, x) SMC_outl( x, lp, BYTE_TEST )
588#define SMC_GET_FIFO_INT() SMC_inl( ioaddr, FIFO_INT ) 635#define SMC_GET_FIFO_INT(lp) SMC_inl( lp, FIFO_INT )
589#define SMC_SET_FIFO_INT(x) SMC_outl( x, ioaddr, FIFO_INT ) 636#define SMC_SET_FIFO_INT(lp, x) SMC_outl( x, lp, FIFO_INT )
590#define SMC_SET_FIFO_TDA(x) \ 637#define SMC_SET_FIFO_TDA(lp, x) \
591 do { \ 638 do { \
592 unsigned long __flags; \ 639 unsigned long __flags; \
593 int __mask; \ 640 int __mask; \
594 local_irq_save(__flags); \ 641 local_irq_save(__flags); \
595 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<24); \ 642 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<24); \
596 SMC_SET_FIFO_INT( __mask | (x)<<24 ); \ 643 SMC_SET_FIFO_INT( (lp), __mask | (x)<<24 ); \
597 local_irq_restore(__flags); \ 644 local_irq_restore(__flags); \
598 } while (0) 645 } while (0)
599#define SMC_SET_FIFO_TSL(x) \ 646#define SMC_SET_FIFO_TSL(lp, x) \
600 do { \ 647 do { \
601 unsigned long __flags; \ 648 unsigned long __flags; \
602 int __mask; \ 649 int __mask; \
603 local_irq_save(__flags); \ 650 local_irq_save(__flags); \
604 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<16); \ 651 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<16); \
605 SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<16)); \ 652 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<16)); \
606 local_irq_restore(__flags); \ 653 local_irq_restore(__flags); \
607 } while (0) 654 } while (0)
608#define SMC_SET_FIFO_RSA(x) \ 655#define SMC_SET_FIFO_RSA(lp, x) \
609 do { \ 656 do { \
610 unsigned long __flags; \ 657 unsigned long __flags; \
611 int __mask; \ 658 int __mask; \
612 local_irq_save(__flags); \ 659 local_irq_save(__flags); \
613 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<8); \ 660 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<8); \
614 SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<8)); \ 661 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<8)); \
615 local_irq_restore(__flags); \ 662 local_irq_restore(__flags); \
616 } while (0) 663 } while (0)
617#define SMC_SET_FIFO_RSL(x) \ 664#define SMC_SET_FIFO_RSL(lp, x) \
618 do { \ 665 do { \
619 unsigned long __flags; \ 666 unsigned long __flags; \
620 int __mask; \ 667 int __mask; \
621 local_irq_save(__flags); \ 668 local_irq_save(__flags); \
622 __mask = SMC_GET_FIFO_INT() & ~0xFF; \ 669 __mask = SMC_GET_FIFO_INT((lp)) & ~0xFF; \
623 SMC_SET_FIFO_INT( __mask | ((x) & 0xFF)); \ 670 SMC_SET_FIFO_INT( (lp),__mask | ((x) & 0xFF)); \
624 local_irq_restore(__flags); \ 671 local_irq_restore(__flags); \
625 } while (0) 672 } while (0)
626#define SMC_GET_RX_CFG() SMC_inl( ioaddr, RX_CFG ) 673#define SMC_GET_RX_CFG(lp) SMC_inl( lp, RX_CFG )
627#define SMC_SET_RX_CFG(x) SMC_outl( x, ioaddr, RX_CFG ) 674#define SMC_SET_RX_CFG(lp, x) SMC_outl( x, lp, RX_CFG )
628#define SMC_GET_TX_CFG() SMC_inl( ioaddr, TX_CFG ) 675#define SMC_GET_TX_CFG(lp) SMC_inl( lp, TX_CFG )
629#define SMC_SET_TX_CFG(x) SMC_outl( x, ioaddr, TX_CFG ) 676#define SMC_SET_TX_CFG(lp, x) SMC_outl( x, lp, TX_CFG )
630#define SMC_GET_HW_CFG() SMC_inl( ioaddr, HW_CFG ) 677#define SMC_GET_HW_CFG(lp) SMC_inl( lp, HW_CFG )
631#define SMC_SET_HW_CFG(x) SMC_outl( x, ioaddr, HW_CFG ) 678#define SMC_SET_HW_CFG(lp, x) SMC_outl( x, lp, HW_CFG )
632#define SMC_GET_RX_DP_CTRL() SMC_inl( ioaddr, RX_DP_CTRL ) 679#define SMC_GET_RX_DP_CTRL(lp) SMC_inl( lp, RX_DP_CTRL )
633#define SMC_SET_RX_DP_CTRL(x) SMC_outl( x, ioaddr, RX_DP_CTRL ) 680#define SMC_SET_RX_DP_CTRL(lp, x) SMC_outl( x, lp, RX_DP_CTRL )
634#define SMC_GET_PMT_CTRL() SMC_inl( ioaddr, PMT_CTRL ) 681#define SMC_GET_PMT_CTRL(lp) SMC_inl( lp, PMT_CTRL )
635#define SMC_SET_PMT_CTRL(x) SMC_outl( x, ioaddr, PMT_CTRL ) 682#define SMC_SET_PMT_CTRL(lp, x) SMC_outl( x, lp, PMT_CTRL )
636#define SMC_GET_GPIO_CFG() SMC_inl( ioaddr, GPIO_CFG ) 683#define SMC_GET_GPIO_CFG(lp) SMC_inl( lp, GPIO_CFG )
637#define SMC_SET_GPIO_CFG(x) SMC_outl( x, ioaddr, GPIO_CFG ) 684#define SMC_SET_GPIO_CFG(lp, x) SMC_outl( x, lp, GPIO_CFG )
638#define SMC_GET_RX_FIFO_INF() SMC_inl( ioaddr, RX_FIFO_INF ) 685#define SMC_GET_RX_FIFO_INF(lp) SMC_inl( lp, RX_FIFO_INF )
639#define SMC_SET_RX_FIFO_INF(x) SMC_outl( x, ioaddr, RX_FIFO_INF ) 686#define SMC_SET_RX_FIFO_INF(lp, x) SMC_outl( x, lp, RX_FIFO_INF )
640#define SMC_GET_TX_FIFO_INF() SMC_inl( ioaddr, TX_FIFO_INF ) 687#define SMC_GET_TX_FIFO_INF(lp) SMC_inl( lp, TX_FIFO_INF )
641#define SMC_SET_TX_FIFO_INF(x) SMC_outl( x, ioaddr, TX_FIFO_INF ) 688#define SMC_SET_TX_FIFO_INF(lp, x) SMC_outl( x, lp, TX_FIFO_INF )
642#define SMC_GET_GPT_CFG() SMC_inl( ioaddr, GPT_CFG ) 689#define SMC_GET_GPT_CFG(lp) SMC_inl( lp, GPT_CFG )
643#define SMC_SET_GPT_CFG(x) SMC_outl( x, ioaddr, GPT_CFG ) 690#define SMC_SET_GPT_CFG(lp, x) SMC_outl( x, lp, GPT_CFG )
644#define SMC_GET_RX_DROP() SMC_inl( ioaddr, RX_DROP ) 691#define SMC_GET_RX_DROP(lp) SMC_inl( lp, RX_DROP )
645#define SMC_SET_RX_DROP(x) SMC_outl( x, ioaddr, RX_DROP ) 692#define SMC_SET_RX_DROP(lp, x) SMC_outl( x, lp, RX_DROP )
646#define SMC_GET_MAC_CMD() SMC_inl( ioaddr, MAC_CSR_CMD ) 693#define SMC_GET_MAC_CMD(lp) SMC_inl( lp, MAC_CSR_CMD )
647#define SMC_SET_MAC_CMD(x) SMC_outl( x, ioaddr, MAC_CSR_CMD ) 694#define SMC_SET_MAC_CMD(lp, x) SMC_outl( x, lp, MAC_CSR_CMD )
648#define SMC_GET_MAC_DATA() SMC_inl( ioaddr, MAC_CSR_DATA ) 695#define SMC_GET_MAC_DATA(lp) SMC_inl( lp, MAC_CSR_DATA )
649#define SMC_SET_MAC_DATA(x) SMC_outl( x, ioaddr, MAC_CSR_DATA ) 696#define SMC_SET_MAC_DATA(lp, x) SMC_outl( x, lp, MAC_CSR_DATA )
650#define SMC_GET_AFC_CFG() SMC_inl( ioaddr, AFC_CFG ) 697#define SMC_GET_AFC_CFG(lp) SMC_inl( lp, AFC_CFG )
651#define SMC_SET_AFC_CFG(x) SMC_outl( x, ioaddr, AFC_CFG ) 698#define SMC_SET_AFC_CFG(lp, x) SMC_outl( x, lp, AFC_CFG )
652#define SMC_GET_E2P_CMD() SMC_inl( ioaddr, E2P_CMD ) 699#define SMC_GET_E2P_CMD(lp) SMC_inl( lp, E2P_CMD )
653#define SMC_SET_E2P_CMD(x) SMC_outl( x, ioaddr, E2P_CMD ) 700#define SMC_SET_E2P_CMD(lp, x) SMC_outl( x, lp, E2P_CMD )
654#define SMC_GET_E2P_DATA() SMC_inl( ioaddr, E2P_DATA ) 701#define SMC_GET_E2P_DATA(lp) SMC_inl( lp, E2P_DATA )
655#define SMC_SET_E2P_DATA(x) SMC_outl( x, ioaddr, E2P_DATA ) 702#define SMC_SET_E2P_DATA(lp, x) SMC_outl( x, lp, E2P_DATA )
656 703
657/* MAC register read/write macros */ 704/* MAC register read/write macros */
658#define SMC_GET_MAC_CSR(a,v) \ 705#define SMC_GET_MAC_CSR(lp,a,v) \
659 do { \ 706 do { \
660 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 707 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
661 SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | \ 708 SMC_SET_MAC_CMD((lp),MAC_CSR_CMD_CSR_BUSY_ | \
662 MAC_CSR_CMD_R_NOT_W_ | (a) ); \ 709 MAC_CSR_CMD_R_NOT_W_ | (a) ); \
663 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 710 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
664 v = SMC_GET_MAC_DATA(); \ 711 v = SMC_GET_MAC_DATA((lp)); \
665 } while (0) 712 } while (0)
666#define SMC_SET_MAC_CSR(a,v) \ 713#define SMC_SET_MAC_CSR(lp,a,v) \
667 do { \ 714 do { \
668 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 715 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
669 SMC_SET_MAC_DATA(v); \ 716 SMC_SET_MAC_DATA((lp), v); \
670 SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | (a) ); \ 717 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_CSR_BUSY_ | (a) ); \
671 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 718 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
672 } while (0) 719 } while (0)
673#define SMC_GET_MAC_CR(x) SMC_GET_MAC_CSR( MAC_CR, x ) 720#define SMC_GET_MAC_CR(lp, x) SMC_GET_MAC_CSR( (lp), MAC_CR, x )
674#define SMC_SET_MAC_CR(x) SMC_SET_MAC_CSR( MAC_CR, x ) 721#define SMC_SET_MAC_CR(lp, x) SMC_SET_MAC_CSR( (lp), MAC_CR, x )
675#define SMC_GET_ADDRH(x) SMC_GET_MAC_CSR( ADDRH, x ) 722#define SMC_GET_ADDRH(lp, x) SMC_GET_MAC_CSR( (lp), ADDRH, x )
676#define SMC_SET_ADDRH(x) SMC_SET_MAC_CSR( ADDRH, x ) 723#define SMC_SET_ADDRH(lp, x) SMC_SET_MAC_CSR( (lp), ADDRH, x )
677#define SMC_GET_ADDRL(x) SMC_GET_MAC_CSR( ADDRL, x ) 724#define SMC_GET_ADDRL(lp, x) SMC_GET_MAC_CSR( (lp), ADDRL, x )
678#define SMC_SET_ADDRL(x) SMC_SET_MAC_CSR( ADDRL, x ) 725#define SMC_SET_ADDRL(lp, x) SMC_SET_MAC_CSR( (lp), ADDRL, x )
679#define SMC_GET_HASHH(x) SMC_GET_MAC_CSR( HASHH, x ) 726#define SMC_GET_HASHH(lp, x) SMC_GET_MAC_CSR( (lp), HASHH, x )
680#define SMC_SET_HASHH(x) SMC_SET_MAC_CSR( HASHH, x ) 727#define SMC_SET_HASHH(lp, x) SMC_SET_MAC_CSR( (lp), HASHH, x )
681#define SMC_GET_HASHL(x) SMC_GET_MAC_CSR( HASHL, x ) 728#define SMC_GET_HASHL(lp, x) SMC_GET_MAC_CSR( (lp), HASHL, x )
682#define SMC_SET_HASHL(x) SMC_SET_MAC_CSR( HASHL, x ) 729#define SMC_SET_HASHL(lp, x) SMC_SET_MAC_CSR( (lp), HASHL, x )
683#define SMC_GET_MII_ACC(x) SMC_GET_MAC_CSR( MII_ACC, x ) 730#define SMC_GET_MII_ACC(lp, x) SMC_GET_MAC_CSR( (lp), MII_ACC, x )
684#define SMC_SET_MII_ACC(x) SMC_SET_MAC_CSR( MII_ACC, x ) 731#define SMC_SET_MII_ACC(lp, x) SMC_SET_MAC_CSR( (lp), MII_ACC, x )
685#define SMC_GET_MII_DATA(x) SMC_GET_MAC_CSR( MII_DATA, x ) 732#define SMC_GET_MII_DATA(lp, x) SMC_GET_MAC_CSR( (lp), MII_DATA, x )
686#define SMC_SET_MII_DATA(x) SMC_SET_MAC_CSR( MII_DATA, x ) 733#define SMC_SET_MII_DATA(lp, x) SMC_SET_MAC_CSR( (lp), MII_DATA, x )
687#define SMC_GET_FLOW(x) SMC_GET_MAC_CSR( FLOW, x ) 734#define SMC_GET_FLOW(lp, x) SMC_GET_MAC_CSR( (lp), FLOW, x )
688#define SMC_SET_FLOW(x) SMC_SET_MAC_CSR( FLOW, x ) 735#define SMC_SET_FLOW(lp, x) SMC_SET_MAC_CSR( (lp), FLOW, x )
689#define SMC_GET_VLAN1(x) SMC_GET_MAC_CSR( VLAN1, x ) 736#define SMC_GET_VLAN1(lp, x) SMC_GET_MAC_CSR( (lp), VLAN1, x )
690#define SMC_SET_VLAN1(x) SMC_SET_MAC_CSR( VLAN1, x ) 737#define SMC_SET_VLAN1(lp, x) SMC_SET_MAC_CSR( (lp), VLAN1, x )
691#define SMC_GET_VLAN2(x) SMC_GET_MAC_CSR( VLAN2, x ) 738#define SMC_GET_VLAN2(lp, x) SMC_GET_MAC_CSR( (lp), VLAN2, x )
692#define SMC_SET_VLAN2(x) SMC_SET_MAC_CSR( VLAN2, x ) 739#define SMC_SET_VLAN2(lp, x) SMC_SET_MAC_CSR( (lp), VLAN2, x )
693#define SMC_SET_WUFF(x) SMC_SET_MAC_CSR( WUFF, x ) 740#define SMC_SET_WUFF(lp, x) SMC_SET_MAC_CSR( (lp), WUFF, x )
694#define SMC_GET_WUCSR(x) SMC_GET_MAC_CSR( WUCSR, x ) 741#define SMC_GET_WUCSR(lp, x) SMC_GET_MAC_CSR( (lp), WUCSR, x )
695#define SMC_SET_WUCSR(x) SMC_SET_MAC_CSR( WUCSR, x ) 742#define SMC_SET_WUCSR(lp, x) SMC_SET_MAC_CSR( (lp), WUCSR, x )
696 743
697/* PHY register read/write macros */ 744/* PHY register read/write macros */
698#define SMC_GET_MII(a,phy,v) \ 745#define SMC_GET_MII(lp,a,phy,v) \
699 do { \ 746 do { \
700 u32 __v; \ 747 u32 __v; \
701 do { \ 748 do { \
702 SMC_GET_MII_ACC(__v); \ 749 SMC_GET_MII_ACC((lp), __v); \
703 } while ( __v & MII_ACC_MII_BUSY_ ); \ 750 } while ( __v & MII_ACC_MII_BUSY_ ); \
704 SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) | \ 751 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
705 MII_ACC_MII_BUSY_); \ 752 MII_ACC_MII_BUSY_); \
706 do { \ 753 do { \
707 SMC_GET_MII_ACC(__v); \ 754 SMC_GET_MII_ACC( (lp), __v); \
708 } while ( __v & MII_ACC_MII_BUSY_ ); \ 755 } while ( __v & MII_ACC_MII_BUSY_ ); \
709 SMC_GET_MII_DATA(v); \ 756 SMC_GET_MII_DATA((lp), v); \
710 } while (0) 757 } while (0)
711#define SMC_SET_MII(a,phy,v) \ 758#define SMC_SET_MII(lp,a,phy,v) \
712 do { \ 759 do { \
713 u32 __v; \ 760 u32 __v; \
714 do { \ 761 do { \
715 SMC_GET_MII_ACC(__v); \ 762 SMC_GET_MII_ACC((lp), __v); \
716 } while ( __v & MII_ACC_MII_BUSY_ ); \ 763 } while ( __v & MII_ACC_MII_BUSY_ ); \
717 SMC_SET_MII_DATA(v); \ 764 SMC_SET_MII_DATA((lp), v); \
718 SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) | \ 765 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
719 MII_ACC_MII_BUSY_ | \ 766 MII_ACC_MII_BUSY_ | \
720 MII_ACC_MII_WRITE_ ); \ 767 MII_ACC_MII_WRITE_ ); \
721 do { \ 768 do { \
722 SMC_GET_MII_ACC(__v); \ 769 SMC_GET_MII_ACC((lp), __v); \
723 } while ( __v & MII_ACC_MII_BUSY_ ); \ 770 } while ( __v & MII_ACC_MII_BUSY_ ); \
724 } while (0) 771 } while (0)
725#define SMC_GET_PHY_BMCR(phy,x) SMC_GET_MII( MII_BMCR, phy, x ) 772#define SMC_GET_PHY_BMCR(lp,phy,x) SMC_GET_MII( (lp), MII_BMCR, phy, x )
726#define SMC_SET_PHY_BMCR(phy,x) SMC_SET_MII( MII_BMCR, phy, x ) 773#define SMC_SET_PHY_BMCR(lp,phy,x) SMC_SET_MII( (lp), MII_BMCR, phy, x )
727#define SMC_GET_PHY_BMSR(phy,x) SMC_GET_MII( MII_BMSR, phy, x ) 774#define SMC_GET_PHY_BMSR(lp,phy,x) SMC_GET_MII( (lp), MII_BMSR, phy, x )
728#define SMC_GET_PHY_ID1(phy,x) SMC_GET_MII( MII_PHYSID1, phy, x ) 775#define SMC_GET_PHY_ID1(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID1, phy, x )
729#define SMC_GET_PHY_ID2(phy,x) SMC_GET_MII( MII_PHYSID2, phy, x ) 776#define SMC_GET_PHY_ID2(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID2, phy, x )
730#define SMC_GET_PHY_MII_ADV(phy,x) SMC_GET_MII( MII_ADVERTISE, phy, x ) 777#define SMC_GET_PHY_MII_ADV(lp,phy,x) SMC_GET_MII( (lp), MII_ADVERTISE, phy, x )
731#define SMC_SET_PHY_MII_ADV(phy,x) SMC_SET_MII( MII_ADVERTISE, phy, x ) 778#define SMC_SET_PHY_MII_ADV(lp,phy,x) SMC_SET_MII( (lp), MII_ADVERTISE, phy, x )
732#define SMC_GET_PHY_MII_LPA(phy,x) SMC_GET_MII( MII_LPA, phy, x ) 779#define SMC_GET_PHY_MII_LPA(lp,phy,x) SMC_GET_MII( (lp), MII_LPA, phy, x )
733#define SMC_SET_PHY_MII_LPA(phy,x) SMC_SET_MII( MII_LPA, phy, x ) 780#define SMC_SET_PHY_MII_LPA(lp,phy,x) SMC_SET_MII( (lp), MII_LPA, phy, x )
734#define SMC_GET_PHY_CTRL_STS(phy,x) SMC_GET_MII( PHY_MODE_CTRL_STS, phy, x ) 781#define SMC_GET_PHY_CTRL_STS(lp,phy,x) SMC_GET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
735#define SMC_SET_PHY_CTRL_STS(phy,x) SMC_SET_MII( PHY_MODE_CTRL_STS, phy, x ) 782#define SMC_SET_PHY_CTRL_STS(lp,phy,x) SMC_SET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
736#define SMC_GET_PHY_INT_SRC(phy,x) SMC_GET_MII( PHY_INT_SRC, phy, x ) 783#define SMC_GET_PHY_INT_SRC(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_SRC, phy, x )
737#define SMC_SET_PHY_INT_SRC(phy,x) SMC_SET_MII( PHY_INT_SRC, phy, x ) 784#define SMC_SET_PHY_INT_SRC(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_SRC, phy, x )
738#define SMC_GET_PHY_INT_MASK(phy,x) SMC_GET_MII( PHY_INT_MASK, phy, x ) 785#define SMC_GET_PHY_INT_MASK(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_MASK, phy, x )
739#define SMC_SET_PHY_INT_MASK(phy,x) SMC_SET_MII( PHY_INT_MASK, phy, x ) 786#define SMC_SET_PHY_INT_MASK(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_MASK, phy, x )
740#define SMC_GET_PHY_SPECIAL(phy,x) SMC_GET_MII( PHY_SPECIAL, phy, x ) 787#define SMC_GET_PHY_SPECIAL(lp,phy,x) SMC_GET_MII( (lp), PHY_SPECIAL, phy, x )
741 788
742 789
743 790
744/* Misc read/write macros */ 791/* Misc read/write macros */
745 792
746#ifndef SMC_GET_MAC_ADDR 793#ifndef SMC_GET_MAC_ADDR
747#define SMC_GET_MAC_ADDR(addr) \ 794#define SMC_GET_MAC_ADDR(lp, addr) \
748 do { \ 795 do { \
749 unsigned int __v; \ 796 unsigned int __v; \
750 \ 797 \
751 SMC_GET_MAC_CSR(ADDRL, __v); \ 798 SMC_GET_MAC_CSR((lp), ADDRL, __v); \
752 addr[0] = __v; addr[1] = __v >> 8; \ 799 addr[0] = __v; addr[1] = __v >> 8; \
753 addr[2] = __v >> 16; addr[3] = __v >> 24; \ 800 addr[2] = __v >> 16; addr[3] = __v >> 24; \
754 SMC_GET_MAC_CSR(ADDRH, __v); \ 801 SMC_GET_MAC_CSR((lp), ADDRH, __v); \
755 addr[4] = __v; addr[5] = __v >> 8; \ 802 addr[4] = __v; addr[5] = __v >> 8; \
756 } while (0) 803 } while (0)
757#endif 804#endif
758 805
759#define SMC_SET_MAC_ADDR(addr) \ 806#define SMC_SET_MAC_ADDR(lp, addr) \
760 do { \ 807 do { \
761 SMC_SET_MAC_CSR(ADDRL, \ 808 SMC_SET_MAC_CSR((lp), ADDRL, \
762 addr[0] | \ 809 addr[0] | \
763 (addr[1] << 8) | \ 810 (addr[1] << 8) | \
764 (addr[2] << 16) | \ 811 (addr[2] << 16) | \
765 (addr[3] << 24)); \ 812 (addr[3] << 24)); \
766 SMC_SET_MAC_CSR(ADDRH, addr[4]|(addr[5] << 8));\ 813 SMC_SET_MAC_CSR((lp), ADDRH, addr[4]|(addr[5] << 8));\
767 } while (0) 814 } while (0)
768 815
769 816
770#define SMC_WRITE_EEPROM_CMD(cmd, addr) \ 817#define SMC_WRITE_EEPROM_CMD(lp, cmd, addr) \
771 do { \ 818 do { \
772 while (SMC_GET_E2P_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 819 while (SMC_GET_E2P_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
773 SMC_SET_MAC_CMD(MAC_CSR_CMD_R_NOT_W_ | a ); \ 820 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_R_NOT_W_ | a ); \
774 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 821 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
775 } while (0) 822 } while (0)
776 823
777#endif /* _SMC911X_H_ */ 824#endif /* _SMC911X_H_ */
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