diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ata/sata_nv.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/drivers/ata/sata_nv.c b/drivers/ata/sata_nv.c index 745d85686f5e..b564ff84a390 100644 --- a/drivers/ata/sata_nv.c +++ b/drivers/ata/sata_nv.c | |||
| @@ -1034,14 +1034,15 @@ static int nv_adma_port_start(struct ata_port *ap) | |||
| 1034 | 1034 | ||
| 1035 | /* clear GO for register mode, enable interrupt */ | 1035 | /* clear GO for register mode, enable interrupt */ |
| 1036 | tmp = readw(mmio + NV_ADMA_CTL); | 1036 | tmp = readw(mmio + NV_ADMA_CTL); |
| 1037 | writew( (tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN, mmio + NV_ADMA_CTL); | 1037 | writew( (tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN | |
| 1038 | NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL); | ||
| 1038 | 1039 | ||
| 1039 | tmp = readw(mmio + NV_ADMA_CTL); | 1040 | tmp = readw(mmio + NV_ADMA_CTL); |
| 1040 | writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); | 1041 | writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); |
| 1041 | readl( mmio + NV_ADMA_CTL ); /* flush posted write */ | 1042 | readw( mmio + NV_ADMA_CTL ); /* flush posted write */ |
| 1042 | udelay(1); | 1043 | udelay(1); |
| 1043 | writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); | 1044 | writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); |
| 1044 | readl( mmio + NV_ADMA_CTL ); /* flush posted write */ | 1045 | readw( mmio + NV_ADMA_CTL ); /* flush posted write */ |
| 1045 | 1046 | ||
| 1046 | return 0; | 1047 | return 0; |
| 1047 | } | 1048 | } |
| @@ -1093,14 +1094,15 @@ static int nv_adma_port_resume(struct ata_port *ap) | |||
| 1093 | 1094 | ||
| 1094 | /* clear GO for register mode, enable interrupt */ | 1095 | /* clear GO for register mode, enable interrupt */ |
| 1095 | tmp = readw(mmio + NV_ADMA_CTL); | 1096 | tmp = readw(mmio + NV_ADMA_CTL); |
| 1096 | writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN, mmio + NV_ADMA_CTL); | 1097 | writew( (tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN | |
| 1098 | NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL); | ||
| 1097 | 1099 | ||
| 1098 | tmp = readw(mmio + NV_ADMA_CTL); | 1100 | tmp = readw(mmio + NV_ADMA_CTL); |
| 1099 | writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); | 1101 | writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); |
| 1100 | readl( mmio + NV_ADMA_CTL ); /* flush posted write */ | 1102 | readw( mmio + NV_ADMA_CTL ); /* flush posted write */ |
| 1101 | udelay(1); | 1103 | udelay(1); |
| 1102 | writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); | 1104 | writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); |
| 1103 | readl( mmio + NV_ADMA_CTL ); /* flush posted write */ | 1105 | readw( mmio + NV_ADMA_CTL ); /* flush posted write */ |
| 1104 | 1106 | ||
| 1105 | return 0; | 1107 | return 0; |
| 1106 | } | 1108 | } |
| @@ -1491,10 +1493,10 @@ static void nv_adma_error_handler(struct ata_port *ap) | |||
| 1491 | /* Reset channel */ | 1493 | /* Reset channel */ |
| 1492 | tmp = readw(mmio + NV_ADMA_CTL); | 1494 | tmp = readw(mmio + NV_ADMA_CTL); |
| 1493 | writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); | 1495 | writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); |
| 1494 | readl( mmio + NV_ADMA_CTL ); /* flush posted write */ | 1496 | readw( mmio + NV_ADMA_CTL ); /* flush posted write */ |
| 1495 | udelay(1); | 1497 | udelay(1); |
| 1496 | writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); | 1498 | writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); |
| 1497 | readl( mmio + NV_ADMA_CTL ); /* flush posted write */ | 1499 | readw( mmio + NV_ADMA_CTL ); /* flush posted write */ |
| 1498 | } | 1500 | } |
| 1499 | 1501 | ||
| 1500 | ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, | 1502 | ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, |