diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/s2io-regs.h | 1 | ||||
-rw-r--r-- | drivers/net/s2io.c | 391 | ||||
-rw-r--r-- | drivers/net/s2io.h | 21 |
3 files changed, 253 insertions, 160 deletions
diff --git a/drivers/net/s2io-regs.h b/drivers/net/s2io-regs.h index a914fef44309..518e96d75371 100644 --- a/drivers/net/s2io-regs.h +++ b/drivers/net/s2io-regs.h | |||
@@ -300,6 +300,7 @@ typedef struct _XENA_dev_config { | |||
300 | u64 gpio_control; | 300 | u64 gpio_control; |
301 | #define GPIO_CTRL_GPIO_0 BIT(8) | 301 | #define GPIO_CTRL_GPIO_0 BIT(8) |
302 | u64 misc_control; | 302 | u64 misc_control; |
303 | #define FAULT_BEHAVIOUR BIT(0) | ||
303 | #define EXT_REQ_EN BIT(1) | 304 | #define EXT_REQ_EN BIT(1) |
304 | #define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3) | 305 | #define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3) |
305 | 306 | ||
diff --git a/drivers/net/s2io.c b/drivers/net/s2io.c index 063040bc62d7..350723bd5eb8 100644 --- a/drivers/net/s2io.c +++ b/drivers/net/s2io.c | |||
@@ -1415,7 +1415,7 @@ static int init_nic(struct s2io_nic *nic) | |||
1415 | 1415 | ||
1416 | val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) | | 1416 | val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) | |
1417 | TTI_DATA2_MEM_TX_UFC_B(0x20) | | 1417 | TTI_DATA2_MEM_TX_UFC_B(0x20) | |
1418 | TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80); | 1418 | TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80); |
1419 | writeq(val64, &bar0->tti_data2_mem); | 1419 | writeq(val64, &bar0->tti_data2_mem); |
1420 | 1420 | ||
1421 | val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD; | 1421 | val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD; |
@@ -1611,7 +1611,8 @@ static int init_nic(struct s2io_nic *nic) | |||
1611 | * that does not start on an ADB to reduce disconnects. | 1611 | * that does not start on an ADB to reduce disconnects. |
1612 | */ | 1612 | */ |
1613 | if (nic->device_type == XFRAME_II_DEVICE) { | 1613 | if (nic->device_type == XFRAME_II_DEVICE) { |
1614 | val64 = EXT_REQ_EN | MISC_LINK_STABILITY_PRD(3); | 1614 | val64 = FAULT_BEHAVIOUR | EXT_REQ_EN | |
1615 | MISC_LINK_STABILITY_PRD(3); | ||
1615 | writeq(val64, &bar0->misc_control); | 1616 | writeq(val64, &bar0->misc_control); |
1616 | val64 = readq(&bar0->pic_control2); | 1617 | val64 = readq(&bar0->pic_control2); |
1617 | val64 &= ~(BIT(13)|BIT(14)|BIT(15)); | 1618 | val64 &= ~(BIT(13)|BIT(14)|BIT(15)); |
@@ -1878,41 +1879,36 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag) | |||
1878 | } | 1879 | } |
1879 | } | 1880 | } |
1880 | 1881 | ||
1881 | static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc) | 1882 | /** |
1883 | * verify_pcc_quiescent- Checks for PCC quiescent state | ||
1884 | * Return: 1 If PCC is quiescence | ||
1885 | * 0 If PCC is not quiescence | ||
1886 | */ | ||
1887 | static int verify_pcc_quiescent(nic_t *sp, int flag) | ||
1882 | { | 1888 | { |
1883 | int ret = 0; | 1889 | int ret = 0, herc; |
1890 | XENA_dev_config_t __iomem *bar0 = sp->bar0; | ||
1891 | u64 val64 = readq(&bar0->adapter_status); | ||
1892 | |||
1893 | herc = (sp->device_type == XFRAME_II_DEVICE); | ||
1884 | 1894 | ||
1885 | if (flag == FALSE) { | 1895 | if (flag == FALSE) { |
1886 | if ((!herc && (rev_id >= 4)) || herc) { | 1896 | if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) { |
1887 | if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) && | 1897 | if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE)) |
1888 | ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == | ||
1889 | ADAPTER_STATUS_RC_PRC_QUIESCENT)) { | ||
1890 | ret = 1; | 1898 | ret = 1; |
1891 | } | 1899 | } else { |
1892 | }else { | 1900 | if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE)) |
1893 | if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) && | ||
1894 | ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == | ||
1895 | ADAPTER_STATUS_RC_PRC_QUIESCENT)) { | ||
1896 | ret = 1; | 1901 | ret = 1; |
1897 | } | ||
1898 | } | 1902 | } |
1899 | } else { | 1903 | } else { |
1900 | if ((!herc && (rev_id >= 4)) || herc) { | 1904 | if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) { |
1901 | if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) == | 1905 | if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) == |
1902 | ADAPTER_STATUS_RMAC_PCC_IDLE) && | 1906 | ADAPTER_STATUS_RMAC_PCC_IDLE)) |
1903 | (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) || | ||
1904 | ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == | ||
1905 | ADAPTER_STATUS_RC_PRC_QUIESCENT))) { | ||
1906 | ret = 1; | 1907 | ret = 1; |
1907 | } | ||
1908 | } else { | 1908 | } else { |
1909 | if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) == | 1909 | if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) == |
1910 | ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) && | 1910 | ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE)) |
1911 | (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) || | ||
1912 | ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == | ||
1913 | ADAPTER_STATUS_RC_PRC_QUIESCENT))) { | ||
1914 | ret = 1; | 1911 | ret = 1; |
1915 | } | ||
1916 | } | 1912 | } |
1917 | } | 1913 | } |
1918 | 1914 | ||
@@ -1920,9 +1916,6 @@ static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc) | |||
1920 | } | 1916 | } |
1921 | /** | 1917 | /** |
1922 | * verify_xena_quiescence - Checks whether the H/W is ready | 1918 | * verify_xena_quiescence - Checks whether the H/W is ready |
1923 | * @val64 : Value read from adapter status register. | ||
1924 | * @flag : indicates if the adapter enable bit was ever written once | ||
1925 | * before. | ||
1926 | * Description: Returns whether the H/W is ready to go or not. Depending | 1919 | * Description: Returns whether the H/W is ready to go or not. Depending |
1927 | * on whether adapter enable bit was written or not the comparison | 1920 | * on whether adapter enable bit was written or not the comparison |
1928 | * differs and the calling function passes the input argument flag to | 1921 | * differs and the calling function passes the input argument flag to |
@@ -1931,24 +1924,63 @@ static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc) | |||
1931 | * 0 If Xena is not quiescence | 1924 | * 0 If Xena is not quiescence |
1932 | */ | 1925 | */ |
1933 | 1926 | ||
1934 | static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag) | 1927 | static int verify_xena_quiescence(nic_t *sp) |
1935 | { | 1928 | { |
1936 | int ret = 0, herc; | 1929 | int mode; |
1937 | u64 tmp64 = ~((u64) val64); | 1930 | XENA_dev_config_t __iomem *bar0 = sp->bar0; |
1938 | int rev_id = get_xena_rev_id(sp->pdev); | 1931 | u64 val64 = readq(&bar0->adapter_status); |
1932 | mode = s2io_verify_pci_mode(sp); | ||
1939 | 1933 | ||
1940 | herc = (sp->device_type == XFRAME_II_DEVICE); | 1934 | if (!(val64 & ADAPTER_STATUS_TDMA_READY)) { |
1941 | if (! | 1935 | DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!"); |
1942 | (tmp64 & | 1936 | return 0; |
1943 | (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY | | 1937 | } |
1944 | ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY | | 1938 | if (!(val64 & ADAPTER_STATUS_RDMA_READY)) { |
1945 | ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY | | 1939 | DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!"); |
1946 | ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK | | 1940 | return 0; |
1947 | ADAPTER_STATUS_P_PLL_LOCK))) { | 1941 | } |
1948 | ret = check_prc_pcc_state(val64, flag, rev_id, herc); | 1942 | if (!(val64 & ADAPTER_STATUS_PFC_READY)) { |
1943 | DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!"); | ||
1944 | return 0; | ||
1945 | } | ||
1946 | if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) { | ||
1947 | DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!"); | ||
1948 | return 0; | ||
1949 | } | ||
1950 | if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) { | ||
1951 | DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!"); | ||
1952 | return 0; | ||
1953 | } | ||
1954 | if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) { | ||
1955 | DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!"); | ||
1956 | return 0; | ||
1957 | } | ||
1958 | if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) { | ||
1959 | DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!"); | ||
1960 | return 0; | ||
1961 | } | ||
1962 | if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) { | ||
1963 | DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!"); | ||
1964 | return 0; | ||
1949 | } | 1965 | } |
1950 | 1966 | ||
1951 | return ret; | 1967 | /* |
1968 | * In PCI 33 mode, the P_PLL is not used, and therefore, | ||
1969 | * the the P_PLL_LOCK bit in the adapter_status register will | ||
1970 | * not be asserted. | ||
1971 | */ | ||
1972 | if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) && | ||
1973 | sp->device_type == XFRAME_II_DEVICE && mode != | ||
1974 | PCI_MODE_PCI_33) { | ||
1975 | DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!"); | ||
1976 | return 0; | ||
1977 | } | ||
1978 | if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == | ||
1979 | ADAPTER_STATUS_RC_PRC_QUIESCENT)) { | ||
1980 | DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!"); | ||
1981 | return 0; | ||
1982 | } | ||
1983 | return 1; | ||
1952 | } | 1984 | } |
1953 | 1985 | ||
1954 | /** | 1986 | /** |
@@ -2053,7 +2085,7 @@ static int start_nic(struct s2io_nic *nic) | |||
2053 | * it. | 2085 | * it. |
2054 | */ | 2086 | */ |
2055 | val64 = readq(&bar0->adapter_status); | 2087 | val64 = readq(&bar0->adapter_status); |
2056 | if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) { | 2088 | if (!verify_xena_quiescence(nic)) { |
2057 | DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name); | 2089 | DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name); |
2058 | DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n", | 2090 | DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n", |
2059 | (unsigned long long) val64); | 2091 | (unsigned long long) val64); |
@@ -2577,7 +2609,6 @@ static int s2io_poll(struct net_device *dev, int *budget) | |||
2577 | mac_info_t *mac_control; | 2609 | mac_info_t *mac_control; |
2578 | struct config_param *config; | 2610 | struct config_param *config; |
2579 | XENA_dev_config_t __iomem *bar0 = nic->bar0; | 2611 | XENA_dev_config_t __iomem *bar0 = nic->bar0; |
2580 | u64 val64 = 0xFFFFFFFFFFFFFFFFULL; | ||
2581 | int i; | 2612 | int i; |
2582 | 2613 | ||
2583 | atomic_inc(&nic->isr_cnt); | 2614 | atomic_inc(&nic->isr_cnt); |
@@ -2589,8 +2620,8 @@ static int s2io_poll(struct net_device *dev, int *budget) | |||
2589 | nic->pkts_to_process = dev->quota; | 2620 | nic->pkts_to_process = dev->quota; |
2590 | org_pkts_to_process = nic->pkts_to_process; | 2621 | org_pkts_to_process = nic->pkts_to_process; |
2591 | 2622 | ||
2592 | writeq(val64, &bar0->rx_traffic_int); | 2623 | writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int); |
2593 | val64 = readl(&bar0->rx_traffic_int); | 2624 | readl(&bar0->rx_traffic_int); |
2594 | 2625 | ||
2595 | for (i = 0; i < config->rx_ring_num; i++) { | 2626 | for (i = 0; i < config->rx_ring_num; i++) { |
2596 | rx_intr_handler(&mac_control->rings[i]); | 2627 | rx_intr_handler(&mac_control->rings[i]); |
@@ -2616,7 +2647,7 @@ static int s2io_poll(struct net_device *dev, int *budget) | |||
2616 | } | 2647 | } |
2617 | /* Re enable the Rx interrupts. */ | 2648 | /* Re enable the Rx interrupts. */ |
2618 | writeq(0x0, &bar0->rx_traffic_mask); | 2649 | writeq(0x0, &bar0->rx_traffic_mask); |
2619 | val64 = readl(&bar0->rx_traffic_mask); | 2650 | readl(&bar0->rx_traffic_mask); |
2620 | atomic_dec(&nic->isr_cnt); | 2651 | atomic_dec(&nic->isr_cnt); |
2621 | return 0; | 2652 | return 0; |
2622 | 2653 | ||
@@ -2851,11 +2882,10 @@ static void tx_intr_handler(fifo_info_t *fifo_data) | |||
2851 | } | 2882 | } |
2852 | if ((err >> 48) == 0xA) { | 2883 | if ((err >> 48) == 0xA) { |
2853 | DBG_PRINT(TX_DBG, "TxD returned due \ | 2884 | DBG_PRINT(TX_DBG, "TxD returned due \ |
2854 | to loss of link\n"); | 2885 | to loss of link\n"); |
2855 | } | 2886 | } |
2856 | else { | 2887 | else { |
2857 | DBG_PRINT(ERR_DBG, "***TxD error \ | 2888 | DBG_PRINT(ERR_DBG, "***TxD error %llx\n", err); |
2858 | %llx\n", err); | ||
2859 | } | 2889 | } |
2860 | } | 2890 | } |
2861 | 2891 | ||
@@ -3294,6 +3324,25 @@ static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit) | |||
3294 | } | 3324 | } |
3295 | return ret; | 3325 | return ret; |
3296 | } | 3326 | } |
3327 | /* | ||
3328 | * check_pci_device_id - Checks if the device id is supported | ||
3329 | * @id : device id | ||
3330 | * Description: Function to check if the pci device id is supported by driver. | ||
3331 | * Return value: Actual device id if supported else PCI_ANY_ID | ||
3332 | */ | ||
3333 | static u16 check_pci_device_id(u16 id) | ||
3334 | { | ||
3335 | switch (id) { | ||
3336 | case PCI_DEVICE_ID_HERC_WIN: | ||
3337 | case PCI_DEVICE_ID_HERC_UNI: | ||
3338 | return XFRAME_II_DEVICE; | ||
3339 | case PCI_DEVICE_ID_S2IO_UNI: | ||
3340 | case PCI_DEVICE_ID_S2IO_WIN: | ||
3341 | return XFRAME_I_DEVICE; | ||
3342 | default: | ||
3343 | return PCI_ANY_ID; | ||
3344 | } | ||
3345 | } | ||
3297 | 3346 | ||
3298 | /** | 3347 | /** |
3299 | * s2io_reset - Resets the card. | 3348 | * s2io_reset - Resets the card. |
@@ -3310,37 +3359,52 @@ static void s2io_reset(nic_t * sp) | |||
3310 | XENA_dev_config_t __iomem *bar0 = sp->bar0; | 3359 | XENA_dev_config_t __iomem *bar0 = sp->bar0; |
3311 | u64 val64; | 3360 | u64 val64; |
3312 | u16 subid, pci_cmd; | 3361 | u16 subid, pci_cmd; |
3362 | int i; | ||
3363 | u16 val16; | ||
3364 | DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n", | ||
3365 | __FUNCTION__, sp->dev->name); | ||
3313 | 3366 | ||
3314 | /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */ | 3367 | /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */ |
3315 | pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd)); | 3368 | pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd)); |
3316 | 3369 | ||
3370 | if (sp->device_type == XFRAME_II_DEVICE) { | ||
3371 | int ret; | ||
3372 | ret = pci_set_power_state(sp->pdev, 3); | ||
3373 | if (!ret) | ||
3374 | ret = pci_set_power_state(sp->pdev, 0); | ||
3375 | else { | ||
3376 | DBG_PRINT(ERR_DBG,"%s PME based SW_Reset failed!\n", | ||
3377 | __FUNCTION__); | ||
3378 | goto old_way; | ||
3379 | } | ||
3380 | msleep(20); | ||
3381 | goto new_way; | ||
3382 | } | ||
3383 | old_way: | ||
3317 | val64 = SW_RESET_ALL; | 3384 | val64 = SW_RESET_ALL; |
3318 | writeq(val64, &bar0->sw_reset); | 3385 | writeq(val64, &bar0->sw_reset); |
3319 | 3386 | new_way: | |
3320 | /* | ||
3321 | * At this stage, if the PCI write is indeed completed, the | ||
3322 | * card is reset and so is the PCI Config space of the device. | ||
3323 | * So a read cannot be issued at this stage on any of the | ||
3324 | * registers to ensure the write into "sw_reset" register | ||
3325 | * has gone through. | ||
3326 | * Question: Is there any system call that will explicitly force | ||
3327 | * all the write commands still pending on the bus to be pushed | ||
3328 | * through? | ||
3329 | * As of now I'am just giving a 250ms delay and hoping that the | ||
3330 | * PCI write to sw_reset register is done by this time. | ||
3331 | */ | ||
3332 | msleep(250); | ||
3333 | if (strstr(sp->product_name, "CX4")) { | 3387 | if (strstr(sp->product_name, "CX4")) { |
3334 | msleep(750); | 3388 | msleep(750); |
3335 | } | 3389 | } |
3390 | msleep(250); | ||
3391 | for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) { | ||
3336 | 3392 | ||
3337 | /* Restore the PCI state saved during initialization. */ | 3393 | /* Restore the PCI state saved during initialization. */ |
3338 | pci_restore_state(sp->pdev); | 3394 | pci_restore_state(sp->pdev); |
3339 | pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, | 3395 | pci_read_config_word(sp->pdev, 0x2, &val16); |
3340 | pci_cmd); | 3396 | if (check_pci_device_id(val16) != (u16)PCI_ANY_ID) |
3341 | s2io_init_pci(sp); | 3397 | break; |
3398 | msleep(200); | ||
3399 | } | ||
3342 | 3400 | ||
3343 | msleep(250); | 3401 | if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) { |
3402 | DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__); | ||
3403 | } | ||
3404 | |||
3405 | pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd); | ||
3406 | |||
3407 | s2io_init_pci(sp); | ||
3344 | 3408 | ||
3345 | /* Set swapper to enable I/O register access */ | 3409 | /* Set swapper to enable I/O register access */ |
3346 | s2io_set_swapper(sp); | 3410 | s2io_set_swapper(sp); |
@@ -4104,39 +4168,33 @@ static void s2io_txpic_intr_handle(nic_t *sp) | |||
4104 | } | 4168 | } |
4105 | else if (val64 & GPIO_INT_REG_LINK_UP) { | 4169 | else if (val64 & GPIO_INT_REG_LINK_UP) { |
4106 | val64 = readq(&bar0->adapter_status); | 4170 | val64 = readq(&bar0->adapter_status); |
4107 | if (verify_xena_quiescence(sp, val64, | ||
4108 | sp->device_enabled_once)) { | ||
4109 | /* Enable Adapter */ | 4171 | /* Enable Adapter */ |
4110 | val64 = readq(&bar0->adapter_control); | 4172 | val64 = readq(&bar0->adapter_control); |
4111 | val64 |= ADAPTER_CNTL_EN; | 4173 | val64 |= ADAPTER_CNTL_EN; |
4112 | writeq(val64, &bar0->adapter_control); | 4174 | writeq(val64, &bar0->adapter_control); |
4113 | val64 |= ADAPTER_LED_ON; | 4175 | val64 |= ADAPTER_LED_ON; |
4114 | writeq(val64, &bar0->adapter_control); | 4176 | writeq(val64, &bar0->adapter_control); |
4115 | if (!sp->device_enabled_once) | 4177 | if (!sp->device_enabled_once) |
4116 | sp->device_enabled_once = 1; | 4178 | sp->device_enabled_once = 1; |
4117 | 4179 | ||
4118 | s2io_link(sp, LINK_UP); | 4180 | s2io_link(sp, LINK_UP); |
4119 | /* | 4181 | /* |
4120 | * unmask link down interrupt and mask link-up | 4182 | * unmask link down interrupt and mask link-up |
4121 | * intr | 4183 | * intr |
4122 | */ | 4184 | */ |
4123 | val64 = readq(&bar0->gpio_int_mask); | 4185 | val64 = readq(&bar0->gpio_int_mask); |
4124 | val64 &= ~GPIO_INT_MASK_LINK_DOWN; | 4186 | val64 &= ~GPIO_INT_MASK_LINK_DOWN; |
4125 | val64 |= GPIO_INT_MASK_LINK_UP; | 4187 | val64 |= GPIO_INT_MASK_LINK_UP; |
4126 | writeq(val64, &bar0->gpio_int_mask); | 4188 | writeq(val64, &bar0->gpio_int_mask); |
4127 | 4189 | ||
4128 | } | ||
4129 | }else if (val64 & GPIO_INT_REG_LINK_DOWN) { | 4190 | }else if (val64 & GPIO_INT_REG_LINK_DOWN) { |
4130 | val64 = readq(&bar0->adapter_status); | 4191 | val64 = readq(&bar0->adapter_status); |
4131 | if (verify_xena_quiescence(sp, val64, | 4192 | s2io_link(sp, LINK_DOWN); |
4132 | sp->device_enabled_once)) { | 4193 | /* Link is down so unmaks link up interrupt */ |
4133 | s2io_link(sp, LINK_DOWN); | 4194 | val64 = readq(&bar0->gpio_int_mask); |
4134 | /* Link is down so unmaks link up interrupt */ | 4195 | val64 &= ~GPIO_INT_MASK_LINK_UP; |
4135 | val64 = readq(&bar0->gpio_int_mask); | 4196 | val64 |= GPIO_INT_MASK_LINK_DOWN; |
4136 | val64 &= ~GPIO_INT_MASK_LINK_UP; | 4197 | writeq(val64, &bar0->gpio_int_mask); |
4137 | val64 |= GPIO_INT_MASK_LINK_DOWN; | ||
4138 | writeq(val64, &bar0->gpio_int_mask); | ||
4139 | } | ||
4140 | } | 4198 | } |
4141 | } | 4199 | } |
4142 | val64 = readq(&bar0->gpio_int_mask); | 4200 | val64 = readq(&bar0->gpio_int_mask); |
@@ -4161,7 +4219,7 @@ static irqreturn_t s2io_isr(int irq, void *dev_id) | |||
4161 | nic_t *sp = dev->priv; | 4219 | nic_t *sp = dev->priv; |
4162 | XENA_dev_config_t __iomem *bar0 = sp->bar0; | 4220 | XENA_dev_config_t __iomem *bar0 = sp->bar0; |
4163 | int i; | 4221 | int i; |
4164 | u64 reason = 0, val64, org_mask; | 4222 | u64 reason = 0; |
4165 | mac_info_t *mac_control; | 4223 | mac_info_t *mac_control; |
4166 | struct config_param *config; | 4224 | struct config_param *config; |
4167 | 4225 | ||
@@ -4180,22 +4238,24 @@ static irqreturn_t s2io_isr(int irq, void *dev_id) | |||
4180 | reason = readq(&bar0->general_int_status); | 4238 | reason = readq(&bar0->general_int_status); |
4181 | 4239 | ||
4182 | if (!reason) { | 4240 | if (!reason) { |
4183 | /* The interrupt was not raised by Xena. */ | 4241 | /* The interrupt was not raised by us. */ |
4242 | atomic_dec(&sp->isr_cnt); | ||
4243 | return IRQ_NONE; | ||
4244 | } | ||
4245 | else if (unlikely(reason == S2IO_MINUS_ONE) ) { | ||
4246 | /* Disable device and get out */ | ||
4184 | atomic_dec(&sp->isr_cnt); | 4247 | atomic_dec(&sp->isr_cnt); |
4185 | return IRQ_NONE; | 4248 | return IRQ_NONE; |
4186 | } | 4249 | } |
4187 | |||
4188 | val64 = 0xFFFFFFFFFFFFFFFFULL; | ||
4189 | /* Store current mask before masking all interrupts */ | ||
4190 | org_mask = readq(&bar0->general_int_mask); | ||
4191 | writeq(val64, &bar0->general_int_mask); | ||
4192 | 4250 | ||
4193 | if (napi) { | 4251 | if (napi) { |
4194 | if (reason & GEN_INTR_RXTRAFFIC) { | 4252 | if (reason & GEN_INTR_RXTRAFFIC) { |
4195 | if (netif_rx_schedule_prep(dev)) { | 4253 | if ( likely ( netif_rx_schedule_prep(dev)) ) { |
4196 | writeq(val64, &bar0->rx_traffic_mask); | ||
4197 | __netif_rx_schedule(dev); | 4254 | __netif_rx_schedule(dev); |
4255 | writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask); | ||
4198 | } | 4256 | } |
4257 | else | ||
4258 | writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int); | ||
4199 | } | 4259 | } |
4200 | } else { | 4260 | } else { |
4201 | /* | 4261 | /* |
@@ -4205,7 +4265,9 @@ static irqreturn_t s2io_isr(int irq, void *dev_id) | |||
4205 | * will ensure that the actual interrupt causing bit get's | 4265 | * will ensure that the actual interrupt causing bit get's |
4206 | * cleared and hence a read can be avoided. | 4266 | * cleared and hence a read can be avoided. |
4207 | */ | 4267 | */ |
4208 | writeq(val64, &bar0->rx_traffic_int); | 4268 | if (reason & GEN_INTR_RXTRAFFIC) |
4269 | writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int); | ||
4270 | |||
4209 | for (i = 0; i < config->rx_ring_num; i++) { | 4271 | for (i = 0; i < config->rx_ring_num; i++) { |
4210 | rx_intr_handler(&mac_control->rings[i]); | 4272 | rx_intr_handler(&mac_control->rings[i]); |
4211 | } | 4273 | } |
@@ -4216,7 +4278,8 @@ static irqreturn_t s2io_isr(int irq, void *dev_id) | |||
4216 | * will ensure that the actual interrupt causing bit get's | 4278 | * will ensure that the actual interrupt causing bit get's |
4217 | * cleared and hence a read can be avoided. | 4279 | * cleared and hence a read can be avoided. |
4218 | */ | 4280 | */ |
4219 | writeq(val64, &bar0->tx_traffic_int); | 4281 | if (reason & GEN_INTR_TXTRAFFIC) |
4282 | writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int); | ||
4220 | 4283 | ||
4221 | for (i = 0; i < config->tx_fifo_num; i++) | 4284 | for (i = 0; i < config->tx_fifo_num; i++) |
4222 | tx_intr_handler(&mac_control->fifos[i]); | 4285 | tx_intr_handler(&mac_control->fifos[i]); |
@@ -4912,6 +4975,7 @@ static void s2io_vpd_read(nic_t *nic) | |||
4912 | strcpy(nic->product_name, "Xframe I 10GbE network adapter"); | 4975 | strcpy(nic->product_name, "Xframe I 10GbE network adapter"); |
4913 | vpd_addr = 0x50; | 4976 | vpd_addr = 0x50; |
4914 | } | 4977 | } |
4978 | strcpy(nic->serial_num, "NOT AVAILABLE"); | ||
4915 | 4979 | ||
4916 | vpd_data = kmalloc(256, GFP_KERNEL); | 4980 | vpd_data = kmalloc(256, GFP_KERNEL); |
4917 | if (!vpd_data) | 4981 | if (!vpd_data) |
@@ -4935,7 +4999,22 @@ static void s2io_vpd_read(nic_t *nic) | |||
4935 | pci_read_config_dword(nic->pdev, (vpd_addr + 4), | 4999 | pci_read_config_dword(nic->pdev, (vpd_addr + 4), |
4936 | (u32 *)&vpd_data[i]); | 5000 | (u32 *)&vpd_data[i]); |
4937 | } | 5001 | } |
4938 | if ((!fail) && (vpd_data[1] < VPD_PRODUCT_NAME_LEN)) { | 5002 | |
5003 | if(!fail) { | ||
5004 | /* read serial number of adapter */ | ||
5005 | for (cnt = 0; cnt < 256; cnt++) { | ||
5006 | if ((vpd_data[cnt] == 'S') && | ||
5007 | (vpd_data[cnt+1] == 'N') && | ||
5008 | (vpd_data[cnt+2] < VPD_STRING_LEN)) { | ||
5009 | memset(nic->serial_num, 0, VPD_STRING_LEN); | ||
5010 | memcpy(nic->serial_num, &vpd_data[cnt + 3], | ||
5011 | vpd_data[cnt+2]); | ||
5012 | break; | ||
5013 | } | ||
5014 | } | ||
5015 | } | ||
5016 | |||
5017 | if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) { | ||
4939 | memset(nic->product_name, 0, vpd_data[1]); | 5018 | memset(nic->product_name, 0, vpd_data[1]); |
4940 | memcpy(nic->product_name, &vpd_data[3], vpd_data[1]); | 5019 | memcpy(nic->product_name, &vpd_data[3], vpd_data[1]); |
4941 | } | 5020 | } |
@@ -5890,50 +5969,45 @@ static void s2io_set_link(struct work_struct *work) | |||
5890 | } | 5969 | } |
5891 | 5970 | ||
5892 | val64 = readq(&bar0->adapter_status); | 5971 | val64 = readq(&bar0->adapter_status); |
5893 | if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) { | 5972 | if (LINK_IS_UP(val64)) { |
5894 | if (LINK_IS_UP(val64)) { | 5973 | if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) { |
5895 | val64 = readq(&bar0->adapter_control); | 5974 | if (verify_xena_quiescence(nic)) { |
5896 | val64 |= ADAPTER_CNTL_EN; | 5975 | val64 = readq(&bar0->adapter_control); |
5897 | writeq(val64, &bar0->adapter_control); | 5976 | val64 |= ADAPTER_CNTL_EN; |
5898 | if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type, | ||
5899 | subid)) { | ||
5900 | val64 = readq(&bar0->gpio_control); | ||
5901 | val64 |= GPIO_CTRL_GPIO_0; | ||
5902 | writeq(val64, &bar0->gpio_control); | ||
5903 | val64 = readq(&bar0->gpio_control); | ||
5904 | } else { | ||
5905 | val64 |= ADAPTER_LED_ON; | ||
5906 | writeq(val64, &bar0->adapter_control); | 5977 | writeq(val64, &bar0->adapter_control); |
5907 | } | 5978 | if (CARDS_WITH_FAULTY_LINK_INDICATORS( |
5908 | if (s2io_link_fault_indication(nic) == | 5979 | nic->device_type, subid)) { |
5909 | MAC_RMAC_ERR_TIMER) { | 5980 | val64 = readq(&bar0->gpio_control); |
5910 | val64 = readq(&bar0->adapter_status); | 5981 | val64 |= GPIO_CTRL_GPIO_0; |
5911 | if (!LINK_IS_UP(val64)) { | 5982 | writeq(val64, &bar0->gpio_control); |
5912 | DBG_PRINT(ERR_DBG, "%s:", dev->name); | 5983 | val64 = readq(&bar0->gpio_control); |
5913 | DBG_PRINT(ERR_DBG, " Link down"); | 5984 | } else { |
5914 | DBG_PRINT(ERR_DBG, "after "); | 5985 | val64 |= ADAPTER_LED_ON; |
5915 | DBG_PRINT(ERR_DBG, "enabling "); | 5986 | writeq(val64, &bar0->adapter_control); |
5916 | DBG_PRINT(ERR_DBG, "device \n"); | ||
5917 | } | 5987 | } |
5918 | } | ||
5919 | if (nic->device_enabled_once == FALSE) { | ||
5920 | nic->device_enabled_once = TRUE; | 5988 | nic->device_enabled_once = TRUE; |
5989 | } else { | ||
5990 | DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name); | ||
5991 | DBG_PRINT(ERR_DBG, "device is not Quiescent\n"); | ||
5992 | netif_stop_queue(dev); | ||
5921 | } | 5993 | } |
5994 | } | ||
5995 | val64 = readq(&bar0->adapter_status); | ||
5996 | if (!LINK_IS_UP(val64)) { | ||
5997 | DBG_PRINT(ERR_DBG, "%s:", dev->name); | ||
5998 | DBG_PRINT(ERR_DBG, " Link down after enabling "); | ||
5999 | DBG_PRINT(ERR_DBG, "device \n"); | ||
6000 | } else | ||
5922 | s2io_link(nic, LINK_UP); | 6001 | s2io_link(nic, LINK_UP); |
5923 | } else { | 6002 | } else { |
5924 | if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type, | 6003 | if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type, |
5925 | subid)) { | 6004 | subid)) { |
5926 | val64 = readq(&bar0->gpio_control); | 6005 | val64 = readq(&bar0->gpio_control); |
5927 | val64 &= ~GPIO_CTRL_GPIO_0; | 6006 | val64 &= ~GPIO_CTRL_GPIO_0; |
5928 | writeq(val64, &bar0->gpio_control); | 6007 | writeq(val64, &bar0->gpio_control); |
5929 | val64 = readq(&bar0->gpio_control); | 6008 | val64 = readq(&bar0->gpio_control); |
5930 | } | ||
5931 | s2io_link(nic, LINK_DOWN); | ||
5932 | } | 6009 | } |
5933 | } else { /* NIC is not Quiescent. */ | 6010 | s2io_link(nic, LINK_DOWN); |
5934 | DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name); | ||
5935 | DBG_PRINT(ERR_DBG, "device is not Quiescent\n"); | ||
5936 | netif_stop_queue(dev); | ||
5937 | } | 6011 | } |
5938 | clear_bit(0, &(nic->link_state)); | 6012 | clear_bit(0, &(nic->link_state)); |
5939 | } | 6013 | } |
@@ -5982,7 +6056,7 @@ static int set_rxd_buffer_pointer(nic_t *sp, RxD_t *rxdp, buffAdd_t *ba, | |||
5982 | *skb = dev_alloc_skb(size); | 6056 | *skb = dev_alloc_skb(size); |
5983 | if (!(*skb)) { | 6057 | if (!(*skb)) { |
5984 | DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n", | 6058 | DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n", |
5985 | dev->name); | 6059 | dev->name); |
5986 | return -ENOMEM; | 6060 | return -ENOMEM; |
5987 | } | 6061 | } |
5988 | ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2 = | 6062 | ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2 = |
@@ -6252,7 +6326,8 @@ static void s2io_card_down(nic_t * sp) | |||
6252 | rxd_owner_bit_reset(sp); | 6326 | rxd_owner_bit_reset(sp); |
6253 | 6327 | ||
6254 | val64 = readq(&bar0->adapter_status); | 6328 | val64 = readq(&bar0->adapter_status); |
6255 | if (verify_xena_quiescence(sp, val64, sp->device_enabled_once)) { | 6329 | if (verify_xena_quiescence(sp)) { |
6330 | if(verify_pcc_quiescent(sp, sp->device_enabled_once)) | ||
6256 | break; | 6331 | break; |
6257 | } | 6332 | } |
6258 | 6333 | ||
@@ -6315,6 +6390,13 @@ static int s2io_card_up(nic_t * sp) | |||
6315 | DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i, | 6390 | DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i, |
6316 | atomic_read(&sp->rx_bufs_left[i])); | 6391 | atomic_read(&sp->rx_bufs_left[i])); |
6317 | } | 6392 | } |
6393 | /* Maintain the state prior to the open */ | ||
6394 | if (sp->promisc_flg) | ||
6395 | sp->promisc_flg = 0; | ||
6396 | if (sp->m_cast_flg) { | ||
6397 | sp->m_cast_flg = 0; | ||
6398 | sp->all_multi_pos= 0; | ||
6399 | } | ||
6318 | 6400 | ||
6319 | /* Setting its receive mode */ | 6401 | /* Setting its receive mode */ |
6320 | s2io_set_multicast(dev); | 6402 | s2io_set_multicast(dev); |
@@ -6914,7 +6996,7 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre) | |||
6914 | sp->bar0 = ioremap(pci_resource_start(pdev, 0), | 6996 | sp->bar0 = ioremap(pci_resource_start(pdev, 0), |
6915 | pci_resource_len(pdev, 0)); | 6997 | pci_resource_len(pdev, 0)); |
6916 | if (!sp->bar0) { | 6998 | if (!sp->bar0) { |
6917 | DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem1\n", | 6999 | DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n", |
6918 | dev->name); | 7000 | dev->name); |
6919 | ret = -ENOMEM; | 7001 | ret = -ENOMEM; |
6920 | goto bar0_remap_failed; | 7002 | goto bar0_remap_failed; |
@@ -6923,7 +7005,7 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre) | |||
6923 | sp->bar1 = ioremap(pci_resource_start(pdev, 2), | 7005 | sp->bar1 = ioremap(pci_resource_start(pdev, 2), |
6924 | pci_resource_len(pdev, 2)); | 7006 | pci_resource_len(pdev, 2)); |
6925 | if (!sp->bar1) { | 7007 | if (!sp->bar1) { |
6926 | DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem2\n", | 7008 | DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n", |
6927 | dev->name); | 7009 | dev->name); |
6928 | ret = -ENOMEM; | 7010 | ret = -ENOMEM; |
6929 | goto bar1_remap_failed; | 7011 | goto bar1_remap_failed; |
@@ -7081,13 +7163,14 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre) | |||
7081 | DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name, | 7163 | DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name, |
7082 | s2io_driver_version); | 7164 | s2io_driver_version); |
7083 | DBG_PRINT(ERR_DBG, "%s: MAC ADDR: " | 7165 | DBG_PRINT(ERR_DBG, "%s: MAC ADDR: " |
7084 | "%02x:%02x:%02x:%02x:%02x:%02x\n", dev->name, | 7166 | "%02x:%02x:%02x:%02x:%02x:%02x", dev->name, |
7085 | sp->def_mac_addr[0].mac_addr[0], | 7167 | sp->def_mac_addr[0].mac_addr[0], |
7086 | sp->def_mac_addr[0].mac_addr[1], | 7168 | sp->def_mac_addr[0].mac_addr[1], |
7087 | sp->def_mac_addr[0].mac_addr[2], | 7169 | sp->def_mac_addr[0].mac_addr[2], |
7088 | sp->def_mac_addr[0].mac_addr[3], | 7170 | sp->def_mac_addr[0].mac_addr[3], |
7089 | sp->def_mac_addr[0].mac_addr[4], | 7171 | sp->def_mac_addr[0].mac_addr[4], |
7090 | sp->def_mac_addr[0].mac_addr[5]); | 7172 | sp->def_mac_addr[0].mac_addr[5]); |
7173 | DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num); | ||
7091 | if (sp->device_type & XFRAME_II_DEVICE) { | 7174 | if (sp->device_type & XFRAME_II_DEVICE) { |
7092 | mode = s2io_print_pci_mode(sp); | 7175 | mode = s2io_print_pci_mode(sp); |
7093 | if (mode < 0) { | 7176 | if (mode < 0) { |
@@ -7200,7 +7283,6 @@ static void __devexit s2io_rem_nic(struct pci_dev *pdev) | |||
7200 | free_shared_mem(sp); | 7283 | free_shared_mem(sp); |
7201 | iounmap(sp->bar0); | 7284 | iounmap(sp->bar0); |
7202 | iounmap(sp->bar1); | 7285 | iounmap(sp->bar1); |
7203 | pci_disable_device(pdev); | ||
7204 | if (sp->intr_type != MSI_X) | 7286 | if (sp->intr_type != MSI_X) |
7205 | pci_release_regions(pdev); | 7287 | pci_release_regions(pdev); |
7206 | else { | 7288 | else { |
@@ -7211,6 +7293,7 @@ static void __devexit s2io_rem_nic(struct pci_dev *pdev) | |||
7211 | } | 7293 | } |
7212 | pci_set_drvdata(pdev, NULL); | 7294 | pci_set_drvdata(pdev, NULL); |
7213 | free_netdev(dev); | 7295 | free_netdev(dev); |
7296 | pci_disable_device(pdev); | ||
7214 | } | 7297 | } |
7215 | 7298 | ||
7216 | /** | 7299 | /** |
diff --git a/drivers/net/s2io.h b/drivers/net/s2io.h index 577fa3ad214e..8114f4b80e8a 100644 --- a/drivers/net/s2io.h +++ b/drivers/net/s2io.h | |||
@@ -30,6 +30,8 @@ | |||
30 | #undef SUCCESS | 30 | #undef SUCCESS |
31 | #define SUCCESS 0 | 31 | #define SUCCESS 0 |
32 | #define FAILURE -1 | 32 | #define FAILURE -1 |
33 | #define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL | ||
34 | #define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100 | ||
33 | 35 | ||
34 | #define CHECKBIT(value, nbit) (value & (1 << nbit)) | 36 | #define CHECKBIT(value, nbit) (value & (1 << nbit)) |
35 | 37 | ||
@@ -537,9 +539,9 @@ typedef struct _RxD_block { | |||
537 | 539 | ||
538 | #define SIZE_OF_BLOCK 4096 | 540 | #define SIZE_OF_BLOCK 4096 |
539 | 541 | ||
540 | #define RXD_MODE_1 0 | 542 | #define RXD_MODE_1 0 /* One Buffer mode */ |
541 | #define RXD_MODE_3A 1 | 543 | #define RXD_MODE_3A 1 /* Three Buffer mode */ |
542 | #define RXD_MODE_3B 2 | 544 | #define RXD_MODE_3B 2 /* Two Buffer mode */ |
543 | 545 | ||
544 | /* Structure to hold virtual addresses of Buf0 and Buf1 in | 546 | /* Structure to hold virtual addresses of Buf0 and Buf1 in |
545 | * 2buf mode. */ | 547 | * 2buf mode. */ |
@@ -849,8 +851,9 @@ struct s2io_nic { | |||
849 | spinlock_t rx_lock; | 851 | spinlock_t rx_lock; |
850 | atomic_t isr_cnt; | 852 | atomic_t isr_cnt; |
851 | u64 *ufo_in_band_v; | 853 | u64 *ufo_in_band_v; |
852 | #define VPD_PRODUCT_NAME_LEN 50 | 854 | #define VPD_STRING_LEN 80 |
853 | u8 product_name[VPD_PRODUCT_NAME_LEN]; | 855 | u8 product_name[VPD_STRING_LEN]; |
856 | u8 serial_num[VPD_STRING_LEN]; | ||
854 | }; | 857 | }; |
855 | 858 | ||
856 | #define RESET_ERROR 1; | 859 | #define RESET_ERROR 1; |
@@ -974,11 +977,13 @@ static void tx_intr_handler(fifo_info_t *fifo_data); | |||
974 | static void alarm_intr_handler(struct s2io_nic *sp); | 977 | static void alarm_intr_handler(struct s2io_nic *sp); |
975 | 978 | ||
976 | static int s2io_starter(void); | 979 | static int s2io_starter(void); |
980 | static void s2io_closer(void); | ||
977 | static void s2io_tx_watchdog(struct net_device *dev); | 981 | static void s2io_tx_watchdog(struct net_device *dev); |
978 | static void s2io_tasklet(unsigned long dev_addr); | 982 | static void s2io_tasklet(unsigned long dev_addr); |
979 | static void s2io_set_multicast(struct net_device *dev); | 983 | static void s2io_set_multicast(struct net_device *dev); |
980 | static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp); | 984 | static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp); |
981 | static void s2io_link(nic_t * sp, int link); | 985 | static void s2io_link(nic_t * sp, int link); |
986 | static void s2io_reset(nic_t * sp); | ||
982 | static int s2io_poll(struct net_device *dev, int *budget); | 987 | static int s2io_poll(struct net_device *dev, int *budget); |
983 | static void s2io_init_pci(nic_t * sp); | 988 | static void s2io_init_pci(nic_t * sp); |
984 | static int s2io_set_mac_addr(struct net_device *dev, u8 * addr); | 989 | static int s2io_set_mac_addr(struct net_device *dev, u8 * addr); |
@@ -990,13 +995,17 @@ s2io_msix_ring_handle(int irq, void *dev_id); | |||
990 | static irqreturn_t | 995 | static irqreturn_t |
991 | s2io_msix_fifo_handle(int irq, void *dev_id); | 996 | s2io_msix_fifo_handle(int irq, void *dev_id); |
992 | static irqreturn_t s2io_isr(int irq, void *dev_id); | 997 | static irqreturn_t s2io_isr(int irq, void *dev_id); |
993 | static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag); | 998 | static int verify_xena_quiescence(nic_t *sp); |
994 | static const struct ethtool_ops netdev_ethtool_ops; | 999 | static const struct ethtool_ops netdev_ethtool_ops; |
995 | static void s2io_set_link(struct work_struct *work); | 1000 | static void s2io_set_link(struct work_struct *work); |
996 | static int s2io_set_swapper(nic_t * sp); | 1001 | static int s2io_set_swapper(nic_t * sp); |
997 | static void s2io_card_down(nic_t *nic); | 1002 | static void s2io_card_down(nic_t *nic); |
998 | static int s2io_card_up(nic_t *nic); | 1003 | static int s2io_card_up(nic_t *nic); |
999 | static int get_xena_rev_id(struct pci_dev *pdev); | 1004 | static int get_xena_rev_id(struct pci_dev *pdev); |
1005 | static int wait_for_cmd_complete(void *addr, u64 busy_bit); | ||
1006 | static int s2io_add_isr(nic_t * sp); | ||
1007 | static void s2io_rem_isr(nic_t * sp); | ||
1008 | |||
1000 | static void restore_xmsi_data(nic_t *nic); | 1009 | static void restore_xmsi_data(nic_t *nic); |
1001 | 1010 | ||
1002 | static int s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, lro_t **lro, RxD_t *rxdp, nic_t *sp); | 1011 | static int s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, lro_t **lro, RxD_t *rxdp, nic_t *sp); |