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-rw-r--r--drivers/net/bnx2x/bnx2x_link.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/net/bnx2x/bnx2x_link.c b/drivers/net/bnx2x/bnx2x_link.c
index 89b33e27f614..b6588c5411ea 100644
--- a/drivers/net/bnx2x/bnx2x_link.c
+++ b/drivers/net/bnx2x/bnx2x_link.c
@@ -5302,7 +5302,7 @@ static u8 bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
5302{ 5302{
5303 struct bnx2x *bp = params->bp; 5303 struct bnx2x *bp = params->bp;
5304 u16 autoneg_val, an_1000_val, an_10_100_val; 5304 u16 autoneg_val, an_1000_val, an_10_100_val;
5305 bnx2x_wait_reset_complete(bp, phy); 5305
5306 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, 5306 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
5307 1 << NIG_LATCH_BC_ENABLE_MI_INT); 5307 1 << NIG_LATCH_BC_ENABLE_MI_INT);
5308 5308
@@ -5431,6 +5431,7 @@ static u8 bnx2x_8481_config_init(struct bnx2x_phy *phy,
5431 5431
5432 /* HW reset */ 5432 /* HW reset */
5433 bnx2x_ext_phy_hw_reset(bp, params->port); 5433 bnx2x_ext_phy_hw_reset(bp, params->port);
5434 bnx2x_wait_reset_complete(bp, phy);
5434 5435
5435 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 5436 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
5436 return bnx2x_848xx_cmn_config_init(phy, params, vars); 5437 return bnx2x_848xx_cmn_config_init(phy, params, vars);
@@ -5453,8 +5454,9 @@ static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
5453 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, 5454 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
5454 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 5455 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
5455 port); 5456 port);
5456 msleep(200); /* 100 is not enough */ 5457 bnx2x_wait_reset_complete(bp, phy);
5457 5458 /* Wait for GPHY to come out of reset */
5459 msleep(50);
5458 /* BCM84823 requires that XGXS links up first @ 10G for normal 5460 /* BCM84823 requires that XGXS links up first @ 10G for normal
5459 behavior */ 5461 behavior */
5460 temp = vars->line_speed; 5462 temp = vars->line_speed;