diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/mtd/nand/denali.c | 82 | ||||
-rw-r--r-- | drivers/mtd/nand/denali.h | 2 |
2 files changed, 40 insertions, 44 deletions
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 52d1cf067cd4..3184eb9bdd57 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c | |||
@@ -19,6 +19,7 @@ | |||
19 | 19 | ||
20 | #include <linux/interrupt.h> | 20 | #include <linux/interrupt.h> |
21 | #include <linux/delay.h> | 21 | #include <linux/delay.h> |
22 | #include <linux/dma-mapping.h> | ||
22 | #include <linux/wait.h> | 23 | #include <linux/wait.h> |
23 | #include <linux/mutex.h> | 24 | #include <linux/mutex.h> |
24 | #include <linux/slab.h> | 25 | #include <linux/slab.h> |
@@ -192,7 +193,7 @@ static void reset_bank(struct denali_nand_info *denali) | |||
192 | irq_status = wait_for_irq(denali, irq_mask); | 193 | irq_status = wait_for_irq(denali, irq_mask); |
193 | 194 | ||
194 | if (irq_status & operation_timeout[denali->flash_bank]) | 195 | if (irq_status & operation_timeout[denali->flash_bank]) |
195 | dev_err(&denali->dev->dev, "reset bank failed.\n"); | 196 | dev_err(denali->dev, "reset bank failed.\n"); |
196 | } | 197 | } |
197 | 198 | ||
198 | /* Reset the flash controller */ | 199 | /* Reset the flash controller */ |
@@ -200,7 +201,7 @@ static uint16_t denali_nand_reset(struct denali_nand_info *denali) | |||
200 | { | 201 | { |
201 | uint32_t i; | 202 | uint32_t i; |
202 | 203 | ||
203 | dev_dbg(&denali->dev->dev, "%s, Line %d, Function: %s\n", | 204 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
204 | __FILE__, __LINE__, __func__); | 205 | __FILE__, __LINE__, __func__); |
205 | 206 | ||
206 | for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) | 207 | for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) |
@@ -216,7 +217,7 @@ static uint16_t denali_nand_reset(struct denali_nand_info *denali) | |||
216 | cpu_relax(); | 217 | cpu_relax(); |
217 | if (ioread32(denali->flash_reg + intr_status_addresses[i]) & | 218 | if (ioread32(denali->flash_reg + intr_status_addresses[i]) & |
218 | operation_timeout[i]) | 219 | operation_timeout[i]) |
219 | dev_dbg(&denali->dev->dev, | 220 | dev_dbg(denali->dev, |
220 | "NAND Reset operation timed out on bank %d\n", i); | 221 | "NAND Reset operation timed out on bank %d\n", i); |
221 | } | 222 | } |
222 | 223 | ||
@@ -254,7 +255,7 @@ static void nand_onfi_timing_set(struct denali_nand_info *denali, | |||
254 | uint16_t acc_clks; | 255 | uint16_t acc_clks; |
255 | uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; | 256 | uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; |
256 | 257 | ||
257 | dev_dbg(&denali->dev->dev, "%s, Line %d, Function: %s\n", | 258 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
258 | __FILE__, __LINE__, __func__); | 259 | __FILE__, __LINE__, __func__); |
259 | 260 | ||
260 | en_lo = CEIL_DIV(Trp[mode], CLK_X); | 261 | en_lo = CEIL_DIV(Trp[mode], CLK_X); |
@@ -291,7 +292,7 @@ static void nand_onfi_timing_set(struct denali_nand_info *denali, | |||
291 | acc_clks++; | 292 | acc_clks++; |
292 | 293 | ||
293 | if ((data_invalid - acc_clks * CLK_X) < 2) | 294 | if ((data_invalid - acc_clks * CLK_X) < 2) |
294 | dev_warn(&denali->dev->dev, "%s, Line %d: Warning!\n", | 295 | dev_warn(denali->dev, "%s, Line %d: Warning!\n", |
295 | __FILE__, __LINE__); | 296 | __FILE__, __LINE__); |
296 | 297 | ||
297 | addr_2_data = CEIL_DIV(Tadl[mode], CLK_X); | 298 | addr_2_data = CEIL_DIV(Tadl[mode], CLK_X); |
@@ -419,7 +420,7 @@ static void get_hynix_nand_para(struct denali_nand_info *denali, | |||
419 | #endif | 420 | #endif |
420 | break; | 421 | break; |
421 | default: | 422 | default: |
422 | dev_warn(&denali->dev->dev, | 423 | dev_warn(denali->dev, |
423 | "Spectra: Unknown Hynix NAND (Device ID: 0x%x)." | 424 | "Spectra: Unknown Hynix NAND (Device ID: 0x%x)." |
424 | "Will use default parameter values instead.\n", | 425 | "Will use default parameter values instead.\n", |
425 | device_id); | 426 | device_id); |
@@ -441,7 +442,7 @@ static void find_valid_banks(struct denali_nand_info *denali) | |||
441 | index_addr_read_data(denali, | 442 | index_addr_read_data(denali, |
442 | (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]); | 443 | (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]); |
443 | 444 | ||
444 | dev_dbg(&denali->dev->dev, | 445 | dev_dbg(denali->dev, |
445 | "Return 1st ID for bank[%d]: %x\n", i, id[i]); | 446 | "Return 1st ID for bank[%d]: %x\n", i, id[i]); |
446 | 447 | ||
447 | if (i == 0) { | 448 | if (i == 0) { |
@@ -461,13 +462,13 @@ static void find_valid_banks(struct denali_nand_info *denali) | |||
461 | * Multichip support is not enabled. | 462 | * Multichip support is not enabled. |
462 | */ | 463 | */ |
463 | if (denali->total_used_banks != 1) { | 464 | if (denali->total_used_banks != 1) { |
464 | dev_err(&denali->dev->dev, | 465 | dev_err(denali->dev, |
465 | "Sorry, Intel CE4100 only supports " | 466 | "Sorry, Intel CE4100 only supports " |
466 | "a single NAND device.\n"); | 467 | "a single NAND device.\n"); |
467 | BUG(); | 468 | BUG(); |
468 | } | 469 | } |
469 | } | 470 | } |
470 | dev_dbg(&denali->dev->dev, | 471 | dev_dbg(denali->dev, |
471 | "denali->total_used_banks: %d\n", denali->total_used_banks); | 472 | "denali->total_used_banks: %d\n", denali->total_used_banks); |
472 | } | 473 | } |
473 | 474 | ||
@@ -501,7 +502,7 @@ static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) | |||
501 | uint32_t id_bytes[5], addr; | 502 | uint32_t id_bytes[5], addr; |
502 | uint8_t i, maf_id, device_id; | 503 | uint8_t i, maf_id, device_id; |
503 | 504 | ||
504 | dev_dbg(&denali->dev->dev, | 505 | dev_dbg(denali->dev, |
505 | "%s, Line %d, Function: %s\n", | 506 | "%s, Line %d, Function: %s\n", |
506 | __FILE__, __LINE__, __func__); | 507 | __FILE__, __LINE__, __func__); |
507 | 508 | ||
@@ -530,7 +531,7 @@ static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) | |||
530 | get_hynix_nand_para(denali, device_id); | 531 | get_hynix_nand_para(denali, device_id); |
531 | } | 532 | } |
532 | 533 | ||
533 | dev_info(&denali->dev->dev, | 534 | dev_info(denali->dev, |
534 | "Dump timing register values:" | 535 | "Dump timing register values:" |
535 | "acc_clks: %d, re_2_we: %d, re_2_re: %d\n" | 536 | "acc_clks: %d, re_2_we: %d, re_2_re: %d\n" |
536 | "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n" | 537 | "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n" |
@@ -560,7 +561,7 @@ static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) | |||
560 | static void denali_set_intr_modes(struct denali_nand_info *denali, | 561 | static void denali_set_intr_modes(struct denali_nand_info *denali, |
561 | uint16_t INT_ENABLE) | 562 | uint16_t INT_ENABLE) |
562 | { | 563 | { |
563 | dev_dbg(&denali->dev->dev, "%s, Line %d, Function: %s\n", | 564 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
564 | __FILE__, __LINE__, __func__); | 565 | __FILE__, __LINE__, __func__); |
565 | 566 | ||
566 | if (INT_ENABLE) | 567 | if (INT_ENABLE) |
@@ -800,7 +801,7 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, | |||
800 | irq_status = wait_for_irq(denali, irq_mask); | 801 | irq_status = wait_for_irq(denali, irq_mask); |
801 | 802 | ||
802 | if (irq_status == 0) { | 803 | if (irq_status == 0) { |
803 | dev_err(&denali->dev->dev, | 804 | dev_err(denali->dev, |
804 | "cmd, page, addr on timeout " | 805 | "cmd, page, addr on timeout " |
805 | "(0x%x, 0x%x, 0x%x)\n", | 806 | "(0x%x, 0x%x, 0x%x)\n", |
806 | cmd, denali->page, addr); | 807 | cmd, denali->page, addr); |
@@ -875,11 +876,11 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |||
875 | irq_status = wait_for_irq(denali, irq_mask); | 876 | irq_status = wait_for_irq(denali, irq_mask); |
876 | 877 | ||
877 | if (irq_status == 0) { | 878 | if (irq_status == 0) { |
878 | dev_err(&denali->dev->dev, "OOB write failed\n"); | 879 | dev_err(denali->dev, "OOB write failed\n"); |
879 | status = -EIO; | 880 | status = -EIO; |
880 | } | 881 | } |
881 | } else { | 882 | } else { |
882 | dev_err(&denali->dev->dev, "unable to send pipeline command\n"); | 883 | dev_err(denali->dev, "unable to send pipeline command\n"); |
883 | status = -EIO; | 884 | status = -EIO; |
884 | } | 885 | } |
885 | return status; | 886 | return status; |
@@ -904,7 +905,7 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |||
904 | irq_status = wait_for_irq(denali, irq_mask); | 905 | irq_status = wait_for_irq(denali, irq_mask); |
905 | 906 | ||
906 | if (irq_status == 0) | 907 | if (irq_status == 0) |
907 | dev_err(&denali->dev->dev, "page on OOB timeout %d\n", | 908 | dev_err(denali->dev, "page on OOB timeout %d\n", |
908 | denali->page); | 909 | denali->page); |
909 | 910 | ||
910 | /* We set the device back to MAIN_ACCESS here as I observed | 911 | /* We set the device back to MAIN_ACCESS here as I observed |
@@ -1045,7 +1046,6 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip, | |||
1045 | const uint8_t *buf, bool raw_xfer) | 1046 | const uint8_t *buf, bool raw_xfer) |
1046 | { | 1047 | { |
1047 | struct denali_nand_info *denali = mtd_to_denali(mtd); | 1048 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
1048 | struct pci_dev *pci_dev = denali->dev; | ||
1049 | 1049 | ||
1050 | dma_addr_t addr = denali->buf.dma_buf; | 1050 | dma_addr_t addr = denali->buf.dma_buf; |
1051 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | 1051 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; |
@@ -1071,7 +1071,7 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip, | |||
1071 | mtd->oobsize); | 1071 | mtd->oobsize); |
1072 | } | 1072 | } |
1073 | 1073 | ||
1074 | pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_TODEVICE); | 1074 | dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE); |
1075 | 1075 | ||
1076 | clear_interrupts(denali); | 1076 | clear_interrupts(denali); |
1077 | denali_enable_dma(denali, true); | 1077 | denali_enable_dma(denali, true); |
@@ -1082,7 +1082,7 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip, | |||
1082 | irq_status = wait_for_irq(denali, irq_mask); | 1082 | irq_status = wait_for_irq(denali, irq_mask); |
1083 | 1083 | ||
1084 | if (irq_status == 0) { | 1084 | if (irq_status == 0) { |
1085 | dev_err(&denali->dev->dev, | 1085 | dev_err(denali->dev, |
1086 | "timeout on write_page (type = %d)\n", | 1086 | "timeout on write_page (type = %d)\n", |
1087 | raw_xfer); | 1087 | raw_xfer); |
1088 | denali->status = | 1088 | denali->status = |
@@ -1091,7 +1091,7 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip, | |||
1091 | } | 1091 | } |
1092 | 1092 | ||
1093 | denali_enable_dma(denali, false); | 1093 | denali_enable_dma(denali, false); |
1094 | pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_TODEVICE); | 1094 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE); |
1095 | } | 1095 | } |
1096 | 1096 | ||
1097 | /* NAND core entry points */ | 1097 | /* NAND core entry points */ |
@@ -1139,7 +1139,6 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |||
1139 | uint8_t *buf, int page) | 1139 | uint8_t *buf, int page) |
1140 | { | 1140 | { |
1141 | struct denali_nand_info *denali = mtd_to_denali(mtd); | 1141 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
1142 | struct pci_dev *pci_dev = denali->dev; | ||
1143 | 1142 | ||
1144 | dma_addr_t addr = denali->buf.dma_buf; | 1143 | dma_addr_t addr = denali->buf.dma_buf; |
1145 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | 1144 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; |
@@ -1150,7 +1149,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |||
1150 | bool check_erased_page = false; | 1149 | bool check_erased_page = false; |
1151 | 1150 | ||
1152 | if (page != denali->page) { | 1151 | if (page != denali->page) { |
1153 | dev_err(&denali->dev->dev, "IN %s: page %d is not" | 1152 | dev_err(denali->dev, "IN %s: page %d is not" |
1154 | " equal to denali->page %d, investigate!!", | 1153 | " equal to denali->page %d, investigate!!", |
1155 | __func__, page, denali->page); | 1154 | __func__, page, denali->page); |
1156 | BUG(); | 1155 | BUG(); |
@@ -1159,7 +1158,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |||
1159 | setup_ecc_for_xfer(denali, true, false); | 1158 | setup_ecc_for_xfer(denali, true, false); |
1160 | 1159 | ||
1161 | denali_enable_dma(denali, true); | 1160 | denali_enable_dma(denali, true); |
1162 | pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_FROMDEVICE); | 1161 | dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); |
1163 | 1162 | ||
1164 | clear_interrupts(denali); | 1163 | clear_interrupts(denali); |
1165 | denali_setup_dma(denali, DENALI_READ); | 1164 | denali_setup_dma(denali, DENALI_READ); |
@@ -1167,7 +1166,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |||
1167 | /* wait for operation to complete */ | 1166 | /* wait for operation to complete */ |
1168 | irq_status = wait_for_irq(denali, irq_mask); | 1167 | irq_status = wait_for_irq(denali, irq_mask); |
1169 | 1168 | ||
1170 | pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE); | 1169 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
1171 | 1170 | ||
1172 | memcpy(buf, denali->buf.buf, mtd->writesize); | 1171 | memcpy(buf, denali->buf.buf, mtd->writesize); |
1173 | 1172 | ||
@@ -1192,7 +1191,6 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |||
1192 | uint8_t *buf, int page) | 1191 | uint8_t *buf, int page) |
1193 | { | 1192 | { |
1194 | struct denali_nand_info *denali = mtd_to_denali(mtd); | 1193 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
1195 | struct pci_dev *pci_dev = denali->dev; | ||
1196 | 1194 | ||
1197 | dma_addr_t addr = denali->buf.dma_buf; | 1195 | dma_addr_t addr = denali->buf.dma_buf; |
1198 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | 1196 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; |
@@ -1201,7 +1199,7 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |||
1201 | uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP; | 1199 | uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP; |
1202 | 1200 | ||
1203 | if (page != denali->page) { | 1201 | if (page != denali->page) { |
1204 | dev_err(&denali->dev->dev, "IN %s: page %d is not" | 1202 | dev_err(denali->dev, "IN %s: page %d is not" |
1205 | " equal to denali->page %d, investigate!!", | 1203 | " equal to denali->page %d, investigate!!", |
1206 | __func__, page, denali->page); | 1204 | __func__, page, denali->page); |
1207 | BUG(); | 1205 | BUG(); |
@@ -1210,7 +1208,7 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |||
1210 | setup_ecc_for_xfer(denali, false, true); | 1208 | setup_ecc_for_xfer(denali, false, true); |
1211 | denali_enable_dma(denali, true); | 1209 | denali_enable_dma(denali, true); |
1212 | 1210 | ||
1213 | pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_FROMDEVICE); | 1211 | dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE); |
1214 | 1212 | ||
1215 | clear_interrupts(denali); | 1213 | clear_interrupts(denali); |
1216 | denali_setup_dma(denali, DENALI_READ); | 1214 | denali_setup_dma(denali, DENALI_READ); |
@@ -1218,7 +1216,7 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |||
1218 | /* wait for operation to complete */ | 1216 | /* wait for operation to complete */ |
1219 | irq_status = wait_for_irq(denali, irq_mask); | 1217 | irq_status = wait_for_irq(denali, irq_mask); |
1220 | 1218 | ||
1221 | pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE); | 1219 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
1222 | 1220 | ||
1223 | denali_enable_dma(denali, false); | 1221 | denali_enable_dma(denali, false); |
1224 | 1222 | ||
@@ -1330,7 +1328,7 @@ static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data, | |||
1330 | uint8_t *ecc_code) | 1328 | uint8_t *ecc_code) |
1331 | { | 1329 | { |
1332 | struct denali_nand_info *denali = mtd_to_denali(mtd); | 1330 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
1333 | dev_err(&denali->dev->dev, | 1331 | dev_err(denali->dev, |
1334 | "denali_ecc_calculate called unexpectedly\n"); | 1332 | "denali_ecc_calculate called unexpectedly\n"); |
1335 | BUG(); | 1333 | BUG(); |
1336 | return -EIO; | 1334 | return -EIO; |
@@ -1340,7 +1338,7 @@ static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data, | |||
1340 | uint8_t *read_ecc, uint8_t *calc_ecc) | 1338 | uint8_t *read_ecc, uint8_t *calc_ecc) |
1341 | { | 1339 | { |
1342 | struct denali_nand_info *denali = mtd_to_denali(mtd); | 1340 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
1343 | dev_err(&denali->dev->dev, | 1341 | dev_err(denali->dev, |
1344 | "denali_ecc_correct called unexpectedly\n"); | 1342 | "denali_ecc_correct called unexpectedly\n"); |
1345 | BUG(); | 1343 | BUG(); |
1346 | return -EIO; | 1344 | return -EIO; |
@@ -1349,7 +1347,7 @@ static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data, | |||
1349 | static void denali_ecc_hwctl(struct mtd_info *mtd, int mode) | 1347 | static void denali_ecc_hwctl(struct mtd_info *mtd, int mode) |
1350 | { | 1348 | { |
1351 | struct denali_nand_info *denali = mtd_to_denali(mtd); | 1349 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
1352 | dev_err(&denali->dev->dev, | 1350 | dev_err(denali->dev, |
1353 | "denali_ecc_hwctl called unexpectedly\n"); | 1351 | "denali_ecc_hwctl called unexpectedly\n"); |
1354 | BUG(); | 1352 | BUG(); |
1355 | } | 1353 | } |
@@ -1484,24 +1482,22 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |||
1484 | } | 1482 | } |
1485 | 1483 | ||
1486 | /* Is 32-bit DMA supported? */ | 1484 | /* Is 32-bit DMA supported? */ |
1487 | ret = pci_set_dma_mask(dev, DMA_BIT_MASK(32)); | 1485 | ret = dma_set_mask(&dev->dev, DMA_BIT_MASK(32)); |
1488 | |||
1489 | if (ret) { | 1486 | if (ret) { |
1490 | printk(KERN_ERR "Spectra: no usable DMA configuration\n"); | 1487 | printk(KERN_ERR "Spectra: no usable DMA configuration\n"); |
1491 | goto failed_enable_dev; | 1488 | goto failed_enable_dev; |
1492 | } | 1489 | } |
1493 | denali->buf.dma_buf = | 1490 | denali->buf.dma_buf = dma_map_single(&dev->dev, denali->buf.buf, |
1494 | pci_map_single(dev, denali->buf.buf, | 1491 | DENALI_BUF_SIZE, |
1495 | DENALI_BUF_SIZE, | 1492 | DMA_BIDIRECTIONAL); |
1496 | PCI_DMA_BIDIRECTIONAL); | ||
1497 | 1493 | ||
1498 | if (pci_dma_mapping_error(dev, denali->buf.dma_buf)) { | 1494 | if (dma_mapping_error(&dev->dev, denali->buf.dma_buf)) { |
1499 | dev_err(&dev->dev, "Spectra: failed to map DMA buffer\n"); | 1495 | dev_err(&dev->dev, "Spectra: failed to map DMA buffer\n"); |
1500 | goto failed_enable_dev; | 1496 | goto failed_enable_dev; |
1501 | } | 1497 | } |
1502 | 1498 | ||
1503 | pci_set_master(dev); | 1499 | pci_set_master(dev); |
1504 | denali->dev = dev; | 1500 | denali->dev = &dev->dev; |
1505 | denali->mtd.dev.parent = &dev->dev; | 1501 | denali->mtd.dev.parent = &dev->dev; |
1506 | 1502 | ||
1507 | ret = pci_request_regions(dev, DENALI_NAND_NAME); | 1503 | ret = pci_request_regions(dev, DENALI_NAND_NAME); |
@@ -1681,8 +1677,8 @@ failed_remap_reg: | |||
1681 | failed_req_regions: | 1677 | failed_req_regions: |
1682 | pci_release_regions(dev); | 1678 | pci_release_regions(dev); |
1683 | failed_dma_map: | 1679 | failed_dma_map: |
1684 | pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE, | 1680 | dma_unmap_single(&dev->dev, denali->buf.dma_buf, DENALI_BUF_SIZE, |
1685 | PCI_DMA_BIDIRECTIONAL); | 1681 | DMA_BIDIRECTIONAL); |
1686 | failed_enable_dev: | 1682 | failed_enable_dev: |
1687 | pci_disable_device(dev); | 1683 | pci_disable_device(dev); |
1688 | failed_alloc_memery: | 1684 | failed_alloc_memery: |
@@ -1704,8 +1700,8 @@ static void denali_pci_remove(struct pci_dev *dev) | |||
1704 | iounmap(denali->flash_mem); | 1700 | iounmap(denali->flash_mem); |
1705 | pci_release_regions(dev); | 1701 | pci_release_regions(dev); |
1706 | pci_disable_device(dev); | 1702 | pci_disable_device(dev); |
1707 | pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE, | 1703 | dma_unmap_single(&dev->dev, denali->buf.dma_buf, DENALI_BUF_SIZE, |
1708 | PCI_DMA_BIDIRECTIONAL); | 1704 | DMA_BIDIRECTIONAL); |
1709 | pci_set_drvdata(dev, NULL); | 1705 | pci_set_drvdata(dev, NULL); |
1710 | kfree(denali); | 1706 | kfree(denali); |
1711 | } | 1707 | } |
diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index 3918bcb1561e..9b875fd23687 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h | |||
@@ -732,7 +732,7 @@ struct denali_nand_info { | |||
732 | int status; | 732 | int status; |
733 | int platform; | 733 | int platform; |
734 | struct nand_buf buf; | 734 | struct nand_buf buf; |
735 | struct pci_dev *dev; | 735 | struct device *dev; |
736 | int total_used_banks; | 736 | int total_used_banks; |
737 | uint32_t block; /* stored for future use */ | 737 | uint32_t block; /* stored for future use */ |
738 | uint16_t page; | 738 | uint16_t page; |