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-rw-r--r--drivers/clk/ux500/clk-prcc.c1
-rw-r--r--drivers/clk/ux500/u8500_clk.c142
-rw-r--r--drivers/clocksource/clksrc-dbx500-prcmu.c3
-rw-r--r--drivers/crypto/ux500/cryp/cryp.c2
-rw-r--r--drivers/crypto/ux500/cryp/cryp_core.c1
-rw-r--r--drivers/crypto/ux500/hash/hash_core.c1
-rw-r--r--drivers/mfd/db8500-prcmu.c316
-rw-r--r--drivers/mfd/dbx500-prcmu-regs.h204
-rw-r--r--drivers/staging/ste_rmi4/Makefile1
-rw-r--r--drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c31
-rw-r--r--drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c31
-rw-r--r--drivers/staging/ste_rmi4/synaptics_i2c_rmi4.h1
12 files changed, 330 insertions, 404 deletions
diff --git a/drivers/clk/ux500/clk-prcc.c b/drivers/clk/ux500/clk-prcc.c
index 7eee7f768355..bd4769a84485 100644
--- a/drivers/clk/ux500/clk-prcc.c
+++ b/drivers/clk/ux500/clk-prcc.c
@@ -13,7 +13,6 @@
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/err.h> 14#include <linux/err.h>
15#include <linux/types.h> 15#include <linux/types.h>
16#include <mach/hardware.h>
17 16
18#include "clk.h" 17#include "clk.h"
19 18
diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
index 6b889a0e90b3..0c9b83d98f11 100644
--- a/drivers/clk/ux500/u8500_clk.c
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -12,10 +12,10 @@
12#include <linux/clk-provider.h> 12#include <linux/clk-provider.h>
13#include <linux/mfd/dbx500-prcmu.h> 13#include <linux/mfd/dbx500-prcmu.h>
14#include <linux/platform_data/clk-ux500.h> 14#include <linux/platform_data/clk-ux500.h>
15#include <mach/db8500-regs.h>
16#include "clk.h" 15#include "clk.h"
17 16
18void u8500_clk_init(void) 17void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
18 u32 clkrst5_base, u32 clkrst6_base)
19{ 19{
20 struct prcmu_fw_version *fw_version; 20 struct prcmu_fw_version *fw_version;
21 const char *sgaclk_parent = NULL; 21 const char *sgaclk_parent = NULL;
@@ -215,147 +215,147 @@ void u8500_clk_init(void)
215 */ 215 */
216 216
217 /* PRCC P-clocks */ 217 /* PRCC P-clocks */
218 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", U8500_CLKRST1_BASE, 218 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base,
219 BIT(0), 0); 219 BIT(0), 0);
220 clk_register_clkdev(clk, "apb_pclk", "uart0"); 220 clk_register_clkdev(clk, "apb_pclk", "uart0");
221 221
222 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", U8500_CLKRST1_BASE, 222 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base,
223 BIT(1), 0); 223 BIT(1), 0);
224 clk_register_clkdev(clk, "apb_pclk", "uart1"); 224 clk_register_clkdev(clk, "apb_pclk", "uart1");
225 225
226 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", U8500_CLKRST1_BASE, 226 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base,
227 BIT(2), 0); 227 BIT(2), 0);
228 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1"); 228 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1");
229 229
230 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", U8500_CLKRST1_BASE, 230 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base,
231 BIT(3), 0); 231 BIT(3), 0);
232 clk_register_clkdev(clk, "apb_pclk", "msp0"); 232 clk_register_clkdev(clk, "apb_pclk", "msp0");
233 clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.0"); 233 clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.0");
234 234
235 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", U8500_CLKRST1_BASE, 235 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base,
236 BIT(4), 0); 236 BIT(4), 0);
237 clk_register_clkdev(clk, "apb_pclk", "msp1"); 237 clk_register_clkdev(clk, "apb_pclk", "msp1");
238 clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.1"); 238 clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.1");
239 239
240 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", U8500_CLKRST1_BASE, 240 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base,
241 BIT(5), 0); 241 BIT(5), 0);
242 clk_register_clkdev(clk, "apb_pclk", "sdi0"); 242 clk_register_clkdev(clk, "apb_pclk", "sdi0");
243 243
244 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", U8500_CLKRST1_BASE, 244 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base,
245 BIT(6), 0); 245 BIT(6), 0);
246 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2"); 246 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2");
247 247
248 clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", U8500_CLKRST1_BASE, 248 clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base,
249 BIT(7), 0); 249 BIT(7), 0);
250 clk_register_clkdev(clk, NULL, "spi3"); 250 clk_register_clkdev(clk, NULL, "spi3");
251 251
252 clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", U8500_CLKRST1_BASE, 252 clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base,
253 BIT(8), 0); 253 BIT(8), 0);
254 clk_register_clkdev(clk, "apb_pclk", "slimbus0"); 254 clk_register_clkdev(clk, "apb_pclk", "slimbus0");
255 255
256 clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", U8500_CLKRST1_BASE, 256 clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base,
257 BIT(9), 0); 257 BIT(9), 0);
258 clk_register_clkdev(clk, NULL, "gpio.0"); 258 clk_register_clkdev(clk, NULL, "gpio.0");
259 clk_register_clkdev(clk, NULL, "gpio.1"); 259 clk_register_clkdev(clk, NULL, "gpio.1");
260 clk_register_clkdev(clk, NULL, "gpioblock0"); 260 clk_register_clkdev(clk, NULL, "gpioblock0");
261 261
262 clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", U8500_CLKRST1_BASE, 262 clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base,
263 BIT(10), 0); 263 BIT(10), 0);
264 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4"); 264 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4");
265 265
266 clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", U8500_CLKRST1_BASE, 266 clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base,
267 BIT(11), 0); 267 BIT(11), 0);
268 clk_register_clkdev(clk, "apb_pclk", "msp3"); 268 clk_register_clkdev(clk, "apb_pclk", "msp3");
269 clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.3"); 269 clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.3");
270 270
271 clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", U8500_CLKRST2_BASE, 271 clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base,
272 BIT(0), 0); 272 BIT(0), 0);
273 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3"); 273 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3");
274 274
275 clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", U8500_CLKRST2_BASE, 275 clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base,
276 BIT(1), 0); 276 BIT(1), 0);
277 clk_register_clkdev(clk, NULL, "spi2"); 277 clk_register_clkdev(clk, NULL, "spi2");
278 278
279 clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", U8500_CLKRST2_BASE, 279 clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base,
280 BIT(2), 0); 280 BIT(2), 0);
281 clk_register_clkdev(clk, NULL, "spi1"); 281 clk_register_clkdev(clk, NULL, "spi1");
282 282
283 clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", U8500_CLKRST2_BASE, 283 clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base,
284 BIT(3), 0); 284 BIT(3), 0);
285 clk_register_clkdev(clk, NULL, "pwl"); 285 clk_register_clkdev(clk, NULL, "pwl");
286 286
287 clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", U8500_CLKRST2_BASE, 287 clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base,
288 BIT(4), 0); 288 BIT(4), 0);
289 clk_register_clkdev(clk, "apb_pclk", "sdi4"); 289 clk_register_clkdev(clk, "apb_pclk", "sdi4");
290 290
291 clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", U8500_CLKRST2_BASE, 291 clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base,
292 BIT(5), 0); 292 BIT(5), 0);
293 clk_register_clkdev(clk, "apb_pclk", "msp2"); 293 clk_register_clkdev(clk, "apb_pclk", "msp2");
294 clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.2"); 294 clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.2");
295 295
296 clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", U8500_CLKRST2_BASE, 296 clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base,
297 BIT(6), 0); 297 BIT(6), 0);
298 clk_register_clkdev(clk, "apb_pclk", "sdi1"); 298 clk_register_clkdev(clk, "apb_pclk", "sdi1");
299 299
300 clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", U8500_CLKRST2_BASE, 300 clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base,
301 BIT(7), 0); 301 BIT(7), 0);
302 clk_register_clkdev(clk, "apb_pclk", "sdi3"); 302 clk_register_clkdev(clk, "apb_pclk", "sdi3");
303 303
304 clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", U8500_CLKRST2_BASE, 304 clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base,
305 BIT(8), 0); 305 BIT(8), 0);
306 clk_register_clkdev(clk, NULL, "spi0"); 306 clk_register_clkdev(clk, NULL, "spi0");
307 307
308 clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", U8500_CLKRST2_BASE, 308 clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base,
309 BIT(9), 0); 309 BIT(9), 0);
310 clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0"); 310 clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0");
311 311
312 clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", U8500_CLKRST2_BASE, 312 clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base,
313 BIT(10), 0); 313 BIT(10), 0);
314 clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0"); 314 clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0");
315 315
316 clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", U8500_CLKRST2_BASE, 316 clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base,
317 BIT(11), 0); 317 BIT(11), 0);
318 clk_register_clkdev(clk, NULL, "gpio.6"); 318 clk_register_clkdev(clk, NULL, "gpio.6");
319 clk_register_clkdev(clk, NULL, "gpio.7"); 319 clk_register_clkdev(clk, NULL, "gpio.7");
320 clk_register_clkdev(clk, NULL, "gpioblock1"); 320 clk_register_clkdev(clk, NULL, "gpioblock1");
321 321
322 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", U8500_CLKRST2_BASE, 322 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base,
323 BIT(12), 0); 323 BIT(12), 0);
324 324
325 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE, 325 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
326 BIT(0), 0); 326 BIT(0), 0);
327 clk_register_clkdev(clk, NULL, "fsmc"); 327 clk_register_clkdev(clk, NULL, "fsmc");
328 328
329 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", U8500_CLKRST3_BASE, 329 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
330 BIT(1), 0); 330 BIT(1), 0);
331 clk_register_clkdev(clk, "apb_pclk", "ssp0"); 331 clk_register_clkdev(clk, "apb_pclk", "ssp0");
332 332
333 clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", U8500_CLKRST3_BASE, 333 clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base,
334 BIT(2), 0); 334 BIT(2), 0);
335 clk_register_clkdev(clk, "apb_pclk", "ssp1"); 335 clk_register_clkdev(clk, "apb_pclk", "ssp1");
336 336
337 clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", U8500_CLKRST3_BASE, 337 clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base,
338 BIT(3), 0); 338 BIT(3), 0);
339 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0"); 339 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0");
340 340
341 clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", U8500_CLKRST3_BASE, 341 clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base,
342 BIT(4), 0); 342 BIT(4), 0);
343 clk_register_clkdev(clk, "apb_pclk", "sdi2"); 343 clk_register_clkdev(clk, "apb_pclk", "sdi2");
344 344
345 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", U8500_CLKRST3_BASE, 345 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base,
346 BIT(5), 0); 346 BIT(5), 0);
347 clk_register_clkdev(clk, "apb_pclk", "ske"); 347 clk_register_clkdev(clk, "apb_pclk", "ske");
348 clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad"); 348 clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad");
349 349
350 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", U8500_CLKRST3_BASE, 350 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base,
351 BIT(6), 0); 351 BIT(6), 0);
352 clk_register_clkdev(clk, "apb_pclk", "uart2"); 352 clk_register_clkdev(clk, "apb_pclk", "uart2");
353 353
354 clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", U8500_CLKRST3_BASE, 354 clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base,
355 BIT(7), 0); 355 BIT(7), 0);
356 clk_register_clkdev(clk, "apb_pclk", "sdi5"); 356 clk_register_clkdev(clk, "apb_pclk", "sdi5");
357 357
358 clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", U8500_CLKRST3_BASE, 358 clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base,
359 BIT(8), 0); 359 BIT(8), 0);
360 clk_register_clkdev(clk, NULL, "gpio.2"); 360 clk_register_clkdev(clk, NULL, "gpio.2");
361 clk_register_clkdev(clk, NULL, "gpio.3"); 361 clk_register_clkdev(clk, NULL, "gpio.3");
@@ -363,45 +363,45 @@ void u8500_clk_init(void)
363 clk_register_clkdev(clk, NULL, "gpio.5"); 363 clk_register_clkdev(clk, NULL, "gpio.5");
364 clk_register_clkdev(clk, NULL, "gpioblock2"); 364 clk_register_clkdev(clk, NULL, "gpioblock2");
365 365
366 clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", U8500_CLKRST5_BASE, 366 clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base,
367 BIT(0), 0); 367 BIT(0), 0);
368 clk_register_clkdev(clk, "usb", "musb-ux500.0"); 368 clk_register_clkdev(clk, "usb", "musb-ux500.0");
369 369
370 clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", U8500_CLKRST5_BASE, 370 clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base,
371 BIT(1), 0); 371 BIT(1), 0);
372 clk_register_clkdev(clk, NULL, "gpio.8"); 372 clk_register_clkdev(clk, NULL, "gpio.8");
373 clk_register_clkdev(clk, NULL, "gpioblock3"); 373 clk_register_clkdev(clk, NULL, "gpioblock3");
374 374
375 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", U8500_CLKRST6_BASE, 375 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base,
376 BIT(0), 0); 376 BIT(0), 0);
377 clk_register_clkdev(clk, "apb_pclk", "rng"); 377 clk_register_clkdev(clk, "apb_pclk", "rng");
378 378
379 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", U8500_CLKRST6_BASE, 379 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base,
380 BIT(1), 0); 380 BIT(1), 0);
381 clk_register_clkdev(clk, NULL, "cryp0"); 381 clk_register_clkdev(clk, NULL, "cryp0");
382 clk_register_clkdev(clk, NULL, "cryp1"); 382 clk_register_clkdev(clk, NULL, "cryp1");
383 383
384 clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", U8500_CLKRST6_BASE, 384 clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base,
385 BIT(2), 0); 385 BIT(2), 0);
386 clk_register_clkdev(clk, NULL, "hash0"); 386 clk_register_clkdev(clk, NULL, "hash0");
387 387
388 clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", U8500_CLKRST6_BASE, 388 clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base,
389 BIT(3), 0); 389 BIT(3), 0);
390 clk_register_clkdev(clk, NULL, "pka"); 390 clk_register_clkdev(clk, NULL, "pka");
391 391
392 clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", U8500_CLKRST6_BASE, 392 clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base,
393 BIT(4), 0); 393 BIT(4), 0);
394 clk_register_clkdev(clk, NULL, "hash1"); 394 clk_register_clkdev(clk, NULL, "hash1");
395 395
396 clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", U8500_CLKRST6_BASE, 396 clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base,
397 BIT(5), 0); 397 BIT(5), 0);
398 clk_register_clkdev(clk, NULL, "cfgreg"); 398 clk_register_clkdev(clk, NULL, "cfgreg");
399 399
400 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", U8500_CLKRST6_BASE, 400 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base,
401 BIT(6), 0); 401 BIT(6), 0);
402 clk_register_clkdev(clk, "apb_pclk", "mtu0"); 402 clk_register_clkdev(clk, "apb_pclk", "mtu0");
403 403
404 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", U8500_CLKRST6_BASE, 404 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base,
405 BIT(7), 0); 405 BIT(7), 0);
406 clk_register_clkdev(clk, "apb_pclk", "mtu1"); 406 clk_register_clkdev(clk, "apb_pclk", "mtu1");
407 407
@@ -415,110 +415,110 @@ void u8500_clk_init(void)
415 415
416 /* Periph1 */ 416 /* Periph1 */
417 clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk", 417 clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
418 U8500_CLKRST1_BASE, BIT(0), CLK_SET_RATE_GATE); 418 clkrst1_base, BIT(0), CLK_SET_RATE_GATE);
419 clk_register_clkdev(clk, NULL, "uart0"); 419 clk_register_clkdev(clk, NULL, "uart0");
420 420
421 clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk", 421 clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
422 U8500_CLKRST1_BASE, BIT(1), CLK_SET_RATE_GATE); 422 clkrst1_base, BIT(1), CLK_SET_RATE_GATE);
423 clk_register_clkdev(clk, NULL, "uart1"); 423 clk_register_clkdev(clk, NULL, "uart1");
424 424
425 clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk", 425 clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
426 U8500_CLKRST1_BASE, BIT(2), CLK_SET_RATE_GATE); 426 clkrst1_base, BIT(2), CLK_SET_RATE_GATE);
427 clk_register_clkdev(clk, NULL, "nmk-i2c.1"); 427 clk_register_clkdev(clk, NULL, "nmk-i2c.1");
428 428
429 clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk", 429 clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
430 U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE); 430 clkrst1_base, BIT(3), CLK_SET_RATE_GATE);
431 clk_register_clkdev(clk, NULL, "msp0"); 431 clk_register_clkdev(clk, NULL, "msp0");
432 clk_register_clkdev(clk, NULL, "ux500-msp-i2s.0"); 432 clk_register_clkdev(clk, NULL, "ux500-msp-i2s.0");
433 433
434 clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk", 434 clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
435 U8500_CLKRST1_BASE, BIT(4), CLK_SET_RATE_GATE); 435 clkrst1_base, BIT(4), CLK_SET_RATE_GATE);
436 clk_register_clkdev(clk, NULL, "msp1"); 436 clk_register_clkdev(clk, NULL, "msp1");
437 clk_register_clkdev(clk, NULL, "ux500-msp-i2s.1"); 437 clk_register_clkdev(clk, NULL, "ux500-msp-i2s.1");
438 438
439 clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk", 439 clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
440 U8500_CLKRST1_BASE, BIT(5), CLK_SET_RATE_GATE); 440 clkrst1_base, BIT(5), CLK_SET_RATE_GATE);
441 clk_register_clkdev(clk, NULL, "sdi0"); 441 clk_register_clkdev(clk, NULL, "sdi0");
442 442
443 clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk", 443 clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
444 U8500_CLKRST1_BASE, BIT(6), CLK_SET_RATE_GATE); 444 clkrst1_base, BIT(6), CLK_SET_RATE_GATE);
445 clk_register_clkdev(clk, NULL, "nmk-i2c.2"); 445 clk_register_clkdev(clk, NULL, "nmk-i2c.2");
446 446
447 clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", 447 clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
448 U8500_CLKRST1_BASE, BIT(8), CLK_SET_RATE_GATE); 448 clkrst1_base, BIT(8), CLK_SET_RATE_GATE);
449 clk_register_clkdev(clk, NULL, "slimbus0"); 449 clk_register_clkdev(clk, NULL, "slimbus0");
450 450
451 clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", 451 clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
452 U8500_CLKRST1_BASE, BIT(9), CLK_SET_RATE_GATE); 452 clkrst1_base, BIT(9), CLK_SET_RATE_GATE);
453 clk_register_clkdev(clk, NULL, "nmk-i2c.4"); 453 clk_register_clkdev(clk, NULL, "nmk-i2c.4");
454 454
455 clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk", 455 clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
456 U8500_CLKRST1_BASE, BIT(10), CLK_SET_RATE_GATE); 456 clkrst1_base, BIT(10), CLK_SET_RATE_GATE);
457 clk_register_clkdev(clk, NULL, "msp3"); 457 clk_register_clkdev(clk, NULL, "msp3");
458 clk_register_clkdev(clk, NULL, "ux500-msp-i2s.3"); 458 clk_register_clkdev(clk, NULL, "ux500-msp-i2s.3");
459 459
460 /* Periph2 */ 460 /* Periph2 */
461 clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk", 461 clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
462 U8500_CLKRST2_BASE, BIT(0), CLK_SET_RATE_GATE); 462 clkrst2_base, BIT(0), CLK_SET_RATE_GATE);
463 clk_register_clkdev(clk, NULL, "nmk-i2c.3"); 463 clk_register_clkdev(clk, NULL, "nmk-i2c.3");
464 464
465 clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk", 465 clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
466 U8500_CLKRST2_BASE, BIT(2), CLK_SET_RATE_GATE); 466 clkrst2_base, BIT(2), CLK_SET_RATE_GATE);
467 clk_register_clkdev(clk, NULL, "sdi4"); 467 clk_register_clkdev(clk, NULL, "sdi4");
468 468
469 clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk", 469 clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
470 U8500_CLKRST2_BASE, BIT(3), CLK_SET_RATE_GATE); 470 clkrst2_base, BIT(3), CLK_SET_RATE_GATE);
471 clk_register_clkdev(clk, NULL, "msp2"); 471 clk_register_clkdev(clk, NULL, "msp2");
472 clk_register_clkdev(clk, NULL, "ux500-msp-i2s.2"); 472 clk_register_clkdev(clk, NULL, "ux500-msp-i2s.2");
473 473
474 clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk", 474 clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
475 U8500_CLKRST2_BASE, BIT(4), CLK_SET_RATE_GATE); 475 clkrst2_base, BIT(4), CLK_SET_RATE_GATE);
476 clk_register_clkdev(clk, NULL, "sdi1"); 476 clk_register_clkdev(clk, NULL, "sdi1");
477 477
478 clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk", 478 clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
479 U8500_CLKRST2_BASE, BIT(5), CLK_SET_RATE_GATE); 479 clkrst2_base, BIT(5), CLK_SET_RATE_GATE);
480 clk_register_clkdev(clk, NULL, "sdi3"); 480 clk_register_clkdev(clk, NULL, "sdi3");
481 481
482 /* Note that rate is received from parent. */ 482 /* Note that rate is received from parent. */
483 clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk", 483 clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
484 U8500_CLKRST2_BASE, BIT(6), 484 clkrst2_base, BIT(6),
485 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); 485 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
486 clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk", 486 clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
487 U8500_CLKRST2_BASE, BIT(7), 487 clkrst2_base, BIT(7),
488 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); 488 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
489 489
490 /* Periph3 */ 490 /* Periph3 */
491 clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk", 491 clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
492 U8500_CLKRST3_BASE, BIT(1), CLK_SET_RATE_GATE); 492 clkrst3_base, BIT(1), CLK_SET_RATE_GATE);
493 clk_register_clkdev(clk, NULL, "ssp0"); 493 clk_register_clkdev(clk, NULL, "ssp0");
494 494
495 clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk", 495 clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
496 U8500_CLKRST3_BASE, BIT(2), CLK_SET_RATE_GATE); 496 clkrst3_base, BIT(2), CLK_SET_RATE_GATE);
497 clk_register_clkdev(clk, NULL, "ssp1"); 497 clk_register_clkdev(clk, NULL, "ssp1");
498 498
499 clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk", 499 clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
500 U8500_CLKRST3_BASE, BIT(3), CLK_SET_RATE_GATE); 500 clkrst3_base, BIT(3), CLK_SET_RATE_GATE);
501 clk_register_clkdev(clk, NULL, "nmk-i2c.0"); 501 clk_register_clkdev(clk, NULL, "nmk-i2c.0");
502 502
503 clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk", 503 clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
504 U8500_CLKRST3_BASE, BIT(4), CLK_SET_RATE_GATE); 504 clkrst3_base, BIT(4), CLK_SET_RATE_GATE);
505 clk_register_clkdev(clk, NULL, "sdi2"); 505 clk_register_clkdev(clk, NULL, "sdi2");
506 506
507 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k", 507 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
508 U8500_CLKRST3_BASE, BIT(5), CLK_SET_RATE_GATE); 508 clkrst3_base, BIT(5), CLK_SET_RATE_GATE);
509 clk_register_clkdev(clk, NULL, "ske"); 509 clk_register_clkdev(clk, NULL, "ske");
510 clk_register_clkdev(clk, NULL, "nmk-ske-keypad"); 510 clk_register_clkdev(clk, NULL, "nmk-ske-keypad");
511 511
512 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk", 512 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
513 U8500_CLKRST3_BASE, BIT(6), CLK_SET_RATE_GATE); 513 clkrst3_base, BIT(6), CLK_SET_RATE_GATE);
514 clk_register_clkdev(clk, NULL, "uart2"); 514 clk_register_clkdev(clk, NULL, "uart2");
515 515
516 clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk", 516 clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
517 U8500_CLKRST3_BASE, BIT(7), CLK_SET_RATE_GATE); 517 clkrst3_base, BIT(7), CLK_SET_RATE_GATE);
518 clk_register_clkdev(clk, NULL, "sdi5"); 518 clk_register_clkdev(clk, NULL, "sdi5");
519 519
520 /* Periph6 */ 520 /* Periph6 */
521 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk", 521 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
522 U8500_CLKRST6_BASE, BIT(0), CLK_SET_RATE_GATE); 522 clkrst6_base, BIT(0), CLK_SET_RATE_GATE);
523 clk_register_clkdev(clk, NULL, "rng"); 523 clk_register_clkdev(clk, NULL, "rng");
524} 524}
diff --git a/drivers/clocksource/clksrc-dbx500-prcmu.c b/drivers/clocksource/clksrc-dbx500-prcmu.c
index c26c369eb9e6..54f3d119d99c 100644
--- a/drivers/clocksource/clksrc-dbx500-prcmu.c
+++ b/drivers/clocksource/clksrc-dbx500-prcmu.c
@@ -17,9 +17,6 @@
17 17
18#include <asm/sched_clock.h> 18#include <asm/sched_clock.h>
19 19
20#include <mach/setup.h>
21#include <mach/hardware.h>
22
23#define RATE_32K 32768 20#define RATE_32K 32768
24 21
25#define TIMER_MODE_CONTINOUS 0x1 22#define TIMER_MODE_CONTINOUS 0x1
diff --git a/drivers/crypto/ux500/cryp/cryp.c b/drivers/crypto/ux500/cryp/cryp.c
index e208ceaf81c9..3eafa903ebcd 100644
--- a/drivers/crypto/ux500/cryp/cryp.c
+++ b/drivers/crypto/ux500/cryp/cryp.c
@@ -12,8 +12,6 @@
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/types.h> 13#include <linux/types.h>
14 14
15#include <mach/hardware.h>
16
17#include "cryp_p.h" 15#include "cryp_p.h"
18#include "cryp.h" 16#include "cryp.h"
19 17
diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c
index 8bc5fef07e7a..2809b19e3add 100644
--- a/drivers/crypto/ux500/cryp/cryp_core.c
+++ b/drivers/crypto/ux500/cryp/cryp_core.c
@@ -32,7 +32,6 @@
32#include <crypto/scatterwalk.h> 32#include <crypto/scatterwalk.h>
33 33
34#include <linux/platform_data/crypto-ux500.h> 34#include <linux/platform_data/crypto-ux500.h>
35#include <mach/hardware.h>
36 35
37#include "cryp_p.h" 36#include "cryp_p.h"
38#include "cryp.h" 37#include "cryp.h"
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index 632c3339895f..1827e9f1f873 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -32,7 +32,6 @@
32#include <crypto/algapi.h> 32#include <crypto/algapi.h>
33 33
34#include <linux/platform_data/crypto-ux500.h> 34#include <linux/platform_data/crypto-ux500.h>
35#include <mach/hardware.h>
36 35
37#include "hash_alg.h" 36#include "hash_alg.h"
38 37
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 21f261bf9e95..21434beb420a 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -26,7 +26,6 @@
26#include <linux/fs.h> 26#include <linux/fs.h>
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/uaccess.h> 28#include <linux/uaccess.h>
29#include <linux/irqchip/arm-gic.h>
30#include <linux/mfd/core.h> 29#include <linux/mfd/core.h>
31#include <linux/mfd/dbx500-prcmu.h> 30#include <linux/mfd/dbx500-prcmu.h>
32#include <linux/mfd/abx500/ab8500.h> 31#include <linux/mfd/abx500/ab8500.h>
@@ -34,9 +33,7 @@
34#include <linux/regulator/machine.h> 33#include <linux/regulator/machine.h>
35#include <linux/cpufreq.h> 34#include <linux/cpufreq.h>
36#include <linux/platform_data/ux500_wdt.h> 35#include <linux/platform_data/ux500_wdt.h>
37#include <mach/hardware.h> 36#include <linux/platform_data/db8500_thermal.h>
38#include <mach/irqs.h>
39#include <mach/db8500-regs.h>
40#include "dbx500-prcmu-regs.h" 37#include "dbx500-prcmu-regs.h"
41 38
42/* Index of different voltages to be used when accessing AVSData */ 39/* Index of different voltages to be used when accessing AVSData */
@@ -276,8 +273,34 @@ static struct irq_domain *db8500_irq_domain;
276 * the bits in the bit field are not. (The bits also have a tendency to move 273 * the bits in the bit field are not. (The bits also have a tendency to move
277 * around, to further complicate matters.) 274 * around, to further complicate matters.)
278 */ 275 */
279#define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE) 276#define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name))
280#define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name) 277#define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
278
279#define IRQ_PRCMU_RTC 0
280#define IRQ_PRCMU_RTT0 1
281#define IRQ_PRCMU_RTT1 2
282#define IRQ_PRCMU_HSI0 3
283#define IRQ_PRCMU_HSI1 4
284#define IRQ_PRCMU_CA_WAKE 5
285#define IRQ_PRCMU_USB 6
286#define IRQ_PRCMU_ABB 7
287#define IRQ_PRCMU_ABB_FIFO 8
288#define IRQ_PRCMU_ARM 9
289#define IRQ_PRCMU_MODEM_SW_RESET_REQ 10
290#define IRQ_PRCMU_GPIO0 11
291#define IRQ_PRCMU_GPIO1 12
292#define IRQ_PRCMU_GPIO2 13
293#define IRQ_PRCMU_GPIO3 14
294#define IRQ_PRCMU_GPIO4 15
295#define IRQ_PRCMU_GPIO5 16
296#define IRQ_PRCMU_GPIO6 17
297#define IRQ_PRCMU_GPIO7 18
298#define IRQ_PRCMU_GPIO8 19
299#define IRQ_PRCMU_CA_SLEEP 20
300#define IRQ_PRCMU_HOTMON_LOW 21
301#define IRQ_PRCMU_HOTMON_HIGH 22
302#define NUM_PRCMU_WAKEUPS 23
303
281static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = { 304static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
282 IRQ_ENTRY(RTC), 305 IRQ_ENTRY(RTC),
283 IRQ_ENTRY(RTT0), 306 IRQ_ENTRY(RTT0),
@@ -422,9 +445,10 @@ static DEFINE_SPINLOCK(clkout_lock);
422 445
423/* Global var to runtime determine TCDM base for v2 or v1 */ 446/* Global var to runtime determine TCDM base for v2 or v1 */
424static __iomem void *tcdm_base; 447static __iomem void *tcdm_base;
448static __iomem void *prcmu_base;
425 449
426struct clk_mgt { 450struct clk_mgt {
427 void __iomem *reg; 451 u32 offset;
428 u32 pllsw; 452 u32 pllsw;
429 int branch; 453 int branch;
430 bool clk38div; 454 bool clk38div;
@@ -599,9 +623,9 @@ int db8500_prcmu_set_display_clocks(void)
599 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 623 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
600 cpu_relax(); 624 cpu_relax();
601 625
602 writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT); 626 writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT);
603 writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT); 627 writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT);
604 writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT); 628 writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT);
605 629
606 /* Release the HW semaphore. */ 630 /* Release the HW semaphore. */
607 writel(0, PRCM_SEM); 631 writel(0, PRCM_SEM);
@@ -613,7 +637,7 @@ int db8500_prcmu_set_display_clocks(void)
613 637
614u32 db8500_prcmu_read(unsigned int reg) 638u32 db8500_prcmu_read(unsigned int reg)
615{ 639{
616 return readl(_PRCMU_BASE + reg); 640 return readl(prcmu_base + reg);
617} 641}
618 642
619void db8500_prcmu_write(unsigned int reg, u32 value) 643void db8500_prcmu_write(unsigned int reg, u32 value)
@@ -621,7 +645,7 @@ void db8500_prcmu_write(unsigned int reg, u32 value)
621 unsigned long flags; 645 unsigned long flags;
622 646
623 spin_lock_irqsave(&prcmu_lock, flags); 647 spin_lock_irqsave(&prcmu_lock, flags);
624 writel(value, (_PRCMU_BASE + reg)); 648 writel(value, (prcmu_base + reg));
625 spin_unlock_irqrestore(&prcmu_lock, flags); 649 spin_unlock_irqrestore(&prcmu_lock, flags);
626} 650}
627 651
@@ -631,9 +655,9 @@ void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
631 unsigned long flags; 655 unsigned long flags;
632 656
633 spin_lock_irqsave(&prcmu_lock, flags); 657 spin_lock_irqsave(&prcmu_lock, flags);
634 val = readl(_PRCMU_BASE + reg); 658 val = readl(prcmu_base + reg);
635 val = ((val & ~mask) | (value & mask)); 659 val = ((val & ~mask) | (value & mask));
636 writel(val, (_PRCMU_BASE + reg)); 660 writel(val, (prcmu_base + reg));
637 spin_unlock_irqrestore(&prcmu_lock, flags); 661 spin_unlock_irqrestore(&prcmu_lock, flags);
638} 662}
639 663
@@ -793,119 +817,6 @@ u8 db8500_prcmu_get_power_state_result(void)
793 return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS); 817 return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
794} 818}
795 819
796/* This function decouple the gic from the prcmu */
797int db8500_prcmu_gic_decouple(void)
798{
799 u32 val = readl(PRCM_A9_MASK_REQ);
800
801 /* Set bit 0 register value to 1 */
802 writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
803 PRCM_A9_MASK_REQ);
804
805 /* Make sure the register is updated */
806 readl(PRCM_A9_MASK_REQ);
807
808 /* Wait a few cycles for the gic mask completion */
809 udelay(1);
810
811 return 0;
812}
813
814/* This function recouple the gic with the prcmu */
815int db8500_prcmu_gic_recouple(void)
816{
817 u32 val = readl(PRCM_A9_MASK_REQ);
818
819 /* Set bit 0 register value to 0 */
820 writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);
821
822 return 0;
823}
824
825#define PRCMU_GIC_NUMBER_REGS 5
826
827/*
828 * This function checks if there are pending irq on the gic. It only
829 * makes sense if the gic has been decoupled before with the
830 * db8500_prcmu_gic_decouple function. Disabling an interrupt only
831 * disables the forwarding of the interrupt to any CPU interface. It
832 * does not prevent the interrupt from changing state, for example
833 * becoming pending, or active and pending if it is already
834 * active. Hence, we have to check the interrupt is pending *and* is
835 * active.
836 */
837bool db8500_prcmu_gic_pending_irq(void)
838{
839 u32 pr; /* Pending register */
840 u32 er; /* Enable register */
841 void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
842 int i;
843
844 /* 5 registers. STI & PPI not skipped */
845 for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {
846
847 pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4);
848 er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
849
850 if (pr & er)
851 return true; /* There is a pending interrupt */
852 }
853
854 return false;
855}
856
857/*
858 * This function checks if there are pending interrupt on the
859 * prcmu which has been delegated to monitor the irqs with the
860 * db8500_prcmu_copy_gic_settings function.
861 */
862bool db8500_prcmu_pending_irq(void)
863{
864 u32 it, im;
865 int i;
866
867 for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
868 it = readl(PRCM_ARMITVAL31TO0 + i * 4);
869 im = readl(PRCM_ARMITMSK31TO0 + i * 4);
870 if (it & im)
871 return true; /* There is a pending interrupt */
872 }
873
874 return false;
875}
876
877/*
878 * This function checks if the specified cpu is in in WFI. It's usage
879 * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
880 * function. Of course passing smp_processor_id() to this function will
881 * always return false...
882 */
883bool db8500_prcmu_is_cpu_in_wfi(int cpu)
884{
885 return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 :
886 PRCM_ARM_WFI_STANDBY_WFI0;
887}
888
889/*
890 * This function copies the gic SPI settings to the prcmu in order to
891 * monitor them and abort/finish the retention/off sequence or state.
892 */
893int db8500_prcmu_copy_gic_settings(void)
894{
895 u32 er; /* Enable register */
896 void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
897 int i;
898
899 /* We skip the STI and PPI */
900 for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
901 er = readl_relaxed(dist_base +
902 GIC_DIST_ENABLE_SET + (i + 1) * 4);
903 writel(er, PRCM_ARMITMSK31TO0 + i * 4);
904 }
905
906 return 0;
907}
908
909/* This function should only be called while mb0_transfer.lock is held. */ 820/* This function should only be called while mb0_transfer.lock is held. */
910static void config_wakeups(void) 821static void config_wakeups(void)
911{ 822{
@@ -1059,7 +970,7 @@ int db8500_prcmu_set_ddr_opp(u8 opp)
1059/* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */ 970/* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
1060static void request_even_slower_clocks(bool enable) 971static void request_even_slower_clocks(bool enable)
1061{ 972{
1062 void __iomem *clock_reg[] = { 973 u32 clock_reg[] = {
1063 PRCM_ACLK_MGT, 974 PRCM_ACLK_MGT,
1064 PRCM_DMACLK_MGT 975 PRCM_DMACLK_MGT
1065 }; 976 };
@@ -1076,7 +987,7 @@ static void request_even_slower_clocks(bool enable)
1076 u32 val; 987 u32 val;
1077 u32 div; 988 u32 div;
1078 989
1079 val = readl(clock_reg[i]); 990 val = readl(prcmu_base + clock_reg[i]);
1080 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK); 991 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
1081 if (enable) { 992 if (enable) {
1082 if ((div <= 1) || (div > 15)) { 993 if ((div <= 1) || (div > 15)) {
@@ -1092,7 +1003,7 @@ static void request_even_slower_clocks(bool enable)
1092 } 1003 }
1093 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) | 1004 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
1094 (div & PRCM_CLK_MGT_CLKPLLDIV_MASK)); 1005 (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
1095 writel(val, clock_reg[i]); 1006 writel(val, prcmu_base + clock_reg[i]);
1096 } 1007 }
1097 1008
1098unlock_and_return: 1009unlock_and_return:
@@ -1446,14 +1357,14 @@ static int request_clock(u8 clock, bool enable)
1446 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 1357 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1447 cpu_relax(); 1358 cpu_relax();
1448 1359
1449 val = readl(clk_mgt[clock].reg); 1360 val = readl(prcmu_base + clk_mgt[clock].offset);
1450 if (enable) { 1361 if (enable) {
1451 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); 1362 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1452 } else { 1363 } else {
1453 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); 1364 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1454 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); 1365 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1455 } 1366 }
1456 writel(val, clk_mgt[clock].reg); 1367 writel(val, prcmu_base + clk_mgt[clock].offset);
1457 1368
1458 /* Release the HW semaphore. */ 1369 /* Release the HW semaphore. */
1459 writel(0, PRCM_SEM); 1370 writel(0, PRCM_SEM);
@@ -1629,7 +1540,7 @@ static unsigned long clock_rate(u8 clock)
1629 u32 pllsw; 1540 u32 pllsw;
1630 unsigned long rate = ROOT_CLOCK_RATE; 1541 unsigned long rate = ROOT_CLOCK_RATE;
1631 1542
1632 val = readl(clk_mgt[clock].reg); 1543 val = readl(prcmu_base + clk_mgt[clock].offset);
1633 1544
1634 if (val & PRCM_CLK_MGT_CLK38) { 1545 if (val & PRCM_CLK_MGT_CLK38) {
1635 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV)) 1546 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
@@ -1785,7 +1696,7 @@ static long round_clock_rate(u8 clock, unsigned long rate)
1785 unsigned long src_rate; 1696 unsigned long src_rate;
1786 long rounded_rate; 1697 long rounded_rate;
1787 1698
1788 val = readl(clk_mgt[clock].reg); 1699 val = readl(prcmu_base + clk_mgt[clock].offset);
1789 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), 1700 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1790 clk_mgt[clock].branch); 1701 clk_mgt[clock].branch);
1791 div = clock_divider(src_rate, rate); 1702 div = clock_divider(src_rate, rate);
@@ -1933,7 +1844,7 @@ static void set_clock_rate(u8 clock, unsigned long rate)
1933 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) 1844 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1934 cpu_relax(); 1845 cpu_relax();
1935 1846
1936 val = readl(clk_mgt[clock].reg); 1847 val = readl(prcmu_base + clk_mgt[clock].offset);
1937 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), 1848 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1938 clk_mgt[clock].branch); 1849 clk_mgt[clock].branch);
1939 div = clock_divider(src_rate, rate); 1850 div = clock_divider(src_rate, rate);
@@ -1961,7 +1872,7 @@ static void set_clock_rate(u8 clock, unsigned long rate)
1961 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK; 1872 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1962 val |= min(div, (u32)31); 1873 val |= min(div, (u32)31);
1963 } 1874 }
1964 writel(val, clk_mgt[clock].reg); 1875 writel(val, prcmu_base + clk_mgt[clock].offset);
1965 1876
1966 /* Release the HW semaphore. */ 1877 /* Release the HW semaphore. */
1967 writel(0, PRCM_SEM); 1878 writel(0, PRCM_SEM);
@@ -2764,14 +2675,13 @@ static struct irq_domain_ops db8500_irq_ops = {
2764 .xlate = irq_domain_xlate_twocell, 2675 .xlate = irq_domain_xlate_twocell,
2765}; 2676};
2766 2677
2767static int db8500_irq_init(struct device_node *np) 2678static int db8500_irq_init(struct device_node *np, int irq_base)
2768{ 2679{
2769 int irq_base = 0;
2770 int i; 2680 int i;
2771 2681
2772 /* In the device tree case, just take some IRQs */ 2682 /* In the device tree case, just take some IRQs */
2773 if (!np) 2683 if (np)
2774 irq_base = IRQ_PRCMU_BASE; 2684 irq_base = 0;
2775 2685
2776 db8500_irq_domain = irq_domain_add_simple( 2686 db8500_irq_domain = irq_domain_add_simple(
2777 np, NUM_PRCMU_WAKEUPS, irq_base, 2687 np, NUM_PRCMU_WAKEUPS, irq_base,
@@ -2825,8 +2735,19 @@ static void dbx500_fw_version_init(struct platform_device *pdev,
2825 } 2735 }
2826} 2736}
2827 2737
2828void __init db8500_prcmu_early_init(void) 2738void __init db8500_prcmu_early_init(u32 phy_base, u32 size)
2829{ 2739{
2740 /*
2741 * This is a temporary remap to bring up the clocks. It is
2742 * subsequently replaces with a real remap. After the merge of
2743 * the mailbox subsystem all of this early code goes away, and the
2744 * clock driver can probe independently. An early initcall will
2745 * still be needed, but it can be diverted into drivers/clk/ux500.
2746 */
2747 prcmu_base = ioremap(phy_base, size);
2748 if (!prcmu_base)
2749 pr_err("%s: ioremap() of prcmu registers failed!\n", __func__);
2750
2830 spin_lock_init(&mb0_transfer.lock); 2751 spin_lock_init(&mb0_transfer.lock);
2831 spin_lock_init(&mb0_transfer.dbb_irqs_lock); 2752 spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2832 mutex_init(&mb0_transfer.ac_wake_lock); 2753 mutex_init(&mb0_transfer.ac_wake_lock);
@@ -3092,18 +3013,57 @@ static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
3092 }, 3013 },
3093}; 3014};
3094 3015
3095static struct resource ab8500_resources[] = {
3096 [0] = {
3097 .start = IRQ_DB8500_AB8500,
3098 .end = IRQ_DB8500_AB8500,
3099 .flags = IORESOURCE_IRQ
3100 }
3101};
3102
3103static struct ux500_wdt_data db8500_wdt_pdata = { 3016static struct ux500_wdt_data db8500_wdt_pdata = {
3104 .timeout = 600, /* 10 minutes */ 3017 .timeout = 600, /* 10 minutes */
3105 .has_28_bits_resolution = true, 3018 .has_28_bits_resolution = true,
3106}; 3019};
3020/*
3021 * Thermal Sensor
3022 */
3023
3024static struct resource db8500_thsens_resources[] = {
3025 {
3026 .name = "IRQ_HOTMON_LOW",
3027 .start = IRQ_PRCMU_HOTMON_LOW,
3028 .end = IRQ_PRCMU_HOTMON_LOW,
3029 .flags = IORESOURCE_IRQ,
3030 },
3031 {
3032 .name = "IRQ_HOTMON_HIGH",
3033 .start = IRQ_PRCMU_HOTMON_HIGH,
3034 .end = IRQ_PRCMU_HOTMON_HIGH,
3035 .flags = IORESOURCE_IRQ,
3036 },
3037};
3038
3039static struct db8500_thsens_platform_data db8500_thsens_data = {
3040 .trip_points[0] = {
3041 .temp = 70000,
3042 .type = THERMAL_TRIP_ACTIVE,
3043 .cdev_name = {
3044 [0] = "thermal-cpufreq-0",
3045 },
3046 },
3047 .trip_points[1] = {
3048 .temp = 75000,
3049 .type = THERMAL_TRIP_ACTIVE,
3050 .cdev_name = {
3051 [0] = "thermal-cpufreq-0",
3052 },
3053 },
3054 .trip_points[2] = {
3055 .temp = 80000,
3056 .type = THERMAL_TRIP_ACTIVE,
3057 .cdev_name = {
3058 [0] = "thermal-cpufreq-0",
3059 },
3060 },
3061 .trip_points[3] = {
3062 .temp = 85000,
3063 .type = THERMAL_TRIP_CRITICAL,
3064 },
3065 .num_trips = 4,
3066};
3107 3067
3108static struct mfd_cell db8500_prcmu_devs[] = { 3068static struct mfd_cell db8500_prcmu_devs[] = {
3109 { 3069 {
@@ -3125,11 +3085,10 @@ static struct mfd_cell db8500_prcmu_devs[] = {
3125 .id = -1, 3085 .id = -1,
3126 }, 3086 },
3127 { 3087 {
3128 .name = "ab8500-core", 3088 .name = "db8500-thermal",
3129 .of_compatible = "stericsson,ab8500", 3089 .num_resources = ARRAY_SIZE(db8500_thsens_resources),
3130 .num_resources = ARRAY_SIZE(ab8500_resources), 3090 .resources = db8500_thsens_resources,
3131 .resources = ab8500_resources, 3091 .platform_data = &db8500_thsens_data,
3132 .id = AB8500_VERSION_AB8500,
3133 }, 3092 },
3134}; 3093};
3135 3094
@@ -3141,6 +3100,24 @@ static void db8500_prcmu_update_cpufreq(void)
3141 } 3100 }
3142} 3101}
3143 3102
3103static int db8500_prcmu_register_ab8500(struct device *parent,
3104 struct ab8500_platform_data *pdata,
3105 int irq)
3106{
3107 struct resource ab8500_resource = DEFINE_RES_IRQ(irq);
3108 struct mfd_cell ab8500_cell = {
3109 .name = "ab8500-core",
3110 .of_compatible = "stericsson,ab8500",
3111 .id = AB8500_VERSION_AB8500,
3112 .platform_data = pdata,
3113 .pdata_size = sizeof(struct ab8500_platform_data),
3114 .resources = &ab8500_resource,
3115 .num_resources = 1,
3116 };
3117
3118 return mfd_add_devices(parent, 0, &ab8500_cell, 1, NULL, 0, NULL);
3119}
3120
3144/** 3121/**
3145 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic 3122 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
3146 * 3123 *
@@ -3149,11 +3126,21 @@ static int db8500_prcmu_probe(struct platform_device *pdev)
3149{ 3126{
3150 struct device_node *np = pdev->dev.of_node; 3127 struct device_node *np = pdev->dev.of_node;
3151 struct prcmu_pdata *pdata = dev_get_platdata(&pdev->dev); 3128 struct prcmu_pdata *pdata = dev_get_platdata(&pdev->dev);
3152 int irq = 0, err = 0, i; 3129 int irq = 0, err = 0;
3153 struct resource *res; 3130 struct resource *res;
3154 3131
3132 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu");
3133 if (!res) {
3134 dev_err(&pdev->dev, "no prcmu memory region provided\n");
3135 return -ENOENT;
3136 }
3137 prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
3138 if (!prcmu_base) {
3139 dev_err(&pdev->dev,
3140 "failed to ioremap prcmu register memory\n");
3141 return -ENOENT;
3142 }
3155 init_prcm_registers(); 3143 init_prcm_registers();
3156
3157 dbx500_fw_version_init(pdev, pdata->version_offset); 3144 dbx500_fw_version_init(pdev, pdata->version_offset);
3158 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm"); 3145 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm");
3159 if (!res) { 3146 if (!res) {
@@ -3180,26 +3167,27 @@ static int db8500_prcmu_probe(struct platform_device *pdev)
3180 goto no_irq_return; 3167 goto no_irq_return;
3181 } 3168 }
3182 3169
3183 db8500_irq_init(np); 3170 db8500_irq_init(np, pdata->irq_base);
3184
3185 for (i = 0; i < ARRAY_SIZE(db8500_prcmu_devs); i++) {
3186 if (!strcmp(db8500_prcmu_devs[i].name, "ab8500-core")) {
3187 db8500_prcmu_devs[i].platform_data = pdata->ab_platdata;
3188 db8500_prcmu_devs[i].pdata_size = sizeof(struct ab8500_platform_data);
3189 }
3190 }
3191 3171
3192 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); 3172 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3193 3173
3194 db8500_prcmu_update_cpufreq(); 3174 db8500_prcmu_update_cpufreq();
3195 3175
3196 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, 3176 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
3197 ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, NULL); 3177 ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, db8500_irq_domain);
3198 if (err) { 3178 if (err) {
3199 pr_err("prcmu: Failed to add subdevices\n"); 3179 pr_err("prcmu: Failed to add subdevices\n");
3200 return err; 3180 return err;
3201 } 3181 }
3202 3182
3183 err = db8500_prcmu_register_ab8500(&pdev->dev, pdata->ab_platdata,
3184 pdata->ab_irq);
3185 if (err) {
3186 mfd_remove_devices(&pdev->dev);
3187 pr_err("prcmu: Failed to add ab8500 subdevice\n");
3188 goto no_irq_return;
3189 }
3190
3203 pr_info("DB8500 PRCMU initialized\n"); 3191 pr_info("DB8500 PRCMU initialized\n");
3204 3192
3205no_irq_return: 3193no_irq_return:
diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h
index 79c76ebdba52..d14836ed2114 100644
--- a/drivers/mfd/dbx500-prcmu-regs.h
+++ b/drivers/mfd/dbx500-prcmu-regs.h
@@ -13,136 +13,110 @@
13#ifndef __DB8500_PRCMU_REGS_H 13#ifndef __DB8500_PRCMU_REGS_H
14#define __DB8500_PRCMU_REGS_H 14#define __DB8500_PRCMU_REGS_H
15 15
16#include <mach/hardware.h>
17
18#define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end)) 16#define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
19 17
20#define PRCM_CLK_MGT(_offset) (void __iomem *)(IO_ADDRESS(U8500_PRCMU_BASE) \ 18#define PRCM_ACLK_MGT (0x004)
21 + _offset) 19#define PRCM_SVACLK_MGT (0x008)
22#define PRCM_ACLK_MGT PRCM_CLK_MGT(0x004) 20#define PRCM_SIACLK_MGT (0x00C)
23#define PRCM_SVACLK_MGT PRCM_CLK_MGT(0x008) 21#define PRCM_SGACLK_MGT (0x014)
24#define PRCM_SIACLK_MGT PRCM_CLK_MGT(0x00C) 22#define PRCM_UARTCLK_MGT (0x018)
25#define PRCM_SGACLK_MGT PRCM_CLK_MGT(0x014) 23#define PRCM_MSP02CLK_MGT (0x01C)
26#define PRCM_UARTCLK_MGT PRCM_CLK_MGT(0x018) 24#define PRCM_I2CCLK_MGT (0x020)
27#define PRCM_MSP02CLK_MGT PRCM_CLK_MGT(0x01C) 25#define PRCM_SDMMCCLK_MGT (0x024)
28#define PRCM_I2CCLK_MGT PRCM_CLK_MGT(0x020) 26#define PRCM_SLIMCLK_MGT (0x028)
29#define PRCM_SDMMCCLK_MGT PRCM_CLK_MGT(0x024) 27#define PRCM_PER1CLK_MGT (0x02C)
30#define PRCM_SLIMCLK_MGT PRCM_CLK_MGT(0x028) 28#define PRCM_PER2CLK_MGT (0x030)
31#define PRCM_PER1CLK_MGT PRCM_CLK_MGT(0x02C) 29#define PRCM_PER3CLK_MGT (0x034)
32#define PRCM_PER2CLK_MGT PRCM_CLK_MGT(0x030) 30#define PRCM_PER5CLK_MGT (0x038)
33#define PRCM_PER3CLK_MGT PRCM_CLK_MGT(0x034) 31#define PRCM_PER6CLK_MGT (0x03C)
34#define PRCM_PER5CLK_MGT PRCM_CLK_MGT(0x038) 32#define PRCM_PER7CLK_MGT (0x040)
35#define PRCM_PER6CLK_MGT PRCM_CLK_MGT(0x03C) 33#define PRCM_LCDCLK_MGT (0x044)
36#define PRCM_PER7CLK_MGT PRCM_CLK_MGT(0x040) 34#define PRCM_BMLCLK_MGT (0x04C)
37#define PRCM_LCDCLK_MGT PRCM_CLK_MGT(0x044) 35#define PRCM_HSITXCLK_MGT (0x050)
38#define PRCM_BMLCLK_MGT PRCM_CLK_MGT(0x04C) 36#define PRCM_HSIRXCLK_MGT (0x054)
39#define PRCM_HSITXCLK_MGT PRCM_CLK_MGT(0x050) 37#define PRCM_HDMICLK_MGT (0x058)
40#define PRCM_HSIRXCLK_MGT PRCM_CLK_MGT(0x054) 38#define PRCM_APEATCLK_MGT (0x05C)
41#define PRCM_HDMICLK_MGT PRCM_CLK_MGT(0x058) 39#define PRCM_APETRACECLK_MGT (0x060)
42#define PRCM_APEATCLK_MGT PRCM_CLK_MGT(0x05C) 40#define PRCM_MCDECLK_MGT (0x064)
43#define PRCM_APETRACECLK_MGT PRCM_CLK_MGT(0x060) 41#define PRCM_IPI2CCLK_MGT (0x068)
44#define PRCM_MCDECLK_MGT PRCM_CLK_MGT(0x064) 42#define PRCM_DSIALTCLK_MGT (0x06C)
45#define PRCM_IPI2CCLK_MGT PRCM_CLK_MGT(0x068) 43#define PRCM_DMACLK_MGT (0x074)
46#define PRCM_DSIALTCLK_MGT PRCM_CLK_MGT(0x06C) 44#define PRCM_B2R2CLK_MGT (0x078)
47#define PRCM_DMACLK_MGT PRCM_CLK_MGT(0x074) 45#define PRCM_TVCLK_MGT (0x07C)
48#define PRCM_B2R2CLK_MGT PRCM_CLK_MGT(0x078) 46#define PRCM_UNIPROCLK_MGT (0x278)
49#define PRCM_TVCLK_MGT PRCM_CLK_MGT(0x07C) 47#define PRCM_SSPCLK_MGT (0x280)
50#define PRCM_UNIPROCLK_MGT PRCM_CLK_MGT(0x278) 48#define PRCM_RNGCLK_MGT (0x284)
51#define PRCM_SSPCLK_MGT PRCM_CLK_MGT(0x280) 49#define PRCM_UICCCLK_MGT (0x27C)
52#define PRCM_RNGCLK_MGT PRCM_CLK_MGT(0x284) 50#define PRCM_MSP1CLK_MGT (0x288)
53#define PRCM_UICCCLK_MGT PRCM_CLK_MGT(0x27C) 51
54#define PRCM_MSP1CLK_MGT PRCM_CLK_MGT(0x288) 52#define PRCM_ARM_PLLDIVPS (prcmu_base + 0x118)
55
56#define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118)
57#define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE 0x3f 53#define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE 0x3f
58#define PRCM_ARM_PLLDIVPS_MAX_MASK 0xf 54#define PRCM_ARM_PLLDIVPS_MAX_MASK 0xf
59 55
60#define PRCM_PLLARM_LOCKP (_PRCMU_BASE + 0x0a8) 56#define PRCM_PLLARM_LOCKP (prcmu_base + 0x0a8)
61#define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 0x2 57#define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 0x2
62 58
63#define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114) 59#define PRCM_ARM_CHGCLKREQ (prcmu_base + 0x114)
64#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ BIT(0) 60#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ BIT(0)
65#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL BIT(16) 61#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL BIT(16)
66 62
67#define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98) 63#define PRCM_PLLARM_ENABLE (prcmu_base + 0x98)
68#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE 0x1 64#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE 0x1
69#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON 0x100 65#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON 0x100
70 66
71#define PRCM_ARMCLKFIX_MGT (_PRCMU_BASE + 0x0) 67#define PRCM_ARMCLKFIX_MGT (prcmu_base + 0x0)
72#define PRCM_A9PL_FORCE_CLKEN (_PRCMU_BASE + 0x19C) 68#define PRCM_A9PL_FORCE_CLKEN (prcmu_base + 0x19C)
73#define PRCM_A9_RESETN_CLR (_PRCMU_BASE + 0x1f4) 69#define PRCM_A9_RESETN_CLR (prcmu_base + 0x1f4)
74#define PRCM_A9_RESETN_SET (_PRCMU_BASE + 0x1f0) 70#define PRCM_A9_RESETN_SET (prcmu_base + 0x1f0)
75#define PRCM_ARM_LS_CLAMP (_PRCMU_BASE + 0x30c) 71#define PRCM_ARM_LS_CLAMP (prcmu_base + 0x30c)
76#define PRCM_SRAM_A9 (_PRCMU_BASE + 0x308) 72#define PRCM_SRAM_A9 (prcmu_base + 0x308)
77 73
78#define PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN BIT(0) 74#define PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN BIT(0)
79#define PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN BIT(1) 75#define PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN BIT(1)
80 76
81/* ARM WFI Standby signal register */
82#define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130)
83#define PRCM_ARM_WFI_STANDBY_WFI0 0x08
84#define PRCM_ARM_WFI_STANDBY_WFI1 0x10
85#define PRCM_IOCR (_PRCMU_BASE + 0x310)
86#define PRCM_IOCR_IOFORCE 0x1
87
88/* CPU mailbox registers */ 77/* CPU mailbox registers */
89#define PRCM_MBOX_CPU_VAL (_PRCMU_BASE + 0x0fc) 78#define PRCM_MBOX_CPU_VAL (prcmu_base + 0x0fc)
90#define PRCM_MBOX_CPU_SET (_PRCMU_BASE + 0x100) 79#define PRCM_MBOX_CPU_SET (prcmu_base + 0x100)
91#define PRCM_MBOX_CPU_CLR (_PRCMU_BASE + 0x104) 80#define PRCM_MBOX_CPU_CLR (prcmu_base + 0x104)
92 81
93/* Dual A9 core interrupt management unit registers */ 82#define PRCM_HOSTACCESS_REQ (prcmu_base + 0x334)
94#define PRCM_A9_MASK_REQ (_PRCMU_BASE + 0x328)
95#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1
96
97#define PRCM_A9_MASK_ACK (_PRCMU_BASE + 0x32c)
98#define PRCM_ARMITMSK31TO0 (_PRCMU_BASE + 0x11c)
99#define PRCM_ARMITMSK63TO32 (_PRCMU_BASE + 0x120)
100#define PRCM_ARMITMSK95TO64 (_PRCMU_BASE + 0x124)
101#define PRCM_ARMITMSK127TO96 (_PRCMU_BASE + 0x128)
102#define PRCM_POWER_STATE_VAL (_PRCMU_BASE + 0x25C)
103#define PRCM_ARMITVAL31TO0 (_PRCMU_BASE + 0x260)
104#define PRCM_ARMITVAL63TO32 (_PRCMU_BASE + 0x264)
105#define PRCM_ARMITVAL95TO64 (_PRCMU_BASE + 0x268)
106#define PRCM_ARMITVAL127TO96 (_PRCMU_BASE + 0x26C)
107
108#define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334)
109#define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ 0x1 83#define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ 0x1
110#define PRCM_HOSTACCESS_REQ_WAKE_REQ BIT(16) 84#define PRCM_HOSTACCESS_REQ_WAKE_REQ BIT(16)
111#define ARM_WAKEUP_MODEM 0x1 85#define ARM_WAKEUP_MODEM 0x1
112 86
113#define PRCM_ARM_IT1_CLR (_PRCMU_BASE + 0x48C) 87#define PRCM_ARM_IT1_CLR (prcmu_base + 0x48C)
114#define PRCM_ARM_IT1_VAL (_PRCMU_BASE + 0x494) 88#define PRCM_ARM_IT1_VAL (prcmu_base + 0x494)
115#define PRCM_HOLD_EVT (_PRCMU_BASE + 0x174) 89#define PRCM_HOLD_EVT (prcmu_base + 0x174)
116 90
117#define PRCM_MOD_AWAKE_STATUS (_PRCMU_BASE + 0x4A0) 91#define PRCM_MOD_AWAKE_STATUS (prcmu_base + 0x4A0)
118#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE BIT(0) 92#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE BIT(0)
119#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE BIT(1) 93#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE BIT(1)
120#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_VMODEM_OFF_ISO BIT(2) 94#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_VMODEM_OFF_ISO BIT(2)
121 95
122#define PRCM_ITSTATUS0 (_PRCMU_BASE + 0x148) 96#define PRCM_ITSTATUS0 (prcmu_base + 0x148)
123#define PRCM_ITSTATUS1 (_PRCMU_BASE + 0x150) 97#define PRCM_ITSTATUS1 (prcmu_base + 0x150)
124#define PRCM_ITSTATUS2 (_PRCMU_BASE + 0x158) 98#define PRCM_ITSTATUS2 (prcmu_base + 0x158)
125#define PRCM_ITSTATUS3 (_PRCMU_BASE + 0x160) 99#define PRCM_ITSTATUS3 (prcmu_base + 0x160)
126#define PRCM_ITSTATUS4 (_PRCMU_BASE + 0x168) 100#define PRCM_ITSTATUS4 (prcmu_base + 0x168)
127#define PRCM_ITSTATUS5 (_PRCMU_BASE + 0x484) 101#define PRCM_ITSTATUS5 (prcmu_base + 0x484)
128#define PRCM_ITCLEAR5 (_PRCMU_BASE + 0x488) 102#define PRCM_ITCLEAR5 (prcmu_base + 0x488)
129#define PRCM_ARMIT_MASKXP70_IT (_PRCMU_BASE + 0x1018) 103#define PRCM_ARMIT_MASKXP70_IT (prcmu_base + 0x1018)
130 104
131/* System reset register */ 105/* System reset register */
132#define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228) 106#define PRCM_APE_SOFTRST (prcmu_base + 0x228)
133 107
134/* Level shifter and clamp control registers */ 108/* Level shifter and clamp control registers */
135#define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420) 109#define PRCM_MMIP_LS_CLAMP_SET (prcmu_base + 0x420)
136#define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424) 110#define PRCM_MMIP_LS_CLAMP_CLR (prcmu_base + 0x424)
137 111
138#define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP BIT(11) 112#define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP BIT(11)
139#define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI BIT(22) 113#define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI BIT(22)
140 114
141/* PRCMU clock/PLL/reset registers */ 115/* PRCMU clock/PLL/reset registers */
142#define PRCM_PLLSOC0_FREQ (_PRCMU_BASE + 0x080) 116#define PRCM_PLLSOC0_FREQ (prcmu_base + 0x080)
143#define PRCM_PLLSOC1_FREQ (_PRCMU_BASE + 0x084) 117#define PRCM_PLLSOC1_FREQ (prcmu_base + 0x084)
144#define PRCM_PLLARM_FREQ (_PRCMU_BASE + 0x088) 118#define PRCM_PLLARM_FREQ (prcmu_base + 0x088)
145#define PRCM_PLLDDR_FREQ (_PRCMU_BASE + 0x08C) 119#define PRCM_PLLDDR_FREQ (prcmu_base + 0x08C)
146#define PRCM_PLL_FREQ_D_SHIFT 0 120#define PRCM_PLL_FREQ_D_SHIFT 0
147#define PRCM_PLL_FREQ_D_MASK BITS(0, 7) 121#define PRCM_PLL_FREQ_D_MASK BITS(0, 7)
148#define PRCM_PLL_FREQ_N_SHIFT 8 122#define PRCM_PLL_FREQ_N_SHIFT 8
@@ -152,14 +126,14 @@
152#define PRCM_PLL_FREQ_SELDIV2 BIT(24) 126#define PRCM_PLL_FREQ_SELDIV2 BIT(24)
153#define PRCM_PLL_FREQ_DIV2EN BIT(25) 127#define PRCM_PLL_FREQ_DIV2EN BIT(25)
154 128
155#define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500) 129#define PRCM_PLLDSI_FREQ (prcmu_base + 0x500)
156#define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504) 130#define PRCM_PLLDSI_ENABLE (prcmu_base + 0x504)
157#define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508) 131#define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508)
158#define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530) 132#define PRCM_DSI_PLLOUT_SEL (prcmu_base + 0x530)
159#define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C) 133#define PRCM_DSITVCLK_DIV (prcmu_base + 0x52C)
160#define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508) 134#define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508)
161#define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4) 135#define PRCM_APE_RESETN_SET (prcmu_base + 0x1E4)
162#define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8) 136#define PRCM_APE_RESETN_CLR (prcmu_base + 0x1E8)
163 137
164#define PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE BIT(0) 138#define PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE BIT(0)
165 139
@@ -188,30 +162,30 @@
188 162
189#define PRCM_APE_RESETN_DSIPLL_RESETN BIT(14) 163#define PRCM_APE_RESETN_DSIPLL_RESETN BIT(14)
190 164
191#define PRCM_CLKOCR (_PRCMU_BASE + 0x1CC) 165#define PRCM_CLKOCR (prcmu_base + 0x1CC)
192#define PRCM_CLKOCR_CLKOUT0_REF_CLK (1 << 0) 166#define PRCM_CLKOCR_CLKOUT0_REF_CLK (1 << 0)
193#define PRCM_CLKOCR_CLKOUT0_MASK BITS(0, 13) 167#define PRCM_CLKOCR_CLKOUT0_MASK BITS(0, 13)
194#define PRCM_CLKOCR_CLKOUT1_REF_CLK (1 << 16) 168#define PRCM_CLKOCR_CLKOUT1_REF_CLK (1 << 16)
195#define PRCM_CLKOCR_CLKOUT1_MASK BITS(16, 29) 169#define PRCM_CLKOCR_CLKOUT1_MASK BITS(16, 29)
196 170
197/* ePOD and memory power signal control registers */ 171/* ePOD and memory power signal control registers */
198#define PRCM_EPOD_C_SET (_PRCMU_BASE + 0x410) 172#define PRCM_EPOD_C_SET (prcmu_base + 0x410)
199#define PRCM_SRAM_LS_SLEEP (_PRCMU_BASE + 0x304) 173#define PRCM_SRAM_LS_SLEEP (prcmu_base + 0x304)
200 174
201/* Debug power control unit registers */ 175/* Debug power control unit registers */
202#define PRCM_POWER_STATE_SET (_PRCMU_BASE + 0x254) 176#define PRCM_POWER_STATE_SET (prcmu_base + 0x254)
203 177
204/* Miscellaneous unit registers */ 178/* Miscellaneous unit registers */
205#define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324) 179#define PRCM_DSI_SW_RESET (prcmu_base + 0x324)
206#define PRCM_GPIOCR (_PRCMU_BASE + 0x138) 180#define PRCM_GPIOCR (prcmu_base + 0x138)
207#define PRCM_GPIOCR_DBG_STM_MOD_CMD1 0x800 181#define PRCM_GPIOCR_DBG_STM_MOD_CMD1 0x800
208#define PRCM_GPIOCR_DBG_UARTMOD_CMD0 0x1 182#define PRCM_GPIOCR_DBG_UARTMOD_CMD0 0x1
209 183
210/* PRCMU HW semaphore */ 184/* PRCMU HW semaphore */
211#define PRCM_SEM (_PRCMU_BASE + 0x400) 185#define PRCM_SEM (prcmu_base + 0x400)
212#define PRCM_SEM_PRCM_SEM BIT(0) 186#define PRCM_SEM_PRCM_SEM BIT(0)
213 187
214#define PRCM_TCR (_PRCMU_BASE + 0x1C8) 188#define PRCM_TCR (prcmu_base + 0x1C8)
215#define PRCM_TCR_TENSEL_MASK BITS(0, 7) 189#define PRCM_TCR_TENSEL_MASK BITS(0, 7)
216#define PRCM_TCR_STOP_TIMERS BIT(16) 190#define PRCM_TCR_STOP_TIMERS BIT(16)
217#define PRCM_TCR_DOZE_MODE BIT(17) 191#define PRCM_TCR_DOZE_MODE BIT(17)
@@ -239,15 +213,15 @@
239/* GPIOCR register */ 213/* GPIOCR register */
240#define PRCM_GPIOCR_SPI2_SELECT BIT(23) 214#define PRCM_GPIOCR_SPI2_SELECT BIT(23)
241 215
242#define PRCM_DDR_SUBSYS_APE_MINBW (_PRCMU_BASE + 0x438) 216#define PRCM_DDR_SUBSYS_APE_MINBW (prcmu_base + 0x438)
243#define PRCM_CGATING_BYPASS (_PRCMU_BASE + 0x134) 217#define PRCM_CGATING_BYPASS (prcmu_base + 0x134)
244#define PRCM_CGATING_BYPASS_ICN2 BIT(6) 218#define PRCM_CGATING_BYPASS_ICN2 BIT(6)
245 219
246/* Miscellaneous unit registers */ 220/* Miscellaneous unit registers */
247#define PRCM_RESOUTN_SET (_PRCMU_BASE + 0x214) 221#define PRCM_RESOUTN_SET (prcmu_base + 0x214)
248#define PRCM_RESOUTN_CLR (_PRCMU_BASE + 0x218) 222#define PRCM_RESOUTN_CLR (prcmu_base + 0x218)
249 223
250/* System reset register */ 224/* System reset register */
251#define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228) 225#define PRCM_APE_SOFTRST (prcmu_base + 0x228)
252 226
253#endif /* __DB8500_PRCMU_REGS_H */ 227#endif /* __DB8500_PRCMU_REGS_H */
diff --git a/drivers/staging/ste_rmi4/Makefile b/drivers/staging/ste_rmi4/Makefile
index e4c03351420f..6cce2ed187ef 100644
--- a/drivers/staging/ste_rmi4/Makefile
+++ b/drivers/staging/ste_rmi4/Makefile
@@ -2,4 +2,3 @@
2# Makefile for the RMI4 touchscreen driver. 2# Makefile for the RMI4 touchscreen driver.
3# 3#
4obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4) += synaptics_i2c_rmi4.o 4obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4) += synaptics_i2c_rmi4.o
5obj-$(CONFIG_MACH_MOP500) += board-mop500-u8500uib-rmi4.o
diff --git a/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c b/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c
deleted file mode 100644
index 47439c3f7258..000000000000
--- a/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * Some platform data for the RMI4 touchscreen that will override the __weak
3 * platform data in the Ux500 machine if this driver is activated.
4 */
5#include <linux/i2c.h>
6#include <linux/gpio.h>
7#include <linux/interrupt.h>
8#include <mach/irqs.h>
9#include "synaptics_i2c_rmi4.h"
10
11/*
12 * Synaptics RMI4 touchscreen interface on the U8500 UIB
13 */
14
15/*
16 * Descriptor structure.
17 * Describes the number of i2c devices on the bus that speak RMI.
18 */
19static struct synaptics_rmi4_platform_data rmi4_i2c_dev_platformdata = {
20 .irq_number = NOMADIK_GPIO_TO_IRQ(84),
21 .irq_type = (IRQF_TRIGGER_FALLING | IRQF_SHARED),
22 .x_flip = false,
23 .y_flip = true,
24};
25
26struct i2c_board_info __initdata mop500_i2c3_devices_u8500[] = {
27 {
28 I2C_BOARD_INFO("synaptics_rmi4_i2c", 0x4B),
29 .platform_data = &rmi4_i2c_dev_platformdata,
30 },
31};
diff --git a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
index 6a21f67af086..2e3530736bc0 100644
--- a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
+++ b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c
@@ -864,6 +864,16 @@ static int synaptics_rmi4_i2c_query_device(struct synaptics_rmi4_data *pdata)
864 return 0; 864 return 0;
865} 865}
866 866
867/*
868 * Descriptor structure.
869 * Describes the number of i2c devices on the bus that speak RMI.
870 */
871static struct synaptics_rmi4_platform_data synaptics_rmi4_platformdata = {
872 .irq_type = (IRQF_TRIGGER_FALLING | IRQF_SHARED),
873 .x_flip = false,
874 .y_flip = true,
875};
876
867/** 877/**
868 * synaptics_rmi4_probe() - Initialze the i2c-client touchscreen driver 878 * synaptics_rmi4_probe() - Initialze the i2c-client touchscreen driver
869 * @i2c: i2c client structure pointer 879 * @i2c: i2c client structure pointer
@@ -890,10 +900,8 @@ static int synaptics_rmi4_probe
890 return -EIO; 900 return -EIO;
891 } 901 }
892 902
893 if (!platformdata) { 903 if (!platformdata)
894 dev_err(&client->dev, "%s: no platform data\n", __func__); 904 platformdata = &synaptics_rmi4_platformdata;
895 return -EINVAL;
896 }
897 905
898 /* Allocate and initialize the instance data for this client */ 906 /* Allocate and initialize the instance data for this client */
899 rmi4_data = kcalloc(2, sizeof(struct synaptics_rmi4_data), 907 rmi4_data = kcalloc(2, sizeof(struct synaptics_rmi4_data),
@@ -977,13 +985,13 @@ static int synaptics_rmi4_probe
977 synaptics_rmi4_i2c_block_read(rmi4_data, 985 synaptics_rmi4_i2c_block_read(rmi4_data,
978 rmi4_data->fn01_data_base_addr + 1, intr_status, 986 rmi4_data->fn01_data_base_addr + 1, intr_status,
979 rmi4_data->number_of_interrupt_register); 987 rmi4_data->number_of_interrupt_register);
980 retval = request_threaded_irq(platformdata->irq_number, NULL, 988 retval = request_threaded_irq(client->irq, NULL,
981 synaptics_rmi4_irq, 989 synaptics_rmi4_irq,
982 platformdata->irq_type, 990 platformdata->irq_type,
983 DRIVER_NAME, rmi4_data); 991 DRIVER_NAME, rmi4_data);
984 if (retval) { 992 if (retval) {
985 dev_err(&client->dev, "%s:Unable to get attn irq %d\n", 993 dev_err(&client->dev, "%s:Unable to get attn irq %d\n",
986 __func__, platformdata->irq_number); 994 __func__, client->irq);
987 goto err_query_dev; 995 goto err_query_dev;
988 } 996 }
989 997
@@ -996,7 +1004,7 @@ static int synaptics_rmi4_probe
996 return retval; 1004 return retval;
997 1005
998err_free_irq: 1006err_free_irq:
999 free_irq(platformdata->irq_number, rmi4_data); 1007 free_irq(client->irq, rmi4_data);
1000err_query_dev: 1008err_query_dev:
1001 regulator_disable(rmi4_data->regulator); 1009 regulator_disable(rmi4_data->regulator);
1002err_regulator_enable: 1010err_regulator_enable:
@@ -1019,11 +1027,10 @@ err_input:
1019static int synaptics_rmi4_remove(struct i2c_client *client) 1027static int synaptics_rmi4_remove(struct i2c_client *client)
1020{ 1028{
1021 struct synaptics_rmi4_data *rmi4_data = i2c_get_clientdata(client); 1029 struct synaptics_rmi4_data *rmi4_data = i2c_get_clientdata(client);
1022 const struct synaptics_rmi4_platform_data *pdata = rmi4_data->board;
1023 1030
1024 rmi4_data->touch_stopped = true; 1031 rmi4_data->touch_stopped = true;
1025 wake_up(&rmi4_data->wait); 1032 wake_up(&rmi4_data->wait);
1026 free_irq(pdata->irq_number, rmi4_data); 1033 free_irq(client->irq, rmi4_data);
1027 input_unregister_device(rmi4_data->input_dev); 1034 input_unregister_device(rmi4_data->input_dev);
1028 regulator_disable(rmi4_data->regulator); 1035 regulator_disable(rmi4_data->regulator);
1029 regulator_put(rmi4_data->regulator); 1036 regulator_put(rmi4_data->regulator);
@@ -1046,10 +1053,9 @@ static int synaptics_rmi4_suspend(struct device *dev)
1046 int retval; 1053 int retval;
1047 unsigned char intr_status; 1054 unsigned char intr_status;
1048 struct synaptics_rmi4_data *rmi4_data = dev_get_drvdata(dev); 1055 struct synaptics_rmi4_data *rmi4_data = dev_get_drvdata(dev);
1049 const struct synaptics_rmi4_platform_data *pdata = rmi4_data->board;
1050 1056
1051 rmi4_data->touch_stopped = true; 1057 rmi4_data->touch_stopped = true;
1052 disable_irq(pdata->irq_number); 1058 disable_irq(rmi4_data->i2c_client->irq);
1053 1059
1054 retval = synaptics_rmi4_i2c_block_read(rmi4_data, 1060 retval = synaptics_rmi4_i2c_block_read(rmi4_data,
1055 rmi4_data->fn01_data_base_addr + 1, 1061 rmi4_data->fn01_data_base_addr + 1,
@@ -1080,11 +1086,10 @@ static int synaptics_rmi4_resume(struct device *dev)
1080 int retval; 1086 int retval;
1081 unsigned char intr_status; 1087 unsigned char intr_status;
1082 struct synaptics_rmi4_data *rmi4_data = dev_get_drvdata(dev); 1088 struct synaptics_rmi4_data *rmi4_data = dev_get_drvdata(dev);
1083 const struct synaptics_rmi4_platform_data *pdata = rmi4_data->board;
1084 1089
1085 regulator_enable(rmi4_data->regulator); 1090 regulator_enable(rmi4_data->regulator);
1086 1091
1087 enable_irq(pdata->irq_number); 1092 enable_irq(rmi4_data->i2c_client->irq);
1088 rmi4_data->touch_stopped = false; 1093 rmi4_data->touch_stopped = false;
1089 1094
1090 retval = synaptics_rmi4_i2c_block_read(rmi4_data, 1095 retval = synaptics_rmi4_i2c_block_read(rmi4_data,
diff --git a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.h b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.h
index 384436ef8068..8c9166ba71c7 100644
--- a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.h
+++ b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.h
@@ -38,7 +38,6 @@
38 * This structure gives platform data for rmi4. 38 * This structure gives platform data for rmi4.
39 */ 39 */
40struct synaptics_rmi4_platform_data { 40struct synaptics_rmi4_platform_data {
41 int irq_number;
42 int irq_type; 41 int irq_type;
43 bool x_flip; 42 bool x_flip;
44 bool y_flip; 43 bool y_flip;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 10:13:33 -0500