133 files changed, 7831 insertions, 3100 deletions

diff --git a/drivers/atm/ambassador.c b/drivers/atm/ambassador.c
index ffe9b655292e..9f47e8625266 100644
--- a/drivers/atm/ambassador.c
+++ b/drivers/atm/ambassador.c
@@ -1926,8 +1926,9 @@ static int __devinit ucode_init (loader_block * lb, amb_dev * dev) {
   const struct firmware *fw;
   unsigned long start_address;
   const struct ihex_binrec *rec;
+  const char *errmsg = 0;
   int res;
-  
+
   res = request_ihex_firmware(&fw, "atmsar11.fw", &dev->pci_dev->dev);
   if (res) {
     PRINTK (KERN_ERR, "Cannot load microcode data");
@@ -1937,8 +1938,8 @@ static int __devinit ucode_init (loader_block * lb, amb_dev * dev) {
   /* First record contains just the start address */
   rec = (const struct ihex_binrec *)fw->data;
   if (be16_to_cpu(rec->len) != sizeof(__be32) || be32_to_cpu(rec->addr)) {
-    PRINTK (KERN_ERR, "Bad microcode data (no start record)");
-    return -EINVAL;
+    errmsg = "no start record";
+    goto fail;
   }
   start_address = be32_to_cpup((__be32 *)rec->data);
 
@@ -1950,12 +1951,12 @@ static int __devinit ucode_init (loader_block * lb, amb_dev * dev) {
     PRINTD (DBG_LOAD, "starting region (%x, %u)", be32_to_cpu(rec->addr),
             be16_to_cpu(rec->len));
     if (be16_to_cpu(rec->len) > 4 * MAX_TRANSFER_DATA) {
-            PRINTK (KERN_ERR, "Bad microcode data (record too long)");
-            return -EINVAL;
+            errmsg = "record too long";
+            goto fail;
     }
     if (be16_to_cpu(rec->len) & 3) {
-            PRINTK (KERN_ERR, "Bad microcode data (odd number of bytes)");
-            return -EINVAL;
+            errmsg = "odd number of bytes";
+            goto fail;
     }
     res = loader_write(lb, dev, rec);
     if (res)
@@ -1970,6 +1971,10 @@ static int __devinit ucode_init (loader_block * lb, amb_dev * dev) {
     res = loader_start(lb, dev, start_address);
 
   return res;
+fail:
+  release_firmware(fw);
+  PRINTK(KERN_ERR, "Bad microcode data (%s)", errmsg);
+  return -EINVAL;
 }
 
 /********** give adapter parameters **********/
diff --git a/drivers/char/hvc_vio.c b/drivers/char/hvc_vio.c
index 27370e99c66f..5e2f52b33327 100644
--- a/drivers/char/hvc_vio.c
+++ b/drivers/char/hvc_vio.c
@@ -39,7 +39,7 @@
 
 #include "hvc_console.h"
 
-char hvc_driver_name[] = "hvc_console";
+static const char hvc_driver_name[] = "hvc_console";
 
 static struct vio_device_id hvc_driver_table[] __devinitdata = {
         {"serial", "hvterm1"},
diff --git a/drivers/char/ipmi/ipmi_watchdog.c b/drivers/char/ipmi/ipmi_watchdog.c
index f4d334f2536e..320668f4c3aa 100644
--- a/drivers/char/ipmi/ipmi_watchdog.c
+++ b/drivers/char/ipmi/ipmi_watchdog.c
@@ -1081,7 +1081,7 @@ ipmi_nmi(struct notifier_block *self, unsigned long val, void *data)
 {
         struct die_args *args = data;
 
-        if (val != DIE_NMI)
+        if (val != DIE_NMIUNKNOWN)
                 return NOTIFY_OK;
 
         /* Hack, if it's a memory or I/O error, ignore it. */
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 6ee23592700a..ef138731c0ea 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -109,7 +109,7 @@ config FSL_DMA
 
 config MPC512X_DMA
         tristate "Freescale MPC512x built-in DMA engine support"
-        depends on PPC_MPC512x
+        depends on PPC_MPC512x || PPC_MPC831x
         select DMA_ENGINE
         ---help---
           Enable support for the Freescale MPC512x built-in DMA engine.
diff --git a/drivers/dma/mpc512x_dma.c b/drivers/dma/mpc512x_dma.c
index 4e9cbf300594..59c270192ccc 100644
--- a/drivers/dma/mpc512x_dma.c
+++ b/drivers/dma/mpc512x_dma.c
@@ -1,6 +1,7 @@
 /*
  * Copyright (C) Freescale Semicondutor, Inc. 2007, 2008.
  * Copyright (C) Semihalf 2009
+ * Copyright (C) Ilya Yanok, Emcraft Systems 2010
  *
  * Written by Piotr Ziecik <kosmo@semihalf.com>. Hardware description
  * (defines, structures and comments) was taken from MPC5121 DMA driver
@@ -70,6 +71,8 @@
 #define MPC_DMA_DMAES_SBE       (1 << 1)
 #define MPC_DMA_DMAES_DBE       (1 << 0)
 
+#define MPC_DMA_DMAGPOR_SNOOP_ENABLE    (1 << 6)
+
 #define MPC_DMA_TSIZE_1         0x00
 #define MPC_DMA_TSIZE_2         0x01
 #define MPC_DMA_TSIZE_4         0x02
@@ -104,7 +107,10 @@ struct __attribute__ ((__packed__)) mpc_dma_regs {
         /* 0x30 */
         u32 dmahrsh;            /* DMA hw request status high(ch63~32) */
         u32 dmahrsl;            /* DMA hardware request status low(ch31~0) */
-        u32 dmaihsa;            /* DMA interrupt high select AXE(ch63~32) */
+        union {
+                u32 dmaihsa;    /* DMA interrupt high select AXE(ch63~32) */
+                u32 dmagpor;    /* (General purpose register on MPC8308) */
+        };
         u32 dmailsa;            /* DMA interrupt low select AXE(ch31~0) */
         /* 0x40 ~ 0xff */
         u32 reserve0[48];       /* Reserved */
@@ -195,7 +201,9 @@ struct mpc_dma {
         struct mpc_dma_regs __iomem     *regs;
         struct mpc_dma_tcd __iomem      *tcd;
         int                             irq;
+        int                             irq2;
         uint                            error_status;
+        int                             is_mpc8308;
 
         /* Lock for error_status field in this structure */
         spinlock_t                      error_status_lock;
@@ -252,11 +260,13 @@ static void mpc_dma_execute(struct mpc_dma_chan *mchan)
                 prev = mdesc;
         }
 
-        prev->tcd->start = 0;
         prev->tcd->int_maj = 1;
 
         /* Send first descriptor in chain into hardware */
         memcpy_toio(&mdma->tcd[cid], first->tcd, sizeof(struct mpc_dma_tcd));
+
+        if (first != prev)
+                mdma->tcd[cid].e_sg = 1;
         out_8(&mdma->regs->dmassrt, cid);
 }
 
@@ -274,6 +284,9 @@ static void mpc_dma_irq_process(struct mpc_dma *mdma, u32 is, u32 es, int off)
 
                 spin_lock(&mchan->lock);
 
+                out_8(&mdma->regs->dmacint, ch + off);
+                out_8(&mdma->regs->dmacerr, ch + off);
+
                 /* Check error status */
                 if (es & (1 << ch))
                         list_for_each_entry(mdesc, &mchan->active, node)
@@ -302,36 +315,68 @@ static irqreturn_t mpc_dma_irq(int irq, void *data)
         spin_unlock(&mdma->error_status_lock);
 
         /* Handle interrupt on each channel */
-        mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmainth),
+        if (mdma->dma.chancnt > 32) {
+                mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmainth),
                                         in_be32(&mdma->regs->dmaerrh), 32);
+        }
         mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmaintl),
                                         in_be32(&mdma->regs->dmaerrl), 0);
 
-        /* Ack interrupt on all channels */
-        out_be32(&mdma->regs->dmainth, 0xFFFFFFFF);
-        out_be32(&mdma->regs->dmaintl, 0xFFFFFFFF);
-        out_be32(&mdma->regs->dmaerrh, 0xFFFFFFFF);
-        out_be32(&mdma->regs->dmaerrl, 0xFFFFFFFF);
-
         /* Schedule tasklet */
         tasklet_schedule(&mdma->tasklet);
 
         return IRQ_HANDLED;
 }
 
-/* DMA Tasklet */
-static void mpc_dma_tasklet(unsigned long data)
+/* proccess completed descriptors */
+static void mpc_dma_process_completed(struct mpc_dma *mdma)
 {
-        struct mpc_dma *mdma = (void *)data;
         dma_cookie_t last_cookie = 0;
         struct mpc_dma_chan *mchan;
         struct mpc_dma_desc *mdesc;
         struct dma_async_tx_descriptor *desc;
         unsigned long flags;
         LIST_HEAD(list);
-        uint es;
         int i;
 
+        for (i = 0; i < mdma->dma.chancnt; i++) {
+                mchan = &mdma->channels[i];
+
+                /* Get all completed descriptors */
+                spin_lock_irqsave(&mchan->lock, flags);
+                if (!list_empty(&mchan->completed))
+                        list_splice_tail_init(&mchan->completed, &list);
+                spin_unlock_irqrestore(&mchan->lock, flags);
+
+                if (list_empty(&list))
+                        continue;
+
+                /* Execute callbacks and run dependencies */
+                list_for_each_entry(mdesc, &list, node) {
+                        desc = &mdesc->desc;
+
+                        if (desc->callback)
+                                desc->callback(desc->callback_param);
+
+                        last_cookie = desc->cookie;
+                        dma_run_dependencies(desc);
+                }
+
+                /* Free descriptors */
+                spin_lock_irqsave(&mchan->lock, flags);
+                list_splice_tail_init(&list, &mchan->free);
+                mchan->completed_cookie = last_cookie;
+                spin_unlock_irqrestore(&mchan->lock, flags);
+        }
+}
+
+/* DMA Tasklet */
+static void mpc_dma_tasklet(unsigned long data)
+{
+        struct mpc_dma *mdma = (void *)data;
+        unsigned long flags;
+        uint es;
+
         spin_lock_irqsave(&mdma->error_status_lock, flags);
         es = mdma->error_status;
         mdma->error_status = 0;
@@ -370,35 +415,7 @@ static void mpc_dma_tasklet(unsigned long data)
                         dev_err(mdma->dma.dev, "- Destination Bus Error\n");
         }
 
-        for (i = 0; i < mdma->dma.chancnt; i++) {
-                mchan = &mdma->channels[i];
-
-                /* Get all completed descriptors */
-                spin_lock_irqsave(&mchan->lock, flags);
-                if (!list_empty(&mchan->completed))
-                        list_splice_tail_init(&mchan->completed, &list);
-                spin_unlock_irqrestore(&mchan->lock, flags);
-
-                if (list_empty(&list))
-                        continue;
-
-                /* Execute callbacks and run dependencies */
-                list_for_each_entry(mdesc, &list, node) {
-                        desc = &mdesc->desc;
-
-                        if (desc->callback)
-                                desc->callback(desc->callback_param);
-
-                        last_cookie = desc->cookie;
-                        dma_run_dependencies(desc);
-                }
-
-                /* Free descriptors */
-                spin_lock_irqsave(&mchan->lock, flags);
-                list_splice_tail_init(&list, &mchan->free);
-                mchan->completed_cookie = last_cookie;
-                spin_unlock_irqrestore(&mchan->lock, flags);
-        }
+        mpc_dma_process_completed(mdma);
 }
 
 /* Submit descriptor to hardware */
@@ -563,6 +580,7 @@ static struct dma_async_tx_descriptor *
 mpc_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
                                         size_t len, unsigned long flags)
 {
+        struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
         struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
         struct mpc_dma_desc *mdesc = NULL;
         struct mpc_dma_tcd *tcd;
@@ -577,8 +595,11 @@ mpc_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
         }
         spin_unlock_irqrestore(&mchan->lock, iflags);
 
-        if (!mdesc)
+        if (!mdesc) {
+                /* try to free completed descriptors */
+                mpc_dma_process_completed(mdma);
                 return NULL;
+        }
 
         mdesc->error = 0;
         tcd = mdesc->tcd;
@@ -591,7 +612,8 @@ mpc_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
                 tcd->dsize = MPC_DMA_TSIZE_32;
                 tcd->soff = 32;
                 tcd->doff = 32;
-        } else if (IS_ALIGNED(src | dst | len, 16)) {
+        } else if (!mdma->is_mpc8308 && IS_ALIGNED(src | dst | len, 16)) {
+                /* MPC8308 doesn't support 16 byte transfers */
                 tcd->ssize = MPC_DMA_TSIZE_16;
                 tcd->dsize = MPC_DMA_TSIZE_16;
                 tcd->soff = 16;
@@ -651,6 +673,15 @@ static int __devinit mpc_dma_probe(struct platform_device *op,
                 return -EINVAL;
         }
 
+        if (of_device_is_compatible(dn, "fsl,mpc8308-dma")) {
+                mdma->is_mpc8308 = 1;
+                mdma->irq2 = irq_of_parse_and_map(dn, 1);
+                if (mdma->irq2 == NO_IRQ) {
+                        dev_err(dev, "Error mapping IRQ!\n");
+                        return -EINVAL;
+                }
+        }
+
         retval = of_address_to_resource(dn, 0, &res);
         if (retval) {
                 dev_err(dev, "Error parsing memory region!\n");
@@ -681,11 +712,23 @@ static int __devinit mpc_dma_probe(struct platform_device *op,
                 return -EINVAL;
         }
 
+        if (mdma->is_mpc8308) {
+                retval = devm_request_irq(dev, mdma->irq2, &mpc_dma_irq, 0,
+                                DRV_NAME, mdma);
+                if (retval) {
+                        dev_err(dev, "Error requesting IRQ2!\n");
+                        return -EINVAL;
+                }
+        }
+
         spin_lock_init(&mdma->error_status_lock);
 
         dma = &mdma->dma;
         dma->dev = dev;
-        dma->chancnt = MPC_DMA_CHANNELS;
+        if (!mdma->is_mpc8308)
+                dma->chancnt = MPC_DMA_CHANNELS;
+        else
+                dma->chancnt = 16; /* MPC8308 DMA has only 16 channels */
         dma->device_alloc_chan_resources = mpc_dma_alloc_chan_resources;
         dma->device_free_chan_resources = mpc_dma_free_chan_resources;
         dma->device_issue_pending = mpc_dma_issue_pending;
@@ -721,26 +764,40 @@ static int __devinit mpc_dma_probe(struct platform_device *op,
          * - Round-robin group arbitration,
          * - Round-robin channel arbitration.
          */
-        out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_EDCG |
-                                MPC_DMA_DMACR_ERGA | MPC_DMA_DMACR_ERCA);
-
-        /* Disable hardware DMA requests */
-        out_be32(&mdma->regs->dmaerqh, 0);
-        out_be32(&mdma->regs->dmaerql, 0);
-
-        /* Disable error interrupts */
-        out_be32(&mdma->regs->dmaeeih, 0);
-        out_be32(&mdma->regs->dmaeeil, 0);
-
-        /* Clear interrupts status */
-        out_be32(&mdma->regs->dmainth, 0xFFFFFFFF);
-        out_be32(&mdma->regs->dmaintl, 0xFFFFFFFF);
-        out_be32(&mdma->regs->dmaerrh, 0xFFFFFFFF);
-        out_be32(&mdma->regs->dmaerrl, 0xFFFFFFFF);
-
-        /* Route interrupts to IPIC */
-        out_be32(&mdma->regs->dmaihsa, 0);
-        out_be32(&mdma->regs->dmailsa, 0);
+        if (!mdma->is_mpc8308) {
+                out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_EDCG |
+                                        MPC_DMA_DMACR_ERGA | MPC_DMA_DMACR_ERCA);
+
+                /* Disable hardware DMA requests */
+                out_be32(&mdma->regs->dmaerqh, 0);
+                out_be32(&mdma->regs->dmaerql, 0);
+
+                /* Disable error interrupts */
+                out_be32(&mdma->regs->dmaeeih, 0);
+                out_be32(&mdma->regs->dmaeeil, 0);
+
+                /* Clear interrupts status */
+                out_be32(&mdma->regs->dmainth, 0xFFFFFFFF);
+                out_be32(&mdma->regs->dmaintl, 0xFFFFFFFF);
+                out_be32(&mdma->regs->dmaerrh, 0xFFFFFFFF);
+                out_be32(&mdma->regs->dmaerrl, 0xFFFFFFFF);
+
+                /* Route interrupts to IPIC */
+                out_be32(&mdma->regs->dmaihsa, 0);
+                out_be32(&mdma->regs->dmailsa, 0);
+        } else {
+                /* MPC8308 has 16 channels and lacks some registers */
+                out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_ERCA);
+
+                /* enable snooping */
+                out_be32(&mdma->regs->dmagpor, MPC_DMA_DMAGPOR_SNOOP_ENABLE);
+                /* Disable error interrupts */
+                out_be32(&mdma->regs->dmaeeil, 0);
+
+                /* Clear interrupts status */
+                out_be32(&mdma->regs->dmaintl, 0xFFFF);
+                out_be32(&mdma->regs->dmaerrl, 0xFFFF);
+        }
 
         /* Register DMA engine */
         dev_set_drvdata(dev, mdma);
diff --git a/drivers/infiniband/hw/cxgb3/cxio_hal.c b/drivers/infiniband/hw/cxgb3/cxio_hal.c
index 09dda0b8740e..c3f5aca4ef00 100644
--- a/drivers/infiniband/hw/cxgb3/cxio_hal.c
+++ b/drivers/infiniband/hw/cxgb3/cxio_hal.c
@@ -189,6 +189,7 @@ int cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq, int kernel)
         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 }
 
+#ifdef notyet
 int cxio_resize_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
 {
         struct rdma_cq_setup setup;
@@ -200,6 +201,7 @@ int cxio_resize_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
         setup.ovfl_mode = 1;
         return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
 }
+#endif
 
 static u32 get_qpid(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
 {
diff --git a/drivers/infiniband/hw/cxgb3/iwch_provider.h b/drivers/infiniband/hw/cxgb3/iwch_provider.h
index a237d49bdcc9..c5406da3f4cd 100644
--- a/drivers/infiniband/hw/cxgb3/iwch_provider.h
+++ b/drivers/infiniband/hw/cxgb3/iwch_provider.h
@@ -335,8 +335,6 @@ int iwch_post_terminate(struct iwch_qp *qhp, struct respQ_msg_t *rsp_msg);
 int iwch_post_zb_read(struct iwch_qp *qhp);
 int iwch_register_device(struct iwch_dev *dev);
 void iwch_unregister_device(struct iwch_dev *dev);
-int iwch_quiesce_qps(struct iwch_cq *chp);
-int iwch_resume_qps(struct iwch_cq *chp);
 void stop_read_rep_timer(struct iwch_qp *qhp);
 int iwch_register_mem(struct iwch_dev *rhp, struct iwch_pd *php,
                       struct iwch_mr *mhp, int shift);
diff --git a/drivers/infiniband/hw/cxgb3/iwch_qp.c b/drivers/infiniband/hw/cxgb3/iwch_qp.c
index 0993137181d7..1b4cd09f74dc 100644
--- a/drivers/infiniband/hw/cxgb3/iwch_qp.c
+++ b/drivers/infiniband/hw/cxgb3/iwch_qp.c
@@ -1149,59 +1149,3 @@ out:
         PDBG("%s exit state %d\n", __func__, qhp->attr.state);
         return ret;
 }
-
-static int quiesce_qp(struct iwch_qp *qhp)
-{
-        spin_lock_irq(&qhp->lock);
-        iwch_quiesce_tid(qhp->ep);
-        qhp->flags |= QP_QUIESCED;
-        spin_unlock_irq(&qhp->lock);
-        return 0;
-}
-
-static int resume_qp(struct iwch_qp *qhp)
-{
-        spin_lock_irq(&qhp->lock);
-        iwch_resume_tid(qhp->ep);
-        qhp->flags &= ~QP_QUIESCED;
-        spin_unlock_irq(&qhp->lock);
-        return 0;
-}
-
-int iwch_quiesce_qps(struct iwch_cq *chp)
-{
-        int i;
-        struct iwch_qp *qhp;
-
-        for (i=0; i < T3_MAX_NUM_QP; i++) {
-                qhp = get_qhp(chp->rhp, i);
-                if (!qhp)
-                        continue;
-                if ((qhp->attr.rcq == chp->cq.cqid) && !qp_quiesced(qhp)) {
-                        quiesce_qp(qhp);
-                        continue;
-                }
-                if ((qhp->attr.scq == chp->cq.cqid) && !qp_quiesced(qhp))
-                        quiesce_qp(qhp);
-        }
-        return 0;
-}
-
-int iwch_resume_qps(struct iwch_cq *chp)
-{
-        int i;
-        struct iwch_qp *qhp;
-
-        for (i=0; i < T3_MAX_NUM_QP; i++) {
-                qhp = get_qhp(chp->rhp, i);
-                if (!qhp)
-                        continue;
-                if ((qhp->attr.rcq == chp->cq.cqid) && qp_quiesced(qhp)) {
-                        resume_qp(qhp);
-                        continue;
-                }
-                if ((qhp->attr.scq == chp->cq.cqid) && qp_quiesced(qhp))
-                        resume_qp(qhp);
-        }
-        return 0;
-}
diff --git a/drivers/infiniband/hw/cxgb4/iw_cxgb4.h b/drivers/infiniband/hw/cxgb4/iw_cxgb4.h
index 16032cdb4337..cc600c2dd0b3 100644
--- a/drivers/infiniband/hw/cxgb4/iw_cxgb4.h
+++ b/drivers/infiniband/hw/cxgb4/iw_cxgb4.h
@@ -760,7 +760,6 @@ int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
 int c4iw_flush_sq(struct t4_wq *wq, struct t4_cq *cq, int count);
 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
-int c4iw_post_zb_read(struct c4iw_qp *qhp);
 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
diff --git a/drivers/infiniband/hw/cxgb4/qp.c b/drivers/infiniband/hw/cxgb4/qp.c
index 057cb2505ea1..20800900ef3f 100644
--- a/drivers/infiniband/hw/cxgb4/qp.c
+++ b/drivers/infiniband/hw/cxgb4/qp.c
@@ -892,36 +892,6 @@ static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
         }
 }
 
-int c4iw_post_zb_read(struct c4iw_qp *qhp)
-{
-        union t4_wr *wqe;
-        struct sk_buff *skb;
-        u8 len16;
-
-        PDBG("%s enter\n", __func__);
-        skb = alloc_skb(40, GFP_KERNEL);
-        if (!skb) {
-                printk(KERN_ERR "%s cannot send zb_read!!\n", __func__);
-                return -ENOMEM;
-        }
-        set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
-
-        wqe = (union t4_wr *)skb_put(skb, sizeof wqe->read);
-        memset(wqe, 0, sizeof wqe->read);
-        wqe->read.r2 = cpu_to_be64(0);
-        wqe->read.stag_sink = cpu_to_be32(1);
-        wqe->read.to_sink_hi = cpu_to_be32(0);
-        wqe->read.to_sink_lo = cpu_to_be32(1);
-        wqe->read.stag_src = cpu_to_be32(1);
-        wqe->read.plen = cpu_to_be32(0);
-        wqe->read.to_src_hi = cpu_to_be32(0);
-        wqe->read.to_src_lo = cpu_to_be32(1);
-        len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
-        init_wr_hdr(wqe, 0, FW_RI_RDMA_READ_WR, FW_RI_COMPLETION_FLAG, len16);
-
-        return c4iw_ofld_send(&qhp->rhp->rdev, skb);
-}
-
 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
                            gfp_t gfp)
 {
@@ -1029,7 +999,6 @@ static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
         wqe->cookie = (unsigned long) &ep->com.wr_wait;
 
         wqe->u.fini.type = FW_RI_TYPE_FINI;
-        c4iw_init_wr_wait(&ep->com.wr_wait);
         ret = c4iw_ofld_send(&rhp->rdev, skb);
         if (ret)
                 goto out;
@@ -1125,7 +1094,6 @@ static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
         if (qhp->attr.mpa_attr.initiator)
                 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
 
-        c4iw_init_wr_wait(&qhp->ep->com.wr_wait);
         ret = c4iw_ofld_send(&rhp->rdev, skb);
         if (ret)
                 goto out;
diff --git a/drivers/infiniband/hw/ipath/ipath_driver.c b/drivers/infiniband/hw/ipath/ipath_driver.c
index 765f0fc1da76..b33f0457a1ff 100644
--- a/drivers/infiniband/hw/ipath/ipath_driver.c
+++ b/drivers/infiniband/hw/ipath/ipath_driver.c
@@ -530,9 +530,8 @@ static int __devinit ipath_init_one(struct pci_dev *pdev,
         for (j = 0; j < 6; j++) {
                 if (!pdev->resource[j].start)
                         continue;
-                ipath_cdbg(VERBOSE, "BAR %d start %llx, end %llx, len %llx\n",
-                           j, (unsigned long long)pdev->resource[j].start,
-                           (unsigned long long)pdev->resource[j].end,
+                ipath_cdbg(VERBOSE, "BAR %d %pR, len %llx\n",
+                           j, &pdev->resource[j],
                            (unsigned long long)pci_resource_len(pdev, j));
         }
 
diff --git a/drivers/infiniband/hw/mlx4/cq.c b/drivers/infiniband/hw/mlx4/cq.c
index 5a219a2fdf16..e8df155bc3b0 100644
--- a/drivers/infiniband/hw/mlx4/cq.c
+++ b/drivers/infiniband/hw/mlx4/cq.c
@@ -397,10 +397,14 @@ int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
                 cq->resize_buf = NULL;
                 cq->resize_umem = NULL;
         } else {
+                struct mlx4_ib_cq_buf tmp_buf;
+                int tmp_cqe = 0;
+
                 spin_lock_irq(&cq->lock);
                 if (cq->resize_buf) {
                         mlx4_ib_cq_resize_copy_cqes(cq);
-                        mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
+                        tmp_buf = cq->buf;
+                        tmp_cqe = cq->ibcq.cqe;
                         cq->buf      = cq->resize_buf->buf;
                         cq->ibcq.cqe = cq->resize_buf->cqe;
 
@@ -408,6 +412,9 @@ int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
                         cq->resize_buf = NULL;
                 }
                 spin_unlock_irq(&cq->lock);
+
+                if (tmp_cqe)
+                        mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe);
         }
 
         goto out;
diff --git a/drivers/infiniband/hw/mlx4/mad.c b/drivers/infiniband/hw/mlx4/mad.c
index c9a8dd63b9e2..57ffa50f509e 100644
--- a/drivers/infiniband/hw/mlx4/mad.c
+++ b/drivers/infiniband/hw/mlx4/mad.c
@@ -211,6 +211,8 @@ static void forward_trap(struct mlx4_ib_dev *dev, u8 port_num, struct ib_mad *ma
         if (agent) {
                 send_buf = ib_create_send_mad(agent, qpn, 0, 0, IB_MGMT_MAD_HDR,
                                               IB_MGMT_MAD_DATA, GFP_ATOMIC);
+                if (IS_ERR(send_buf))
+                        return;
                 /*
                  * We rely here on the fact that MLX QPs don't use the
                  * address handle after the send is posted (this is
diff --git a/drivers/infiniband/hw/mthca/mthca_mad.c b/drivers/infiniband/hw/mthca/mthca_mad.c
index 5648659ff0b0..03a59534f59e 100644
--- a/drivers/infiniband/hw/mthca/mthca_mad.c
+++ b/drivers/infiniband/hw/mthca/mthca_mad.c
@@ -171,6 +171,8 @@ static void forward_trap(struct mthca_dev *dev,
         if (agent) {
                 send_buf = ib_create_send_mad(agent, qpn, 0, 0, IB_MGMT_MAD_HDR,
                                               IB_MGMT_MAD_DATA, GFP_ATOMIC);
+                if (IS_ERR(send_buf))
+                        return;
                 /*
                  * We rely here on the fact that MLX QPs don't use the
                  * address handle after the send is posted (this is
diff --git a/drivers/infiniband/hw/nes/nes_nic.c b/drivers/infiniband/hw/nes/nes_nic.c
index 3892e2c0e95a..5a4c36484722 100644
--- a/drivers/infiniband/hw/nes/nes_nic.c
+++ b/drivers/infiniband/hw/nes/nes_nic.c
@@ -908,8 +908,8 @@ static void nes_netdev_set_multicast_list(struct net_device *netdev)
                                         nesvnic->nic_index &&
                                         mc_index < max_pft_entries_avaiable) {
                                                 nes_debug(NES_DBG_NIC_RX,
-                                        "mc_index=%d skipping nic_index=%d,\
-                                        used for=%d \n", mc_index,
+                                        "mc_index=%d skipping nic_index=%d, "
+                                        "used for=%d \n", mc_index,
                                         nesvnic->nic_index,
                                         nesadapter->pft_mcast_map[mc_index]);
                                 mc_index++;
diff --git a/drivers/infiniband/hw/qib/qib.h b/drivers/infiniband/hw/qib/qib.h
index 64c9e7d02d4a..73225eee3cc6 100644
--- a/drivers/infiniband/hw/qib/qib.h
+++ b/drivers/infiniband/hw/qib/qib.h
@@ -766,7 +766,7 @@ struct qib_devdata {
         void (*f_sdma_hw_start_up)(struct qib_pportdata *);
         void (*f_sdma_init_early)(struct qib_pportdata *);
         void (*f_set_cntr_sample)(struct qib_pportdata *, u32, u32);
-        void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32);
+        void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32, u32);
         u32 (*f_hdrqempty)(struct qib_ctxtdata *);
         u64 (*f_portcntr)(struct qib_pportdata *, u32);
         u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **,
diff --git a/drivers/infiniband/hw/qib/qib_cq.c b/drivers/infiniband/hw/qib/qib_cq.c
index a86cbf880f98..5246aa486bbe 100644
--- a/drivers/infiniband/hw/qib/qib_cq.c
+++ b/drivers/infiniband/hw/qib/qib_cq.c
@@ -100,7 +100,8 @@ void qib_cq_enter(struct qib_cq *cq, struct ib_wc *entry, int solicited)
         wc->head = next;
 
         if (cq->notify == IB_CQ_NEXT_COMP ||
-            (cq->notify == IB_CQ_SOLICITED && solicited)) {
+            (cq->notify == IB_CQ_SOLICITED &&
+             (solicited || entry->status != IB_WC_SUCCESS))) {
                 cq->notify = IB_CQ_NONE;
                 cq->triggered++;
                 /*
diff --git a/drivers/infiniband/hw/qib/qib_driver.c b/drivers/infiniband/hw/qib/qib_driver.c
index 9cd193603fb1..23e584f4c36c 100644
--- a/drivers/infiniband/hw/qib/qib_driver.c
+++ b/drivers/infiniband/hw/qib/qib_driver.c
@@ -71,6 +71,11 @@ MODULE_DESCRIPTION("QLogic IB driver");
  */
 #define QIB_PIO_MAXIBHDR 128
 
+/*
+ * QIB_MAX_PKT_RCV is the max # if packets processed per receive interrupt.
+ */
+#define QIB_MAX_PKT_RECV 64
+
 struct qlogic_ib_stats qib_stats;
 
 const char *qib_get_unit_name(int unit)
@@ -284,14 +289,147 @@ static inline void *qib_get_egrbuf(const struct qib_ctxtdata *rcd, u32 etail)
  * Returns 1 if error was a CRC, else 0.
  * Needed for some chip's synthesized error counters.
  */
-static u32 qib_rcv_hdrerr(struct qib_pportdata *ppd, u32 ctxt,
-                          u32 eflags, u32 l, u32 etail, __le32 *rhf_addr,
-                          struct qib_message_header *hdr)
+static u32 qib_rcv_hdrerr(struct qib_ctxtdata *rcd, struct qib_pportdata *ppd,
+                          u32 ctxt, u32 eflags, u32 l, u32 etail,
+                          __le32 *rhf_addr, struct qib_message_header *rhdr)
 {
         u32 ret = 0;
 
         if (eflags & (QLOGIC_IB_RHF_H_ICRCERR | QLOGIC_IB_RHF_H_VCRCERR))
                 ret = 1;
+        else if (eflags == QLOGIC_IB_RHF_H_TIDERR) {
+                /* For TIDERR and RC QPs premptively schedule a NAK */
+                struct qib_ib_header *hdr = (struct qib_ib_header *) rhdr;
+                struct qib_other_headers *ohdr = NULL;
+                struct qib_ibport *ibp = &ppd->ibport_data;
+                struct qib_qp *qp = NULL;
+                u32 tlen = qib_hdrget_length_in_bytes(rhf_addr);
+                u16 lid  = be16_to_cpu(hdr->lrh[1]);
+                int lnh = be16_to_cpu(hdr->lrh[0]) & 3;
+                u32 qp_num;
+                u32 opcode;
+                u32 psn;
+                int diff;
+                unsigned long flags;
+
+                /* Sanity check packet */
+                if (tlen < 24)
+                        goto drop;
+
+                if (lid < QIB_MULTICAST_LID_BASE) {
+                        lid &= ~((1 << ppd->lmc) - 1);
+                        if (unlikely(lid != ppd->lid))
+                                goto drop;
+                }
+
+                /* Check for GRH */
+                if (lnh == QIB_LRH_BTH)
+                        ohdr = &hdr->u.oth;
+                else if (lnh == QIB_LRH_GRH) {
+                        u32 vtf;
+
+                        ohdr = &hdr->u.l.oth;
+                        if (hdr->u.l.grh.next_hdr != IB_GRH_NEXT_HDR)
+                                goto drop;
+                        vtf = be32_to_cpu(hdr->u.l.grh.version_tclass_flow);
+                        if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
+                                goto drop;
+                } else
+                        goto drop;
+
+                /* Get opcode and PSN from packet */
+                opcode = be32_to_cpu(ohdr->bth[0]);
+                opcode >>= 24;
+                psn = be32_to_cpu(ohdr->bth[2]);
+
+                /* Get the destination QP number. */
+                qp_num = be32_to_cpu(ohdr->bth[1]) & QIB_QPN_MASK;
+                if (qp_num != QIB_MULTICAST_QPN) {
+                        int ruc_res;
+                        qp = qib_lookup_qpn(ibp, qp_num);
+                        if (!qp)
+                                goto drop;
+
+                        /*
+                         * Handle only RC QPs - for other QP types drop error
+                         * packet.
+                         */
+                        spin_lock(&qp->r_lock);
+
+                        /* Check for valid receive state. */
+                        if (!(ib_qib_state_ops[qp->state] &
+                              QIB_PROCESS_RECV_OK)) {
+                                ibp->n_pkt_drops++;
+                                goto unlock;
+                        }
+
+                        switch (qp->ibqp.qp_type) {
+                        case IB_QPT_RC:
+                                spin_lock_irqsave(&qp->s_lock, flags);
+                                ruc_res =
+                                        qib_ruc_check_hdr(
+                                                ibp, hdr,
+                                                lnh == QIB_LRH_GRH,
+                                                qp,
+                                                be32_to_cpu(ohdr->bth[0]));
+                                if (ruc_res) {
+                                        spin_unlock_irqrestore(&qp->s_lock,
+                                                               flags);
+                                        goto unlock;
+                                }
+                                spin_unlock_irqrestore(&qp->s_lock, flags);
+
+                                /* Only deal with RDMA Writes for now */
+                                if (opcode <
+                                    IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST) {
+                                        diff = qib_cmp24(psn, qp->r_psn);
+                                        if (!qp->r_nak_state && diff >= 0) {
+                                                ibp->n_rc_seqnak++;
+                                                qp->r_nak_state =
+                                                        IB_NAK_PSN_ERROR;
+                                                /* Use the expected PSN. */
+                                                qp->r_ack_psn = qp->r_psn;
+                                                /*
+                                                 * Wait to send the sequence
+                                                 * NAK until all packets
+                                                 * in the receive queue have
+                                                 * been processed.
+                                                 * Otherwise, we end up
+                                                 * propagating congestion.
+                                                 */
+                                                if (list_empty(&qp->rspwait)) {
+                                                        qp->r_flags |=
+                                                                QIB_R_RSP_NAK;
+                                                        atomic_inc(
+                                                                &qp->refcount);
+                                                        list_add_tail(
+                                                         &qp->rspwait,
+                                                         &rcd->qp_wait_list);
+                                                }
+                                        } /* Out of sequence NAK */
+                                } /* QP Request NAKs */
+                                break;
+                        case IB_QPT_SMI:
+                        case IB_QPT_GSI:
+                        case IB_QPT_UD:
+                        case IB_QPT_UC:
+                        default:
+                                /* For now don't handle any other QP types */
+                                break;
+                        }
+
+unlock:
+                        spin_unlock(&qp->r_lock);
+                        /*
+                         * Notify qib_destroy_qp() if it is waiting
+                         * for us to finish.
+                         */
+                        if (atomic_dec_and_test(&qp->refcount))
+                                wake_up(&qp->wait);
+                } /* Unicast QP */
+        } /* Valid packet with TIDErr */
+
+drop:
         return ret;
 }
 
@@ -335,7 +473,7 @@ u32 qib_kreceive(struct qib_ctxtdata *rcd, u32 *llic, u32 *npkts)
                 smp_rmb();  /* prevent speculative reads of dma'ed hdrq */
         }
 
-        for (last = 0, i = 1; !last && i <= 64; i += !last) {
+        for (last = 0, i = 1; !last; i += !last) {
                 hdr = dd->f_get_msgheader(dd, rhf_addr);
                 eflags = qib_hdrget_err_flags(rhf_addr);
                 etype = qib_hdrget_rcv_type(rhf_addr);
@@ -371,7 +509,7 @@ u32 qib_kreceive(struct qib_ctxtdata *rcd, u32 *llic, u32 *npkts)
                  * packets; only qibhdrerr should be set.
                  */
                 if (unlikely(eflags))
-                        crcs += qib_rcv_hdrerr(ppd, rcd->ctxt, eflags, l,
+                        crcs += qib_rcv_hdrerr(rcd, ppd, rcd->ctxt, eflags, l,
                                                etail, rhf_addr, hdr);
                 else if (etype == RCVHQ_RCV_TYPE_NON_KD) {
                         qib_ib_rcv(rcd, hdr, ebuf, tlen);
@@ -384,6 +522,9 @@ move_along:
                 l += rsize;
                 if (l >= maxcnt)
                         l = 0;
+                if (i == QIB_MAX_PKT_RECV)
+                        last = 1;
+
                 rhf_addr = (__le32 *) rcd->rcvhdrq + l + dd->rhf_offset;
                 if (dd->flags & QIB_NODMA_RTAIL) {
                         u32 seq = qib_hdrget_seq(rhf_addr);
@@ -402,7 +543,7 @@ move_along:
                  */
                 lval = l;
                 if (!last && !(i & 0xf)) {
-                        dd->f_update_usrhead(rcd, lval, updegr, etail);
+                        dd->f_update_usrhead(rcd, lval, updegr, etail, i);
                         updegr = 0;
                 }
         }
@@ -444,7 +585,7 @@ bail:
          * if no packets were processed.
          */
         lval = (u64)rcd->head | dd->rhdrhead_intr_off;
-        dd->f_update_usrhead(rcd, lval, updegr, etail);
+        dd->f_update_usrhead(rcd, lval, updegr, etail, i);
         return crcs;
 }
 
diff --git a/drivers/infiniband/hw/qib/qib_file_ops.c b/drivers/infiniband/hw/qib/qib_file_ops.c
index 79d9971aff1f..75bfad16c114 100644
--- a/drivers/infiniband/hw/qib/qib_file_ops.c
+++ b/drivers/infiniband/hw/qib/qib_file_ops.c
@@ -1379,17 +1379,17 @@ static int get_a_ctxt(struct file *fp, const struct qib_user_info *uinfo,
                 /* find device (with ACTIVE ports) with fewest ctxts in use */
                 for (ndev = 0; ndev < devmax; ndev++) {
                         struct qib_devdata *dd = qib_lookup(ndev);
-                        unsigned cused = 0, cfree = 0;
+                        unsigned cused = 0, cfree = 0, pusable = 0;
                         if (!dd)
                                 continue;
                         if (port && port <= dd->num_pports &&
                             usable(dd->pport + port - 1))
-                                dusable = 1;
+                                pusable = 1;
                         else
                                 for (i = 0; i < dd->num_pports; i++)
                                         if (usable(dd->pport + i))
-                                                dusable++;
-                        if (!dusable)
+                                                pusable++;
+                        if (!pusable)
                                 continue;
                         for (ctxt = dd->first_user_ctxt; ctxt < dd->cfgctxts;
                              ctxt++)
@@ -1397,7 +1397,7 @@ static int get_a_ctxt(struct file *fp, const struct qib_user_info *uinfo,
                                         cused++;
                                 else
                                         cfree++;
-                        if (cfree && cused < inuse) {
+                        if (pusable && cfree && cused < inuse) {
                                 udd = dd;
                                 inuse = cused;
                         }
diff --git a/drivers/infiniband/hw/qib/qib_iba6120.c b/drivers/infiniband/hw/qib/qib_iba6120.c
index a5e29dbb9537..774dea897e9c 100644
--- a/drivers/infiniband/hw/qib/qib_iba6120.c
+++ b/drivers/infiniband/hw/qib/qib_iba6120.c
@@ -2074,7 +2074,7 @@ static void qib_6120_config_ctxts(struct qib_devdata *dd)
 }
 
 static void qib_update_6120_usrhead(struct qib_ctxtdata *rcd, u64 hd,
-                                    u32 updegr, u32 egrhd)
+                                    u32 updegr, u32 egrhd, u32 npkts)
 {
         qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
         if (updegr)
diff --git a/drivers/infiniband/hw/qib/qib_iba7220.c b/drivers/infiniband/hw/qib/qib_iba7220.c
index 6fd8d74e7392..127a0d5069f0 100644
--- a/drivers/infiniband/hw/qib/qib_iba7220.c
+++ b/drivers/infiniband/hw/qib/qib_iba7220.c
@@ -2297,7 +2297,7 @@ static void qib_7220_config_ctxts(struct qib_devdata *dd)
         nchipctxts = qib_read_kreg32(dd, kr_portcnt);
         dd->cspec->numctxts = nchipctxts;
         if (qib_n_krcv_queues > 1) {
-                dd->qpn_mask = 0x3f;
+                dd->qpn_mask = 0x3e;
                 dd->first_user_ctxt = qib_n_krcv_queues * dd->num_pports;
                 if (dd->first_user_ctxt > nchipctxts)
                         dd->first_user_ctxt = nchipctxts;
@@ -2703,7 +2703,7 @@ static int qib_7220_set_loopback(struct qib_pportdata *ppd, const char *what)
 }
 
 static void qib_update_7220_usrhead(struct qib_ctxtdata *rcd, u64 hd,
-                                    u32 updegr, u32 egrhd)
+                                    u32 updegr, u32 egrhd, u32 npkts)
 {
         qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
         if (updegr)
diff --git a/drivers/infiniband/hw/qib/qib_iba7322.c b/drivers/infiniband/hw/qib/qib_iba7322.c
index 584d443b5335..dbbb0e85afe4 100644
--- a/drivers/infiniband/hw/qib/qib_iba7322.c
+++ b/drivers/infiniband/hw/qib/qib_iba7322.c
@@ -71,6 +71,9 @@ static void qib_7322_mini_pcs_reset(struct qib_pportdata *);
 
 static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32);
 static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned);
+static void serdes_7322_los_enable(struct qib_pportdata *, int);
+static int serdes_7322_init_old(struct qib_pportdata *);
+static int serdes_7322_init_new(struct qib_pportdata *);
 
 #define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb))
 
@@ -111,6 +114,21 @@ static ushort qib_singleport;
 module_param_named(singleport, qib_singleport, ushort, S_IRUGO);
 MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space");
 
+/*
+ * Receive header queue sizes
+ */
+static unsigned qib_rcvhdrcnt;
+module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO);
+MODULE_PARM_DESC(rcvhdrcnt, "receive header count");
+
+static unsigned qib_rcvhdrsize;
+module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO);
+MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words");
+
+static unsigned qib_rcvhdrentsize;
+module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO);
+MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words");
+
 #define MAX_ATTEN_LEN 64 /* plenty for any real system */
 /* for read back, default index is ~5m copper cable */
 static char txselect_list[MAX_ATTEN_LEN] = "10";
@@ -544,6 +562,7 @@ static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *);
 
 #define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */
 #define TXDDS_EXTRA_SZ 13 /* number of extra tx settings entries */
+#define TXDDS_MFG_SZ 2    /* number of mfg tx settings entries */
 #define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */
 
 #define H1_FORCE_VAL 8
@@ -604,6 +623,7 @@ struct qib_chippport_specific {
         u8 ibmalfusesnap;
         struct qib_qsfp_data qsfp_data;
         char epmsgbuf[192]; /* for port error interrupt msg buffer */
+        u8 bounced;
 };
 
 static struct {
@@ -1677,6 +1697,8 @@ static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst)
             (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) {
                 force_h1(ppd);
                 ppd->cpspec->qdr_reforce = 1;
+                if (!ppd->dd->cspec->r1)
+                        serdes_7322_los_enable(ppd, 0);
         } else if (ppd->cpspec->qdr_reforce &&
                 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) &&
                  (ibclt == IB_7322_LT_STATE_CFGENH ||
@@ -1692,18 +1714,37 @@ static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst)
               ibclt <= IB_7322_LT_STATE_SLEEPQUIET)))
                 adj_tx_serdes(ppd);
 
-        if (!ppd->cpspec->qdr_dfe_on && ibclt != IB_7322_LT_STATE_LINKUP &&
-            ibclt <= IB_7322_LT_STATE_SLEEPQUIET) {
-                ppd->cpspec->qdr_dfe_on = 1;
-                ppd->cpspec->qdr_dfe_time = 0;
-                /* On link down, reenable QDR adaptation */
-                qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
-                        ppd->dd->cspec->r1 ?
-                                    QDR_STATIC_ADAPT_DOWN_R1 :
-                                    QDR_STATIC_ADAPT_DOWN);
+        if (ibclt != IB_7322_LT_STATE_LINKUP) {
+                u8 ltstate = qib_7322_phys_portstate(ibcst);
+                u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0,
+                                          LinkTrainingState);
+                if (!ppd->dd->cspec->r1 &&
+                    pibclt == IB_7322_LT_STATE_LINKUP &&
+                    ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
+                    ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
+                    ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
+                    ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
+                        /* If the link went down (but no into recovery,
+                         * turn LOS back on */
+                        serdes_7322_los_enable(ppd, 1);
+                if (!ppd->cpspec->qdr_dfe_on &&
+                    ibclt <= IB_7322_LT_STATE_SLEEPQUIET) {
+                        ppd->cpspec->qdr_dfe_on = 1;
+                        ppd->cpspec->qdr_dfe_time = 0;
+                        /* On link down, reenable QDR adaptation */
+                        qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
+                                            ppd->dd->cspec->r1 ?
+                                            QDR_STATIC_ADAPT_DOWN_R1 :
+                                            QDR_STATIC_ADAPT_DOWN);
+                        printk(KERN_INFO QIB_DRV_NAME
+                                " IB%u:%u re-enabled QDR adaptation "
+                                "ibclt %x\n", ppd->dd->unit, ppd->port, ibclt);
+                }
         }
 }
 
+static int qib_7322_set_ib_cfg(struct qib_pportdata *, int, u32);
+
 /*
  * This is per-pport error handling.
  * will likely get it's own MSIx interrupt (one for each port,
@@ -1840,7 +1881,23 @@ static noinline void handle_7322_p_errors(struct qib_pportdata *ppd)
                     IB_PHYSPORTSTATE_DISABLED)
                         qib_set_ib_7322_lstate(ppd, 0,
                                QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
-                else
+                else {
+                        u32 lstate;
+                        /*
+                         * We need the current logical link state before
+                         * lflags are set in handle_e_ibstatuschanged.
+                         */
+                        lstate = qib_7322_iblink_state(ibcs);
+
+                        if (IS_QMH(dd) && !ppd->cpspec->bounced &&
+                            ltstate == IB_PHYSPORTSTATE_LINKUP &&
+                            (lstate >= IB_PORT_INIT &&
+                                lstate <= IB_PORT_ACTIVE)) {
+                                ppd->cpspec->bounced = 1;
+                                qib_7322_set_ib_cfg(ppd, QIB_IB_CFG_LSTATE,
+                                        IB_LINKCMD_DOWN | IB_LINKINITCMD_POLL);
+                        }
+
                         /*
                          * Since going into a recovery state causes the link
                          * state to go down and since recovery is transitory,
@@ -1854,6 +1911,7 @@ static noinline void handle_7322_p_errors(struct qib_pportdata *ppd)
                             ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
                             ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
                                 qib_handle_e_ibstatuschanged(ppd, ibcs);
+                }
         }
         if (*msg && iserr)
                 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
@@ -2785,7 +2843,6 @@ static irqreturn_t qib_7322intr(int irq, void *data)
                                 ctxtrbits &= ~rmask;
                                 if (dd->rcd[i]) {
                                         qib_kreceive(dd->rcd[i], NULL, &npkts);
-                                        adjust_rcv_timeout(dd->rcd[i], npkts);
                                 }
                         }
                         rmask <<= 1;
@@ -2835,7 +2892,6 @@ static irqreturn_t qib_7322pintr(int irq, void *data)
                        (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt);
 
         qib_kreceive(rcd, NULL, &npkts);
-        adjust_rcv_timeout(rcd, npkts);
 
         return IRQ_HANDLED;
 }
@@ -3157,6 +3213,10 @@ static unsigned qib_7322_boardname(struct qib_devdata *dd)
         case BOARD_QME7342:
                 n = "InfiniPath_QME7342";
                 break;
+        case 8:
+                n = "InfiniPath_QME7362";
+                dd->flags |= QIB_HAS_QSFP;
+                break;
         case 15:
                 n = "InfiniPath_QLE7342_TEST";
                 dd->flags |= QIB_HAS_QSFP;
@@ -3475,11 +3535,6 @@ static void qib_7322_config_ctxts(struct qib_devdata *dd)
         nchipctxts = qib_read_kreg32(dd, kr_contextcnt);
         dd->cspec->numctxts = nchipctxts;
         if (qib_n_krcv_queues > 1 && dd->num_pports) {
-                /*
-                 * Set the mask for which bits from the QPN are used
-                 * to select a context number.
-                 */
-                dd->qpn_mask = 0x3f;
                 dd->first_user_ctxt = NUM_IB_PORTS +
                         (qib_n_krcv_queues - 1) * dd->num_pports;
                 if (dd->first_user_ctxt > nchipctxts)
@@ -3530,8 +3585,11 @@ static void qib_7322_config_ctxts(struct qib_devdata *dd)
 
         /* kr_rcvegrcnt changes based on the number of contexts enabled */
         dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
-        dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt,
-                                dd->num_pports > 1 ? 1024U : 2048U);
+        if (qib_rcvhdrcnt)
+                dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt);
+        else
+                dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt,
+                                    dd->num_pports > 1 ? 1024U : 2048U);
 }
 
 static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which)
@@ -4002,8 +4060,14 @@ static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t)
 }
 
 static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd,
-                                    u32 updegr, u32 egrhd)
+                                    u32 updegr, u32 egrhd, u32 npkts)
 {
+        /*
+         * Need to write timeout register before updating rcvhdrhead to ensure
+         * that the timer is enabled on reception of a packet.
+         */
+        if (hd >> IBA7322_HDRHEAD_PKTINT_SHIFT)
+                adjust_rcv_timeout(rcd, npkts);
         qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
         qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
         if (updegr)
@@ -5522,7 +5586,7 @@ static void qsfp_7322_event(struct work_struct *work)
                 u64 now = get_jiffies_64();
                 if (time_after64(now, pwrup))
                         break;
-                msleep(1);
+                msleep(20);
         }
         ret = qib_refresh_qsfp_cache(ppd, &qd->cache);
         /*
@@ -5579,6 +5643,7 @@ static void set_no_qsfp_atten(struct qib_devdata *dd, int change)
         u32 pidx, unit, port, deflt, h1;
         unsigned long val;
         int any = 0, seth1;
+        int txdds_size;
 
         str = txselect_list;
 
@@ -5587,6 +5652,10 @@ static void set_no_qsfp_atten(struct qib_devdata *dd, int change)
         for (pidx = 0; pidx < dd->num_pports; ++pidx)
                 dd->pport[pidx].cpspec->no_eep = deflt;
 
+        txdds_size = TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ;
+        if (IS_QME(dd) || IS_QMH(dd))
+                txdds_size += TXDDS_MFG_SZ;
+
         while (*nxt && nxt[1]) {
                 str = ++nxt;
                 unit = simple_strtoul(str, &nxt, 0);
@@ -5609,7 +5678,7 @@ static void set_no_qsfp_atten(struct qib_devdata *dd, int change)
                                 ;
                         continue;
                 }
-                if (val >= TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)
+                if (val >= txdds_size)
                         continue;
                 seth1 = 0;
                 h1 = 0; /* gcc thinks it might be used uninitted */
@@ -5661,10 +5730,11 @@ static int setup_txselect(const char *str, struct kernel_param *kp)
                 return -ENOSPC;
         }
         val = simple_strtoul(str, &n, 0);
-        if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) {
+        if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
+                                TXDDS_MFG_SZ)) {
                 printk(KERN_INFO QIB_DRV_NAME
                        "txselect_values must start with a number < %d\n",
-                        TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ);
+                        TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + TXDDS_MFG_SZ);
                 return -EINVAL;
         }
         strcpy(txselect_list, str);
@@ -5810,7 +5880,8 @@ static void write_7322_initregs(struct qib_devdata *dd)
                 unsigned n, regno;
                 unsigned long flags;
 
-                if (!dd->qpn_mask || !dd->pport[pidx].link_speed_supported)
+                if (dd->n_krcv_queues < 2 ||
+                        !dd->pport[pidx].link_speed_supported)
                         continue;
 
                 ppd = &dd->pport[pidx];
@@ -6097,8 +6168,10 @@ static int qib_init_7322_variables(struct qib_devdata *dd)
                 ppd++;
         }
 
-        dd->rcvhdrentsize = QIB_RCVHDR_ENTSIZE;
-        dd->rcvhdrsize = QIB_DFLT_RCVHDRSIZE;
+        dd->rcvhdrentsize = qib_rcvhdrentsize ?
+                qib_rcvhdrentsize : QIB_RCVHDR_ENTSIZE;
+        dd->rcvhdrsize = qib_rcvhdrsize ?
+                qib_rcvhdrsize : QIB_DFLT_RCVHDRSIZE;
         dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32);
 
         /* we always allocate at least 2048 bytes for eager buffers */
@@ -6495,7 +6568,7 @@ static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start,
                 /* make sure we see an updated copy next time around */
                 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
                 sleeps++;
-                msleep(1);
+                msleep(20);
         }
 
         switch (which) {
@@ -6993,6 +7066,12 @@ static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = {
         {  0, 1,  0, 12 },      /* QMH7342 backplane settings */
 };
 
+static const struct txdds_ent txdds_extra_mfg[TXDDS_MFG_SZ] = {
+        /* amp, pre, main, post */
+        { 0, 0, 0, 0 },         /* QME7342 mfg settings */
+        { 0, 0, 0, 6 },         /* QME7342 P2 mfg settings */
+};
+
 static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds,
                                                unsigned atten)
 {
@@ -7066,6 +7145,16 @@ static void find_best_ent(struct qib_pportdata *ppd,
                 *sdr_dds = &txdds_extra_sdr[idx];
                 *ddr_dds = &txdds_extra_ddr[idx];
                 *qdr_dds = &txdds_extra_qdr[idx];
+        } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) &&
+                   ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
+                                          TXDDS_MFG_SZ)) {
+                idx = ppd->cpspec->no_eep - (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ);
+                printk(KERN_INFO QIB_DRV_NAME
+                        " IB%u:%u use idx %u into txdds_mfg\n",
+                        ppd->dd->unit, ppd->port, idx);
+                *sdr_dds = &txdds_extra_mfg[idx];
+                *ddr_dds = &txdds_extra_mfg[idx];
+                *qdr_dds = &txdds_extra_mfg[idx];
         } else {
                 /* this shouldn't happen, it's range checked */
                 *sdr_dds = txdds_sdr + qib_long_atten;
@@ -7210,9 +7299,30 @@ static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data,
         }
 }
 
+static void serdes_7322_los_enable(struct qib_pportdata *ppd, int enable)
+{
+        u64 data = qib_read_kreg_port(ppd, krp_serdesctrl);
+        printk(KERN_INFO QIB_DRV_NAME " IB%u:%u Turning LOS %s\n",
+                ppd->dd->unit, ppd->port, (enable ? "on" : "off"));
+        if (enable)
+                data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
+        else
+                data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
+        qib_write_kreg_port(ppd, krp_serdesctrl, data);
+}
+
 static int serdes_7322_init(struct qib_pportdata *ppd)
 {
-        u64 data;
+        int ret = 0;
+        if (ppd->dd->cspec->r1)
+                ret = serdes_7322_init_old(ppd);
+        else
+                ret = serdes_7322_init_new(ppd);
+        return ret;
+}
+
+static int serdes_7322_init_old(struct qib_pportdata *ppd)
+{
         u32 le_val;
 
         /*
@@ -7270,11 +7380,7 @@ static int serdes_7322_init(struct qib_pportdata *ppd)
         ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
         ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
 
-        data = qib_read_kreg_port(ppd, krp_serdesctrl);
-        /* Turn off IB latency mode */
-        data &= ~SYM_MASK(IBSerdesCtrl_0, IB_LAT_MODE);
-        qib_write_kreg_port(ppd, krp_serdesctrl, data |
-                SYM_MASK(IBSerdesCtrl_0, RXLOSEN));
+        serdes_7322_los_enable(ppd, 1);
 
         /* rxbistena; set 0 to avoid effects of it switch later */
         ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15);
@@ -7314,6 +7420,205 @@ static int serdes_7322_init(struct qib_pportdata *ppd)
         return 0;
 }
 
+static int serdes_7322_init_new(struct qib_pportdata *ppd)
+{
+        u64 tstart;
+        u32 le_val, rxcaldone;
+        int chan, chan_done = (1 << SERDES_CHANS) - 1;
+
+        /*
+         * Initialize the Tx DDS tables.  Also done every QSFP event,
+         * for adapters with QSFP
+         */
+        init_txdds_table(ppd, 0);
+
+        /* Clear cmode-override, may be set from older driver */
+        ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
+
+        /* ensure no tx overrides from earlier driver loads */
+        qib_write_kreg_port(ppd, krp_tx_deemph_override,
+                SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
+                reset_tx_deemphasis_override));
+
+        /* START OF LSI SUGGESTED SERDES BRINGUP */
+        /* Reset - Calibration Setup */
+        /*       Stop DFE adaptaion */
+        ibsd_wr_allchans(ppd, 1, 0, BMASK(9, 1));
+        /*       Disable LE1 */
+        ibsd_wr_allchans(ppd, 13, 0, BMASK(5, 5));
+        /*       Disable autoadapt for LE1 */
+        ibsd_wr_allchans(ppd, 1, 0, BMASK(15, 15));
+        /*       Disable LE2 */
+        ibsd_wr_allchans(ppd, 13, 0, BMASK(6, 6));
+        /*       Disable VGA */
+        ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
+        /*       Disable AFE Offset Cancel */
+        ibsd_wr_allchans(ppd, 12, 0, BMASK(12, 12));
+        /*       Disable Timing Loop */
+        ibsd_wr_allchans(ppd, 2, 0, BMASK(3, 3));
+        /*       Disable Frequency Loop */
+        ibsd_wr_allchans(ppd, 2, 0, BMASK(4, 4));
+        /*       Disable Baseline Wander Correction */
+        ibsd_wr_allchans(ppd, 13, 0, BMASK(13, 13));
+        /*       Disable RX Calibration */
+        ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
+        /*       Disable RX Offset Calibration */
+        ibsd_wr_allchans(ppd, 12, 0, BMASK(4, 4));
+        /*       Select BB CDR */
+        ibsd_wr_allchans(ppd, 2, (1 << 15), BMASK(15, 15));
+        /*       CDR Step Size */
+        ibsd_wr_allchans(ppd, 5, 0, BMASK(9, 8));
+        /*       Enable phase Calibration */
+        ibsd_wr_allchans(ppd, 12, (1 << 5), BMASK(5, 5));
+        /*       DFE Bandwidth [2:14-12] */
+        ibsd_wr_allchans(ppd, 2, (4 << 12), BMASK(14, 12));
+        /*       DFE Config (4 taps only) */
+        ibsd_wr_allchans(ppd, 16, 0, BMASK(1, 0));
+        /*       Gain Loop Bandwidth */
+        if (!ppd->dd->cspec->r1) {
+                ibsd_wr_allchans(ppd, 12, 1 << 12, BMASK(12, 12));
+                ibsd_wr_allchans(ppd, 12, 2 << 8, BMASK(11, 8));
+        } else {
+                ibsd_wr_allchans(ppd, 19, (3 << 11), BMASK(13, 11));
+        }
+        /*       Baseline Wander Correction Gain [13:4-0] (leave as default) */
+        /*       Baseline Wander Correction Gain [3:7-5] (leave as default) */
+        /*       Data Rate Select [5:7-6] (leave as default) */
+        /*       RX Parralel Word Width [3:10-8] (leave as default) */
+
+        /* RX REST */
+        /*       Single- or Multi-channel reset */
+        /*       RX Analog reset */
+        /*       RX Digital reset */
+        ibsd_wr_allchans(ppd, 0, 0, BMASK(15, 13));
+        msleep(20);
+        /*       RX Analog reset */
+        ibsd_wr_allchans(ppd, 0, (1 << 14), BMASK(14, 14));
+        msleep(20);
+        /*       RX Digital reset */
+        ibsd_wr_allchans(ppd, 0, (1 << 13), BMASK(13, 13));
+        msleep(20);
+
+        /* setup LoS params; these are subsystem, so chan == 5 */
+        /* LoS filter threshold_count on, ch 0-3, set to 8 */
+        ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
+        ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
+        ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
+        ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
+
+        /* LoS filter threshold_count off, ch 0-3, set to 4 */
+        ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
+        ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
+        ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
+        ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
+
+        /* LoS filter select enabled */
+        ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
+
+        /* LoS target data:  SDR=4, DDR=2, QDR=1 */
+        ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
+        ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
+        ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
+
+        /* Turn on LOS on initial SERDES init */
+        serdes_7322_los_enable(ppd, 1);
+        /* FLoop LOS gate: PPM filter  enabled */
+        ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
+
+        /* RX LATCH CALIBRATION */
+        /*       Enable Eyefinder Phase Calibration latch */
+        ibsd_wr_allchans(ppd, 15, 1, BMASK(0, 0));
+        /*       Enable RX Offset Calibration latch */
+        ibsd_wr_allchans(ppd, 12, (1 << 4), BMASK(4, 4));
+        msleep(20);
+        /*       Start Calibration */
+        ibsd_wr_allchans(ppd, 4, (1 << 10), BMASK(10, 10));
+        tstart = get_jiffies_64();
+        while (chan_done &&
+               !time_after64(tstart, tstart + msecs_to_jiffies(500))) {
+                msleep(20);
+                for (chan = 0; chan < SERDES_CHANS; ++chan) {
+                        rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
+                                            (chan + (chan >> 1)),
+                                            25, 0, 0);
+                        if ((~rxcaldone & (u32)BMASK(9, 9)) == 0 &&
+                            (~chan_done & (1 << chan)) == 0)
+                                chan_done &= ~(1 << chan);
+                }
+        }
+        if (chan_done) {
+                printk(KERN_INFO QIB_DRV_NAME
+                         " Serdes %d calibration not done after .5 sec: 0x%x\n",
+                         IBSD(ppd->hw_pidx), chan_done);
+        } else {
+                for (chan = 0; chan < SERDES_CHANS; ++chan) {
+                        rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
+                                            (chan + (chan >> 1)),
+                                            25, 0, 0);
+                        if ((~rxcaldone & (u32)BMASK(10, 10)) == 0)
+                                printk(KERN_INFO QIB_DRV_NAME
+                                         " Serdes %d chan %d calibration "
+                                         "failed\n", IBSD(ppd->hw_pidx), chan);
+                }
+        }
+
+        /*       Turn off Calibration */
+        ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
+        msleep(20);
+
+        /* BRING RX UP */
+        /*       Set LE2 value (May be overridden in qsfp_7322_event) */
+        le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
+        ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
+        /*       Set LE2 Loop bandwidth */
+        ibsd_wr_allchans(ppd, 3, (7 << 5), BMASK(7, 5));
+        /*       Enable LE2 */
+        ibsd_wr_allchans(ppd, 13, (1 << 6), BMASK(6, 6));
+        msleep(20);
+        /*       Enable H0 only */
+        ibsd_wr_allchans(ppd, 1, 1, BMASK(9, 1));
+        /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
+        le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
+        ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
+        /*       Enable VGA */
+        ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
+        msleep(20);
+        /*       Set Frequency Loop Bandwidth */
+        ibsd_wr_allchans(ppd, 2, (7 << 5), BMASK(8, 5));
+        /*       Enable Frequency Loop */
+        ibsd_wr_allchans(ppd, 2, (1 << 4), BMASK(4, 4));
+        /*       Set Timing Loop Bandwidth */
+        ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
+        /*       Enable Timing Loop */
+        ibsd_wr_allchans(ppd, 2, (1 << 3), BMASK(3, 3));
+        msleep(50);
+        /*       Enable DFE
+         *       Set receive adaptation mode.  SDR and DDR adaptation are
+         *       always on, and QDR is initially enabled; later disabled.
+         */
+        qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
+        qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
+        qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
+                            ppd->dd->cspec->r1 ?
+                            QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
+        ppd->cpspec->qdr_dfe_on = 1;
+        /*       Disable LE1  */
+        ibsd_wr_allchans(ppd, 13, (0 << 5), (1 << 5));
+        /*       Disable auto adapt for LE1 */
+        ibsd_wr_allchans(ppd, 1, (0 << 15), BMASK(15, 15));
+        msleep(20);
+        /*       Enable AFE Offset Cancel */
+        ibsd_wr_allchans(ppd, 12, (1 << 12), BMASK(12, 12));
+        /*       Enable Baseline Wander Correction */
+        ibsd_wr_allchans(ppd, 12, (1 << 13), BMASK(13, 13));
+        /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
+        ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
+        /* VGA output common mode */
+        ibsd_wr_allchans(ppd, 12, (3 << 2), BMASK(3, 2));
+
+        return 0;
+}
+
 /* start adjust QMH serdes parameters */
 
 static void set_man_code(struct qib_pportdata *ppd, int chan, int code)
diff --git a/drivers/infiniband/hw/qib/qib_init.c b/drivers/infiniband/hw/qib/qib_init.c
index f3b503936043..7896afbb9ce8 100644
--- a/drivers/infiniband/hw/qib/qib_init.c
+++ b/drivers/infiniband/hw/qib/qib_init.c
@@ -92,9 +92,11 @@ unsigned long *qib_cpulist;
 /* set number of contexts we'll actually use */
 void qib_set_ctxtcnt(struct qib_devdata *dd)
 {
-        if (!qib_cfgctxts)
+        if (!qib_cfgctxts) {
                 dd->cfgctxts = dd->first_user_ctxt + num_online_cpus();
-        else if (qib_cfgctxts < dd->num_pports)
+                if (dd->cfgctxts > dd->ctxtcnt)
+                        dd->cfgctxts = dd->ctxtcnt;
+        } else if (qib_cfgctxts < dd->num_pports)
                 dd->cfgctxts = dd->ctxtcnt;
         else if (qib_cfgctxts <= dd->ctxtcnt)
                 dd->cfgctxts = qib_cfgctxts;
diff --git a/drivers/infiniband/hw/qib/qib_intr.c b/drivers/infiniband/hw/qib/qib_intr.c
index 54a40828a106..a693c56ec8a6 100644
--- a/drivers/infiniband/hw/qib/qib_intr.c
+++ b/drivers/infiniband/hw/qib/qib_intr.c
@@ -131,7 +131,8 @@ void qib_handle_e_ibstatuschanged(struct qib_pportdata *ppd, u64 ibcs)
                         /* start a 75msec timer to clear symbol errors */
                         mod_timer(&ppd->symerr_clear_timer,
                                   msecs_to_jiffies(75));
-                } else if (ltstate == IB_PHYSPORTSTATE_LINKUP) {
+                } else if (ltstate == IB_PHYSPORTSTATE_LINKUP &&
+                           !(ppd->lflags & QIBL_LINKACTIVE)) {
                         /* active, but not active defered */
                         qib_hol_up(ppd); /* useful only for 6120 now */
                         *ppd->statusp |=
diff --git a/drivers/infiniband/hw/qib/qib_keys.c b/drivers/infiniband/hw/qib/qib_keys.c
index 4b80eb153d57..8fd19a47df0c 100644
--- a/drivers/infiniband/hw/qib/qib_keys.c
+++ b/drivers/infiniband/hw/qib/qib_keys.c
@@ -136,7 +136,6 @@ int qib_lkey_ok(struct qib_lkey_table *rkt, struct qib_pd *pd,
         struct qib_mregion *mr;
         unsigned n, m;
         size_t off;
-        int ret = 0;
         unsigned long flags;
 
         /*
@@ -152,6 +151,8 @@ int qib_lkey_ok(struct qib_lkey_table *rkt, struct qib_pd *pd,
                 if (!dev->dma_mr)
                         goto bail;
                 atomic_inc(&dev->dma_mr->refcount);
+                spin_unlock_irqrestore(&rkt->lock, flags);
+
                 isge->mr = dev->dma_mr;
                 isge->vaddr = (void *) sge->addr;
                 isge->length = sge->length;
@@ -170,19 +171,34 @@ int qib_lkey_ok(struct qib_lkey_table *rkt, struct qib_pd *pd,
                      off + sge->length > mr->length ||
                      (mr->access_flags & acc) != acc))
                 goto bail;
+        atomic_inc(&mr->refcount);
+        spin_unlock_irqrestore(&rkt->lock, flags);
 
         off += mr->offset;
-        m = 0;
-        n = 0;
-        while (off >= mr->map[m]->segs[n].length) {
-                off -= mr->map[m]->segs[n].length;
-                n++;
-                if (n >= QIB_SEGSZ) {
-                        m++;
-                        n = 0;
+        if (mr->page_shift) {
+                /*
+                page sizes are uniform power of 2 so no loop is necessary
+                entries_spanned_by_off is the number of times the loop below
+                would have executed.
+                */
+                size_t entries_spanned_by_off;
+
+                entries_spanned_by_off = off >> mr->page_shift;
+                off -= (entries_spanned_by_off << mr->page_shift);
+                m = entries_spanned_by_off/QIB_SEGSZ;
+                n = entries_spanned_by_off%QIB_SEGSZ;
+        } else {
+                m = 0;
+                n = 0;
+                while (off >= mr->map[m]->segs[n].length) {
+                        off -= mr->map[m]->segs[n].length;
+                        n++;
+                        if (n >= QIB_SEGSZ) {
+                                m++;
+                                n = 0;
+                        }
                 }
         }
-        atomic_inc(&mr->refcount);
         isge->mr = mr;
         isge->vaddr = mr->map[m]->segs[n].vaddr + off;
         isge->length = mr->map[m]->segs[n].length - off;
@@ -190,10 +206,10 @@ int qib_lkey_ok(struct qib_lkey_table *rkt, struct qib_pd *pd,
         isge->m = m;
         isge->n = n;
 ok:
-        ret = 1;
+        return 1;
 bail:
         spin_unlock_irqrestore(&rkt->lock, flags);
-        return ret;
+        return 0;
 }
 
 /**
@@ -214,7 +230,6 @@ int qib_rkey_ok(struct qib_qp *qp, struct qib_sge *sge,
         struct qib_mregion *mr;
         unsigned n, m;
         size_t off;
-        int ret = 0;
         unsigned long flags;
 
         /*
@@ -231,6 +246,8 @@ int qib_rkey_ok(struct qib_qp *qp, struct qib_sge *sge,
                 if (!dev->dma_mr)
                         goto bail;
                 atomic_inc(&dev->dma_mr->refcount);
+                spin_unlock_irqrestore(&rkt->lock, flags);
+
                 sge->mr = dev->dma_mr;
                 sge->vaddr = (void *) vaddr;
                 sge->length = len;
@@ -248,19 +265,34 @@ int qib_rkey_ok(struct qib_qp *qp, struct qib_sge *sge,
         if (unlikely(vaddr < mr->iova || off + len > mr->length ||
                      (mr->access_flags & acc) == 0))
                 goto bail;
+        atomic_inc(&mr->refcount);
+        spin_unlock_irqrestore(&rkt->lock, flags);
 
         off += mr->offset;
-        m = 0;
-        n = 0;
-        while (off >= mr->map[m]->segs[n].length) {
-                off -= mr->map[m]->segs[n].length;
-                n++;
-                if (n >= QIB_SEGSZ) {
-                        m++;
-                        n = 0;
+        if (mr->page_shift) {
+                /*
+                page sizes are uniform power of 2 so no loop is necessary
+                entries_spanned_by_off is the number of times the loop below
+                would have executed.
+                */
+                size_t entries_spanned_by_off;
+
+                entries_spanned_by_off = off >> mr->page_shift;
+                off -= (entries_spanned_by_off << mr->page_shift);
+                m = entries_spanned_by_off/QIB_SEGSZ;
+                n = entries_spanned_by_off%QIB_SEGSZ;
+        } else {
+                m = 0;
+                n = 0;
+                while (off >= mr->map[m]->segs[n].length) {
+                        off -= mr->map[m]->segs[n].length;
+                        n++;
+                        if (n >= QIB_SEGSZ) {
+                                m++;
+                                n = 0;
+                        }
                 }
         }
-        atomic_inc(&mr->refcount);
         sge->mr = mr;
         sge->vaddr = mr->map[m]->segs[n].vaddr + off;
         sge->length = mr->map[m]->segs[n].length - off;
@@ -268,10 +300,10 @@ int qib_rkey_ok(struct qib_qp *qp, struct qib_sge *sge,
         sge->m = m;
         sge->n = n;
 ok:
-        ret = 1;
+        return 1;
 bail:
         spin_unlock_irqrestore(&rkt->lock, flags);
-        return ret;
+        return 0;
 }
 
 /*
diff --git a/drivers/infiniband/hw/qib/qib_mad.c b/drivers/infiniband/hw/qib/qib_mad.c
index 94b0d1f3a8f0..5ad224e4a38b 100644
--- a/drivers/infiniband/hw/qib/qib_mad.c
+++ b/drivers/infiniband/hw/qib/qib_mad.c
@@ -668,8 +668,8 @@ static int subn_set_portinfo(struct ib_smp *smp, struct ib_device *ibdev,
         lid = be16_to_cpu(pip->lid);
         /* Must be a valid unicast LID address. */
         if (lid == 0 || lid >= QIB_MULTICAST_LID_BASE)
-                goto err;
-        if (ppd->lid != lid || ppd->lmc != (pip->mkeyprot_resv_lmc & 7)) {
+                smp->status |= IB_SMP_INVALID_FIELD;
+        else if (ppd->lid != lid || ppd->lmc != (pip->mkeyprot_resv_lmc & 7)) {
                 if (ppd->lid != lid)
                         qib_set_uevent_bits(ppd, _QIB_EVENT_LID_CHANGE_BIT);
                 if (ppd->lmc != (pip->mkeyprot_resv_lmc & 7))
@@ -683,8 +683,8 @@ static int subn_set_portinfo(struct ib_smp *smp, struct ib_device *ibdev,
         msl = pip->neighbormtu_mastersmsl & 0xF;
         /* Must be a valid unicast LID address. */
         if (smlid == 0 || smlid >= QIB_MULTICAST_LID_BASE)
-                goto err;
-        if (smlid != ibp->sm_lid || msl != ibp->sm_sl) {
+                smp->status |= IB_SMP_INVALID_FIELD;
+        else if (smlid != ibp->sm_lid || msl != ibp->sm_sl) {
                 spin_lock_irqsave(&ibp->lock, flags);
                 if (ibp->sm_ah) {
                         if (smlid != ibp->sm_lid)
@@ -707,8 +707,9 @@ static int subn_set_portinfo(struct ib_smp *smp, struct ib_device *ibdev,
                 if (lwe == 0xFF)
                         lwe = ppd->link_width_supported;
                 else if (lwe >= 16 || (lwe & ~ppd->link_width_supported))
-                        goto err;
-                set_link_width_enabled(ppd, lwe);
+                        smp->status |= IB_SMP_INVALID_FIELD;
+                else if (lwe != ppd->link_width_enabled)
+                        set_link_width_enabled(ppd, lwe);
         }
 
         lse = pip->linkspeedactive_enabled & 0xF;
@@ -721,8 +722,9 @@ static int subn_set_portinfo(struct ib_smp *smp, struct ib_device *ibdev,
                 if (lse == 15)
                         lse = ppd->link_speed_supported;
                 else if (lse >= 8 || (lse & ~ppd->link_speed_supported))
-                        goto err;
-                set_link_speed_enabled(ppd, lse);
+                        smp->status |= IB_SMP_INVALID_FIELD;
+                else if (lse != ppd->link_speed_enabled)
+                        set_link_speed_enabled(ppd, lse);
         }
 
         /* Set link down default state. */
@@ -738,7 +740,7 @@ static int subn_set_portinfo(struct ib_smp *smp, struct ib_device *ibdev,
                                         IB_LINKINITCMD_POLL);
                 break;
         default:
-                goto err;
+                smp->status |= IB_SMP_INVALID_FIELD;
         }
 
         ibp->mkeyprot = pip->mkeyprot_resv_lmc >> 6;
@@ -748,15 +750,17 @@ static int subn_set_portinfo(struct ib_smp *smp, struct ib_device *ibdev,
 
         mtu = ib_mtu_enum_to_int((pip->neighbormtu_mastersmsl >> 4) & 0xF);
         if (mtu == -1)
-                goto err;
-        qib_set_mtu(ppd, mtu);
+                smp->status |= IB_SMP_INVALID_FIELD;
+        else
+                qib_set_mtu(ppd, mtu);
 
         /* Set operational VLs */
         vls = (pip->operationalvl_pei_peo_fpi_fpo >> 4) & 0xF;
         if (vls) {
                 if (vls > ppd->vls_supported)
-                        goto err;
-                (void) dd->f_set_ib_cfg(ppd, QIB_IB_CFG_OP_VLS, vls);
+                        smp->status |= IB_SMP_INVALID_FIELD;
+                else
+                        (void) dd->f_set_ib_cfg(ppd, QIB_IB_CFG_OP_VLS, vls);
         }
 
         if (pip->mkey_violations == 0)
@@ -770,10 +774,10 @@ static int subn_set_portinfo(struct ib_smp *smp, struct ib_device *ibdev,
 
         ore = pip->localphyerrors_overrunerrors;
         if (set_phyerrthreshold(ppd, (ore >> 4) & 0xF))
-                goto err;
+                smp->status |= IB_SMP_INVALID_FIELD;
 
         if (set_overrunthreshold(ppd, (ore & 0xF)))
-                goto err;
+                smp->status |= IB_SMP_INVALID_FIELD;
 
         ibp->subnet_timeout = pip->clientrereg_resv_subnetto & 0x1F;
 
@@ -792,7 +796,7 @@ static int subn_set_portinfo(struct ib_smp *smp, struct ib_device *ibdev,
         state = pip->linkspeed_portstate & 0xF;
         lstate = (pip->portphysstate_linkdown >> 4) & 0xF;
         if (lstate && !(state == IB_PORT_DOWN || state == IB_PORT_NOP))
-                goto err;
+                smp->status |= IB_SMP_INVALID_FIELD;
 
         /*
          * Only state changes of DOWN, ARM, and ACTIVE are valid
@@ -812,8 +816,10 @@ static int subn_set_portinfo(struct ib_smp *smp, struct ib_device *ibdev,
                         lstate = QIB_IB_LINKDOWN;
                 else if (lstate == 3)
                         lstate = QIB_IB_LINKDOWN_DISABLE;
-                else
-                        goto err;
+                else {
+                        smp->status |= IB_SMP_INVALID_FIELD;
+                        break;
+                }
                 spin_lock_irqsave(&ppd->lflags_lock, flags);
                 ppd->lflags &= ~QIBL_LINKV;
                 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
@@ -835,8 +841,7 @@ static int subn_set_portinfo(struct ib_smp *smp, struct ib_device *ibdev,
                 qib_set_linkstate(ppd, QIB_IB_LINKACTIVE);
                 break;
         default:
-                /* XXX We have already partially updated our state! */
-                goto err;
+                smp->status |= IB_SMP_INVALID_FIELD;
         }
 
         ret = subn_get_portinfo(smp, ibdev, port);
diff --git a/drivers/infiniband/hw/qib/qib_mr.c b/drivers/infiniband/hw/qib/qib_mr.c
index 5f95f0f6385d..08944e2ee334 100644
--- a/drivers/infiniband/hw/qib/qib_mr.c
+++ b/drivers/infiniband/hw/qib/qib_mr.c
@@ -39,7 +39,6 @@
 /* Fast memory region */
 struct qib_fmr {
         struct ib_fmr ibfmr;
-        u8 page_shift;
         struct qib_mregion mr;        /* must be last */
 };
 
@@ -107,6 +106,7 @@ static struct qib_mr *alloc_mr(int count, struct qib_lkey_table *lk_table)
                         goto bail;
         }
         mr->mr.mapsz = m;
+        mr->mr.page_shift = 0;
         mr->mr.max_segs = count;
 
         /*
@@ -231,6 +231,8 @@ struct ib_mr *qib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
         mr->mr.access_flags = mr_access_flags;
         mr->umem = umem;
 
+        if (is_power_of_2(umem->page_size))
+                mr->mr.page_shift = ilog2(umem->page_size);
         m = 0;
         n = 0;
         list_for_each_entry(chunk, &umem->chunk_list, list) {
@@ -390,7 +392,7 @@ struct ib_fmr *qib_alloc_fmr(struct ib_pd *pd, int mr_access_flags,
         fmr->mr.offset = 0;
         fmr->mr.access_flags = mr_access_flags;
         fmr->mr.max_segs = fmr_attr->max_pages;
-        fmr->page_shift = fmr_attr->page_shift;
+        fmr->mr.page_shift = fmr_attr->page_shift;
 
         atomic_set(&fmr->mr.refcount, 0);
         ret = &fmr->ibfmr;
@@ -437,7 +439,7 @@ int qib_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
         spin_lock_irqsave(&rkt->lock, flags);
         fmr->mr.user_base = iova;
         fmr->mr.iova = iova;
-        ps = 1 << fmr->page_shift;
+        ps = 1 << fmr->mr.page_shift;
         fmr->mr.length = list_len * ps;
         m = 0;
         n = 0;
diff --git a/drivers/infiniband/hw/qib/qib_qp.c b/drivers/infiniband/hw/qib/qib_qp.c
index 6c39851d2ded..e16751f8639e 100644
--- a/drivers/infiniband/hw/qib/qib_qp.c
+++ b/drivers/infiniband/hw/qib/qib_qp.c
@@ -48,13 +48,12 @@ static inline unsigned mk_qpn(struct qib_qpn_table *qpt,
 
 static inline unsigned find_next_offset(struct qib_qpn_table *qpt,
                                         struct qpn_map *map, unsigned off,
-                                        unsigned r)
+                                        unsigned n)
 {
         if (qpt->mask) {
                 off++;
-                if ((off & qpt->mask) >> 1 != r)
-                        off = ((off & qpt->mask) ?
-                                (off | qpt->mask) + 1 : off) | (r << 1);
+                if (((off & qpt->mask) >> 1) >= n)
+                        off = (off | qpt->mask) + 2;
         } else
                 off = find_next_zero_bit(map->page, BITS_PER_PAGE, off);
         return off;
@@ -123,7 +122,6 @@ static int alloc_qpn(struct qib_devdata *dd, struct qib_qpn_table *qpt,
         u32 i, offset, max_scan, qpn;
         struct qpn_map *map;
         u32 ret;
-        int r;
 
         if (type == IB_QPT_SMI || type == IB_QPT_GSI) {
                 unsigned n;
@@ -139,15 +137,11 @@ static int alloc_qpn(struct qib_devdata *dd, struct qib_qpn_table *qpt,
                 goto bail;
         }
 
-        r = smp_processor_id();
-        if (r >= dd->n_krcv_queues)
-                r %= dd->n_krcv_queues;
-        qpn = qpt->last + 1;
+        qpn = qpt->last + 2;
         if (qpn >= QPN_MAX)
                 qpn = 2;
-        if (qpt->mask && ((qpn & qpt->mask) >> 1) != r)
-                qpn = ((qpn & qpt->mask) ? (qpn | qpt->mask) + 1 : qpn) |
-                        (r << 1);
+        if (qpt->mask && ((qpn & qpt->mask) >> 1) >= dd->n_krcv_queues)
+                qpn = (qpn | qpt->mask) + 2;
         offset = qpn & BITS_PER_PAGE_MASK;
         map = &qpt->map[qpn / BITS_PER_PAGE];
         max_scan = qpt->nmaps - !offset;
@@ -163,7 +157,8 @@ static int alloc_qpn(struct qib_devdata *dd, struct qib_qpn_table *qpt,
                                 ret = qpn;
                                 goto bail;
                         }
-                        offset = find_next_offset(qpt, map, offset, r);
+                        offset = find_next_offset(qpt, map, offset,
+                                dd->n_krcv_queues);
                         qpn = mk_qpn(qpt, map, offset);
                         /*
                          * This test differs from alloc_pidmap().
@@ -183,13 +178,13 @@ static int alloc_qpn(struct qib_devdata *dd, struct qib_qpn_table *qpt,
                         if (qpt->nmaps == QPNMAP_ENTRIES)
                                 break;
                         map = &qpt->map[qpt->nmaps++];
-                        offset = qpt->mask ? (r << 1) : 0;
+                        offset = 0;
                 } else if (map < &qpt->map[qpt->nmaps]) {
                         ++map;
-                        offset = qpt->mask ? (r << 1) : 0;
+                        offset = 0;
                 } else {
                         map = &qpt->map[0];
-                        offset = qpt->mask ? (r << 1) : 2;
+                        offset = 2;
                 }
                 qpn = mk_qpn(qpt, map, offset);
         }
@@ -468,6 +463,10 @@ int qib_error_qp(struct qib_qp *qp, enum ib_wc_status err)
                 qp->s_flags &= ~(QIB_S_TIMER | QIB_S_WAIT_RNR);
                 del_timer(&qp->s_timer);
         }
+
+        if (qp->s_flags & QIB_S_ANY_WAIT_SEND)
+                qp->s_flags &= ~QIB_S_ANY_WAIT_SEND;
+
         spin_lock(&dev->pending_lock);
         if (!list_empty(&qp->iowait) && !(qp->s_flags & QIB_S_BUSY)) {
                 qp->s_flags &= ~QIB_S_ANY_WAIT_IO;
@@ -1061,7 +1060,6 @@ struct ib_qp *qib_create_qp(struct ib_pd *ibpd,
                 }
                 qp->ibqp.qp_num = err;
                 qp->port_num = init_attr->port_num;
-                qp->processor_id = smp_processor_id();
                 qib_reset_qp(qp, init_attr->qp_type);
                 break;
 
diff --git a/drivers/infiniband/hw/qib/qib_rc.c b/drivers/infiniband/hw/qib/qib_rc.c
index 955fb7157793..8245237b67ce 100644
--- a/drivers/infiniband/hw/qib/qib_rc.c
+++ b/drivers/infiniband/hw/qib/qib_rc.c
@@ -1407,6 +1407,7 @@ static void qib_rc_rcv_resp(struct qib_ibport *ibp,
                             struct qib_ctxtdata *rcd)
 {
         struct qib_swqe *wqe;
+        struct qib_pportdata *ppd = ppd_from_ibp(ibp);
         enum ib_wc_status status;
         unsigned long flags;
         int diff;
@@ -1414,6 +1415,29 @@ static void qib_rc_rcv_resp(struct qib_ibport *ibp,
         u32 aeth;
         u64 val;
 
+        if (opcode != OP(RDMA_READ_RESPONSE_MIDDLE)) {
+                /*
+                 * If ACK'd PSN on SDMA busy list try to make progress to
+                 * reclaim SDMA credits.
+                 */
+                if ((qib_cmp24(psn, qp->s_sending_psn) >= 0) &&
+                    (qib_cmp24(qp->s_sending_psn, qp->s_sending_hpsn) <= 0)) {
+
+                        /*
+                         * If send tasklet not running attempt to progress
+                         * SDMA queue.
+                         */
+                        if (!(qp->s_flags & QIB_S_BUSY)) {
+                                /* Acquire SDMA Lock */
+                                spin_lock_irqsave(&ppd->sdma_lock, flags);
+                                /* Invoke sdma make progress */
+                                qib_sdma_make_progress(ppd);
+                                /* Release SDMA Lock */
+                                spin_unlock_irqrestore(&ppd->sdma_lock, flags);
+                        }
+                }
+        }
+
         spin_lock_irqsave(&qp->s_lock, flags);
 
         /* Ignore invalid responses. */
diff --git a/drivers/infiniband/hw/qib/qib_ud.c b/drivers/infiniband/hw/qib/qib_ud.c
index e1b3da2a1f85..4a51fd1e9cb7 100644
--- a/drivers/infiniband/hw/qib/qib_ud.c
+++ b/drivers/infiniband/hw/qib/qib_ud.c
@@ -445,13 +445,14 @@ void qib_ud_rcv(struct qib_ibport *ibp, struct qib_ib_header *hdr,
         qkey = be32_to_cpu(ohdr->u.ud.deth[0]);
         src_qp = be32_to_cpu(ohdr->u.ud.deth[1]) & QIB_QPN_MASK;
 
-        /* Get the number of bytes the message was padded by. */
+        /*
+         * Get the number of bytes the message was padded by
+         * and drop incomplete packets.
+         */
         pad = (be32_to_cpu(ohdr->bth[0]) >> 20) & 3;
-        if (unlikely(tlen < (hdrsize + pad + 4))) {
-                /* Drop incomplete packets. */
-                ibp->n_pkt_drops++;
-                goto bail;
-        }
+        if (unlikely(tlen < (hdrsize + pad + 4)))
+                goto drop;
+
         tlen -= hdrsize + pad + 4;
 
         /*
@@ -460,10 +461,8 @@ void qib_ud_rcv(struct qib_ibport *ibp, struct qib_ib_header *hdr,
          */
         if (qp->ibqp.qp_num) {
                 if (unlikely(hdr->lrh[1] == IB_LID_PERMISSIVE ||
-                             hdr->lrh[3] == IB_LID_PERMISSIVE)) {
-                        ibp->n_pkt_drops++;
-                        goto bail;
-                }
+                             hdr->lrh[3] == IB_LID_PERMISSIVE))
+                        goto drop;
                 if (qp->ibqp.qp_num > 1) {
                         u16 pkey1, pkey2;
 
@@ -476,7 +475,7 @@ void qib_ud_rcv(struct qib_ibport *ibp, struct qib_ib_header *hdr,
                                                 0xF,
                                               src_qp, qp->ibqp.qp_num,
                                               hdr->lrh[3], hdr->lrh[1]);
-                                goto bail;
+                                return;
                         }
                 }
                 if (unlikely(qkey != qp->qkey)) {
@@ -484,30 +483,24 @@ void qib_ud_rcv(struct qib_ibport *ibp, struct qib_ib_header *hdr,
                                       (be16_to_cpu(hdr->lrh[0]) >> 4) & 0xF,
                                       src_qp, qp->ibqp.qp_num,
                                       hdr->lrh[3], hdr->lrh[1]);
-                        goto bail;
+                        return;
                 }
                 /* Drop invalid MAD packets (see 13.5.3.1). */
                 if (unlikely(qp->ibqp.qp_num == 1 &&
                              (tlen != 256 ||
-                              (be16_to_cpu(hdr->lrh[0]) >> 12) == 15))) {
-                        ibp->n_pkt_drops++;
-                        goto bail;
-                }
+                              (be16_to_cpu(hdr->lrh[0]) >> 12) == 15)))
+                        goto drop;
         } else {
                 struct ib_smp *smp;
 
                 /* Drop invalid MAD packets (see 13.5.3.1). */
-                if (tlen != 256 || (be16_to_cpu(hdr->lrh[0]) >> 12) != 15) {
-                        ibp->n_pkt_drops++;
-                        goto bail;
-                }
+                if (tlen != 256 || (be16_to_cpu(hdr->lrh[0]) >> 12) != 15)
+                        goto drop;
                 smp = (struct ib_smp *) data;
                 if ((hdr->lrh[1] == IB_LID_PERMISSIVE ||
                      hdr->lrh[3] == IB_LID_PERMISSIVE) &&
-                    smp->mgmt_class != IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) {
-                        ibp->n_pkt_drops++;
-                        goto bail;
-                }
+                    smp->mgmt_class != IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE)
+                        goto drop;
         }
 
         /*
@@ -519,14 +512,12 @@ void qib_ud_rcv(struct qib_ibport *ibp, struct qib_ib_header *hdr,
             opcode == IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE) {
                 wc.ex.imm_data = ohdr->u.ud.imm_data;
                 wc.wc_flags = IB_WC_WITH_IMM;
-                hdrsize += sizeof(u32);
+                tlen -= sizeof(u32);
         } else if (opcode == IB_OPCODE_UD_SEND_ONLY) {
                 wc.ex.imm_data = 0;
                 wc.wc_flags = 0;
-        } else {
-                ibp->n_pkt_drops++;
-                goto bail;
-        }
+        } else
+                goto drop;
 
         /*
          * A GRH is expected to preceed the data even if not
@@ -556,8 +547,7 @@ void qib_ud_rcv(struct qib_ibport *ibp, struct qib_ib_header *hdr,
         /* Silently drop packets which are too big. */
         if (unlikely(wc.byte_len > qp->r_len)) {
                 qp->r_flags |= QIB_R_REUSE_SGE;
-                ibp->n_pkt_drops++;
-                return;
+                goto drop;
         }
         if (has_grh) {
                 qib_copy_sge(&qp->r_sge, &hdr->u.l.grh,
@@ -594,5 +584,8 @@ void qib_ud_rcv(struct qib_ibport *ibp, struct qib_ib_header *hdr,
         qib_cq_enter(to_icq(qp->ibqp.recv_cq), &wc,
                      (ohdr->bth[0] &
                         cpu_to_be32(IB_BTH_SOLICITED)) != 0);
-bail:;
+        return;
+
+drop:
+        ibp->n_pkt_drops++;
 }
diff --git a/drivers/infiniband/hw/qib/qib_user_sdma.c b/drivers/infiniband/hw/qib/qib_user_sdma.c
index 4c19e06b5e85..66208bcd7c13 100644
--- a/drivers/infiniband/hw/qib/qib_user_sdma.c
+++ b/drivers/infiniband/hw/qib/qib_user_sdma.c
@@ -382,6 +382,7 @@ static void qib_user_sdma_free_pkt_list(struct device *dev,
 
                 kmem_cache_free(pq->pkt_slab, pkt);
         }
+        INIT_LIST_HEAD(list);
 }
 
 /*
diff --git a/drivers/infiniband/hw/qib/qib_verbs.h b/drivers/infiniband/hw/qib/qib_verbs.h
index bd57c1273225..63b22a9a7feb 100644
--- a/drivers/infiniband/hw/qib/qib_verbs.h
+++ b/drivers/infiniband/hw/qib/qib_verbs.h
@@ -301,6 +301,7 @@ struct qib_mregion {
         int access_flags;
         u32 max_segs;           /* number of qib_segs in all the arrays */
         u32 mapsz;              /* size of the map array */
+        u8  page_shift;         /* 0 - non unform/non powerof2 sizes */
         atomic_t refcount;
         struct qib_segarray *map[0];    /* the segments */
 };
@@ -435,7 +436,6 @@ struct qib_qp {
         spinlock_t r_lock;      /* used for APM */
         spinlock_t s_lock;
         atomic_t s_dma_busy;
-        unsigned processor_id;  /* Processor ID QP is bound to */
         u32 s_flags;
         u32 s_cur_size;         /* size of send packet in bytes */
         u32 s_len;              /* total length of s_sge */
@@ -813,13 +813,8 @@ extern struct workqueue_struct *qib_cq_wq;
  */
 static inline void qib_schedule_send(struct qib_qp *qp)
 {
-        if (qib_send_ok(qp)) {
-                if (qp->processor_id == smp_processor_id())
-                        queue_work(qib_wq, &qp->s_work);
-                else
-                        queue_work_on(qp->processor_id,
-                                      qib_wq, &qp->s_work);
-        }
+        if (qib_send_ok(qp))
+                queue_work(qib_wq, &qp->s_work);
 }
 
 static inline int qib_pkey_ok(u16 pkey1, u16 pkey2)
diff --git a/drivers/infiniband/ulp/ipoib/Kconfig b/drivers/infiniband/ulp/ipoib/Kconfig
index 9d9a9dc51f18..55855eeabae7 100644
--- a/drivers/infiniband/ulp/ipoib/Kconfig
+++ b/drivers/infiniband/ulp/ipoib/Kconfig
@@ -1,7 +1,6 @@
 config INFINIBAND_IPOIB
         tristate "IP-over-InfiniBand"
         depends on NETDEVICES && INET && (IPV6 || IPV6=n)
-        select INET_LRO
         ---help---
           Support for the IP-over-InfiniBand protocol (IPoIB). This
           transports IP packets over InfiniBand so you can use your IB
diff --git a/drivers/infiniband/ulp/ipoib/ipoib.h b/drivers/infiniband/ulp/ipoib/ipoib.h
index 753a983a5fdc..ab97f92fc257 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib.h
+++ b/drivers/infiniband/ulp/ipoib/ipoib.h
@@ -50,7 +50,7 @@
 #include <rdma/ib_verbs.h>
 #include <rdma/ib_pack.h>
 #include <rdma/ib_sa.h>
-#include <linux/inet_lro.h>
+#include <linux/sched.h>
 
 /* constants */
 
@@ -100,9 +100,6 @@ enum {
         IPOIB_MCAST_FLAG_BUSY     = 2,  /* joining or already joined */
         IPOIB_MCAST_FLAG_ATTACHED = 3,
 
-        IPOIB_MAX_LRO_DESCRIPTORS = 8,
-        IPOIB_LRO_MAX_AGGR        = 64,
-
         MAX_SEND_CQE              = 16,
         IPOIB_CM_COPYBREAK        = 256,
 };
@@ -262,11 +259,6 @@ struct ipoib_ethtool_st {
         u16     max_coalesced_frames;
 };
 
-struct ipoib_lro {
-        struct net_lro_mgr lro_mgr;
-        struct net_lro_desc lro_desc[IPOIB_MAX_LRO_DESCRIPTORS];
-};
-
 /*
  * Device private locking: network stack tx_lock protects members used
  * in TX fast path, lock protects everything else.  lock nests inside
@@ -352,8 +344,6 @@ struct ipoib_dev_priv {
         int     hca_caps;
         struct ipoib_ethtool_st ethtool;
         struct timer_list poll_timer;
-
-        struct ipoib_lro lro;
 };
 
 struct ipoib_ah {
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_cm.c b/drivers/infiniband/ulp/ipoib/ipoib_cm.c
index bb1004114dec..c1c49f2d35b5 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib_cm.c
+++ b/drivers/infiniband/ulp/ipoib/ipoib_cm.c
@@ -1480,6 +1480,7 @@ static ssize_t set_mode(struct device *d, struct device_attribute *attr,
 
                 if (test_bit(IPOIB_FLAG_CSUM, &priv->flags)) {
                         dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
+                        priv->dev->features |= NETIF_F_GRO;
                         if (priv->hca_caps & IB_DEVICE_UD_TSO)
                                 dev->features |= NETIF_F_TSO;
                 }
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_ethtool.c b/drivers/infiniband/ulp/ipoib/ipoib_ethtool.c
index 1a1657c82edd..19f7f5206f78 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib_ethtool.c
+++ b/drivers/infiniband/ulp/ipoib/ipoib_ethtool.c
@@ -106,63 +106,12 @@ static int ipoib_set_coalesce(struct net_device *dev,
         return 0;
 }
 
-static const char ipoib_stats_keys[][ETH_GSTRING_LEN] = {
-        "LRO aggregated", "LRO flushed",
-        "LRO avg aggr", "LRO no desc"
-};
-
-static void ipoib_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
-{
-        switch (stringset) {
-        case ETH_SS_STATS:
-                memcpy(data, *ipoib_stats_keys, sizeof(ipoib_stats_keys));
-                break;
-        }
-}
-
-static int ipoib_get_sset_count(struct net_device *dev, int sset)
-{
-        switch (sset) {
-        case ETH_SS_STATS:
-                return ARRAY_SIZE(ipoib_stats_keys);
-        default:
-                return -EOPNOTSUPP;
-        }
-}
-
-static void ipoib_get_ethtool_stats(struct net_device *dev,
-                                struct ethtool_stats *stats, uint64_t *data)
-{
-        struct ipoib_dev_priv *priv = netdev_priv(dev);
-        int index = 0;
-
-        /* Get LRO statistics */
-        data[index++] = priv->lro.lro_mgr.stats.aggregated;
-        data[index++] = priv->lro.lro_mgr.stats.flushed;
-        if (priv->lro.lro_mgr.stats.flushed)
-                data[index++] = priv->lro.lro_mgr.stats.aggregated /
-                                priv->lro.lro_mgr.stats.flushed;
-        else
-                data[index++] = 0;
-        data[index++] = priv->lro.lro_mgr.stats.no_desc;
-}
-
-static int ipoib_set_flags(struct net_device *dev, u32 flags)
-{
-        return ethtool_op_set_flags(dev, flags, ETH_FLAG_LRO);
-}
-
 static const struct ethtool_ops ipoib_ethtool_ops = {
         .get_drvinfo            = ipoib_get_drvinfo,
         .get_rx_csum            = ipoib_get_rx_csum,
         .set_tso                = ipoib_set_tso,
         .get_coalesce           = ipoib_get_coalesce,
         .set_coalesce           = ipoib_set_coalesce,
-        .get_flags              = ethtool_op_get_flags,
-        .set_flags              = ipoib_set_flags,
-        .get_strings            = ipoib_get_strings,
-        .get_sset_count         = ipoib_get_sset_count,
-        .get_ethtool_stats      = ipoib_get_ethtool_stats,
 };
 
 void ipoib_set_ethtool_ops(struct net_device *dev)
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_ib.c b/drivers/infiniband/ulp/ipoib/ipoib_ib.c
index dfa71903d6e4..806d0292dc39 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib_ib.c
+++ b/drivers/infiniband/ulp/ipoib/ipoib_ib.c
@@ -295,10 +295,7 @@ static void ipoib_ib_handle_rx_wc(struct net_device *dev, struct ib_wc *wc)
         if (test_bit(IPOIB_FLAG_CSUM, &priv->flags) && likely(wc->csum_ok))
                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 
-        if (dev->features & NETIF_F_LRO)
-                lro_receive_skb(&priv->lro.lro_mgr, skb, NULL);
-        else
-                netif_receive_skb(skb);
+        napi_gro_receive(&priv->napi, skb);
 
 repost:
         if (unlikely(ipoib_ib_post_receive(dev, wr_id)))
@@ -450,9 +447,6 @@ poll_more:
         }
 
         if (done < budget) {
-                if (dev->features & NETIF_F_LRO)
-                        lro_flush_all(&priv->lro.lro_mgr);
-
                 napi_complete(napi);
                 if (unlikely(ib_req_notify_cq(priv->recv_cq,
                                               IB_CQ_NEXT_COMP |
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_main.c b/drivers/infiniband/ulp/ipoib/ipoib_main.c
index 9ff7bc73ed95..7a07a728fe0d 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib_main.c
+++ b/drivers/infiniband/ulp/ipoib/ipoib_main.c
@@ -60,15 +60,6 @@ MODULE_PARM_DESC(send_queue_size, "Number of descriptors in send queue");
 module_param_named(recv_queue_size, ipoib_recvq_size, int, 0444);
 MODULE_PARM_DESC(recv_queue_size, "Number of descriptors in receive queue");
 
-static int lro;
-module_param(lro, bool, 0444);
-MODULE_PARM_DESC(lro,  "Enable LRO (Large Receive Offload)");
-
-static int lro_max_aggr = IPOIB_LRO_MAX_AGGR;
-module_param(lro_max_aggr, int, 0644);
-MODULE_PARM_DESC(lro_max_aggr, "LRO: Max packets to be aggregated "
-                "(default = 64)");
-
 #ifdef CONFIG_INFINIBAND_IPOIB_DEBUG
 int ipoib_debug_level;
 
@@ -976,54 +967,6 @@ static const struct header_ops ipoib_header_ops = {
         .create = ipoib_hard_header,
 };
 
-static int get_skb_hdr(struct sk_buff *skb, void **iphdr,
-                       void **tcph, u64 *hdr_flags, void *priv)
-{
-        unsigned int ip_len;
-        struct iphdr *iph;
-
-        if (unlikely(skb->protocol != htons(ETH_P_IP)))
-                return -1;
-
-        /*
-         * In the future we may add an else clause that verifies the
-         * checksum and allows devices which do not calculate checksum
-         * to use LRO.
-         */
-        if (unlikely(skb->ip_summed != CHECKSUM_UNNECESSARY))
-                return -1;
-
-        /* Check for non-TCP packet */
-        skb_reset_network_header(skb);
-        iph = ip_hdr(skb);
-        if (iph->protocol != IPPROTO_TCP)
-                return -1;
-
-        ip_len = ip_hdrlen(skb);
-        skb_set_transport_header(skb, ip_len);
-        *tcph = tcp_hdr(skb);
-
-        /* check if IP header and TCP header are complete */
-        if (ntohs(iph->tot_len) < ip_len + tcp_hdrlen(skb))
-                return -1;
-
-        *hdr_flags = LRO_IPV4 | LRO_TCP;
-        *iphdr = iph;
-
-        return 0;
-}
-
-static void ipoib_lro_setup(struct ipoib_dev_priv *priv)
-{
-        priv->lro.lro_mgr.max_aggr       = lro_max_aggr;
-        priv->lro.lro_mgr.max_desc       = IPOIB_MAX_LRO_DESCRIPTORS;
-        priv->lro.lro_mgr.lro_arr        = priv->lro.lro_desc;
-        priv->lro.lro_mgr.get_skb_header = get_skb_hdr;
-        priv->lro.lro_mgr.features       = LRO_F_NAPI;
-        priv->lro.lro_mgr.dev            = priv->dev;
-        priv->lro.lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
-}
-
 static const struct net_device_ops ipoib_netdev_ops = {
         .ndo_open                = ipoib_open,
         .ndo_stop                = ipoib_stop,
@@ -1067,8 +1010,6 @@ static void ipoib_setup(struct net_device *dev)
 
         priv->dev = dev;
 
-        ipoib_lro_setup(priv);
-
         spin_lock_init(&priv->lock);
 
         mutex_init(&priv->vlan_mutex);
@@ -1218,8 +1159,7 @@ int ipoib_set_dev_features(struct ipoib_dev_priv *priv, struct ib_device *hca)
                 priv->dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
         }
 
-        if (lro)
-                priv->dev->features |= NETIF_F_LRO;
+        priv->dev->features |= NETIF_F_GRO;
 
         if (priv->dev->features & NETIF_F_SG && priv->hca_caps & IB_DEVICE_UD_TSO)
                 priv->dev->features |= NETIF_F_TSO;
diff --git a/drivers/infiniband/ulp/srp/ib_srp.c b/drivers/infiniband/ulp/srp/ib_srp.c
index 1e1e347a7715..4b62105ed1e8 100644
--- a/drivers/infiniband/ulp/srp/ib_srp.c
+++ b/drivers/infiniband/ulp/srp/ib_srp.c
@@ -441,18 +441,28 @@ static void srp_disconnect_target(struct srp_target_port *target)
         wait_for_completion(&target->done);
 }
 
+static bool srp_change_state(struct srp_target_port *target,
+                            enum srp_target_state old,
+                            enum srp_target_state new)
+{
+        bool changed = false;
+
+        spin_lock_irq(&target->lock);
+        if (target->state == old) {
+                target->state = new;
+                changed = true;
+        }
+        spin_unlock_irq(&target->lock);
+        return changed;
+}
+
 static void srp_remove_work(struct work_struct *work)
 {
         struct srp_target_port *target =
                 container_of(work, struct srp_target_port, work);
 
-        spin_lock_irq(target->scsi_host->host_lock);
-        if (target->state != SRP_TARGET_DEAD) {
-                spin_unlock_irq(target->scsi_host->host_lock);
+        if (!srp_change_state(target, SRP_TARGET_DEAD, SRP_TARGET_REMOVED))
                 return;
-        }
-        target->state = SRP_TARGET_REMOVED;
-        spin_unlock_irq(target->scsi_host->host_lock);
 
         spin_lock(&target->srp_host->target_lock);
         list_del(&target->list);
@@ -539,33 +549,34 @@ static void srp_unmap_data(struct scsi_cmnd *scmnd,
                         scsi_sg_count(scmnd), scmnd->sc_data_direction);
 }
 
-static void srp_remove_req(struct srp_target_port *target, struct srp_request *req)
+static void srp_remove_req(struct srp_target_port *target,
+                           struct srp_request *req, s32 req_lim_delta)
 {
+        unsigned long flags;
+
         srp_unmap_data(req->scmnd, target, req);
-        list_move_tail(&req->list, &target->free_reqs);
+        spin_lock_irqsave(&target->lock, flags);
+        target->req_lim += req_lim_delta;
+        req->scmnd = NULL;
+        list_add_tail(&req->list, &target->free_reqs);
+        spin_unlock_irqrestore(&target->lock, flags);
 }
 
 static void srp_reset_req(struct srp_target_port *target, struct srp_request *req)
 {
         req->scmnd->result = DID_RESET << 16;
         req->scmnd->scsi_done(req->scmnd);
-        srp_remove_req(target, req);
+        srp_remove_req(target, req, 0);
 }
 
 static int srp_reconnect_target(struct srp_target_port *target)
 {
         struct ib_qp_attr qp_attr;
-        struct srp_request *req, *tmp;
         struct ib_wc wc;
-        int ret;
+        int i, ret;
 
-        spin_lock_irq(target->scsi_host->host_lock);
-        if (target->state != SRP_TARGET_LIVE) {
-                spin_unlock_irq(target->scsi_host->host_lock);
+        if (!srp_change_state(target, SRP_TARGET_LIVE, SRP_TARGET_CONNECTING))
                 return -EAGAIN;
-        }
-        target->state = SRP_TARGET_CONNECTING;
-        spin_unlock_irq(target->scsi_host->host_lock);
 
         srp_disconnect_target(target);
         /*
@@ -590,27 +601,23 @@ static int srp_reconnect_target(struct srp_target_port *target)
         while (ib_poll_cq(target->send_cq, 1, &wc) > 0)
                 ; /* nothing */
 
-        spin_lock_irq(target->scsi_host->host_lock);
-        list_for_each_entry_safe(req, tmp, &target->req_queue, list)
-                srp_reset_req(target, req);
-        spin_unlock_irq(target->scsi_host->host_lock);
+        for (i = 0; i < SRP_CMD_SQ_SIZE; ++i) {
+                struct srp_request *req = &target->req_ring[i];
+                if (req->scmnd)
+                        srp_reset_req(target, req);
+        }
 
-        target->rx_head  = 0;
-        target->tx_head  = 0;
-        target->tx_tail  = 0;
+        INIT_LIST_HEAD(&target->free_tx);
+        for (i = 0; i < SRP_SQ_SIZE; ++i)
+                list_add(&target->tx_ring[i]->list, &target->free_tx);
 
         target->qp_in_error = 0;
         ret = srp_connect_target(target);
         if (ret)
                 goto err;
 
-        spin_lock_irq(target->scsi_host->host_lock);
-        if (target->state == SRP_TARGET_CONNECTING) {
-                ret = 0;
-                target->state = SRP_TARGET_LIVE;
-        } else
+        if (!srp_change_state(target, SRP_TARGET_CONNECTING, SRP_TARGET_LIVE))
                 ret = -EAGAIN;
-        spin_unlock_irq(target->scsi_host->host_lock);
 
         return ret;
 
@@ -620,17 +627,20 @@ err:
 
         /*
          * We couldn't reconnect, so kill our target port off.
-         * However, we have to defer the real removal because we might
-         * be in the context of the SCSI error handler now, which
-         * would deadlock if we call scsi_remove_host().
+         * However, we have to defer the real removal because we
+         * are in the context of the SCSI error handler now, which
+         * will deadlock if we call scsi_remove_host().
+         *
+         * Schedule our work inside the lock to avoid a race with
+         * the flush_scheduled_work() in srp_remove_one().
          */
-        spin_lock_irq(target->scsi_host->host_lock);
+        spin_lock_irq(&target->lock);
         if (target->state == SRP_TARGET_CONNECTING) {
                 target->state = SRP_TARGET_DEAD;
                 INIT_WORK(&target->work, srp_remove_work);
                 schedule_work(&target->work);
         }
-        spin_unlock_irq(target->scsi_host->host_lock);
+        spin_unlock_irq(&target->lock);
 
         return ret;
 }
@@ -758,7 +768,7 @@ static int srp_map_data(struct scsi_cmnd *scmnd, struct srp_target_port *target,
                 struct srp_direct_buf *buf = (void *) cmd->add_data;
 
                 buf->va  = cpu_to_be64(ib_sg_dma_address(ibdev, scat));
-                buf->key = cpu_to_be32(dev->mr->rkey);
+                buf->key = cpu_to_be32(target->rkey);
                 buf->len = cpu_to_be32(ib_sg_dma_len(ibdev, scat));
         } else if (srp_map_fmr(target, scat, count, req,
                                (void *) cmd->add_data)) {
@@ -783,7 +793,7 @@ static int srp_map_data(struct scsi_cmnd *scmnd, struct srp_target_port *target,
                         buf->desc_list[i].va  =
                                 cpu_to_be64(ib_sg_dma_address(ibdev, sg));
                         buf->desc_list[i].key =
-                                cpu_to_be32(dev->mr->rkey);
+                                cpu_to_be32(target->rkey);
                         buf->desc_list[i].len = cpu_to_be32(dma_len);
                         datalen += dma_len;
                 }
@@ -796,7 +806,7 @@ static int srp_map_data(struct scsi_cmnd *scmnd, struct srp_target_port *target,
                 buf->table_desc.va  =
                         cpu_to_be64(req->cmd->dma + sizeof *cmd + sizeof *buf);
                 buf->table_desc.key =
-                        cpu_to_be32(target->srp_host->srp_dev->mr->rkey);
+                        cpu_to_be32(target->rkey);
                 buf->table_desc.len =
                         cpu_to_be32(count * sizeof (struct srp_direct_buf));
 
@@ -812,9 +822,23 @@ static int srp_map_data(struct scsi_cmnd *scmnd, struct srp_target_port *target,
 }
 
 /*
- * Must be called with target->scsi_host->host_lock held to protect
- * req_lim and tx_head.  Lock cannot be dropped between call here and
- * call to __srp_post_send().
+ * Return an IU and possible credit to the free pool
+ */
+static void srp_put_tx_iu(struct srp_target_port *target, struct srp_iu *iu,
+                          enum srp_iu_type iu_type)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&target->lock, flags);
+        list_add(&iu->list, &target->free_tx);
+        if (iu_type != SRP_IU_RSP)
+                ++target->req_lim;
+        spin_unlock_irqrestore(&target->lock, flags);
+}
+
+/*
+ * Must be called with target->lock held to protect req_lim and free_tx.
+ * If IU is not sent, it must be returned using srp_put_tx_iu().
  *
  * Note:
  * An upper limit for the number of allocated information units for each
@@ -833,83 +857,59 @@ static struct srp_iu *__srp_get_tx_iu(struct srp_target_port *target,
 
         srp_send_completion(target->send_cq, target);
 
-        if (target->tx_head - target->tx_tail >= SRP_SQ_SIZE)
+        if (list_empty(&target->free_tx))
                 return NULL;
 
         /* Initiator responses to target requests do not consume credits */
-        if (target->req_lim <= rsv && iu_type != SRP_IU_RSP) {
-                ++target->zero_req_lim;
-                return NULL;
+        if (iu_type != SRP_IU_RSP) {
+                if (target->req_lim <= rsv) {
+                        ++target->zero_req_lim;
+                        return NULL;
+                }
+
+                --target->req_lim;
         }
 
-        iu = target->tx_ring[target->tx_head & SRP_SQ_MASK];
-        iu->type = iu_type;
+        iu = list_first_entry(&target->free_tx, struct srp_iu, list);
+        list_del(&iu->list);
         return iu;
 }
 
-/*
- * Must be called with target->scsi_host->host_lock held to protect
- * req_lim and tx_head.
- */
-static int __srp_post_send(struct srp_target_port *target,
-                           struct srp_iu *iu, int len)
+static int srp_post_send(struct srp_target_port *target,
+                         struct srp_iu *iu, int len)
 {
         struct ib_sge list;
         struct ib_send_wr wr, *bad_wr;
-        int ret = 0;
 
         list.addr   = iu->dma;
         list.length = len;
-        list.lkey   = target->srp_host->srp_dev->mr->lkey;
+        list.lkey   = target->lkey;
 
         wr.next       = NULL;
-        wr.wr_id      = target->tx_head & SRP_SQ_MASK;
+        wr.wr_id      = (uintptr_t) iu;
         wr.sg_list    = &list;
         wr.num_sge    = 1;
         wr.opcode     = IB_WR_SEND;
         wr.send_flags = IB_SEND_SIGNALED;
 
-        ret = ib_post_send(target->qp, &wr, &bad_wr);
-
-        if (!ret) {
-                ++target->tx_head;
-                if (iu->type != SRP_IU_RSP)
-                        --target->req_lim;
-        }
-
-        return ret;
+        return ib_post_send(target->qp, &wr, &bad_wr);
 }
 
-static int srp_post_recv(struct srp_target_port *target)
+static int srp_post_recv(struct srp_target_port *target, struct srp_iu *iu)
 {
-        unsigned long flags;
-        struct srp_iu *iu;
-        struct ib_sge list;
         struct ib_recv_wr wr, *bad_wr;
-        unsigned int next;
-        int ret;
-
-        spin_lock_irqsave(target->scsi_host->host_lock, flags);
-
-        next     = target->rx_head & SRP_RQ_MASK;
-        wr.wr_id = next;
-        iu       = target->rx_ring[next];
+        struct ib_sge list;
 
         list.addr   = iu->dma;
         list.length = iu->size;
-        list.lkey   = target->srp_host->srp_dev->mr->lkey;
+        list.lkey   = target->lkey;
 
         wr.next     = NULL;
+        wr.wr_id    = (uintptr_t) iu;
         wr.sg_list  = &list;
         wr.num_sge  = 1;
 
-        ret = ib_post_recv(target->qp, &wr, &bad_wr);
-        if (!ret)
-                ++target->rx_head;
-
-        spin_unlock_irqrestore(target->scsi_host->host_lock, flags);
-
-        return ret;
+        return ib_post_recv(target->qp, &wr, &bad_wr);
 }
 
 static void srp_process_rsp(struct srp_target_port *target, struct srp_rsp *rsp)
@@ -917,23 +917,18 @@ static void srp_process_rsp(struct srp_target_port *target, struct srp_rsp *rsp)
         struct srp_request *req;
         struct scsi_cmnd *scmnd;
         unsigned long flags;
-        s32 delta;
-
-        delta = (s32) be32_to_cpu(rsp->req_lim_delta);
-
-        spin_lock_irqsave(target->scsi_host->host_lock, flags);
-
-        target->req_lim += delta;
-
-        req = &target->req_ring[rsp->tag & ~SRP_TAG_TSK_MGMT];
 
         if (unlikely(rsp->tag & SRP_TAG_TSK_MGMT)) {
-                if (be32_to_cpu(rsp->resp_data_len) < 4)
-                        req->tsk_status = -1;
-                else
-                        req->tsk_status = rsp->data[3];
-                complete(&req->done);
+                spin_lock_irqsave(&target->lock, flags);
+                target->req_lim += be32_to_cpu(rsp->req_lim_delta);
+                spin_unlock_irqrestore(&target->lock, flags);
+
+                target->tsk_mgmt_status = -1;
+                if (be32_to_cpu(rsp->resp_data_len) >= 4)
+                        target->tsk_mgmt_status = rsp->data[3];
+                complete(&target->tsk_mgmt_done);
         } else {
+                req = &target->req_ring[rsp->tag];
                 scmnd = req->scmnd;
                 if (!scmnd)
                         shost_printk(KERN_ERR, target->scsi_host,
@@ -953,49 +948,42 @@ static void srp_process_rsp(struct srp_target_port *target, struct srp_rsp *rsp)
                 else if (rsp->flags & (SRP_RSP_FLAG_DIOVER | SRP_RSP_FLAG_DIUNDER))
                         scsi_set_resid(scmnd, be32_to_cpu(rsp->data_in_res_cnt));
 
-                if (!req->tsk_mgmt) {
-                        scmnd->host_scribble = (void *) -1L;
-                        scmnd->scsi_done(scmnd);
-
-                        srp_remove_req(target, req);
-                } else
-                        req->cmd_done = 1;
+                srp_remove_req(target, req, be32_to_cpu(rsp->req_lim_delta));
+                scmnd->host_scribble = NULL;
+                scmnd->scsi_done(scmnd);
         }
-
-        spin_unlock_irqrestore(target->scsi_host->host_lock, flags);
 }
 
 static int srp_response_common(struct srp_target_port *target, s32 req_delta,
                                void *rsp, int len)
 {
-        struct ib_device *dev;
+        struct ib_device *dev = target->srp_host->srp_dev->dev;
         unsigned long flags;
         struct srp_iu *iu;
-        int err = 1;
+        int err;
 
-        dev = target->srp_host->srp_dev->dev;
-
-        spin_lock_irqsave(target->scsi_host->host_lock, flags);
+        spin_lock_irqsave(&target->lock, flags);
         target->req_lim += req_delta;
-
         iu = __srp_get_tx_iu(target, SRP_IU_RSP);
+        spin_unlock_irqrestore(&target->lock, flags);
+
         if (!iu) {
                 shost_printk(KERN_ERR, target->scsi_host, PFX
                              "no IU available to send response\n");
-                goto out;
+                return 1;
         }
 
         ib_dma_sync_single_for_cpu(dev, iu->dma, len, DMA_TO_DEVICE);
         memcpy(iu->buf, rsp, len);
         ib_dma_sync_single_for_device(dev, iu->dma, len, DMA_TO_DEVICE);
 
-        err = __srp_post_send(target, iu, len);
-        if (err)
+        err = srp_post_send(target, iu, len);
+        if (err) {
                 shost_printk(KERN_ERR, target->scsi_host, PFX
                              "unable to post response: %d\n", err);
+                srp_put_tx_iu(target, iu, SRP_IU_RSP);
+        }
 
-out:
-        spin_unlock_irqrestore(target->scsi_host->host_lock, flags);
         return err;
 }
 
@@ -1032,14 +1020,11 @@ static void srp_process_aer_req(struct srp_target_port *target,
 
 static void srp_handle_recv(struct srp_target_port *target, struct ib_wc *wc)
 {
-        struct ib_device *dev;
-        struct srp_iu *iu;
+        struct ib_device *dev = target->srp_host->srp_dev->dev;
+        struct srp_iu *iu = (struct srp_iu *) wc->wr_id;
         int res;
         u8 opcode;
 
-        iu = target->rx_ring[wc->wr_id];
-
-        dev = target->srp_host->srp_dev->dev;
         ib_dma_sync_single_for_cpu(dev, iu->dma, target->max_ti_iu_len,
                                    DMA_FROM_DEVICE);
 
@@ -1080,7 +1065,7 @@ static void srp_handle_recv(struct srp_target_port *target, struct ib_wc *wc)
         ib_dma_sync_single_for_device(dev, iu->dma, target->max_ti_iu_len,
                                       DMA_FROM_DEVICE);
 
-        res = srp_post_recv(target);
+        res = srp_post_recv(target, iu);
         if (res != 0)
                 shost_printk(KERN_ERR, target->scsi_host,
                              PFX "Recv failed with error code %d\n", res);
@@ -1109,6 +1094,7 @@ static void srp_send_completion(struct ib_cq *cq, void *target_ptr)
 {
         struct srp_target_port *target = target_ptr;
         struct ib_wc wc;
+        struct srp_iu *iu;
 
         while (ib_poll_cq(cq, 1, &wc) > 0) {
                 if (wc.status) {
@@ -1119,18 +1105,19 @@ static void srp_send_completion(struct ib_cq *cq, void *target_ptr)
                         break;
                 }
 
-                ++target->tx_tail;
+                iu = (struct srp_iu *) wc.wr_id;
+                list_add(&iu->list, &target->free_tx);
         }
 }
 
-static int srp_queuecommand_lck(struct scsi_cmnd *scmnd,
-                            void (*done)(struct scsi_cmnd *))
+static int srp_queuecommand(struct Scsi_Host *shost, struct scsi_cmnd *scmnd)
 {
-        struct srp_target_port *target = host_to_target(scmnd->device->host);
+        struct srp_target_port *target = host_to_target(shost);
         struct srp_request *req;
         struct srp_iu *iu;
         struct srp_cmd *cmd;
         struct ib_device *dev;
+        unsigned long flags;
         int len;
 
         if (target->state == SRP_TARGET_CONNECTING)
@@ -1139,11 +1126,19 @@ static int srp_queuecommand_lck(struct scsi_cmnd *scmnd,
         if (target->state == SRP_TARGET_DEAD ||
             target->state == SRP_TARGET_REMOVED) {
                 scmnd->result = DID_BAD_TARGET << 16;
-                done(scmnd);
+                scmnd->scsi_done(scmnd);
                 return 0;
         }
 
+        spin_lock_irqsave(&target->lock, flags);
         iu = __srp_get_tx_iu(target, SRP_IU_CMD);
+        if (iu) {
+                req = list_first_entry(&target->free_reqs, struct srp_request,
+                                      list);
+                list_del(&req->list);
+        }
+        spin_unlock_irqrestore(&target->lock, flags);
+
         if (!iu)
                 goto err;
 
@@ -1151,11 +1146,8 @@ static int srp_queuecommand_lck(struct scsi_cmnd *scmnd,
         ib_dma_sync_single_for_cpu(dev, iu->dma, srp_max_iu_len,
                                    DMA_TO_DEVICE);
 
-        req = list_first_entry(&target->free_reqs, struct srp_request, list);
-
-        scmnd->scsi_done     = done;
         scmnd->result        = 0;
-        scmnd->host_scribble = (void *) (long) req->index;
+        scmnd->host_scribble = (void *) req;
 
         cmd = iu->buf;
         memset(cmd, 0, sizeof *cmd);
@@ -1167,37 +1159,38 @@ static int srp_queuecommand_lck(struct scsi_cmnd *scmnd,
 
         req->scmnd    = scmnd;
         req->cmd      = iu;
-        req->cmd_done = 0;
-        req->tsk_mgmt = NULL;
 
         len = srp_map_data(scmnd, target, req);
         if (len < 0) {
                 shost_printk(KERN_ERR, target->scsi_host,
                              PFX "Failed to map data\n");
-                goto err;
+                goto err_iu;
         }
 
         ib_dma_sync_single_for_device(dev, iu->dma, srp_max_iu_len,
                                       DMA_TO_DEVICE);
 
-        if (__srp_post_send(target, iu, len)) {
+        if (srp_post_send(target, iu, len)) {
                 shost_printk(KERN_ERR, target->scsi_host, PFX "Send failed\n");
                 goto err_unmap;
         }
 
-        list_move_tail(&req->list, &target->req_queue);
-
         return 0;
 
 err_unmap:
         srp_unmap_data(scmnd, target, req);
 
+err_iu:
+        srp_put_tx_iu(target, iu, SRP_IU_CMD);
+
+        spin_lock_irqsave(&target->lock, flags);
+        list_add(&req->list, &target->free_reqs);
+        spin_unlock_irqrestore(&target->lock, flags);
+
 err:
         return SCSI_MLQUEUE_HOST_BUSY;
 }
 
-static DEF_SCSI_QCMD(srp_queuecommand)
-
 static int srp_alloc_iu_bufs(struct srp_target_port *target)
 {
         int i;
@@ -1216,6 +1209,8 @@ static int srp_alloc_iu_bufs(struct srp_target_port *target)
                                                   GFP_KERNEL, DMA_TO_DEVICE);
                 if (!target->tx_ring[i])
                         goto err;
+
+                list_add(&target->tx_ring[i]->list, &target->free_tx);
         }
 
         return 0;
@@ -1377,7 +1372,8 @@ static int srp_cm_handler(struct ib_cm_id *cm_id, struct ib_cm_event *event)
                         break;
 
                 for (i = 0; i < SRP_RQ_SIZE; i++) {
-                        target->status = srp_post_recv(target);
+                        struct srp_iu *iu = target->rx_ring[i];
+                        target->status = srp_post_recv(target, iu);
                         if (target->status)
                                 break;
                 }
@@ -1442,25 +1438,24 @@ static int srp_cm_handler(struct ib_cm_id *cm_id, struct ib_cm_event *event)
 }
 
 static int srp_send_tsk_mgmt(struct srp_target_port *target,
-                             struct srp_request *req, u8 func)
+                             u64 req_tag, unsigned int lun, u8 func)
 {
         struct ib_device *dev = target->srp_host->srp_dev->dev;
         struct srp_iu *iu;
         struct srp_tsk_mgmt *tsk_mgmt;
 
-        spin_lock_irq(target->scsi_host->host_lock);
-
         if (target->state == SRP_TARGET_DEAD ||
-            target->state == SRP_TARGET_REMOVED) {
-                req->scmnd->result = DID_BAD_TARGET << 16;
-                goto out;
-        }
+            target->state == SRP_TARGET_REMOVED)
+                return -1;
 
-        init_completion(&req->done);
+        init_completion(&target->tsk_mgmt_done);
 
+        spin_lock_irq(&target->lock);
         iu = __srp_get_tx_iu(target, SRP_IU_TSK_MGMT);
+        spin_unlock_irq(&target->lock);
+
         if (!iu)
-                goto out;
+                return -1;
 
         ib_dma_sync_single_for_cpu(dev, iu->dma, sizeof *tsk_mgmt,
                                    DMA_TO_DEVICE);
@@ -1468,70 +1463,46 @@ static int srp_send_tsk_mgmt(struct srp_target_port *target,
         memset(tsk_mgmt, 0, sizeof *tsk_mgmt);
 
         tsk_mgmt->opcode        = SRP_TSK_MGMT;
-        tsk_mgmt->lun           = cpu_to_be64((u64) req->scmnd->device->lun << 48);
-        tsk_mgmt->tag           = req->index | SRP_TAG_TSK_MGMT;
+        tsk_mgmt->lun           = cpu_to_be64((u64) lun << 48);
+        tsk_mgmt->tag           = req_tag | SRP_TAG_TSK_MGMT;
         tsk_mgmt->tsk_mgmt_func = func;
-        tsk_mgmt->task_tag      = req->index;
+        tsk_mgmt->task_tag      = req_tag;
 
         ib_dma_sync_single_for_device(dev, iu->dma, sizeof *tsk_mgmt,
                                       DMA_TO_DEVICE);
-        if (__srp_post_send(target, iu, sizeof *tsk_mgmt))
-                goto out;
-
-        req->tsk_mgmt = iu;
-
-        spin_unlock_irq(target->scsi_host->host_lock);
-
-        if (!wait_for_completion_timeout(&req->done,
-                                         msecs_to_jiffies(SRP_ABORT_TIMEOUT_MS)))
+        if (srp_post_send(target, iu, sizeof *tsk_mgmt)) {
+                srp_put_tx_iu(target, iu, SRP_IU_TSK_MGMT);
                 return -1;
+        }
 
-        return 0;
-
-out:
-        spin_unlock_irq(target->scsi_host->host_lock);
-        return -1;
-}
-
-static int srp_find_req(struct srp_target_port *target,
-                        struct scsi_cmnd *scmnd,
-                        struct srp_request **req)
-{
-        if (scmnd->host_scribble == (void *) -1L)
+        if (!wait_for_completion_timeout(&target->tsk_mgmt_done,
+                                         msecs_to_jiffies(SRP_ABORT_TIMEOUT_MS)))
                 return -1;
 
-        *req = &target->req_ring[(long) scmnd->host_scribble];
-
         return 0;
 }
 
 static int srp_abort(struct scsi_cmnd *scmnd)
 {
         struct srp_target_port *target = host_to_target(scmnd->device->host);
-        struct srp_request *req;
+        struct srp_request *req = (struct srp_request *) scmnd->host_scribble;
         int ret = SUCCESS;
 
         shost_printk(KERN_ERR, target->scsi_host, "SRP abort called\n");
 
-        if (target->qp_in_error)
+        if (!req || target->qp_in_error)
                 return FAILED;
-        if (srp_find_req(target, scmnd, &req))
+        if (srp_send_tsk_mgmt(target, req->index, scmnd->device->lun,
+                              SRP_TSK_ABORT_TASK))
                 return FAILED;
-        if (srp_send_tsk_mgmt(target, req, SRP_TSK_ABORT_TASK))
-                return FAILED;
-
-        spin_lock_irq(target->scsi_host->host_lock);
 
-        if (req->cmd_done) {
-                srp_remove_req(target, req);
-                scmnd->scsi_done(scmnd);
-        } else if (!req->tsk_status) {
-                srp_remove_req(target, req);
-                scmnd->result = DID_ABORT << 16;
-        } else
-                ret = FAILED;
-
-        spin_unlock_irq(target->scsi_host->host_lock);
+        if (req->scmnd) {
+                if (!target->tsk_mgmt_status) {
+                        srp_remove_req(target, req, 0);
+                        scmnd->result = DID_ABORT << 16;
+                } else
+                        ret = FAILED;
+        }
 
         return ret;
 }
@@ -1539,26 +1510,23 @@ static int srp_abort(struct scsi_cmnd *scmnd)
 static int srp_reset_device(struct scsi_cmnd *scmnd)
 {
         struct srp_target_port *target = host_to_target(scmnd->device->host);
-        struct srp_request *req, *tmp;
+        int i;
 
         shost_printk(KERN_ERR, target->scsi_host, "SRP reset_device called\n");
 
         if (target->qp_in_error)
                 return FAILED;
-        if (srp_find_req(target, scmnd, &req))
+        if (srp_send_tsk_mgmt(target, SRP_TAG_NO_REQ, scmnd->device->lun,
+                              SRP_TSK_LUN_RESET))
                 return FAILED;
-        if (srp_send_tsk_mgmt(target, req, SRP_TSK_LUN_RESET))
+        if (target->tsk_mgmt_status)
                 return FAILED;
-        if (req->tsk_status)
-                return FAILED;
-
-        spin_lock_irq(target->scsi_host->host_lock);
 
-        list_for_each_entry_safe(req, tmp, &target->req_queue, list)
-                if (req->scmnd->device == scmnd->device)
+        for (i = 0; i < SRP_CMD_SQ_SIZE; ++i) {
+                struct srp_request *req = &target->req_ring[i];
+                if (req->scmnd && req->scmnd->device == scmnd->device)
                         srp_reset_req(target, req);
-
-        spin_unlock_irq(target->scsi_host->host_lock);
+        }
 
         return SUCCESS;
 }
@@ -1987,9 +1955,12 @@ static ssize_t srp_create_target(struct device *dev,
         target->io_class   = SRP_REV16A_IB_IO_CLASS;
         target->scsi_host  = target_host;
         target->srp_host   = host;
+        target->lkey       = host->srp_dev->mr->lkey;
+        target->rkey       = host->srp_dev->mr->rkey;
 
+        spin_lock_init(&target->lock);
+        INIT_LIST_HEAD(&target->free_tx);
         INIT_LIST_HEAD(&target->free_reqs);
-        INIT_LIST_HEAD(&target->req_queue);
         for (i = 0; i < SRP_CMD_SQ_SIZE; ++i) {
                 target->req_ring[i].index = i;
                 list_add_tail(&target->req_ring[i].list, &target->free_reqs);
@@ -2217,9 +2188,9 @@ static void srp_remove_one(struct ib_device *device)
                  */
                 spin_lock(&host->target_lock);
                 list_for_each_entry(target, &host->target_list, list) {
-                        spin_lock_irq(target->scsi_host->host_lock);
+                        spin_lock_irq(&target->lock);
                         target->state = SRP_TARGET_REMOVED;
-                        spin_unlock_irq(target->scsi_host->host_lock);
+                        spin_unlock_irq(&target->lock);
                 }
                 spin_unlock(&host->target_lock);
 
@@ -2258,8 +2229,7 @@ static int __init srp_init_module(void)
 {
         int ret;
 
-        BUILD_BUG_ON_NOT_POWER_OF_2(SRP_SQ_SIZE);
-        BUILD_BUG_ON_NOT_POWER_OF_2(SRP_RQ_SIZE);
+        BUILD_BUG_ON(FIELD_SIZEOF(struct ib_wc, wr_id) < sizeof(void *));
 
         if (srp_sg_tablesize > 255) {
                 printk(KERN_WARNING PFX "Clamping srp_sg_tablesize to 255\n");
diff --git a/drivers/infiniband/ulp/srp/ib_srp.h b/drivers/infiniband/ulp/srp/ib_srp.h
index ed0dce9e479f..9dc6fc3fd894 100644
--- a/drivers/infiniband/ulp/srp/ib_srp.h
+++ b/drivers/infiniband/ulp/srp/ib_srp.h
@@ -59,16 +59,15 @@ enum {
 
         SRP_RQ_SHIFT            = 6,
         SRP_RQ_SIZE             = 1 << SRP_RQ_SHIFT,
-        SRP_RQ_MASK             = SRP_RQ_SIZE - 1,
 
         SRP_SQ_SIZE             = SRP_RQ_SIZE,
-        SRP_SQ_MASK             = SRP_SQ_SIZE - 1,
         SRP_RSP_SQ_SIZE         = 1,
         SRP_REQ_SQ_SIZE         = SRP_SQ_SIZE - SRP_RSP_SQ_SIZE,
         SRP_TSK_MGMT_SQ_SIZE    = 1,
         SRP_CMD_SQ_SIZE         = SRP_REQ_SQ_SIZE - SRP_TSK_MGMT_SQ_SIZE,
 
-        SRP_TAG_TSK_MGMT        = 1 << (SRP_RQ_SHIFT + 1),
+        SRP_TAG_NO_REQ          = ~0U,
+        SRP_TAG_TSK_MGMT        = 1U << 31,
 
         SRP_FMR_SIZE            = 256,
         SRP_FMR_POOL_SIZE       = 1024,
@@ -113,15 +112,29 @@ struct srp_request {
         struct list_head        list;
         struct scsi_cmnd       *scmnd;
         struct srp_iu          *cmd;
-        struct srp_iu          *tsk_mgmt;
         struct ib_pool_fmr     *fmr;
-        struct completion       done;
         short                   index;
-        u8                      cmd_done;
-        u8                      tsk_status;
 };
 
 struct srp_target_port {
+        /* These are RW in the hot path, and commonly used together */
+        struct list_head        free_tx;
+        struct list_head        free_reqs;
+        spinlock_t              lock;
+        s32                     req_lim;
+
+        /* These are read-only in the hot path */
+        struct ib_cq           *send_cq ____cacheline_aligned_in_smp;
+        struct ib_cq           *recv_cq;
+        struct ib_qp           *qp;
+        u32                     lkey;
+        u32                     rkey;
+        enum srp_target_state   state;
+
+        /* Everything above this point is used in the hot path of
+         * command processing. Try to keep them packed into cachelines.
+         */
+
         __be64                  id_ext;
         __be64                  ioc_guid;
         __be64                  service_id;
@@ -138,24 +151,13 @@ struct srp_target_port {
         int                     path_query_id;
 
         struct ib_cm_id        *cm_id;
-        struct ib_cq           *recv_cq;
-        struct ib_cq           *send_cq;
-        struct ib_qp           *qp;
 
         int                     max_ti_iu_len;
-        s32                     req_lim;
 
         int                     zero_req_lim;
 
-        unsigned                rx_head;
-        struct srp_iu          *rx_ring[SRP_RQ_SIZE];
-
-        unsigned                tx_head;
-        unsigned                tx_tail;
         struct srp_iu          *tx_ring[SRP_SQ_SIZE];
-
-        struct list_head        free_reqs;
-        struct list_head        req_queue;
+        struct srp_iu          *rx_ring[SRP_RQ_SIZE];
         struct srp_request      req_ring[SRP_CMD_SQ_SIZE];
 
         struct work_struct      work;
@@ -163,16 +165,18 @@ struct srp_target_port {
         struct list_head        list;
         struct completion       done;
         int                     status;
-        enum srp_target_state   state;
         int                     qp_in_error;
+
+        struct completion       tsk_mgmt_done;
+        u8                      tsk_mgmt_status;
 };
 
 struct srp_iu {
+        struct list_head        list;
         u64                     dma;
         void                   *buf;
         size_t                  size;
         enum dma_data_direction direction;
-        enum srp_iu_type        type;
 };
 
 #endif /* IB_SRP_H */
diff --git a/drivers/macintosh/macio_asic.c b/drivers/macintosh/macio_asic.c
index b6e7ddc09d76..4daf9e5a7736 100644
--- a/drivers/macintosh/macio_asic.c
+++ b/drivers/macintosh/macio_asic.c
@@ -387,11 +387,10 @@ static struct macio_dev * macio_add_one_device(struct macio_chip *chip,
         /* Set the DMA ops to the ones from the PCI device, this could be
          * fishy if we didn't know that on PowerMac it's always direct ops
          * or iommu ops that will work fine
+         *
+         * To get all the fields, copy all archdata
          */
-        dev->ofdev.dev.archdata.dma_ops =
-                chip->lbus.pdev->dev.archdata.dma_ops;
-        dev->ofdev.dev.archdata.dma_data =
-                chip->lbus.pdev->dev.archdata.dma_data;
+        dev->ofdev.dev.archdata = chip->lbus.pdev->dev.archdata;
 #endif /* CONFIG_PCI */
 
 #ifdef DEBUG
diff --git a/drivers/macintosh/therm_pm72.c b/drivers/macintosh/therm_pm72.c
index 44549272333c..2e041fd0a00c 100644
--- a/drivers/macintosh/therm_pm72.c
+++ b/drivers/macintosh/therm_pm72.c
@@ -2213,6 +2213,9 @@ static void fcu_lookup_fans(struct device_node *fcu_node)
 static int fcu_of_probe(struct platform_device* dev, const struct of_device_id *match)
 {
         state = state_detached;
+        of_dev = dev;
+
+        dev_info(&dev->dev, "PowerMac G5 Thermal control driver %s\n", VERSION);
 
         /* Lookup the fans in the device tree */
         fcu_lookup_fans(dev->dev.of_node);
@@ -2235,6 +2238,7 @@ static const struct of_device_id fcu_match[] =
         },
         {},
 };
+MODULE_DEVICE_TABLE(of, fcu_match);
 
 static struct of_platform_driver fcu_of_platform_driver = 
 {
@@ -2252,8 +2256,6 @@ static struct of_platform_driver fcu_of_platform_driver =
  */
 static int __init therm_pm72_init(void)
 {
-        struct device_node *np;
-
         rackmac = of_machine_is_compatible("RackMac3,1");
 
         if (!of_machine_is_compatible("PowerMac7,2") &&
@@ -2261,34 +2263,12 @@ static int __init therm_pm72_init(void)
             !rackmac)
                 return -ENODEV;
 
-        printk(KERN_INFO "PowerMac G5 Thermal control driver %s\n", VERSION);
-
-        np = of_find_node_by_type(NULL, "fcu");
-        if (np == NULL) {
-                /* Some machines have strangely broken device-tree */
-                np = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/fan@15e");
-                if (np == NULL) {
-                            printk(KERN_ERR "Can't find FCU in device-tree !\n");
-                            return -ENODEV;
-                }
-        }
-        of_dev = of_platform_device_create(np, "temperature", NULL);
-        if (of_dev == NULL) {
-                printk(KERN_ERR "Can't register FCU platform device !\n");
-                return -ENODEV;
-        }
-
-        of_register_platform_driver(&fcu_of_platform_driver);
-        
-        return 0;
+        return of_register_platform_driver(&fcu_of_platform_driver);
 }
 
 static void __exit therm_pm72_exit(void)
 {
         of_unregister_platform_driver(&fcu_of_platform_driver);
-
-        if (of_dev)
-                of_device_unregister(of_dev);
 }
 
 module_init(therm_pm72_init);
diff --git a/drivers/mfd/sh_mobile_sdhi.c b/drivers/mfd/sh_mobile_sdhi.c
index f1714f93af9d..0a7df44a93c0 100644
--- a/drivers/mfd/sh_mobile_sdhi.c
+++ b/drivers/mfd/sh_mobile_sdhi.c
@@ -131,11 +131,17 @@ static int __devinit sh_mobile_sdhi_probe(struct platform_device *pdev)
          */
         mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
 
+        /*
+         * All SDHI blocks support SDIO IRQ signalling.
+         */
+        mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
+
         if (p && p->dma_slave_tx >= 0 && p->dma_slave_rx >= 0) {
                 priv->param_tx.slave_id = p->dma_slave_tx;
                 priv->param_rx.slave_id = p->dma_slave_rx;
                 priv->dma_priv.chan_priv_tx = &priv->param_tx;
                 priv->dma_priv.chan_priv_rx = &priv->param_rx;
+                priv->dma_priv.alignment_shift = 1; /* 2-byte alignment */
                 mmc_data->dma = &priv->dma_priv;
         }
 
diff --git a/drivers/mmc/card/Kconfig b/drivers/mmc/card/Kconfig
index 57e4416b9ef0..2a876c4099cd 100644
--- a/drivers/mmc/card/Kconfig
+++ b/drivers/mmc/card/Kconfig
@@ -16,6 +16,7 @@ config MMC_BLOCK
 
 config MMC_BLOCK_MINORS
         int "Number of minors per block device"
+        depends on MMC_BLOCK
         range 4 256
         default 8
         help
diff --git a/drivers/mmc/core/Kconfig b/drivers/mmc/core/Kconfig
index bb22ffd76ef8..ef103871517f 100644
--- a/drivers/mmc/core/Kconfig
+++ b/drivers/mmc/core/Kconfig
@@ -16,3 +16,14 @@ config MMC_UNSAFE_RESUME
 
           This option sets a default which can be overridden by the
           module parameter "removable=0" or "removable=1".
+
+config MMC_CLKGATE
+        bool "MMC host clock gating (EXPERIMENTAL)"
+        depends on EXPERIMENTAL
+        help
+          This will attempt to aggressively gate the clock to the MMC card.
+          This is done to save power due to gating off the logic and bus
+          noise when the MMC card is not in use. Your host driver has to
+          support handling this in order for it to be of any use.
+
+          If unsure, say N.
diff --git a/drivers/mmc/core/bus.c b/drivers/mmc/core/bus.c
index af8dc6a2a317..63667a8f140c 100644
--- a/drivers/mmc/core/bus.c
+++ b/drivers/mmc/core/bus.c
@@ -303,14 +303,14 @@ int mmc_add_card(struct mmc_card *card)
                         type, card->rca);
         }
 
-        ret = device_add(&card->dev);
-        if (ret)
-                return ret;
-
 #ifdef CONFIG_DEBUG_FS
         mmc_add_card_debugfs(card);
 #endif
 
+        ret = device_add(&card->dev);
+        if (ret)
+                return ret;
+
         mmc_card_set_present(card);
 
         return 0;
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index a3a780faf85a..6625c057be05 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -22,6 +22,7 @@
 #include <linux/scatterlist.h>
 #include <linux/log2.h>
 #include <linux/regulator/consumer.h>
+#include <linux/pm_runtime.h>
 
 #include <linux/mmc/card.h>
 #include <linux/mmc/host.h>
@@ -130,6 +131,8 @@ void mmc_request_done(struct mmc_host *host, struct mmc_request *mrq)
 
                 if (mrq->done)
                         mrq->done(mrq);
+
+                mmc_host_clk_gate(host);
         }
 }
 
@@ -190,6 +193,7 @@ mmc_start_request(struct mmc_host *host, struct mmc_request *mrq)
                         mrq->stop->mrq = mrq;
                 }
         }
+        mmc_host_clk_ungate(host);
         host->ops->request(host, mrq);
 }
 
@@ -295,8 +299,9 @@ void mmc_set_data_timeout(struct mmc_data *data, const struct mmc_card *card)
                 unsigned int timeout_us, limit_us;
 
                 timeout_us = data->timeout_ns / 1000;
-                timeout_us += data->timeout_clks * 1000 /
-                        (card->host->ios.clock / 1000);
+                if (mmc_host_clk_rate(card->host))
+                        timeout_us += data->timeout_clks * 1000 /
+                                (mmc_host_clk_rate(card->host) / 1000);
 
                 if (data->flags & MMC_DATA_WRITE)
                         /*
@@ -614,6 +619,8 @@ static inline void mmc_set_ios(struct mmc_host *host)
                  ios->power_mode, ios->chip_select, ios->vdd,
                  ios->bus_width, ios->timing);
 
+        if (ios->clock > 0)
+                mmc_set_ungated(host);
         host->ops->set_ios(host, ios);
 }
 
@@ -641,6 +648,61 @@ void mmc_set_clock(struct mmc_host *host, unsigned int hz)
         mmc_set_ios(host);
 }
 
+#ifdef CONFIG_MMC_CLKGATE
+/*
+ * This gates the clock by setting it to 0 Hz.
+ */
+void mmc_gate_clock(struct mmc_host *host)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&host->clk_lock, flags);
+        host->clk_old = host->ios.clock;
+        host->ios.clock = 0;
+        host->clk_gated = true;
+        spin_unlock_irqrestore(&host->clk_lock, flags);
+        mmc_set_ios(host);
+}
+
+/*
+ * This restores the clock from gating by using the cached
+ * clock value.
+ */
+void mmc_ungate_clock(struct mmc_host *host)
+{
+        /*
+         * We should previously have gated the clock, so the clock shall
+         * be 0 here! The clock may however be 0 during initialization,
+         * when some request operations are performed before setting
+         * the frequency. When ungate is requested in that situation
+         * we just ignore the call.
+         */
+        if (host->clk_old) {
+                BUG_ON(host->ios.clock);
+                /* This call will also set host->clk_gated to false */
+                mmc_set_clock(host, host->clk_old);
+        }
+}
+
+void mmc_set_ungated(struct mmc_host *host)
+{
+        unsigned long flags;
+
+        /*
+         * We've been given a new frequency while the clock is gated,
+         * so make sure we regard this as ungating it.
+         */
+        spin_lock_irqsave(&host->clk_lock, flags);
+        host->clk_gated = false;
+        spin_unlock_irqrestore(&host->clk_lock, flags);
+}
+
+#else
+void mmc_set_ungated(struct mmc_host *host)
+{
+}
+#endif
+
 /*
  * Change the bus mode (open drain/push-pull) of a host.
  */
@@ -1424,35 +1486,57 @@ int mmc_set_blocklen(struct mmc_card *card, unsigned int blocklen)
 }
 EXPORT_SYMBOL(mmc_set_blocklen);
 
+static int mmc_rescan_try_freq(struct mmc_host *host, unsigned freq)
+{
+        host->f_init = freq;
+
+#ifdef CONFIG_MMC_DEBUG
+        pr_info("%s: %s: trying to init card at %u Hz\n",
+                mmc_hostname(host), __func__, host->f_init);
+#endif
+        mmc_power_up(host);
+        sdio_reset(host);
+        mmc_go_idle(host);
+
+        mmc_send_if_cond(host, host->ocr_avail);
+
+        /* Order's important: probe SDIO, then SD, then MMC */
+        if (!mmc_attach_sdio(host))
+                return 0;
+        if (!mmc_attach_sd(host))
+                return 0;
+        if (!mmc_attach_mmc(host))
+                return 0;
+
+        mmc_power_off(host);
+        return -EIO;
+}
+
 void mmc_rescan(struct work_struct *work)
 {
+        static const unsigned freqs[] = { 400000, 300000, 200000, 100000 };
         struct mmc_host *host =
                 container_of(work, struct mmc_host, detect.work);
-        u32 ocr;
-        int err;
-        unsigned long flags;
         int i;
-        const unsigned freqs[] = { 400000, 300000, 200000, 100000 };
-
-        spin_lock_irqsave(&host->lock, flags);
 
-        if (host->rescan_disable) {
-                spin_unlock_irqrestore(&host->lock, flags);
+        if (host->rescan_disable)
                 return;
-        }
-
-        spin_unlock_irqrestore(&host->lock, flags);
-
 
         mmc_bus_get(host);
 
-        /* if there is a card registered, check whether it is still present */
-        if ((host->bus_ops != NULL) && host->bus_ops->detect && !host->bus_dead)
+        /*
+         * if there is a _removable_ card registered, check whether it is
+         * still present
+         */
+        if (host->bus_ops && host->bus_ops->detect && !host->bus_dead
+            && mmc_card_is_removable(host))
                 host->bus_ops->detect(host);
 
+        /*
+         * Let mmc_bus_put() free the bus/bus_ops if we've found that
+         * the card is no longer present.
+         */
         mmc_bus_put(host);
-
-
         mmc_bus_get(host);
 
         /* if there still is a card present, stop here */
@@ -1461,8 +1545,6 @@ void mmc_rescan(struct work_struct *work)
                 goto out;
         }
 
-        /* detect a newly inserted card */
-
         /*
          * Only we can add a new handler, so it's safe to
          * release the lock here.
@@ -1472,72 +1554,16 @@ void mmc_rescan(struct work_struct *work)
         if (host->ops->get_cd && host->ops->get_cd(host) == 0)
                 goto out;
 
+        mmc_claim_host(host);
         for (i = 0; i < ARRAY_SIZE(freqs); i++) {
-                mmc_claim_host(host);
-
-                if (freqs[i] >= host->f_min)
-                        host->f_init = freqs[i];
-                else if (!i || freqs[i-1] > host->f_min)
-                        host->f_init = host->f_min;
-                else {
-                        mmc_release_host(host);
-                        goto out;
-                }
-#ifdef CONFIG_MMC_DEBUG
-                pr_info("%s: %s: trying to init card at %u Hz\n",
-                        mmc_hostname(host), __func__, host->f_init);
-#endif
-                mmc_power_up(host);
-                sdio_reset(host);
-                mmc_go_idle(host);
-
-                mmc_send_if_cond(host, host->ocr_avail);
-
-                /*
-                 * First we search for SDIO...
-                 */
-                err = mmc_send_io_op_cond(host, 0, &ocr);
-                if (!err) {
-                        if (mmc_attach_sdio(host, ocr)) {
-                                mmc_claim_host(host);
-                                /*
-                                 * Try SDMEM (but not MMC) even if SDIO
-                                 * is broken.
-                                 */
-                                if (mmc_send_app_op_cond(host, 0, &ocr))
-                                        goto out_fail;
-
-                                if (mmc_attach_sd(host, ocr))
-                                        mmc_power_off(host);
-                        }
-                        goto out;
-                }
-
-                /*
-                 * ...then normal SD...
-                 */
-                err = mmc_send_app_op_cond(host, 0, &ocr);
-                if (!err) {
-                        if (mmc_attach_sd(host, ocr))
-                                mmc_power_off(host);
-                        goto out;
-                }
-
-                /*
-                 * ...and finally MMC.
-                 */
-                err = mmc_send_op_cond(host, 0, &ocr);
-                if (!err) {
-                        if (mmc_attach_mmc(host, ocr))
-                                mmc_power_off(host);
-                        goto out;
-                }
-
-out_fail:
-                mmc_release_host(host);
-                mmc_power_off(host);
+                if (!mmc_rescan_try_freq(host, max(freqs[i], host->f_min)))
+                        break;
+                if (freqs[i] < host->f_min)
+                        break;
         }
-out:
+        mmc_release_host(host);
+
+ out:
         if (host->caps & MMC_CAP_NEEDS_POLL)
                 mmc_schedule_delayed_work(&host->detect, HZ);
 }
@@ -1721,6 +1747,18 @@ int mmc_resume_host(struct mmc_host *host)
                 if (!(host->pm_flags & MMC_PM_KEEP_POWER)) {
                         mmc_power_up(host);
                         mmc_select_voltage(host, host->ocr);
+                        /*
+                         * Tell runtime PM core we just powered up the card,
+                         * since it still believes the card is powered off.
+                         * Note that currently runtime PM is only enabled
+                         * for SDIO cards that are MMC_CAP_POWER_OFF_CARD
+                         */
+                        if (mmc_card_sdio(host->card) &&
+                            (host->caps & MMC_CAP_POWER_OFF_CARD)) {
+                                pm_runtime_disable(&host->card->dev);
+                                pm_runtime_set_active(&host->card->dev);
+                                pm_runtime_enable(&host->card->dev);
+                        }
                 }
                 BUG_ON(!host->bus_ops->resume);
                 err = host->bus_ops->resume(host);
diff --git a/drivers/mmc/core/core.h b/drivers/mmc/core/core.h
index 77240cd11bcf..ca1fdde29df6 100644
--- a/drivers/mmc/core/core.h
+++ b/drivers/mmc/core/core.h
@@ -33,6 +33,9 @@ void mmc_init_erase(struct mmc_card *card);
 
 void mmc_set_chip_select(struct mmc_host *host, int mode);
 void mmc_set_clock(struct mmc_host *host, unsigned int hz);
+void mmc_gate_clock(struct mmc_host *host);
+void mmc_ungate_clock(struct mmc_host *host);
+void mmc_set_ungated(struct mmc_host *host);
 void mmc_set_bus_mode(struct mmc_host *host, unsigned int mode);
 void mmc_set_bus_width(struct mmc_host *host, unsigned int width);
 void mmc_set_bus_width_ddr(struct mmc_host *host, unsigned int width,
@@ -54,9 +57,9 @@ void mmc_rescan(struct work_struct *work);
 void mmc_start_host(struct mmc_host *host);
 void mmc_stop_host(struct mmc_host *host);
 
-int mmc_attach_mmc(struct mmc_host *host, u32 ocr);
-int mmc_attach_sd(struct mmc_host *host, u32 ocr);
-int mmc_attach_sdio(struct mmc_host *host, u32 ocr);
+int mmc_attach_mmc(struct mmc_host *host);
+int mmc_attach_sd(struct mmc_host *host);
+int mmc_attach_sdio(struct mmc_host *host);
 
 /* Module parameters */
 extern int use_spi_crc;
diff --git a/drivers/mmc/core/debugfs.c b/drivers/mmc/core/debugfs.c
index eed1405fd742..998797ed67a6 100644
--- a/drivers/mmc/core/debugfs.c
+++ b/drivers/mmc/core/debugfs.c
@@ -183,6 +183,11 @@ void mmc_add_host_debugfs(struct mmc_host *host)
                         &mmc_clock_fops))
                 goto err_node;
 
+#ifdef CONFIG_MMC_CLKGATE
+        if (!debugfs_create_u32("clk_delay", (S_IRUSR | S_IWUSR),
+                                root, &host->clk_delay))
+                goto err_node;
+#endif
         return;
 
 err_node:
diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index 10b8af27e03a..b3ac6c5bc5c6 100644
--- a/drivers/mmc/core/host.c
+++ b/drivers/mmc/core/host.c
@@ -3,6 +3,7 @@
  *
  *  Copyright (C) 2003 Russell King, All Rights Reserved.
  *  Copyright (C) 2007-2008 Pierre Ossman
+ *  Copyright (C) 2010 Linus Walleij
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -20,6 +21,7 @@
 #include <linux/suspend.h>
 
 #include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
 
 #include "core.h"
 #include "host.h"
@@ -50,6 +52,205 @@ void mmc_unregister_host_class(void)
 static DEFINE_IDR(mmc_host_idr);
 static DEFINE_SPINLOCK(mmc_host_lock);
 
+#ifdef CONFIG_MMC_CLKGATE
+
+/*
+ * Enabling clock gating will make the core call out to the host
+ * once up and once down when it performs a request or card operation
+ * intermingled in any fashion. The driver will see this through
+ * set_ios() operations with ios.clock field set to 0 to gate (disable)
+ * the block clock, and to the old frequency to enable it again.
+ */
+static void mmc_host_clk_gate_delayed(struct mmc_host *host)
+{
+        unsigned long tick_ns;
+        unsigned long freq = host->ios.clock;
+        unsigned long flags;
+
+        if (!freq) {
+                pr_debug("%s: frequency set to 0 in disable function, "
+                         "this means the clock is already disabled.\n",
+                         mmc_hostname(host));
+                return;
+        }
+        /*
+         * New requests may have appeared while we were scheduling,
+         * then there is no reason to delay the check before
+         * clk_disable().
+         */
+        spin_lock_irqsave(&host->clk_lock, flags);
+
+        /*
+         * Delay n bus cycles (at least 8 from MMC spec) before attempting
+         * to disable the MCI block clock. The reference count may have
+         * gone up again after this delay due to rescheduling!
+         */
+        if (!host->clk_requests) {
+                spin_unlock_irqrestore(&host->clk_lock, flags);
+                tick_ns = DIV_ROUND_UP(1000000000, freq);
+                ndelay(host->clk_delay * tick_ns);
+        } else {
+                /* New users appeared while waiting for this work */
+                spin_unlock_irqrestore(&host->clk_lock, flags);
+                return;
+        }
+        mutex_lock(&host->clk_gate_mutex);
+        spin_lock_irqsave(&host->clk_lock, flags);
+        if (!host->clk_requests) {
+                spin_unlock_irqrestore(&host->clk_lock, flags);
+                /* This will set host->ios.clock to 0 */
+                mmc_gate_clock(host);
+                spin_lock_irqsave(&host->clk_lock, flags);
+                pr_debug("%s: gated MCI clock\n", mmc_hostname(host));
+        }
+        spin_unlock_irqrestore(&host->clk_lock, flags);
+        mutex_unlock(&host->clk_gate_mutex);
+}
+
+/*
+ * Internal work. Work to disable the clock at some later point.
+ */
+static void mmc_host_clk_gate_work(struct work_struct *work)
+{
+        struct mmc_host *host = container_of(work, struct mmc_host,
+                                              clk_gate_work);
+
+        mmc_host_clk_gate_delayed(host);
+}
+
+/**
+ *      mmc_host_clk_ungate - ungate hardware MCI clocks
+ *      @host: host to ungate.
+ *
+ *      Makes sure the host ios.clock is restored to a non-zero value
+ *      past this call. Increase clock reference count and ungate clock
+ *      if we're the first user.
+ */
+void mmc_host_clk_ungate(struct mmc_host *host)
+{
+        unsigned long flags;
+
+        mutex_lock(&host->clk_gate_mutex);
+        spin_lock_irqsave(&host->clk_lock, flags);
+        if (host->clk_gated) {
+                spin_unlock_irqrestore(&host->clk_lock, flags);
+                mmc_ungate_clock(host);
+                spin_lock_irqsave(&host->clk_lock, flags);
+                pr_debug("%s: ungated MCI clock\n", mmc_hostname(host));
+        }
+        host->clk_requests++;
+        spin_unlock_irqrestore(&host->clk_lock, flags);
+        mutex_unlock(&host->clk_gate_mutex);
+}
+
+/**
+ *      mmc_host_may_gate_card - check if this card may be gated
+ *      @card: card to check.
+ */
+static bool mmc_host_may_gate_card(struct mmc_card *card)
+{
+        /* If there is no card we may gate it */
+        if (!card)
+                return true;
+        /*
+         * Don't gate SDIO cards! These need to be clocked at all times
+         * since they may be independent systems generating interrupts
+         * and other events. The clock requests counter from the core will
+         * go down to zero since the core does not need it, but we will not
+         * gate the clock, because there is somebody out there that may still
+         * be using it.
+         */
+        if (mmc_card_sdio(card))
+                return false;
+
+        return true;
+}
+
+/**
+ *      mmc_host_clk_gate - gate off hardware MCI clocks
+ *      @host: host to gate.
+ *
+ *      Calls the host driver with ios.clock set to zero as often as possible
+ *      in order to gate off hardware MCI clocks. Decrease clock reference
+ *      count and schedule disabling of clock.
+ */
+void mmc_host_clk_gate(struct mmc_host *host)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&host->clk_lock, flags);
+        host->clk_requests--;
+        if (mmc_host_may_gate_card(host->card) &&
+            !host->clk_requests)
+                schedule_work(&host->clk_gate_work);
+        spin_unlock_irqrestore(&host->clk_lock, flags);
+}
+
+/**
+ *      mmc_host_clk_rate - get current clock frequency setting
+ *      @host: host to get the clock frequency for.
+ *
+ *      Returns current clock frequency regardless of gating.
+ */
+unsigned int mmc_host_clk_rate(struct mmc_host *host)
+{
+        unsigned long freq;
+        unsigned long flags;
+
+        spin_lock_irqsave(&host->clk_lock, flags);
+        if (host->clk_gated)
+                freq = host->clk_old;
+        else
+                freq = host->ios.clock;
+        spin_unlock_irqrestore(&host->clk_lock, flags);
+        return freq;
+}
+
+/**
+ *      mmc_host_clk_init - set up clock gating code
+ *      @host: host with potential clock to control
+ */
+static inline void mmc_host_clk_init(struct mmc_host *host)
+{
+        host->clk_requests = 0;
+        /* Hold MCI clock for 8 cycles by default */
+        host->clk_delay = 8;
+        host->clk_gated = false;
+        INIT_WORK(&host->clk_gate_work, mmc_host_clk_gate_work);
+        spin_lock_init(&host->clk_lock);
+        mutex_init(&host->clk_gate_mutex);
+}
+
+/**
+ *      mmc_host_clk_exit - shut down clock gating code
+ *      @host: host with potential clock to control
+ */
+static inline void mmc_host_clk_exit(struct mmc_host *host)
+{
+        /*
+         * Wait for any outstanding gate and then make sure we're
+         * ungated before exiting.
+         */
+        if (cancel_work_sync(&host->clk_gate_work))
+                mmc_host_clk_gate_delayed(host);
+        if (host->clk_gated)
+                mmc_host_clk_ungate(host);
+        /* There should be only one user now */
+        WARN_ON(host->clk_requests > 1);
+}
+
+#else
+
+static inline void mmc_host_clk_init(struct mmc_host *host)
+{
+}
+
+static inline void mmc_host_clk_exit(struct mmc_host *host)
+{
+}
+
+#endif
+
 /**
  *      mmc_alloc_host - initialise the per-host structure.
  *      @extra: sizeof private data structure
@@ -82,6 +283,8 @@ struct mmc_host *mmc_alloc_host(int extra, struct device *dev)
         host->class_dev.class = &mmc_host_class;
         device_initialize(&host->class_dev);
 
+        mmc_host_clk_init(host);
+
         spin_lock_init(&host->lock);
         init_waitqueue_head(&host->wq);
         INIT_DELAYED_WORK(&host->detect, mmc_rescan);
@@ -163,6 +366,8 @@ void mmc_remove_host(struct mmc_host *host)
         device_del(&host->class_dev);
 
         led_trigger_unregister_simple(host->led);
+
+        mmc_host_clk_exit(host);
 }
 
 EXPORT_SYMBOL(mmc_remove_host);
@@ -183,4 +388,3 @@ void mmc_free_host(struct mmc_host *host)
 }
 
 EXPORT_SYMBOL(mmc_free_host);
-
diff --git a/drivers/mmc/core/host.h b/drivers/mmc/core/host.h
index 8c87e1109a34..de199f911928 100644
--- a/drivers/mmc/core/host.h
+++ b/drivers/mmc/core/host.h
@@ -10,10 +10,31 @@
  */
 #ifndef _MMC_CORE_HOST_H
 #define _MMC_CORE_HOST_H
+#include <linux/mmc/host.h>
 
 int mmc_register_host_class(void);
 void mmc_unregister_host_class(void);
 
+#ifdef CONFIG_MMC_CLKGATE
+void mmc_host_clk_ungate(struct mmc_host *host);
+void mmc_host_clk_gate(struct mmc_host *host);
+unsigned int mmc_host_clk_rate(struct mmc_host *host);
+
+#else
+static inline void mmc_host_clk_ungate(struct mmc_host *host)
+{
+}
+
+static inline void mmc_host_clk_gate(struct mmc_host *host)
+{
+}
+
+static inline unsigned int mmc_host_clk_rate(struct mmc_host *host)
+{
+        return host->ios.clock;
+}
+#endif
+
 void mmc_host_deeper_disable(struct work_struct *work);
 
 #endif
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 77f93c3b8808..16006ef153fe 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -534,39 +534,57 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
          */
         if ((card->csd.mmca_vsn >= CSD_SPEC_VER_4) &&
             (host->caps & (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA))) {
-                unsigned ext_csd_bit, bus_width;
-
-                if (host->caps & MMC_CAP_8_BIT_DATA) {
-                        if (ddr)
-                                ext_csd_bit = EXT_CSD_DDR_BUS_WIDTH_8;
-                        else
-                                ext_csd_bit = EXT_CSD_BUS_WIDTH_8;
-                        bus_width = MMC_BUS_WIDTH_8;
-                } else {
-                        if (ddr)
-                                ext_csd_bit = EXT_CSD_DDR_BUS_WIDTH_4;
-                        else
-                                ext_csd_bit = EXT_CSD_BUS_WIDTH_4;
-                        bus_width = MMC_BUS_WIDTH_4;
+                static unsigned ext_csd_bits[][2] = {
+                        { EXT_CSD_BUS_WIDTH_8, EXT_CSD_DDR_BUS_WIDTH_8 },
+                        { EXT_CSD_BUS_WIDTH_4, EXT_CSD_DDR_BUS_WIDTH_4 },
+                        { EXT_CSD_BUS_WIDTH_1, EXT_CSD_BUS_WIDTH_1 },
+                };
+                static unsigned bus_widths[] = {
+                        MMC_BUS_WIDTH_8,
+                        MMC_BUS_WIDTH_4,
+                        MMC_BUS_WIDTH_1
+                };
+                unsigned idx, bus_width = 0;
+
+                if (host->caps & MMC_CAP_8_BIT_DATA)
+                        idx = 0;
+                else
+                        idx = 1;
+                for (; idx < ARRAY_SIZE(bus_widths); idx++) {
+                        bus_width = bus_widths[idx];
+                        if (bus_width == MMC_BUS_WIDTH_1)
+                                ddr = 0; /* no DDR for 1-bit width */
+                        err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
+                                         EXT_CSD_BUS_WIDTH,
+                                         ext_csd_bits[idx][0]);
+                        if (!err) {
+                                mmc_set_bus_width_ddr(card->host,
+                                                      bus_width, MMC_SDR_MODE);
+                                /*
+                                 * If controller can't handle bus width test,
+                                 * use the highest bus width to maintain
+                                 * compatibility with previous MMC behavior.
+                                 */
+                                if (!(host->caps & MMC_CAP_BUS_WIDTH_TEST))
+                                        break;
+                                err = mmc_bus_test(card, bus_width);
+                                if (!err)
+                                        break;
+                        }
                 }
 
-                err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
-                                 EXT_CSD_BUS_WIDTH, ext_csd_bit);
-
-                if (err && err != -EBADMSG)
-                        goto free_card;
-
+                if (!err && ddr) {
+                        err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
+                                        EXT_CSD_BUS_WIDTH,
+                                        ext_csd_bits[idx][1]);
+                }
                 if (err) {
                         printk(KERN_WARNING "%s: switch to bus width %d ddr %d "
-                               "failed\n", mmc_hostname(card->host),
-                               1 << bus_width, ddr);
-                        err = 0;
-                } else {
-                        if (ddr)
-                                mmc_card_set_ddr_mode(card);
-                        else
-                                ddr = MMC_SDR_MODE;
-
+                                "failed\n", mmc_hostname(card->host),
+                                1 << bus_width, ddr);
+                        goto free_card;
+                } else if (ddr) {
+                        mmc_card_set_ddr_mode(card);
                         mmc_set_bus_width_ddr(card->host, bus_width, ddr);
                 }
         }
@@ -737,14 +755,21 @@ static void mmc_attach_bus_ops(struct mmc_host *host)
 /*
  * Starting point for MMC card init.
  */
-int mmc_attach_mmc(struct mmc_host *host, u32 ocr)
+int mmc_attach_mmc(struct mmc_host *host)
 {
         int err;
+        u32 ocr;
 
         BUG_ON(!host);
         WARN_ON(!host->claimed);
 
+        err = mmc_send_op_cond(host, 0, &ocr);
+        if (err)
+                return err;
+
         mmc_attach_bus_ops(host);
+        if (host->ocr_avail_mmc)
+                host->ocr_avail = host->ocr_avail_mmc;
 
         /*
          * We need to get OCR a different way for SPI.
@@ -784,20 +809,20 @@ int mmc_attach_mmc(struct mmc_host *host, u32 ocr)
                 goto err;
 
         mmc_release_host(host);
-
         err = mmc_add_card(host->card);
+        mmc_claim_host(host);
         if (err)
                 goto remove_card;
 
         return 0;
 
 remove_card:
+        mmc_release_host(host);
         mmc_remove_card(host->card);
-        host->card = NULL;
         mmc_claim_host(host);
+        host->card = NULL;
 err:
         mmc_detach_bus(host);
-        mmc_release_host(host);
 
         printk(KERN_ERR "%s: error %d whilst initialising MMC card\n",
                 mmc_hostname(host), err);
diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c
index 326447c9ede8..60842f878ded 100644
--- a/drivers/mmc/core/mmc_ops.c
+++ b/drivers/mmc/core/mmc_ops.c
@@ -462,3 +462,104 @@ int mmc_send_status(struct mmc_card *card, u32 *status)
         return 0;
 }
 
+static int
+mmc_send_bus_test(struct mmc_card *card, struct mmc_host *host, u8 opcode,
+                  u8 len)
+{
+        struct mmc_request mrq;
+        struct mmc_command cmd;
+        struct mmc_data data;
+        struct scatterlist sg;
+        u8 *data_buf;
+        u8 *test_buf;
+        int i, err;
+        static u8 testdata_8bit[8] = { 0x55, 0xaa, 0, 0, 0, 0, 0, 0 };
+        static u8 testdata_4bit[4] = { 0x5a, 0, 0, 0 };
+
+        /* dma onto stack is unsafe/nonportable, but callers to this
+         * routine normally provide temporary on-stack buffers ...
+         */
+        data_buf = kmalloc(len, GFP_KERNEL);
+        if (!data_buf)
+                return -ENOMEM;
+
+        if (len == 8)
+                test_buf = testdata_8bit;
+        else if (len == 4)
+                test_buf = testdata_4bit;
+        else {
+                printk(KERN_ERR "%s: Invalid bus_width %d\n",
+                       mmc_hostname(host), len);
+                kfree(data_buf);
+                return -EINVAL;
+        }
+
+        if (opcode == MMC_BUS_TEST_W)
+                memcpy(data_buf, test_buf, len);
+
+        memset(&mrq, 0, sizeof(struct mmc_request));
+        memset(&cmd, 0, sizeof(struct mmc_command));
+        memset(&data, 0, sizeof(struct mmc_data));
+
+        mrq.cmd = &cmd;
+        mrq.data = &data;
+        cmd.opcode = opcode;
+        cmd.arg = 0;
+
+        /* NOTE HACK:  the MMC_RSP_SPI_R1 is always correct here, but we
+         * rely on callers to never use this with "native" calls for reading
+         * CSD or CID.  Native versions of those commands use the R2 type,
+         * not R1 plus a data block.
+         */
+        cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_ADTC;
+
+        data.blksz = len;
+        data.blocks = 1;
+        if (opcode == MMC_BUS_TEST_R)
+                data.flags = MMC_DATA_READ;
+        else
+                data.flags = MMC_DATA_WRITE;
+
+        data.sg = &sg;
+        data.sg_len = 1;
+        sg_init_one(&sg, data_buf, len);
+        mmc_wait_for_req(host, &mrq);
+        err = 0;
+        if (opcode == MMC_BUS_TEST_R) {
+                for (i = 0; i < len / 4; i++)
+                        if ((test_buf[i] ^ data_buf[i]) != 0xff) {
+                                err = -EIO;
+                                break;
+                        }
+        }
+        kfree(data_buf);
+
+        if (cmd.error)
+                return cmd.error;
+        if (data.error)
+                return data.error;
+
+        return err;
+}
+
+int mmc_bus_test(struct mmc_card *card, u8 bus_width)
+{
+        int err, width;
+
+        if (bus_width == MMC_BUS_WIDTH_8)
+                width = 8;
+        else if (bus_width == MMC_BUS_WIDTH_4)
+                width = 4;
+        else if (bus_width == MMC_BUS_WIDTH_1)
+                return 0; /* no need for test */
+        else
+                return -EINVAL;
+
+        /*
+         * Ignore errors from BUS_TEST_W.  BUS_TEST_R will fail if there
+         * is a problem.  This improves chances that the test will work.
+         */
+        mmc_send_bus_test(card, card->host, MMC_BUS_TEST_W, width);
+        err = mmc_send_bus_test(card, card->host, MMC_BUS_TEST_R, width);
+        return err;
+}
diff --git a/drivers/mmc/core/mmc_ops.h b/drivers/mmc/core/mmc_ops.h
index 653eb8e84178..e6d44b8a18db 100644
--- a/drivers/mmc/core/mmc_ops.h
+++ b/drivers/mmc/core/mmc_ops.h
@@ -26,6 +26,7 @@ int mmc_send_cid(struct mmc_host *host, u32 *cid);
 int mmc_spi_read_ocr(struct mmc_host *host, int highcap, u32 *ocrp);
 int mmc_spi_set_crc(struct mmc_host *host, int use_crc);
 int mmc_card_sleepawake(struct mmc_host *host, int sleep);
+int mmc_bus_test(struct mmc_card *card, u8 bus_width);
 
 #endif
 
diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c
index 49da4dffd28e..d18c32bca99b 100644
--- a/drivers/mmc/core/sd.c
+++ b/drivers/mmc/core/sd.c
@@ -764,14 +764,21 @@ static void mmc_sd_attach_bus_ops(struct mmc_host *host)
 /*
  * Starting point for SD card init.
  */
-int mmc_attach_sd(struct mmc_host *host, u32 ocr)
+int mmc_attach_sd(struct mmc_host *host)
 {
         int err;
+        u32 ocr;
 
         BUG_ON(!host);
         WARN_ON(!host->claimed);
 
+        err = mmc_send_app_op_cond(host, 0, &ocr);
+        if (err)
+                return err;
+
         mmc_sd_attach_bus_ops(host);
+        if (host->ocr_avail_sd)
+                host->ocr_avail = host->ocr_avail_sd;
 
         /*
          * We need to get OCR a different way for SPI.
@@ -795,7 +802,8 @@ int mmc_attach_sd(struct mmc_host *host, u32 ocr)
                 ocr &= ~0x7F;
         }
 
-        if (ocr & MMC_VDD_165_195) {
+        if ((ocr & MMC_VDD_165_195) &&
+            !(host->ocr_avail_sd & MMC_VDD_165_195)) {
                 printk(KERN_WARNING "%s: SD card claims to support the "
                        "incompletely defined 'low voltage range'. This "
                        "will be ignored.\n", mmc_hostname(host));
@@ -820,20 +828,20 @@ int mmc_attach_sd(struct mmc_host *host, u32 ocr)
                 goto err;
 
         mmc_release_host(host);
-
         err = mmc_add_card(host->card);
+        mmc_claim_host(host);
         if (err)
                 goto remove_card;
 
         return 0;
 
 remove_card:
+        mmc_release_host(host);
         mmc_remove_card(host->card);
         host->card = NULL;
         mmc_claim_host(host);
 err:
         mmc_detach_bus(host);
-        mmc_release_host(host);
 
         printk(KERN_ERR "%s: error %d whilst initialising SD card\n",
                 mmc_hostname(host), err);
diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c
index efef5f94ac42..5c4a54d9b6a4 100644
--- a/drivers/mmc/core/sdio.c
+++ b/drivers/mmc/core/sdio.c
@@ -627,15 +627,27 @@ static int mmc_sdio_suspend(struct mmc_host *host)
 
 static int mmc_sdio_resume(struct mmc_host *host)
 {
-        int i, err;
+        int i, err = 0;
 
         BUG_ON(!host);
         BUG_ON(!host->card);
 
         /* Basic card reinitialization. */
         mmc_claim_host(host);
-        err = mmc_sdio_init_card(host, host->ocr, host->card,
+
+        /* No need to reinitialize powered-resumed nonremovable cards */
+        if (mmc_card_is_removable(host) || !mmc_card_is_powered_resumed(host))
+                err = mmc_sdio_init_card(host, host->ocr, host->card,
                                  (host->pm_flags & MMC_PM_KEEP_POWER));
+        else if (mmc_card_is_powered_resumed(host)) {
+                /* We may have switched to 1-bit mode during suspend */
+                err = sdio_enable_4bit_bus(host->card);
+                if (err > 0) {
+                        mmc_set_bus_width(host, MMC_BUS_WIDTH_4);
+                        err = 0;
+                }
+        }
+
         if (!err && host->sdio_irqs)
                 mmc_signal_sdio_irq(host);
         mmc_release_host(host);
@@ -690,16 +702,22 @@ static const struct mmc_bus_ops mmc_sdio_ops = {
 /*
  * Starting point for SDIO card init.
  */
-int mmc_attach_sdio(struct mmc_host *host, u32 ocr)
+int mmc_attach_sdio(struct mmc_host *host)
 {
-        int err;
-        int i, funcs;
+        int err, i, funcs;
+        u32 ocr;
         struct mmc_card *card;
 
         BUG_ON(!host);
         WARN_ON(!host->claimed);
 
+        err = mmc_send_io_op_cond(host, 0, &ocr);
+        if (err)
+                return err;
+
         mmc_attach_bus(host, &mmc_sdio_ops);
+        if (host->ocr_avail_sdio)
+                host->ocr_avail = host->ocr_avail_sdio;
 
         /*
          * Sanity check the voltages that the card claims to
@@ -769,12 +787,12 @@ int mmc_attach_sdio(struct mmc_host *host, u32 ocr)
                         pm_runtime_enable(&card->sdio_func[i]->dev);
         }
 
-        mmc_release_host(host);
-
         /*
          * First add the card to the driver model...
          */
+        mmc_release_host(host);
         err = mmc_add_card(host->card);
+        mmc_claim_host(host);
         if (err)
                 goto remove_added;
 
@@ -792,15 +810,17 @@ int mmc_attach_sdio(struct mmc_host *host, u32 ocr)
 
 remove_added:
         /* Remove without lock if the device has been added. */
+        mmc_release_host(host);
         mmc_sdio_remove(host);
         mmc_claim_host(host);
 remove:
         /* And with lock if it hasn't been added. */
+        mmc_release_host(host);
         if (host->card)
                 mmc_sdio_remove(host);
+        mmc_claim_host(host);
 err:
         mmc_detach_bus(host);
-        mmc_release_host(host);
 
         printk(KERN_ERR "%s: error %d whilst initialising SDIO card\n",
                 mmc_hostname(host), err);
diff --git a/drivers/mmc/core/sdio_bus.c b/drivers/mmc/core/sdio_bus.c
index 203da443e339..d29b9c36919a 100644
--- a/drivers/mmc/core/sdio_bus.c
+++ b/drivers/mmc/core/sdio_bus.c
@@ -197,44 +197,12 @@ out:
 
 #ifdef CONFIG_PM_RUNTIME
 
-static int sdio_bus_pm_prepare(struct device *dev)
-{
-        struct sdio_func *func = dev_to_sdio_func(dev);
-
-        /*
-         * Resume an SDIO device which was suspended at run time at this
-         * point, in order to allow standard SDIO suspend/resume paths
-         * to keep working as usual.
-         *
-         * Ultimately, the SDIO driver itself will decide (in its
-         * suspend handler, or lack thereof) whether the card should be
-         * removed or kept, and if kept, at what power state.
-         *
-         * At this point, PM core have increased our use count, so it's
-         * safe to directly resume the device. After system is resumed
-         * again, PM core will drop back its runtime PM use count, and if
-         * needed device will be suspended again.
-         *
-         * The end result is guaranteed to be a power state that is
-         * coherent with the device's runtime PM use count.
-         *
-         * The return value of pm_runtime_resume is deliberately unchecked
-         * since there is little point in failing system suspend if a
-         * device can't be resumed.
-         */
-        if (func->card->host->caps & MMC_CAP_POWER_OFF_CARD)
-                pm_runtime_resume(dev);
-
-        return 0;
-}
-
 static const struct dev_pm_ops sdio_bus_pm_ops = {
         SET_RUNTIME_PM_OPS(
                 pm_generic_runtime_suspend,
                 pm_generic_runtime_resume,
                 pm_generic_runtime_idle
         )
-        .prepare = sdio_bus_pm_prepare,
 };
 
 #define SDIO_PM_OPS_PTR (&sdio_bus_pm_ops)
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index e960a9300eb2..c22a4c039988 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -142,6 +142,27 @@ config MMC_SDHCI_ESDHC_IMX
 
           If unsure, say N.
 
+config MMC_SDHCI_DOVE
+        bool "SDHCI support on Marvell's Dove SoC"
+        depends on ARCH_DOVE
+        depends on MMC_SDHCI_PLTFM
+        select MMC_SDHCI_IO_ACCESSORS
+        help
+          This selects the Secure Digital Host Controller Interface in
+          Marvell's Dove SoC.
+
+          If unsure, say N.
+
+config MMC_SDHCI_TEGRA
+        tristate "SDHCI platform support for the Tegra SD/MMC Controller"
+        depends on MMC_SDHCI_PLTFM && ARCH_TEGRA
+        select MMC_SDHCI_IO_ACCESSORS
+        help
+          This selects the Tegra SD/MMC controller. If you have a Tegra
+          platform with SD or MMC devices, say Y or M here.
+
+          If unsure, say N.
+
 config MMC_SDHCI_S3C
         tristate "SDHCI support on Samsung S3C SoC"
         depends on MMC_SDHCI && PLAT_SAMSUNG
@@ -460,6 +481,22 @@ config SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
         help
           If you say yes here SD-Cards may work on the EZkit.
 
+config MMC_DW
+        tristate "Synopsys DesignWare Memory Card Interface"
+        depends on ARM
+        help
+          This selects support for the Synopsys DesignWare Mobile Storage IP
+          block, this provides host support for SD and MMC interfaces, in both
+          PIO and external DMA modes.
+
+config MMC_DW_IDMAC
+        bool "Internal DMAC interface"
+        depends on MMC_DW
+        help
+          This selects support for the internal DMAC block within the Synopsys
+          Designware Mobile Storage IP block. This disables the external DMA
+          interface.
+
 config MMC_SH_MMCIF
         tristate "SuperH Internal MMCIF support"
         depends on MMC_BLOCK && (SUPERH || ARCH_SHMOBILE)
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 7b645ff43b30..e834fb223e9a 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_MMC_TMIO)		+= tmio_mmc.o
 obj-$(CONFIG_MMC_CB710) += cb710-mmc.o
 obj-$(CONFIG_MMC_VIA_SDMMC)     += via-sdmmc.o
 obj-$(CONFIG_SDH_BFIN)          += bfin_sdh.o
+obj-$(CONFIG_MMC_DW)            += dw_mmc.o
 obj-$(CONFIG_MMC_SH_MMCIF)      += sh_mmcif.o
 obj-$(CONFIG_MMC_JZ4740)        += jz4740_mmc.o
 obj-$(CONFIG_MMC_USHC)          += ushc.o
@@ -39,6 +40,8 @@ obj-$(CONFIG_MMC_SDHCI_PLTFM)			+= sdhci-platform.o
 sdhci-platform-y                                := sdhci-pltfm.o
 sdhci-platform-$(CONFIG_MMC_SDHCI_CNS3XXX)      += sdhci-cns3xxx.o
 sdhci-platform-$(CONFIG_MMC_SDHCI_ESDHC_IMX)    += sdhci-esdhc-imx.o
+sdhci-platform-$(CONFIG_MMC_SDHCI_DOVE)         += sdhci-dove.o
+sdhci-platform-$(CONFIG_MMC_SDHCI_TEGRA)        += sdhci-tegra.o
 
 obj-$(CONFIG_MMC_SDHCI_OF)      += sdhci-of.o
 sdhci-of-y                              := sdhci-of-core.o
diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c
index e15547cf701f..0076c7448fe6 100644
--- a/drivers/mmc/host/davinci_mmc.c
+++ b/drivers/mmc/host/davinci_mmc.c
@@ -66,8 +66,8 @@
 #define DAVINCI_MMCBLNC      0x60
 #define DAVINCI_SDIOCTL      0x64
 #define DAVINCI_SDIOST0      0x68
-#define DAVINCI_SDIOEN       0x6C
-#define DAVINCI_SDIOST       0x70
+#define DAVINCI_SDIOIEN      0x6C
+#define DAVINCI_SDIOIST      0x70
 #define DAVINCI_MMCFIFOCTL   0x74 /* FIFO Control Register             */
 
 /* DAVINCI_MMCCTL definitions */
@@ -131,6 +131,14 @@
 #define MMCFIFOCTL_ACCWD_2    (2 << 3) /* access width of 2 bytes    */
 #define MMCFIFOCTL_ACCWD_1    (3 << 3) /* access width of 1 byte     */
 
+/* DAVINCI_SDIOST0 definitions */
+#define SDIOST0_DAT1_HI       BIT(0)
+
+/* DAVINCI_SDIOIEN definitions */
+#define SDIOIEN_IOINTEN       BIT(0)
+
+/* DAVINCI_SDIOIST definitions */
+#define SDIOIST_IOINT         BIT(0)
 
 /* MMCSD Init clock in Hz in opendrain mode */
 #define MMCSD_INIT_CLOCK                200000
@@ -164,7 +172,7 @@ struct mmc_davinci_host {
         unsigned int mmc_input_clk;
         void __iomem *base;
         struct resource *mem_res;
-        int irq;
+        int mmc_irq, sdio_irq;
         unsigned char bus_mode;
 
 #define DAVINCI_MMC_DATADIR_NONE        0
@@ -184,6 +192,7 @@ struct mmc_davinci_host {
         u32 rxdma, txdma;
         bool use_dma;
         bool do_dma;
+        bool sdio_int;
 
         /* Scatterlist DMA uses one or more parameter RAM entries:
          * the main one (associated with rxdma or txdma) plus zero or
@@ -480,7 +489,7 @@ static void mmc_davinci_send_dma_request(struct mmc_davinci_host *host,
         struct scatterlist      *sg;
         unsigned                sg_len;
         unsigned                bytes_left = host->bytes_left;
-        const unsigned          shift = ffs(rw_threshold) - 1;;
+        const unsigned          shift = ffs(rw_threshold) - 1;
 
         if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
                 template = &host->tx_template;
@@ -866,6 +875,19 @@ mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data)
 {
         host->data = NULL;
 
+        if (host->mmc->caps & MMC_CAP_SDIO_IRQ) {
+                /*
+                 * SDIO Interrupt Detection work-around as suggested by
+                 * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata
+                 * 2.1.6): Signal SDIO interrupt only if it is enabled by core
+                 */
+                if (host->sdio_int && !(readl(host->base + DAVINCI_SDIOST0) &
+                                        SDIOST0_DAT1_HI)) {
+                        writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
+                        mmc_signal_sdio_irq(host->mmc);
+                }
+        }
+
         if (host->do_dma) {
                 davinci_abort_dma(host);
 
@@ -932,6 +954,21 @@ davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data)
         mmc_davinci_reset_ctrl(host, 0);
 }
 
+static irqreturn_t mmc_davinci_sdio_irq(int irq, void *dev_id)
+{
+        struct mmc_davinci_host *host = dev_id;
+        unsigned int status;
+
+        status = readl(host->base + DAVINCI_SDIOIST);
+        if (status & SDIOIST_IOINT) {
+                dev_dbg(mmc_dev(host->mmc),
+                        "SDIO interrupt status %x\n", status);
+                writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
+                mmc_signal_sdio_irq(host->mmc);
+        }
+        return IRQ_HANDLED;
+}
+
 static irqreturn_t mmc_davinci_irq(int irq, void *dev_id)
 {
         struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id;
@@ -1076,11 +1113,32 @@ static int mmc_davinci_get_ro(struct mmc_host *mmc)
         return config->get_ro(pdev->id);
 }
 
+static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+        struct mmc_davinci_host *host = mmc_priv(mmc);
+
+        if (enable) {
+                if (!(readl(host->base + DAVINCI_SDIOST0) & SDIOST0_DAT1_HI)) {
+                        writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
+                        mmc_signal_sdio_irq(host->mmc);
+                } else {
+                        host->sdio_int = true;
+                        writel(readl(host->base + DAVINCI_SDIOIEN) |
+                               SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN);
+                }
+        } else {
+                host->sdio_int = false;
+                writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN,
+                       host->base + DAVINCI_SDIOIEN);
+        }
+}
+
 static struct mmc_host_ops mmc_davinci_ops = {
         .request        = mmc_davinci_request,
         .set_ios        = mmc_davinci_set_ios,
         .get_cd         = mmc_davinci_get_cd,
         .get_ro         = mmc_davinci_get_ro,
+        .enable_sdio_irq = mmc_davinci_enable_sdio_irq,
 };
 
 /*----------------------------------------------------------------------*/
@@ -1209,7 +1267,8 @@ static int __init davinci_mmcsd_probe(struct platform_device *pdev)
                 host->nr_sg = MAX_NR_SG;
 
         host->use_dma = use_dma;
-        host->irq = irq;
+        host->mmc_irq = irq;
+        host->sdio_irq = platform_get_irq(pdev, 1);
 
         if (host->use_dma && davinci_acquire_dma_channels(host) != 0)
                 host->use_dma = 0;
@@ -1270,6 +1329,13 @@ static int __init davinci_mmcsd_probe(struct platform_device *pdev)
         if (ret)
                 goto out;
 
+        if (host->sdio_irq >= 0) {
+                ret = request_irq(host->sdio_irq, mmc_davinci_sdio_irq, 0,
+                                  mmc_hostname(mmc), host);
+                if (!ret)
+                        mmc->caps |= MMC_CAP_SDIO_IRQ;
+        }
+
         rename_region(mem, mmc_hostname(mmc));
 
         dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n",
@@ -1313,7 +1379,9 @@ static int __exit davinci_mmcsd_remove(struct platform_device *pdev)
                 mmc_davinci_cpufreq_deregister(host);
 
                 mmc_remove_host(host->mmc);
-                free_irq(host->irq, host);
+                free_irq(host->mmc_irq, host);
+                if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
+                        free_irq(host->sdio_irq, host);
 
                 davinci_release_dma_channels(host);
 
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
new file mode 100644
index 000000000000..2fcc82577c1b
--- /dev/null
+++ b/drivers/mmc/host/dw_mmc.c
@@ -0,0 +1,1796 @@
+/*
+ * Synopsys DesignWare Multimedia Card Interface driver
+ *  (Based on NXP driver for lpc 31xx)
+ *
+ * Copyright (C) 2009 NXP Semiconductors
+ * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/blkdev.h>
+#include <linux/clk.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/scatterlist.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+#include <linux/stat.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/dw_mmc.h>
+#include <linux/bitops.h>
+
+#include "dw_mmc.h"
+
+/* Common flag combinations */
+#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
+                                 SDMMC_INT_HTO | SDMMC_INT_SBE  | \
+                                 SDMMC_INT_EBE)
+#define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
+                                 SDMMC_INT_RESP_ERR)
+#define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
+                                 DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
+#define DW_MCI_SEND_STATUS      1
+#define DW_MCI_RECV_STATUS      2
+#define DW_MCI_DMA_THRESHOLD    16
+
+#ifdef CONFIG_MMC_DW_IDMAC
+struct idmac_desc {
+        u32             des0;   /* Control Descriptor */
+#define IDMAC_DES0_DIC  BIT(1)
+#define IDMAC_DES0_LD   BIT(2)
+#define IDMAC_DES0_FD   BIT(3)
+#define IDMAC_DES0_CH   BIT(4)
+#define IDMAC_DES0_ER   BIT(5)
+#define IDMAC_DES0_CES  BIT(30)
+#define IDMAC_DES0_OWN  BIT(31)
+
+        u32             des1;   /* Buffer sizes */
+#define IDMAC_SET_BUFFER1_SIZE(d, s) \
+        ((d)->des1 = ((d)->des1 & 0x03ffc000) | ((s) & 0x3fff))
+
+        u32             des2;   /* buffer 1 physical address */
+
+        u32             des3;   /* buffer 2 physical address */
+};
+#endif /* CONFIG_MMC_DW_IDMAC */
+
+/**
+ * struct dw_mci_slot - MMC slot state
+ * @mmc: The mmc_host representing this slot.
+ * @host: The MMC controller this slot is using.
+ * @ctype: Card type for this slot.
+ * @mrq: mmc_request currently being processed or waiting to be
+ *      processed, or NULL when the slot is idle.
+ * @queue_node: List node for placing this node in the @queue list of
+ *      &struct dw_mci.
+ * @clock: Clock rate configured by set_ios(). Protected by host->lock.
+ * @flags: Random state bits associated with the slot.
+ * @id: Number of this slot.
+ * @last_detect_state: Most recently observed card detect state.
+ */
+struct dw_mci_slot {
+        struct mmc_host         *mmc;
+        struct dw_mci           *host;
+
+        u32                     ctype;
+
+        struct mmc_request      *mrq;
+        struct list_head        queue_node;
+
+        unsigned int            clock;
+        unsigned long           flags;
+#define DW_MMC_CARD_PRESENT     0
+#define DW_MMC_CARD_NEED_INIT   1
+        int                     id;
+        int                     last_detect_state;
+};
+
+#if defined(CONFIG_DEBUG_FS)
+static int dw_mci_req_show(struct seq_file *s, void *v)
+{
+        struct dw_mci_slot *slot = s->private;
+        struct mmc_request *mrq;
+        struct mmc_command *cmd;
+        struct mmc_command *stop;
+        struct mmc_data *data;
+
+        /* Make sure we get a consistent snapshot */
+        spin_lock_bh(&slot->host->lock);
+        mrq = slot->mrq;
+
+        if (mrq) {
+                cmd = mrq->cmd;
+                data = mrq->data;
+                stop = mrq->stop;
+
+                if (cmd)
+                        seq_printf(s,
+                                   "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
+                                   cmd->opcode, cmd->arg, cmd->flags,
+                                   cmd->resp[0], cmd->resp[1], cmd->resp[2],
+                                   cmd->resp[2], cmd->error);
+                if (data)
+                        seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
+                                   data->bytes_xfered, data->blocks,
+                                   data->blksz, data->flags, data->error);
+                if (stop)
+                        seq_printf(s,
+                                   "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
+                                   stop->opcode, stop->arg, stop->flags,
+                                   stop->resp[0], stop->resp[1], stop->resp[2],
+                                   stop->resp[2], stop->error);
+        }
+
+        spin_unlock_bh(&slot->host->lock);
+
+        return 0;
+}
+
+static int dw_mci_req_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, dw_mci_req_show, inode->i_private);
+}
+
+static const struct file_operations dw_mci_req_fops = {
+        .owner          = THIS_MODULE,
+        .open           = dw_mci_req_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static int dw_mci_regs_show(struct seq_file *s, void *v)
+{
+        seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
+        seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
+        seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
+        seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
+        seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
+        seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
+
+        return 0;
+}
+
+static int dw_mci_regs_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, dw_mci_regs_show, inode->i_private);
+}
+
+static const struct file_operations dw_mci_regs_fops = {
+        .owner          = THIS_MODULE,
+        .open           = dw_mci_regs_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
+{
+        struct mmc_host *mmc = slot->mmc;
+        struct dw_mci *host = slot->host;
+        struct dentry *root;
+        struct dentry *node;
+
+        root = mmc->debugfs_root;
+        if (!root)
+                return;
+
+        node = debugfs_create_file("regs", S_IRUSR, root, host,
+                                   &dw_mci_regs_fops);
+        if (!node)
+                goto err;
+
+        node = debugfs_create_file("req", S_IRUSR, root, slot,
+                                   &dw_mci_req_fops);
+        if (!node)
+                goto err;
+
+        node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
+        if (!node)
+                goto err;
+
+        node = debugfs_create_x32("pending_events", S_IRUSR, root,
+                                  (u32 *)&host->pending_events);
+        if (!node)
+                goto err;
+
+        node = debugfs_create_x32("completed_events", S_IRUSR, root,
+                                  (u32 *)&host->completed_events);
+        if (!node)
+                goto err;
+
+        return;
+
+err:
+        dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
+}
+#endif /* defined(CONFIG_DEBUG_FS) */
+
+static void dw_mci_set_timeout(struct dw_mci *host)
+{
+        /* timeout (maximum) */
+        mci_writel(host, TMOUT, 0xffffffff);
+}
+
+static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
+{
+        struct mmc_data *data;
+        u32 cmdr;
+        cmd->error = -EINPROGRESS;
+
+        cmdr = cmd->opcode;
+
+        if (cmdr == MMC_STOP_TRANSMISSION)
+                cmdr |= SDMMC_CMD_STOP;
+        else
+                cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
+
+        if (cmd->flags & MMC_RSP_PRESENT) {
+                /* We expect a response, so set this bit */
+                cmdr |= SDMMC_CMD_RESP_EXP;
+                if (cmd->flags & MMC_RSP_136)
+                        cmdr |= SDMMC_CMD_RESP_LONG;
+        }
+
+        if (cmd->flags & MMC_RSP_CRC)
+                cmdr |= SDMMC_CMD_RESP_CRC;
+
+        data = cmd->data;
+        if (data) {
+                cmdr |= SDMMC_CMD_DAT_EXP;
+                if (data->flags & MMC_DATA_STREAM)
+                        cmdr |= SDMMC_CMD_STRM_MODE;
+                if (data->flags & MMC_DATA_WRITE)
+                        cmdr |= SDMMC_CMD_DAT_WR;
+        }
+
+        return cmdr;
+}
+
+static void dw_mci_start_command(struct dw_mci *host,
+                                 struct mmc_command *cmd, u32 cmd_flags)
+{
+        host->cmd = cmd;
+        dev_vdbg(&host->pdev->dev,
+                 "start command: ARGR=0x%08x CMDR=0x%08x\n",
+                 cmd->arg, cmd_flags);
+
+        mci_writel(host, CMDARG, cmd->arg);
+        wmb();
+
+        mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
+}
+
+static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
+{
+        dw_mci_start_command(host, data->stop, host->stop_cmdr);
+}
+
+/* DMA interface functions */
+static void dw_mci_stop_dma(struct dw_mci *host)
+{
+        if (host->use_dma) {
+                host->dma_ops->stop(host);
+                host->dma_ops->cleanup(host);
+        } else {
+                /* Data transfer was stopped by the interrupt handler */
+                set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
+        }
+}
+
+#ifdef CONFIG_MMC_DW_IDMAC
+static void dw_mci_dma_cleanup(struct dw_mci *host)
+{
+        struct mmc_data *data = host->data;
+
+        if (data)
+                dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
+                             ((data->flags & MMC_DATA_WRITE)
+                              ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
+}
+
+static void dw_mci_idmac_stop_dma(struct dw_mci *host)
+{
+        u32 temp;
+
+        /* Disable and reset the IDMAC interface */
+        temp = mci_readl(host, CTRL);
+        temp &= ~SDMMC_CTRL_USE_IDMAC;
+        temp |= SDMMC_CTRL_DMA_RESET;
+        mci_writel(host, CTRL, temp);
+
+        /* Stop the IDMAC running */
+        temp = mci_readl(host, BMOD);
+        temp &= ~SDMMC_IDMAC_ENABLE;
+        mci_writel(host, BMOD, temp);
+}
+
+static void dw_mci_idmac_complete_dma(struct dw_mci *host)
+{
+        struct mmc_data *data = host->data;
+
+        dev_vdbg(&host->pdev->dev, "DMA complete\n");
+
+        host->dma_ops->cleanup(host);
+
+        /*
+         * If the card was removed, data will be NULL. No point in trying to
+         * send the stop command or waiting for NBUSY in this case.
+         */
+        if (data) {
+                set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
+                tasklet_schedule(&host->tasklet);
+        }
+}
+
+static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
+                                    unsigned int sg_len)
+{
+        int i;
+        struct idmac_desc *desc = host->sg_cpu;
+
+        for (i = 0; i < sg_len; i++, desc++) {
+                unsigned int length = sg_dma_len(&data->sg[i]);
+                u32 mem_addr = sg_dma_address(&data->sg[i]);
+
+                /* Set the OWN bit and disable interrupts for this descriptor */
+                desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
+
+                /* Buffer length */
+                IDMAC_SET_BUFFER1_SIZE(desc, length);
+
+                /* Physical address to DMA to/from */
+                desc->des2 = mem_addr;
+        }
+
+        /* Set first descriptor */
+        desc = host->sg_cpu;
+        desc->des0 |= IDMAC_DES0_FD;
+
+        /* Set last descriptor */
+        desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
+        desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
+        desc->des0 |= IDMAC_DES0_LD;
+
+        wmb();
+}
+
+static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
+{
+        u32 temp;
+
+        dw_mci_translate_sglist(host, host->data, sg_len);
+
+        /* Select IDMAC interface */
+        temp = mci_readl(host, CTRL);
+        temp |= SDMMC_CTRL_USE_IDMAC;
+        mci_writel(host, CTRL, temp);
+
+        wmb();
+
+        /* Enable the IDMAC */
+        temp = mci_readl(host, BMOD);
+        temp |= SDMMC_IDMAC_ENABLE;
+        mci_writel(host, BMOD, temp);
+
+        /* Start it running */
+        mci_writel(host, PLDMND, 1);
+}
+
+static int dw_mci_idmac_init(struct dw_mci *host)
+{
+        struct idmac_desc *p;
+        int i;
+
+        /* Number of descriptors in the ring buffer */
+        host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
+
+        /* Forward link the descriptor list */
+        for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
+                p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
+
+        /* Set the last descriptor as the end-of-ring descriptor */
+        p->des3 = host->sg_dma;
+        p->des0 = IDMAC_DES0_ER;
+
+        /* Mask out interrupts - get Tx & Rx complete only */
+        mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
+                   SDMMC_IDMAC_INT_TI);
+
+        /* Set the descriptor base address */
+        mci_writel(host, DBADDR, host->sg_dma);
+        return 0;
+}
+
+static struct dw_mci_dma_ops dw_mci_idmac_ops = {
+        .init = dw_mci_idmac_init,
+        .start = dw_mci_idmac_start_dma,
+        .stop = dw_mci_idmac_stop_dma,
+        .complete = dw_mci_idmac_complete_dma,
+        .cleanup = dw_mci_dma_cleanup,
+};
+#endif /* CONFIG_MMC_DW_IDMAC */
+
+static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
+{
+        struct scatterlist *sg;
+        unsigned int i, direction, sg_len;
+        u32 temp;
+
+        /* If we don't have a channel, we can't do DMA */
+        if (!host->use_dma)
+                return -ENODEV;
+
+        /*
+         * We don't do DMA on "complex" transfers, i.e. with
+         * non-word-aligned buffers or lengths. Also, we don't bother
+         * with all the DMA setup overhead for short transfers.
+         */
+        if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
+                return -EINVAL;
+        if (data->blksz & 3)
+                return -EINVAL;
+
+        for_each_sg(data->sg, sg, data->sg_len, i) {
+                if (sg->offset & 3 || sg->length & 3)
+                        return -EINVAL;
+        }
+
+        if (data->flags & MMC_DATA_READ)
+                direction = DMA_FROM_DEVICE;
+        else
+                direction = DMA_TO_DEVICE;
+
+        sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
+                            direction);
+
+        dev_vdbg(&host->pdev->dev,
+                 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
+                 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
+                 sg_len);
+
+        /* Enable the DMA interface */
+        temp = mci_readl(host, CTRL);
+        temp |= SDMMC_CTRL_DMA_ENABLE;
+        mci_writel(host, CTRL, temp);
+
+        /* Disable RX/TX IRQs, let DMA handle it */
+        temp = mci_readl(host, INTMASK);
+        temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
+        mci_writel(host, INTMASK, temp);
+
+        host->dma_ops->start(host, sg_len);
+
+        return 0;
+}
+
+static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
+{
+        u32 temp;
+
+        data->error = -EINPROGRESS;
+
+        WARN_ON(host->data);
+        host->sg = NULL;
+        host->data = data;
+
+        if (dw_mci_submit_data_dma(host, data)) {
+                host->sg = data->sg;
+                host->pio_offset = 0;
+                if (data->flags & MMC_DATA_READ)
+                        host->dir_status = DW_MCI_RECV_STATUS;
+                else
+                        host->dir_status = DW_MCI_SEND_STATUS;
+
+                temp = mci_readl(host, INTMASK);
+                temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
+                mci_writel(host, INTMASK, temp);
+
+                temp = mci_readl(host, CTRL);
+                temp &= ~SDMMC_CTRL_DMA_ENABLE;
+                mci_writel(host, CTRL, temp);
+        }
+}
+
+static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
+{
+        struct dw_mci *host = slot->host;
+        unsigned long timeout = jiffies + msecs_to_jiffies(500);
+        unsigned int cmd_status = 0;
+
+        mci_writel(host, CMDARG, arg);
+        wmb();
+        mci_writel(host, CMD, SDMMC_CMD_START | cmd);
+
+        while (time_before(jiffies, timeout)) {
+                cmd_status = mci_readl(host, CMD);
+                if (!(cmd_status & SDMMC_CMD_START))
+                        return;
+        }
+        dev_err(&slot->mmc->class_dev,
+                "Timeout sending command (cmd %#x arg %#x status %#x)\n",
+                cmd, arg, cmd_status);
+}
+
+static void dw_mci_setup_bus(struct dw_mci_slot *slot)
+{
+        struct dw_mci *host = slot->host;
+        u32 div;
+
+        if (slot->clock != host->current_speed) {
+                if (host->bus_hz % slot->clock)
+                        /*
+                         * move the + 1 after the divide to prevent
+                         * over-clocking the card.
+                         */
+                        div = ((host->bus_hz / slot->clock) >> 1) + 1;
+                else
+                        div = (host->bus_hz  / slot->clock) >> 1;
+
+                dev_info(&slot->mmc->class_dev,
+                         "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
+                         " div = %d)\n", slot->id, host->bus_hz, slot->clock,
+                         div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
+
+                /* disable clock */
+                mci_writel(host, CLKENA, 0);
+                mci_writel(host, CLKSRC, 0);
+
+                /* inform CIU */
+                mci_send_cmd(slot,
+                             SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
+
+                /* set clock to desired speed */
+                mci_writel(host, CLKDIV, div);
+
+                /* inform CIU */
+                mci_send_cmd(slot,
+                             SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
+
+                /* enable clock */
+                mci_writel(host, CLKENA, SDMMC_CLKEN_ENABLE);
+
+                /* inform CIU */
+                mci_send_cmd(slot,
+                             SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
+
+                host->current_speed = slot->clock;
+        }
+
+        /* Set the current slot bus width */
+        mci_writel(host, CTYPE, slot->ctype);
+}
+
+static void dw_mci_start_request(struct dw_mci *host,
+                                 struct dw_mci_slot *slot)
+{
+        struct mmc_request *mrq;
+        struct mmc_command *cmd;
+        struct mmc_data *data;
+        u32 cmdflags;
+
+        mrq = slot->mrq;
+        if (host->pdata->select_slot)
+                host->pdata->select_slot(slot->id);
+
+        /* Slot specific timing and width adjustment */
+        dw_mci_setup_bus(slot);
+
+        host->cur_slot = slot;
+        host->mrq = mrq;
+
+        host->pending_events = 0;
+        host->completed_events = 0;
+        host->data_status = 0;
+
+        data = mrq->data;
+        if (data) {
+                dw_mci_set_timeout(host);
+                mci_writel(host, BYTCNT, data->blksz*data->blocks);
+                mci_writel(host, BLKSIZ, data->blksz);
+        }
+
+        cmd = mrq->cmd;
+        cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
+
+        /* this is the first command, send the initialization clock */
+        if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
+                cmdflags |= SDMMC_CMD_INIT;
+
+        if (data) {
+                dw_mci_submit_data(host, data);
+                wmb();
+        }
+
+        dw_mci_start_command(host, cmd, cmdflags);
+
+        if (mrq->stop)
+                host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
+}
+
+static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
+                                 struct mmc_request *mrq)
+{
+        dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
+                 host->state);
+
+        spin_lock_bh(&host->lock);
+        slot->mrq = mrq;
+
+        if (host->state == STATE_IDLE) {
+                host->state = STATE_SENDING_CMD;
+                dw_mci_start_request(host, slot);
+        } else {
+                list_add_tail(&slot->queue_node, &host->queue);
+        }
+
+        spin_unlock_bh(&host->lock);
+}
+
+static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+        struct dw_mci_slot *slot = mmc_priv(mmc);
+        struct dw_mci *host = slot->host;
+
+        WARN_ON(slot->mrq);
+
+        if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
+                mrq->cmd->error = -ENOMEDIUM;
+                mmc_request_done(mmc, mrq);
+                return;
+        }
+
+        /* We don't support multiple blocks of weird lengths. */
+        dw_mci_queue_request(host, slot, mrq);
+}
+
+static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+        struct dw_mci_slot *slot = mmc_priv(mmc);
+
+        /* set default 1 bit mode */
+        slot->ctype = SDMMC_CTYPE_1BIT;
+
+        switch (ios->bus_width) {
+        case MMC_BUS_WIDTH_1:
+                slot->ctype = SDMMC_CTYPE_1BIT;
+                break;
+        case MMC_BUS_WIDTH_4:
+                slot->ctype = SDMMC_CTYPE_4BIT;
+                break;
+        }
+
+        if (ios->clock) {
+                /*
+                 * Use mirror of ios->clock to prevent race with mmc
+                 * core ios update when finding the minimum.
+                 */
+                slot->clock = ios->clock;
+        }
+
+        switch (ios->power_mode) {
+        case MMC_POWER_UP:
+                set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
+                break;
+        default:
+                break;
+        }
+}
+
+static int dw_mci_get_ro(struct mmc_host *mmc)
+{
+        int read_only;
+        struct dw_mci_slot *slot = mmc_priv(mmc);
+        struct dw_mci_board *brd = slot->host->pdata;
+
+        /* Use platform get_ro function, else try on board write protect */
+        if (brd->get_ro)
+                read_only = brd->get_ro(slot->id);
+        else
+                read_only =
+                        mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
+
+        dev_dbg(&mmc->class_dev, "card is %s\n",
+                read_only ? "read-only" : "read-write");
+
+        return read_only;
+}
+
+static int dw_mci_get_cd(struct mmc_host *mmc)
+{
+        int present;
+        struct dw_mci_slot *slot = mmc_priv(mmc);
+        struct dw_mci_board *brd = slot->host->pdata;
+
+        /* Use platform get_cd function, else try onboard card detect */
+        if (brd->get_cd)
+                present = !brd->get_cd(slot->id);
+        else
+                present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
+                        == 0 ? 1 : 0;
+
+        if (present)
+                dev_dbg(&mmc->class_dev, "card is present\n");
+        else
+                dev_dbg(&mmc->class_dev, "card is not present\n");
+
+        return present;
+}
+
+static const struct mmc_host_ops dw_mci_ops = {
+        .request        = dw_mci_request,
+        .set_ios        = dw_mci_set_ios,
+        .get_ro         = dw_mci_get_ro,
+        .get_cd         = dw_mci_get_cd,
+};
+
+static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
+        __releases(&host->lock)
+        __acquires(&host->lock)
+{
+        struct dw_mci_slot *slot;
+        struct mmc_host *prev_mmc = host->cur_slot->mmc;
+
+        WARN_ON(host->cmd || host->data);
+
+        host->cur_slot->mrq = NULL;
+        host->mrq = NULL;
+        if (!list_empty(&host->queue)) {
+                slot = list_entry(host->queue.next,
+                                  struct dw_mci_slot, queue_node);
+                list_del(&slot->queue_node);
+                dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
+                         mmc_hostname(slot->mmc));
+                host->state = STATE_SENDING_CMD;
+                dw_mci_start_request(host, slot);
+        } else {
+                dev_vdbg(&host->pdev->dev, "list empty\n");
+                host->state = STATE_IDLE;
+        }
+
+        spin_unlock(&host->lock);
+        mmc_request_done(prev_mmc, mrq);
+        spin_lock(&host->lock);
+}
+
+static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
+{
+        u32 status = host->cmd_status;
+
+        host->cmd_status = 0;
+
+        /* Read the response from the card (up to 16 bytes) */
+        if (cmd->flags & MMC_RSP_PRESENT) {
+                if (cmd->flags & MMC_RSP_136) {
+                        cmd->resp[3] = mci_readl(host, RESP0);
+                        cmd->resp[2] = mci_readl(host, RESP1);
+                        cmd->resp[1] = mci_readl(host, RESP2);
+                        cmd->resp[0] = mci_readl(host, RESP3);
+                } else {
+                        cmd->resp[0] = mci_readl(host, RESP0);
+                        cmd->resp[1] = 0;
+                        cmd->resp[2] = 0;
+                        cmd->resp[3] = 0;
+                }
+        }
+
+        if (status & SDMMC_INT_RTO)
+                cmd->error = -ETIMEDOUT;
+        else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
+                cmd->error = -EILSEQ;
+        else if (status & SDMMC_INT_RESP_ERR)
+                cmd->error = -EIO;
+        else
+                cmd->error = 0;
+
+        if (cmd->error) {
+                /* newer ip versions need a delay between retries */
+                if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
+                        mdelay(20);
+
+                if (cmd->data) {
+                        host->data = NULL;
+                        dw_mci_stop_dma(host);
+                }
+        }
+}
+
+static void dw_mci_tasklet_func(unsigned long priv)
+{
+        struct dw_mci *host = (struct dw_mci *)priv;
+        struct mmc_data *data;
+        struct mmc_command *cmd;
+        enum dw_mci_state state;
+        enum dw_mci_state prev_state;
+        u32 status;
+
+        spin_lock(&host->lock);
+
+        state = host->state;
+        data = host->data;
+
+        do {
+                prev_state = state;
+
+                switch (state) {
+                case STATE_IDLE:
+                        break;
+
+                case STATE_SENDING_CMD:
+                        if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
+                                                &host->pending_events))
+                                break;
+
+                        cmd = host->cmd;
+                        host->cmd = NULL;
+                        set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
+                        dw_mci_command_complete(host, host->mrq->cmd);
+                        if (!host->mrq->data || cmd->error) {
+                                dw_mci_request_end(host, host->mrq);
+                                goto unlock;
+                        }
+
+                        prev_state = state = STATE_SENDING_DATA;
+                        /* fall through */
+
+                case STATE_SENDING_DATA:
+                        if (test_and_clear_bit(EVENT_DATA_ERROR,
+                                               &host->pending_events)) {
+                                dw_mci_stop_dma(host);
+                                if (data->stop)
+                                        send_stop_cmd(host, data);
+                                state = STATE_DATA_ERROR;
+                                break;
+                        }
+
+                        if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
+                                                &host->pending_events))
+                                break;
+
+                        set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
+                        prev_state = state = STATE_DATA_BUSY;
+                        /* fall through */
+
+                case STATE_DATA_BUSY:
+                        if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
+                                                &host->pending_events))
+                                break;
+
+                        host->data = NULL;
+                        set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
+                        status = host->data_status;
+
+                        if (status & DW_MCI_DATA_ERROR_FLAGS) {
+                                if (status & SDMMC_INT_DTO) {
+                                        dev_err(&host->pdev->dev,
+                                                "data timeout error\n");
+                                        data->error = -ETIMEDOUT;
+                                } else if (status & SDMMC_INT_DCRC) {
+                                        dev_err(&host->pdev->dev,
+                                                "data CRC error\n");
+                                        data->error = -EILSEQ;
+                                } else {
+                                        dev_err(&host->pdev->dev,
+                                                "data FIFO error "
+                                                "(status=%08x)\n",
+                                                status);
+                                        data->error = -EIO;
+                                }
+                        } else {
+                                data->bytes_xfered = data->blocks * data->blksz;
+                                data->error = 0;
+                        }
+
+                        if (!data->stop) {
+                                dw_mci_request_end(host, host->mrq);
+                                goto unlock;
+                        }
+
+                        prev_state = state = STATE_SENDING_STOP;
+                        if (!data->error)
+                                send_stop_cmd(host, data);
+                        /* fall through */
+
+                case STATE_SENDING_STOP:
+                        if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
+                                                &host->pending_events))
+                                break;
+
+                        host->cmd = NULL;
+                        dw_mci_command_complete(host, host->mrq->stop);
+                        dw_mci_request_end(host, host->mrq);
+                        goto unlock;
+
+                case STATE_DATA_ERROR:
+                        if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
+                                                &host->pending_events))
+                                break;
+
+                        state = STATE_DATA_BUSY;
+                        break;
+                }
+        } while (state != prev_state);
+
+        host->state = state;
+unlock:
+        spin_unlock(&host->lock);
+
+}
+
+static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
+{
+        u16 *pdata = (u16 *)buf;
+
+        WARN_ON(cnt % 2 != 0);
+
+        cnt = cnt >> 1;
+        while (cnt > 0) {
+                mci_writew(host, DATA, *pdata++);
+                cnt--;
+        }
+}
+
+static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
+{
+        u16 *pdata = (u16 *)buf;
+
+        WARN_ON(cnt % 2 != 0);
+
+        cnt = cnt >> 1;
+        while (cnt > 0) {
+                *pdata++ = mci_readw(host, DATA);
+                cnt--;
+        }
+}
+
+static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
+{
+        u32 *pdata = (u32 *)buf;
+
+        WARN_ON(cnt % 4 != 0);
+        WARN_ON((unsigned long)pdata & 0x3);
+
+        cnt = cnt >> 2;
+        while (cnt > 0) {
+                mci_writel(host, DATA, *pdata++);
+                cnt--;
+        }
+}
+
+static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
+{
+        u32 *pdata = (u32 *)buf;
+
+        WARN_ON(cnt % 4 != 0);
+        WARN_ON((unsigned long)pdata & 0x3);
+
+        cnt = cnt >> 2;
+        while (cnt > 0) {
+                *pdata++ = mci_readl(host, DATA);
+                cnt--;
+        }
+}
+
+static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
+{
+        u64 *pdata = (u64 *)buf;
+
+        WARN_ON(cnt % 8 != 0);
+
+        cnt = cnt >> 3;
+        while (cnt > 0) {
+                mci_writeq(host, DATA, *pdata++);
+                cnt--;
+        }
+}
+
+static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
+{
+        u64 *pdata = (u64 *)buf;
+
+        WARN_ON(cnt % 8 != 0);
+
+        cnt = cnt >> 3;
+        while (cnt > 0) {
+                *pdata++ = mci_readq(host, DATA);
+                cnt--;
+        }
+}
+
+static void dw_mci_read_data_pio(struct dw_mci *host)
+{
+        struct scatterlist *sg = host->sg;
+        void *buf = sg_virt(sg);
+        unsigned int offset = host->pio_offset;
+        struct mmc_data *data = host->data;
+        int shift = host->data_shift;
+        u32 status;
+        unsigned int nbytes = 0, len, old_len, count = 0;
+
+        do {
+                len = SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift;
+                if (count == 0)
+                        old_len = len;
+
+                if (offset + len <= sg->length) {
+                        host->pull_data(host, (void *)(buf + offset), len);
+
+                        offset += len;
+                        nbytes += len;
+
+                        if (offset == sg->length) {
+                                flush_dcache_page(sg_page(sg));
+                                host->sg = sg = sg_next(sg);
+                                if (!sg)
+                                        goto done;
+
+                                offset = 0;
+                                buf = sg_virt(sg);
+                        }
+                } else {
+                        unsigned int remaining = sg->length - offset;
+                        host->pull_data(host, (void *)(buf + offset),
+                                        remaining);
+                        nbytes += remaining;
+
+                        flush_dcache_page(sg_page(sg));
+                        host->sg = sg = sg_next(sg);
+                        if (!sg)
+                                goto done;
+
+                        offset = len - remaining;
+                        buf = sg_virt(sg);
+                        host->pull_data(host, buf, offset);
+                        nbytes += offset;
+                }
+
+                status = mci_readl(host, MINTSTS);
+                mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
+                if (status & DW_MCI_DATA_ERROR_FLAGS) {
+                        host->data_status = status;
+                        data->bytes_xfered += nbytes;
+                        smp_wmb();
+
+                        set_bit(EVENT_DATA_ERROR, &host->pending_events);
+
+                        tasklet_schedule(&host->tasklet);
+                        return;
+                }
+                count++;
+        } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
+        len = SDMMC_GET_FCNT(mci_readl(host, STATUS));
+        host->pio_offset = offset;
+        data->bytes_xfered += nbytes;
+        return;
+
+done:
+        data->bytes_xfered += nbytes;
+        smp_wmb();
+        set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
+}
+
+static void dw_mci_write_data_pio(struct dw_mci *host)
+{
+        struct scatterlist *sg = host->sg;
+        void *buf = sg_virt(sg);
+        unsigned int offset = host->pio_offset;
+        struct mmc_data *data = host->data;
+        int shift = host->data_shift;
+        u32 status;
+        unsigned int nbytes = 0, len;
+
+        do {
+                len = SDMMC_FIFO_SZ -
+                        (SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift);
+                if (offset + len <= sg->length) {
+                        host->push_data(host, (void *)(buf + offset), len);
+
+                        offset += len;
+                        nbytes += len;
+                        if (offset == sg->length) {
+                                host->sg = sg = sg_next(sg);
+                                if (!sg)
+                                        goto done;
+
+                                offset = 0;
+                                buf = sg_virt(sg);
+                        }
+                } else {
+                        unsigned int remaining = sg->length - offset;
+
+                        host->push_data(host, (void *)(buf + offset),
+                                        remaining);
+                        nbytes += remaining;
+
+                        host->sg = sg = sg_next(sg);
+                        if (!sg)
+                                goto done;
+
+                        offset = len - remaining;
+                        buf = sg_virt(sg);
+                        host->push_data(host, (void *)buf, offset);
+                        nbytes += offset;
+                }
+
+                status = mci_readl(host, MINTSTS);
+                mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
+                if (status & DW_MCI_DATA_ERROR_FLAGS) {
+                        host->data_status = status;
+                        data->bytes_xfered += nbytes;
+
+                        smp_wmb();
+
+                        set_bit(EVENT_DATA_ERROR, &host->pending_events);
+
+                        tasklet_schedule(&host->tasklet);
+                        return;
+                }
+        } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
+
+        host->pio_offset = offset;
+        data->bytes_xfered += nbytes;
+
+        return;
+
+done:
+        data->bytes_xfered += nbytes;
+        smp_wmb();
+        set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
+}
+
+static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
+{
+        if (!host->cmd_status)
+                host->cmd_status = status;
+
+        smp_wmb();
+
+        set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
+        tasklet_schedule(&host->tasklet);
+}
+
+static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
+{
+        struct dw_mci *host = dev_id;
+        u32 status, pending;
+        unsigned int pass_count = 0;
+
+        do {
+                status = mci_readl(host, RINTSTS);
+                pending = mci_readl(host, MINTSTS); /* read-only mask reg */
+
+                /*
+                 * DTO fix - version 2.10a and below, and only if internal DMA
+                 * is configured.
+                 */
+                if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
+                        if (!pending &&
+                            ((mci_readl(host, STATUS) >> 17) & 0x1fff))
+                                pending |= SDMMC_INT_DATA_OVER;
+                }
+
+                if (!pending)
+                        break;
+
+                if (pending & DW_MCI_CMD_ERROR_FLAGS) {
+                        mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
+                        host->cmd_status = status;
+                        smp_wmb();
+                        set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
+                        tasklet_schedule(&host->tasklet);
+                }
+
+                if (pending & DW_MCI_DATA_ERROR_FLAGS) {
+                        /* if there is an error report DATA_ERROR */
+                        mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
+                        host->data_status = status;
+                        smp_wmb();
+                        set_bit(EVENT_DATA_ERROR, &host->pending_events);
+                        tasklet_schedule(&host->tasklet);
+                }
+
+                if (pending & SDMMC_INT_DATA_OVER) {
+                        mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
+                        if (!host->data_status)
+                                host->data_status = status;
+                        smp_wmb();
+                        if (host->dir_status == DW_MCI_RECV_STATUS) {
+                                if (host->sg != NULL)
+                                        dw_mci_read_data_pio(host);
+                        }
+                        set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
+                        tasklet_schedule(&host->tasklet);
+                }
+
+                if (pending & SDMMC_INT_RXDR) {
+                        mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
+                        if (host->sg)
+                                dw_mci_read_data_pio(host);
+                }
+
+                if (pending & SDMMC_INT_TXDR) {
+                        mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
+                        if (host->sg)
+                                dw_mci_write_data_pio(host);
+                }
+
+                if (pending & SDMMC_INT_CMD_DONE) {
+                        mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
+                        dw_mci_cmd_interrupt(host, status);
+                }
+
+                if (pending & SDMMC_INT_CD) {
+                        mci_writel(host, RINTSTS, SDMMC_INT_CD);
+                        tasklet_schedule(&host->card_tasklet);
+                }
+
+        } while (pass_count++ < 5);
+
+#ifdef CONFIG_MMC_DW_IDMAC
+        /* Handle DMA interrupts */
+        pending = mci_readl(host, IDSTS);
+        if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
+                mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
+                mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
+                set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
+                host->dma_ops->complete(host);
+        }
+#endif
+
+        return IRQ_HANDLED;
+}
+
+static void dw_mci_tasklet_card(unsigned long data)
+{
+        struct dw_mci *host = (struct dw_mci *)data;
+        int i;
+
+        for (i = 0; i < host->num_slots; i++) {
+                struct dw_mci_slot *slot = host->slot[i];
+                struct mmc_host *mmc = slot->mmc;
+                struct mmc_request *mrq;
+                int present;
+                u32 ctrl;
+
+                present = dw_mci_get_cd(mmc);
+                while (present != slot->last_detect_state) {
+                        spin_lock(&host->lock);
+
+                        dev_dbg(&slot->mmc->class_dev, "card %s\n",
+                                present ? "inserted" : "removed");
+
+                        /* Card change detected */
+                        slot->last_detect_state = present;
+
+                        /* Power up slot */
+                        if (present != 0) {
+                                if (host->pdata->setpower)
+                                        host->pdata->setpower(slot->id,
+                                                              mmc->ocr_avail);
+
+                                set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
+                        }
+
+                        /* Clean up queue if present */
+                        mrq = slot->mrq;
+                        if (mrq) {
+                                if (mrq == host->mrq) {
+                                        host->data = NULL;
+                                        host->cmd = NULL;
+
+                                        switch (host->state) {
+                                        case STATE_IDLE:
+                                                break;
+                                        case STATE_SENDING_CMD:
+                                                mrq->cmd->error = -ENOMEDIUM;
+                                                if (!mrq->data)
+                                                        break;
+                                                /* fall through */
+                                        case STATE_SENDING_DATA:
+                                                mrq->data->error = -ENOMEDIUM;
+                                                dw_mci_stop_dma(host);
+                                                break;
+                                        case STATE_DATA_BUSY:
+                                        case STATE_DATA_ERROR:
+                                                if (mrq->data->error == -EINPROGRESS)
+                                                        mrq->data->error = -ENOMEDIUM;
+                                                if (!mrq->stop)
+                                                        break;
+                                                /* fall through */
+                                        case STATE_SENDING_STOP:
+                                                mrq->stop->error = -ENOMEDIUM;
+                                                break;
+                                        }
+
+                                        dw_mci_request_end(host, mrq);
+                                } else {
+                                        list_del(&slot->queue_node);
+                                        mrq->cmd->error = -ENOMEDIUM;
+                                        if (mrq->data)
+                                                mrq->data->error = -ENOMEDIUM;
+                                        if (mrq->stop)
+                                                mrq->stop->error = -ENOMEDIUM;
+
+                                        spin_unlock(&host->lock);
+                                        mmc_request_done(slot->mmc, mrq);
+                                        spin_lock(&host->lock);
+                                }
+                        }
+
+                        /* Power down slot */
+                        if (present == 0) {
+                                if (host->pdata->setpower)
+                                        host->pdata->setpower(slot->id, 0);
+                                clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
+
+                                /*
+                                 * Clear down the FIFO - doing so generates a
+                                 * block interrupt, hence setting the
+                                 * scatter-gather pointer to NULL.
+                                 */
+                                host->sg = NULL;
+
+                                ctrl = mci_readl(host, CTRL);
+                                ctrl |= SDMMC_CTRL_FIFO_RESET;
+                                mci_writel(host, CTRL, ctrl);
+
+#ifdef CONFIG_MMC_DW_IDMAC
+                                ctrl = mci_readl(host, BMOD);
+                                ctrl |= 0x01; /* Software reset of DMA */
+                                mci_writel(host, BMOD, ctrl);
+#endif
+
+                        }
+
+                        spin_unlock(&host->lock);
+                        present = dw_mci_get_cd(mmc);
+                }
+
+                mmc_detect_change(slot->mmc,
+                        msecs_to_jiffies(host->pdata->detect_delay_ms));
+        }
+}
+
+static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)
+{
+        struct mmc_host *mmc;
+        struct dw_mci_slot *slot;
+
+        mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->pdev->dev);
+        if (!mmc)
+                return -ENOMEM;
+
+        slot = mmc_priv(mmc);
+        slot->id = id;
+        slot->mmc = mmc;
+        slot->host = host;
+
+        mmc->ops = &dw_mci_ops;
+        mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
+        mmc->f_max = host->bus_hz;
+
+        if (host->pdata->get_ocr)
+                mmc->ocr_avail = host->pdata->get_ocr(id);
+        else
+                mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+        /*
+         * Start with slot power disabled, it will be enabled when a card
+         * is detected.
+         */
+        if (host->pdata->setpower)
+                host->pdata->setpower(id, 0);
+
+        mmc->caps = 0;
+        if (host->pdata->get_bus_wd)
+                if (host->pdata->get_bus_wd(slot->id) >= 4)
+                        mmc->caps |= MMC_CAP_4_BIT_DATA;
+
+        if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
+                mmc->caps |= MMC_CAP_SD_HIGHSPEED;
+
+#ifdef CONFIG_MMC_DW_IDMAC
+        mmc->max_segs = host->ring_size;
+        mmc->max_blk_size = 65536;
+        mmc->max_blk_count = host->ring_size;
+        mmc->max_seg_size = 0x1000;
+        mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
+#else
+        if (host->pdata->blk_settings) {
+                mmc->max_segs = host->pdata->blk_settings->max_segs;
+                mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
+                mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
+                mmc->max_req_size = host->pdata->blk_settings->max_req_size;
+                mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
+        } else {
+                /* Useful defaults if platform data is unset. */
+                mmc->max_segs = 64;
+                mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
+                mmc->max_blk_count = 512;
+                mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
+                mmc->max_seg_size = mmc->max_req_size;
+        }
+#endif /* CONFIG_MMC_DW_IDMAC */
+
+        if (dw_mci_get_cd(mmc))
+                set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
+        else
+                clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
+
+        host->slot[id] = slot;
+        mmc_add_host(mmc);
+
+#if defined(CONFIG_DEBUG_FS)
+        dw_mci_init_debugfs(slot);
+#endif
+
+        /* Card initially undetected */
+        slot->last_detect_state = 0;
+
+        return 0;
+}
+
+static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
+{
+        /* Shutdown detect IRQ */
+        if (slot->host->pdata->exit)
+                slot->host->pdata->exit(id);
+
+        /* Debugfs stuff is cleaned up by mmc core */
+        mmc_remove_host(slot->mmc);
+        slot->host->slot[id] = NULL;
+        mmc_free_host(slot->mmc);
+}
+
+static void dw_mci_init_dma(struct dw_mci *host)
+{
+        /* Alloc memory for sg translation */
+        host->sg_cpu = dma_alloc_coherent(&host->pdev->dev, PAGE_SIZE,
+                                          &host->sg_dma, GFP_KERNEL);
+        if (!host->sg_cpu) {
+                dev_err(&host->pdev->dev, "%s: could not alloc DMA memory\n",
+                        __func__);
+                goto no_dma;
+        }
+
+        /* Determine which DMA interface to use */
+#ifdef CONFIG_MMC_DW_IDMAC
+        host->dma_ops = &dw_mci_idmac_ops;
+        dev_info(&host->pdev->dev, "Using internal DMA controller.\n");
+#endif
+
+        if (!host->dma_ops)
+                goto no_dma;
+
+        if (host->dma_ops->init) {
+                if (host->dma_ops->init(host)) {
+                        dev_err(&host->pdev->dev, "%s: Unable to initialize "
+                                "DMA Controller.\n", __func__);
+                        goto no_dma;
+                }
+        } else {
+                dev_err(&host->pdev->dev, "DMA initialization not found.\n");
+                goto no_dma;
+        }
+
+        host->use_dma = 1;
+        return;
+
+no_dma:
+        dev_info(&host->pdev->dev, "Using PIO mode.\n");
+        host->use_dma = 0;
+        return;
+}
+
+static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
+{
+        unsigned long timeout = jiffies + msecs_to_jiffies(500);
+        unsigned int ctrl;
+
+        mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
+                                SDMMC_CTRL_DMA_RESET));
+
+        /* wait till resets clear */
+        do {
+                ctrl = mci_readl(host, CTRL);
+                if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
+                              SDMMC_CTRL_DMA_RESET)))
+                        return true;
+        } while (time_before(jiffies, timeout));
+
+        dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
+
+        return false;
+}
+
+static int dw_mci_probe(struct platform_device *pdev)
+{
+        struct dw_mci *host;
+        struct resource *regs;
+        struct dw_mci_board *pdata;
+        int irq, ret, i, width;
+        u32 fifo_size;
+
+        regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!regs)
+                return -ENXIO;
+
+        irq = platform_get_irq(pdev, 0);
+        if (irq < 0)
+                return irq;
+
+        host = kzalloc(sizeof(struct dw_mci), GFP_KERNEL);
+        if (!host)
+                return -ENOMEM;
+
+        host->pdev = pdev;
+        host->pdata = pdata = pdev->dev.platform_data;
+        if (!pdata || !pdata->init) {
+                dev_err(&pdev->dev,
+                        "Platform data must supply init function\n");
+                ret = -ENODEV;
+                goto err_freehost;
+        }
+
+        if (!pdata->select_slot && pdata->num_slots > 1) {
+                dev_err(&pdev->dev,
+                        "Platform data must supply select_slot function\n");
+                ret = -ENODEV;
+                goto err_freehost;
+        }
+
+        if (!pdata->bus_hz) {
+                dev_err(&pdev->dev,
+                        "Platform data must supply bus speed\n");
+                ret = -ENODEV;
+                goto err_freehost;
+        }
+
+        host->bus_hz = pdata->bus_hz;
+        host->quirks = pdata->quirks;
+
+        spin_lock_init(&host->lock);
+        INIT_LIST_HEAD(&host->queue);
+
+        ret = -ENOMEM;
+        host->regs = ioremap(regs->start, regs->end - regs->start + 1);
+        if (!host->regs)
+                goto err_freehost;
+
+        host->dma_ops = pdata->dma_ops;
+        dw_mci_init_dma(host);
+
+        /*
+         * Get the host data width - this assumes that HCON has been set with
+         * the correct values.
+         */
+        i = (mci_readl(host, HCON) >> 7) & 0x7;
+        if (!i) {
+                host->push_data = dw_mci_push_data16;
+                host->pull_data = dw_mci_pull_data16;
+                width = 16;
+                host->data_shift = 1;
+        } else if (i == 2) {
+                host->push_data = dw_mci_push_data64;
+                host->pull_data = dw_mci_pull_data64;
+                width = 64;
+                host->data_shift = 3;
+        } else {
+                /* Check for a reserved value, and warn if it is */
+                WARN((i != 1),
+                     "HCON reports a reserved host data width!\n"
+                     "Defaulting to 32-bit access.\n");
+                host->push_data = dw_mci_push_data32;
+                host->pull_data = dw_mci_pull_data32;
+                width = 32;
+                host->data_shift = 2;
+        }
+
+        /* Reset all blocks */
+        if (!mci_wait_reset(&pdev->dev, host)) {
+                ret = -ENODEV;
+                goto err_dmaunmap;
+        }
+
+        /* Clear the interrupts for the host controller */
+        mci_writel(host, RINTSTS, 0xFFFFFFFF);
+        mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
+
+        /* Put in max timeout */
+        mci_writel(host, TMOUT, 0xFFFFFFFF);
+
+        /*
+         * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
+         *                          Tx Mark = fifo_size / 2 DMA Size = 8
+         */
+        fifo_size = mci_readl(host, FIFOTH);
+        fifo_size = (fifo_size >> 16) & 0x7ff;
+        mci_writel(host, FIFOTH, ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
+                                  ((fifo_size/2) << 0)));
+
+        /* disable clock to CIU */
+        mci_writel(host, CLKENA, 0);
+        mci_writel(host, CLKSRC, 0);
+
+        tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
+        tasklet_init(&host->card_tasklet,
+                     dw_mci_tasklet_card, (unsigned long)host);
+
+        ret = request_irq(irq, dw_mci_interrupt, 0, "dw-mci", host);
+        if (ret)
+                goto err_dmaunmap;
+
+        platform_set_drvdata(pdev, host);
+
+        if (host->pdata->num_slots)
+                host->num_slots = host->pdata->num_slots;
+        else
+                host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
+
+        /* We need at least one slot to succeed */
+        for (i = 0; i < host->num_slots; i++) {
+                ret = dw_mci_init_slot(host, i);
+                if (ret) {
+                        ret = -ENODEV;
+                        goto err_init_slot;
+                }
+        }
+
+        /*
+         * Enable interrupts for command done, data over, data empty, card det,
+         * receive ready and error such as transmit, receive timeout, crc error
+         */
+        mci_writel(host, RINTSTS, 0xFFFFFFFF);
+        mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
+                   SDMMC_INT_TXDR | SDMMC_INT_RXDR |
+                   DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
+        mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
+
+        dev_info(&pdev->dev, "DW MMC controller at irq %d, "
+                 "%d bit host data width\n", irq, width);
+        if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
+                dev_info(&pdev->dev, "Internal DMAC interrupt fix enabled.\n");
+
+        return 0;
+
+err_init_slot:
+        /* De-init any initialized slots */
+        while (i > 0) {
+                if (host->slot[i])
+                        dw_mci_cleanup_slot(host->slot[i], i);
+                i--;
+        }
+        free_irq(irq, host);
+
+err_dmaunmap:
+        if (host->use_dma && host->dma_ops->exit)
+                host->dma_ops->exit(host);
+        dma_free_coherent(&host->pdev->dev, PAGE_SIZE,
+                          host->sg_cpu, host->sg_dma);
+        iounmap(host->regs);
+
+err_freehost:
+        kfree(host);
+        return ret;
+}
+
+static int __exit dw_mci_remove(struct platform_device *pdev)
+{
+        struct dw_mci *host = platform_get_drvdata(pdev);
+        int i;
+
+        mci_writel(host, RINTSTS, 0xFFFFFFFF);
+        mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
+
+        platform_set_drvdata(pdev, NULL);
+
+        for (i = 0; i < host->num_slots; i++) {
+                dev_dbg(&pdev->dev, "remove slot %d\n", i);
+                if (host->slot[i])
+                        dw_mci_cleanup_slot(host->slot[i], i);
+        }
+
+        /* disable clock to CIU */
+        mci_writel(host, CLKENA, 0);
+        mci_writel(host, CLKSRC, 0);
+
+        free_irq(platform_get_irq(pdev, 0), host);
+        dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
+
+        if (host->use_dma && host->dma_ops->exit)
+                host->dma_ops->exit(host);
+
+        iounmap(host->regs);
+
+        kfree(host);
+        return 0;
+}
+
+#ifdef CONFIG_PM
+/*
+ * TODO: we should probably disable the clock to the card in the suspend path.
+ */
+static int dw_mci_suspend(struct platform_device *pdev, pm_message_t mesg)
+{
+        int i, ret;
+        struct dw_mci *host = platform_get_drvdata(pdev);
+
+        for (i = 0; i < host->num_slots; i++) {
+                struct dw_mci_slot *slot = host->slot[i];
+                if (!slot)
+                        continue;
+                ret = mmc_suspend_host(slot->mmc);
+                if (ret < 0) {
+                        while (--i >= 0) {
+                                slot = host->slot[i];
+                                if (slot)
+                                        mmc_resume_host(host->slot[i]->mmc);
+                        }
+                        return ret;
+                }
+        }
+
+        return 0;
+}
+
+static int dw_mci_resume(struct platform_device *pdev)
+{
+        int i, ret;
+        struct dw_mci *host = platform_get_drvdata(pdev);
+
+        for (i = 0; i < host->num_slots; i++) {
+                struct dw_mci_slot *slot = host->slot[i];
+                if (!slot)
+                        continue;
+                ret = mmc_resume_host(host->slot[i]->mmc);
+                if (ret < 0)
+                        return ret;
+        }
+
+        return 0;
+}
+#else
+#define dw_mci_suspend  NULL
+#define dw_mci_resume   NULL
+#endif /* CONFIG_PM */
+
+static struct platform_driver dw_mci_driver = {
+        .remove         = __exit_p(dw_mci_remove),
+        .suspend        = dw_mci_suspend,
+        .resume         = dw_mci_resume,
+        .driver         = {
+                .name           = "dw_mmc",
+        },
+};
+
+static int __init dw_mci_init(void)
+{
+        return platform_driver_probe(&dw_mci_driver, dw_mci_probe);
+}
+
+static void __exit dw_mci_exit(void)
+{
+        platform_driver_unregister(&dw_mci_driver);
+}
+
+module_init(dw_mci_init);
+module_exit(dw_mci_exit);
+
+MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
+MODULE_AUTHOR("NXP Semiconductor VietNam");
+MODULE_AUTHOR("Imagination Technologies Ltd");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
new file mode 100644
index 000000000000..5dd55a75233d
--- /dev/null
+++ b/drivers/mmc/host/dw_mmc.h
@@ -0,0 +1,168 @@
+/*
+ * Synopsys DesignWare Multimedia Card Interface driver
+ *  (Based on NXP driver for lpc 31xx)
+ *
+ * Copyright (C) 2009 NXP Semiconductors
+ * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _DW_MMC_H_
+#define _DW_MMC_H_
+
+#define SDMMC_CTRL              0x000
+#define SDMMC_PWREN             0x004
+#define SDMMC_CLKDIV            0x008
+#define SDMMC_CLKSRC            0x00c
+#define SDMMC_CLKENA            0x010
+#define SDMMC_TMOUT             0x014
+#define SDMMC_CTYPE             0x018
+#define SDMMC_BLKSIZ            0x01c
+#define SDMMC_BYTCNT            0x020
+#define SDMMC_INTMASK           0x024
+#define SDMMC_CMDARG            0x028
+#define SDMMC_CMD               0x02c
+#define SDMMC_RESP0             0x030
+#define SDMMC_RESP1             0x034
+#define SDMMC_RESP2             0x038
+#define SDMMC_RESP3             0x03c
+#define SDMMC_MINTSTS           0x040
+#define SDMMC_RINTSTS           0x044
+#define SDMMC_STATUS            0x048
+#define SDMMC_FIFOTH            0x04c
+#define SDMMC_CDETECT           0x050
+#define SDMMC_WRTPRT            0x054
+#define SDMMC_GPIO              0x058
+#define SDMMC_TCBCNT            0x05c
+#define SDMMC_TBBCNT            0x060
+#define SDMMC_DEBNCE            0x064
+#define SDMMC_USRID             0x068
+#define SDMMC_VERID             0x06c
+#define SDMMC_HCON              0x070
+#define SDMMC_BMOD              0x080
+#define SDMMC_PLDMND            0x084
+#define SDMMC_DBADDR            0x088
+#define SDMMC_IDSTS             0x08c
+#define SDMMC_IDINTEN           0x090
+#define SDMMC_DSCADDR           0x094
+#define SDMMC_BUFADDR           0x098
+#define SDMMC_DATA              0x100
+#define SDMMC_DATA_ADR          0x100
+
+/* shift bit field */
+#define _SBF(f, v)              ((v) << (f))
+
+/* Control register defines */
+#define SDMMC_CTRL_USE_IDMAC            BIT(25)
+#define SDMMC_CTRL_CEATA_INT_EN         BIT(11)
+#define SDMMC_CTRL_SEND_AS_CCSD         BIT(10)
+#define SDMMC_CTRL_SEND_CCSD            BIT(9)
+#define SDMMC_CTRL_ABRT_READ_DATA       BIT(8)
+#define SDMMC_CTRL_SEND_IRQ_RESP        BIT(7)
+#define SDMMC_CTRL_READ_WAIT            BIT(6)
+#define SDMMC_CTRL_DMA_ENABLE           BIT(5)
+#define SDMMC_CTRL_INT_ENABLE           BIT(4)
+#define SDMMC_CTRL_DMA_RESET            BIT(2)
+#define SDMMC_CTRL_FIFO_RESET           BIT(1)
+#define SDMMC_CTRL_RESET                BIT(0)
+/* Clock Enable register defines */
+#define SDMMC_CLKEN_LOW_PWR             BIT(16)
+#define SDMMC_CLKEN_ENABLE              BIT(0)
+/* time-out register defines */
+#define SDMMC_TMOUT_DATA(n)             _SBF(8, (n))
+#define SDMMC_TMOUT_DATA_MSK            0xFFFFFF00
+#define SDMMC_TMOUT_RESP(n)             ((n) & 0xFF)
+#define SDMMC_TMOUT_RESP_MSK            0xFF
+/* card-type register defines */
+#define SDMMC_CTYPE_8BIT                BIT(16)
+#define SDMMC_CTYPE_4BIT                BIT(0)
+#define SDMMC_CTYPE_1BIT                0
+/* Interrupt status & mask register defines */
+#define SDMMC_INT_SDIO                  BIT(16)
+#define SDMMC_INT_EBE                   BIT(15)
+#define SDMMC_INT_ACD                   BIT(14)
+#define SDMMC_INT_SBE                   BIT(13)
+#define SDMMC_INT_HLE                   BIT(12)
+#define SDMMC_INT_FRUN                  BIT(11)
+#define SDMMC_INT_HTO                   BIT(10)
+#define SDMMC_INT_DTO                   BIT(9)
+#define SDMMC_INT_RTO                   BIT(8)
+#define SDMMC_INT_DCRC                  BIT(7)
+#define SDMMC_INT_RCRC                  BIT(6)
+#define SDMMC_INT_RXDR                  BIT(5)
+#define SDMMC_INT_TXDR                  BIT(4)
+#define SDMMC_INT_DATA_OVER             BIT(3)
+#define SDMMC_INT_CMD_DONE              BIT(2)
+#define SDMMC_INT_RESP_ERR              BIT(1)
+#define SDMMC_INT_CD                    BIT(0)
+#define SDMMC_INT_ERROR                 0xbfc2
+/* Command register defines */
+#define SDMMC_CMD_START                 BIT(31)
+#define SDMMC_CMD_CCS_EXP               BIT(23)
+#define SDMMC_CMD_CEATA_RD              BIT(22)
+#define SDMMC_CMD_UPD_CLK               BIT(21)
+#define SDMMC_CMD_INIT                  BIT(15)
+#define SDMMC_CMD_STOP                  BIT(14)
+#define SDMMC_CMD_PRV_DAT_WAIT          BIT(13)
+#define SDMMC_CMD_SEND_STOP             BIT(12)
+#define SDMMC_CMD_STRM_MODE             BIT(11)
+#define SDMMC_CMD_DAT_WR                BIT(10)
+#define SDMMC_CMD_DAT_EXP               BIT(9)
+#define SDMMC_CMD_RESP_CRC              BIT(8)
+#define SDMMC_CMD_RESP_LONG             BIT(7)
+#define SDMMC_CMD_RESP_EXP              BIT(6)
+#define SDMMC_CMD_INDX(n)               ((n) & 0x1F)
+/* Status register defines */
+#define SDMMC_GET_FCNT(x)               (((x)>>17) & 0x1FF)
+#define SDMMC_FIFO_SZ                   32
+/* Internal DMAC interrupt defines */
+#define SDMMC_IDMAC_INT_AI              BIT(9)
+#define SDMMC_IDMAC_INT_NI              BIT(8)
+#define SDMMC_IDMAC_INT_CES             BIT(5)
+#define SDMMC_IDMAC_INT_DU              BIT(4)
+#define SDMMC_IDMAC_INT_FBE             BIT(2)
+#define SDMMC_IDMAC_INT_RI              BIT(1)
+#define SDMMC_IDMAC_INT_TI              BIT(0)
+/* Internal DMAC bus mode bits */
+#define SDMMC_IDMAC_ENABLE              BIT(7)
+#define SDMMC_IDMAC_FB                  BIT(1)
+#define SDMMC_IDMAC_SWRESET             BIT(0)
+
+/* Register access macros */
+#define mci_readl(dev, reg)                     \
+        __raw_readl(dev->regs + SDMMC_##reg)
+#define mci_writel(dev, reg, value)                     \
+        __raw_writel((value), dev->regs + SDMMC_##reg)
+
+/* 16-bit FIFO access macros */
+#define mci_readw(dev, reg)                     \
+        __raw_readw(dev->regs + SDMMC_##reg)
+#define mci_writew(dev, reg, value)                     \
+        __raw_writew((value), dev->regs + SDMMC_##reg)
+
+/* 64-bit FIFO access macros */
+#ifdef readq
+#define mci_readq(dev, reg)                     \
+        __raw_readq(dev->regs + SDMMC_##reg)
+#define mci_writeq(dev, reg, value)                     \
+        __raw_writeq((value), dev->regs + SDMMC_##reg)
+#else
+/*
+ * Dummy readq implementation for architectures that don't define it.
+ *
+ * We would assume that none of these architectures would configure
+ * the IP block with a 64bit FIFO width, so this code will never be
+ * executed on those machines. Defining these macros here keeps the
+ * rest of the code free from ifdefs.
+ */
+#define mci_readq(dev, reg)                     \
+        (*(volatile u64 __force *)(dev->regs + SDMMC_##reg))
+#define mci_writeq(dev, reg, value)                     \
+        (*(volatile u64 __force *)(dev->regs + SDMMC_##reg) = value)
+#endif
+
+#endif /* _DW_MMC_H_ */
diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
index bdd2cbb87cba..4428594261c5 100644
--- a/drivers/mmc/host/mxcmmc.c
+++ b/drivers/mmc/host/mxcmmc.c
@@ -31,6 +31,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
 
 #include <asm/dma.h>
 #include <asm/irq.h>
@@ -141,10 +142,49 @@ struct mxcmci_host {
 
         struct work_struct      datawork;
         spinlock_t              lock;
+
+        struct regulator        *vcc;
 };
 
 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
 
+static inline void mxcmci_init_ocr(struct mxcmci_host *host)
+{
+        host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc");
+
+        if (IS_ERR(host->vcc)) {
+                host->vcc = NULL;
+        } else {
+                host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc);
+                if (host->pdata && host->pdata->ocr_avail)
+                        dev_warn(mmc_dev(host->mmc),
+                                "pdata->ocr_avail will not be used\n");
+        }
+
+        if (host->vcc == NULL) {
+                /* fall-back to platform data */
+                if (host->pdata && host->pdata->ocr_avail)
+                        host->mmc->ocr_avail = host->pdata->ocr_avail;
+                else
+                        host->mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+        }
+}
+
+static inline void mxcmci_set_power(struct mxcmci_host *host,
+                                    unsigned char power_mode,
+                                    unsigned int vdd)
+{
+        if (host->vcc) {
+                if (power_mode == MMC_POWER_UP)
+                        mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
+                else if (power_mode == MMC_POWER_OFF)
+                        mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
+        }
+
+        if (host->pdata && host->pdata->setpower)
+                host->pdata->setpower(mmc_dev(host->mmc), vdd);
+}
+
 static inline int mxcmci_use_dma(struct mxcmci_host *host)
 {
         return host->do_dma;
@@ -680,9 +720,9 @@ static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
                 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
 
         if (host->power_mode != ios->power_mode) {
-                if (host->pdata && host->pdata->setpower)
-                        host->pdata->setpower(mmc_dev(mmc), ios->vdd);
+                mxcmci_set_power(host, ios->power_mode, ios->vdd);
                 host->power_mode = ios->power_mode;
+
                 if (ios->power_mode == MMC_POWER_ON)
                         host->cmdat |= CMD_DAT_CONT_INIT;
         }
@@ -807,10 +847,7 @@ static int mxcmci_probe(struct platform_device *pdev)
         host->pdata = pdev->dev.platform_data;
         spin_lock_init(&host->lock);
 
-        if (host->pdata && host->pdata->ocr_avail)
-                mmc->ocr_avail = host->pdata->ocr_avail;
-        else
-                mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+        mxcmci_init_ocr(host);
 
         if (host->pdata && host->pdata->dat3_card_detect)
                 host->default_irq_mask =
@@ -915,6 +952,9 @@ static int mxcmci_remove(struct platform_device *pdev)
 
         mmc_remove_host(mmc);
 
+        if (host->vcc)
+                regulator_put(host->vcc);
+
         if (host->pdata && host->pdata->exit)
                 host->pdata->exit(&pdev->dev, mmc);
 
@@ -927,7 +967,6 @@ static int mxcmci_remove(struct platform_device *pdev)
         clk_put(host->clk);
 
         release_mem_region(host->res->start, resource_size(host->res));
-        release_resource(host->res);
 
         mmc_free_host(mmc);
 
diff --git a/drivers/mmc/host/sdhci-dove.c b/drivers/mmc/host/sdhci-dove.c
new file mode 100644
index 000000000000..2aeef4ffed8c
--- /dev/null
+++ b/drivers/mmc/host/sdhci-dove.c
@@ -0,0 +1,70 @@
+/*
+ * sdhci-dove.c Support for SDHCI on Marvell's Dove SoC
+ *
+ * Author: Saeed Bishara <saeed@marvell.com>
+ *         Mike Rapoport <mike@compulab.co.il>
+ * Based on sdhci-cns3xxx.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/io.h>
+#include <linux/mmc/host.h>
+
+#include "sdhci.h"
+#include "sdhci-pltfm.h"
+
+static u16 sdhci_dove_readw(struct sdhci_host *host, int reg)
+{
+        u16 ret;
+
+        switch (reg) {
+        case SDHCI_HOST_VERSION:
+        case SDHCI_SLOT_INT_STATUS:
+                /* those registers don't exist */
+                return 0;
+        default:
+                ret = readw(host->ioaddr + reg);
+        }
+        return ret;
+}
+
+static u32 sdhci_dove_readl(struct sdhci_host *host, int reg)
+{
+        u32 ret;
+
+        switch (reg) {
+        case SDHCI_CAPABILITIES:
+                ret = readl(host->ioaddr + reg);
+                /* Mask the support for 3.0V */
+                ret &= ~SDHCI_CAN_VDD_300;
+                break;
+        default:
+                ret = readl(host->ioaddr + reg);
+        }
+        return ret;
+}
+
+static struct sdhci_ops sdhci_dove_ops = {
+        .read_w = sdhci_dove_readw,
+        .read_l = sdhci_dove_readl,
+};
+
+struct sdhci_pltfm_data sdhci_dove_pdata = {
+        .ops    = &sdhci_dove_ops,
+        .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
+                  SDHCI_QUIRK_NO_BUSY_IRQ |
+                  SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
+                  SDHCI_QUIRK_FORCE_DMA,
+};
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
index 3d9c2460d437..0dc905b20eee 100644
--- a/drivers/mmc/host/sdhci-pci.c
+++ b/drivers/mmc/host/sdhci-pci.c
@@ -176,6 +176,74 @@ static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc_sdio = {
         .quirks         = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 };
 
+/* O2Micro extra registers */
+#define O2_SD_LOCK_WP           0xD3
+#define O2_SD_MULTI_VCC3V       0xEE
+#define O2_SD_CLKREQ            0xEC
+#define O2_SD_CAPS              0xE0
+#define O2_SD_ADMA1             0xE2
+#define O2_SD_ADMA2             0xE7
+#define O2_SD_INF_MOD           0xF1
+
+static int o2_probe(struct sdhci_pci_chip *chip)
+{
+        int ret;
+        u8 scratch;
+
+        switch (chip->pdev->device) {
+        case PCI_DEVICE_ID_O2_8220:
+        case PCI_DEVICE_ID_O2_8221:
+        case PCI_DEVICE_ID_O2_8320:
+        case PCI_DEVICE_ID_O2_8321:
+                /* This extra setup is required due to broken ADMA. */
+                ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
+                if (ret)
+                        return ret;
+                scratch &= 0x7f;
+                pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
+
+                /* Set Multi 3 to VCC3V# */
+                pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
+
+                /* Disable CLK_REQ# support after media DET */
+                ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch);
+                if (ret)
+                        return ret;
+                scratch |= 0x20;
+                pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
+
+                /* Choose capabilities, enable SDMA.  We have to write 0x01
+                 * to the capabilities register first to unlock it.
+                 */
+                ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
+                if (ret)
+                        return ret;
+                scratch |= 0x01;
+                pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
+                pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
+
+                /* Disable ADMA1/2 */
+                pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
+                pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
+
+                /* Disable the infinite transfer mode */
+                ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch);
+                if (ret)
+                        return ret;
+                scratch |= 0x08;
+                pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
+
+                /* Lock WP */
+                ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
+                if (ret)
+                        return ret;
+                scratch |= 0x80;
+                pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
+        }
+
+        return 0;
+}
+
 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
 {
         u8 scratch;
@@ -204,6 +272,7 @@ static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
 static int jmicron_probe(struct sdhci_pci_chip *chip)
 {
         int ret;
+        u16 mmcdev = 0;
 
         if (chip->pdev->revision == 0) {
                 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
@@ -225,12 +294,17 @@ static int jmicron_probe(struct sdhci_pci_chip *chip)
          * 2. The MMC interface has a lower subfunction number
          *    than the SD interface.
          */
-        if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) {
+        if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
+                mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
+        else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
+                mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
+
+        if (mmcdev) {
                 struct pci_dev *sd_dev;
 
                 sd_dev = NULL;
                 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
-                        PCI_DEVICE_ID_JMICRON_JMB38X_MMC, sd_dev)) != NULL) {
+                                                mmcdev, sd_dev)) != NULL) {
                         if ((PCI_SLOT(chip->pdev->devfn) ==
                                 PCI_SLOT(sd_dev->devfn)) &&
                                 (chip->pdev->bus == sd_dev->bus))
@@ -290,13 +364,25 @@ static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
                         slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
         }
 
+        /* JM388 MMC doesn't support 1.8V while SD supports it */
+        if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
+                slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
+                        MMC_VDD_29_30 | MMC_VDD_30_31 |
+                        MMC_VDD_165_195; /* allow 1.8V */
+                slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
+                        MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
+        }
+
         /*
          * The secondary interface requires a bit set to get the
          * interrupts.
          */
-        if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC)
+        if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
+            slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
                 jmicron_enable_mmc(slot->host, 1);
 
+        slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
+
         return 0;
 }
 
@@ -305,7 +391,8 @@ static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
         if (dead)
                 return;
 
-        if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC)
+        if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
+            slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
                 jmicron_enable_mmc(slot->host, 0);
 }
 
@@ -313,7 +400,8 @@ static int jmicron_suspend(struct sdhci_pci_chip *chip, pm_message_t state)
 {
         int i;
 
-        if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC) {
+        if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
+            chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
                 for (i = 0;i < chip->num_slots;i++)
                         jmicron_enable_mmc(chip->slots[i]->host, 0);
         }
@@ -325,7 +413,8 @@ static int jmicron_resume(struct sdhci_pci_chip *chip)
 {
         int ret, i;
 
-        if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC) {
+        if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
+            chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
                 for (i = 0;i < chip->num_slots;i++)
                         jmicron_enable_mmc(chip->slots[i]->host, 1);
         }
@@ -339,6 +428,10 @@ static int jmicron_resume(struct sdhci_pci_chip *chip)
         return 0;
 }
 
+static const struct sdhci_pci_fixes sdhci_o2 = {
+        .probe          = o2_probe,
+};
+
 static const struct sdhci_pci_fixes sdhci_jmicron = {
         .probe          = jmicron_probe,
 
@@ -510,6 +603,22 @@ static const struct pci_device_id pci_ids[] __devinitdata = {
         },
 
         {
+                .vendor         = PCI_VENDOR_ID_JMICRON,
+                .device         = PCI_DEVICE_ID_JMICRON_JMB388_SD,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .driver_data    = (kernel_ulong_t)&sdhci_jmicron,
+        },
+
+        {
+                .vendor         = PCI_VENDOR_ID_JMICRON,
+                .device         = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .driver_data    = (kernel_ulong_t)&sdhci_jmicron,
+        },
+
+        {
                 .vendor         = PCI_VENDOR_ID_SYSKONNECT,
                 .device         = 0x8000,
                 .subvendor      = PCI_ANY_ID,
@@ -589,6 +698,46 @@ static const struct pci_device_id pci_ids[] __devinitdata = {
                 .driver_data    = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio,
         },
 
+        {
+                .vendor         = PCI_VENDOR_ID_O2,
+                .device         = PCI_DEVICE_ID_O2_8120,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .driver_data    = (kernel_ulong_t)&sdhci_o2,
+        },
+
+        {
+                .vendor         = PCI_VENDOR_ID_O2,
+                .device         = PCI_DEVICE_ID_O2_8220,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .driver_data    = (kernel_ulong_t)&sdhci_o2,
+        },
+
+        {
+                .vendor         = PCI_VENDOR_ID_O2,
+                .device         = PCI_DEVICE_ID_O2_8221,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .driver_data    = (kernel_ulong_t)&sdhci_o2,
+        },
+
+        {
+                .vendor         = PCI_VENDOR_ID_O2,
+                .device         = PCI_DEVICE_ID_O2_8320,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .driver_data    = (kernel_ulong_t)&sdhci_o2,
+        },
+
+        {
+                .vendor         = PCI_VENDOR_ID_O2,
+                .device         = PCI_DEVICE_ID_O2_8321,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .driver_data    = (kernel_ulong_t)&sdhci_o2,
+        },
+
         {       /* Generic SD host controller */
                 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
         },
diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index 0502f89f662b..dbab0407f4b6 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -170,6 +170,12 @@ static const struct platform_device_id sdhci_pltfm_ids[] = {
 #ifdef CONFIG_MMC_SDHCI_ESDHC_IMX
         { "sdhci-esdhc-imx", (kernel_ulong_t)&sdhci_esdhc_imx_pdata },
 #endif
+#ifdef CONFIG_MMC_SDHCI_DOVE
+        { "sdhci-dove", (kernel_ulong_t)&sdhci_dove_pdata },
+#endif
+#ifdef CONFIG_MMC_SDHCI_TEGRA
+        { "sdhci-tegra", (kernel_ulong_t)&sdhci_tegra_pdata },
+#endif
         { },
 };
 MODULE_DEVICE_TABLE(platform, sdhci_pltfm_ids);
diff --git a/drivers/mmc/host/sdhci-pltfm.h b/drivers/mmc/host/sdhci-pltfm.h
index c1bfe48af56a..ea2e44d9be5e 100644
--- a/drivers/mmc/host/sdhci-pltfm.h
+++ b/drivers/mmc/host/sdhci-pltfm.h
@@ -22,5 +22,7 @@ struct sdhci_pltfm_host {
 
 extern struct sdhci_pltfm_data sdhci_cns3xxx_pdata;
 extern struct sdhci_pltfm_data sdhci_esdhc_imx_pdata;
+extern struct sdhci_pltfm_data sdhci_dove_pdata;
+extern struct sdhci_pltfm_data sdhci_tegra_pdata;
 
 #endif /* _DRIVERS_MMC_SDHCI_PLTFM_H */
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index aacb862ecc8a..17203586305c 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -130,6 +130,15 @@ static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
         if (!clksrc)
                 return UINT_MAX;
 
+        /*
+         * Clock divider's step is different as 1 from that of host controller
+         * when 'clk_type' is S3C_SDHCI_CLK_DIV_EXTERNAL.
+         */
+        if (ourhost->pdata->clk_type) {
+                rate = clk_round_rate(clksrc, wanted);
+                return wanted - rate;
+        }
+
         rate = clk_get_rate(clksrc);
 
         for (div = 1; div < 256; div *= 2) {
@@ -232,6 +241,42 @@ static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
         return min;
 }
 
+/* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
+static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
+{
+        struct sdhci_s3c *ourhost = to_s3c(host);
+
+        return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], UINT_MAX);
+}
+
+/* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
+static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
+{
+        struct sdhci_s3c *ourhost = to_s3c(host);
+
+        /*
+         * initial clock can be in the frequency range of
+         * 100KHz-400KHz, so we set it as max value.
+         */
+        return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], 400000);
+}
+
+/* sdhci_cmu_set_clock - callback on clock change.*/
+static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+        struct sdhci_s3c *ourhost = to_s3c(host);
+
+        /* don't bother if the clock is going off */
+        if (clock == 0)
+                return;
+
+        sdhci_s3c_set_clock(host, clock);
+
+        clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
+
+        host->clock = clock;
+}
+
 static struct sdhci_ops sdhci_s3c_ops = {
         .get_max_clock          = sdhci_s3c_get_max_clk,
         .set_clock              = sdhci_s3c_set_clock,
@@ -361,6 +406,13 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 
                 clks++;
                 sc->clk_bus[ptr] = clk;
+
+                /*
+                 * save current clock index to know which clock bus
+                 * is used later in overriding functions.
+                 */
+                sc->cur_clk = ptr;
+
                 clk_enable(clk);
 
                 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
@@ -427,6 +479,20 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
         /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
         host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
 
+        /*
+         * If controller does not have internal clock divider,
+         * we can use overriding functions instead of default.
+         */
+        if (pdata->clk_type) {
+                sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
+                sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
+                sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
+        }
+
+        /* It supports additional host capabilities if needed */
+        if (pdata->host_caps)
+                host->mmc->caps |= pdata->host_caps;
+
         ret = sdhci_add_host(host);
         if (ret) {
                 dev_err(dev, "sdhci_add_host() failed\n");
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
new file mode 100644
index 000000000000..4823ee94a63f
--- /dev/null
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -0,0 +1,257 @@
+/*
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+
+#include <mach/gpio.h>
+#include <mach/sdhci.h>
+
+#include "sdhci.h"
+#include "sdhci-pltfm.h"
+
+static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg)
+{
+        u32 val;
+
+        if (unlikely(reg == SDHCI_PRESENT_STATE)) {
+                /* Use wp_gpio here instead? */
+                val = readl(host->ioaddr + reg);
+                return val | SDHCI_WRITE_PROTECT;
+        }
+
+        return readl(host->ioaddr + reg);
+}
+
+static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
+{
+        if (unlikely(reg == SDHCI_HOST_VERSION)) {
+                /* Erratum: Version register is invalid in HW. */
+                return SDHCI_SPEC_200;
+        }
+
+        return readw(host->ioaddr + reg);
+}
+
+static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
+{
+        /* Seems like we're getting spurious timeout and crc errors, so
+         * disable signalling of them. In case of real errors software
+         * timers should take care of eventually detecting them.
+         */
+        if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
+                val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
+
+        writel(val, host->ioaddr + reg);
+
+        if (unlikely(reg == SDHCI_INT_ENABLE)) {
+                /* Erratum: Must enable block gap interrupt detection */
+                u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
+                if (val & SDHCI_INT_CARD_INT)
+                        gap_ctrl |= 0x8;
+                else
+                        gap_ctrl &= ~0x8;
+                writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
+        }
+}
+
+static unsigned int tegra_sdhci_get_ro(struct sdhci_host *sdhci)
+{
+        struct platform_device *pdev = to_platform_device(mmc_dev(sdhci->mmc));
+        struct tegra_sdhci_platform_data *plat;
+
+        plat = pdev->dev.platform_data;
+
+        if (!gpio_is_valid(plat->wp_gpio))
+                return -1;
+
+        return gpio_get_value(plat->wp_gpio);
+}
+
+static irqreturn_t carddetect_irq(int irq, void *data)
+{
+        struct sdhci_host *sdhost = (struct sdhci_host *)data;
+
+        tasklet_schedule(&sdhost->card_tasklet);
+        return IRQ_HANDLED;
+};
+
+static int tegra_sdhci_8bit(struct sdhci_host *host, int bus_width)
+{
+        struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
+        struct tegra_sdhci_platform_data *plat;
+        u32 ctrl;
+
+        plat = pdev->dev.platform_data;
+
+        ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+        if (plat->is_8bit && bus_width == MMC_BUS_WIDTH_8) {
+                ctrl &= ~SDHCI_CTRL_4BITBUS;
+                ctrl |= SDHCI_CTRL_8BITBUS;
+        } else {
+                ctrl &= ~SDHCI_CTRL_8BITBUS;
+                if (bus_width == MMC_BUS_WIDTH_4)
+                        ctrl |= SDHCI_CTRL_4BITBUS;
+                else
+                        ctrl &= ~SDHCI_CTRL_4BITBUS;
+        }
+        sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+        return 0;
+}
+
+
+static int tegra_sdhci_pltfm_init(struct sdhci_host *host,
+                                  struct sdhci_pltfm_data *pdata)
+{
+        struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+        struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
+        struct tegra_sdhci_platform_data *plat;
+        struct clk *clk;
+        int rc;
+
+        plat = pdev->dev.platform_data;
+        if (plat == NULL) {
+                dev_err(mmc_dev(host->mmc), "missing platform data\n");
+                return -ENXIO;
+        }
+
+        if (gpio_is_valid(plat->power_gpio)) {
+                rc = gpio_request(plat->power_gpio, "sdhci_power");
+                if (rc) {
+                        dev_err(mmc_dev(host->mmc),
+                                "failed to allocate power gpio\n");
+                        goto out;
+                }
+                tegra_gpio_enable(plat->power_gpio);
+                gpio_direction_output(plat->power_gpio, 1);
+        }
+
+        if (gpio_is_valid(plat->cd_gpio)) {
+                rc = gpio_request(plat->cd_gpio, "sdhci_cd");
+                if (rc) {
+                        dev_err(mmc_dev(host->mmc),
+                                "failed to allocate cd gpio\n");
+                        goto out_power;
+                }
+                tegra_gpio_enable(plat->cd_gpio);
+                gpio_direction_input(plat->cd_gpio);
+
+                rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq,
+                                 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
+                                 mmc_hostname(host->mmc), host);
+
+                if (rc) {
+                        dev_err(mmc_dev(host->mmc), "request irq error\n");
+                        goto out_cd;
+                }
+
+        }
+
+        if (gpio_is_valid(plat->wp_gpio)) {
+                rc = gpio_request(plat->wp_gpio, "sdhci_wp");
+                if (rc) {
+                        dev_err(mmc_dev(host->mmc),
+                                "failed to allocate wp gpio\n");
+                        goto out_cd;
+                }
+                tegra_gpio_enable(plat->wp_gpio);
+                gpio_direction_input(plat->wp_gpio);
+        }
+
+        clk = clk_get(mmc_dev(host->mmc), NULL);
+        if (IS_ERR(clk)) {
+                dev_err(mmc_dev(host->mmc), "clk err\n");
+                rc = PTR_ERR(clk);
+                goto out_wp;
+        }
+        clk_enable(clk);
+        pltfm_host->clk = clk;
+
+        if (plat->is_8bit)
+                host->mmc->caps |= MMC_CAP_8_BIT_DATA;
+
+        return 0;
+
+out_wp:
+        if (gpio_is_valid(plat->wp_gpio)) {
+                tegra_gpio_disable(plat->wp_gpio);
+                gpio_free(plat->wp_gpio);
+        }
+
+out_cd:
+        if (gpio_is_valid(plat->cd_gpio)) {
+                tegra_gpio_disable(plat->cd_gpio);
+                gpio_free(plat->cd_gpio);
+        }
+
+out_power:
+        if (gpio_is_valid(plat->power_gpio)) {
+                tegra_gpio_disable(plat->power_gpio);
+                gpio_free(plat->power_gpio);
+        }
+
+out:
+        return rc;
+}
+
+static void tegra_sdhci_pltfm_exit(struct sdhci_host *host)
+{
+        struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+        struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
+        struct tegra_sdhci_platform_data *plat;
+
+        plat = pdev->dev.platform_data;
+
+        if (gpio_is_valid(plat->wp_gpio)) {
+                tegra_gpio_disable(plat->wp_gpio);
+                gpio_free(plat->wp_gpio);
+        }
+
+        if (gpio_is_valid(plat->cd_gpio)) {
+                tegra_gpio_disable(plat->cd_gpio);
+                gpio_free(plat->cd_gpio);
+        }
+
+        if (gpio_is_valid(plat->power_gpio)) {
+                tegra_gpio_disable(plat->power_gpio);
+                gpio_free(plat->power_gpio);
+        }
+
+        clk_disable(pltfm_host->clk);
+        clk_put(pltfm_host->clk);
+}
+
+static struct sdhci_ops tegra_sdhci_ops = {
+        .get_ro     = tegra_sdhci_get_ro,
+        .read_l     = tegra_sdhci_readl,
+        .read_w     = tegra_sdhci_readw,
+        .write_l    = tegra_sdhci_writel,
+        .platform_8bit_width = tegra_sdhci_8bit,
+};
+
+struct sdhci_pltfm_data sdhci_tegra_pdata = {
+        .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
+                  SDHCI_QUIRK_SINGLE_POWER_WRITE |
+                  SDHCI_QUIRK_NO_HISPD_BIT |
+                  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
+        .ops  = &tegra_sdhci_ops,
+        .init = tegra_sdhci_pltfm_init,
+        .exit = tegra_sdhci_pltfm_exit,
+};
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index a25db426c910..9e15f41f87be 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -23,6 +23,7 @@
 
 #include <linux/leds.h>
 
+#include <linux/mmc/mmc.h>
 #include <linux/mmc/host.h>
 
 #include "sdhci.h"
@@ -77,8 +78,11 @@ static void sdhci_dumpregs(struct sdhci_host *host)
         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
                 sdhci_readw(host, SDHCI_ACMD12_ERR),
                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
-        printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Max curr: 0x%08x\n",
+        printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
                 sdhci_readl(host, SDHCI_CAPABILITIES),
+                sdhci_readl(host, SDHCI_CAPABILITIES_1));
+        printk(KERN_DEBUG DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
+                sdhci_readw(host, SDHCI_COMMAND),
                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 
         if (host->flags & SDHCI_USE_ADMA)
@@ -1518,7 +1522,11 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
 
         if (intmask & SDHCI_INT_DATA_TIMEOUT)
                 host->data->error = -ETIMEDOUT;
-        else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
+        else if (intmask & SDHCI_INT_DATA_END_BIT)
+                host->data->error = -EILSEQ;
+        else if ((intmask & SDHCI_INT_DATA_CRC) &&
+                SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
+                        != MMC_BUS_TEST_R)
                 host->data->error = -EILSEQ;
         else if (intmask & SDHCI_INT_ADMA_ERROR) {
                 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
@@ -1736,7 +1744,7 @@ EXPORT_SYMBOL_GPL(sdhci_alloc_host);
 int sdhci_add_host(struct sdhci_host *host)
 {
         struct mmc_host *mmc;
-        unsigned int caps;
+        unsigned int caps, ocr_avail;
         int ret;
 
         WARN_ON(host == NULL);
@@ -1890,13 +1898,26 @@ int sdhci_add_host(struct sdhci_host *host)
             mmc_card_is_removable(mmc))
                 mmc->caps |= MMC_CAP_NEEDS_POLL;
 
-        mmc->ocr_avail = 0;
+        ocr_avail = 0;
         if (caps & SDHCI_CAN_VDD_330)
-                mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
+                ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
         if (caps & SDHCI_CAN_VDD_300)
-                mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
+                ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
         if (caps & SDHCI_CAN_VDD_180)
-                mmc->ocr_avail |= MMC_VDD_165_195;
+                ocr_avail |= MMC_VDD_165_195;
+
+        mmc->ocr_avail = ocr_avail;
+        mmc->ocr_avail_sdio = ocr_avail;
+        if (host->ocr_avail_sdio)
+                mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
+        mmc->ocr_avail_sd = ocr_avail;
+        if (host->ocr_avail_sd)
+                mmc->ocr_avail_sd &= host->ocr_avail_sd;
+        else /* normal SD controllers don't support 1.8V */
+                mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
+        mmc->ocr_avail_mmc = ocr_avail;
+        if (host->ocr_avail_mmc)
+                mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
 
         if (mmc->ocr_avail == 0) {
                 printk(KERN_ERR "%s: Hardware doesn't report any "
@@ -1928,10 +1949,14 @@ int sdhci_add_host(struct sdhci_host *host)
          * of bytes. When doing hardware scatter/gather, each entry cannot
          * be larger than 64 KiB though.
          */
-        if (host->flags & SDHCI_USE_ADMA)
-                mmc->max_seg_size = 65536;
-        else
+        if (host->flags & SDHCI_USE_ADMA) {
+                if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
+                        mmc->max_seg_size = 65535;
+                else
+                        mmc->max_seg_size = 65536;
+        } else {
                 mmc->max_seg_size = mmc->max_req_size;
+        }
 
         /*
          * Maximum block size. This varies from controller to controller and
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index e42d7f00c060..6e0969e40650 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -52,6 +52,7 @@
 #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
 
 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
+#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
 
 #define SDHCI_RESPONSE          0x10
 
@@ -165,7 +166,7 @@
 #define  SDHCI_CAN_VDD_180      0x04000000
 #define  SDHCI_CAN_64BIT        0x10000000
 
-/* 44-47 reserved for more caps */
+#define SDHCI_CAPABILITIES_1    0x44
 
 #define SDHCI_MAX_CURRENT       0x48
 
diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c
index e7765a89593e..e3c6ef208391 100644
--- a/drivers/mmc/host/tmio_mmc.c
+++ b/drivers/mmc/host/tmio_mmc.c
@@ -25,16 +25,261 @@
  *   double buffer support
  *
  */
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <linux/device.h>
+
 #include <linux/delay.h>
+#include <linux/device.h>
 #include <linux/dmaengine.h>
-#include <linux/mmc/host.h>
+#include <linux/highmem.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
 #include <linux/mfd/core.h>
 #include <linux/mfd/tmio.h>
+#include <linux/mmc/host.h>
+#include <linux/module.h>
+#include <linux/pagemap.h>
+#include <linux/scatterlist.h>
+#include <linux/workqueue.h>
+#include <linux/spinlock.h>
+
+#define CTL_SD_CMD 0x00
+#define CTL_ARG_REG 0x04
+#define CTL_STOP_INTERNAL_ACTION 0x08
+#define CTL_XFER_BLK_COUNT 0xa
+#define CTL_RESPONSE 0x0c
+#define CTL_STATUS 0x1c
+#define CTL_IRQ_MASK 0x20
+#define CTL_SD_CARD_CLK_CTL 0x24
+#define CTL_SD_XFER_LEN 0x26
+#define CTL_SD_MEM_CARD_OPT 0x28
+#define CTL_SD_ERROR_DETAIL_STATUS 0x2c
+#define CTL_SD_DATA_PORT 0x30
+#define CTL_TRANSACTION_CTL 0x34
+#define CTL_SDIO_STATUS 0x36
+#define CTL_SDIO_IRQ_MASK 0x38
+#define CTL_RESET_SD 0xe0
+#define CTL_SDIO_REGS 0x100
+#define CTL_CLK_AND_WAIT_CTL 0x138
+#define CTL_RESET_SDIO 0x1e0
+
+/* Definitions for values the CTRL_STATUS register can take. */
+#define TMIO_STAT_CMDRESPEND    0x00000001
+#define TMIO_STAT_DATAEND       0x00000004
+#define TMIO_STAT_CARD_REMOVE   0x00000008
+#define TMIO_STAT_CARD_INSERT   0x00000010
+#define TMIO_STAT_SIGSTATE      0x00000020
+#define TMIO_STAT_WRPROTECT     0x00000080
+#define TMIO_STAT_CARD_REMOVE_A 0x00000100
+#define TMIO_STAT_CARD_INSERT_A 0x00000200
+#define TMIO_STAT_SIGSTATE_A    0x00000400
+#define TMIO_STAT_CMD_IDX_ERR   0x00010000
+#define TMIO_STAT_CRCFAIL       0x00020000
+#define TMIO_STAT_STOPBIT_ERR   0x00040000
+#define TMIO_STAT_DATATIMEOUT   0x00080000
+#define TMIO_STAT_RXOVERFLOW    0x00100000
+#define TMIO_STAT_TXUNDERRUN    0x00200000
+#define TMIO_STAT_CMDTIMEOUT    0x00400000
+#define TMIO_STAT_RXRDY         0x01000000
+#define TMIO_STAT_TXRQ          0x02000000
+#define TMIO_STAT_ILL_FUNC      0x20000000
+#define TMIO_STAT_CMD_BUSY      0x40000000
+#define TMIO_STAT_ILL_ACCESS    0x80000000
+
+/* Definitions for values the CTRL_SDIO_STATUS register can take. */
+#define TMIO_SDIO_STAT_IOIRQ    0x0001
+#define TMIO_SDIO_STAT_EXPUB52  0x4000
+#define TMIO_SDIO_STAT_EXWT     0x8000
+#define TMIO_SDIO_MASK_ALL      0xc007
+
+/* Define some IRQ masks */
+/* This is the mask used at reset by the chip */
+#define TMIO_MASK_ALL           0x837f031d
+#define TMIO_MASK_READOP  (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND)
+#define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND)
+#define TMIO_MASK_CMD     (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \
+                TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
+#define TMIO_MASK_IRQ     (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD)
+
+#define enable_mmc_irqs(host, i) \
+        do { \
+                u32 mask;\
+                mask  = sd_ctrl_read32((host), CTL_IRQ_MASK); \
+                mask &= ~((i) & TMIO_MASK_IRQ); \
+                sd_ctrl_write32((host), CTL_IRQ_MASK, mask); \
+        } while (0)
+
+#define disable_mmc_irqs(host, i) \
+        do { \
+                u32 mask;\
+                mask  = sd_ctrl_read32((host), CTL_IRQ_MASK); \
+                mask |= ((i) & TMIO_MASK_IRQ); \
+                sd_ctrl_write32((host), CTL_IRQ_MASK, mask); \
+        } while (0)
+
+#define ack_mmc_irqs(host, i) \
+        do { \
+                sd_ctrl_write32((host), CTL_STATUS, ~(i)); \
+        } while (0)
+
+/* This is arbitrary, just noone needed any higher alignment yet */
+#define MAX_ALIGN 4
+
+struct tmio_mmc_host {
+        void __iomem *ctl;
+        unsigned long bus_shift;
+        struct mmc_command      *cmd;
+        struct mmc_request      *mrq;
+        struct mmc_data         *data;
+        struct mmc_host         *mmc;
+        int                     irq;
+        unsigned int            sdio_irq_enabled;
+
+        /* Callbacks for clock / power control */
+        void (*set_pwr)(struct platform_device *host, int state);
+        void (*set_clk_div)(struct platform_device *host, int state);
+
+        /* pio related stuff */
+        struct scatterlist      *sg_ptr;
+        struct scatterlist      *sg_orig;
+        unsigned int            sg_len;
+        unsigned int            sg_off;
+
+        struct platform_device *pdev;
+
+        /* DMA support */
+        struct dma_chan         *chan_rx;
+        struct dma_chan         *chan_tx;
+        struct tasklet_struct   dma_complete;
+        struct tasklet_struct   dma_issue;
+#ifdef CONFIG_TMIO_MMC_DMA
+        unsigned int            dma_sglen;
+        u8                      bounce_buf[PAGE_CACHE_SIZE] __attribute__((aligned(MAX_ALIGN)));
+        struct scatterlist      bounce_sg;
+#endif
+
+        /* Track lost interrupts */
+        struct delayed_work     delayed_reset_work;
+        spinlock_t              lock;
+        unsigned long           last_req_ts;
+};
+
+static void tmio_check_bounce_buffer(struct tmio_mmc_host *host);
+
+static u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
+{
+        return readw(host->ctl + (addr << host->bus_shift));
+}
+
+static void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
+                u16 *buf, int count)
+{
+        readsw(host->ctl + (addr << host->bus_shift), buf, count);
+}
 
-#include "tmio_mmc.h"
+static u32 sd_ctrl_read32(struct tmio_mmc_host *host, int addr)
+{
+        return readw(host->ctl + (addr << host->bus_shift)) |
+               readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
+}
+
+static void sd_ctrl_write16(struct tmio_mmc_host *host, int addr, u16 val)
+{
+        writew(val, host->ctl + (addr << host->bus_shift));
+}
+
+static void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
+                u16 *buf, int count)
+{
+        writesw(host->ctl + (addr << host->bus_shift), buf, count);
+}
+
+static void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, u32 val)
+{
+        writew(val, host->ctl + (addr << host->bus_shift));
+        writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
+}
+
+static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data)
+{
+        host->sg_len = data->sg_len;
+        host->sg_ptr = data->sg;
+        host->sg_orig = data->sg;
+        host->sg_off = 0;
+}
+
+static int tmio_mmc_next_sg(struct tmio_mmc_host *host)
+{
+        host->sg_ptr = sg_next(host->sg_ptr);
+        host->sg_off = 0;
+        return --host->sg_len;
+}
+
+static char *tmio_mmc_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
+{
+        local_irq_save(*flags);
+        return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
+}
+
+static void tmio_mmc_kunmap_atomic(void *virt, unsigned long *flags)
+{
+        kunmap_atomic(virt, KM_BIO_SRC_IRQ);
+        local_irq_restore(*flags);
+}
+
+#ifdef CONFIG_MMC_DEBUG
+
+#define STATUS_TO_TEXT(a) \
+        do { \
+                if (status & TMIO_STAT_##a) \
+                        printk(#a); \
+        } while (0)
+
+void pr_debug_status(u32 status)
+{
+        printk(KERN_DEBUG "status: %08x = ", status);
+        STATUS_TO_TEXT(CARD_REMOVE);
+        STATUS_TO_TEXT(CARD_INSERT);
+        STATUS_TO_TEXT(SIGSTATE);
+        STATUS_TO_TEXT(WRPROTECT);
+        STATUS_TO_TEXT(CARD_REMOVE_A);
+        STATUS_TO_TEXT(CARD_INSERT_A);
+        STATUS_TO_TEXT(SIGSTATE_A);
+        STATUS_TO_TEXT(CMD_IDX_ERR);
+        STATUS_TO_TEXT(STOPBIT_ERR);
+        STATUS_TO_TEXT(ILL_FUNC);
+        STATUS_TO_TEXT(CMD_BUSY);
+        STATUS_TO_TEXT(CMDRESPEND);
+        STATUS_TO_TEXT(DATAEND);
+        STATUS_TO_TEXT(CRCFAIL);
+        STATUS_TO_TEXT(DATATIMEOUT);
+        STATUS_TO_TEXT(CMDTIMEOUT);
+        STATUS_TO_TEXT(RXOVERFLOW);
+        STATUS_TO_TEXT(TXUNDERRUN);
+        STATUS_TO_TEXT(RXRDY);
+        STATUS_TO_TEXT(TXRQ);
+        STATUS_TO_TEXT(ILL_ACCESS);
+        printk("\n");
+}
+
+#else
+#define pr_debug_status(s)  do { } while (0)
+#endif
+
+static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+        struct tmio_mmc_host *host = mmc_priv(mmc);
+
+        if (enable) {
+                host->sdio_irq_enabled = 1;
+                sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
+                sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK,
+                        (TMIO_SDIO_MASK_ALL & ~TMIO_SDIO_STAT_IOIRQ));
+        } else {
+                sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, TMIO_SDIO_MASK_ALL);
+                sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000);
+                host->sdio_irq_enabled = 0;
+        }
+}
 
 static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
 {
@@ -55,8 +300,23 @@ static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
 
 static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
 {
+        struct mfd_cell *cell = host->pdev->dev.platform_data;
+        struct tmio_mmc_data *pdata = cell->driver_data;
+
+        /*
+         * Testing on sh-mobile showed that SDIO IRQs are unmasked when
+         * CTL_CLK_AND_WAIT_CTL gets written, so we have to disable the
+         * device IRQ here and restore the SDIO IRQ mask before
+         * re-enabling the device IRQ.
+         */
+        if (pdata->flags & TMIO_MMC_SDIO_IRQ)
+                disable_irq(host->irq);
         sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
         msleep(10);
+        if (pdata->flags & TMIO_MMC_SDIO_IRQ) {
+                tmio_mmc_enable_sdio_irq(host->mmc, host->sdio_irq_enabled);
+                enable_irq(host->irq);
+        }
         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 &
                 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
         msleep(10);
@@ -64,11 +324,21 @@ static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
 
 static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
 {
+        struct mfd_cell *cell = host->pdev->dev.platform_data;
+        struct tmio_mmc_data *pdata = cell->driver_data;
+
         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
                 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
         msleep(10);
+        /* see comment in tmio_mmc_clk_stop above */
+        if (pdata->flags & TMIO_MMC_SDIO_IRQ)
+                disable_irq(host->irq);
         sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
         msleep(10);
+        if (pdata->flags & TMIO_MMC_SDIO_IRQ) {
+                tmio_mmc_enable_sdio_irq(host->mmc, host->sdio_irq_enabled);
+                enable_irq(host->irq);
+        }
 }
 
 static void reset(struct tmio_mmc_host *host)
@@ -82,15 +352,60 @@ static void reset(struct tmio_mmc_host *host)
         msleep(10);
 }
 
+static void tmio_mmc_reset_work(struct work_struct *work)
+{
+        struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
+                                                  delayed_reset_work.work);
+        struct mmc_request *mrq;
+        unsigned long flags;
+
+        spin_lock_irqsave(&host->lock, flags);
+        mrq = host->mrq;
+
+        /* request already finished */
+        if (!mrq
+            || time_is_after_jiffies(host->last_req_ts +
+                msecs_to_jiffies(2000))) {
+                spin_unlock_irqrestore(&host->lock, flags);
+                return;
+        }
+
+        dev_warn(&host->pdev->dev,
+                "timeout waiting for hardware interrupt (CMD%u)\n",
+                mrq->cmd->opcode);
+
+        if (host->data)
+                host->data->error = -ETIMEDOUT;
+        else if (host->cmd)
+                host->cmd->error = -ETIMEDOUT;
+        else
+                mrq->cmd->error = -ETIMEDOUT;
+
+        host->cmd = NULL;
+        host->data = NULL;
+        host->mrq = NULL;
+
+        spin_unlock_irqrestore(&host->lock, flags);
+
+        reset(host);
+
+        mmc_request_done(host->mmc, mrq);
+}
+
 static void
 tmio_mmc_finish_request(struct tmio_mmc_host *host)
 {
         struct mmc_request *mrq = host->mrq;
 
+        if (!mrq)
+                return;
+
         host->mrq = NULL;
         host->cmd = NULL;
         host->data = NULL;
 
+        cancel_delayed_work(&host->delayed_reset_work);
+
         mmc_request_done(host->mmc, mrq);
 }
 
@@ -200,6 +515,7 @@ static void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
         return;
 }
 
+/* needs to be called with host->lock held */
 static void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
 {
         struct mmc_data *data = host->data;
@@ -233,6 +549,8 @@ static void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
         if (data->flags & MMC_DATA_READ) {
                 if (!host->chan_rx)
                         disable_mmc_irqs(host, TMIO_MASK_READOP);
+                else
+                        tmio_check_bounce_buffer(host);
                 dev_dbg(&host->pdev->dev, "Complete Rx request %p\n",
                         host->mrq);
         } else {
@@ -254,10 +572,12 @@ static void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
 
 static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
 {
-        struct mmc_data *data = host->data;
+        struct mmc_data *data;
+        spin_lock(&host->lock);
+        data = host->data;
 
         if (!data)
-                return;
+                goto out;
 
         if (host->chan_tx && (data->flags & MMC_DATA_WRITE)) {
                 /*
@@ -278,6 +598,8 @@ static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
         } else {
                 tmio_mmc_do_data_irq(host);
         }
+out:
+        spin_unlock(&host->lock);
 }
 
 static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
@@ -286,9 +608,11 @@ static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
         struct mmc_command *cmd = host->cmd;
         int i, addr;
 
+        spin_lock(&host->lock);
+
         if (!host->cmd) {
                 pr_debug("Spurious CMD irq\n");
-                return;
+                goto out;
         }
 
         host->cmd = NULL;
@@ -324,8 +648,7 @@ static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
                         if (!host->chan_rx)
                                 enable_mmc_irqs(host, TMIO_MASK_READOP);
                 } else {
-                        struct dma_chan *chan = host->chan_tx;
-                        if (!chan)
+                        if (!host->chan_tx)
                                 enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
                         else
                                 tasklet_schedule(&host->dma_issue);
@@ -334,13 +657,19 @@ static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
                 tmio_mmc_finish_request(host);
         }
 
+out:
+        spin_unlock(&host->lock);
+
         return;
 }
 
 static irqreturn_t tmio_mmc_irq(int irq, void *devid)
 {
         struct tmio_mmc_host *host = devid;
+        struct mfd_cell *cell = host->pdev->dev.platform_data;
+        struct tmio_mmc_data *pdata = cell->driver_data;
         unsigned int ireg, irq_mask, status;
+        unsigned int sdio_ireg, sdio_irq_mask, sdio_status;
 
         pr_debug("MMC IRQ begin\n");
 
@@ -348,6 +677,29 @@ static irqreturn_t tmio_mmc_irq(int irq, void *devid)
         irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK);
         ireg = status & TMIO_MASK_IRQ & ~irq_mask;
 
+        sdio_ireg = 0;
+        if (!ireg && pdata->flags & TMIO_MMC_SDIO_IRQ) {
+                sdio_status = sd_ctrl_read16(host, CTL_SDIO_STATUS);
+                sdio_irq_mask = sd_ctrl_read16(host, CTL_SDIO_IRQ_MASK);
+                sdio_ireg = sdio_status & TMIO_SDIO_MASK_ALL & ~sdio_irq_mask;
+
+                sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status & ~TMIO_SDIO_MASK_ALL);
+
+                if (sdio_ireg && !host->sdio_irq_enabled) {
+                        pr_warning("tmio_mmc: Spurious SDIO IRQ, disabling! 0x%04x 0x%04x 0x%04x\n",
+                                   sdio_status, sdio_irq_mask, sdio_ireg);
+                        tmio_mmc_enable_sdio_irq(host->mmc, 0);
+                        goto out;
+                }
+
+                if (host->mmc->caps & MMC_CAP_SDIO_IRQ &&
+                        sdio_ireg & TMIO_SDIO_STAT_IOIRQ)
+                        mmc_signal_sdio_irq(host->mmc);
+
+                if (sdio_ireg)
+                        goto out;
+        }
+
         pr_debug_status(status);
         pr_debug_status(ireg);
 
@@ -375,8 +727,10 @@ static irqreturn_t tmio_mmc_irq(int irq, void *devid)
  */
 
                 /* Command completion */
-                if (ireg & TMIO_MASK_CMD) {
-                        ack_mmc_irqs(host, TMIO_MASK_CMD);
+                if (ireg & (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT)) {
+                        ack_mmc_irqs(host,
+                                     TMIO_STAT_CMDRESPEND |
+                                     TMIO_STAT_CMDTIMEOUT);
                         tmio_mmc_cmd_irq(host, status);
                 }
 
@@ -407,6 +761,16 @@ out:
 }
 
 #ifdef CONFIG_TMIO_MMC_DMA
+static void tmio_check_bounce_buffer(struct tmio_mmc_host *host)
+{
+        if (host->sg_ptr == &host->bounce_sg) {
+                unsigned long flags;
+                void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags);
+                memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length);
+                tmio_mmc_kunmap_atomic(sg_vaddr, &flags);
+        }
+}
+
 static void tmio_mmc_enable_dma(struct tmio_mmc_host *host, bool enable)
 {
 #if defined(CONFIG_SUPERH) || defined(CONFIG_ARCH_SHMOBILE)
@@ -427,12 +791,39 @@ static void tmio_dma_complete(void *arg)
                 enable_mmc_irqs(host, TMIO_STAT_DATAEND);
 }
 
-static int tmio_mmc_start_dma_rx(struct tmio_mmc_host *host)
+static void tmio_mmc_start_dma_rx(struct tmio_mmc_host *host)
 {
-        struct scatterlist *sg = host->sg_ptr;
+        struct scatterlist *sg = host->sg_ptr, *sg_tmp;
         struct dma_async_tx_descriptor *desc = NULL;
         struct dma_chan *chan = host->chan_rx;
-        int ret;
+        struct mfd_cell *cell = host->pdev->dev.platform_data;
+        struct tmio_mmc_data *pdata = cell->driver_data;
+        dma_cookie_t cookie;
+        int ret, i;
+        bool aligned = true, multiple = true;
+        unsigned int align = (1 << pdata->dma->alignment_shift) - 1;
+
+        for_each_sg(sg, sg_tmp, host->sg_len, i) {
+                if (sg_tmp->offset & align)
+                        aligned = false;
+                if (sg_tmp->length & align) {
+                        multiple = false;
+                        break;
+                }
+        }
+
+        if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_CACHE_SIZE ||
+                          align >= MAX_ALIGN)) || !multiple) {
+                ret = -EINVAL;
+                goto pio;
+        }
+
+        /* The only sg element can be unaligned, use our bounce buffer then */
+        if (!aligned) {
+                sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
+                host->sg_ptr = &host->bounce_sg;
+                sg = host->sg_ptr;
+        }
 
         ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, DMA_FROM_DEVICE);
         if (ret > 0) {
@@ -442,21 +833,21 @@ static int tmio_mmc_start_dma_rx(struct tmio_mmc_host *host)
         }
 
         if (desc) {
-                host->desc = desc;
                 desc->callback = tmio_dma_complete;
                 desc->callback_param = host;
-                host->cookie = desc->tx_submit(desc);
-                if (host->cookie < 0) {
-                        host->desc = NULL;
-                        ret = host->cookie;
+                cookie = desc->tx_submit(desc);
+                if (cookie < 0) {
+                        desc = NULL;
+                        ret = cookie;
                 } else {
                         chan->device->device_issue_pending(chan);
                 }
         }
         dev_dbg(&host->pdev->dev, "%s(): mapped %d -> %d, cookie %d, rq %p\n",
-                __func__, host->sg_len, ret, host->cookie, host->mrq);
+                __func__, host->sg_len, ret, cookie, host->mrq);
 
-        if (!host->desc) {
+pio:
+        if (!desc) {
                 /* DMA failed, fall back to PIO */
                 if (ret >= 0)
                         ret = -EIO;
@@ -471,24 +862,49 @@ static int tmio_mmc_start_dma_rx(struct tmio_mmc_host *host)
                 dev_warn(&host->pdev->dev,
                          "DMA failed: %d, falling back to PIO\n", ret);
                 tmio_mmc_enable_dma(host, false);
-                reset(host);
-                /* Fail this request, let above layers recover */
-                host->mrq->cmd->error = ret;
-                tmio_mmc_finish_request(host);
         }
 
         dev_dbg(&host->pdev->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
-                desc, host->cookie, host->sg_len);
-
-        return ret > 0 ? 0 : ret;
+                desc, cookie, host->sg_len);
 }
 
-static int tmio_mmc_start_dma_tx(struct tmio_mmc_host *host)
+static void tmio_mmc_start_dma_tx(struct tmio_mmc_host *host)
 {
-        struct scatterlist *sg = host->sg_ptr;
+        struct scatterlist *sg = host->sg_ptr, *sg_tmp;
         struct dma_async_tx_descriptor *desc = NULL;
         struct dma_chan *chan = host->chan_tx;
-        int ret;
+        struct mfd_cell *cell = host->pdev->dev.platform_data;
+        struct tmio_mmc_data *pdata = cell->driver_data;
+        dma_cookie_t cookie;
+        int ret, i;
+        bool aligned = true, multiple = true;
+        unsigned int align = (1 << pdata->dma->alignment_shift) - 1;
+
+        for_each_sg(sg, sg_tmp, host->sg_len, i) {
+                if (sg_tmp->offset & align)
+                        aligned = false;
+                if (sg_tmp->length & align) {
+                        multiple = false;
+                        break;
+                }
+        }
+
+        if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_CACHE_SIZE ||
+                          align >= MAX_ALIGN)) || !multiple) {
+                ret = -EINVAL;
+                goto pio;
+        }
+
+        /* The only sg element can be unaligned, use our bounce buffer then */
+        if (!aligned) {
+                unsigned long flags;
+                void *sg_vaddr = tmio_mmc_kmap_atomic(sg, &flags);
+                sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
+                memcpy(host->bounce_buf, sg_vaddr, host->bounce_sg.length);
+                tmio_mmc_kunmap_atomic(sg_vaddr, &flags);
+                host->sg_ptr = &host->bounce_sg;
+                sg = host->sg_ptr;
+        }
 
         ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, DMA_TO_DEVICE);
         if (ret > 0) {
@@ -498,19 +914,19 @@ static int tmio_mmc_start_dma_tx(struct tmio_mmc_host *host)
         }
 
         if (desc) {
-                host->desc = desc;
                 desc->callback = tmio_dma_complete;
                 desc->callback_param = host;
-                host->cookie = desc->tx_submit(desc);
-                if (host->cookie < 0) {
-                        host->desc = NULL;
-                        ret = host->cookie;
+                cookie = desc->tx_submit(desc);
+                if (cookie < 0) {
+                        desc = NULL;
+                        ret = cookie;
                 }
         }
         dev_dbg(&host->pdev->dev, "%s(): mapped %d -> %d, cookie %d, rq %p\n",
-                __func__, host->sg_len, ret, host->cookie, host->mrq);
+                __func__, host->sg_len, ret, cookie, host->mrq);
 
-        if (!host->desc) {
+pio:
+        if (!desc) {
                 /* DMA failed, fall back to PIO */
                 if (ret >= 0)
                         ret = -EIO;
@@ -525,30 +941,22 @@ static int tmio_mmc_start_dma_tx(struct tmio_mmc_host *host)
                 dev_warn(&host->pdev->dev,
                          "DMA failed: %d, falling back to PIO\n", ret);
                 tmio_mmc_enable_dma(host, false);
-                reset(host);
-                /* Fail this request, let above layers recover */
-                host->mrq->cmd->error = ret;
-                tmio_mmc_finish_request(host);
         }
 
         dev_dbg(&host->pdev->dev, "%s(): desc %p, cookie %d\n", __func__,
-                desc, host->cookie);
-
-        return ret > 0 ? 0 : ret;
+                desc, cookie);
 }
 
-static int tmio_mmc_start_dma(struct tmio_mmc_host *host,
+static void tmio_mmc_start_dma(struct tmio_mmc_host *host,
                                struct mmc_data *data)
 {
         if (data->flags & MMC_DATA_READ) {
                 if (host->chan_rx)
-                        return tmio_mmc_start_dma_rx(host);
+                        tmio_mmc_start_dma_rx(host);
         } else {
                 if (host->chan_tx)
-                        return tmio_mmc_start_dma_tx(host);
+                        tmio_mmc_start_dma_tx(host);
         }
-
-        return 0;
 }
 
 static void tmio_issue_tasklet_fn(unsigned long priv)
@@ -562,6 +970,12 @@ static void tmio_issue_tasklet_fn(unsigned long priv)
 static void tmio_tasklet_fn(unsigned long arg)
 {
         struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
+        unsigned long flags;
+
+        spin_lock_irqsave(&host->lock, flags);
+
+        if (!host->data)
+                goto out;
 
         if (host->data->flags & MMC_DATA_READ)
                 dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->dma_sglen,
@@ -571,6 +985,8 @@ static void tmio_tasklet_fn(unsigned long arg)
                              DMA_TO_DEVICE);
 
         tmio_mmc_do_data_irq(host);
+out:
+        spin_unlock_irqrestore(&host->lock, flags);
 }
 
 /* It might be necessary to make filter MFD specific */
@@ -584,9 +1000,6 @@ static bool tmio_mmc_filter(struct dma_chan *chan, void *arg)
 static void tmio_mmc_request_dma(struct tmio_mmc_host *host,
                                  struct tmio_mmc_data *pdata)
 {
-        host->cookie = -EINVAL;
-        host->desc = NULL;
-
         /* We can only either use DMA for both Tx and Rx or not use it at all */
         if (pdata->dma) {
                 dma_cap_mask_t mask;
@@ -632,15 +1045,15 @@ static void tmio_mmc_release_dma(struct tmio_mmc_host *host)
                 host->chan_rx = NULL;
                 dma_release_channel(chan);
         }
-
-        host->cookie = -EINVAL;
-        host->desc = NULL;
 }
 #else
-static int tmio_mmc_start_dma(struct tmio_mmc_host *host,
+static void tmio_check_bounce_buffer(struct tmio_mmc_host *host)
+{
+}
+
+static void tmio_mmc_start_dma(struct tmio_mmc_host *host,
                                struct mmc_data *data)
 {
-        return 0;
 }
 
 static void tmio_mmc_request_dma(struct tmio_mmc_host *host,
@@ -682,7 +1095,9 @@ static int tmio_mmc_start_data(struct tmio_mmc_host *host,
         sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
         sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
 
-        return tmio_mmc_start_dma(host, data);
+        tmio_mmc_start_dma(host, data);
+
+        return 0;
 }
 
 /* Process requests from the MMC layer */
@@ -694,6 +1109,8 @@ static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
         if (host->mrq)
                 pr_debug("request not null\n");
 
+        host->last_req_ts = jiffies;
+        wmb();
         host->mrq = mrq;
 
         if (mrq->data) {
@@ -703,10 +1120,14 @@ static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
         }
 
         ret = tmio_mmc_start_command(host, mrq->cmd);
-        if (!ret)
+        if (!ret) {
+                schedule_delayed_work(&host->delayed_reset_work,
+                                      msecs_to_jiffies(2000));
                 return;
+        }
 
 fail:
+        host->mrq = NULL;
         mrq->cmd->error = ret;
         mmc_request_done(mmc, mrq);
 }
@@ -780,6 +1201,7 @@ static const struct mmc_host_ops tmio_mmc_ops = {
         .set_ios        = tmio_mmc_set_ios,
         .get_ro         = tmio_mmc_get_ro,
         .get_cd         = tmio_mmc_get_cd,
+        .enable_sdio_irq = tmio_mmc_enable_sdio_irq,
 };
 
 #ifdef CONFIG_PM
@@ -864,10 +1286,15 @@ static int __devinit tmio_mmc_probe(struct platform_device *dev)
                 goto host_free;
 
         mmc->ops = &tmio_mmc_ops;
-        mmc->caps = MMC_CAP_4_BIT_DATA;
-        mmc->caps |= pdata->capabilities;
+        mmc->caps = MMC_CAP_4_BIT_DATA | pdata->capabilities;
         mmc->f_max = pdata->hclk;
         mmc->f_min = mmc->f_max / 512;
+        mmc->max_segs = 32;
+        mmc->max_blk_size = 512;
+        mmc->max_blk_count = (PAGE_CACHE_SIZE / mmc->max_blk_size) *
+                mmc->max_segs;
+        mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
+        mmc->max_seg_size = mmc->max_req_size;
         if (pdata->ocr_mask)
                 mmc->ocr_avail = pdata->ocr_mask;
         else
@@ -890,12 +1317,19 @@ static int __devinit tmio_mmc_probe(struct platform_device *dev)
                 goto cell_disable;
 
         disable_mmc_irqs(host, TMIO_MASK_ALL);
+        if (pdata->flags & TMIO_MMC_SDIO_IRQ)
+                tmio_mmc_enable_sdio_irq(mmc, 0);
 
         ret = request_irq(host->irq, tmio_mmc_irq, IRQF_DISABLED |
                 IRQF_TRIGGER_FALLING, dev_name(&dev->dev), host);
         if (ret)
                 goto cell_disable;
 
+        spin_lock_init(&host->lock);
+
+        /* Init delayed work for request timeouts */
+        INIT_DELAYED_WORK(&host->delayed_reset_work, tmio_mmc_reset_work);
+
         /* See if we also get DMA */
         tmio_mmc_request_dma(host, pdata);
 
@@ -934,6 +1368,7 @@ static int __devexit tmio_mmc_remove(struct platform_device *dev)
         if (mmc) {
                 struct tmio_mmc_host *host = mmc_priv(mmc);
                 mmc_remove_host(mmc);
+                cancel_delayed_work_sync(&host->delayed_reset_work);
                 tmio_mmc_release_dma(host);
                 free_irq(host->irq, host);
                 if (cell->disable)
diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
deleted file mode 100644
index 0fedc78e3ea5..000000000000
--- a/drivers/mmc/host/tmio_mmc.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/* Definitons for use with the tmio_mmc.c
- *
- * (c) 2004 Ian Molton <spyro@f2s.com>
- * (c) 2007 Ian Molton <spyro@f2s.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/highmem.h>
-#include <linux/interrupt.h>
-#include <linux/dmaengine.h>
-
-#define CTL_SD_CMD 0x00
-#define CTL_ARG_REG 0x04
-#define CTL_STOP_INTERNAL_ACTION 0x08
-#define CTL_XFER_BLK_COUNT 0xa
-#define CTL_RESPONSE 0x0c
-#define CTL_STATUS 0x1c
-#define CTL_IRQ_MASK 0x20
-#define CTL_SD_CARD_CLK_CTL 0x24
-#define CTL_SD_XFER_LEN 0x26
-#define CTL_SD_MEM_CARD_OPT 0x28
-#define CTL_SD_ERROR_DETAIL_STATUS 0x2c
-#define CTL_SD_DATA_PORT 0x30
-#define CTL_TRANSACTION_CTL 0x34
-#define CTL_RESET_SD 0xe0
-#define CTL_SDIO_REGS 0x100
-#define CTL_CLK_AND_WAIT_CTL 0x138
-#define CTL_RESET_SDIO 0x1e0
-
-/* Definitions for values the CTRL_STATUS register can take. */
-#define TMIO_STAT_CMDRESPEND    0x00000001
-#define TMIO_STAT_DATAEND       0x00000004
-#define TMIO_STAT_CARD_REMOVE   0x00000008
-#define TMIO_STAT_CARD_INSERT   0x00000010
-#define TMIO_STAT_SIGSTATE      0x00000020
-#define TMIO_STAT_WRPROTECT     0x00000080
-#define TMIO_STAT_CARD_REMOVE_A 0x00000100
-#define TMIO_STAT_CARD_INSERT_A 0x00000200
-#define TMIO_STAT_SIGSTATE_A    0x00000400
-#define TMIO_STAT_CMD_IDX_ERR   0x00010000
-#define TMIO_STAT_CRCFAIL       0x00020000
-#define TMIO_STAT_STOPBIT_ERR   0x00040000
-#define TMIO_STAT_DATATIMEOUT   0x00080000
-#define TMIO_STAT_RXOVERFLOW    0x00100000
-#define TMIO_STAT_TXUNDERRUN    0x00200000
-#define TMIO_STAT_CMDTIMEOUT    0x00400000
-#define TMIO_STAT_RXRDY         0x01000000
-#define TMIO_STAT_TXRQ          0x02000000
-#define TMIO_STAT_ILL_FUNC      0x20000000
-#define TMIO_STAT_CMD_BUSY      0x40000000
-#define TMIO_STAT_ILL_ACCESS    0x80000000
-
-/* Define some IRQ masks */
-/* This is the mask used at reset by the chip */
-#define TMIO_MASK_ALL           0x837f031d
-#define TMIO_MASK_READOP  (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND)
-#define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND)
-#define TMIO_MASK_CMD     (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \
-                TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
-#define TMIO_MASK_IRQ     (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD)
-
-
-#define enable_mmc_irqs(host, i) \
-        do { \
-                u32 mask;\
-                mask  = sd_ctrl_read32((host), CTL_IRQ_MASK); \
-                mask &= ~((i) & TMIO_MASK_IRQ); \
-                sd_ctrl_write32((host), CTL_IRQ_MASK, mask); \
-        } while (0)
-
-#define disable_mmc_irqs(host, i) \
-        do { \
-                u32 mask;\
-                mask  = sd_ctrl_read32((host), CTL_IRQ_MASK); \
-                mask |= ((i) & TMIO_MASK_IRQ); \
-                sd_ctrl_write32((host), CTL_IRQ_MASK, mask); \
-        } while (0)
-
-#define ack_mmc_irqs(host, i) \
-        do { \
-                sd_ctrl_write32((host), CTL_STATUS, ~(i)); \
-        } while (0)
-
-
-struct tmio_mmc_host {
-        void __iomem *ctl;
-        unsigned long bus_shift;
-        struct mmc_command      *cmd;
-        struct mmc_request      *mrq;
-        struct mmc_data         *data;
-        struct mmc_host         *mmc;
-        int                     irq;
-
-        /* Callbacks for clock / power control */
-        void (*set_pwr)(struct platform_device *host, int state);
-        void (*set_clk_div)(struct platform_device *host, int state);
-
-        /* pio related stuff */
-        struct scatterlist      *sg_ptr;
-        unsigned int            sg_len;
-        unsigned int            sg_off;
-
-        struct platform_device *pdev;
-
-        /* DMA support */
-        struct dma_chan         *chan_rx;
-        struct dma_chan         *chan_tx;
-        struct tasklet_struct   dma_complete;
-        struct tasklet_struct   dma_issue;
-#ifdef CONFIG_TMIO_MMC_DMA
-        struct dma_async_tx_descriptor *desc;
-        unsigned int            dma_sglen;
-        dma_cookie_t            cookie;
-#endif
-};
-
-#include <linux/io.h>
-
-static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
-{
-        return readw(host->ctl + (addr << host->bus_shift));
-}
-
-static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
-                u16 *buf, int count)
-{
-        readsw(host->ctl + (addr << host->bus_shift), buf, count);
-}
-
-static inline u32 sd_ctrl_read32(struct tmio_mmc_host *host, int addr)
-{
-        return readw(host->ctl + (addr << host->bus_shift)) |
-               readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
-}
-
-static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
-                u16 val)
-{
-        writew(val, host->ctl + (addr << host->bus_shift));
-}
-
-static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
-                u16 *buf, int count)
-{
-        writesw(host->ctl + (addr << host->bus_shift), buf, count);
-}
-
-static inline void sd_ctrl_write32(struct tmio_mmc_host *host, int addr,
-                u32 val)
-{
-        writew(val, host->ctl + (addr << host->bus_shift));
-        writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
-}
-
-#include <linux/scatterlist.h>
-#include <linux/blkdev.h>
-
-static inline void tmio_mmc_init_sg(struct tmio_mmc_host *host,
-        struct mmc_data *data)
-{
-        host->sg_len = data->sg_len;
-        host->sg_ptr = data->sg;
-        host->sg_off = 0;
-}
-
-static inline int tmio_mmc_next_sg(struct tmio_mmc_host *host)
-{
-        host->sg_ptr = sg_next(host->sg_ptr);
-        host->sg_off = 0;
-        return --host->sg_len;
-}
-
-static inline char *tmio_mmc_kmap_atomic(struct scatterlist *sg,
-        unsigned long *flags)
-{
-        local_irq_save(*flags);
-        return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
-}
-
-static inline void tmio_mmc_kunmap_atomic(void *virt,
-        unsigned long *flags)
-{
-        kunmap_atomic(virt, KM_BIO_SRC_IRQ);
-        local_irq_restore(*flags);
-}
-
-#ifdef CONFIG_MMC_DEBUG
-
-#define STATUS_TO_TEXT(a) \
-        do { \
-                if (status & TMIO_STAT_##a) \
-                        printk(#a); \
-        } while (0)
-
-void pr_debug_status(u32 status)
-{
-        printk(KERN_DEBUG "status: %08x = ", status);
-        STATUS_TO_TEXT(CARD_REMOVE);
-        STATUS_TO_TEXT(CARD_INSERT);
-        STATUS_TO_TEXT(SIGSTATE);
-        STATUS_TO_TEXT(WRPROTECT);
-        STATUS_TO_TEXT(CARD_REMOVE_A);
-        STATUS_TO_TEXT(CARD_INSERT_A);
-        STATUS_TO_TEXT(SIGSTATE_A);
-        STATUS_TO_TEXT(CMD_IDX_ERR);
-        STATUS_TO_TEXT(STOPBIT_ERR);
-        STATUS_TO_TEXT(ILL_FUNC);
-        STATUS_TO_TEXT(CMD_BUSY);
-        STATUS_TO_TEXT(CMDRESPEND);
-        STATUS_TO_TEXT(DATAEND);
-        STATUS_TO_TEXT(CRCFAIL);
-        STATUS_TO_TEXT(DATATIMEOUT);
-        STATUS_TO_TEXT(CMDTIMEOUT);
-        STATUS_TO_TEXT(RXOVERFLOW);
-        STATUS_TO_TEXT(TXUNDERRUN);
-        STATUS_TO_TEXT(RXRDY);
-        STATUS_TO_TEXT(TXRQ);
-        STATUS_TO_TEXT(ILL_ACCESS);
-        printk("\n");
-}
-
-#else
-#define pr_debug_status(s)  do { } while (0)
-#endif
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 3fda24a28d2f..ff652c77a0a5 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1944,19 +1944,12 @@ config 68360_ENET
 config FEC
         bool "FEC ethernet controller (of ColdFire and some i.MX CPUs)"
         depends on M523x || M527x || M5272 || M528x || M520x || M532x || \
-                MACH_MX27 || ARCH_MX35 || ARCH_MX25 || ARCH_MX5
+                MACH_MX27 || ARCH_MX35 || ARCH_MX25 || ARCH_MX5 || SOC_IMX28
         select PHYLIB
         help
           Say Y here if you want to use the built-in 10/100 Fast ethernet
           controller on some Motorola ColdFire and Freescale i.MX processors.
 
-config FEC2
-        bool "Second FEC ethernet controller (on some ColdFire CPUs)"
-        depends on FEC
-        help
-          Say Y here if you want to use the second built-in 10/100 Fast
-          ethernet controller on some Motorola ColdFire processors.
-
 config FEC_MPC52xx
         tristate "MPC52xx FEC driver"
         depends on PPC_MPC52xx && PPC_BESTCOMM
diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c
index ce1e5e9d06f6..0b9fc5173aef 100644
--- a/drivers/net/bfin_mac.c
+++ b/drivers/net/bfin_mac.c
@@ -8,6 +8,11 @@
  * Licensed under the GPL-2 or later.
  */
 
+#define DRV_VERSION     "1.1"
+#define DRV_DESC        "Blackfin on-chip Ethernet MAC driver"
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
@@ -41,12 +46,7 @@
 
 #include "bfin_mac.h"
 
-#define DRV_NAME        "bfin_mac"
-#define DRV_VERSION     "1.1"
-#define DRV_AUTHOR      "Bryan Wu, Luke Yang"
-#define DRV_DESC        "Blackfin on-chip Ethernet MAC driver"
-
-MODULE_AUTHOR(DRV_AUTHOR);
+MODULE_AUTHOR("Bryan Wu, Luke Yang");
 MODULE_LICENSE("GPL");
 MODULE_DESCRIPTION(DRV_DESC);
 MODULE_ALIAS("platform:bfin_mac");
@@ -189,8 +189,7 @@ static int desc_list_init(void)
                 /* allocate a new skb for next time receive */
                 new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN);
                 if (!new_skb) {
-                        printk(KERN_NOTICE DRV_NAME
-                               ": init: low on mem - packet dropped\n");
+                        pr_notice("init: low on mem - packet dropped\n");
                         goto init_error;
                 }
                 skb_reserve(new_skb, NET_IP_ALIGN);
@@ -240,7 +239,7 @@ static int desc_list_init(void)
 
 init_error:
         desc_list_free();
-        printk(KERN_ERR DRV_NAME ": kmalloc failed\n");
+        pr_err("kmalloc failed\n");
         return -ENOMEM;
 }
 
@@ -259,8 +258,7 @@ static int bfin_mdio_poll(void)
         while ((bfin_read_EMAC_STAADD()) & STABUSY) {
                 udelay(1);
                 if (timeout_cnt-- < 0) {
-                        printk(KERN_ERR DRV_NAME
-                        ": wait MDC/MDIO transaction to complete timeout\n");
+                        pr_err("wait MDC/MDIO transaction to complete timeout\n");
                         return -ETIMEDOUT;
                 }
         }
@@ -350,9 +348,9 @@ static void bfin_mac_adjust_link(struct net_device *dev)
                                         opmode &= ~RMII_10;
                                         break;
                                 default:
-                                        printk(KERN_WARNING
-                                                "%s: Ack!  Speed (%d) is not 10/100!\n",
-                                                DRV_NAME, phydev->speed);
+                                        netdev_warn(dev,
+                                                "Ack! Speed (%d) is not 10/100!\n",
+                                                phydev->speed);
                                         break;
                                 }
                                 bfin_write_EMAC_OPMODE(opmode);
@@ -417,14 +415,13 @@ static int mii_probe(struct net_device *dev, int phy_mode)
 
         /* now we are supposed to have a proper phydev, to attach to... */
         if (!phydev) {
-                printk(KERN_INFO "%s: Don't found any phy device at all\n",
-                        dev->name);
+                netdev_err(dev, "no phy device found\n");
                 return -ENODEV;
         }
 
         if (phy_mode != PHY_INTERFACE_MODE_RMII &&
                 phy_mode != PHY_INTERFACE_MODE_MII) {
-                printk(KERN_INFO "%s: Invalid phy interface mode\n", dev->name);
+                netdev_err(dev, "invalid phy interface mode\n");
                 return -EINVAL;
         }
 
@@ -432,7 +429,7 @@ static int mii_probe(struct net_device *dev, int phy_mode)
                         0, phy_mode);
 
         if (IS_ERR(phydev)) {
-                printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
+                netdev_err(dev, "could not attach PHY\n");
                 return PTR_ERR(phydev);
         }
 
@@ -453,11 +450,10 @@ static int mii_probe(struct net_device *dev, int phy_mode)
         lp->old_duplex = -1;
         lp->phydev = phydev;
 
-        printk(KERN_INFO "%s: attached PHY driver [%s] "
-               "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)"
-               "@sclk=%dMHz)\n",
-               DRV_NAME, phydev->drv->name, dev_name(&phydev->dev), phydev->irq,
-               MDC_CLK, mdc_div, sclk/1000000);
+        pr_info("attached PHY driver [%s] "
+                "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n",
+                phydev->drv->name, dev_name(&phydev->dev), phydev->irq,
+                MDC_CLK, mdc_div, sclk/1000000);
 
         return 0;
 }
@@ -502,7 +498,7 @@ bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
 static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
                                         struct ethtool_drvinfo *info)
 {
-        strcpy(info->driver, DRV_NAME);
+        strcpy(info->driver, KBUILD_MODNAME);
         strcpy(info->version, DRV_VERSION);
         strcpy(info->fw_version, "N/A");
         strcpy(info->bus_info, dev_name(&dev->dev));
@@ -562,7 +558,7 @@ static const struct ethtool_ops bfin_mac_ethtool_ops = {
 };
 
 /**************************************************************************/
-void setup_system_regs(struct net_device *dev)
+static void setup_system_regs(struct net_device *dev)
 {
         struct bfin_mac_local *lp = netdev_priv(dev);
         int i;
@@ -592,6 +588,10 @@ void setup_system_regs(struct net_device *dev)
 
         bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
 
+        /* Set vlan regs to let 1522 bytes long packets pass through */
+        bfin_write_EMAC_VLAN1(lp->vlan1_mask);
+        bfin_write_EMAC_VLAN2(lp->vlan2_mask);
+
         /* Initialize the TX DMA channel registers */
         bfin_write_DMA2_X_COUNT(0);
         bfin_write_DMA2_X_MODIFY(4);
@@ -827,8 +827,7 @@ static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
                 while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt))
                         udelay(1);
                 if (timeout_cnt == 0)
-                        printk(KERN_ERR DRV_NAME
-                                        ": fails to timestamp the TX packet\n");
+                        netdev_err(netdev, "timestamp the TX packet failed\n");
                 else {
                         struct skb_shared_hwtstamps shhwtstamps;
                         u64 ns;
@@ -1083,8 +1082,7 @@ static void bfin_mac_rx(struct net_device *dev)
          * we which case we simply drop the packet
          */
         if (current_rx_ptr->status.status_word & RX_ERROR_MASK) {
-                printk(KERN_NOTICE DRV_NAME
-                       ": rx: receive error - packet dropped\n");
+                netdev_notice(dev, "rx: receive error - packet dropped\n");
                 dev->stats.rx_dropped++;
                 goto out;
         }
@@ -1094,8 +1092,7 @@ static void bfin_mac_rx(struct net_device *dev)
 
         new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN);
         if (!new_skb) {
-                printk(KERN_NOTICE DRV_NAME
-                       ": rx: low on mem - packet dropped\n");
+                netdev_notice(dev, "rx: low on mem - packet dropped\n");
                 dev->stats.rx_dropped++;
                 goto out;
         }
@@ -1213,7 +1210,7 @@ static int bfin_mac_enable(struct phy_device *phydev)
         int ret;
         u32 opmode;
 
-        pr_debug("%s: %s\n", DRV_NAME, __func__);
+        pr_debug("%s\n", __func__);
 
         /* Set RX DMA */
         bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
@@ -1323,7 +1320,7 @@ static void bfin_mac_set_multicast_list(struct net_device *dev)
         u32 sysctl;
 
         if (dev->flags & IFF_PROMISC) {
-                printk(KERN_INFO "%s: set to promisc mode\n", dev->name);
+                netdev_info(dev, "set promisc mode\n");
                 sysctl = bfin_read_EMAC_OPMODE();
                 sysctl |= PR;
                 bfin_write_EMAC_OPMODE(sysctl);
@@ -1393,7 +1390,7 @@ static int bfin_mac_open(struct net_device *dev)
          * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
          */
         if (!is_valid_ether_addr(dev->dev_addr)) {
-                printk(KERN_WARNING DRV_NAME ": no valid ethernet hw addr\n");
+                netdev_warn(dev, "no valid ethernet hw addr\n");
                 return -EINVAL;
         }
 
@@ -1527,6 +1524,9 @@ static int __devinit bfin_mac_probe(struct platform_device *pdev)
                 goto out_err_mii_probe;
         }
 
+        lp->vlan1_mask = ETH_P_8021Q | mii_bus_data->vlan1_mask;
+        lp->vlan2_mask = ETH_P_8021Q | mii_bus_data->vlan2_mask;
+
         /* Fill in the fields of the device structure with ethernet values. */
         ether_setup(ndev);
 
@@ -1558,7 +1558,7 @@ static int __devinit bfin_mac_probe(struct platform_device *pdev)
         bfin_mac_hwtstamp_init(ndev);
 
         /* now, print out the card info, in a short format.. */
-        dev_info(&pdev->dev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
+        netdev_info(ndev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
 
         return 0;
 
@@ -1650,7 +1650,7 @@ static int __devinit bfin_mii_bus_probe(struct platform_device *pdev)
          * so set the GPIO pins to Ethernet mode
          */
         pin_req = mii_bus_pd->mac_peripherals;
-        rc = peripheral_request_list(pin_req, DRV_NAME);
+        rc = peripheral_request_list(pin_req, KBUILD_MODNAME);
         if (rc) {
                 dev_err(&pdev->dev, "Requesting peripherals failed!\n");
                 return rc;
@@ -1739,7 +1739,7 @@ static struct platform_driver bfin_mac_driver = {
         .resume = bfin_mac_resume,
         .suspend = bfin_mac_suspend,
         .driver = {
-                .name = DRV_NAME,
+                .name = KBUILD_MODNAME,
                 .owner  = THIS_MODULE,
         },
 };
diff --git a/drivers/net/bfin_mac.h b/drivers/net/bfin_mac.h
index aed68bed2365..f8559ac9a403 100644
--- a/drivers/net/bfin_mac.h
+++ b/drivers/net/bfin_mac.h
@@ -17,7 +17,14 @@
 #include <linux/etherdevice.h>
 #include <linux/bfin_mac.h>
 
+/*
+ * Disable hardware checksum for bug #5600 if writeback cache is
+ * enabled. Otherwize, corrupted RX packet will be sent up stack
+ * without error mark.
+ */
+#ifndef CONFIG_BFIN_EXTMEM_WRITEBACK
 #define BFIN_MAC_CSUM_OFFLOAD
+#endif
 
 #define TX_RECLAIM_JIFFIES (HZ / 5)
 
@@ -68,7 +75,6 @@ struct bfin_mac_local {
          */
         struct net_device_stats stats;
 
-        unsigned char Mac[6];   /* MAC address of the board */
         spinlock_t lock;
 
         int wol;                /* Wake On Lan */
@@ -76,6 +82,9 @@ struct bfin_mac_local {
         struct timer_list tx_reclaim_timer;
         struct net_device *ndev;
 
+        /* Data for EMAC_VLAN1 regs */
+        u16 vlan1_mask, vlan2_mask;
+
         /* MII and PHY stuffs */
         int old_link;          /* used by bf537_adjust_link */
         int old_speed;
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 77d6c8d6d86b..6a858a29db56 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -636,6 +636,7 @@ struct bnx2x_common {
 
 #define CHIP_METAL(bp)                  (bp->common.chip_id & 0x00000ff0)
 #define CHIP_BOND_ID(bp)                (bp->common.chip_id & 0x0000000f)
+#define CHIP_PARITY_ENABLED(bp) (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp))
 
         int                     flash_size;
 #define NVRAM_1MB_SIZE                  0x20000 /* 1M bit in bytes */
diff --git a/drivers/net/bnx2x/bnx2x_dump.h b/drivers/net/bnx2x/bnx2x_dump.h
index dc18c25ca9e5..fb3ff7c4d7ca 100644
--- a/drivers/net/bnx2x/bnx2x_dump.h
+++ b/drivers/net/bnx2x/bnx2x_dump.h
@@ -1,10 +1,16 @@
 /* bnx2x_dump.h: Broadcom Everest network driver.
  *
- * Copyright (c) 2009 Broadcom Corporation
+ * Copyright (c) 2011 Broadcom Corporation
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation.
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License version 2, available
+ * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
+ *
+ * Notwithstanding the above, under no circumstances may you combine this
+ * software in any way with any other Broadcom software provided under a
+ * license other than the GPL, without Broadcom's express prior written
+ * consent.
  */
 
 
@@ -17,53 +23,53 @@
 #define BNX2X_DUMP_H
 
 
-struct dump_sign {
-        u32 time_stamp;
-        u32 diag_ver;
-        u32 grc_dump_ver;
-};
 
-#define TSTORM_WAITP_ADDR               0x1b8a80
-#define CSTORM_WAITP_ADDR               0x238a80
-#define XSTORM_WAITP_ADDR               0x2b8a80
-#define USTORM_WAITP_ADDR               0x338a80
-#define TSTORM_CAM_MODE                 0x1b1440
+/*definitions */
+#define XSTORM_WAITP_ADDR    0x2b8a80
+#define TSTORM_WAITP_ADDR    0x1b8a80
+#define USTORM_WAITP_ADDR    0x338a80
+#define CSTORM_WAITP_ADDR    0x238a80
+#define TSTORM_CAM_MODE         0x1B1440
 
-#define RI_E1                           0x1
-#define RI_E1H                          0x2
+#define MAX_TIMER_PENDING      200
+#define TIMER_SCAN_DONT_CARE   0xFF
+#define RI_E1                   0x1
+#define RI_E1H                  0x2
 #define RI_E2                   0x4
-#define RI_ONLINE                       0x100
+#define RI_ONLINE               0x100
 #define RI_PATH0_DUMP           0x200
 #define RI_PATH1_DUMP           0x400
-#define RI_E1_OFFLINE                   (RI_E1)
-#define RI_E1_ONLINE                    (RI_E1 | RI_ONLINE)
-#define RI_E1H_OFFLINE                  (RI_E1H)
-#define RI_E1H_ONLINE                   (RI_E1H | RI_ONLINE)
-#define RI_E2_OFFLINE                   (RI_E2)
-#define RI_E2_ONLINE                    (RI_E2 | RI_ONLINE)
-#define RI_E1E1H_OFFLINE                (RI_E1 | RI_E1H)
-#define RI_E1E1H_ONLINE                 (RI_E1 | RI_E1H | RI_ONLINE)
-#define RI_E1HE2_OFFLINE                (RI_E2 | RI_E1H)
-#define RI_E1HE2_ONLINE                 (RI_E2 | RI_E1H | RI_ONLINE)
-#define RI_E1E2_OFFLINE                 (RI_E2 | RI_E1)
-#define RI_E1E2_ONLINE                  (RI_E2 | RI_E1 | RI_ONLINE)
-#define RI_ALL_OFFLINE                  (RI_E1 | RI_E1H | RI_E2)
-#define RI_ALL_ONLINE                   (RI_E1 | RI_E1H | RI_E2 | RI_ONLINE)
-
-#define MAX_TIMER_PENDING               200
-#define TIMER_SCAN_DONT_CARE            0xFF
+#define RI_E1_OFFLINE           (RI_E1)
+#define RI_E1_ONLINE            (RI_E1 | RI_ONLINE)
+#define RI_E1H_OFFLINE          (RI_E1H)
+#define RI_E1H_ONLINE           (RI_E1H | RI_ONLINE)
+#define RI_E2_OFFLINE           (RI_E2)
+#define RI_E2_ONLINE            (RI_E2 | RI_ONLINE)
+#define RI_E1E1H_OFFLINE        (RI_E1 | RI_E1H)
+#define RI_E1E1H_ONLINE         (RI_E1 | RI_E1H | RI_ONLINE)
+#define RI_E1HE2_OFFLINE        (RI_E2 | RI_E1H)
+#define RI_E1HE2_ONLINE         (RI_E2 | RI_E1H | RI_ONLINE)
+#define RI_E1E2_OFFLINE         (RI_E2 | RI_E1)
+#define RI_E1E2_ONLINE          (RI_E2 | RI_E1 | RI_ONLINE)
+#define RI_ALL_OFFLINE         (RI_E1 | RI_E1H | RI_E2)
+#define RI_ALL_ONLINE          (RI_E1 | RI_E1H | RI_E2 | RI_ONLINE)
 
+struct dump_sign {
+        u32 time_stamp;
+        u32 diag_ver;
+        u32 grc_dump_ver;
+};
 
 struct dump_hdr {
-        u32              hdr_size;      /* in dwords, excluding this field */
-        struct dump_sign dump_sign;
-        u32              xstorm_waitp;
-        u32              tstorm_waitp;
-        u32              ustorm_waitp;
-        u32              cstorm_waitp;
-        u16              info;
-        u8               idle_chk;
-        u8               reserved;
+        u32  hdr_size;  /* in dwords, excluding this field */
+        struct dump_sign        dump_sign;
+        u32  xstorm_waitp;
+        u32  tstorm_waitp;
+        u32  ustorm_waitp;
+        u32  cstorm_waitp;
+        u16  info;
+        u8   idle_chk;
+        u8   reserved;
 };
 
 struct reg_addr {
@@ -80,202 +86,185 @@ struct wreg_addr {
         u16 info;
 };
 
-
-#define REGS_COUNT                      558
+#define REGS_COUNT                      834
 static const struct reg_addr reg_addrs[REGS_COUNT] = {
         { 0x2000, 341, RI_ALL_ONLINE }, { 0x2800, 103, RI_ALL_ONLINE },
         { 0x3000, 287, RI_ALL_ONLINE }, { 0x3800, 331, RI_ALL_ONLINE },
-        { 0x8800, 6, RI_E1_ONLINE }, { 0xa000, 223, RI_ALL_ONLINE },
-        { 0xa388, 1, RI_ALL_ONLINE }, { 0xa398, 1, RI_ALL_ONLINE },
-        { 0xa39c, 7, RI_E1H_ONLINE }, { 0xa3c0, 3, RI_E1H_ONLINE },
-        { 0xa3d0, 1, RI_E1H_ONLINE }, { 0xa3d8, 1, RI_E1H_ONLINE },
-        { 0xa3e0, 1, RI_E1H_ONLINE }, { 0xa3e8, 1, RI_E1H_ONLINE },
-        { 0xa3f0, 1, RI_E1H_ONLINE }, { 0xa3f8, 1, RI_E1H_ONLINE },
-        { 0xa400, 69, RI_ALL_ONLINE }, { 0xa518, 1, RI_ALL_ONLINE },
-        { 0xa520, 1, RI_ALL_ONLINE }, { 0xa528, 1, RI_ALL_ONLINE },
-        { 0xa530, 1, RI_ALL_ONLINE }, { 0xa538, 1, RI_ALL_ONLINE },
-        { 0xa540, 1, RI_ALL_ONLINE }, { 0xa548, 1, RI_ALL_ONLINE },
-        { 0xa550, 1, RI_ALL_ONLINE }, { 0xa558, 1, RI_ALL_ONLINE },
-        { 0xa560, 1, RI_ALL_ONLINE }, { 0xa568, 1, RI_ALL_ONLINE },
-        { 0xa570, 1, RI_ALL_ONLINE }, { 0xa580, 1, RI_ALL_ONLINE },
-        { 0xa590, 1, RI_ALL_ONLINE }, { 0xa5a0, 1, RI_ALL_ONLINE },
-        { 0xa5c0, 1, RI_ALL_ONLINE }, { 0xa5e0, 1, RI_E1H_ONLINE },
-        { 0xa5e8, 1, RI_E1H_ONLINE }, { 0xa5f0, 1, RI_E1H_ONLINE },
-        { 0xa5f8, 10, RI_E1H_ONLINE }, { 0x10000, 236, RI_ALL_ONLINE },
-        { 0x103bc, 1, RI_ALL_ONLINE }, { 0x103cc, 1, RI_ALL_ONLINE },
-        { 0x103dc, 1, RI_ALL_ONLINE }, { 0x10400, 57, RI_ALL_ONLINE },
-        { 0x104e8, 2, RI_ALL_ONLINE }, { 0x104f4, 2, RI_ALL_ONLINE },
-        { 0x10500, 146, RI_ALL_ONLINE }, { 0x10750, 2, RI_ALL_ONLINE },
-        { 0x10760, 2, RI_ALL_ONLINE }, { 0x10770, 2, RI_ALL_ONLINE },
-        { 0x10780, 2, RI_ALL_ONLINE }, { 0x10790, 2, RI_ALL_ONLINE },
-        { 0x107a0, 2, RI_ALL_ONLINE }, { 0x107b0, 2, RI_ALL_ONLINE },
-        { 0x107c0, 2, RI_ALL_ONLINE }, { 0x107d0, 2, RI_ALL_ONLINE },
-        { 0x107e0, 2, RI_ALL_ONLINE }, { 0x10880, 2, RI_ALL_ONLINE },
-        { 0x10900, 2, RI_ALL_ONLINE }, { 0x12000, 1, RI_ALL_ONLINE },
-        { 0x14000, 1, RI_ALL_ONLINE }, { 0x16000, 26, RI_E1H_ONLINE },
-        { 0x16070, 18, RI_E1H_ONLINE }, { 0x160c0, 27, RI_E1H_ONLINE },
-        { 0x16140, 1, RI_E1H_ONLINE }, { 0x16160, 1, RI_E1H_ONLINE },
-        { 0x16180, 2, RI_E1H_ONLINE }, { 0x161c0, 2, RI_E1H_ONLINE },
-        { 0x16204, 5, RI_E1H_ONLINE }, { 0x18000, 1, RI_E1H_ONLINE },
-        { 0x18008, 1, RI_E1H_ONLINE }, { 0x20000, 24, RI_ALL_ONLINE },
-        { 0x20060, 8, RI_ALL_ONLINE }, { 0x20080, 138, RI_ALL_ONLINE },
-        { 0x202b4, 1, RI_ALL_ONLINE }, { 0x202c4, 1, RI_ALL_ONLINE },
-        { 0x20400, 2, RI_ALL_ONLINE }, { 0x2040c, 8, RI_ALL_ONLINE },
-        { 0x2042c, 18, RI_E1H_ONLINE }, { 0x20480, 1, RI_ALL_ONLINE },
-        { 0x20500, 1, RI_ALL_ONLINE }, { 0x20600, 1, RI_ALL_ONLINE },
-        { 0x28000, 1, RI_ALL_ONLINE }, { 0x28004, 8191, RI_ALL_OFFLINE },
-        { 0x30000, 1, RI_ALL_ONLINE }, { 0x30004, 16383, RI_ALL_OFFLINE },
-        { 0x40000, 98, RI_ALL_ONLINE }, { 0x40194, 1, RI_ALL_ONLINE },
-        { 0x401a4, 1, RI_ALL_ONLINE }, { 0x401a8, 11, RI_E1H_ONLINE },
-        { 0x40200, 4, RI_ALL_ONLINE }, { 0x40400, 43, RI_ALL_ONLINE },
-        { 0x404b8, 1, RI_ALL_ONLINE }, { 0x404c8, 1, RI_ALL_ONLINE },
-        { 0x404cc, 3, RI_E1H_ONLINE }, { 0x40500, 2, RI_ALL_ONLINE },
+        { 0x8800, 6, RI_ALL_ONLINE }, { 0x8818, 1, RI_E1HE2_ONLINE },
+        { 0x9000, 164, RI_E2_ONLINE }, { 0x9400, 33, RI_E2_ONLINE },
+        { 0xa000, 27, RI_ALL_ONLINE }, { 0xa06c, 1, RI_E1E1H_ONLINE },
+        { 0xa070, 71, RI_ALL_ONLINE }, { 0xa18c, 4, RI_E1E1H_ONLINE },
+        { 0xa19c, 62, RI_ALL_ONLINE }, { 0xa294, 2, RI_E1E1H_ONLINE },
+        { 0xa29c, 56, RI_ALL_ONLINE }, { 0xa39c, 7, RI_E1HE2_ONLINE },
+        { 0xa3c0, 3, RI_E1HE2_ONLINE }, { 0xa3d0, 1, RI_E1HE2_ONLINE },
+        { 0xa3d8, 1, RI_E1HE2_ONLINE }, { 0xa3e0, 1, RI_E1HE2_ONLINE },
+        { 0xa3e8, 1, RI_E1HE2_ONLINE }, { 0xa3f0, 1, RI_E1HE2_ONLINE },
+        { 0xa3f8, 1, RI_E1HE2_ONLINE }, { 0xa400, 43, RI_ALL_ONLINE },
+        { 0xa4ac, 2, RI_E1E1H_ONLINE }, { 0xa4b4, 1, RI_ALL_ONLINE },
+        { 0xa4b8, 2, RI_E1E1H_ONLINE }, { 0xa4c0, 3, RI_ALL_ONLINE },
+        { 0xa4cc, 5, RI_E1E1H_ONLINE }, { 0xa4e0, 9, RI_ALL_ONLINE },
+        { 0xa504, 1, RI_E1E1H_ONLINE }, { 0xa508, 3, RI_ALL_ONLINE },
+        { 0xa518, 1, RI_ALL_ONLINE }, { 0xa520, 1, RI_ALL_ONLINE },
+        { 0xa528, 1, RI_ALL_ONLINE }, { 0xa530, 1, RI_ALL_ONLINE },
+        { 0xa538, 1, RI_ALL_ONLINE }, { 0xa540, 1, RI_ALL_ONLINE },
+        { 0xa548, 1, RI_E1E1H_ONLINE }, { 0xa550, 1, RI_E1E1H_ONLINE },
+        { 0xa558, 1, RI_E1E1H_ONLINE }, { 0xa560, 1, RI_E1E1H_ONLINE },
+        { 0xa568, 1, RI_E1E1H_ONLINE }, { 0xa570, 1, RI_ALL_ONLINE },
+        { 0xa580, 1, RI_ALL_ONLINE }, { 0xa590, 1, RI_ALL_ONLINE },
+        { 0xa5a0, 1, RI_ALL_ONLINE }, { 0xa5c0, 1, RI_ALL_ONLINE },
+        { 0xa5e0, 1, RI_E1HE2_ONLINE }, { 0xa5e8, 1, RI_E1HE2_ONLINE },
+        { 0xa5f0, 1, RI_E1HE2_ONLINE }, { 0xa5f8, 10, RI_E1HE2_ONLINE },
+        { 0xa620, 111, RI_E2_ONLINE }, { 0xa800, 51, RI_E2_ONLINE },
+        { 0xa8d4, 4, RI_E2_ONLINE }, { 0xa8e8, 1, RI_E2_ONLINE },
+        { 0xa8f0, 1, RI_E2_ONLINE }, { 0x10000, 236, RI_ALL_ONLINE },
+        { 0x10400, 57, RI_ALL_ONLINE }, { 0x104e8, 2, RI_ALL_ONLINE },
+        { 0x104f4, 2, RI_ALL_ONLINE }, { 0x10500, 146, RI_ALL_ONLINE },
+        { 0x10750, 2, RI_ALL_ONLINE }, { 0x10760, 2, RI_ALL_ONLINE },
+        { 0x10770, 2, RI_ALL_ONLINE }, { 0x10780, 2, RI_ALL_ONLINE },
+        { 0x10790, 2, RI_ALL_ONLINE }, { 0x107a0, 2, RI_ALL_ONLINE },
+        { 0x107b0, 2, RI_ALL_ONLINE }, { 0x107c0, 2, RI_ALL_ONLINE },
+        { 0x107d0, 2, RI_ALL_ONLINE }, { 0x107e0, 2, RI_ALL_ONLINE },
+        { 0x10880, 2, RI_ALL_ONLINE }, { 0x10900, 2, RI_ALL_ONLINE },
+        { 0x16000, 26, RI_E1HE2_ONLINE }, { 0x16070, 18, RI_E1HE2_ONLINE },
+        { 0x160c0, 27, RI_E1HE2_ONLINE }, { 0x16140, 1, RI_E1HE2_ONLINE },
+        { 0x16160, 1, RI_E1HE2_ONLINE }, { 0x16180, 2, RI_E1HE2_ONLINE },
+        { 0x161c0, 2, RI_E1HE2_ONLINE }, { 0x16204, 5, RI_E1HE2_ONLINE },
+        { 0x18000, 1, RI_E1HE2_ONLINE }, { 0x18008, 1, RI_E1HE2_ONLINE },
+        { 0x18010, 35, RI_E2_ONLINE }, { 0x180a4, 2, RI_E2_ONLINE },
+        { 0x180c0, 191, RI_E2_ONLINE }, { 0x18440, 1, RI_E2_ONLINE },
+        { 0x18460, 1, RI_E2_ONLINE }, { 0x18480, 2, RI_E2_ONLINE },
+        { 0x184c0, 2, RI_E2_ONLINE }, { 0x18500, 15, RI_E2_ONLINE },
+        { 0x20000, 24, RI_ALL_ONLINE }, { 0x20060, 8, RI_ALL_ONLINE },
+        { 0x20080, 94, RI_ALL_ONLINE }, { 0x201f8, 1, RI_E1E1H_ONLINE },
+        { 0x201fc, 1, RI_ALL_ONLINE }, { 0x20200, 1, RI_E1E1H_ONLINE },
+        { 0x20204, 1, RI_ALL_ONLINE }, { 0x20208, 1, RI_E1E1H_ONLINE },
+        { 0x2020c, 39, RI_ALL_ONLINE }, { 0x202c8, 1, RI_E2_ONLINE },
+        { 0x202d8, 4, RI_E2_ONLINE }, { 0x20400, 2, RI_ALL_ONLINE },
+        { 0x2040c, 8, RI_ALL_ONLINE }, { 0x2042c, 18, RI_E1HE2_ONLINE },
+        { 0x20480, 1, RI_ALL_ONLINE }, { 0x20500, 1, RI_ALL_ONLINE },
+        { 0x20600, 1, RI_ALL_ONLINE }, { 0x28000, 1, RI_ALL_ONLINE },
+        { 0x28004, 8191, RI_ALL_OFFLINE }, { 0x30000, 1, RI_ALL_ONLINE },
+        { 0x30004, 16383, RI_ALL_OFFLINE }, { 0x40000, 98, RI_ALL_ONLINE },
+        { 0x401a8, 8, RI_E1HE2_ONLINE }, { 0x401c8, 1, RI_E1H_ONLINE },
+        { 0x401cc, 2, RI_E1HE2_ONLINE }, { 0x401d4, 2, RI_E2_ONLINE },
+        { 0x40200, 4, RI_ALL_ONLINE }, { 0x40220, 18, RI_E2_ONLINE },
+        { 0x40400, 43, RI_ALL_ONLINE }, { 0x404cc, 3, RI_E1HE2_ONLINE },
+        { 0x404e0, 1, RI_E2_ONLINE }, { 0x40500, 2, RI_ALL_ONLINE },
         { 0x40510, 2, RI_ALL_ONLINE }, { 0x40520, 2, RI_ALL_ONLINE },
         { 0x40530, 2, RI_ALL_ONLINE }, { 0x40540, 2, RI_ALL_ONLINE },
-        { 0x42000, 164, RI_ALL_ONLINE }, { 0x4229c, 1, RI_ALL_ONLINE },
-        { 0x422ac, 1, RI_ALL_ONLINE }, { 0x422bc, 1, RI_ALL_ONLINE },
-        { 0x422d4, 5, RI_E1H_ONLINE }, { 0x42400, 49, RI_ALL_ONLINE },
-        { 0x424c8, 38, RI_ALL_ONLINE }, { 0x42568, 2, RI_ALL_ONLINE },
-        { 0x42800, 1, RI_ALL_ONLINE }, { 0x50000, 20, RI_ALL_ONLINE },
-        { 0x50050, 8, RI_ALL_ONLINE }, { 0x50070, 88, RI_ALL_ONLINE },
-        { 0x501dc, 1, RI_ALL_ONLINE }, { 0x501ec, 1, RI_ALL_ONLINE },
-        { 0x501f0, 4, RI_E1H_ONLINE }, { 0x50200, 2, RI_ALL_ONLINE },
-        { 0x5020c, 7, RI_ALL_ONLINE }, { 0x50228, 6, RI_E1H_ONLINE },
-        { 0x50240, 1, RI_ALL_ONLINE }, { 0x50280, 1, RI_ALL_ONLINE },
+        { 0x40550, 10, RI_E2_ONLINE }, { 0x40610, 2, RI_E2_ONLINE },
+        { 0x42000, 164, RI_ALL_ONLINE }, { 0x422c0, 4, RI_E2_ONLINE },
+        { 0x422d4, 5, RI_E1HE2_ONLINE }, { 0x422e8, 1, RI_E2_ONLINE },
+        { 0x42400, 49, RI_ALL_ONLINE }, { 0x424c8, 38, RI_ALL_ONLINE },
+        { 0x42568, 2, RI_ALL_ONLINE }, { 0x42640, 5, RI_E2_ONLINE },
+        { 0x42800, 1, RI_ALL_ONLINE }, { 0x50000, 1, RI_ALL_ONLINE },
+        { 0x50004, 19, RI_ALL_ONLINE }, { 0x50050, 8, RI_ALL_ONLINE },
+        { 0x50070, 88, RI_ALL_ONLINE }, { 0x501f0, 4, RI_E1HE2_ONLINE },
+        { 0x50200, 2, RI_ALL_ONLINE }, { 0x5020c, 7, RI_ALL_ONLINE },
+        { 0x50228, 6, RI_E1HE2_ONLINE }, { 0x50240, 1, RI_ALL_ONLINE },
+        { 0x50280, 1, RI_ALL_ONLINE }, { 0x50300, 1, RI_E2_ONLINE },
+        { 0x5030c, 1, RI_E2_ONLINE }, { 0x50318, 1, RI_E2_ONLINE },
+        { 0x5031c, 1, RI_E2_ONLINE }, { 0x50320, 2, RI_E2_ONLINE },
         { 0x52000, 1, RI_ALL_ONLINE }, { 0x54000, 1, RI_ALL_ONLINE },
         { 0x54004, 3327, RI_ALL_OFFLINE }, { 0x58000, 1, RI_ALL_ONLINE },
-        { 0x58004, 8191, RI_ALL_OFFLINE }, { 0x60000, 71, RI_ALL_ONLINE },
-        { 0x60128, 1, RI_ALL_ONLINE }, { 0x60138, 1, RI_ALL_ONLINE },
-        { 0x6013c, 24, RI_E1H_ONLINE }, { 0x60200, 1, RI_ALL_ONLINE },
+        { 0x58004, 8191, RI_E1E1H_OFFLINE }, { 0x60000, 26, RI_ALL_ONLINE },
+        { 0x60068, 8, RI_E1E1H_ONLINE }, { 0x60088, 12, RI_ALL_ONLINE },
+        { 0x600b8, 9, RI_E1E1H_ONLINE }, { 0x600dc, 1, RI_ALL_ONLINE },
+        { 0x600e0, 5, RI_E1E1H_ONLINE }, { 0x600f4, 1, RI_ALL_ONLINE },
+        { 0x600f8, 1, RI_E1E1H_ONLINE }, { 0x600fc, 8, RI_ALL_ONLINE },
+        { 0x6013c, 24, RI_E1H_ONLINE }, { 0x6019c, 2, RI_E2_ONLINE },
+        { 0x601ac, 18, RI_E2_ONLINE }, { 0x60200, 1, RI_ALL_ONLINE },
+        { 0x60204, 2, RI_ALL_OFFLINE }, { 0x60210, 13, RI_E2_ONLINE },
         { 0x61000, 1, RI_ALL_ONLINE }, { 0x61004, 511, RI_ALL_OFFLINE },
-        { 0x70000, 8, RI_ALL_ONLINE }, { 0x70020, 21496, RI_ALL_OFFLINE },
-        { 0x85000, 3, RI_ALL_ONLINE }, { 0x8500c, 4, RI_ALL_OFFLINE },
-        { 0x8501c, 7, RI_ALL_ONLINE }, { 0x85038, 4, RI_ALL_OFFLINE },
-        { 0x85048, 1, RI_ALL_ONLINE }, { 0x8504c, 109, RI_ALL_OFFLINE },
-        { 0x85200, 32, RI_ALL_ONLINE }, { 0x85280, 11104, RI_ALL_OFFLINE },
-        { 0xa0000, 16384, RI_ALL_ONLINE }, { 0xb0000, 16384, RI_E1H_ONLINE },
-        { 0xc1000, 7, RI_ALL_ONLINE }, { 0xc1028, 1, RI_ALL_ONLINE },
-        { 0xc1038, 1, RI_ALL_ONLINE }, { 0xc1800, 2, RI_ALL_ONLINE },
-        { 0xc2000, 164, RI_ALL_ONLINE }, { 0xc229c, 1, RI_ALL_ONLINE },
-        { 0xc22ac, 1, RI_ALL_ONLINE }, { 0xc22bc, 1, RI_ALL_ONLINE },
+        { 0x70000, 8, RI_ALL_ONLINE }, { 0x70020, 8184, RI_ALL_OFFLINE },
+        { 0x85000, 3, RI_ALL_ONLINE }, { 0x8501c, 7, RI_ALL_ONLINE },
+        { 0x85048, 1, RI_ALL_ONLINE }, { 0x85200, 32, RI_ALL_ONLINE },
+        { 0xc1000, 7, RI_ALL_ONLINE }, { 0xc103c, 2, RI_E2_ONLINE },
+        { 0xc1800, 2, RI_ALL_ONLINE }, { 0xc2000, 164, RI_ALL_ONLINE },
+        { 0xc22c0, 5, RI_E2_ONLINE }, { 0xc22d8, 4, RI_E2_ONLINE },
         { 0xc2400, 49, RI_ALL_ONLINE }, { 0xc24c8, 38, RI_ALL_ONLINE },
         { 0xc2568, 2, RI_ALL_ONLINE }, { 0xc2600, 1, RI_ALL_ONLINE },
-        { 0xc4000, 165, RI_ALL_ONLINE }, { 0xc42a0, 1, RI_ALL_ONLINE },
-        { 0xc42b0, 1, RI_ALL_ONLINE }, { 0xc42c0, 1, RI_ALL_ONLINE },
-        { 0xc42e0, 7, RI_E1H_ONLINE }, { 0xc4400, 51, RI_ALL_ONLINE },
-        { 0xc44d0, 38, RI_ALL_ONLINE }, { 0xc4570, 2, RI_ALL_ONLINE },
+        { 0xc4000, 165, RI_ALL_ONLINE }, { 0xc42d8, 2, RI_E2_ONLINE },
+        { 0xc42e0, 7, RI_E1HE2_ONLINE }, { 0xc42fc, 1, RI_E2_ONLINE },
+        { 0xc4400, 51, RI_ALL_ONLINE }, { 0xc44d0, 38, RI_ALL_ONLINE },
+        { 0xc4570, 2, RI_ALL_ONLINE }, { 0xc4578, 5, RI_E2_ONLINE },
         { 0xc4600, 1, RI_ALL_ONLINE }, { 0xd0000, 19, RI_ALL_ONLINE },
         { 0xd004c, 8, RI_ALL_ONLINE }, { 0xd006c, 91, RI_ALL_ONLINE },
-        { 0xd01e4, 1, RI_ALL_ONLINE }, { 0xd01f4, 1, RI_ALL_ONLINE },
-        { 0xd0200, 2, RI_ALL_ONLINE }, { 0xd020c, 7, RI_ALL_ONLINE },
-        { 0xd0228, 18, RI_E1H_ONLINE }, { 0xd0280, 1, RI_ALL_ONLINE },
-        { 0xd0300, 1, RI_ALL_ONLINE }, { 0xd0400, 1, RI_ALL_ONLINE },
-        { 0xd4000, 1, RI_ALL_ONLINE }, { 0xd4004, 2559, RI_ALL_OFFLINE },
-        { 0xd8000, 1, RI_ALL_ONLINE }, { 0xd8004, 8191, RI_ALL_OFFLINE },
-        { 0xe0000, 21, RI_ALL_ONLINE }, { 0xe0054, 8, RI_ALL_ONLINE },
-        { 0xe0074, 85, RI_ALL_ONLINE }, { 0xe01d4, 1, RI_ALL_ONLINE },
-        { 0xe01e4, 1, RI_ALL_ONLINE }, { 0xe0200, 2, RI_ALL_ONLINE },
-        { 0xe020c, 8, RI_ALL_ONLINE }, { 0xe022c, 18, RI_E1H_ONLINE },
+        { 0xd01fc, 1, RI_E2_ONLINE }, { 0xd0200, 2, RI_ALL_ONLINE },
+        { 0xd020c, 7, RI_ALL_ONLINE }, { 0xd0228, 18, RI_E1HE2_ONLINE },
+        { 0xd0280, 1, RI_ALL_ONLINE }, { 0xd0300, 1, RI_ALL_ONLINE },
+        { 0xd0400, 1, RI_ALL_ONLINE }, { 0xd4000, 1, RI_ALL_ONLINE },
+        { 0xd4004, 2559, RI_ALL_OFFLINE }, { 0xd8000, 1, RI_ALL_ONLINE },
+        { 0xd8004, 8191, RI_ALL_OFFLINE }, { 0xe0000, 21, RI_ALL_ONLINE },
+        { 0xe0054, 8, RI_ALL_ONLINE }, { 0xe0074, 49, RI_ALL_ONLINE },
+        { 0xe0138, 1, RI_E1E1H_ONLINE }, { 0xe013c, 35, RI_ALL_ONLINE },
+        { 0xe01f4, 2, RI_E2_ONLINE }, { 0xe0200, 2, RI_ALL_ONLINE },
+        { 0xe020c, 8, RI_ALL_ONLINE }, { 0xe022c, 18, RI_E1HE2_ONLINE },
         { 0xe0280, 1, RI_ALL_ONLINE }, { 0xe0300, 1, RI_ALL_ONLINE },
         { 0xe1000, 1, RI_ALL_ONLINE }, { 0xe2000, 1, RI_ALL_ONLINE },
         { 0xe2004, 2047, RI_ALL_OFFLINE }, { 0xf0000, 1, RI_ALL_ONLINE },
         { 0xf0004, 16383, RI_ALL_OFFLINE }, { 0x101000, 12, RI_ALL_ONLINE },
-        { 0x10103c, 1, RI_ALL_ONLINE }, { 0x10104c, 1, RI_ALL_ONLINE },
-        { 0x101050, 1, RI_E1H_ONLINE }, { 0x101100, 1, RI_ALL_ONLINE },
-        { 0x101800, 8, RI_ALL_ONLINE }, { 0x102000, 18, RI_ALL_ONLINE },
-        { 0x102054, 1, RI_ALL_ONLINE }, { 0x102064, 1, RI_ALL_ONLINE },
+        { 0x101050, 1, RI_E1HE2_ONLINE }, { 0x101054, 3, RI_E2_ONLINE },
+        { 0x101100, 1, RI_ALL_ONLINE }, { 0x101800, 8, RI_ALL_ONLINE },
+        { 0x102000, 18, RI_ALL_ONLINE }, { 0x102068, 6, RI_E2_ONLINE },
         { 0x102080, 17, RI_ALL_ONLINE }, { 0x1020c8, 8, RI_E1H_ONLINE },
-        { 0x102400, 1, RI_ALL_ONLINE }, { 0x103000, 26, RI_ALL_ONLINE },
-        { 0x103074, 1, RI_ALL_ONLINE }, { 0x103084, 1, RI_ALL_ONLINE },
-        { 0x103094, 1, RI_ALL_ONLINE }, { 0x103098, 5, RI_E1H_ONLINE },
+        { 0x1020e8, 9, RI_E2_ONLINE }, { 0x102400, 1, RI_ALL_ONLINE },
+        { 0x103000, 26, RI_ALL_ONLINE }, { 0x103098, 5, RI_E1HE2_ONLINE },
+        { 0x1030ac, 10, RI_E2_ONLINE }, { 0x1030d8, 8, RI_E2_ONLINE },
+        { 0x103400, 1, RI_E2_ONLINE }, { 0x103404, 135, RI_E2_OFFLINE },
         { 0x103800, 8, RI_ALL_ONLINE }, { 0x104000, 63, RI_ALL_ONLINE },
-        { 0x104108, 1, RI_ALL_ONLINE }, { 0x104118, 1, RI_ALL_ONLINE },
-        { 0x104200, 17, RI_ALL_ONLINE }, { 0x104400, 64, RI_ALL_ONLINE },
-        { 0x104500, 192, RI_ALL_OFFLINE }, { 0x104800, 64, RI_ALL_ONLINE },
-        { 0x104900, 192, RI_ALL_OFFLINE }, { 0x105000, 7, RI_ALL_ONLINE },
-        { 0x10501c, 1, RI_ALL_OFFLINE }, { 0x105020, 3, RI_ALL_ONLINE },
-        { 0x10502c, 1, RI_ALL_OFFLINE }, { 0x105030, 3, RI_ALL_ONLINE },
-        { 0x10503c, 1, RI_ALL_OFFLINE }, { 0x105040, 3, RI_ALL_ONLINE },
-        { 0x10504c, 1, RI_ALL_OFFLINE }, { 0x105050, 3, RI_ALL_ONLINE },
-        { 0x10505c, 1, RI_ALL_OFFLINE }, { 0x105060, 3, RI_ALL_ONLINE },
-        { 0x10506c, 1, RI_ALL_OFFLINE }, { 0x105070, 3, RI_ALL_ONLINE },
-        { 0x10507c, 1, RI_ALL_OFFLINE }, { 0x105080, 3, RI_ALL_ONLINE },
-        { 0x10508c, 1, RI_ALL_OFFLINE }, { 0x105090, 3, RI_ALL_ONLINE },
-        { 0x10509c, 1, RI_ALL_OFFLINE }, { 0x1050a0, 3, RI_ALL_ONLINE },
-        { 0x1050ac, 1, RI_ALL_OFFLINE }, { 0x1050b0, 3, RI_ALL_ONLINE },
-        { 0x1050bc, 1, RI_ALL_OFFLINE }, { 0x1050c0, 3, RI_ALL_ONLINE },
-        { 0x1050cc, 1, RI_ALL_OFFLINE }, { 0x1050d0, 3, RI_ALL_ONLINE },
-        { 0x1050dc, 1, RI_ALL_OFFLINE }, { 0x1050e0, 3, RI_ALL_ONLINE },
-        { 0x1050ec, 1, RI_ALL_OFFLINE }, { 0x1050f0, 3, RI_ALL_ONLINE },
-        { 0x1050fc, 1, RI_ALL_OFFLINE }, { 0x105100, 3, RI_ALL_ONLINE },
-        { 0x10510c, 1, RI_ALL_OFFLINE }, { 0x105110, 3, RI_ALL_ONLINE },
-        { 0x10511c, 1, RI_ALL_OFFLINE }, { 0x105120, 3, RI_ALL_ONLINE },
-        { 0x10512c, 1, RI_ALL_OFFLINE }, { 0x105130, 3, RI_ALL_ONLINE },
-        { 0x10513c, 1, RI_ALL_OFFLINE }, { 0x105140, 3, RI_ALL_ONLINE },
-        { 0x10514c, 1, RI_ALL_OFFLINE }, { 0x105150, 3, RI_ALL_ONLINE },
-        { 0x10515c, 1, RI_ALL_OFFLINE }, { 0x105160, 3, RI_ALL_ONLINE },
-        { 0x10516c, 1, RI_ALL_OFFLINE }, { 0x105170, 3, RI_ALL_ONLINE },
-        { 0x10517c, 1, RI_ALL_OFFLINE }, { 0x105180, 3, RI_ALL_ONLINE },
-        { 0x10518c, 1, RI_ALL_OFFLINE }, { 0x105190, 3, RI_ALL_ONLINE },
-        { 0x10519c, 1, RI_ALL_OFFLINE }, { 0x1051a0, 3, RI_ALL_ONLINE },
-        { 0x1051ac, 1, RI_ALL_OFFLINE }, { 0x1051b0, 3, RI_ALL_ONLINE },
-        { 0x1051bc, 1, RI_ALL_OFFLINE }, { 0x1051c0, 3, RI_ALL_ONLINE },
-        { 0x1051cc, 1, RI_ALL_OFFLINE }, { 0x1051d0, 3, RI_ALL_ONLINE },
-        { 0x1051dc, 1, RI_ALL_OFFLINE }, { 0x1051e0, 3, RI_ALL_ONLINE },
-        { 0x1051ec, 1, RI_ALL_OFFLINE }, { 0x1051f0, 3, RI_ALL_ONLINE },
-        { 0x1051fc, 1, RI_ALL_OFFLINE }, { 0x105200, 3, RI_ALL_ONLINE },
-        { 0x10520c, 1, RI_ALL_OFFLINE }, { 0x105210, 3, RI_ALL_ONLINE },
-        { 0x10521c, 1, RI_ALL_OFFLINE }, { 0x105220, 3, RI_ALL_ONLINE },
-        { 0x10522c, 1, RI_ALL_OFFLINE }, { 0x105230, 3, RI_ALL_ONLINE },
-        { 0x10523c, 1, RI_ALL_OFFLINE }, { 0x105240, 3, RI_ALL_ONLINE },
-        { 0x10524c, 1, RI_ALL_OFFLINE }, { 0x105250, 3, RI_ALL_ONLINE },
-        { 0x10525c, 1, RI_ALL_OFFLINE }, { 0x105260, 3, RI_ALL_ONLINE },
-        { 0x10526c, 1, RI_ALL_OFFLINE }, { 0x105270, 3, RI_ALL_ONLINE },
-        { 0x10527c, 1, RI_ALL_OFFLINE }, { 0x105280, 3, RI_ALL_ONLINE },
-        { 0x10528c, 1, RI_ALL_OFFLINE }, { 0x105290, 3, RI_ALL_ONLINE },
-        { 0x10529c, 1, RI_ALL_OFFLINE }, { 0x1052a0, 3, RI_ALL_ONLINE },
-        { 0x1052ac, 1, RI_ALL_OFFLINE }, { 0x1052b0, 3, RI_ALL_ONLINE },
-        { 0x1052bc, 1, RI_ALL_OFFLINE }, { 0x1052c0, 3, RI_ALL_ONLINE },
-        { 0x1052cc, 1, RI_ALL_OFFLINE }, { 0x1052d0, 3, RI_ALL_ONLINE },
-        { 0x1052dc, 1, RI_ALL_OFFLINE }, { 0x1052e0, 3, RI_ALL_ONLINE },
-        { 0x1052ec, 1, RI_ALL_OFFLINE }, { 0x1052f0, 3, RI_ALL_ONLINE },
-        { 0x1052fc, 1, RI_ALL_OFFLINE }, { 0x105300, 3, RI_ALL_ONLINE },
-        { 0x10530c, 1, RI_ALL_OFFLINE }, { 0x105310, 3, RI_ALL_ONLINE },
-        { 0x10531c, 1, RI_ALL_OFFLINE }, { 0x105320, 3, RI_ALL_ONLINE },
-        { 0x10532c, 1, RI_ALL_OFFLINE }, { 0x105330, 3, RI_ALL_ONLINE },
-        { 0x10533c, 1, RI_ALL_OFFLINE }, { 0x105340, 3, RI_ALL_ONLINE },
-        { 0x10534c, 1, RI_ALL_OFFLINE }, { 0x105350, 3, RI_ALL_ONLINE },
-        { 0x10535c, 1, RI_ALL_OFFLINE }, { 0x105360, 3, RI_ALL_ONLINE },
-        { 0x10536c, 1, RI_ALL_OFFLINE }, { 0x105370, 3, RI_ALL_ONLINE },
-        { 0x10537c, 1, RI_ALL_OFFLINE }, { 0x105380, 3, RI_ALL_ONLINE },
-        { 0x10538c, 1, RI_ALL_OFFLINE }, { 0x105390, 3, RI_ALL_ONLINE },
-        { 0x10539c, 1, RI_ALL_OFFLINE }, { 0x1053a0, 3, RI_ALL_ONLINE },
-        { 0x1053ac, 1, RI_ALL_OFFLINE }, { 0x1053b0, 3, RI_ALL_ONLINE },
-        { 0x1053bc, 1, RI_ALL_OFFLINE }, { 0x1053c0, 3, RI_ALL_ONLINE },
-        { 0x1053cc, 1, RI_ALL_OFFLINE }, { 0x1053d0, 3, RI_ALL_ONLINE },
-        { 0x1053dc, 1, RI_ALL_OFFLINE }, { 0x1053e0, 3, RI_ALL_ONLINE },
-        { 0x1053ec, 1, RI_ALL_OFFLINE }, { 0x1053f0, 3, RI_ALL_ONLINE },
-        { 0x1053fc, 769, RI_ALL_OFFLINE }, { 0x108000, 33, RI_ALL_ONLINE },
-        { 0x108090, 1, RI_ALL_ONLINE }, { 0x1080a0, 1, RI_ALL_ONLINE },
-        { 0x1080ac, 5, RI_E1H_ONLINE }, { 0x108100, 5, RI_ALL_ONLINE },
-        { 0x108120, 5, RI_ALL_ONLINE }, { 0x108200, 74, RI_ALL_ONLINE },
-        { 0x108400, 74, RI_ALL_ONLINE }, { 0x108800, 152, RI_ALL_ONLINE },
-        { 0x109000, 1, RI_ALL_ONLINE }, { 0x120000, 347, RI_ALL_ONLINE },
-        { 0x120578, 1, RI_ALL_ONLINE }, { 0x120588, 1, RI_ALL_ONLINE },
-        { 0x120598, 1, RI_ALL_ONLINE }, { 0x12059c, 23, RI_E1H_ONLINE },
-        { 0x120614, 1, RI_E1H_ONLINE }, { 0x12061c, 30, RI_E1H_ONLINE },
-        { 0x12080c, 65, RI_ALL_ONLINE }, { 0x120a00, 2, RI_ALL_ONLINE },
-        { 0x122000, 2, RI_ALL_ONLINE }, { 0x128000, 2, RI_E1H_ONLINE },
-        { 0x140000, 114, RI_ALL_ONLINE }, { 0x1401d4, 1, RI_ALL_ONLINE },
-        { 0x1401e4, 1, RI_ALL_ONLINE }, { 0x140200, 6, RI_ALL_ONLINE },
-        { 0x144000, 4, RI_ALL_ONLINE }, { 0x148000, 4, RI_ALL_ONLINE },
-        { 0x14c000, 4, RI_ALL_ONLINE }, { 0x150000, 4, RI_ALL_ONLINE },
-        { 0x154000, 4, RI_ALL_ONLINE }, { 0x158000, 4, RI_ALL_ONLINE },
-        { 0x15c000, 7, RI_E1H_ONLINE }, { 0x161000, 7, RI_ALL_ONLINE },
-        { 0x161028, 1, RI_ALL_ONLINE }, { 0x161038, 1, RI_ALL_ONLINE },
-        { 0x161800, 2, RI_ALL_ONLINE }, { 0x164000, 60, RI_ALL_ONLINE },
-        { 0x1640fc, 1, RI_ALL_ONLINE }, { 0x16410c, 1, RI_ALL_ONLINE },
-        { 0x164110, 2, RI_E1H_ONLINE }, { 0x164200, 1, RI_ALL_ONLINE },
+        { 0x10411c, 16, RI_E2_ONLINE }, { 0x104200, 17, RI_ALL_ONLINE },
+        { 0x104400, 64, RI_ALL_ONLINE }, { 0x104500, 192, RI_ALL_OFFLINE },
+        { 0x104800, 64, RI_ALL_ONLINE }, { 0x104900, 192, RI_ALL_OFFLINE },
+        { 0x105000, 256, RI_ALL_ONLINE }, { 0x105400, 768, RI_ALL_OFFLINE },
+        { 0x107000, 7, RI_E2_ONLINE }, { 0x108000, 33, RI_E1E1H_ONLINE },
+        { 0x1080ac, 5, RI_E1H_ONLINE }, { 0x108100, 5, RI_E1E1H_ONLINE },
+        { 0x108120, 5, RI_E1E1H_ONLINE }, { 0x108200, 74, RI_E1E1H_ONLINE },
+        { 0x108400, 74, RI_E1E1H_ONLINE }, { 0x108800, 152, RI_E1E1H_ONLINE },
+        { 0x110000, 111, RI_E2_ONLINE }, { 0x110200, 4, RI_E2_ONLINE },
+        { 0x120000, 2, RI_ALL_ONLINE }, { 0x120008, 4, RI_ALL_ONLINE },
+        { 0x120018, 3, RI_ALL_ONLINE }, { 0x120024, 4, RI_ALL_ONLINE },
+        { 0x120034, 3, RI_ALL_ONLINE }, { 0x120040, 4, RI_ALL_ONLINE },
+        { 0x120050, 3, RI_ALL_ONLINE }, { 0x12005c, 4, RI_ALL_ONLINE },
+        { 0x12006c, 3, RI_ALL_ONLINE }, { 0x120078, 4, RI_ALL_ONLINE },
+        { 0x120088, 3, RI_ALL_ONLINE }, { 0x120094, 4, RI_ALL_ONLINE },
+        { 0x1200a4, 3, RI_ALL_ONLINE }, { 0x1200b0, 4, RI_ALL_ONLINE },
+        { 0x1200c0, 3, RI_ALL_ONLINE }, { 0x1200cc, 4, RI_ALL_ONLINE },
+        { 0x1200dc, 3, RI_ALL_ONLINE }, { 0x1200e8, 4, RI_ALL_ONLINE },
+        { 0x1200f8, 3, RI_ALL_ONLINE }, { 0x120104, 4, RI_ALL_ONLINE },
+        { 0x120114, 1, RI_ALL_ONLINE }, { 0x120118, 22, RI_ALL_ONLINE },
+        { 0x120170, 2, RI_E1E1H_ONLINE }, { 0x120178, 243, RI_ALL_ONLINE },
+        { 0x120544, 4, RI_E1E1H_ONLINE }, { 0x120554, 7, RI_ALL_ONLINE },
+        { 0x12059c, 6, RI_E1HE2_ONLINE }, { 0x1205b4, 1, RI_E1HE2_ONLINE },
+        { 0x1205b8, 16, RI_E1HE2_ONLINE }, { 0x1205f8, 4, RI_E2_ONLINE },
+        { 0x120618, 1, RI_E2_ONLINE }, { 0x12061c, 20, RI_E1HE2_ONLINE },
+        { 0x12066c, 11, RI_E1HE2_ONLINE }, { 0x120698, 5, RI_E2_ONLINE },
+        { 0x1206b0, 76, RI_E2_ONLINE }, { 0x1207fc, 1, RI_E2_ONLINE },
+        { 0x120808, 66, RI_ALL_ONLINE }, { 0x120910, 7, RI_E2_ONLINE },
+        { 0x120930, 9, RI_E2_ONLINE }, { 0x120a00, 2, RI_ALL_ONLINE },
+        { 0x122000, 2, RI_ALL_ONLINE }, { 0x122008, 2046, RI_E1_OFFLINE },
+        { 0x128000, 2, RI_E1HE2_ONLINE }, { 0x128008, 6142, RI_E1HE2_OFFLINE },
+        { 0x130000, 35, RI_E2_ONLINE }, { 0x130100, 29, RI_E2_ONLINE },
+        { 0x130180, 1, RI_E2_ONLINE }, { 0x130200, 1, RI_E2_ONLINE },
+        { 0x130280, 1, RI_E2_ONLINE }, { 0x130300, 5, RI_E2_ONLINE },
+        { 0x130380, 1, RI_E2_ONLINE }, { 0x130400, 1, RI_E2_ONLINE },
+        { 0x130480, 5, RI_E2_ONLINE }, { 0x130800, 72, RI_E2_ONLINE },
+        { 0x131000, 136, RI_E2_ONLINE }, { 0x132000, 148, RI_E2_ONLINE },
+        { 0x134000, 544, RI_E2_ONLINE }, { 0x140000, 64, RI_ALL_ONLINE },
+        { 0x140100, 5, RI_E1E1H_ONLINE }, { 0x140114, 45, RI_ALL_ONLINE },
+        { 0x140200, 6, RI_ALL_ONLINE }, { 0x140220, 4, RI_E2_ONLINE },
+        { 0x140240, 4, RI_E2_ONLINE }, { 0x140260, 4, RI_E2_ONLINE },
+        { 0x140280, 4, RI_E2_ONLINE }, { 0x1402a0, 4, RI_E2_ONLINE },
+        { 0x1402c0, 4, RI_E2_ONLINE }, { 0x1402e0, 13, RI_E2_ONLINE },
+        { 0x144000, 4, RI_E1E1H_ONLINE }, { 0x148000, 4, RI_E1E1H_ONLINE },
+        { 0x14c000, 4, RI_E1E1H_ONLINE }, { 0x150000, 4, RI_E1E1H_ONLINE },
+        { 0x154000, 4, RI_E1E1H_ONLINE }, { 0x158000, 4, RI_E1E1H_ONLINE },
+        { 0x15c000, 2, RI_E1HE2_ONLINE }, { 0x15c008, 5, RI_E1H_ONLINE },
+        { 0x15c020, 27, RI_E2_ONLINE }, { 0x15c090, 13, RI_E2_ONLINE },
+        { 0x15c0c8, 34, RI_E2_ONLINE }, { 0x161000, 7, RI_ALL_ONLINE },
+        { 0x16103c, 2, RI_E2_ONLINE }, { 0x161800, 2, RI_ALL_ONLINE },
+        { 0x164000, 60, RI_ALL_ONLINE }, { 0x164110, 2, RI_E1HE2_ONLINE },
+        { 0x164118, 15, RI_E2_ONLINE }, { 0x164200, 1, RI_ALL_ONLINE },
         { 0x164208, 1, RI_ALL_ONLINE }, { 0x164210, 1, RI_ALL_ONLINE },
         { 0x164218, 1, RI_ALL_ONLINE }, { 0x164220, 1, RI_ALL_ONLINE },
         { 0x164228, 1, RI_ALL_ONLINE }, { 0x164230, 1, RI_ALL_ONLINE },
@@ -284,169 +273,298 @@ static const struct reg_addr reg_addrs[REGS_COUNT] = {
         { 0x164258, 1, RI_ALL_ONLINE }, { 0x164260, 1, RI_ALL_ONLINE },
         { 0x164270, 2, RI_ALL_ONLINE }, { 0x164280, 2, RI_ALL_ONLINE },
         { 0x164800, 2, RI_ALL_ONLINE }, { 0x165000, 2, RI_ALL_ONLINE },
-        { 0x166000, 164, RI_ALL_ONLINE }, { 0x16629c, 1, RI_ALL_ONLINE },
-        { 0x1662ac, 1, RI_ALL_ONLINE }, { 0x1662bc, 1, RI_ALL_ONLINE },
+        { 0x166000, 164, RI_ALL_ONLINE }, { 0x1662cc, 7, RI_E2_ONLINE },
         { 0x166400, 49, RI_ALL_ONLINE }, { 0x1664c8, 38, RI_ALL_ONLINE },
-        { 0x166568, 2, RI_ALL_ONLINE }, { 0x166800, 1, RI_ALL_ONLINE },
-        { 0x168000, 270, RI_ALL_ONLINE }, { 0x168444, 1, RI_ALL_ONLINE },
-        { 0x168454, 1, RI_ALL_ONLINE }, { 0x168800, 19, RI_ALL_ONLINE },
-        { 0x168900, 1, RI_ALL_ONLINE }, { 0x168a00, 128, RI_ALL_ONLINE },
-        { 0x16a000, 1, RI_ALL_ONLINE }, { 0x16a004, 1535, RI_ALL_OFFLINE },
-        { 0x16c000, 1, RI_ALL_ONLINE }, { 0x16c004, 1535, RI_ALL_OFFLINE },
-        { 0x16e000, 16, RI_E1H_ONLINE }, { 0x16e100, 1, RI_E1H_ONLINE },
-        { 0x16e200, 2, RI_E1H_ONLINE }, { 0x16e400, 183, RI_E1H_ONLINE },
-        { 0x170000, 93, RI_ALL_ONLINE }, { 0x170180, 1, RI_ALL_ONLINE },
-        { 0x170190, 1, RI_ALL_ONLINE }, { 0x170200, 4, RI_ALL_ONLINE },
-        { 0x170214, 1, RI_ALL_ONLINE }, { 0x178000, 1, RI_ALL_ONLINE },
-        { 0x180000, 61, RI_ALL_ONLINE }, { 0x180100, 1, RI_ALL_ONLINE },
-        { 0x180110, 1, RI_ALL_ONLINE }, { 0x180120, 1, RI_ALL_ONLINE },
-        { 0x180130, 1, RI_ALL_ONLINE }, { 0x18013c, 2, RI_E1H_ONLINE },
-        { 0x180200, 58, RI_ALL_ONLINE }, { 0x180340, 4, RI_ALL_ONLINE },
-        { 0x180400, 1, RI_ALL_ONLINE }, { 0x180404, 255, RI_ALL_OFFLINE },
+        { 0x166568, 2, RI_ALL_ONLINE }, { 0x166570, 5, RI_E2_ONLINE },
+        { 0x166800, 1, RI_ALL_ONLINE }, { 0x168000, 137, RI_ALL_ONLINE },
+        { 0x168224, 2, RI_E1E1H_ONLINE }, { 0x16822c, 29, RI_ALL_ONLINE },
+        { 0x1682a0, 12, RI_E1E1H_ONLINE }, { 0x1682d0, 12, RI_ALL_ONLINE },
+        { 0x168300, 2, RI_E1E1H_ONLINE }, { 0x168308, 68, RI_ALL_ONLINE },
+        { 0x168418, 2, RI_E1E1H_ONLINE }, { 0x168420, 6, RI_ALL_ONLINE },
+        { 0x168800, 19, RI_ALL_ONLINE }, { 0x168900, 1, RI_ALL_ONLINE },
+        { 0x168a00, 128, RI_ALL_ONLINE }, { 0x16a000, 1, RI_ALL_ONLINE },
+        { 0x16a004, 1535, RI_ALL_OFFLINE }, { 0x16c000, 1, RI_ALL_ONLINE },
+        { 0x16c004, 1535, RI_ALL_OFFLINE }, { 0x16e000, 16, RI_E1H_ONLINE },
+        { 0x16e040, 8, RI_E2_ONLINE }, { 0x16e100, 1, RI_E1H_ONLINE },
+        { 0x16e200, 2, RI_E1H_ONLINE }, { 0x16e400, 161, RI_E1H_ONLINE },
+        { 0x16e684, 2, RI_E1HE2_ONLINE }, { 0x16e68c, 12, RI_E1H_ONLINE },
+        { 0x16e6bc, 4, RI_E1HE2_ONLINE }, { 0x16e6cc, 4, RI_E1H_ONLINE },
+        { 0x16e6e0, 12, RI_E2_ONLINE }, { 0x16e768, 17, RI_E2_ONLINE },
+        { 0x170000, 24, RI_ALL_ONLINE }, { 0x170060, 4, RI_E1E1H_ONLINE },
+        { 0x170070, 65, RI_ALL_ONLINE }, { 0x170194, 11, RI_E2_ONLINE },
+        { 0x1701c4, 1, RI_E2_ONLINE }, { 0x1701cc, 7, RI_E2_ONLINE },
+        { 0x1701ec, 1, RI_E2_ONLINE }, { 0x1701f4, 1, RI_E2_ONLINE },
+        { 0x170200, 4, RI_ALL_ONLINE }, { 0x170214, 1, RI_ALL_ONLINE },
+        { 0x170218, 77, RI_E2_ONLINE }, { 0x170400, 64, RI_E2_ONLINE },
+        { 0x178000, 1, RI_ALL_ONLINE }, { 0x180000, 61, RI_ALL_ONLINE },
+        { 0x18013c, 2, RI_E1HE2_ONLINE }, { 0x180200, 58, RI_ALL_ONLINE },
+        { 0x180340, 4, RI_ALL_ONLINE }, { 0x180380, 1, RI_E2_ONLINE },
+        { 0x180388, 1, RI_E2_ONLINE }, { 0x180390, 1, RI_E2_ONLINE },
+        { 0x180398, 1, RI_E2_ONLINE }, { 0x1803a0, 5, RI_E2_ONLINE },
+        { 0x180400, 1, RI_ALL_ONLINE }, { 0x180404, 255, RI_E1E1H_OFFLINE },
         { 0x181000, 4, RI_ALL_ONLINE }, { 0x181010, 1020, RI_ALL_OFFLINE },
-        { 0x1a0000, 1, RI_ALL_ONLINE }, { 0x1a0004, 1023, RI_ALL_OFFLINE },
-        { 0x1a1000, 1, RI_ALL_ONLINE }, { 0x1a1004, 4607, RI_ALL_OFFLINE },
-        { 0x1a5800, 2560, RI_E1H_OFFLINE }, { 0x1a8000, 64, RI_ALL_OFFLINE },
-        { 0x1a8100, 1984, RI_E1H_OFFLINE }, { 0x1aa000, 1, RI_E1H_ONLINE },
-        { 0x1aa004, 6655, RI_E1H_OFFLINE }, { 0x1b1800, 128, RI_ALL_OFFLINE },
-        { 0x1b1c00, 128, RI_ALL_OFFLINE }, { 0x1b2000, 1, RI_ALL_OFFLINE },
-        { 0x1b2400, 64, RI_E1H_OFFLINE }, { 0x1b8200, 1, RI_ALL_ONLINE },
+        { 0x1a0000, 1, RI_ALL_ONLINE }, { 0x1a0004, 5631, RI_ALL_OFFLINE },
+        { 0x1a5800, 2560, RI_E1HE2_OFFLINE }, { 0x1a8000, 1, RI_ALL_ONLINE },
+        { 0x1a8004, 8191, RI_E1HE2_OFFLINE }, { 0x1b0000, 1, RI_ALL_ONLINE },
+        { 0x1b0004, 15, RI_E1H_OFFLINE }, { 0x1b0040, 1, RI_E1HE2_ONLINE },
+        { 0x1b0044, 239, RI_E1H_OFFLINE }, { 0x1b0400, 1, RI_ALL_ONLINE },
+        { 0x1b0404, 255, RI_E1H_OFFLINE }, { 0x1b0800, 1, RI_ALL_ONLINE },
+        { 0x1b0840, 1, RI_E1HE2_ONLINE }, { 0x1b0c00, 1, RI_ALL_ONLINE },
+        { 0x1b1000, 1, RI_ALL_ONLINE }, { 0x1b1040, 1, RI_E1HE2_ONLINE },
+        { 0x1b1400, 1, RI_ALL_ONLINE }, { 0x1b1440, 1, RI_E1HE2_ONLINE },
+        { 0x1b1480, 1, RI_E1HE2_ONLINE }, { 0x1b14c0, 1, RI_E1HE2_ONLINE },
+        { 0x1b1800, 128, RI_ALL_OFFLINE }, { 0x1b1c00, 128, RI_ALL_OFFLINE },
+        { 0x1b2000, 1, RI_ALL_ONLINE }, { 0x1b2400, 1, RI_E1HE2_ONLINE },
+        { 0x1b2404, 5631, RI_E2_OFFLINE }, { 0x1b8000, 1, RI_ALL_ONLINE },
+        { 0x1b8040, 1, RI_ALL_ONLINE }, { 0x1b8080, 1, RI_ALL_ONLINE },
+        { 0x1b80c0, 1, RI_ALL_ONLINE }, { 0x1b8100, 1, RI_ALL_ONLINE },
+        { 0x1b8140, 1, RI_ALL_ONLINE }, { 0x1b8180, 1, RI_ALL_ONLINE },
+        { 0x1b81c0, 1, RI_ALL_ONLINE }, { 0x1b8200, 1, RI_ALL_ONLINE },
         { 0x1b8240, 1, RI_ALL_ONLINE }, { 0x1b8280, 1, RI_ALL_ONLINE },
-        { 0x1b82c0, 1, RI_ALL_ONLINE }, { 0x1b8a00, 1, RI_ALL_ONLINE },
-        { 0x1b8a80, 1, RI_ALL_ONLINE }, { 0x1c0000, 2, RI_ALL_ONLINE },
-        { 0x200000, 65, RI_ALL_ONLINE }, { 0x200110, 1, RI_ALL_ONLINE },
-        { 0x200120, 1, RI_ALL_ONLINE }, { 0x200130, 1, RI_ALL_ONLINE },
-        { 0x200140, 1, RI_ALL_ONLINE }, { 0x20014c, 2, RI_E1H_ONLINE },
-        { 0x200200, 58, RI_ALL_ONLINE }, { 0x200340, 4, RI_ALL_ONLINE },
-        { 0x200400, 1, RI_ALL_ONLINE }, { 0x200404, 255, RI_ALL_OFFLINE },
-        { 0x202000, 4, RI_ALL_ONLINE }, { 0x202010, 2044, RI_ALL_OFFLINE },
-        { 0x220000, 1, RI_ALL_ONLINE }, { 0x220004, 1023, RI_ALL_OFFLINE },
-        { 0x221000, 1, RI_ALL_ONLINE }, { 0x221004, 4607, RI_ALL_OFFLINE },
-        { 0x225800, 1536, RI_E1H_OFFLINE }, { 0x227000, 1, RI_E1H_ONLINE },
-        { 0x227004, 1023, RI_E1H_OFFLINE }, { 0x228000, 64, RI_ALL_OFFLINE },
-        { 0x228100, 8640, RI_E1H_OFFLINE }, { 0x231800, 128, RI_ALL_OFFLINE },
-        { 0x231c00, 128, RI_ALL_OFFLINE }, { 0x232000, 1, RI_ALL_OFFLINE },
-        { 0x232400, 64, RI_E1H_OFFLINE }, { 0x238200, 1, RI_ALL_ONLINE },
-        { 0x238240, 1, RI_ALL_ONLINE }, { 0x238280, 1, RI_ALL_ONLINE },
-        { 0x2382c0, 1, RI_ALL_ONLINE }, { 0x238a00, 1, RI_ALL_ONLINE },
-        { 0x238a80, 1, RI_ALL_ONLINE }, { 0x240000, 2, RI_ALL_ONLINE },
-        { 0x280000, 65, RI_ALL_ONLINE }, { 0x280110, 1, RI_ALL_ONLINE },
-        { 0x280120, 1, RI_ALL_ONLINE }, { 0x280130, 1, RI_ALL_ONLINE },
-        { 0x280140, 1, RI_ALL_ONLINE }, { 0x28014c, 2, RI_E1H_ONLINE },
-        { 0x280200, 58, RI_ALL_ONLINE }, { 0x280340, 4, RI_ALL_ONLINE },
-        { 0x280400, 1, RI_ALL_ONLINE }, { 0x280404, 255, RI_ALL_OFFLINE },
-        { 0x282000, 4, RI_ALL_ONLINE }, { 0x282010, 2044, RI_ALL_OFFLINE },
-        { 0x2a0000, 1, RI_ALL_ONLINE }, { 0x2a0004, 1023, RI_ALL_OFFLINE },
-        { 0x2a1000, 1, RI_ALL_ONLINE }, { 0x2a1004, 4607, RI_ALL_OFFLINE },
-        { 0x2a5800, 2560, RI_E1H_OFFLINE }, { 0x2a8000, 64, RI_ALL_OFFLINE },
-        { 0x2a8100, 960, RI_E1H_OFFLINE }, { 0x2a9000, 1, RI_E1H_ONLINE },
-        { 0x2a9004, 7679, RI_E1H_OFFLINE }, { 0x2b1800, 128, RI_ALL_OFFLINE },
-        { 0x2b1c00, 128, RI_ALL_OFFLINE }, { 0x2b2000, 1, RI_ALL_OFFLINE },
-        { 0x2b2400, 64, RI_E1H_OFFLINE }, { 0x2b8200, 1, RI_ALL_ONLINE },
-        { 0x2b8240, 1, RI_ALL_ONLINE }, { 0x2b8280, 1, RI_ALL_ONLINE },
-        { 0x2b82c0, 1, RI_ALL_ONLINE }, { 0x2b8a00, 1, RI_ALL_ONLINE },
-        { 0x2b8a80, 1, RI_ALL_ONLINE }, { 0x2c0000, 2, RI_ALL_ONLINE },
-        { 0x300000, 65, RI_ALL_ONLINE }, { 0x300110, 1, RI_ALL_ONLINE },
-        { 0x300120, 1, RI_ALL_ONLINE }, { 0x300130, 1, RI_ALL_ONLINE },
-        { 0x300140, 1, RI_ALL_ONLINE }, { 0x30014c, 2, RI_E1H_ONLINE },
+        { 0x1b82c0, 1, RI_ALL_ONLINE }, { 0x1b8300, 1, RI_ALL_ONLINE },
+        { 0x1b8340, 1, RI_ALL_ONLINE }, { 0x1b8380, 1, RI_ALL_ONLINE },
+        { 0x1b83c0, 1, RI_ALL_ONLINE }, { 0x1b8400, 1, RI_ALL_ONLINE },
+        { 0x1b8440, 1, RI_ALL_ONLINE }, { 0x1b8480, 1, RI_ALL_ONLINE },
+        { 0x1b84c0, 1, RI_ALL_ONLINE }, { 0x1b8500, 1, RI_ALL_ONLINE },
+        { 0x1b8540, 1, RI_ALL_ONLINE }, { 0x1b8580, 1, RI_ALL_ONLINE },
+        { 0x1b85c0, 19, RI_E2_ONLINE }, { 0x1b8800, 1, RI_ALL_ONLINE },
+        { 0x1b8840, 1, RI_ALL_ONLINE }, { 0x1b8880, 1, RI_ALL_ONLINE },
+        { 0x1b88c0, 1, RI_ALL_ONLINE }, { 0x1b8900, 1, RI_ALL_ONLINE },
+        { 0x1b8940, 1, RI_ALL_ONLINE }, { 0x1b8980, 1, RI_ALL_ONLINE },
+        { 0x1b89c0, 1, RI_ALL_ONLINE }, { 0x1b8a00, 1, RI_ALL_ONLINE },
+        { 0x1b8a40, 1, RI_ALL_ONLINE }, { 0x1b8a80, 1, RI_ALL_ONLINE },
+        { 0x1b8ac0, 1, RI_ALL_ONLINE }, { 0x1b8b00, 1, RI_ALL_ONLINE },
+        { 0x1b8b40, 1, RI_ALL_ONLINE }, { 0x1b8b80, 1, RI_ALL_ONLINE },
+        { 0x1b8bc0, 1, RI_ALL_ONLINE }, { 0x1b8c00, 1, RI_ALL_ONLINE },
+        { 0x1b8c40, 1, RI_ALL_ONLINE }, { 0x1b8c80, 1, RI_ALL_ONLINE },
+        { 0x1b8cc0, 1, RI_ALL_ONLINE }, { 0x1b8cc4, 1, RI_E2_ONLINE },
+        { 0x1b8d00, 1, RI_ALL_ONLINE }, { 0x1b8d40, 1, RI_ALL_ONLINE },
+        { 0x1b8d80, 1, RI_ALL_ONLINE }, { 0x1b8dc0, 1, RI_ALL_ONLINE },
+        { 0x1b8e00, 1, RI_ALL_ONLINE }, { 0x1b8e40, 1, RI_ALL_ONLINE },
+        { 0x1b8e80, 1, RI_ALL_ONLINE }, { 0x1b8e84, 1, RI_E2_ONLINE },
+        { 0x1b8ec0, 1, RI_E1HE2_ONLINE }, { 0x1b8f00, 1, RI_E1HE2_ONLINE },
+        { 0x1b8f40, 1, RI_E1HE2_ONLINE }, { 0x1b8f80, 1, RI_E1HE2_ONLINE },
+        { 0x1b8fc0, 1, RI_E1HE2_ONLINE }, { 0x1b8fc4, 2, RI_E2_ONLINE },
+        { 0x1b8fd0, 6, RI_E2_ONLINE }, { 0x1b9000, 1, RI_E2_ONLINE },
+        { 0x1b9040, 3, RI_E2_ONLINE }, { 0x1b9400, 14, RI_E2_ONLINE },
+        { 0x1b943c, 19, RI_E2_ONLINE }, { 0x1b9490, 10, RI_E2_ONLINE },
+        { 0x1c0000, 2, RI_ALL_ONLINE }, { 0x200000, 65, RI_ALL_ONLINE },
+        { 0x20014c, 2, RI_E1HE2_ONLINE }, { 0x200200, 58, RI_ALL_ONLINE },
+        { 0x200340, 4, RI_ALL_ONLINE }, { 0x200380, 1, RI_E2_ONLINE },
+        { 0x200388, 1, RI_E2_ONLINE }, { 0x200390, 1, RI_E2_ONLINE },
+        { 0x200398, 1, RI_E2_ONLINE }, { 0x2003a0, 1, RI_E2_ONLINE },
+        { 0x2003a8, 2, RI_E2_ONLINE }, { 0x200400, 1, RI_ALL_ONLINE },
+        { 0x200404, 255, RI_E1E1H_OFFLINE }, { 0x202000, 4, RI_ALL_ONLINE },
+        { 0x202010, 2044, RI_ALL_OFFLINE }, { 0x220000, 1, RI_ALL_ONLINE },
+        { 0x220004, 5631, RI_ALL_OFFLINE }, { 0x225800, 2560, RI_E1HE2_OFFLINE},
+        { 0x228000, 1, RI_ALL_ONLINE }, { 0x228004, 8191, RI_E1HE2_OFFLINE },
+        { 0x230000, 1, RI_ALL_ONLINE }, { 0x230004, 15, RI_E1H_OFFLINE },
+        { 0x230040, 1, RI_E1HE2_ONLINE }, { 0x230044, 239, RI_E1H_OFFLINE },
+        { 0x230400, 1, RI_ALL_ONLINE }, { 0x230404, 255, RI_E1H_OFFLINE },
+        { 0x230800, 1, RI_ALL_ONLINE }, { 0x230840, 1, RI_E1HE2_ONLINE },
+        { 0x230c00, 1, RI_ALL_ONLINE }, { 0x231000, 1, RI_ALL_ONLINE },
+        { 0x231040, 1, RI_E1HE2_ONLINE }, { 0x231400, 1, RI_ALL_ONLINE },
+        { 0x231440, 1, RI_E1HE2_ONLINE }, { 0x231480, 1, RI_E1HE2_ONLINE },
+        { 0x2314c0, 1, RI_E1HE2_ONLINE }, { 0x231800, 128, RI_ALL_OFFLINE },
+        { 0x231c00, 128, RI_ALL_OFFLINE }, { 0x232000, 1, RI_ALL_ONLINE },
+        { 0x232400, 1, RI_E1HE2_ONLINE }, { 0x232404, 5631, RI_E2_OFFLINE },
+        { 0x238000, 1, RI_ALL_ONLINE }, { 0x238040, 1, RI_ALL_ONLINE },
+        { 0x238080, 1, RI_ALL_ONLINE }, { 0x2380c0, 1, RI_ALL_ONLINE },
+        { 0x238100, 1, RI_ALL_ONLINE }, { 0x238140, 1, RI_ALL_ONLINE },
+        { 0x238180, 1, RI_ALL_ONLINE }, { 0x2381c0, 1, RI_ALL_ONLINE },
+        { 0x238200, 1, RI_ALL_ONLINE }, { 0x238240, 1, RI_ALL_ONLINE },
+        { 0x238280, 1, RI_ALL_ONLINE }, { 0x2382c0, 1, RI_ALL_ONLINE },
+        { 0x238300, 1, RI_ALL_ONLINE }, { 0x238340, 1, RI_ALL_ONLINE },
+        { 0x238380, 1, RI_ALL_ONLINE }, { 0x2383c0, 1, RI_ALL_ONLINE },
+        { 0x238400, 1, RI_ALL_ONLINE }, { 0x238440, 1, RI_ALL_ONLINE },
+        { 0x238480, 1, RI_ALL_ONLINE }, { 0x2384c0, 1, RI_ALL_ONLINE },
+        { 0x238500, 1, RI_ALL_ONLINE }, { 0x238540, 1, RI_ALL_ONLINE },
+        { 0x238580, 1, RI_ALL_ONLINE }, { 0x2385c0, 19, RI_E2_ONLINE },
+        { 0x238800, 1, RI_ALL_ONLINE }, { 0x238840, 1, RI_ALL_ONLINE },
+        { 0x238880, 1, RI_ALL_ONLINE }, { 0x2388c0, 1, RI_ALL_ONLINE },
+        { 0x238900, 1, RI_ALL_ONLINE }, { 0x238940, 1, RI_ALL_ONLINE },
+        { 0x238980, 1, RI_ALL_ONLINE }, { 0x2389c0, 1, RI_ALL_ONLINE },
+        { 0x238a00, 1, RI_ALL_ONLINE }, { 0x238a40, 1, RI_ALL_ONLINE },
+        { 0x238a80, 1, RI_ALL_ONLINE }, { 0x238ac0, 1, RI_ALL_ONLINE },
+        { 0x238b00, 1, RI_ALL_ONLINE }, { 0x238b40, 1, RI_ALL_ONLINE },
+        { 0x238b80, 1, RI_ALL_ONLINE }, { 0x238bc0, 1, RI_ALL_ONLINE },
+        { 0x238c00, 1, RI_ALL_ONLINE }, { 0x238c40, 1, RI_ALL_ONLINE },
+        { 0x238c80, 1, RI_ALL_ONLINE }, { 0x238cc0, 1, RI_ALL_ONLINE },
+        { 0x238cc4, 1, RI_E2_ONLINE }, { 0x238d00, 1, RI_ALL_ONLINE },
+        { 0x238d40, 1, RI_ALL_ONLINE }, { 0x238d80, 1, RI_ALL_ONLINE },
+        { 0x238dc0, 1, RI_ALL_ONLINE }, { 0x238e00, 1, RI_ALL_ONLINE },
+        { 0x238e40, 1, RI_ALL_ONLINE }, { 0x238e80, 1, RI_ALL_ONLINE },
+        { 0x238e84, 1, RI_E2_ONLINE }, { 0x238ec0, 1, RI_E1HE2_ONLINE },
+        { 0x238f00, 1, RI_E1HE2_ONLINE }, { 0x238f40, 1, RI_E1HE2_ONLINE },
+        { 0x238f80, 1, RI_E1HE2_ONLINE }, { 0x238fc0, 1, RI_E1HE2_ONLINE },
+        { 0x238fc4, 2, RI_E2_ONLINE }, { 0x238fd0, 6, RI_E2_ONLINE },
+        { 0x239000, 1, RI_E2_ONLINE }, { 0x239040, 3, RI_E2_ONLINE },
+        { 0x240000, 2, RI_ALL_ONLINE }, { 0x280000, 65, RI_ALL_ONLINE },
+        { 0x28014c, 2, RI_E1HE2_ONLINE }, { 0x280200, 58, RI_ALL_ONLINE },
+        { 0x280340, 4, RI_ALL_ONLINE }, { 0x280380, 1, RI_E2_ONLINE },
+        { 0x280388, 1, RI_E2_ONLINE }, { 0x280390, 1, RI_E2_ONLINE },
+        { 0x280398, 1, RI_E2_ONLINE }, { 0x2803a0, 1, RI_E2_ONLINE },
+        { 0x2803a8, 2, RI_E2_ONLINE }, { 0x280400, 1, RI_ALL_ONLINE },
+        { 0x280404, 255, RI_E1E1H_OFFLINE }, { 0x282000, 4, RI_ALL_ONLINE },
+        { 0x282010, 2044, RI_ALL_OFFLINE }, { 0x2a0000, 1, RI_ALL_ONLINE },
+        { 0x2a0004, 5631, RI_ALL_OFFLINE }, { 0x2a5800, 2560, RI_E1HE2_OFFLINE},
+        { 0x2a8000, 1, RI_ALL_ONLINE }, { 0x2a8004, 8191, RI_E1HE2_OFFLINE },
+        { 0x2b0000, 1, RI_ALL_ONLINE }, { 0x2b0004, 15, RI_E1H_OFFLINE },
+        { 0x2b0040, 1, RI_E1HE2_ONLINE }, { 0x2b0044, 239, RI_E1H_OFFLINE },
+        { 0x2b0400, 1, RI_ALL_ONLINE }, { 0x2b0404, 255, RI_E1H_OFFLINE },
+        { 0x2b0800, 1, RI_ALL_ONLINE }, { 0x2b0840, 1, RI_E1HE2_ONLINE },
+        { 0x2b0c00, 1, RI_ALL_ONLINE }, { 0x2b1000, 1, RI_ALL_ONLINE },
+        { 0x2b1040, 1, RI_E1HE2_ONLINE }, { 0x2b1400, 1, RI_ALL_ONLINE },
+        { 0x2b1440, 1, RI_E1HE2_ONLINE }, { 0x2b1480, 1, RI_E1HE2_ONLINE },
+        { 0x2b14c0, 1, RI_E1HE2_ONLINE }, { 0x2b1800, 128, RI_ALL_OFFLINE },
+        { 0x2b1c00, 128, RI_ALL_OFFLINE }, { 0x2b2000, 1, RI_ALL_ONLINE },
+        { 0x2b2400, 1, RI_E1HE2_ONLINE }, { 0x2b2404, 5631, RI_E2_OFFLINE },
+        { 0x2b8000, 1, RI_ALL_ONLINE }, { 0x2b8040, 1, RI_ALL_ONLINE },
+        { 0x2b8080, 1, RI_ALL_ONLINE }, { 0x2b80c0, 1, RI_ALL_ONLINE },
+        { 0x2b8100, 1, RI_ALL_ONLINE }, { 0x2b8140, 1, RI_ALL_ONLINE },
+        { 0x2b8180, 1, RI_ALL_ONLINE }, { 0x2b81c0, 1, RI_ALL_ONLINE },
+        { 0x2b8200, 1, RI_ALL_ONLINE }, { 0x2b8240, 1, RI_ALL_ONLINE },
+        { 0x2b8280, 1, RI_ALL_ONLINE }, { 0x2b82c0, 1, RI_ALL_ONLINE },
+        { 0x2b8300, 1, RI_ALL_ONLINE }, { 0x2b8340, 1, RI_ALL_ONLINE },
+        { 0x2b8380, 1, RI_ALL_ONLINE }, { 0x2b83c0, 1, RI_ALL_ONLINE },
+        { 0x2b8400, 1, RI_ALL_ONLINE }, { 0x2b8440, 1, RI_ALL_ONLINE },
+        { 0x2b8480, 1, RI_ALL_ONLINE }, { 0x2b84c0, 1, RI_ALL_ONLINE },
+        { 0x2b8500, 1, RI_ALL_ONLINE }, { 0x2b8540, 1, RI_ALL_ONLINE },
+        { 0x2b8580, 1, RI_ALL_ONLINE }, { 0x2b85c0, 19, RI_E2_ONLINE },
+        { 0x2b8800, 1, RI_ALL_ONLINE }, { 0x2b8840, 1, RI_ALL_ONLINE },
+        { 0x2b8880, 1, RI_ALL_ONLINE }, { 0x2b88c0, 1, RI_ALL_ONLINE },
+        { 0x2b8900, 1, RI_ALL_ONLINE }, { 0x2b8940, 1, RI_ALL_ONLINE },
+        { 0x2b8980, 1, RI_ALL_ONLINE }, { 0x2b89c0, 1, RI_ALL_ONLINE },
+        { 0x2b8a00, 1, RI_ALL_ONLINE }, { 0x2b8a40, 1, RI_ALL_ONLINE },
+        { 0x2b8a80, 1, RI_ALL_ONLINE }, { 0x2b8ac0, 1, RI_ALL_ONLINE },
+        { 0x2b8b00, 1, RI_ALL_ONLINE }, { 0x2b8b40, 1, RI_ALL_ONLINE },
+        { 0x2b8b80, 1, RI_ALL_ONLINE }, { 0x2b8bc0, 1, RI_ALL_ONLINE },
+        { 0x2b8c00, 1, RI_ALL_ONLINE }, { 0x2b8c40, 1, RI_ALL_ONLINE },
+        { 0x2b8c80, 1, RI_ALL_ONLINE }, { 0x2b8cc0, 1, RI_ALL_ONLINE },
+        { 0x2b8cc4, 1, RI_E2_ONLINE }, { 0x2b8d00, 1, RI_ALL_ONLINE },
+        { 0x2b8d40, 1, RI_ALL_ONLINE }, { 0x2b8d80, 1, RI_ALL_ONLINE },
+        { 0x2b8dc0, 1, RI_ALL_ONLINE }, { 0x2b8e00, 1, RI_ALL_ONLINE },
+        { 0x2b8e40, 1, RI_ALL_ONLINE }, { 0x2b8e80, 1, RI_ALL_ONLINE },
+        { 0x2b8e84, 1, RI_E2_ONLINE }, { 0x2b8ec0, 1, RI_E1HE2_ONLINE },
+        { 0x2b8f00, 1, RI_E1HE2_ONLINE }, { 0x2b8f40, 1, RI_E1HE2_ONLINE },
+        { 0x2b8f80, 1, RI_E1HE2_ONLINE }, { 0x2b8fc0, 1, RI_E1HE2_ONLINE },
+        { 0x2b8fc4, 2, RI_E2_ONLINE }, { 0x2b8fd0, 6, RI_E2_ONLINE },
+        { 0x2b9000, 1, RI_E2_ONLINE }, { 0x2b9040, 3, RI_E2_ONLINE },
+        { 0x2b9400, 14, RI_E2_ONLINE }, { 0x2b943c, 19, RI_E2_ONLINE },
+        { 0x2b9490, 10, RI_E2_ONLINE }, { 0x2c0000, 2, RI_ALL_ONLINE },
+        { 0x300000, 65, RI_ALL_ONLINE }, { 0x30014c, 2, RI_E1HE2_ONLINE },
         { 0x300200, 58, RI_ALL_ONLINE }, { 0x300340, 4, RI_ALL_ONLINE },
-        { 0x300400, 1, RI_ALL_ONLINE }, { 0x300404, 255, RI_ALL_OFFLINE },
+        { 0x300380, 1, RI_E2_ONLINE }, { 0x300388, 1, RI_E2_ONLINE },
+        { 0x300390, 1, RI_E2_ONLINE }, { 0x300398, 1, RI_E2_ONLINE },
+        { 0x3003a0, 1, RI_E2_ONLINE }, { 0x3003a8, 2, RI_E2_ONLINE },
+        { 0x300400, 1, RI_ALL_ONLINE }, { 0x300404, 255, RI_E1E1H_OFFLINE },
         { 0x302000, 4, RI_ALL_ONLINE }, { 0x302010, 2044, RI_ALL_OFFLINE },
-        { 0x320000, 1, RI_ALL_ONLINE }, { 0x320004, 1023, RI_ALL_OFFLINE },
-        { 0x321000, 1, RI_ALL_ONLINE }, { 0x321004, 4607, RI_ALL_OFFLINE },
-        { 0x325800, 2560, RI_E1H_OFFLINE }, { 0x328000, 64, RI_ALL_OFFLINE },
-        { 0x328100, 536, RI_E1H_OFFLINE }, { 0x328960, 1, RI_E1H_ONLINE },
-        { 0x328964, 8103, RI_E1H_OFFLINE }, { 0x331800, 128, RI_ALL_OFFLINE },
-        { 0x331c00, 128, RI_ALL_OFFLINE }, { 0x332000, 1, RI_ALL_OFFLINE },
-        { 0x332400, 64, RI_E1H_OFFLINE }, { 0x338200, 1, RI_ALL_ONLINE },
+        { 0x320000, 1, RI_ALL_ONLINE }, { 0x320004, 5631, RI_ALL_OFFLINE },
+        { 0x325800, 2560, RI_E1HE2_OFFLINE }, { 0x328000, 1, RI_ALL_ONLINE },
+        { 0x328004, 8191, RI_E1HE2_OFFLINE }, { 0x330000, 1, RI_ALL_ONLINE },
+        { 0x330004, 15, RI_E1H_OFFLINE }, { 0x330040, 1, RI_E1HE2_ONLINE },
+        { 0x330044, 239, RI_E1H_OFFLINE }, { 0x330400, 1, RI_ALL_ONLINE },
+        { 0x330404, 255, RI_E1H_OFFLINE }, { 0x330800, 1, RI_ALL_ONLINE },
+        { 0x330840, 1, RI_E1HE2_ONLINE }, { 0x330c00, 1, RI_ALL_ONLINE },
+        { 0x331000, 1, RI_ALL_ONLINE }, { 0x331040, 1, RI_E1HE2_ONLINE },
+        { 0x331400, 1, RI_ALL_ONLINE }, { 0x331440, 1, RI_E1HE2_ONLINE },
+        { 0x331480, 1, RI_E1HE2_ONLINE }, { 0x3314c0, 1, RI_E1HE2_ONLINE },
+        { 0x331800, 128, RI_ALL_OFFLINE }, { 0x331c00, 128, RI_ALL_OFFLINE },
+        { 0x332000, 1, RI_ALL_ONLINE }, { 0x332400, 1, RI_E1HE2_ONLINE },
+        { 0x332404, 5631, RI_E2_OFFLINE }, { 0x338000, 1, RI_ALL_ONLINE },
+        { 0x338040, 1, RI_ALL_ONLINE }, { 0x338080, 1, RI_ALL_ONLINE },
+        { 0x3380c0, 1, RI_ALL_ONLINE }, { 0x338100, 1, RI_ALL_ONLINE },
+        { 0x338140, 1, RI_ALL_ONLINE }, { 0x338180, 1, RI_ALL_ONLINE },
+        { 0x3381c0, 1, RI_ALL_ONLINE }, { 0x338200, 1, RI_ALL_ONLINE },
         { 0x338240, 1, RI_ALL_ONLINE }, { 0x338280, 1, RI_ALL_ONLINE },
-        { 0x3382c0, 1, RI_ALL_ONLINE }, { 0x338a00, 1, RI_ALL_ONLINE },
-        { 0x338a80, 1, RI_ALL_ONLINE }, { 0x340000, 2, RI_ALL_ONLINE }
+        { 0x3382c0, 1, RI_ALL_ONLINE }, { 0x338300, 1, RI_ALL_ONLINE },
+        { 0x338340, 1, RI_ALL_ONLINE }, { 0x338380, 1, RI_ALL_ONLINE },
+        { 0x3383c0, 1, RI_ALL_ONLINE }, { 0x338400, 1, RI_ALL_ONLINE },
+        { 0x338440, 1, RI_ALL_ONLINE }, { 0x338480, 1, RI_ALL_ONLINE },
+        { 0x3384c0, 1, RI_ALL_ONLINE }, { 0x338500, 1, RI_ALL_ONLINE },
+        { 0x338540, 1, RI_ALL_ONLINE }, { 0x338580, 1, RI_ALL_ONLINE },
+        { 0x3385c0, 19, RI_E2_ONLINE }, { 0x338800, 1, RI_ALL_ONLINE },
+        { 0x338840, 1, RI_ALL_ONLINE }, { 0x338880, 1, RI_ALL_ONLINE },
+        { 0x3388c0, 1, RI_ALL_ONLINE }, { 0x338900, 1, RI_ALL_ONLINE },
+        { 0x338940, 1, RI_ALL_ONLINE }, { 0x338980, 1, RI_ALL_ONLINE },
+        { 0x3389c0, 1, RI_ALL_ONLINE }, { 0x338a00, 1, RI_ALL_ONLINE },
+        { 0x338a40, 1, RI_ALL_ONLINE }, { 0x338a80, 1, RI_ALL_ONLINE },
+        { 0x338ac0, 1, RI_ALL_ONLINE }, { 0x338b00, 1, RI_ALL_ONLINE },
+        { 0x338b40, 1, RI_ALL_ONLINE }, { 0x338b80, 1, RI_ALL_ONLINE },
+        { 0x338bc0, 1, RI_ALL_ONLINE }, { 0x338c00, 1, RI_ALL_ONLINE },
+        { 0x338c40, 1, RI_ALL_ONLINE }, { 0x338c80, 1, RI_ALL_ONLINE },
+        { 0x338cc0, 1, RI_ALL_ONLINE }, { 0x338cc4, 1, RI_E2_ONLINE },
+        { 0x338d00, 1, RI_ALL_ONLINE }, { 0x338d40, 1, RI_ALL_ONLINE },
+        { 0x338d80, 1, RI_ALL_ONLINE }, { 0x338dc0, 1, RI_ALL_ONLINE },
+        { 0x338e00, 1, RI_ALL_ONLINE }, { 0x338e40, 1, RI_ALL_ONLINE },
+        { 0x338e80, 1, RI_ALL_ONLINE }, { 0x338e84, 1, RI_E2_ONLINE },
+        { 0x338ec0, 1, RI_E1HE2_ONLINE }, { 0x338f00, 1, RI_E1HE2_ONLINE },
+        { 0x338f40, 1, RI_E1HE2_ONLINE }, { 0x338f80, 1, RI_E1HE2_ONLINE },
+        { 0x338fc0, 1, RI_E1HE2_ONLINE }, { 0x338fc4, 2, RI_E2_ONLINE },
+        { 0x338fd0, 6, RI_E2_ONLINE }, { 0x339000, 1, RI_E2_ONLINE },
+        { 0x339040, 3, RI_E2_ONLINE }, { 0x340000, 2, RI_ALL_ONLINE },
 };
 
-
-#define IDLE_REGS_COUNT                 277
+#define IDLE_REGS_COUNT                 237
 static const struct reg_addr idle_addrs[IDLE_REGS_COUNT] = {
-        { 0x2114, 1, RI_ALL_ONLINE }, { 0x2120, 1, RI_ALL_ONLINE },
-        { 0x212c, 4, RI_ALL_ONLINE }, { 0x2814, 1, RI_ALL_ONLINE },
-        { 0x281c, 2, RI_ALL_ONLINE }, { 0xa38c, 1, RI_ALL_ONLINE },
+        { 0x2104, 1, RI_ALL_ONLINE }, { 0x2110, 2, RI_ALL_ONLINE },
+        { 0x211c, 8, RI_ALL_ONLINE }, { 0x2814, 1, RI_ALL_ONLINE },
+        { 0x281c, 2, RI_ALL_ONLINE }, { 0x2854, 1, RI_ALL_ONLINE },
+        { 0x285c, 1, RI_ALL_ONLINE }, { 0x9010, 7, RI_E2_ONLINE },
+        { 0x9030, 1, RI_E2_ONLINE }, { 0x9068, 16, RI_E2_ONLINE },
+        { 0x9230, 2, RI_E2_ONLINE }, { 0x9244, 1, RI_E2_ONLINE },
+        { 0x9298, 1, RI_E2_ONLINE }, { 0x92a8, 1, RI_E2_ONLINE },
+        { 0xa38c, 1, RI_ALL_ONLINE }, { 0xa3c4, 1, RI_E1HE2_ONLINE },
         { 0xa408, 1, RI_ALL_ONLINE }, { 0xa42c, 12, RI_ALL_ONLINE },
-        { 0xa600, 5, RI_E1H_ONLINE }, { 0xa618, 1, RI_E1H_ONLINE },
-        { 0xc09c, 1, RI_ALL_ONLINE }, { 0x103b0, 1, RI_ALL_ONLINE },
-        { 0x103c0, 1, RI_ALL_ONLINE }, { 0x103d0, 1, RI_E1H_ONLINE },
-        { 0x2021c, 11, RI_ALL_ONLINE }, { 0x202a8, 1, RI_ALL_ONLINE },
-        { 0x202b8, 1, RI_ALL_ONLINE }, { 0x20404, 1, RI_ALL_ONLINE },
-        { 0x2040c, 2, RI_ALL_ONLINE }, { 0x2041c, 2, RI_ALL_ONLINE },
-        { 0x40154, 14, RI_ALL_ONLINE }, { 0x40198, 1, RI_ALL_ONLINE },
-        { 0x404ac, 1, RI_ALL_ONLINE }, { 0x404bc, 1, RI_ALL_ONLINE },
-        { 0x42290, 1, RI_ALL_ONLINE }, { 0x422a0, 1, RI_ALL_ONLINE },
-        { 0x422b0, 1, RI_ALL_ONLINE }, { 0x42548, 1, RI_ALL_ONLINE },
-        { 0x42550, 1, RI_ALL_ONLINE }, { 0x42558, 1, RI_ALL_ONLINE },
-        { 0x50160, 8, RI_ALL_ONLINE }, { 0x501d0, 1, RI_ALL_ONLINE },
-        { 0x501e0, 1, RI_ALL_ONLINE }, { 0x50204, 1, RI_ALL_ONLINE },
-        { 0x5020c, 2, RI_ALL_ONLINE }, { 0x5021c, 1, RI_ALL_ONLINE },
-        { 0x60090, 1, RI_ALL_ONLINE }, { 0x6011c, 1, RI_ALL_ONLINE },
-        { 0x6012c, 1, RI_ALL_ONLINE }, { 0xc101c, 1, RI_ALL_ONLINE },
-        { 0xc102c, 1, RI_ALL_ONLINE }, { 0xc2290, 1, RI_ALL_ONLINE },
-        { 0xc22a0, 1, RI_ALL_ONLINE }, { 0xc22b0, 1, RI_ALL_ONLINE },
-        { 0xc2548, 1, RI_ALL_ONLINE }, { 0xc2550, 1, RI_ALL_ONLINE },
-        { 0xc2558, 1, RI_ALL_ONLINE }, { 0xc4294, 1, RI_ALL_ONLINE },
-        { 0xc42a4, 1, RI_ALL_ONLINE }, { 0xc42b4, 1, RI_ALL_ONLINE },
-        { 0xc4550, 1, RI_ALL_ONLINE }, { 0xc4558, 1, RI_ALL_ONLINE },
-        { 0xc4560, 1, RI_ALL_ONLINE }, { 0xd016c, 8, RI_ALL_ONLINE },
-        { 0xd01d8, 1, RI_ALL_ONLINE }, { 0xd01e8, 1, RI_ALL_ONLINE },
-        { 0xd0204, 1, RI_ALL_ONLINE }, { 0xd020c, 3, RI_ALL_ONLINE },
-        { 0xe0154, 8, RI_ALL_ONLINE }, { 0xe01c8, 1, RI_ALL_ONLINE },
-        { 0xe01d8, 1, RI_ALL_ONLINE }, { 0xe0204, 1, RI_ALL_ONLINE },
-        { 0xe020c, 2, RI_ALL_ONLINE }, { 0xe021c, 2, RI_ALL_ONLINE },
-        { 0x101014, 1, RI_ALL_ONLINE }, { 0x101030, 1, RI_ALL_ONLINE },
-        { 0x101040, 1, RI_ALL_ONLINE }, { 0x102058, 1, RI_ALL_ONLINE },
-        { 0x102080, 16, RI_ALL_ONLINE }, { 0x103004, 2, RI_ALL_ONLINE },
-        { 0x103068, 1, RI_ALL_ONLINE }, { 0x103078, 1, RI_ALL_ONLINE },
-        { 0x103088, 1, RI_ALL_ONLINE }, { 0x10309c, 2, RI_E1H_ONLINE },
+        { 0xa600, 5, RI_E1HE2_ONLINE }, { 0xa618, 1, RI_E1HE2_ONLINE },
+        { 0xa714, 1, RI_E2_ONLINE }, { 0xa720, 1, RI_E2_ONLINE },
+        { 0xa750, 1, RI_E2_ONLINE }, { 0xc09c, 1, RI_E1E1H_ONLINE },
+        { 0x103b0, 1, RI_ALL_ONLINE }, { 0x103c0, 1, RI_ALL_ONLINE },
+        { 0x103d0, 1, RI_E1H_ONLINE }, { 0x183bc, 1, RI_E2_ONLINE },
+        { 0x183cc, 1, RI_E2_ONLINE }, { 0x2021c, 11, RI_ALL_ONLINE },
+        { 0x202a8, 1, RI_ALL_ONLINE }, { 0x202b8, 1, RI_ALL_ONLINE },
+        { 0x20404, 1, RI_ALL_ONLINE }, { 0x2040c, 2, RI_ALL_ONLINE },
+        { 0x2041c, 2, RI_ALL_ONLINE }, { 0x40154, 14, RI_ALL_ONLINE },
+        { 0x40198, 1, RI_ALL_ONLINE }, { 0x404ac, 1, RI_ALL_ONLINE },
+        { 0x404bc, 1, RI_ALL_ONLINE }, { 0x42290, 1, RI_ALL_ONLINE },
+        { 0x422a0, 1, RI_ALL_ONLINE }, { 0x422b0, 1, RI_ALL_ONLINE },
+        { 0x42548, 1, RI_ALL_ONLINE }, { 0x42550, 1, RI_ALL_ONLINE },
+        { 0x42558, 1, RI_ALL_ONLINE }, { 0x50160, 8, RI_ALL_ONLINE },
+        { 0x501d0, 1, RI_ALL_ONLINE }, { 0x501e0, 1, RI_ALL_ONLINE },
+        { 0x50204, 1, RI_ALL_ONLINE }, { 0x5020c, 2, RI_ALL_ONLINE },
+        { 0x5021c, 1, RI_ALL_ONLINE }, { 0x60090, 1, RI_ALL_ONLINE },
+        { 0x6011c, 1, RI_ALL_ONLINE }, { 0x6012c, 1, RI_ALL_ONLINE },
+        { 0xc101c, 1, RI_ALL_ONLINE }, { 0xc102c, 1, RI_ALL_ONLINE },
+        { 0xc2290, 1, RI_ALL_ONLINE }, { 0xc22a0, 1, RI_ALL_ONLINE },
+        { 0xc22b0, 1, RI_ALL_ONLINE }, { 0xc2548, 1, RI_ALL_ONLINE },
+        { 0xc2550, 1, RI_ALL_ONLINE }, { 0xc2558, 1, RI_ALL_ONLINE },
+        { 0xc4294, 1, RI_ALL_ONLINE }, { 0xc42a4, 1, RI_ALL_ONLINE },
+        { 0xc42b4, 1, RI_ALL_ONLINE }, { 0xc4550, 1, RI_ALL_ONLINE },
+        { 0xc4558, 1, RI_ALL_ONLINE }, { 0xc4560, 1, RI_ALL_ONLINE },
+        { 0xd016c, 8, RI_ALL_ONLINE }, { 0xd01d8, 1, RI_ALL_ONLINE },
+        { 0xd01e8, 1, RI_ALL_ONLINE }, { 0xd0204, 1, RI_ALL_ONLINE },
+        { 0xd020c, 3, RI_ALL_ONLINE }, { 0xe0154, 8, RI_ALL_ONLINE },
+        { 0xe01c8, 1, RI_ALL_ONLINE }, { 0xe01d8, 1, RI_ALL_ONLINE },
+        { 0xe0204, 1, RI_ALL_ONLINE }, { 0xe020c, 2, RI_ALL_ONLINE },
+        { 0xe021c, 2, RI_ALL_ONLINE }, { 0x101014, 1, RI_ALL_ONLINE },
+        { 0x101030, 1, RI_ALL_ONLINE }, { 0x101040, 1, RI_ALL_ONLINE },
+        { 0x102058, 1, RI_ALL_ONLINE }, { 0x102080, 16, RI_ALL_ONLINE },
+        { 0x103004, 2, RI_ALL_ONLINE }, { 0x103068, 1, RI_ALL_ONLINE },
+        { 0x103078, 1, RI_ALL_ONLINE }, { 0x103088, 1, RI_ALL_ONLINE },
+        { 0x10309c, 2, RI_E1HE2_ONLINE }, { 0x1030b8, 2, RI_E2_ONLINE },
+        { 0x1030cc, 1, RI_E2_ONLINE }, { 0x1030e0, 1, RI_E2_ONLINE },
         { 0x104004, 1, RI_ALL_ONLINE }, { 0x104018, 1, RI_ALL_ONLINE },
         { 0x104020, 1, RI_ALL_ONLINE }, { 0x10403c, 1, RI_ALL_ONLINE },
         { 0x1040fc, 1, RI_ALL_ONLINE }, { 0x10410c, 1, RI_ALL_ONLINE },
         { 0x104400, 64, RI_ALL_ONLINE }, { 0x104800, 64, RI_ALL_ONLINE },
-        { 0x105000, 3, RI_ALL_ONLINE }, { 0x105010, 3, RI_ALL_ONLINE },
-        { 0x105020, 3, RI_ALL_ONLINE }, { 0x105030, 3, RI_ALL_ONLINE },
-        { 0x105040, 3, RI_ALL_ONLINE }, { 0x105050, 3, RI_ALL_ONLINE },
-        { 0x105060, 3, RI_ALL_ONLINE }, { 0x105070, 3, RI_ALL_ONLINE },
-        { 0x105080, 3, RI_ALL_ONLINE }, { 0x105090, 3, RI_ALL_ONLINE },
-        { 0x1050a0, 3, RI_ALL_ONLINE }, { 0x1050b0, 3, RI_ALL_ONLINE },
-        { 0x1050c0, 3, RI_ALL_ONLINE }, { 0x1050d0, 3, RI_ALL_ONLINE },
-        { 0x1050e0, 3, RI_ALL_ONLINE }, { 0x1050f0, 3, RI_ALL_ONLINE },
-        { 0x105100, 3, RI_ALL_ONLINE }, { 0x105110, 3, RI_ALL_ONLINE },
-        { 0x105120, 3, RI_ALL_ONLINE }, { 0x105130, 3, RI_ALL_ONLINE },
-        { 0x105140, 3, RI_ALL_ONLINE }, { 0x105150, 3, RI_ALL_ONLINE },
-        { 0x105160, 3, RI_ALL_ONLINE }, { 0x105170, 3, RI_ALL_ONLINE },
-        { 0x105180, 3, RI_ALL_ONLINE }, { 0x105190, 3, RI_ALL_ONLINE },
-        { 0x1051a0, 3, RI_ALL_ONLINE }, { 0x1051b0, 3, RI_ALL_ONLINE },
-        { 0x1051c0, 3, RI_ALL_ONLINE }, { 0x1051d0, 3, RI_ALL_ONLINE },
-        { 0x1051e0, 3, RI_ALL_ONLINE }, { 0x1051f0, 3, RI_ALL_ONLINE },
-        { 0x105200, 3, RI_ALL_ONLINE }, { 0x105210, 3, RI_ALL_ONLINE },
-        { 0x105220, 3, RI_ALL_ONLINE }, { 0x105230, 3, RI_ALL_ONLINE },
-        { 0x105240, 3, RI_ALL_ONLINE }, { 0x105250, 3, RI_ALL_ONLINE },
-        { 0x105260, 3, RI_ALL_ONLINE }, { 0x105270, 3, RI_ALL_ONLINE },
-        { 0x105280, 3, RI_ALL_ONLINE }, { 0x105290, 3, RI_ALL_ONLINE },
-        { 0x1052a0, 3, RI_ALL_ONLINE }, { 0x1052b0, 3, RI_ALL_ONLINE },
-        { 0x1052c0, 3, RI_ALL_ONLINE }, { 0x1052d0, 3, RI_ALL_ONLINE },
-        { 0x1052e0, 3, RI_ALL_ONLINE }, { 0x1052f0, 3, RI_ALL_ONLINE },
-        { 0x105300, 3, RI_ALL_ONLINE }, { 0x105310, 3, RI_ALL_ONLINE },
-        { 0x105320, 3, RI_ALL_ONLINE }, { 0x105330, 3, RI_ALL_ONLINE },
-        { 0x105340, 3, RI_ALL_ONLINE }, { 0x105350, 3, RI_ALL_ONLINE },
-        { 0x105360, 3, RI_ALL_ONLINE }, { 0x105370, 3, RI_ALL_ONLINE },
-        { 0x105380, 3, RI_ALL_ONLINE }, { 0x105390, 3, RI_ALL_ONLINE },
-        { 0x1053a0, 3, RI_ALL_ONLINE }, { 0x1053b0, 3, RI_ALL_ONLINE },
-        { 0x1053c0, 3, RI_ALL_ONLINE }, { 0x1053d0, 3, RI_ALL_ONLINE },
-        { 0x1053e0, 3, RI_ALL_ONLINE }, { 0x1053f0, 3, RI_ALL_ONLINE },
-        { 0x108094, 1, RI_ALL_ONLINE }, { 0x1201b0, 2, RI_ALL_ONLINE },
-        { 0x12032c, 1, RI_ALL_ONLINE }, { 0x12036c, 3, RI_ALL_ONLINE },
-        { 0x120408, 2, RI_ALL_ONLINE }, { 0x120414, 15, RI_ALL_ONLINE },
-        { 0x120478, 2, RI_ALL_ONLINE }, { 0x12052c, 1, RI_ALL_ONLINE },
-        { 0x120564, 3, RI_ALL_ONLINE }, { 0x12057c, 1, RI_ALL_ONLINE },
-        { 0x12058c, 1, RI_ALL_ONLINE }, { 0x120608, 1, RI_E1H_ONLINE },
-        { 0x120808, 1, RI_E1_ONLINE }, { 0x12080c, 2, RI_ALL_ONLINE },
+        { 0x105000, 256, RI_ALL_ONLINE }, { 0x108094, 1, RI_E1E1H_ONLINE },
+        { 0x1201b0, 2, RI_ALL_ONLINE }, { 0x12032c, 1, RI_ALL_ONLINE },
+        { 0x12036c, 3, RI_ALL_ONLINE }, { 0x120408, 2, RI_ALL_ONLINE },
+        { 0x120414, 15, RI_ALL_ONLINE }, { 0x120478, 2, RI_ALL_ONLINE },
+        { 0x12052c, 1, RI_ALL_ONLINE }, { 0x120564, 3, RI_ALL_ONLINE },
+        { 0x12057c, 1, RI_ALL_ONLINE }, { 0x12058c, 1, RI_ALL_ONLINE },
+        { 0x120608, 1, RI_E1HE2_ONLINE }, { 0x120738, 1, RI_E2_ONLINE },
+        { 0x120778, 2, RI_E2_ONLINE }, { 0x120808, 3, RI_ALL_ONLINE },
         { 0x120818, 1, RI_ALL_ONLINE }, { 0x120820, 1, RI_ALL_ONLINE },
         { 0x120828, 1, RI_ALL_ONLINE }, { 0x120830, 1, RI_ALL_ONLINE },
         { 0x120838, 1, RI_ALL_ONLINE }, { 0x120840, 1, RI_ALL_ONLINE },
@@ -462,48 +580,50 @@ static const struct reg_addr idle_addrs[IDLE_REGS_COUNT] = {
         { 0x1208d8, 1, RI_ALL_ONLINE }, { 0x1208e0, 1, RI_ALL_ONLINE },
         { 0x1208e8, 1, RI_ALL_ONLINE }, { 0x1208f0, 1, RI_ALL_ONLINE },
         { 0x1208f8, 1, RI_ALL_ONLINE }, { 0x120900, 1, RI_ALL_ONLINE },
-        { 0x120908, 1, RI_ALL_ONLINE }, { 0x14005c, 2, RI_ALL_ONLINE },
-        { 0x1400d0, 2, RI_ALL_ONLINE }, { 0x1400e0, 1, RI_ALL_ONLINE },
-        { 0x1401c8, 1, RI_ALL_ONLINE }, { 0x140200, 6, RI_ALL_ONLINE },
-        { 0x16101c, 1, RI_ALL_ONLINE }, { 0x16102c, 1, RI_ALL_ONLINE },
-        { 0x164014, 2, RI_ALL_ONLINE }, { 0x1640f0, 1, RI_ALL_ONLINE },
-        { 0x166290, 1, RI_ALL_ONLINE }, { 0x1662a0, 1, RI_ALL_ONLINE },
-        { 0x1662b0, 1, RI_ALL_ONLINE }, { 0x166548, 1, RI_ALL_ONLINE },
-        { 0x166550, 1, RI_ALL_ONLINE }, { 0x166558, 1, RI_ALL_ONLINE },
-        { 0x168000, 1, RI_ALL_ONLINE }, { 0x168008, 1, RI_ALL_ONLINE },
-        { 0x168010, 1, RI_ALL_ONLINE }, { 0x168018, 1, RI_ALL_ONLINE },
-        { 0x168028, 2, RI_ALL_ONLINE }, { 0x168058, 4, RI_ALL_ONLINE },
-        { 0x168070, 1, RI_ALL_ONLINE }, { 0x168238, 1, RI_ALL_ONLINE },
-        { 0x1682d0, 2, RI_ALL_ONLINE }, { 0x1682e0, 1, RI_ALL_ONLINE },
-        { 0x168300, 67, RI_ALL_ONLINE }, { 0x168410, 2, RI_ALL_ONLINE },
+        { 0x120908, 1, RI_ALL_ONLINE }, { 0x120940, 5, RI_E2_ONLINE },
+        { 0x130030, 1, RI_E2_ONLINE }, { 0x13004c, 3, RI_E2_ONLINE },
+        { 0x130064, 2, RI_E2_ONLINE }, { 0x13009c, 1, RI_E2_ONLINE },
+        { 0x130130, 1, RI_E2_ONLINE }, { 0x13016c, 1, RI_E2_ONLINE },
+        { 0x130300, 1, RI_E2_ONLINE }, { 0x130480, 1, RI_E2_ONLINE },
+        { 0x14005c, 2, RI_ALL_ONLINE }, { 0x1400d0, 2, RI_ALL_ONLINE },
+        { 0x1400e0, 1, RI_ALL_ONLINE }, { 0x1401c8, 1, RI_ALL_ONLINE },
+        { 0x140200, 6, RI_ALL_ONLINE }, { 0x16101c, 1, RI_ALL_ONLINE },
+        { 0x16102c, 1, RI_ALL_ONLINE }, { 0x164014, 2, RI_ALL_ONLINE },
+        { 0x1640f0, 1, RI_ALL_ONLINE }, { 0x166290, 1, RI_ALL_ONLINE },
+        { 0x1662a0, 1, RI_ALL_ONLINE }, { 0x1662b0, 1, RI_ALL_ONLINE },
+        { 0x166548, 1, RI_ALL_ONLINE }, { 0x166550, 1, RI_ALL_ONLINE },
+        { 0x166558, 1, RI_ALL_ONLINE }, { 0x168000, 1, RI_ALL_ONLINE },
+        { 0x168008, 1, RI_ALL_ONLINE }, { 0x168010, 1, RI_ALL_ONLINE },
+        { 0x168018, 1, RI_ALL_ONLINE }, { 0x168028, 2, RI_ALL_ONLINE },
+        { 0x168058, 4, RI_ALL_ONLINE }, { 0x168070, 1, RI_ALL_ONLINE },
+        { 0x168238, 1, RI_ALL_ONLINE }, { 0x1682d0, 2, RI_ALL_ONLINE },
+        { 0x1682e0, 1, RI_ALL_ONLINE }, { 0x168300, 2, RI_E1E1H_ONLINE },
+        { 0x168308, 65, RI_ALL_ONLINE }, { 0x168410, 2, RI_ALL_ONLINE },
         { 0x168438, 1, RI_ALL_ONLINE }, { 0x168448, 1, RI_ALL_ONLINE },
         { 0x168a00, 128, RI_ALL_ONLINE }, { 0x16e200, 128, RI_E1H_ONLINE },
-        { 0x16e404, 2, RI_E1H_ONLINE }, { 0x16e584, 70, RI_E1H_ONLINE },
-        { 0x1700a4, 1, RI_ALL_ONLINE }, { 0x1700ac, 2, RI_ALL_ONLINE },
-        { 0x1700c0, 1, RI_ALL_ONLINE }, { 0x170174, 1, RI_ALL_ONLINE },
-        { 0x170184, 1, RI_ALL_ONLINE }, { 0x1800f4, 1, RI_ALL_ONLINE },
-        { 0x180104, 1, RI_ALL_ONLINE }, { 0x180114, 1, RI_ALL_ONLINE },
-        { 0x180124, 1, RI_ALL_ONLINE }, { 0x18026c, 1, RI_ALL_ONLINE },
-        { 0x1802a0, 1, RI_ALL_ONLINE }, { 0x1a1000, 1, RI_ALL_ONLINE },
-        { 0x1aa000, 1, RI_E1H_ONLINE }, { 0x1b8000, 1, RI_ALL_ONLINE },
-        { 0x1b8040, 1, RI_ALL_ONLINE }, { 0x1b8080, 1, RI_ALL_ONLINE },
-        { 0x1b80c0, 1, RI_ALL_ONLINE }, { 0x200104, 1, RI_ALL_ONLINE },
-        { 0x200114, 1, RI_ALL_ONLINE }, { 0x200124, 1, RI_ALL_ONLINE },
-        { 0x200134, 1, RI_ALL_ONLINE }, { 0x20026c, 1, RI_ALL_ONLINE },
-        { 0x2002a0, 1, RI_ALL_ONLINE }, { 0x221000, 1, RI_ALL_ONLINE },
-        { 0x227000, 1, RI_E1H_ONLINE }, { 0x238000, 1, RI_ALL_ONLINE },
-        { 0x238040, 1, RI_ALL_ONLINE }, { 0x238080, 1, RI_ALL_ONLINE },
-        { 0x2380c0, 1, RI_ALL_ONLINE }, { 0x280104, 1, RI_ALL_ONLINE },
-        { 0x280114, 1, RI_ALL_ONLINE }, { 0x280124, 1, RI_ALL_ONLINE },
-        { 0x280134, 1, RI_ALL_ONLINE }, { 0x28026c, 1, RI_ALL_ONLINE },
-        { 0x2802a0, 1, RI_ALL_ONLINE }, { 0x2a1000, 1, RI_ALL_ONLINE },
-        { 0x2a9000, 1, RI_E1H_ONLINE }, { 0x2b8000, 1, RI_ALL_ONLINE },
-        { 0x2b8040, 1, RI_ALL_ONLINE }, { 0x2b8080, 1, RI_ALL_ONLINE },
-        { 0x2b80c0, 1, RI_ALL_ONLINE }, { 0x300104, 1, RI_ALL_ONLINE },
+        { 0x16e404, 2, RI_E1H_ONLINE }, { 0x16e584, 64, RI_E1H_ONLINE },
+        { 0x16e684, 2, RI_E1HE2_ONLINE }, { 0x16e68c, 4, RI_E1H_ONLINE },
+        { 0x16e6fc, 4, RI_E2_ONLINE }, { 0x1700a4, 1, RI_ALL_ONLINE },
+        { 0x1700ac, 2, RI_ALL_ONLINE }, { 0x1700c0, 1, RI_ALL_ONLINE },
+        { 0x170174, 1, RI_ALL_ONLINE }, { 0x170184, 1, RI_ALL_ONLINE },
+        { 0x1800f4, 1, RI_ALL_ONLINE }, { 0x180104, 1, RI_ALL_ONLINE },
+        { 0x180114, 1, RI_ALL_ONLINE }, { 0x180124, 1, RI_ALL_ONLINE },
+        { 0x18026c, 1, RI_ALL_ONLINE }, { 0x1802a0, 1, RI_ALL_ONLINE },
+        { 0x1b8000, 1, RI_ALL_ONLINE }, { 0x1b8040, 1, RI_ALL_ONLINE },
+        { 0x1b8080, 1, RI_ALL_ONLINE }, { 0x1b80c0, 1, RI_ALL_ONLINE },
+        { 0x200104, 1, RI_ALL_ONLINE }, { 0x200114, 1, RI_ALL_ONLINE },
+        { 0x200124, 1, RI_ALL_ONLINE }, { 0x200134, 1, RI_ALL_ONLINE },
+        { 0x20026c, 1, RI_ALL_ONLINE }, { 0x2002a0, 1, RI_ALL_ONLINE },
+        { 0x238000, 1, RI_ALL_ONLINE }, { 0x238040, 1, RI_ALL_ONLINE },
+        { 0x238080, 1, RI_ALL_ONLINE }, { 0x2380c0, 1, RI_ALL_ONLINE },
+        { 0x280104, 1, RI_ALL_ONLINE }, { 0x280114, 1, RI_ALL_ONLINE },
+        { 0x280124, 1, RI_ALL_ONLINE }, { 0x280134, 1, RI_ALL_ONLINE },
+        { 0x28026c, 1, RI_ALL_ONLINE }, { 0x2802a0, 1, RI_ALL_ONLINE },
+        { 0x2b8000, 1, RI_ALL_ONLINE }, { 0x2b8040, 1, RI_ALL_ONLINE },
+        { 0x2b8080, 1, RI_ALL_ONLINE }, { 0x300104, 1, RI_ALL_ONLINE },
         { 0x300114, 1, RI_ALL_ONLINE }, { 0x300124, 1, RI_ALL_ONLINE },
         { 0x300134, 1, RI_ALL_ONLINE }, { 0x30026c, 1, RI_ALL_ONLINE },
-        { 0x3002a0, 1, RI_ALL_ONLINE }, { 0x321000, 1, RI_ALL_ONLINE },
-        { 0x328960, 1, RI_E1H_ONLINE }, { 0x338000, 1, RI_ALL_ONLINE },
+        { 0x3002a0, 1, RI_ALL_ONLINE }, { 0x338000, 1, RI_ALL_ONLINE },
         { 0x338040, 1, RI_ALL_ONLINE }, { 0x338080, 1, RI_ALL_ONLINE },
         { 0x3380c0, 1, RI_ALL_ONLINE }
 };
@@ -515,7 +635,6 @@ static const struct wreg_addr wreg_addrs_e1[WREGS_COUNT_E1] = {
         { 0x1b0c00, 192, 1, read_reg_e1_0, RI_E1_OFFLINE }
 };
 
-
 #define WREGS_COUNT_E1H                 1
 static const u32 read_reg_e1h_0[] = { 0x1b1040, 0x1b1000 };
 
@@ -530,22 +649,53 @@ static const struct wreg_addr wreg_addrs_e2[WREGS_COUNT_E2] = {
         { 0x1b0c00, 128, 2, read_reg_e2_0, RI_E2_OFFLINE }
 };
 
-static const struct dump_sign dump_sign_all = { 0x49aa93ee, 0x40835, 0x22 };
-
+static const struct dump_sign dump_sign_all = { 0x4d18b0a4, 0x60010, 0x3a };
 
 #define TIMER_REGS_COUNT_E1             2
-static const u32 timer_status_regs_e1[TIMER_REGS_COUNT_E1] =
-        { 0x164014, 0x164018 };
-static const u32 timer_scan_regs_e1[TIMER_REGS_COUNT_E1] =
-        { 0x1640d0, 0x1640d4 };
 
+static const u32 timer_status_regs_e1[TIMER_REGS_COUNT_E1] = {
+        0x164014, 0x164018 };
+static const u32 timer_scan_regs_e1[TIMER_REGS_COUNT_E1] = {
+        0x1640d0, 0x1640d4 };
 
 #define TIMER_REGS_COUNT_E1H            2
-static const u32 timer_status_regs_e1h[TIMER_REGS_COUNT_E1H] =
-        { 0x164014, 0x164018 };
-static const u32 timer_scan_regs_e1h[TIMER_REGS_COUNT_E1H] =
-        { 0x1640d0, 0x1640d4 };
 
+static const u32 timer_status_regs_e1h[TIMER_REGS_COUNT_E1H] = {
+        0x164014, 0x164018 };
+static const u32 timer_scan_regs_e1h[TIMER_REGS_COUNT_E1H] = {
+        0x1640d0, 0x1640d4 };
+
+#define TIMER_REGS_COUNT_E2             2
+
+static const u32 timer_status_regs_e2[TIMER_REGS_COUNT_E2] = {
+        0x164014, 0x164018 };
+static const u32 timer_scan_regs_e2[TIMER_REGS_COUNT_E2] = {
+        0x1640d0, 0x1640d4 };
+
+#define PAGE_MODE_VALUES_E1 0
+
+#define PAGE_READ_REGS_E1 0
+
+#define PAGE_WRITE_REGS_E1 0
+
+static const u32 page_vals_e1[] = { 0 };
+
+static const u32 page_write_regs_e1[] = { 0 };
+
+static const struct reg_addr page_read_regs_e1[] = { { 0x0, 0, RI_E1_ONLINE } };
+
+#define PAGE_MODE_VALUES_E1H 0
+
+#define PAGE_READ_REGS_E1H 0
+
+#define PAGE_WRITE_REGS_E1H 0
+
+static const u32 page_vals_e1h[] = { 0 };
+
+static const u32 page_write_regs_e1h[] = { 0 };
+
+static const struct reg_addr page_read_regs_e1h[] = {
+        { 0x0, 0, RI_E1H_ONLINE } };
 
 #define PAGE_MODE_VALUES_E2 2
 
diff --git a/drivers/net/bnx2x/bnx2x_ethtool.c b/drivers/net/bnx2x/bnx2x_ethtool.c
index 99c672d894ca..5b44a8b48509 100644
--- a/drivers/net/bnx2x/bnx2x_ethtool.c
+++ b/drivers/net/bnx2x/bnx2x_ethtool.c
@@ -24,6 +24,7 @@
 #include "bnx2x.h"
 #include "bnx2x_cmn.h"
 #include "bnx2x_dump.h"
+#include "bnx2x_init.h"
 
 /* Note: in the format strings below %s is replaced by the queue-name which is
  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
@@ -472,7 +473,7 @@ static int bnx2x_get_regs_len(struct net_device *dev)
 {
         struct bnx2x *bp = netdev_priv(dev);
         int regdump_len = 0;
-        int i;
+        int i, j, k;
 
         if (CHIP_IS_E1(bp)) {
                 for (i = 0; i < REGS_COUNT; i++)
@@ -502,6 +503,15 @@ static int bnx2x_get_regs_len(struct net_device *dev)
                         if (IS_E2_ONLINE(wreg_addrs_e2[i].info))
                                 regdump_len += wreg_addrs_e2[i].size *
                                         (1 + wreg_addrs_e2[i].read_regs_count);
+
+                for (i = 0; i < PAGE_MODE_VALUES_E2; i++)
+                        for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
+                                for (k = 0; k < PAGE_READ_REGS_E2; k++)
+                                        if (IS_E2_ONLINE(page_read_regs_e2[k].
+                                                         info))
+                                                regdump_len +=
+                                                page_read_regs_e2[k].size;
+                        }
         }
         regdump_len *= 4;
         regdump_len += sizeof(struct dump_hdr);
@@ -539,6 +549,12 @@ static void bnx2x_get_regs(struct net_device *dev,
         if (!netif_running(bp->dev))
                 return;
 
+        /* Disable parity attentions as long as following dump may
+         * cause false alarms by reading never written registers. We
+         * will re-enable parity attentions right after the dump.
+         */
+        bnx2x_disable_blocks_parity(bp);
+
         dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
         dump_hdr.dump_sign = dump_sign_all;
         dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
@@ -580,6 +596,10 @@ static void bnx2x_get_regs(struct net_device *dev,
 
                 bnx2x_read_pages_regs_e2(bp, p);
         }
+        /* Re-enable parity attentions */
+        bnx2x_clear_blocks_parity(bp);
+        if (CHIP_PARITY_ENABLED(bp))
+                bnx2x_enable_blocks_parity(bp);
 }
 
 #define PHY_FW_VER_LEN                  20
diff --git a/drivers/net/bnx2x/bnx2x_init.h b/drivers/net/bnx2x/bnx2x_init.h
index a9d54874a559..5a268e9a0895 100644
--- a/drivers/net/bnx2x/bnx2x_init.h
+++ b/drivers/net/bnx2x/bnx2x_init.h
@@ -192,5 +192,225 @@ struct src_ent {
         u64 next;
 };
 
+/****************************************************************************
+* Parity configuration
+****************************************************************************/
+#define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2) \
+{ \
+        block##_REG_##block##_PRTY_MASK, \
+        block##_REG_##block##_PRTY_STS_CLR, \
+        en_mask, {m1, m1h, m2}, #block \
+}
+
+#define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2) \
+{ \
+        block##_REG_##block##_PRTY_MASK_0, \
+        block##_REG_##block##_PRTY_STS_CLR_0, \
+        en_mask, {m1, m1h, m2}, #block"_0" \
+}
+
+#define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2) \
+{ \
+        block##_REG_##block##_PRTY_MASK_1, \
+        block##_REG_##block##_PRTY_STS_CLR_1, \
+        en_mask, {m1, m1h, m2}, #block"_1" \
+}
+
+static const struct {
+        u32 mask_addr;
+        u32 sts_clr_addr;
+        u32 en_mask;            /* Mask to enable parity attentions */
+        struct {
+                u32 e1;         /* 57710 */
+                u32 e1h;        /* 57711 */
+                u32 e2;         /* 57712 */
+        } reg_mask;             /* Register mask (all valid bits) */
+        char name[7];           /* Block's longest name is 6 characters long
+                                 * (name + suffix)
+                                 */
+} bnx2x_blocks_parity_data[] = {
+        /* bit 19 masked */
+        /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
+        /* bit 5,18,20-31 */
+        /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
+        /* bit 5 */
+        /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
+        /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
+        /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
+
+        /* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
+         * want to handle "system kill" flow at the moment.
+         */
+        BLOCK_PRTY_INFO(PXP, 0x3ffffff, 0x3ffffff, 0x3ffffff, 0x3ffffff),
+        BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff),
+        BLOCK_PRTY_INFO_1(PXP2, 0x7ff, 0x7f, 0x7f, 0x7ff),
+        BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0),
+        BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff),
+        BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1),
+        BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff),
+        BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3),
+        {GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
+                GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0,
+                {0xf, 0xf, 0xf}, "UPB"},
+        {GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
+                GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
+                {0xf, 0xf, 0xf}, "XPB"},
+        BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7),
+        BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f),
+        BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf),
+        BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1),
+        BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf),
+        BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf),
+        BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff),
+        BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff),
+        BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
+        BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff),
+        BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
+        BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
+        BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f),
+        BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
+        BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f),
+        BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
+        BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f),
+        BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
+        BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f),
+};
+
+
+/* [28] MCP Latched rom_parity
+ * [29] MCP Latched ump_rx_parity
+ * [30] MCP Latched ump_tx_parity
+ * [31] MCP Latched scpad_parity
+ */
+#define MISC_AEU_ENABLE_MCP_PRTY_BITS   \
+        (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
+         AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
+         AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
+         AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
+
+/* Below registers control the MCP parity attention output. When
+ * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
+ * enabled, when cleared - disabled.
+ */
+static const u32 mcp_attn_ctl_regs[] = {
+        MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
+        MISC_REG_AEU_ENABLE4_NIG_0,
+        MISC_REG_AEU_ENABLE4_PXP_0,
+        MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
+        MISC_REG_AEU_ENABLE4_NIG_1,
+        MISC_REG_AEU_ENABLE4_PXP_1
+};
+
+static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, u8 enable)
+{
+        int i;
+        u32 reg_val;
+
+        for (i = 0; i < ARRAY_SIZE(mcp_attn_ctl_regs); i++) {
+                reg_val = REG_RD(bp, mcp_attn_ctl_regs[i]);
+
+                if (enable)
+                        reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS;
+                else
+                        reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;
+
+                REG_WR(bp, mcp_attn_ctl_regs[i], reg_val);
+        }
+}
+
+static inline u32 bnx2x_parity_reg_mask(struct bnx2x *bp, int idx)
+{
+        if (CHIP_IS_E1(bp))
+                return bnx2x_blocks_parity_data[idx].reg_mask.e1;
+        else if (CHIP_IS_E1H(bp))
+                return bnx2x_blocks_parity_data[idx].reg_mask.e1h;
+        else
+                return bnx2x_blocks_parity_data[idx].reg_mask.e2;
+}
+
+static inline void bnx2x_disable_blocks_parity(struct bnx2x *bp)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
+                u32 dis_mask = bnx2x_parity_reg_mask(bp, i);
+
+                if (dis_mask) {
+                        REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
+                               dis_mask);
+                        DP(NETIF_MSG_HW, "Setting parity mask "
+                                                 "for %s to\t\t0x%x\n",
+                                    bnx2x_blocks_parity_data[i].name, dis_mask);
+                }
+        }
+
+        /* Disable MCP parity attentions */
+        bnx2x_set_mcp_parity(bp, false);
+}
+
+/**
+ * Clear the parity error status registers.
+ */
+static inline void bnx2x_clear_blocks_parity(struct bnx2x *bp)
+{
+        int i;
+        u32 reg_val, mcp_aeu_bits =
+                AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
+                AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
+                AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |
+                AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;
+
+        /* Clear SEM_FAST parities */
+        REG_WR(bp, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
+        REG_WR(bp, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
+        REG_WR(bp, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
+        REG_WR(bp, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
+
+        for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
+                u32 reg_mask = bnx2x_parity_reg_mask(bp, i);
+
+                if (reg_mask) {
+                        reg_val = REG_RD(bp, bnx2x_blocks_parity_data[i].
+                                         sts_clr_addr);
+                        if (reg_val & reg_mask)
+                                DP(NETIF_MSG_HW,
+                                            "Parity errors in %s: 0x%x\n",
+                                            bnx2x_blocks_parity_data[i].name,
+                                            reg_val & reg_mask);
+                }
+        }
+
+        /* Check if there were parity attentions in MCP */
+        reg_val = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_MCP);
+        if (reg_val & mcp_aeu_bits)
+                DP(NETIF_MSG_HW, "Parity error in MCP: 0x%x\n",
+                   reg_val & mcp_aeu_bits);
+
+        /* Clear parity attentions in MCP:
+         * [7]  clears Latched rom_parity
+         * [8]  clears Latched ump_rx_parity
+         * [9]  clears Latched ump_tx_parity
+         * [10] clears Latched scpad_parity (both ports)
+         */
+        REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
+}
+
+static inline void bnx2x_enable_blocks_parity(struct bnx2x *bp)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
+                u32 reg_mask = bnx2x_parity_reg_mask(bp, i);
+
+                if (reg_mask)
+                        REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
+                                bnx2x_blocks_parity_data[i].en_mask & reg_mask);
+        }
+
+        /* Enable MCP parity attentions */
+        bnx2x_set_mcp_parity(bp, true);
+}
+
+
 #endif /* BNX2X_INIT_H */
 
diff --git a/drivers/net/bnx2x/bnx2x_main.c b/drivers/net/bnx2x/bnx2x_main.c
index 489a5512a04d..84e1af4d65e1 100644
--- a/drivers/net/bnx2x/bnx2x_main.c
+++ b/drivers/net/bnx2x/bnx2x_main.c
@@ -3152,7 +3152,6 @@ static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
 #define LOAD_COUNTER_MASK       (((u32)0x1 << LOAD_COUNTER_BITS) - 1)
 #define RESET_DONE_FLAG_MASK    (~LOAD_COUNTER_MASK)
 #define RESET_DONE_FLAG_SHIFT   LOAD_COUNTER_BITS
-#define CHIP_PARITY_SUPPORTED(bp)   (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp))
 
 /*
  * should be run under rtnl lock
@@ -3527,7 +3526,7 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
            try to handle this event */
         bnx2x_acquire_alr(bp);
 
-        if (bnx2x_chk_parity_attn(bp)) {
+        if (CHIP_PARITY_ENABLED(bp) && bnx2x_chk_parity_attn(bp)) {
                 bp->recovery_state = BNX2X_RECOVERY_INIT;
                 bnx2x_set_reset_in_progress(bp);
                 schedule_delayed_work(&bp->reset_task, 0);
@@ -4754,7 +4753,7 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
         return 0; /* OK */
 }
 
-static void enable_blocks_attention(struct bnx2x *bp)
+static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
 {
         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
         if (CHIP_IS_E2(bp))
@@ -4808,53 +4807,9 @@ static void enable_blocks_attention(struct bnx2x *bp)
         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
-        REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18);         /* bit 3,4 masked */
+        REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
 }
 
-static const struct {
-        u32 addr;
-        u32 mask;
-} bnx2x_parity_mask[] = {
-        {PXP_REG_PXP_PRTY_MASK,         0x3ffffff},
-        {PXP2_REG_PXP2_PRTY_MASK_0,     0xffffffff},
-        {PXP2_REG_PXP2_PRTY_MASK_1,     0x7f},
-        {HC_REG_HC_PRTY_MASK,           0x7},
-        {MISC_REG_MISC_PRTY_MASK,       0x1},
-        {QM_REG_QM_PRTY_MASK,           0x0},
-        {DORQ_REG_DORQ_PRTY_MASK,       0x0},
-        {GRCBASE_UPB + PB_REG_PB_PRTY_MASK, 0x0},
-        {GRCBASE_XPB + PB_REG_PB_PRTY_MASK, 0x0},
-        {SRC_REG_SRC_PRTY_MASK,         0x4}, /* bit 2 */
-        {CDU_REG_CDU_PRTY_MASK,         0x0},
-        {CFC_REG_CFC_PRTY_MASK,         0x0},
-        {DBG_REG_DBG_PRTY_MASK,         0x0},
-        {DMAE_REG_DMAE_PRTY_MASK,       0x0},
-        {BRB1_REG_BRB1_PRTY_MASK,       0x0},
-        {PRS_REG_PRS_PRTY_MASK,         (1<<6)},/* bit 6 */
-        {TSDM_REG_TSDM_PRTY_MASK,       0x18},  /* bit 3,4 */
-        {CSDM_REG_CSDM_PRTY_MASK,       0x8},   /* bit 3 */
-        {USDM_REG_USDM_PRTY_MASK,       0x38},  /* bit 3,4,5 */
-        {XSDM_REG_XSDM_PRTY_MASK,       0x8},   /* bit 3 */
-        {TSEM_REG_TSEM_PRTY_MASK_0,     0x0},
-        {TSEM_REG_TSEM_PRTY_MASK_1,     0x0},
-        {USEM_REG_USEM_PRTY_MASK_0,     0x0},
-        {USEM_REG_USEM_PRTY_MASK_1,     0x0},
-        {CSEM_REG_CSEM_PRTY_MASK_0,     0x0},
-        {CSEM_REG_CSEM_PRTY_MASK_1,     0x0},
-        {XSEM_REG_XSEM_PRTY_MASK_0,     0x0},
-        {XSEM_REG_XSEM_PRTY_MASK_1,     0x0}
-};
-
-static void enable_blocks_parity(struct bnx2x *bp)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(bnx2x_parity_mask); i++)
-                REG_WR(bp, bnx2x_parity_mask[i].addr,
-                        bnx2x_parity_mask[i].mask);
-}
-
-
 static void bnx2x_reset_common(struct bnx2x *bp)
 {
         /* reset_common */
@@ -5350,9 +5305,9 @@ static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
         /* clear PXP2 attentions */
         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
 
-        enable_blocks_attention(bp);
-        if (CHIP_PARITY_SUPPORTED(bp))
-                enable_blocks_parity(bp);
+        bnx2x_enable_blocks_attention(bp);
+        if (CHIP_PARITY_ENABLED(bp))
+                bnx2x_enable_blocks_parity(bp);
 
         if (!BP_NOMCP(bp)) {
                 /* In E2 2-PORT mode, same ext phy is used for the two paths */
@@ -8751,13 +8706,6 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
                 dev_err(&bp->pdev->dev, "MCP disabled, "
                                         "must load devices in order!\n");
 
-        /* Set multi queue mode */
-        if ((multi_mode != ETH_RSS_MODE_DISABLED) &&
-            ((int_mode == INT_MODE_INTx) || (int_mode == INT_MODE_MSI))) {
-                dev_err(&bp->pdev->dev, "Multi disabled since int_mode "
-                                        "requested is not MSI-X\n");
-                multi_mode = ETH_RSS_MODE_DISABLED;
-        }
         bp->multi_mode = multi_mode;
         bp->int_mode = int_mode;
 
@@ -9560,9 +9508,15 @@ static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
         /* Delete all NAPI objects */
         bnx2x_del_all_napi(bp);
 
+        /* Power on: we can't let PCI layer write to us while we are in D3 */
+        bnx2x_set_power_state(bp, PCI_D0);
+
         /* Disable MSI/MSI-X */
         bnx2x_disable_msi(bp);
 
+        /* Power off */
+        bnx2x_set_power_state(bp, PCI_D3hot);
+
         /* Make sure RESET task is not scheduled before continuing */
         cancel_delayed_work_sync(&bp->reset_task);
 
diff --git a/drivers/net/bnx2x/bnx2x_reg.h b/drivers/net/bnx2x/bnx2x_reg.h
index bfd875b72906..38ef7ca9f21d 100644
--- a/drivers/net/bnx2x/bnx2x_reg.h
+++ b/drivers/net/bnx2x/bnx2x_reg.h
@@ -18,6 +18,8 @@
  * WR - Write Clear (write 1 to clear the bit)
  *
  */
+#ifndef BNX2X_REG_H
+#define BNX2X_REG_H
 
 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR                        (0x1<<0)
 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS                (0x1<<2)
@@ -39,6 +41,8 @@
 #define BRB1_REG_BRB1_PRTY_MASK                                  0x60138
 /* [R 4] Parity register #0 read */
 #define BRB1_REG_BRB1_PRTY_STS                                   0x6012c
+/* [RC 4] Parity register #0 read clear */
+#define BRB1_REG_BRB1_PRTY_STS_CLR                               0x60130
 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
  * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
  * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
@@ -132,8 +136,12 @@
 #define CCM_REG_CCM_INT_MASK                                     0xd01e4
 /* [R 11] Interrupt register #0 read */
 #define CCM_REG_CCM_INT_STS                                      0xd01d8
+/* [RW 27] Parity mask register #0 read/write */
+#define CCM_REG_CCM_PRTY_MASK                                    0xd01f4
 /* [R 27] Parity register #0 read */
 #define CCM_REG_CCM_PRTY_STS                                     0xd01e8
+/* [RC 27] Parity register #0 read clear */
+#define CCM_REG_CCM_PRTY_STS_CLR                                 0xd01ec
 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
    REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
    Is used to determine the number of the AG context REG-pairs written back;
@@ -350,6 +358,8 @@
 #define CDU_REG_CDU_PRTY_MASK                                    0x10104c
 /* [R 5] Parity register #0 read */
 #define CDU_REG_CDU_PRTY_STS                                     0x101040
+/* [RC 5] Parity register #0 read clear */
+#define CDU_REG_CDU_PRTY_STS_CLR                                 0x101044
 /* [RC 32] logging of error data in case of a CDU load error:
    {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
    ype_error; ctual_active; ctual_compressed_context}; */
@@ -381,6 +391,8 @@
 #define CFC_REG_CFC_PRTY_MASK                                    0x104118
 /* [R 4] Parity register #0 read */
 #define CFC_REG_CFC_PRTY_STS                                     0x10410c
+/* [RC 4] Parity register #0 read clear */
+#define CFC_REG_CFC_PRTY_STS_CLR                                 0x104110
 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
 #define CFC_REG_CID_CAM                                          0x104800
 #define CFC_REG_CONTROL0                                         0x104028
@@ -466,6 +478,8 @@
 #define CSDM_REG_CSDM_PRTY_MASK                                  0xc22bc
 /* [R 11] Parity register #0 read */
 #define CSDM_REG_CSDM_PRTY_STS                                   0xc22b0
+/* [RC 11] Parity register #0 read clear */
+#define CSDM_REG_CSDM_PRTY_STS_CLR                               0xc22b4
 #define CSDM_REG_ENABLE_IN1                                      0xc2238
 #define CSDM_REG_ENABLE_IN2                                      0xc223c
 #define CSDM_REG_ENABLE_OUT1                                     0xc2240
@@ -556,6 +570,9 @@
 /* [R 32] Parity register #0 read */
 #define CSEM_REG_CSEM_PRTY_STS_0                                 0x200124
 #define CSEM_REG_CSEM_PRTY_STS_1                                 0x200134
+/* [RC 32] Parity register #0 read clear */
+#define CSEM_REG_CSEM_PRTY_STS_CLR_0                             0x200128
+#define CSEM_REG_CSEM_PRTY_STS_CLR_1                             0x200138
 #define CSEM_REG_ENABLE_IN                                       0x2000a4
 #define CSEM_REG_ENABLE_OUT                                      0x2000a8
 /* [RW 32] This address space contains all registers and memories that are
@@ -648,6 +665,8 @@
 #define DBG_REG_DBG_PRTY_MASK                                    0xc0a8
 /* [R 1] Parity register #0 read */
 #define DBG_REG_DBG_PRTY_STS                                     0xc09c
+/* [RC 1] Parity register #0 read clear */
+#define DBG_REG_DBG_PRTY_STS_CLR                                 0xc0a0
 /* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The
  * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;
  * 4.Completion function=0; 5.Error handling=0 */
@@ -668,6 +687,8 @@
 #define DMAE_REG_DMAE_PRTY_MASK                                  0x102064
 /* [R 4] Parity register #0 read */
 #define DMAE_REG_DMAE_PRTY_STS                                   0x102058
+/* [RC 4] Parity register #0 read clear */
+#define DMAE_REG_DMAE_PRTY_STS_CLR                               0x10205c
 /* [RW 1] Command 0 go. */
 #define DMAE_REG_GO_C0                                           0x102080
 /* [RW 1] Command 1 go. */
@@ -734,6 +755,8 @@
 #define DORQ_REG_DORQ_PRTY_MASK                                  0x170190
 /* [R 2] Parity register #0 read */
 #define DORQ_REG_DORQ_PRTY_STS                                   0x170184
+/* [RC 2] Parity register #0 read clear */
+#define DORQ_REG_DORQ_PRTY_STS_CLR                               0x170188
 /* [RW 8] The address to write the DPM CID to STORM. */
 #define DORQ_REG_DPM_CID_ADDR                                    0x170044
 /* [RW 5] The DPM mode CID extraction offset. */
@@ -842,8 +865,12 @@
 /* [R 1] data availble for error memory. If this bit is clear do not red
  * from error_handling_memory. */
 #define IGU_REG_ERROR_HANDLING_DATA_VALID                        0x130130
+/* [RW 11] Parity mask register #0 read/write */
+#define IGU_REG_IGU_PRTY_MASK                                    0x1300a8
 /* [R 11] Parity register #0 read */
 #define IGU_REG_IGU_PRTY_STS                                     0x13009c
+/* [RC 11] Parity register #0 read clear */
+#define IGU_REG_IGU_PRTY_STS_CLR                                 0x1300a0
 /* [R 4] Debug: int_handle_fsm */
 #define IGU_REG_INT_HANDLE_FSM                                   0x130050
 #define IGU_REG_LEADING_EDGE_LATCH                               0x130134
@@ -1501,6 +1528,8 @@
 #define MISC_REG_MISC_PRTY_MASK                                  0xa398
 /* [R 1] Parity register #0 read */
 #define MISC_REG_MISC_PRTY_STS                                   0xa38c
+/* [RC 1] Parity register #0 read clear */
+#define MISC_REG_MISC_PRTY_STS_CLR                               0xa390
 #define MISC_REG_NIG_WOL_P0                                      0xa270
 #define MISC_REG_NIG_WOL_P1                                      0xa274
 /* [R 1] If set indicate that the pcie_rst_b was asserted without perst
@@ -2082,6 +2111,10 @@
 #define PBF_REG_PBF_INT_MASK                                     0x1401d4
 /* [R 5] Interrupt register #0 read */
 #define PBF_REG_PBF_INT_STS                                      0x1401c8
+/* [RW 20] Parity mask register #0 read/write */
+#define PBF_REG_PBF_PRTY_MASK                                    0x1401e4
+/* [RC 20] Parity register #0 read clear */
+#define PBF_REG_PBF_PRTY_STS_CLR                                 0x1401dc
 #define PB_REG_CONTROL                                           0
 /* [RW 2] Interrupt mask register #0 read/write */
 #define PB_REG_PB_INT_MASK                                       0x28
@@ -2091,6 +2124,8 @@
 #define PB_REG_PB_PRTY_MASK                                      0x38
 /* [R 4] Parity register #0 read */
 #define PB_REG_PB_PRTY_STS                                       0x2c
+/* [RC 4] Parity register #0 read clear */
+#define PB_REG_PB_PRTY_STS_CLR                                   0x30
 #define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR                (0x1<<0)
 #define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW        (0x1<<8)
 #define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR       (0x1<<1)
@@ -2446,6 +2481,8 @@
 #define PRS_REG_PRS_PRTY_MASK                                    0x401a4
 /* [R 8] Parity register #0 read */
 #define PRS_REG_PRS_PRTY_STS                                     0x40198
+/* [RC 8] Parity register #0 read clear */
+#define PRS_REG_PRS_PRTY_STS_CLR                                 0x4019c
 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load
    request message */
 #define PRS_REG_PURE_REGIONS                                     0x40024
@@ -2599,6 +2636,9 @@
 /* [R 32] Parity register #0 read */
 #define PXP2_REG_PXP2_PRTY_STS_0                                 0x12057c
 #define PXP2_REG_PXP2_PRTY_STS_1                                 0x12058c
+/* [RC 32] Parity register #0 read clear */
+#define PXP2_REG_PXP2_PRTY_STS_CLR_0                             0x120580
+#define PXP2_REG_PXP2_PRTY_STS_CLR_1                             0x120590
 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives
    indication about backpressure) */
 #define PXP2_REG_RD_ALMOST_FULL_0                                0x120424
@@ -3001,6 +3041,8 @@
 #define PXP_REG_PXP_PRTY_MASK                                    0x103094
 /* [R 26] Parity register #0 read */
 #define PXP_REG_PXP_PRTY_STS                                     0x103088
+/* [RC 27] Parity register #0 read clear */
+#define PXP_REG_PXP_PRTY_STS_CLR                                 0x10308c
 /* [RW 4] The activity counter initial increment value sent in the load
    request */
 #define QM_REG_ACTCTRINITVAL_0                                   0x168040
@@ -3157,6 +3199,8 @@
 #define QM_REG_QM_PRTY_MASK                                      0x168454
 /* [R 12] Parity register #0 read */
 #define QM_REG_QM_PRTY_STS                                       0x168448
+/* [RC 12] Parity register #0 read clear */
+#define QM_REG_QM_PRTY_STS_CLR                                   0x16844c
 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */
 #define QM_REG_QSTATUS_HIGH                                      0x16802c
 /* [R 32] Current queues in pipeline: Queues from 96 to 127 */
@@ -3442,6 +3486,8 @@
 #define QM_REG_WRRWEIGHTS_9                                      0x168848
 /* [R 6] Keep the fill level of the fifo from write client 1 */
 #define QM_REG_XQM_WRC_FIFOLVL                                   0x168000
+/* [W 1] reset to parity interrupt */
+#define SEM_FAST_REG_PARITY_RST                                  0x18840
 #define SRC_REG_COUNTFREE0                                       0x40500
 /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
    ports. If set the searcher support 8 functions. */
@@ -3470,6 +3516,8 @@
 #define SRC_REG_SRC_PRTY_MASK                                    0x404c8
 /* [R 3] Parity register #0 read */
 #define SRC_REG_SRC_PRTY_STS                                     0x404bc
+/* [RC 3] Parity register #0 read clear */
+#define SRC_REG_SRC_PRTY_STS_CLR                                 0x404c0
 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
 #define TCM_REG_CAM_OCCUP                                        0x5017c
 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
@@ -3596,8 +3644,12 @@
 #define TCM_REG_TCM_INT_MASK                                     0x501dc
 /* [R 11] Interrupt register #0 read */
 #define TCM_REG_TCM_INT_STS                                      0x501d0
+/* [RW 27] Parity mask register #0 read/write */
+#define TCM_REG_TCM_PRTY_MASK                                    0x501ec
 /* [R 27] Parity register #0 read */
 #define TCM_REG_TCM_PRTY_STS                                     0x501e0
+/* [RC 27] Parity register #0 read clear */
+#define TCM_REG_TCM_PRTY_STS_CLR                                 0x501e4
 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
    REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
    Is used to determine the number of the AG context REG-pairs written back;
@@ -3755,6 +3807,10 @@
 #define TM_REG_TM_INT_MASK                                       0x1640fc
 /* [R 1] Interrupt register #0 read */
 #define TM_REG_TM_INT_STS                                        0x1640f0
+/* [RW 7] Parity mask register #0 read/write */
+#define TM_REG_TM_PRTY_MASK                                      0x16410c
+/* [RC 7] Parity register #0 read clear */
+#define TM_REG_TM_PRTY_STS_CLR                                   0x164104
 /* [RW 8] The event id for aggregated interrupt 0 */
 #define TSDM_REG_AGG_INT_EVENT_0                                 0x42038
 #define TSDM_REG_AGG_INT_EVENT_1                                 0x4203c
@@ -3835,6 +3891,8 @@
 #define TSDM_REG_TSDM_PRTY_MASK                                  0x422bc
 /* [R 11] Parity register #0 read */
 #define TSDM_REG_TSDM_PRTY_STS                                   0x422b0
+/* [RC 11] Parity register #0 read clear */
+#define TSDM_REG_TSDM_PRTY_STS_CLR                               0x422b4
 /* [RW 5] The number of time_slots in the arbitration cycle */
 #define TSEM_REG_ARB_CYCLE_SIZE                                  0x180034
 /* [RW 3] The source that is associated with arbitration element 0. Source
@@ -3914,6 +3972,9 @@
 #define TSEM_REG_SLOW_EXT_STORE_EMPTY                            0x1802a0
 /* [RW 8] List of free threads . There is a bit per thread. */
 #define TSEM_REG_THREADS_LIST                                    0x1802e4
+/* [RC 32] Parity register #0 read clear */
+#define TSEM_REG_TSEM_PRTY_STS_CLR_0                             0x180118
+#define TSEM_REG_TSEM_PRTY_STS_CLR_1                             0x180128
 /* [RW 3] The arbitration scheme of time_slot 0 */
 #define TSEM_REG_TS_0_AS                                         0x180038
 /* [RW 3] The arbitration scheme of time_slot 10 */
@@ -4116,6 +4177,8 @@
 #define UCM_REG_UCM_INT_STS                                      0xe01c8
 /* [R 27] Parity register #0 read */
 #define UCM_REG_UCM_PRTY_STS                                     0xe01d8
+/* [RC 27] Parity register #0 read clear */
+#define UCM_REG_UCM_PRTY_STS_CLR                                 0xe01dc
 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
    REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
    Is used to determine the number of the AG context REG-pairs written back;
@@ -4292,6 +4355,8 @@
 #define USDM_REG_USDM_PRTY_MASK                                  0xc42c0
 /* [R 11] Parity register #0 read */
 #define USDM_REG_USDM_PRTY_STS                                   0xc42b4
+/* [RC 11] Parity register #0 read clear */
+#define USDM_REG_USDM_PRTY_STS_CLR                               0xc42b8
 /* [RW 5] The number of time_slots in the arbitration cycle */
 #define USEM_REG_ARB_CYCLE_SIZE                                  0x300034
 /* [RW 3] The source that is associated with arbitration element 0. Source
@@ -4421,6 +4486,9 @@
 /* [R 32] Parity register #0 read */
 #define USEM_REG_USEM_PRTY_STS_0                                 0x300124
 #define USEM_REG_USEM_PRTY_STS_1                                 0x300134
+/* [RC 32] Parity register #0 read clear */
+#define USEM_REG_USEM_PRTY_STS_CLR_0                             0x300128
+#define USEM_REG_USEM_PRTY_STS_CLR_1                             0x300138
 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
  * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
 #define USEM_REG_VFPF_ERR_NUM                                    0x300380
@@ -4797,6 +4865,8 @@
 #define XSDM_REG_XSDM_PRTY_MASK                                  0x1662bc
 /* [R 11] Parity register #0 read */
 #define XSDM_REG_XSDM_PRTY_STS                                   0x1662b0
+/* [RC 11] Parity register #0 read clear */
+#define XSDM_REG_XSDM_PRTY_STS_CLR                               0x1662b4
 /* [RW 5] The number of time_slots in the arbitration cycle */
 #define XSEM_REG_ARB_CYCLE_SIZE                                  0x280034
 /* [RW 3] The source that is associated with arbitration element 0. Source
@@ -4929,6 +4999,9 @@
 /* [R 32] Parity register #0 read */
 #define XSEM_REG_XSEM_PRTY_STS_0                                 0x280124
 #define XSEM_REG_XSEM_PRTY_STS_1                                 0x280134
+/* [RC 32] Parity register #0 read clear */
+#define XSEM_REG_XSEM_PRTY_STS_CLR_0                             0x280128
+#define XSEM_REG_XSEM_PRTY_STS_CLR_1                             0x280138
 #define MCPR_NVM_ACCESS_ENABLE_EN                                (1L<<0)
 #define MCPR_NVM_ACCESS_ENABLE_WR_EN                             (1L<<1)
 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE                             (0xffffffL<<0)
@@ -6316,3 +6389,4 @@ static inline u8 calc_crc8(u32 data, u8 crc)
 }
 
 
+#endif /* BNX2X_REG_H */
diff --git a/drivers/net/bnx2x/bnx2x_stats.c b/drivers/net/bnx2x/bnx2x_stats.c
index 6e4d9b144cc4..bda60d590fa8 100644
--- a/drivers/net/bnx2x/bnx2x_stats.c
+++ b/drivers/net/bnx2x/bnx2x_stats.c
@@ -158,6 +158,11 @@ static void bnx2x_storm_stats_post(struct bnx2x *bp)
 
                 spin_lock_bh(&bp->stats_lock);
 
+                if (bp->stats_pending) {
+                        spin_unlock_bh(&bp->stats_lock);
+                        return;
+                }
+
                 ramrod_data.drv_counter = bp->stats_counter++;
                 ramrod_data.collect_port = bp->port.pmf ? 1 : 0;
                 for_each_eth_queue(bp, i)
diff --git a/drivers/net/cxgb4vf/cxgb4vf_main.c b/drivers/net/cxgb4vf/cxgb4vf_main.c
index 3c403f895750..56166ae2059f 100644
--- a/drivers/net/cxgb4vf/cxgb4vf_main.c
+++ b/drivers/net/cxgb4vf/cxgb4vf_main.c
@@ -749,13 +749,19 @@ static int cxgb4vf_open(struct net_device *dev)
         netif_set_real_num_tx_queues(dev, pi->nqsets);
         err = netif_set_real_num_rx_queues(dev, pi->nqsets);
         if (err)
-                return err;
-        set_bit(pi->port_id, &adapter->open_device_map);
+                goto err_unwind;
         err = link_start(dev);
         if (err)
-                return err;
+                goto err_unwind;
+
         netif_tx_start_all_queues(dev);
+        set_bit(pi->port_id, &adapter->open_device_map);
         return 0;
+
+err_unwind:
+        if (adapter->open_device_map == 0)
+                adapter_down(adapter);
+        return err;
 }
 
 /*
@@ -764,13 +770,12 @@ static int cxgb4vf_open(struct net_device *dev)
  */
 static int cxgb4vf_stop(struct net_device *dev)
 {
-        int ret;
         struct port_info *pi = netdev_priv(dev);
         struct adapter *adapter = pi->adapter;
 
         netif_tx_stop_all_queues(dev);
         netif_carrier_off(dev);
-        ret = t4vf_enable_vi(adapter, pi->viid, false, false);
+        t4vf_enable_vi(adapter, pi->viid, false, false);
         pi->link_cfg.link_ok = 0;
 
         clear_bit(pi->port_id, &adapter->open_device_map);
diff --git a/drivers/net/cxgb4vf/t4vf_hw.c b/drivers/net/cxgb4vf/t4vf_hw.c
index e4bec78c8e3f..0f51c80475ce 100644
--- a/drivers/net/cxgb4vf/t4vf_hw.c
+++ b/drivers/net/cxgb4vf/t4vf_hw.c
@@ -147,9 +147,20 @@ int t4vf_wr_mbox_core(struct adapter *adapter, const void *cmd, int size,
         /*
          * Write the command array into the Mailbox Data register array and
          * transfer ownership of the mailbox to the firmware.
+         *
+         * For the VFs, the Mailbox Data "registers" are actually backed by
+         * T4's "MA" interface rather than PL Registers (as is the case for
+         * the PFs).  Because these are in different coherency domains, the
+         * write to the VF's PL-register-backed Mailbox Control can race in
+         * front of the writes to the MA-backed VF Mailbox Data "registers".
+         * So we need to do a read-back on at least one byte of the VF Mailbox
+         * Data registers before doing the write to the VF Mailbox Control
+         * register.
          */
         for (i = 0, p = cmd; i < size; i += 8)
                 t4_write_reg64(adapter, mbox_data + i, be64_to_cpu(*p++));
+        t4_read_reg(adapter, mbox_data);         /* flush write */
+
         t4_write_reg(adapter, mbox_ctl,
                      MBMSGVALID | MBOWNER(MBOX_OWNER_FW));
         t4_read_reg(adapter, mbox_ctl);          /* flush write */
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 77d08e697b74..aed223b1b897 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -130,10 +130,15 @@ static s32 e1000_set_phy_type(struct e1000_hw *hw)
                 if (hw->mac_type == e1000_82541 ||
                     hw->mac_type == e1000_82541_rev_2 ||
                     hw->mac_type == e1000_82547 ||
-                    hw->mac_type == e1000_82547_rev_2) {
+                    hw->mac_type == e1000_82547_rev_2)
                         hw->phy_type = e1000_phy_igp;
-                        break;
-                }
+                break;
+        case RTL8211B_PHY_ID:
+                hw->phy_type = e1000_phy_8211;
+                break;
+        case RTL8201N_PHY_ID:
+                hw->phy_type = e1000_phy_8201;
+                break;
         default:
                 /* Should never have loaded on this device */
                 hw->phy_type = e1000_phy_undefined;
@@ -318,6 +323,9 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
         case E1000_DEV_ID_82547GI:
                 hw->mac_type = e1000_82547_rev_2;
                 break;
+        case E1000_DEV_ID_INTEL_CE4100_GBE:
+                hw->mac_type = e1000_ce4100;
+                break;
         default:
                 /* Should never have loaded on this device */
                 return -E1000_ERR_MAC_TYPE;
@@ -372,6 +380,9 @@ void e1000_set_media_type(struct e1000_hw *hw)
                 case e1000_82542_rev2_1:
                         hw->media_type = e1000_media_type_fiber;
                         break;
+                case e1000_ce4100:
+                        hw->media_type = e1000_media_type_copper;
+                        break;
                 default:
                         status = er32(STATUS);
                         if (status & E1000_STATUS_TBIMODE) {
@@ -460,6 +471,7 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
                 /* Reset is performed on a shadow of the control register */
                 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
                 break;
+        case e1000_ce4100:
         default:
                 ew32(CTRL, (ctrl | E1000_CTRL_RST));
                 break;
@@ -952,6 +964,67 @@ static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
 }
 
 /**
+ * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series.
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Commits changes to PHY configuration by calling e1000_phy_reset().
+ */
+static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw)
+{
+        s32 ret_val;
+
+        /* SW reset the PHY so all changes take effect */
+        ret_val = e1000_phy_reset(hw);
+        if (ret_val) {
+                e_dbg("Error Resetting the PHY\n");
+                return ret_val;
+        }
+
+        return E1000_SUCCESS;
+}
+
+static s32 gbe_dhg_phy_setup(struct e1000_hw *hw)
+{
+        s32 ret_val;
+        u32 ctrl_aux;
+
+        switch (hw->phy_type) {
+        case e1000_phy_8211:
+                ret_val = e1000_copper_link_rtl_setup(hw);
+                if (ret_val) {
+                        e_dbg("e1000_copper_link_rtl_setup failed!\n");
+                        return ret_val;
+                }
+                break;
+        case e1000_phy_8201:
+                /* Set RMII mode */
+                ctrl_aux = er32(CTL_AUX);
+                ctrl_aux |= E1000_CTL_AUX_RMII;
+                ew32(CTL_AUX, ctrl_aux);
+                E1000_WRITE_FLUSH();
+
+                /* Disable the J/K bits required for receive */
+                ctrl_aux = er32(CTL_AUX);
+                ctrl_aux |= 0x4;
+                ctrl_aux &= ~0x2;
+                ew32(CTL_AUX, ctrl_aux);
+                E1000_WRITE_FLUSH();
+                ret_val = e1000_copper_link_rtl_setup(hw);
+
+                if (ret_val) {
+                        e_dbg("e1000_copper_link_rtl_setup failed!\n");
+                        return ret_val;
+                }
+                break;
+        default:
+                e_dbg("Error Resetting the PHY\n");
+                return E1000_ERR_PHY_TYPE;
+        }
+
+        return E1000_SUCCESS;
+}
+
+/**
  * e1000_copper_link_preconfig - early configuration for copper
  * @hw: Struct containing variables accessed by shared code
  *
@@ -1286,6 +1359,10 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
         if (hw->autoneg_advertised == 0)
                 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 
+        /* IFE/RTL8201N PHY only supports 10/100 */
+        if (hw->phy_type == e1000_phy_8201)
+                hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
+
         e_dbg("Reconfiguring auto-neg advertisement params\n");
         ret_val = e1000_phy_setup_autoneg(hw);
         if (ret_val) {
@@ -1341,7 +1418,7 @@ static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
         s32 ret_val;
         e_dbg("e1000_copper_link_postconfig");
 
-        if (hw->mac_type >= e1000_82544) {
+        if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) {
                 e1000_config_collision_dist(hw);
         } else {
                 ret_val = e1000_config_mac_to_phy(hw);
@@ -1395,6 +1472,12 @@ static s32 e1000_setup_copper_link(struct e1000_hw *hw)
                 ret_val = e1000_copper_link_mgp_setup(hw);
                 if (ret_val)
                         return ret_val;
+        } else {
+                ret_val = gbe_dhg_phy_setup(hw);
+                if (ret_val) {
+                        e_dbg("gbe_dhg_phy_setup failed!\n");
+                        return ret_val;
+                }
         }
 
         if (hw->autoneg) {
@@ -1461,10 +1544,11 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
                 return ret_val;
 
         /* Read the MII 1000Base-T Control Register (Address 9). */
-        ret_val =
-            e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
+        ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
         if (ret_val)
                 return ret_val;
+        else if (hw->phy_type == e1000_phy_8201)
+                mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
 
         /* Need to parse both autoneg_advertised and fc and set up
          * the appropriate PHY registers.  First we will parse for
@@ -1577,9 +1661,14 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
 
         e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
 
-        ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
-        if (ret_val)
-                return ret_val;
+        if (hw->phy_type == e1000_phy_8201) {
+                mii_1000t_ctrl_reg = 0;
+        } else {
+                ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
+                                              mii_1000t_ctrl_reg);
+                if (ret_val)
+                        return ret_val;
+        }
 
         return E1000_SUCCESS;
 }
@@ -1860,7 +1949,7 @@ static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
 
         /* 82544 or newer MAC, Auto Speed Detection takes care of
          * MAC speed/duplex configuration.*/
-        if (hw->mac_type >= e1000_82544)
+        if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100))
                 return E1000_SUCCESS;
 
         /* Read the Device Control Register and set the bits to Force Speed
@@ -1870,27 +1959,49 @@ static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
         ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
 
-        /* Set up duplex in the Device Control and Transmit Control
-         * registers depending on negotiated values.
-         */
-        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
-        if (ret_val)
-                return ret_val;
+        switch (hw->phy_type) {
+        case e1000_phy_8201:
+                ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
+                if (ret_val)
+                        return ret_val;
 
-        if (phy_data & M88E1000_PSSR_DPLX)
-                ctrl |= E1000_CTRL_FD;
-        else
-                ctrl &= ~E1000_CTRL_FD;
+                if (phy_data & RTL_PHY_CTRL_FD)
+                        ctrl |= E1000_CTRL_FD;
+                else
+                        ctrl &= ~E1000_CTRL_FD;
 
-        e1000_config_collision_dist(hw);
+                if (phy_data & RTL_PHY_CTRL_SPD_100)
+                        ctrl |= E1000_CTRL_SPD_100;
+                else
+                        ctrl |= E1000_CTRL_SPD_10;
 
-        /* Set up speed in the Device Control register depending on
-         * negotiated values.
-         */
-        if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
-                ctrl |= E1000_CTRL_SPD_1000;
-        else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
-                ctrl |= E1000_CTRL_SPD_100;
+                e1000_config_collision_dist(hw);
+                break;
+        default:
+                /* Set up duplex in the Device Control and Transmit Control
+                 * registers depending on negotiated values.
+                 */
+                ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
+                                             &phy_data);
+                if (ret_val)
+                        return ret_val;
+
+                if (phy_data & M88E1000_PSSR_DPLX)
+                        ctrl |= E1000_CTRL_FD;
+                else
+                        ctrl &= ~E1000_CTRL_FD;
+
+                e1000_config_collision_dist(hw);
+
+                /* Set up speed in the Device Control register depending on
+                 * negotiated values.
+                 */
+                if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
+                        ctrl |= E1000_CTRL_SPD_1000;
+                else if ((phy_data & M88E1000_PSSR_SPEED) ==
+                         M88E1000_PSSR_100MBS)
+                        ctrl |= E1000_CTRL_SPD_100;
+        }
 
         /* Write the configured values back to the Device Control Reg. */
         ew32(CTRL, ctrl);
@@ -2401,7 +2512,8 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
                  * speed/duplex on the MAC to the current PHY speed/duplex
                  * settings.
                  */
-                if (hw->mac_type >= e1000_82544)
+                if ((hw->mac_type >= e1000_82544) &&
+                    (hw->mac_type != e1000_ce4100))
                         e1000_config_collision_dist(hw);
                 else {
                         ret_val = e1000_config_mac_to_phy(hw);
@@ -2738,7 +2850,7 @@ static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
 {
         u32 i;
         u32 mdic = 0;
-        const u32 phy_addr = 1;
+        const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
 
         e_dbg("e1000_read_phy_reg_ex");
 
@@ -2752,28 +2864,61 @@ static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
                  * Control register.  The MAC will take care of interfacing with the
                  * PHY to retrieve the desired data.
                  */
-                mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
-                        (phy_addr << E1000_MDIC_PHY_SHIFT) |
-                        (E1000_MDIC_OP_READ));
+                if (hw->mac_type == e1000_ce4100) {
+                        mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
+                                (phy_addr << E1000_MDIC_PHY_SHIFT) |
+                                (INTEL_CE_GBE_MDIC_OP_READ) |
+                                (INTEL_CE_GBE_MDIC_GO));
 
-                ew32(MDIC, mdic);
+                        writel(mdic, E1000_MDIO_CMD);
 
-                /* Poll the ready bit to see if the MDI read completed */
-                for (i = 0; i < 64; i++) {
-                        udelay(50);
-                        mdic = er32(MDIC);
-                        if (mdic & E1000_MDIC_READY)
-                                break;
-                }
-                if (!(mdic & E1000_MDIC_READY)) {
-                        e_dbg("MDI Read did not complete\n");
-                        return -E1000_ERR_PHY;
-                }
-                if (mdic & E1000_MDIC_ERROR) {
-                        e_dbg("MDI Error\n");
-                        return -E1000_ERR_PHY;
+                        /* Poll the ready bit to see if the MDI read
+                         * completed
+                         */
+                        for (i = 0; i < 64; i++) {
+                                udelay(50);
+                                mdic = readl(E1000_MDIO_CMD);
+                                if (!(mdic & INTEL_CE_GBE_MDIC_GO))
+                                        break;
+                        }
+
+                        if (mdic & INTEL_CE_GBE_MDIC_GO) {
+                                e_dbg("MDI Read did not complete\n");
+                                return -E1000_ERR_PHY;
+                        }
+
+                        mdic = readl(E1000_MDIO_STS);
+                        if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) {
+                                e_dbg("MDI Read Error\n");
+                                return -E1000_ERR_PHY;
+                        }
+                        *phy_data = (u16) mdic;
+                } else {
+                        mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
+                                (phy_addr << E1000_MDIC_PHY_SHIFT) |
+                                (E1000_MDIC_OP_READ));
+
+                        ew32(MDIC, mdic);
+
+                        /* Poll the ready bit to see if the MDI read
+                         * completed
+                         */
+                        for (i = 0; i < 64; i++) {
+                                udelay(50);
+                                mdic = er32(MDIC);
+                                if (mdic & E1000_MDIC_READY)
+                                        break;
+                        }
+                        if (!(mdic & E1000_MDIC_READY)) {
+                                e_dbg("MDI Read did not complete\n");
+                                return -E1000_ERR_PHY;
+                        }
+                        if (mdic & E1000_MDIC_ERROR) {
+                                e_dbg("MDI Error\n");
+                                return -E1000_ERR_PHY;
+                        }
+                        *phy_data = (u16) mdic;
                 }
-                *phy_data = (u16) mdic;
         } else {
                 /* We must first send a preamble through the MDIO pin to signal the
                  * beginning of an MII instruction.  This is done by sending 32
@@ -2840,7 +2985,7 @@ static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
 {
         u32 i;
         u32 mdic = 0;
-        const u32 phy_addr = 1;
+        const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
 
         e_dbg("e1000_write_phy_reg_ex");
 
@@ -2850,27 +2995,54 @@ static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
         }
 
         if (hw->mac_type > e1000_82543) {
-                /* Set up Op-code, Phy Address, register address, and data intended
-                 * for the PHY register in the MDI Control register.  The MAC will take
-                 * care of interfacing with the PHY to send the desired data.
+                /* Set up Op-code, Phy Address, register address, and data
+                 * intended for the PHY register in the MDI Control register.
+                 * The MAC will take care of interfacing with the PHY to send
+                 * the desired data.
                  */
-                mdic = (((u32) phy_data) |
-                        (reg_addr << E1000_MDIC_REG_SHIFT) |
-                        (phy_addr << E1000_MDIC_PHY_SHIFT) |
-                        (E1000_MDIC_OP_WRITE));
+                if (hw->mac_type == e1000_ce4100) {
+                        mdic = (((u32) phy_data) |
+                                (reg_addr << E1000_MDIC_REG_SHIFT) |
+                                (phy_addr << E1000_MDIC_PHY_SHIFT) |
+                                (INTEL_CE_GBE_MDIC_OP_WRITE) |
+                                (INTEL_CE_GBE_MDIC_GO));
 
-                ew32(MDIC, mdic);
+                        writel(mdic, E1000_MDIO_CMD);
 
-                /* Poll the ready bit to see if the MDI read completed */
-                for (i = 0; i < 641; i++) {
-                        udelay(5);
-                        mdic = er32(MDIC);
-                        if (mdic & E1000_MDIC_READY)
-                                break;
-                }
-                if (!(mdic & E1000_MDIC_READY)) {
-                        e_dbg("MDI Write did not complete\n");
-                        return -E1000_ERR_PHY;
+                        /* Poll the ready bit to see if the MDI read
+                         * completed
+                         */
+                        for (i = 0; i < 640; i++) {
+                                udelay(5);
+                                mdic = readl(E1000_MDIO_CMD);
+                                if (!(mdic & INTEL_CE_GBE_MDIC_GO))
+                                        break;
+                        }
+                        if (mdic & INTEL_CE_GBE_MDIC_GO) {
+                                e_dbg("MDI Write did not complete\n");
+                                return -E1000_ERR_PHY;
+                        }
+                } else {
+                        mdic = (((u32) phy_data) |
+                                (reg_addr << E1000_MDIC_REG_SHIFT) |
+                                (phy_addr << E1000_MDIC_PHY_SHIFT) |
+                                (E1000_MDIC_OP_WRITE));
+
+                        ew32(MDIC, mdic);
+
+                        /* Poll the ready bit to see if the MDI read
+                         * completed
+                         */
+                        for (i = 0; i < 641; i++) {
+                                udelay(5);
+                                mdic = er32(MDIC);
+                                if (mdic & E1000_MDIC_READY)
+                                        break;
+                        }
+                        if (!(mdic & E1000_MDIC_READY)) {
+                                e_dbg("MDI Write did not complete\n");
+                                return -E1000_ERR_PHY;
+                        }
                 }
         } else {
                 /* We'll need to use the SW defined pins to shift the write command
@@ -3048,6 +3220,11 @@ static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
                 if (hw->phy_id == M88E1011_I_PHY_ID)
                         match = true;
                 break;
+        case e1000_ce4100:
+                if ((hw->phy_id == RTL8211B_PHY_ID) ||
+                    (hw->phy_id == RTL8201N_PHY_ID))
+                        match = true;
+                break;
         case e1000_82541:
         case e1000_82541_rev_2:
         case e1000_82547:
@@ -3291,6 +3468,9 @@ s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
 
         if (hw->phy_type == e1000_phy_igp)
                 return e1000_phy_igp_get_info(hw, phy_info);
+        else if ((hw->phy_type == e1000_phy_8211) ||
+                 (hw->phy_type == e1000_phy_8201))
+                return E1000_SUCCESS;
         else
                 return e1000_phy_m88_get_info(hw, phy_info);
 }
@@ -3742,6 +3922,12 @@ static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
 
         e_dbg("e1000_read_eeprom");
 
+        if (hw->mac_type == e1000_ce4100) {
+                GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words,
+                                      data);
+                return E1000_SUCCESS;
+        }
+
         /* If eeprom is not yet detected, do so now */
         if (eeprom->word_size == 0)
                 e1000_init_eeprom_params(hw);
@@ -3904,6 +4090,12 @@ static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
 
         e_dbg("e1000_write_eeprom");
 
+        if (hw->mac_type == e1000_ce4100) {
+                GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words,
+                                       data);
+                return E1000_SUCCESS;
+        }
+
         /* If eeprom is not yet detected, do so now */
         if (eeprom->word_size == 0)
                 e1000_init_eeprom_params(hw);
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index ecd9f6c6bcd5..f5514a0d5be6 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -52,6 +52,7 @@ typedef enum {
         e1000_82545,
         e1000_82545_rev_3,
         e1000_82546,
+        e1000_ce4100,
         e1000_82546_rev_3,
         e1000_82541,
         e1000_82541_rev_2,
@@ -209,9 +210,11 @@ typedef enum {
 } e1000_1000t_rx_status;
 
 typedef enum {
-    e1000_phy_m88 = 0,
-    e1000_phy_igp,
-    e1000_phy_undefined = 0xFF
+        e1000_phy_m88 = 0,
+        e1000_phy_igp,
+        e1000_phy_8211,
+        e1000_phy_8201,
+        e1000_phy_undefined = 0xFF
 } e1000_phy_type;
 
 typedef enum {
@@ -442,6 +445,7 @@ void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
 #define E1000_DEV_ID_82547EI             0x1019
 #define E1000_DEV_ID_82547EI_MOBILE      0x101A
 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
+#define E1000_DEV_ID_INTEL_CE4100_GBE    0x2E6E
 
 #define NODE_ADDRESS_SIZE 6
 #define ETH_LENGTH_OF_ADDRESS 6
@@ -808,6 +812,16 @@ struct e1000_ffvt_entry {
 #define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
 #define E1000_FLA      0x0001C  /* Flash Access - RW */
 #define E1000_MDIC     0x00020  /* MDI Control - RW */
+
+extern void __iomem *ce4100_gbe_mdio_base_virt;
+#define INTEL_CE_GBE_MDIO_RCOMP_BASE    (ce4100_gbe_mdio_base_virt)
+#define E1000_MDIO_STS  (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0)
+#define E1000_MDIO_CMD  (INTEL_CE_GBE_MDIO_RCOMP_BASE + 4)
+#define E1000_MDIO_DRV  (INTEL_CE_GBE_MDIO_RCOMP_BASE + 8)
+#define E1000_MDC_CMD   (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0xC)
+#define E1000_RCOMP_CTL (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0x20)
+#define E1000_RCOMP_STS (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0x24)
+
 #define E1000_SCTL     0x00024  /* SerDes Control - RW */
 #define E1000_FEXTNVM  0x00028  /* Future Extended NVM register */
 #define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
@@ -820,6 +834,34 @@ struct e1000_ffvt_entry {
 #define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
 #define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
 #define E1000_IAM      0x000E0  /* Interrupt Acknowledge Auto Mask */
+
+/* Auxiliary Control Register. This register is CE4100 specific,
+ * RMII/RGMII function is switched by this register - RW
+ * Following are bits definitions of the Auxiliary Control Register
+ */
+#define E1000_CTL_AUX  0x000E0
+#define E1000_CTL_AUX_END_SEL_SHIFT     10
+#define E1000_CTL_AUX_ENDIANESS_SHIFT   8
+#define E1000_CTL_AUX_RGMII_RMII_SHIFT  0
+
+/* descriptor and packet transfer use CTL_AUX.ENDIANESS */
+#define E1000_CTL_AUX_DES_PKT   (0x0 << E1000_CTL_AUX_END_SEL_SHIFT)
+/* descriptor use CTL_AUX.ENDIANESS, packet use default */
+#define E1000_CTL_AUX_DES       (0x1 << E1000_CTL_AUX_END_SEL_SHIFT)
+/* descriptor use default, packet use CTL_AUX.ENDIANESS */
+#define E1000_CTL_AUX_PKT       (0x2 << E1000_CTL_AUX_END_SEL_SHIFT)
+/* all use CTL_AUX.ENDIANESS */
+#define E1000_CTL_AUX_ALL       (0x3 << E1000_CTL_AUX_END_SEL_SHIFT)
+
+#define E1000_CTL_AUX_RGMII     (0x0 << E1000_CTL_AUX_RGMII_RMII_SHIFT)
+#define E1000_CTL_AUX_RMII      (0x1 << E1000_CTL_AUX_RGMII_RMII_SHIFT)
+
+/* LW little endian, Byte big endian */
+#define E1000_CTL_AUX_LWLE_BBE  (0x0 << E1000_CTL_AUX_ENDIANESS_SHIFT)
+#define E1000_CTL_AUX_LWLE_BLE  (0x1 << E1000_CTL_AUX_ENDIANESS_SHIFT)
+#define E1000_CTL_AUX_LWBE_BBE  (0x2 << E1000_CTL_AUX_ENDIANESS_SHIFT)
+#define E1000_CTL_AUX_LWBE_BLE  (0x3 << E1000_CTL_AUX_ENDIANESS_SHIFT)
+
 #define E1000_RCTL     0x00100  /* RX Control - RW */
 #define E1000_RDTR1    0x02820  /* RX Delay Timer (1) - RW */
 #define E1000_RDBAL1   0x02900  /* RX Descriptor Base Address Low (1) - RW */
@@ -1011,6 +1053,7 @@ struct e1000_ffvt_entry {
  * in more current versions of the 8254x. Despite the difference in location,
  * the registers function in the same manner.
  */
+#define E1000_82542_CTL_AUX  E1000_CTL_AUX
 #define E1000_82542_CTRL     E1000_CTRL
 #define E1000_82542_CTRL_DUP E1000_CTRL_DUP
 #define E1000_82542_STATUS   E1000_STATUS
@@ -1571,6 +1614,11 @@ struct e1000_hw {
 #define E1000_MDIC_INT_EN    0x20000000
 #define E1000_MDIC_ERROR     0x40000000
 
+#define INTEL_CE_GBE_MDIC_OP_WRITE      0x04000000
+#define INTEL_CE_GBE_MDIC_OP_READ       0x00000000
+#define INTEL_CE_GBE_MDIC_GO            0x80000000
+#define INTEL_CE_GBE_MDIC_READ_ERROR    0x80000000
+
 #define E1000_KUMCTRLSTA_MASK           0x0000FFFF
 #define E1000_KUMCTRLSTA_OFFSET         0x001F0000
 #define E1000_KUMCTRLSTA_OFFSET_SHIFT   16
@@ -2871,6 +2919,11 @@ struct e1000_host_command_info {
 #define M88E1111_I_PHY_ID  0x01410CC0
 #define L1LXT971A_PHY_ID   0x001378E0
 
+#define RTL8211B_PHY_ID    0x001CC910
+#define RTL8201N_PHY_ID    0x8200
+#define RTL_PHY_CTRL_FD    0x0100 /* Full duplex.0=half; 1=full */
+#define RTL_PHY_CTRL_SPD_100    0x200000 /* Force 100Mb */
+
 /* Bits...
  * 15-5: page
  * 4-0: register offset
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index 340e12d2e4a9..4ff88a683f61 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -28,6 +28,12 @@
 
 #include "e1000.h"
 #include <net/ip6_checksum.h>
+#include <linux/io.h>
+
+/* Intel Media SOC GbE MDIO physical base address */
+static unsigned long ce4100_gbe_mdio_base_phy;
+/* Intel Media SOC GbE MDIO virtual base address */
+void __iomem *ce4100_gbe_mdio_base_virt;
 
 char e1000_driver_name[] = "e1000";
 static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
@@ -79,6 +85,7 @@ static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
         INTEL_E1000_ETHERNET_DEVICE(0x108A),
         INTEL_E1000_ETHERNET_DEVICE(0x1099),
         INTEL_E1000_ETHERNET_DEVICE(0x10B5),
+        INTEL_E1000_ETHERNET_DEVICE(0x2E6E),
         /* required last entry */
         {0,}
 };
@@ -459,6 +466,7 @@ static void e1000_power_down_phy(struct e1000_adapter *adapter)
                 case e1000_82545:
                 case e1000_82545_rev_3:
                 case e1000_82546:
+                case e1000_ce4100:
                 case e1000_82546_rev_3:
                 case e1000_82541:
                 case e1000_82541_rev_2:
@@ -573,6 +581,7 @@ void e1000_reset(struct e1000_adapter *adapter)
         case e1000_82545:
         case e1000_82545_rev_3:
         case e1000_82546:
+        case e1000_ce4100:
         case e1000_82546_rev_3:
                 pba = E1000_PBA_48K;
                 break;
@@ -894,6 +903,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
         static int global_quad_port_a = 0; /* global ksp3 port a indication */
         int i, err, pci_using_dac;
         u16 eeprom_data = 0;
+        u16 tmp = 0;
         u16 eeprom_apme_mask = E1000_EEPROM_APME;
         int bars, need_ioport;
 
@@ -996,6 +1006,14 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
                 goto err_sw_init;
 
         err = -EIO;
+        if (hw->mac_type == e1000_ce4100) {
+                ce4100_gbe_mdio_base_phy = pci_resource_start(pdev, BAR_1);
+                ce4100_gbe_mdio_base_virt = ioremap(ce4100_gbe_mdio_base_phy,
+                                                pci_resource_len(pdev, BAR_1));
+
+                if (!ce4100_gbe_mdio_base_virt)
+                        goto err_mdio_ioremap;
+        }
 
         if (hw->mac_type >= e1000_82543) {
                 netdev->features = NETIF_F_SG |
@@ -1135,6 +1153,20 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
         adapter->wol = adapter->eeprom_wol;
         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
 
+        /* Auto detect PHY address */
+        if (hw->mac_type == e1000_ce4100) {
+                for (i = 0; i < 32; i++) {
+                        hw->phy_addr = i;
+                        e1000_read_phy_reg(hw, PHY_ID2, &tmp);
+                        if (tmp == 0 || tmp == 0xFF) {
+                                if (i == 31)
+                                        goto err_eeprom;
+                                continue;
+                        } else
+                                break;
+                }
+        }
+
         /* reset the hardware with the new settings */
         e1000_reset(adapter);
 
@@ -1171,6 +1203,8 @@ err_eeprom:
         kfree(adapter->rx_ring);
 err_dma:
 err_sw_init:
+err_mdio_ioremap:
+        iounmap(ce4100_gbe_mdio_base_virt);
         iounmap(hw->hw_addr);
 err_ioremap:
         free_netdev(netdev);
@@ -1409,6 +1443,7 @@ static bool e1000_check_64k_bound(struct e1000_adapter *adapter, void *start,
         /* First rev 82545 and 82546 need to not allow any memory
          * write location to cross 64k boundary due to errata 23 */
         if (hw->mac_type == e1000_82545 ||
+            hw->mac_type == e1000_ce4100 ||
             hw->mac_type == e1000_82546) {
                 return ((begin ^ (end - 1)) >> 16) != 0 ? false : true;
         }
diff --git a/drivers/net/e1000/e1000_osdep.h b/drivers/net/e1000/e1000_osdep.h
index edd1c75aa895..55c1711f1688 100644
--- a/drivers/net/e1000/e1000_osdep.h
+++ b/drivers/net/e1000/e1000_osdep.h
@@ -34,12 +34,21 @@
 #ifndef _E1000_OSDEP_H_
 #define _E1000_OSDEP_H_
 
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/delay.h>
 #include <asm/io.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
+
+#define CONFIG_RAM_BASE         0x60000
+#define GBE_CONFIG_OFFSET       0x0
+
+#define GBE_CONFIG_RAM_BASE \
+        ((unsigned int)(CONFIG_RAM_BASE + GBE_CONFIG_OFFSET))
+
+#define GBE_CONFIG_BASE_VIRT    phys_to_virt(GBE_CONFIG_RAM_BASE)
+
+#define GBE_CONFIG_FLASH_WRITE(base, offset, count, data) \
+        (iowrite16_rep(base + offset, data, count))
+
+#define GBE_CONFIG_FLASH_READ(base, offset, count, data) \
+        (ioread16_rep(base + (offset << 1), data, count))
 
 #define er32(reg)                                                       \
         (readl(hw->hw_addr + ((hw->mac_type >= e1000_82543)             \
diff --git a/drivers/net/e1000e/82571.c b/drivers/net/e1000e/82571.c
index e57e4097ef1b..cb6c7b1c1fb8 100644
--- a/drivers/net/e1000e/82571.c
+++ b/drivers/net/e1000e/82571.c
@@ -78,6 +78,8 @@ static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
+static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);
+static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);
 
 /**
  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
@@ -113,6 +115,8 @@ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
                 phy->type                = e1000_phy_bm;
                 phy->ops.acquire = e1000_get_hw_semaphore_82574;
                 phy->ops.release = e1000_put_hw_semaphore_82574;
+                phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
+                phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
                 break;
         default:
                 return -E1000_ERR_PHY;
@@ -121,29 +125,36 @@ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
 
         /* This can only be done after all function pointers are setup. */
         ret_val = e1000_get_phy_id_82571(hw);
+        if (ret_val) {
+                e_dbg("Error getting PHY ID\n");
+                return ret_val;
+        }
 
         /* Verify phy id */
         switch (hw->mac.type) {
         case e1000_82571:
         case e1000_82572:
                 if (phy->id != IGP01E1000_I_PHY_ID)
-                        return -E1000_ERR_PHY;
+                        ret_val = -E1000_ERR_PHY;
                 break;
         case e1000_82573:
                 if (phy->id != M88E1111_I_PHY_ID)
-                        return -E1000_ERR_PHY;
+                        ret_val = -E1000_ERR_PHY;
                 break;
         case e1000_82574:
         case e1000_82583:
                 if (phy->id != BME1000_E_PHY_ID_R2)
-                        return -E1000_ERR_PHY;
+                        ret_val = -E1000_ERR_PHY;
                 break;
         default:
-                return -E1000_ERR_PHY;
+                ret_val = -E1000_ERR_PHY;
                 break;
         }
 
-        return 0;
+        if (ret_val)
+                e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
+
+        return ret_val;
 }
 
 /**
@@ -649,6 +660,58 @@ static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
 }
 
 /**
+ *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
+ *  @hw: pointer to the HW structure
+ *  @active: true to enable LPLU, false to disable
+ *
+ *  Sets the LPLU D0 state according to the active flag.
+ *  LPLU will not be activated unless the
+ *  device autonegotiation advertisement meets standards of
+ *  either 10 or 10/100 or 10/100/1000 at all duplexes.
+ *  This is a function pointer entry point only called by
+ *  PHY setup routines.
+ **/
+static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
+{
+        u16 data = er32(POEMB);
+
+        if (active)
+                data |= E1000_PHY_CTRL_D0A_LPLU;
+        else
+                data &= ~E1000_PHY_CTRL_D0A_LPLU;
+
+        ew32(POEMB, data);
+        return 0;
+}
+
+/**
+ *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
+ *  @hw: pointer to the HW structure
+ *  @active: boolean used to enable/disable lplu
+ *
+ *  The low power link up (lplu) state is set to the power management level D3
+ *  when active is true, else clear lplu for D3. LPLU
+ *  is used during Dx states where the power conservation is most important.
+ *  During driver activity, SmartSpeed should be enabled so performance is
+ *  maintained.
+ **/
+static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
+{
+        u16 data = er32(POEMB);
+
+        if (!active) {
+                data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
+        } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
+                   (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
+                   (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
+                data |= E1000_PHY_CTRL_NOND0A_LPLU;
+        }
+
+        ew32(POEMB, data);
+        return 0;
+}
+
+/**
  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
  *  @hw: pointer to the HW structure
  *
@@ -956,7 +1019,7 @@ static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
  **/
 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
 {
-        u32 ctrl, ctrl_ext, icr;
+        u32 ctrl, ctrl_ext;
         s32 ret_val;
 
         /*
@@ -1040,7 +1103,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
 
         /* Clear any pending interrupt events. */
         ew32(IMC, 0xffffffff);
-        icr = er32(ICR);
+        er32(ICR);
 
         if (hw->mac.type == e1000_82571) {
                 /* Install any alternate MAC address into RAR0 */
diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h
index 2c913b8e9116..5255be753746 100644
--- a/drivers/net/e1000e/e1000.h
+++ b/drivers/net/e1000e/e1000.h
@@ -38,6 +38,7 @@
 #include <linux/netdevice.h>
 #include <linux/pci.h>
 #include <linux/pci-aspm.h>
+#include <linux/crc32.h>
 
 #include "hw.h"
 
@@ -496,6 +497,8 @@ extern void e1000e_free_tx_resources(struct e1000_adapter *adapter);
 extern void e1000e_update_stats(struct e1000_adapter *adapter);
 extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
 extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
+extern void e1000e_get_hw_control(struct e1000_adapter *adapter);
+extern void e1000e_release_hw_control(struct e1000_adapter *adapter);
 extern void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
 
 extern unsigned int copybreak;
diff --git a/drivers/net/e1000e/es2lan.c b/drivers/net/e1000e/es2lan.c
index b18c644e13d1..e45a61c8930a 100644
--- a/drivers/net/e1000e/es2lan.c
+++ b/drivers/net/e1000e/es2lan.c
@@ -784,7 +784,7 @@ static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
  **/
 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 {
-        u32 ctrl, icr;
+        u32 ctrl;
         s32 ret_val;
 
         /*
@@ -818,7 +818,7 @@ static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 
         /* Clear any pending interrupt events. */
         ew32(IMC, 0xffffffff);
-        icr = er32(ICR);
+        er32(ICR);
 
         ret_val = e1000_check_alt_mac_addr_generic(hw);
 
diff --git a/drivers/net/e1000e/ethtool.c b/drivers/net/e1000e/ethtool.c
index affcacf6f5a9..f8ed03dab9b1 100644
--- a/drivers/net/e1000e/ethtool.c
+++ b/drivers/net/e1000e/ethtool.c
@@ -624,20 +624,24 @@ static void e1000_get_drvinfo(struct net_device *netdev,
         struct e1000_adapter *adapter = netdev_priv(netdev);
         char firmware_version[32];
 
-        strncpy(drvinfo->driver,  e1000e_driver_name, 32);
-        strncpy(drvinfo->version, e1000e_driver_version, 32);
+        strncpy(drvinfo->driver,  e1000e_driver_name,
+                sizeof(drvinfo->driver) - 1);
+        strncpy(drvinfo->version, e1000e_driver_version,
+                sizeof(drvinfo->version) - 1);
 
         /*
          * EEPROM image version # is reported as firmware version # for
          * PCI-E controllers
          */
-        sprintf(firmware_version, "%d.%d-%d",
+        snprintf(firmware_version, sizeof(firmware_version), "%d.%d-%d",
                 (adapter->eeprom_vers & 0xF000) >> 12,
                 (adapter->eeprom_vers & 0x0FF0) >> 4,
                 (adapter->eeprom_vers & 0x000F));
 
-        strncpy(drvinfo->fw_version, firmware_version, 32);
-        strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
+        strncpy(drvinfo->fw_version, firmware_version,
+                sizeof(drvinfo->fw_version) - 1);
+        strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
+                sizeof(drvinfo->bus_info) - 1);
         drvinfo->regdump_len = e1000_get_regs_len(netdev);
         drvinfo->eedump_len = e1000_get_eeprom_len(netdev);
 }
@@ -1704,6 +1708,19 @@ static void e1000_diag_test(struct net_device *netdev,
         bool if_running = netif_running(netdev);
 
         set_bit(__E1000_TESTING, &adapter->state);
+
+        if (!if_running) {
+                /* Get control of and reset hardware */
+                if (adapter->flags & FLAG_HAS_AMT)
+                        e1000e_get_hw_control(adapter);
+
+                e1000e_power_up_phy(adapter);
+
+                adapter->hw.phy.autoneg_wait_to_complete = 1;
+                e1000e_reset(adapter);
+                adapter->hw.phy.autoneg_wait_to_complete = 0;
+        }
+
         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
                 /* Offline tests */
 
@@ -1717,8 +1734,6 @@ static void e1000_diag_test(struct net_device *netdev,
                 if (if_running)
                         /* indicate we're in test mode */
                         dev_close(netdev);
-                else
-                        e1000e_reset(adapter);
 
                 if (e1000_reg_test(adapter, &data[0]))
                         eth_test->flags |= ETH_TEST_FL_FAILED;
@@ -1732,8 +1747,6 @@ static void e1000_diag_test(struct net_device *netdev,
                         eth_test->flags |= ETH_TEST_FL_FAILED;
 
                 e1000e_reset(adapter);
-                /* make sure the phy is powered up */
-                e1000e_power_up_phy(adapter);
                 if (e1000_loopback_test(adapter, &data[3]))
                         eth_test->flags |= ETH_TEST_FL_FAILED;
 
@@ -1755,28 +1768,29 @@ static void e1000_diag_test(struct net_device *netdev,
                 if (if_running)
                         dev_open(netdev);
         } else {
-                if (!if_running && (adapter->flags & FLAG_HAS_AMT)) {
-                        clear_bit(__E1000_TESTING, &adapter->state);
-                        dev_open(netdev);
-                        set_bit(__E1000_TESTING, &adapter->state);
-                }
+                /* Online tests */
 
                 e_info("online testing starting\n");
-                /* Online tests */
-                if (e1000_link_test(adapter, &data[4]))
-                        eth_test->flags |= ETH_TEST_FL_FAILED;
 
-                /* Online tests aren't run; pass by default */
+                /* register, eeprom, intr and loopback tests not run online */
                 data[0] = 0;
                 data[1] = 0;
                 data[2] = 0;
                 data[3] = 0;
 
-                if (!if_running && (adapter->flags & FLAG_HAS_AMT))
-                        dev_close(netdev);
+                if (e1000_link_test(adapter, &data[4]))
+                        eth_test->flags |= ETH_TEST_FL_FAILED;
 
                 clear_bit(__E1000_TESTING, &adapter->state);
         }
+
+        if (!if_running) {
+                e1000e_reset(adapter);
+
+                if (adapter->flags & FLAG_HAS_AMT)
+                        e1000e_release_hw_control(adapter);
+        }
+
         msleep_interruptible(4 * 1000);
 }
 
diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h
index ba302a5c2c30..e774380c7cec 100644
--- a/drivers/net/e1000e/hw.h
+++ b/drivers/net/e1000e/hw.h
@@ -83,6 +83,7 @@ enum e1e_registers {
         E1000_EXTCNF_CTRL  = 0x00F00, /* Extended Configuration Control */
         E1000_EXTCNF_SIZE  = 0x00F08, /* Extended Configuration Size */
         E1000_PHY_CTRL     = 0x00F10, /* PHY Control Register in CSR */
+#define E1000_POEMB     E1000_PHY_CTRL  /* PHY OEM Bits */
         E1000_PBA      = 0x01000, /* Packet Buffer Allocation - RW */
         E1000_PBS      = 0x01008, /* Packet Buffer Size */
         E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index d86cc0832720..5328a2927731 100644
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -1395,22 +1395,6 @@ void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
         }
 }
 
-static u32 e1000_calc_rx_da_crc(u8 mac[])
-{
-        u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
-        u32 i, j, mask, crc;
-
-        crc = 0xffffffff;
-        for (i = 0; i < 6; i++) {
-                crc = crc ^ mac[i];
-                for (j = 8; j > 0; j--) {
-                        mask = (crc & 1) * (-1);
-                        crc = (crc >> 1) ^ (poly & mask);
-                }
-        }
-        return ~crc;
-}
-
 /**
  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
  *  with 82579 PHY
@@ -1453,8 +1437,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
                         mac_addr[4] = (addr_high & 0xFF);
                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
 
-                        ew32(PCH_RAICC(i),
-                                        e1000_calc_rx_da_crc(mac_addr));
+                        ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
                 }
 
                 /* Write Rx addresses to the PHY */
@@ -2977,7 +2960,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
 {
         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
         u16 reg;
-        u32 ctrl, icr, kab;
+        u32 ctrl, kab;
         s32 ret_val;
 
         /*
@@ -3067,7 +3050,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
                 ew32(CRC_OFFSET, 0x65656565);
 
         ew32(IMC, 0xffffffff);
-        icr = er32(ICR);
+        er32(ICR);
 
         kab = er32(KABGTXD);
         kab |= E1000_KABGTXD_BGSQLBIAS;
@@ -3118,7 +3101,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
          * Reset the phy after disabling host wakeup to reset the Rx buffer.
          */
         if (hw->phy.type == e1000_phy_82578) {
-                hw->phy.ops.read_reg(hw, BM_WUC, &i);
+                e1e_rphy(hw, BM_WUC, &i);
                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
                 if (ret_val)
                         return ret_val;
@@ -3276,9 +3259,8 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
             (hw->phy.type == e1000_phy_82577)) {
                 ew32(FCRTV_PCH, hw->fc.refresh_time);
 
-                ret_val = hw->phy.ops.write_reg(hw,
-                                             PHY_REG(BM_PORT_CTRL_PAGE, 27),
-                                             hw->fc.pause_time);
+                ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
+                                   hw->fc.pause_time);
                 if (ret_val)
                         return ret_val;
         }
@@ -3342,8 +3324,7 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
                         return ret_val;
                 break;
         case e1000_phy_ife:
-                ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
-                                               &reg_data);
+                ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
                 if (ret_val)
                         return ret_val;
 
@@ -3361,8 +3342,7 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
                         reg_data |= IFE_PMC_AUTO_MDIX;
                         break;
                 }
-                ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
-                                                reg_data);
+                ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
                 if (ret_val)
                         return ret_val;
                 break;
@@ -3646,7 +3626,8 @@ static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
 {
         if (hw->phy.type == e1000_phy_ife)
                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
-                               (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
+                                (IFE_PSCL_PROBE_MODE |
+                                 IFE_PSCL_PROBE_LEDS_OFF));
 
         ew32(LEDCTL, hw->mac.ledctl_mode1);
         return 0;
@@ -3660,8 +3641,7 @@ static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
  **/
 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
 {
-        return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
-                                        (u16)hw->mac.ledctl_mode1);
+        return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
 }
 
 /**
@@ -3672,8 +3652,7 @@ static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
  **/
 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
 {
-        return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
-                                        (u16)hw->mac.ledctl_default);
+        return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
 }
 
 /**
@@ -3704,7 +3683,7 @@ static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
                 }
         }
 
-        return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
+        return e1e_wphy(hw, HV_LED_CONFIG, data);
 }
 
 /**
@@ -3735,7 +3714,7 @@ static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
                 }
         }
 
-        return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
+        return e1e_wphy(hw, HV_LED_CONFIG, data);
 }
 
 /**
@@ -3844,20 +3823,20 @@ static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
         if ((hw->phy.type == e1000_phy_82578) ||
             (hw->phy.type == e1000_phy_82579) ||
             (hw->phy.type == e1000_phy_82577)) {
-                hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
+                e1e_rphy(hw, HV_SCC_UPPER, &phy_data);
+                e1e_rphy(hw, HV_SCC_LOWER, &phy_data);
+                e1e_rphy(hw, HV_ECOL_UPPER, &phy_data);
+                e1e_rphy(hw, HV_ECOL_LOWER, &phy_data);
+                e1e_rphy(hw, HV_MCC_UPPER, &phy_data);
+                e1e_rphy(hw, HV_MCC_LOWER, &phy_data);
+                e1e_rphy(hw, HV_LATECOL_UPPER, &phy_data);
+                e1e_rphy(hw, HV_LATECOL_LOWER, &phy_data);
+                e1e_rphy(hw, HV_COLC_UPPER, &phy_data);
+                e1e_rphy(hw, HV_COLC_LOWER, &phy_data);
+                e1e_rphy(hw, HV_DC_UPPER, &phy_data);
+                e1e_rphy(hw, HV_DC_LOWER, &phy_data);
+                e1e_rphy(hw, HV_TNCRS_UPPER, &phy_data);
+                e1e_rphy(hw, HV_TNCRS_LOWER, &phy_data);
         }
 }
 
diff --git a/drivers/net/e1000e/lib.c b/drivers/net/e1000e/lib.c
index 7e55170a601e..ff2872153b21 100644
--- a/drivers/net/e1000e/lib.c
+++ b/drivers/net/e1000e/lib.c
@@ -1135,7 +1135,8 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
                 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg);
                 if (ret_val)
                         return ret_val;
-                ret_val = e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
+                ret_val =
+                    e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
                 if (ret_val)
                         return ret_val;
 
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c
index fe50242aa9e6..fa5b60452547 100644
--- a/drivers/net/e1000e/netdev.c
+++ b/drivers/net/e1000e/netdev.c
@@ -1980,15 +1980,15 @@ static void e1000_irq_enable(struct e1000_adapter *adapter)
 }
 
 /**
- * e1000_get_hw_control - get control of the h/w from f/w
+ * e1000e_get_hw_control - get control of the h/w from f/w
  * @adapter: address of board private structure
  *
- * e1000_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
+ * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
  * For ASF and Pass Through versions of f/w this means that
  * the driver is loaded. For AMT version (only with 82573)
  * of the f/w this means that the network i/f is open.
  **/
-static void e1000_get_hw_control(struct e1000_adapter *adapter)
+void e1000e_get_hw_control(struct e1000_adapter *adapter)
 {
         struct e1000_hw *hw = &adapter->hw;
         u32 ctrl_ext;
@@ -2005,16 +2005,16 @@ static void e1000_get_hw_control(struct e1000_adapter *adapter)
 }
 
 /**
- * e1000_release_hw_control - release control of the h/w to f/w
+ * e1000e_release_hw_control - release control of the h/w to f/w
  * @adapter: address of board private structure
  *
- * e1000_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
+ * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
  * For ASF and Pass Through versions of f/w this means that the
  * driver is no longer loaded. For AMT version (only with 82573) i
  * of the f/w this means that the network i/f is closed.
  *
  **/
-static void e1000_release_hw_control(struct e1000_adapter *adapter)
+void e1000e_release_hw_control(struct e1000_adapter *adapter)
 {
         struct e1000_hw *hw = &adapter->hw;
         u32 ctrl_ext;
@@ -2445,7 +2445,7 @@ static void e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
             (vid == adapter->mng_vlan_id)) {
                 /* release control to f/w */
-                e1000_release_hw_control(adapter);
+                e1000e_release_hw_control(adapter);
                 return;
         }
 
@@ -2734,6 +2734,9 @@ static void e1000_setup_rctl(struct e1000_adapter *adapter)
                         ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
                 else
                         ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
+
+                if (ret_val)
+                        e_dbg("failed to enable jumbo frame workaround mode\n");
         }
 
         /* Program MC offset vector base */
@@ -3184,7 +3187,6 @@ void e1000e_reset(struct e1000_adapter *adapter)
                 ew32(PBA, pba);
         }
 
-
         /*
          * flow control settings
          *
@@ -3272,7 +3274,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
          * that the network interface is in control
          */
         if (adapter->flags & FLAG_HAS_AMT)
-                e1000_get_hw_control(adapter);
+                e1000e_get_hw_control(adapter);
 
         ew32(WUC, 0);
 
@@ -3285,6 +3287,13 @@ void e1000e_reset(struct e1000_adapter *adapter)
         ew32(VET, ETH_P_8021Q);
 
         e1000e_reset_adaptive(hw);
+
+        if (!netif_running(adapter->netdev) &&
+            !test_bit(__E1000_TESTING, &adapter->state)) {
+                e1000_power_down_phy(adapter);
+                return;
+        }
+
         e1000_get_phy_info(hw);
 
         if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
@@ -3570,7 +3579,7 @@ static int e1000_open(struct net_device *netdev)
          * interface is now open and reset the part to a known state.
          */
         if (adapter->flags & FLAG_HAS_AMT) {
-                e1000_get_hw_control(adapter);
+                e1000e_get_hw_control(adapter);
                 e1000e_reset(adapter);
         }
 
@@ -3634,7 +3643,7 @@ static int e1000_open(struct net_device *netdev)
         return 0;
 
 err_req_irq:
-        e1000_release_hw_control(adapter);
+        e1000e_release_hw_control(adapter);
         e1000_power_down_phy(adapter);
         e1000e_free_rx_resources(adapter);
 err_setup_rx:
@@ -3689,8 +3698,9 @@ static int e1000_close(struct net_device *netdev)
          * If AMT is enabled, let the firmware know that the network
          * interface is now closed
          */
-        if (adapter->flags & FLAG_HAS_AMT)
-                e1000_release_hw_control(adapter);
+        if ((adapter->flags & FLAG_HAS_AMT) &&
+            !test_bit(__E1000_TESTING, &adapter->state))
+                e1000e_release_hw_control(adapter);
 
         if ((adapter->flags & FLAG_HAS_ERT) ||
             (adapter->hw.mac.type == e1000_pch2lan))
@@ -5209,7 +5219,7 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
          * Release control of h/w to f/w.  If f/w is AMT enabled, this
          * would have already happened in close and is redundant.
          */
-        e1000_release_hw_control(adapter);
+        e1000e_release_hw_control(adapter);
 
         pci_disable_device(pdev);
 
@@ -5366,7 +5376,7 @@ static int __e1000_resume(struct pci_dev *pdev)
          * under the control of the driver.
          */
         if (!(adapter->flags & FLAG_HAS_AMT))
-                e1000_get_hw_control(adapter);
+                e1000e_get_hw_control(adapter);
 
         return 0;
 }
@@ -5613,7 +5623,7 @@ static void e1000_io_resume(struct pci_dev *pdev)
          * under the control of the driver.
          */
         if (!(adapter->flags & FLAG_HAS_AMT))
-                e1000_get_hw_control(adapter);
+                e1000e_get_hw_control(adapter);
 
 }
 
@@ -5636,7 +5646,7 @@ static void e1000_print_device_info(struct e1000_adapter *adapter)
         ret_val = e1000_read_pba_string_generic(hw, pba_str,
                                                 E1000_PBANUM_LENGTH);
         if (ret_val)
-                strcpy(pba_str, "Unknown");
+                strncpy((char *)pba_str, "Unknown", sizeof(pba_str) - 1);
         e_info("MAC: %d, PHY: %d, PBA No: %s\n",
                hw->mac.type, hw->phy.type, pba_str);
 }
@@ -5963,9 +5973,9 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
          * under the control of the driver.
          */
         if (!(adapter->flags & FLAG_HAS_AMT))
-                e1000_get_hw_control(adapter);
+                e1000e_get_hw_control(adapter);
 
-        strcpy(netdev->name, "eth%d");
+        strncpy(netdev->name, "eth%d", sizeof(netdev->name) - 1);
         err = register_netdev(netdev);
         if (err)
                 goto err_register;
@@ -5982,12 +5992,11 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
 
 err_register:
         if (!(adapter->flags & FLAG_HAS_AMT))
-                e1000_release_hw_control(adapter);
+                e1000e_release_hw_control(adapter);
 err_eeprom:
         if (!e1000_check_reset_block(&adapter->hw))
                 e1000_phy_hw_reset(&adapter->hw);
 err_hw_init:
-
         kfree(adapter->tx_ring);
         kfree(adapter->rx_ring);
 err_sw_init:
@@ -6053,7 +6062,7 @@ static void __devexit e1000_remove(struct pci_dev *pdev)
          * Release control of h/w to f/w.  If f/w is AMT enabled, this
          * would have already happened in close and is redundant.
          */
-        e1000_release_hw_control(adapter);
+        e1000e_release_hw_control(adapter);
 
         e1000e_reset_interrupt_capability(adapter);
         kfree(adapter->tx_ring);
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c
index 1781efeb55e3..a640f1c369ae 100644
--- a/drivers/net/e1000e/phy.c
+++ b/drivers/net/e1000e/phy.c
@@ -637,12 +637,11 @@ s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
  **/
 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
 {
-        struct e1000_phy_info *phy = &hw->phy;
         s32 ret_val;
         u16 phy_data;
 
         /* Enable CRS on TX. This must be set for half-duplex operation. */
-        ret_val = phy->ops.read_reg(hw, I82577_CFG_REG, &phy_data);
+        ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
         if (ret_val)
                 goto out;
 
@@ -651,7 +650,7 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
         /* Enable downshift */
         phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
 
-        ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data);
+        ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
 
 out:
         return ret_val;
@@ -774,16 +773,14 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
         }
 
         if (phy->type == e1000_phy_82578) {
-                ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
-                                            &phy_data);
+                ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
                 if (ret_val)
                         return ret_val;
 
                 /* 82578 PHY - set the downshift count to 1x. */
                 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
                 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
-                ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
-                                             phy_data);
+                ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
                 if (ret_val)
                         return ret_val;
         }
@@ -1319,9 +1316,8 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
                                  * We didn't get link.
                                  * Reset the DSP and cross our fingers.
                                  */
-                                ret_val = e1e_wphy(hw,
-                                                M88E1000_PHY_PAGE_SELECT,
-                                                0x001d);
+                                ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
+                                                   0x001d);
                                 if (ret_val)
                                         return ret_val;
                                 ret_val = e1000e_phy_reset_dsp(hw);
@@ -3071,12 +3067,12 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
                 goto out;
 
         /* Do not apply workaround if in PHY loopback bit 14 set */
-        hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
+        e1e_rphy(hw, PHY_CONTROL, &data);
         if (data & PHY_CONTROL_LB)
                 goto out;
 
         /* check if link is up and at 1Gbps */
-        ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
+        ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
         if (ret_val)
                 goto out;
 
@@ -3092,14 +3088,12 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
         mdelay(200);
 
         /* flush the packets in the fifo buffer */
-        ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
-                                        HV_MUX_DATA_CTRL_GEN_TO_MAC |
-                                        HV_MUX_DATA_CTRL_FORCE_SPEED);
+        ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC |
+                           HV_MUX_DATA_CTRL_FORCE_SPEED);
         if (ret_val)
                 goto out;
 
-        ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
-                                        HV_MUX_DATA_CTRL_GEN_TO_MAC);
+        ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
 
 out:
         return ret_val;
@@ -3119,7 +3113,7 @@ s32 e1000_check_polarity_82577(struct e1000_hw *hw)
         s32 ret_val;
         u16 data;
 
-        ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
+        ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
 
         if (!ret_val)
                 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
@@ -3142,13 +3136,13 @@ s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
         u16 phy_data;
         bool link;
 
-        ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
+        ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
         if (ret_val)
                 goto out;
 
         e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
 
-        ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
+        ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
         if (ret_val)
                 goto out;
 
@@ -3212,7 +3206,7 @@ s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
         if (ret_val)
                 goto out;
 
-        ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
+        ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
         if (ret_val)
                 goto out;
 
@@ -3224,7 +3218,7 @@ s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
                 if (ret_val)
                         goto out;
 
-                ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
+                ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
                 if (ret_val)
                         goto out;
 
@@ -3258,7 +3252,7 @@ s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
         s32 ret_val;
         u16 phy_data, length;
 
-        ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
+        ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
         if (ret_val)
                 goto out;
 
diff --git a/drivers/net/ehea/ehea.h b/drivers/net/ehea/ehea.h
index a724a2d14506..6c7257bd73fc 100644
--- a/drivers/net/ehea/ehea.h
+++ b/drivers/net/ehea/ehea.h
@@ -40,7 +40,7 @@
 #include <asm/io.h>
 
 #define DRV_NAME        "ehea"
-#define DRV_VERSION     "EHEA_0106"
+#define DRV_VERSION     "EHEA_0107"
 
 /* eHEA capability flags */
 #define DLPAR_PORT_ADD_REM 1
diff --git a/drivers/net/ehea/ehea_main.c b/drivers/net/ehea/ehea_main.c
index 1032b5bbe238..f75d3144b8a5 100644
--- a/drivers/net/ehea/ehea_main.c
+++ b/drivers/net/ehea/ehea_main.c
@@ -437,7 +437,7 @@ static void ehea_init_fill_rq1(struct ehea_port_res *pr, int nr_rq1a)
                 }
         }
         /* Ring doorbell */
-        ehea_update_rq1a(pr->qp, i);
+        ehea_update_rq1a(pr->qp, i - 1);
 }
 
 static int ehea_refill_rq_def(struct ehea_port_res *pr,
@@ -1329,9 +1329,7 @@ static int ehea_fill_port_res(struct ehea_port_res *pr)
         int ret;
         struct ehea_qp_init_attr *init_attr = &pr->qp->init_attr;
 
-        ehea_init_fill_rq1(pr, init_attr->act_nr_rwqes_rq1
-                               - init_attr->act_nr_rwqes_rq2
-                               - init_attr->act_nr_rwqes_rq3 - 1);
+        ehea_init_fill_rq1(pr, pr->rq1_skba.len);
 
         ret = ehea_refill_rq2(pr, init_attr->act_nr_rwqes_rq2 - 1);
 
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index cce32d43175f..2a71373719ae 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -17,6 +17,8 @@
  *
  * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
  * Copyright (c) 2004-2006 Macq Electronique SA.
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
  */
 
 #include <linux/module.h>
@@ -45,29 +47,41 @@
 
 #include <asm/cacheflush.h>
 
-#ifndef CONFIG_ARCH_MXC
+#ifndef CONFIG_ARM
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
 #endif
 
 #include "fec.h"
 
-#ifdef CONFIG_ARCH_MXC
-#include <mach/hardware.h>
+#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
 #define FEC_ALIGNMENT   0xf
 #else
 #define FEC_ALIGNMENT   0x3
 #endif
 
-/*
- * Define the fixed address of the FEC hardware.
- */
-#if defined(CONFIG_M5272)
+#define DRIVER_NAME     "fec"
+
+/* Controller is ENET-MAC */
+#define FEC_QUIRK_ENET_MAC              (1 << 0)
+/* Controller needs driver to swap frame */
+#define FEC_QUIRK_SWAP_FRAME            (1 << 1)
 
-static unsigned char    fec_mac_default[] = {
-        0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+static struct platform_device_id fec_devtype[] = {
+        {
+                .name = DRIVER_NAME,
+                .driver_data = 0,
+        }, {
+                .name = "imx28-fec",
+                .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
+        }
 };
 
+static unsigned char macaddr[ETH_ALEN];
+module_param_array(macaddr, byte, NULL, 0);
+MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
+
+#if defined(CONFIG_M5272)
 /*
  * Some hardware gets it MAC address out of local flash memory.
  * if this is non-zero then assume it is the address to get MAC from.
@@ -133,7 +147,8 @@ static unsigned char	fec_mac_default[] = {
  * account when setting it.
  */
 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
-    defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC)
+    defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
+    defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
 #define OPT_FRAME_SIZE  (PKT_MAXBUF_SIZE << 16)
 #else
 #define OPT_FRAME_SIZE  0
@@ -186,7 +201,6 @@ struct fec_enet_private {
         int     mii_timeout;
         uint    phy_speed;
         phy_interface_t phy_interface;
-        int     index;
         int     link;
         int     full_duplex;
         struct  completion mdio_done;
@@ -213,10 +227,23 @@ static void fec_stop(struct net_device *dev);
 /* Transmitter timeout */
 #define TX_TIMEOUT (2 * HZ)
 
+static void *swap_buffer(void *bufaddr, int len)
+{
+        int i;
+        unsigned int *buf = bufaddr;
+
+        for (i = 0; i < (len + 3) / 4; i++, buf++)
+                *buf = cpu_to_be32(*buf);
+
+        return bufaddr;
+}
+
 static netdev_tx_t
 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 {
         struct fec_enet_private *fep = netdev_priv(dev);
+        const struct platform_device_id *id_entry =
+                                platform_get_device_id(fep->pdev);
         struct bufdesc *bdp;
         void *bufaddr;
         unsigned short  status;
@@ -261,6 +288,14 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
                 bufaddr = fep->tx_bounce[index];
         }
 
+        /*
+         * Some design made an incorrect assumption on endian mode of
+         * the system that it's running on. As the result, driver has to
+         * swap every frame going to and coming from the controller.
+         */
+        if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
+                swap_buffer(bufaddr, skb->len);
+
         /* Save skb pointer */
         fep->tx_skbuff[fep->skb_cur] = skb;
 
@@ -429,6 +464,8 @@ static void
 fec_enet_rx(struct net_device *dev)
 {
         struct  fec_enet_private *fep = netdev_priv(dev);
+        const struct platform_device_id *id_entry =
+                                platform_get_device_id(fep->pdev);
         struct bufdesc *bdp;
         unsigned short status;
         struct  sk_buff *skb;
@@ -492,6 +529,9 @@ fec_enet_rx(struct net_device *dev)
                 dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen,
                                 DMA_FROM_DEVICE);
 
+                if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
+                        swap_buffer(data, pkt_len);
+
                 /* This does 16 byte alignment, exactly what we need.
                  * The packet length includes FCS, but we don't want to
                  * include that when passing upstream as it messes up
@@ -538,37 +578,50 @@ rx_processing_done:
 }
 
 /* ------------------------------------------------------------------------- */
-#ifdef CONFIG_M5272
 static void __inline__ fec_get_mac(struct net_device *dev)
 {
         struct fec_enet_private *fep = netdev_priv(dev);
+        struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
         unsigned char *iap, tmpaddr[ETH_ALEN];
 
-        if (FEC_FLASHMAC) {
-                /*
-                 * Get MAC address from FLASH.
-                 * If it is all 1's or 0's, use the default.
-                 */
-                iap = (unsigned char *)FEC_FLASHMAC;
-                if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
-                    (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
-                        iap = fec_mac_default;
-                if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
-                    (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
-                        iap = fec_mac_default;
-        } else {
-                *((unsigned long *) &tmpaddr[0]) = readl(fep->hwp + FEC_ADDR_LOW);
-                *((unsigned short *) &tmpaddr[4]) = (readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
+        /*
+         * try to get mac address in following order:
+         *
+         * 1) module parameter via kernel command line in form
+         *    fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
+         */
+        iap = macaddr;
+
+        /*
+         * 2) from flash or fuse (via platform data)
+         */
+        if (!is_valid_ether_addr(iap)) {
+#ifdef CONFIG_M5272
+                if (FEC_FLASHMAC)
+                        iap = (unsigned char *)FEC_FLASHMAC;
+#else
+                if (pdata)
+                        memcpy(iap, pdata->mac, ETH_ALEN);
+#endif
+        }
+
+        /*
+         * 3) FEC mac registers set by bootloader
+         */
+        if (!is_valid_ether_addr(iap)) {
+                *((unsigned long *) &tmpaddr[0]) =
+                        be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
+                *((unsigned short *) &tmpaddr[4]) =
+                        be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
                 iap = &tmpaddr[0];
         }
 
         memcpy(dev->dev_addr, iap, ETH_ALEN);
 
-        /* Adjust MAC if using default MAC address */
-        if (iap == fec_mac_default)
-                 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
+        /* Adjust MAC if using macaddr */
+        if (iap == macaddr)
+                 dev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->pdev->id;
 }
-#endif
 
 /* ------------------------------------------------------------------------- */
 
@@ -651,8 +704,8 @@ static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
         fep->mii_timeout = 0;
         init_completion(&fep->mdio_done);
 
-        /* start a read op */
-        writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
+        /* start a write op */
+        writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
                 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
                 FEC_MMFR_TA | FEC_MMFR_DATA(value),
                 fep->hwp + FEC_MII_DATA);
@@ -681,6 +734,7 @@ static int fec_enet_mii_probe(struct net_device *dev)
         char mdio_bus_id[MII_BUS_ID_SIZE];
         char phy_name[MII_BUS_ID_SIZE + 3];
         int phy_id;
+        int dev_id = fep->pdev->id;
 
         fep->phy_dev = NULL;
 
@@ -692,6 +746,8 @@ static int fec_enet_mii_probe(struct net_device *dev)
                         continue;
                 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
                         continue;
+                if (dev_id--)
+                        continue;
                 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
                 break;
         }
@@ -729,10 +785,35 @@ static int fec_enet_mii_probe(struct net_device *dev)
 
 static int fec_enet_mii_init(struct platform_device *pdev)
 {
+        static struct mii_bus *fec0_mii_bus;
         struct net_device *dev = platform_get_drvdata(pdev);
         struct fec_enet_private *fep = netdev_priv(dev);
+        const struct platform_device_id *id_entry =
+                                platform_get_device_id(fep->pdev);
         int err = -ENXIO, i;
 
+        /*
+         * The dual fec interfaces are not equivalent with enet-mac.
+         * Here are the differences:
+         *
+         *  - fec0 supports MII & RMII modes while fec1 only supports RMII
+         *  - fec0 acts as the 1588 time master while fec1 is slave
+         *  - external phys can only be configured by fec0
+         *
+         * That is to say fec1 can not work independently. It only works
+         * when fec0 is working. The reason behind this design is that the
+         * second interface is added primarily for Switch mode.
+         *
+         * Because of the last point above, both phys are attached on fec0
+         * mdio interface in board design, and need to be configured by
+         * fec0 mii_bus.
+         */
+        if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && pdev->id) {
+                /* fec1 uses fec0 mii_bus */
+                fep->mii_bus = fec0_mii_bus;
+                return 0;
+        }
+
         fep->mii_timeout = 0;
 
         /*
@@ -769,6 +850,10 @@ static int fec_enet_mii_init(struct platform_device *pdev)
         if (mdiobus_register(fep->mii_bus))
                 goto err_out_free_mdio_irq;
 
+        /* save fec0 mii_bus */
+        if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
+                fec0_mii_bus = fep->mii_bus;
+
         return 0;
 
 err_out_free_mdio_irq:
@@ -1067,9 +1152,8 @@ static const struct net_device_ops fec_netdev_ops = {
  /*
   * XXX:  We need to clean up on failure exits here.
   *
-  * index is only used in legacy code
   */
-static int fec_enet_init(struct net_device *dev, int index)
+static int fec_enet_init(struct net_device *dev)
 {
         struct fec_enet_private *fep = netdev_priv(dev);
         struct bufdesc *cbd_base;
@@ -1086,26 +1170,11 @@ static int fec_enet_init(struct net_device *dev, int index)
 
         spin_lock_init(&fep->hw_lock);
 
-        fep->index = index;
         fep->hwp = (void __iomem *)dev->base_addr;
         fep->netdev = dev;
 
-        /* Set the Ethernet address */
-#ifdef CONFIG_M5272
+        /* Get the Ethernet address */
         fec_get_mac(dev);
-#else
-        {
-                unsigned long l;
-                l = readl(fep->hwp + FEC_ADDR_LOW);
-                dev->dev_addr[0] = (unsigned char)((l & 0xFF000000) >> 24);
-                dev->dev_addr[1] = (unsigned char)((l & 0x00FF0000) >> 16);
-                dev->dev_addr[2] = (unsigned char)((l & 0x0000FF00) >> 8);
-                dev->dev_addr[3] = (unsigned char)((l & 0x000000FF) >> 0);
-                l = readl(fep->hwp + FEC_ADDR_HIGH);
-                dev->dev_addr[4] = (unsigned char)((l & 0xFF000000) >> 24);
-                dev->dev_addr[5] = (unsigned char)((l & 0x00FF0000) >> 16);
-        }
-#endif
 
         /* Set receive and transmit descriptor base. */
         fep->rx_bd_base = cbd_base;
@@ -1156,12 +1225,25 @@ static void
 fec_restart(struct net_device *dev, int duplex)
 {
         struct fec_enet_private *fep = netdev_priv(dev);
+        const struct platform_device_id *id_entry =
+                                platform_get_device_id(fep->pdev);
         int i;
+        u32 val, temp_mac[2];
 
         /* Whack a reset.  We should wait for this. */
         writel(1, fep->hwp + FEC_ECNTRL);
         udelay(10);
 
+        /*
+         * enet-mac reset will reset mac address registers too,
+         * so need to reconfigure it.
+         */
+        if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
+                memcpy(&temp_mac, dev->dev_addr, ETH_ALEN);
+                writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
+                writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
+        }
+
         /* Clear any outstanding interrupt. */
         writel(0xffc00000, fep->hwp + FEC_IEVENT);
 
@@ -1208,20 +1290,45 @@ fec_restart(struct net_device *dev, int duplex)
         /* Set MII speed */
         writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
 
-#ifdef FEC_MIIGSK_ENR
-        if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
-                /* disable the gasket and wait */
-                writel(0, fep->hwp + FEC_MIIGSK_ENR);
-                while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
-                        udelay(1);
+        /*
+         * The phy interface and speed need to get configured
+         * differently on enet-mac.
+         */
+        if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
+                val = readl(fep->hwp + FEC_R_CNTRL);
 
-                /* configure the gasket: RMII, 50 MHz, no loopback, no echo */
-                writel(1, fep->hwp + FEC_MIIGSK_CFGR);
+                /* MII or RMII */
+                if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
+                        val |= (1 << 8);
+                else
+                        val &= ~(1 << 8);
 
-                /* re-enable the gasket */
-                writel(2, fep->hwp + FEC_MIIGSK_ENR);
-        }
+                /* 10M or 100M */
+                if (fep->phy_dev && fep->phy_dev->speed == SPEED_100)
+                        val &= ~(1 << 9);
+                else
+                        val |= (1 << 9);
+
+                writel(val, fep->hwp + FEC_R_CNTRL);
+        } else {
+#ifdef FEC_MIIGSK_ENR
+                if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
+                        /* disable the gasket and wait */
+                        writel(0, fep->hwp + FEC_MIIGSK_ENR);
+                        while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
+                                udelay(1);
+
+                        /*
+                         * configure the gasket:
+                         *   RMII, 50 MHz, no loopback, no echo
+                         */
+                        writel(1, fep->hwp + FEC_MIIGSK_CFGR);
+
+                        /* re-enable the gasket */
+                        writel(2, fep->hwp + FEC_MIIGSK_ENR);
+                }
 #endif
+        }
 
         /* And last, enable the transmit and receive processing */
         writel(2, fep->hwp + FEC_ECNTRL);
@@ -1316,7 +1423,7 @@ fec_probe(struct platform_device *pdev)
         }
         clk_enable(fep->clk);
 
-        ret = fec_enet_init(ndev, 0);
+        ret = fec_enet_init(ndev);
         if (ret)
                 goto failed_init;
 
@@ -1380,8 +1487,10 @@ fec_suspend(struct device *dev)
 
         if (ndev) {
                 fep = netdev_priv(ndev);
-                if (netif_running(ndev))
-                        fec_enet_close(ndev);
+                if (netif_running(ndev)) {
+                        fec_stop(ndev);
+                        netif_device_detach(ndev);
+                }
                 clk_disable(fep->clk);
         }
         return 0;
@@ -1396,8 +1505,10 @@ fec_resume(struct device *dev)
         if (ndev) {
                 fep = netdev_priv(ndev);
                 clk_enable(fep->clk);
-                if (netif_running(ndev))
-                        fec_enet_open(ndev);
+                if (netif_running(ndev)) {
+                        fec_restart(ndev, fep->full_duplex);
+                        netif_device_attach(ndev);
+                }
         }
         return 0;
 }
@@ -1414,12 +1525,13 @@ static const struct dev_pm_ops fec_pm_ops = {
 
 static struct platform_driver fec_driver = {
         .driver = {
-                .name   = "fec",
+                .name   = DRIVER_NAME,
                 .owner  = THIS_MODULE,
 #ifdef CONFIG_PM
                 .pm     = &fec_pm_ops,
 #endif
         },
+        .id_table = fec_devtype,
         .probe  = fec_probe,
         .remove = __devexit_p(fec_drv_remove),
 };
diff --git a/drivers/net/fec.h b/drivers/net/fec.h
index 2c48b25668d5..ace318df4c8d 100644
--- a/drivers/net/fec.h
+++ b/drivers/net/fec.h
@@ -14,7 +14,8 @@
 /****************************************************************************/
 
 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
-    defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC)
+    defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
+    defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
 /*
  *      Just figures, Motorola would have to change the offsets for
  *      registers in the same peripheral device on different models
@@ -78,7 +79,7 @@
 /*
  *      Define the buffer descriptor structure.
  */
-#ifdef CONFIG_ARCH_MXC
+#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
 struct bufdesc {
         unsigned short cbd_datlen;      /* Data length */
         unsigned short cbd_sc;  /* Control and status info */
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index cd2d72d825df..af09296ef0dd 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -3949,6 +3949,7 @@ static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
                 writel(flags, base + NvRegWakeUpFlags);
                 spin_unlock_irq(&np->lock);
         }
+        device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
         return 0;
 }
 
@@ -5488,14 +5489,10 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
         /* set mac address */
         nv_copy_mac_to_hw(dev);
 
-        /* Workaround current PCI init glitch:  wakeup bits aren't
-         * being set from PCI PM capability.
-         */
-        device_init_wakeup(&pci_dev->dev, 1);
-
         /* disable WOL */
         writel(0, base + NvRegWakeUpFlags);
         np->wolenabled = 0;
+        device_set_wakeup_enable(&pci_dev->dev, false);
 
         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
 
@@ -5746,8 +5743,9 @@ static void __devexit nv_remove(struct pci_dev *pci_dev)
 }
 
 #ifdef CONFIG_PM
-static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
+static int nv_suspend(struct device *device)
 {
+        struct pci_dev *pdev = to_pci_dev(device);
         struct net_device *dev = pci_get_drvdata(pdev);
         struct fe_priv *np = netdev_priv(dev);
         u8 __iomem *base = get_hwbase(dev);
@@ -5763,25 +5761,17 @@ static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
         for (i = 0; i <= np->register_size/sizeof(u32); i++)
                 np->saved_config_space[i] = readl(base + i*sizeof(u32));
 
-        pci_save_state(pdev);
-        pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
-        pci_disable_device(pdev);
-        pci_set_power_state(pdev, pci_choose_state(pdev, state));
         return 0;
 }
 
-static int nv_resume(struct pci_dev *pdev)
+static int nv_resume(struct device *device)
 {
+        struct pci_dev *pdev = to_pci_dev(device);
         struct net_device *dev = pci_get_drvdata(pdev);
         struct fe_priv *np = netdev_priv(dev);
         u8 __iomem *base = get_hwbase(dev);
         int i, rc = 0;
 
-        pci_set_power_state(pdev, PCI_D0);
-        pci_restore_state(pdev);
-        /* ack any pending wake events, disable PME */
-        pci_enable_wake(pdev, PCI_D0, 0);
-
         /* restore non-pci configuration space */
         for (i = 0; i <= np->register_size/sizeof(u32); i++)
                 writel(np->saved_config_space[i], base+i*sizeof(u32));
@@ -5800,6 +5790,9 @@ static int nv_resume(struct pci_dev *pdev)
         return rc;
 }
 
+static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
+#define NV_PM_OPS (&nv_pm_ops)
+
 static void nv_shutdown(struct pci_dev *pdev)
 {
         struct net_device *dev = pci_get_drvdata(pdev);
@@ -5822,15 +5815,13 @@ static void nv_shutdown(struct pci_dev *pdev)
          * only put the device into D3 if we really go for poweroff.
          */
         if (system_state == SYSTEM_POWER_OFF) {
-                if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
-                        pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
+                pci_wake_from_d3(pdev, np->wolenabled);
                 pci_set_power_state(pdev, PCI_D3hot);
         }
 }
 #else
-#define nv_suspend NULL
+#define NV_PM_OPS NULL
 #define nv_shutdown NULL
-#define nv_resume NULL
 #endif /* CONFIG_PM */
 
 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
@@ -6002,9 +5993,8 @@ static struct pci_driver driver = {
         .id_table       = pci_tbl,
         .probe          = nv_probe,
         .remove         = __devexit_p(nv_remove),
-        .suspend        = nv_suspend,
-        .resume         = nv_resume,
         .shutdown       = nv_shutdown,
+        .driver.pm      = NV_PM_OPS,
 };
 
 static int __init init_nic(void)
diff --git a/drivers/net/hamradio/yam.c b/drivers/net/hamradio/yam.c
index 4e7d1d0a2340..7d9ced0738c5 100644
--- a/drivers/net/hamradio/yam.c
+++ b/drivers/net/hamradio/yam.c
@@ -396,7 +396,7 @@ static unsigned char *add_mcs(unsigned char *bits, int bitrate,
         while (p) {
                 if (p->bitrate == bitrate) {
                         memcpy(p->bits, bits, YAM_FPGA_SIZE);
-                        return p->bits;
+                        goto out;
                 }
                 p = p->next;
         }
@@ -411,7 +411,7 @@ static unsigned char *add_mcs(unsigned char *bits, int bitrate,
         p->bitrate = bitrate;
         p->next = yam_data;
         yam_data = p;
-
+ out:
         release_firmware(fw);
         return p->bits;
 }
diff --git a/drivers/net/ixgbe/ixgbe.h b/drivers/net/ixgbe/ixgbe.h
index 3ae30b8cb7d6..3b8c92463617 100644
--- a/drivers/net/ixgbe/ixgbe.h
+++ b/drivers/net/ixgbe/ixgbe.h
@@ -508,6 +508,8 @@ extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
 extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
+extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
+                                   struct ixgbe_ring *);
 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
@@ -524,26 +526,13 @@ extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
 extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
-                                                 struct ixgbe_atr_input *input,
+                                                 union ixgbe_atr_hash_dword input,
+                                                 union ixgbe_atr_hash_dword common,
                                                  u8 queue);
 extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
-                                      struct ixgbe_atr_input *input,
+                                      union ixgbe_atr_input *input,
                                       struct ixgbe_atr_input_masks *input_masks,
                                       u16 soft_id, u8 queue);
-extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input,
-                                       u16 vlan_id);
-extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input,
-                                        u32 src_addr);
-extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input,
-                                        u32 dst_addr);
-extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input,
-                                        u16 src_port);
-extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input,
-                                        u16 dst_port);
-extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input,
-                                         u16 flex_byte);
-extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
-                                      u8 l4type);
 extern void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
                                    struct ixgbe_ring *ring);
 extern void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
diff --git a/drivers/net/ixgbe/ixgbe_82599.c b/drivers/net/ixgbe/ixgbe_82599.c
index bfd3c227cd4a..8d316d9cd29d 100644
--- a/drivers/net/ixgbe/ixgbe_82599.c
+++ b/drivers/net/ixgbe/ixgbe_82599.c
@@ -1003,7 +1003,7 @@ s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
                 udelay(10);
         }
         if (i >= IXGBE_FDIRCMD_CMD_POLL) {
-                hw_dbg(hw ,"Flow Director previous command isn't complete, "
+                hw_dbg(hw, "Flow Director previous command isn't complete, "
                        "aborting table re-initialization.\n");
                 return IXGBE_ERR_FDIR_REINIT_FAILED;
         }
@@ -1113,13 +1113,10 @@ s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
         /* Move the flexible bytes to use the ethertype - shift 6 words */
         fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
 
-        fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
 
         /* Prime the keys for hashing */
-        IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
-                        htonl(IXGBE_ATR_BUCKET_HASH_KEY));
-        IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
-                        htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
+        IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
+        IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
 
         /*
          * Poll init-done after we write the register.  Estimated times:
@@ -1209,10 +1206,8 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
         fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
 
         /* Prime the keys for hashing */
-        IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
-                        htonl(IXGBE_ATR_BUCKET_HASH_KEY));
-        IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
-                        htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
+        IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
+        IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
 
         /*
          * Poll init-done after we write the register.  Estimated times:
@@ -1251,8 +1246,8 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
  *  @stream: input bitstream to compute the hash on
  *  @key: 32-bit hash key
  **/
-static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
-                                        u32 key)
+static u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
+                                        u32 key)
 {
         /*
          * The algorithm is as follows:
@@ -1272,410 +1267,250 @@ static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
          *    To simplify for programming, the algorithm is implemented
          *    in software this way:
          *
-         *    Key[31:0], Stream[335:0]
+         *    key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
+         *
+         *    for (i = 0; i < 352; i+=32)
+         *        hi_hash_dword[31:0] ^= Stream[(i+31):i];
+         *
+         *    lo_hash_dword[15:0]  ^= Stream[15:0];
+         *    lo_hash_dword[15:0]  ^= hi_hash_dword[31:16];
+         *    lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
          *
-         *    tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
-         *    int_key[350:0] = tmp_key[351:1]
-         *    int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
+         *    hi_hash_dword[31:0]  ^= Stream[351:320];
          *
-         *    hash[15:0] = 0;
-         *    for (i = 0; i < 351; i++) {
-         *        if (int_key[i])
-         *            hash ^= int_stream[(i + 15):i];
+         *    if(key[0])
+         *        hash[15:0] ^= Stream[15:0];
+         *
+         *    for (i = 0; i < 16; i++) {
+         *        if (key[i])
+         *            hash[15:0] ^= lo_hash_dword[(i+15):i];
+         *        if (key[i + 16])
+         *            hash[15:0] ^= hi_hash_dword[(i+15):i];
          *    }
+         *
          */
+        __be32 common_hash_dword = 0;
+        u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
+        u32 hash_result = 0;
+        u8 i;
 
-        union {
-                u64    fill[6];
-                u32    key[11];
-                u8     key_stream[44];
-        } tmp_key;
+        /* record the flow_vm_vlan bits as they are a key part to the hash */
+        flow_vm_vlan = ntohl(atr_input->dword_stream[0]);
 
-        u8   *stream = (u8 *)atr_input;
-        u8   int_key[44];      /* upper-most bit unused */
-        u8   hash_str[46];     /* upper-most 2 bits unused */
-        u16  hash_result = 0;
-        int  i, j, k, h;
+        /* generate common hash dword */
+        for (i = 10; i; i -= 2)
+                common_hash_dword ^= atr_input->dword_stream[i] ^
+                                     atr_input->dword_stream[i - 1];
 
-        /*
-         * Initialize the fill member to prevent warnings
-         * on some compilers
-         */
-         tmp_key.fill[0] = 0;
+        hi_hash_dword = ntohl(common_hash_dword);
 
-        /* First load the temporary key stream */
-        for (i = 0; i < 6; i++) {
-                u64 fillkey = ((u64)key << 32) | key;
-                tmp_key.fill[i] = fillkey;
-        }
+        /* low dword is word swapped version of common */
+        lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
 
-        /*
-         * Set the interim key for the hashing.  Bit 352 is unused, so we must
-         * shift and compensate when building the key.
-         */
+        /* apply flow ID/VM pool/VLAN ID bits to hash words */
+        hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
 
-        int_key[0] = tmp_key.key_stream[0] >> 1;
-        for (i = 1, j = 0; i < 44; i++) {
-                unsigned int this_key = tmp_key.key_stream[j] << 7;
-                j++;
-                int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
-        }
-
-        /*
-         * Set the interim bit string for the hashing.  Bits 368 and 367 are
-         * unused, so shift and compensate when building the string.
-         */
-        hash_str[0] = (stream[40] & 0x7f) >> 1;
-        for (i = 1, j = 40; i < 46; i++) {
-                unsigned int this_str = stream[j] << 7;
-                j++;
-                if (j > 41)
-                        j = 0;
-                hash_str[i] = (u8)(this_str | (stream[j] >> 1));
-        }
+        /* Process bits 0 and 16 */
+        if (key & 0x0001) hash_result ^= lo_hash_dword;
+        if (key & 0x00010000) hash_result ^= hi_hash_dword;
 
         /*
-         * Now compute the hash.  i is the index into hash_str, j is into our
-         * key stream, k is counting the number of bits, and h interates within
-         * each byte.
+         * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
+         * delay this because bit 0 of the stream should not be processed
+         * so we do not add the vlan until after bit 0 was processed
          */
-        for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
-                for (h = 0; h < 8 && k < 351; h++, k++) {
-                        if (int_key[j] & (1 << h)) {
-                                /*
-                                 * Key bit is set, XOR in the current 16-bit
-                                 * string.  Example of processing:
-                                 *    h = 0,
-                                 *      tmp = (hash_str[i - 2] & 0 << 16) |
-                                 *            (hash_str[i - 1] & 0xff << 8) |
-                                 *            (hash_str[i] & 0xff >> 0)
-                                 *      So tmp = hash_str[15 + k:k], since the
-                                 *      i + 2 clause rolls off the 16-bit value
-                                 *    h = 7,
-                                 *      tmp = (hash_str[i - 2] & 0x7f << 9) |
-                                 *            (hash_str[i - 1] & 0xff << 1) |
-                                 *            (hash_str[i] & 0x80 >> 7)
-                                 */
-                                int tmp = (hash_str[i] >> h);
-                                tmp |= (hash_str[i - 1] << (8 - h));
-                                tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
-                                             << (16 - h);
-                                hash_result ^= (u16)tmp;
-                        }
-                }
-        }
-
-        return hash_result;
-}
-
-/**
- *  ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
- *  @input: input stream to modify
- *  @vlan: the VLAN id to load
- **/
-s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
-{
-        input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
-        input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
-
-        return 0;
-}
-
-/**
- *  ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
- *  @input: input stream to modify
- *  @src_addr: the IP address to load
- **/
-s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
-{
-        input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
-        input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
-                                                       (src_addr >> 16) & 0xff;
-        input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
-                                                        (src_addr >> 8) & 0xff;
-        input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
-
-        return 0;
-}
-
-/**
- *  ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
- *  @input: input stream to modify
- *  @dst_addr: the IP address to load
- **/
-s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
-{
-        input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
-        input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
-                                                       (dst_addr >> 16) & 0xff;
-        input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
-                                                        (dst_addr >> 8) & 0xff;
-        input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
-
-        return 0;
-}
+        lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
 
-/**
- *  ixgbe_atr_set_src_port_82599 - Sets the source port
- *  @input: input stream to modify
- *  @src_port: the source port to load
- **/
-s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
-{
-        input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
-        input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
-
-        return 0;
-}
-
-/**
- *  ixgbe_atr_set_dst_port_82599 - Sets the destination port
- *  @input: input stream to modify
- *  @dst_port: the destination port to load
- **/
-s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
-{
-        input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
-        input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
-
-        return 0;
-}
-
-/**
- *  ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
- *  @input: input stream to modify
- *  @flex_bytes: the flexible bytes to load
- **/
-s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
-{
-        input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
-        input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
-
-        return 0;
-}
-
-/**
- *  ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
- *  @input: input stream to modify
- *  @l4type: the layer 4 type value to load
- **/
-s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
-{
-        input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
-
-        return 0;
-}
-
-/**
- *  ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
- *  @input: input stream to search
- *  @vlan: the VLAN id to load
- **/
-static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan)
-{
-        *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
-        *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
-
-        return 0;
-}
-
-/**
- *  ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
- *  @input: input stream to search
- *  @src_addr: the IP address to load
- **/
-static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
-                                        u32 *src_addr)
-{
-        *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
-        *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
-        *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
-        *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
-
-        return 0;
-}
 
-/**
- *  ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
- *  @input: input stream to search
- *  @dst_addr: the IP address to load
- **/
-static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
-                                        u32 *dst_addr)
-{
-        *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
-        *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
-        *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
-        *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
+        /* process the remaining 30 bits in the key 2 bits at a time */
+        for (i = 15; i; i-- ) {
+                if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
+                if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
+        }
 
-        return 0;
+        return hash_result & IXGBE_ATR_HASH_MASK;
 }
 
-/**
- *  ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
- *  @input: input stream to search
- *  @src_addr_1: the first 4 bytes of the IP address to load
- *  @src_addr_2: the second 4 bytes of the IP address to load
- *  @src_addr_3: the third 4 bytes of the IP address to load
- *  @src_addr_4: the fourth 4 bytes of the IP address to load
- **/
-static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
-                                        u32 *src_addr_1, u32 *src_addr_2,
-                                        u32 *src_addr_3, u32 *src_addr_4)
-{
-        *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
-        *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
-        *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
-        *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
-
-        *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
-        *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
-        *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
-        *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
-
-        *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
-        *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
-        *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
-        *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
-
-        *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
-        *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
-        *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
-        *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
-
-        return 0;
-}
+/*
+ * These defines allow us to quickly generate all of the necessary instructions
+ * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
+ * for values 0 through 15
+ */
+#define IXGBE_ATR_COMMON_HASH_KEY \
+                (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
+#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
+do { \
+        u32 n = (_n); \
+        if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
+                common_hash ^= lo_hash_dword >> n; \
+        else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
+                bucket_hash ^= lo_hash_dword >> n; \
+        else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
+                sig_hash ^= lo_hash_dword << (16 - n); \
+        if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
+                common_hash ^= hi_hash_dword >> n; \
+        else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
+                bucket_hash ^= hi_hash_dword >> n; \
+        else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
+                sig_hash ^= hi_hash_dword << (16 - n); \
+} while (0);
 
 /**
- *  ixgbe_atr_get_src_port_82599 - Gets the source port
- *  @input: input stream to modify
- *  @src_port: the source port to load
+ *  ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
+ *  @stream: input bitstream to compute the hash on
  *
- *  Even though the input is given in big-endian, the FDIRPORT registers
- *  expect the ports to be programmed in little-endian.  Hence the need to swap
- *  endianness when retrieving the data.  This can be confusing since the
- *  internal hash engine expects it to be big-endian.
+ *  This function is almost identical to the function above but contains
+ *  several optomizations such as unwinding all of the loops, letting the
+ *  compiler work out all of the conditional ifs since the keys are static
+ *  defines, and computing two keys at once since the hashed dword stream
+ *  will be the same for both keys.
  **/
-static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
-                                        u16 *src_port)
+static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
+                                            union ixgbe_atr_hash_dword common)
 {
-        *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
-        *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
+        u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
+        u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
 
-        return 0;
-}
+        /* record the flow_vm_vlan bits as they are a key part to the hash */
+        flow_vm_vlan = ntohl(input.dword);
 
-/**
- *  ixgbe_atr_get_dst_port_82599 - Gets the destination port
- *  @input: input stream to modify
- *  @dst_port: the destination port to load
- *
- *  Even though the input is given in big-endian, the FDIRPORT registers
- *  expect the ports to be programmed in little-endian.  Hence the need to swap
- *  endianness when retrieving the data.  This can be confusing since the
- *  internal hash engine expects it to be big-endian.
- **/
-static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
-                                        u16 *dst_port)
-{
-        *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
-        *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
+        /* generate common hash dword */
+        hi_hash_dword = ntohl(common.dword);
 
-        return 0;
-}
+        /* low dword is word swapped version of common */
+        lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
 
-/**
- *  ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
- *  @input: input stream to modify
- *  @flex_bytes: the flexible bytes to load
- **/
-static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
-                                         u16 *flex_byte)
-{
-        *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
-        *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
+        /* apply flow ID/VM pool/VLAN ID bits to hash words */
+        hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
 
-        return 0;
-}
+        /* Process bits 0 and 16 */
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
 
-/**
- *  ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
- *  @input: input stream to modify
- *  @l4type: the layer 4 type value to load
- **/
-static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
-                                      u8 *l4type)
-{
-        *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
+        /*
+         * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
+         * delay this because bit 0 of the stream should not be processed
+         * so we do not add the vlan until after bit 0 was processed
+         */
+        lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
+
+        /* Process remaining 30 bit of the key */
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
+
+        /* combine common_hash result with signature and bucket hashes */
+        bucket_hash ^= common_hash;
+        bucket_hash &= IXGBE_ATR_HASH_MASK;
 
-        return 0;
+        sig_hash ^= common_hash << 16;
+        sig_hash &= IXGBE_ATR_HASH_MASK << 16;
+
+        /* return completed signature hash */
+        return sig_hash ^ bucket_hash;
 }
 
 /**
  *  ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
  *  @hw: pointer to hardware structure
- *  @stream: input bitstream
+ *  @input: unique input dword
+ *  @common: compressed common input dword
  *  @queue: queue index to direct traffic to
  **/
 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
-                                          struct ixgbe_atr_input *input,
+                                          union ixgbe_atr_hash_dword input,
+                                          union ixgbe_atr_hash_dword common,
                                           u8 queue)
 {
         u64  fdirhashcmd;
-        u64  fdircmd;
-        u32  fdirhash;
-        u16  bucket_hash, sig_hash;
-        u8   l4type;
-
-        bucket_hash = ixgbe_atr_compute_hash_82599(input,
-                                                   IXGBE_ATR_BUCKET_HASH_KEY);
-
-        /* bucket_hash is only 15 bits */
-        bucket_hash &= IXGBE_ATR_HASH_MASK;
-
-        sig_hash = ixgbe_atr_compute_hash_82599(input,
-                                                IXGBE_ATR_SIGNATURE_HASH_KEY);
-
-        /* Get the l4type in order to program FDIRCMD properly */
-        /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
-        ixgbe_atr_get_l4type_82599(input, &l4type);
+        u32  fdircmd;
 
         /*
-         * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
-         * is for FDIRCMD.  Then do a 64-bit register write from FDIRHASH.
+         * Get the flow_type in order to program FDIRCMD properly
+         * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
          */
-        fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
-
-        fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
-                   IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
-
-        switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
-        case IXGBE_ATR_L4TYPE_TCP:
-                fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
-                break;
-        case IXGBE_ATR_L4TYPE_UDP:
-                fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
-                break;
-        case IXGBE_ATR_L4TYPE_SCTP:
-                fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
+        switch (input.formatted.flow_type) {
+        case IXGBE_ATR_FLOW_TYPE_TCPV4:
+        case IXGBE_ATR_FLOW_TYPE_UDPV4:
+        case IXGBE_ATR_FLOW_TYPE_SCTPV4:
+        case IXGBE_ATR_FLOW_TYPE_TCPV6:
+        case IXGBE_ATR_FLOW_TYPE_UDPV6:
+        case IXGBE_ATR_FLOW_TYPE_SCTPV6:
                 break;
         default:
-                hw_dbg(hw, "Error on l4type input\n");
+                hw_dbg(hw, " Error on flow type input\n");
                 return IXGBE_ERR_CONFIG;
         }
 
-        if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
-                fdircmd |= IXGBE_FDIRCMD_IPV6;
+        /* configure FDIRCMD register */
+        fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
+                  IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
+        fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
+        fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
 
-        fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
-        fdirhashcmd = ((fdircmd << 32) | fdirhash);
+        /*
+         * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
+         * is for FDIRCMD.  Then do a 64-bit register write from FDIRHASH.
+         */
+        fdirhashcmd = (u64)fdircmd << 32;
+        fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
 
         IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
 
+        hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
+
         return 0;
 }
 
 /**
+ *  ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
+ *  @input_mask: mask to be bit swapped
+ *
+ *  The source and destination port masks for flow director are bit swapped
+ *  in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc.  In order to
+ *  generate a correctly swapped value we need to bit swap the mask and that
+ *  is what is accomplished by this function.
+ **/
+static u32 ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks)
+{
+        u32 mask = ntohs(input_masks->dst_port_mask);
+        mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
+        mask |= ntohs(input_masks->src_port_mask);
+        mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
+        mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
+        mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
+        return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
+}
+
+/*
+ * These two macros are meant to address the fact that we have registers
+ * that are either all or in part big-endian.  As a result on big-endian
+ * systems we will end up byte swapping the value to little-endian before
+ * it is byte swapped again and written to the hardware in the original
+ * big-endian format.
+ */
+#define IXGBE_STORE_AS_BE32(_value) \
+        (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
+         (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
+
+#define IXGBE_WRITE_REG_BE32(a, reg, value) \
+        IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
+
+#define IXGBE_STORE_AS_BE16(_value) \
+        (((u16)(_value) >> 8) | ((u16)(_value) << 8))
+
+/**
  *  ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
  *  @hw: pointer to hardware structure
  *  @input: input bitstream
@@ -1687,135 +1522,139 @@ s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
  *  hardware writes must be protected from one another.
  **/
 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
-                                      struct ixgbe_atr_input *input,
+                                      union ixgbe_atr_input *input,
                                       struct ixgbe_atr_input_masks *input_masks,
                                       u16 soft_id, u8 queue)
 {
-        u32 fdircmd = 0;
         u32 fdirhash;
-        u32 src_ipv4 = 0, dst_ipv4 = 0;
-        u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
-        u16 src_port, dst_port, vlan_id, flex_bytes;
-        u16 bucket_hash;
-        u8  l4type;
-        u8  fdirm = 0;
-
-        /* Get our input values */
-        ixgbe_atr_get_l4type_82599(input, &l4type);
+        u32 fdircmd;
+        u32 fdirport, fdirtcpm;
+        u32 fdirvlan;
+        /* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */
+        u32 fdirm = IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP | IXGBE_FDIRM_FLEX |
+                    IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6;
 
         /*
-         * Check l4type formatting, and bail out before we touch the hardware
+         * Check flow_type formatting, and bail out before we touch the hardware
          * if there's a configuration issue
          */
-        switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
-        case IXGBE_ATR_L4TYPE_TCP:
-                fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
-                break;
-        case IXGBE_ATR_L4TYPE_UDP:
-                fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
-                break;
-        case IXGBE_ATR_L4TYPE_SCTP:
-                fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
+        switch (input->formatted.flow_type) {
+        case IXGBE_ATR_FLOW_TYPE_IPV4:
+                /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
+                fdirm |= IXGBE_FDIRM_L4P;
+        case IXGBE_ATR_FLOW_TYPE_SCTPV4:
+                if (input_masks->dst_port_mask || input_masks->src_port_mask) {
+                        hw_dbg(hw, " Error on src/dst port mask\n");
+                        return IXGBE_ERR_CONFIG;
+                }
+        case IXGBE_ATR_FLOW_TYPE_TCPV4:
+        case IXGBE_ATR_FLOW_TYPE_UDPV4:
                 break;
         default:
-                hw_dbg(hw, "Error on l4type input\n");
+                hw_dbg(hw, " Error on flow type input\n");
                 return IXGBE_ERR_CONFIG;
         }
 
-        bucket_hash = ixgbe_atr_compute_hash_82599(input,
-                                                   IXGBE_ATR_BUCKET_HASH_KEY);
-
-        /* bucket_hash is only 15 bits */
-        bucket_hash &= IXGBE_ATR_HASH_MASK;
-
-        ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
-        ixgbe_atr_get_src_port_82599(input, &src_port);
-        ixgbe_atr_get_dst_port_82599(input, &dst_port);
-        ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
-
-        fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
-
-        /* Now figure out if we're IPv4 or IPv6 */
-        if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
-                /* IPv6 */
-                ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
-                                             &src_ipv6_3, &src_ipv6_4);
-
-                IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
-                IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
-                IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
-                /* The last 4 bytes is the same register as IPv4 */
-                IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
-
-                fdircmd |= IXGBE_FDIRCMD_IPV6;
-                fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
-        } else {
-                /* IPv4 */
-                ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
-                IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
-        }
-
-        ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
-        IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
-
-        IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
-                                    (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
-        IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
-                      (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
-
         /*
-         * Program the relevant mask registers.  L4type cannot be
-         * masked out in this implementation.
+         * Program the relevant mask registers.  If src/dst_port or src/dst_addr
+         * are zero, then assume a full mask for that field.  Also assume that
+         * a VLAN of 0 is unspecified, so mask that out as well.  L4type
+         * cannot be masked out in this implementation.
          *
          * This also assumes IPv4 only.  IPv6 masking isn't supported at this
          * point in time.
          */
-        IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, input_masks->src_ip_mask);
-        IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, input_masks->dst_ip_mask);
-
-        switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
-        case IXGBE_ATR_L4TYPE_TCP:
-                IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, input_masks->src_port_mask);
-                IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
-                                (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
-                                 (input_masks->dst_port_mask << 16)));
+
+        /* Program FDIRM */
+        switch (ntohs(input_masks->vlan_id_mask) & 0xEFFF) {
+        case 0xEFFF:
+                /* Unmask VLAN ID - bit 0 and fall through to unmask prio */
+                fdirm &= ~IXGBE_FDIRM_VLANID;
+        case 0xE000:
+                /* Unmask VLAN prio - bit 1 */
+                fdirm &= ~IXGBE_FDIRM_VLANP;
                 break;
-        case IXGBE_ATR_L4TYPE_UDP:
-                IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, input_masks->src_port_mask);
-                IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
-                                (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
-                                 (input_masks->src_port_mask << 16)));
+        case 0x0FFF:
+                /* Unmask VLAN ID - bit 0 */
+                fdirm &= ~IXGBE_FDIRM_VLANID;
                 break;
-        default:
-                /* this already would have failed above */
+        case 0x0000:
+                /* do nothing, vlans already masked */
                 break;
+        default:
+                hw_dbg(hw, " Error on VLAN mask\n");
+                return IXGBE_ERR_CONFIG;
         }
 
-        /* Program the last mask register, FDIRM */
-        if (input_masks->vlan_id_mask)
-                /* Mask both VLAN and VLANP - bits 0 and 1 */
-                fdirm |= 0x3;
-
-        if (input_masks->data_mask)
-                /* Flex bytes need masking, so mask the whole thing - bit 4 */
-                fdirm |= 0x10;
+        if (input_masks->flex_mask & 0xFFFF) {
+                if ((input_masks->flex_mask & 0xFFFF) != 0xFFFF) {
+                        hw_dbg(hw, " Error on flexible byte mask\n");
+                        return IXGBE_ERR_CONFIG;
+                }
+                /* Unmask Flex Bytes - bit 4 */
+                fdirm &= ~IXGBE_FDIRM_FLEX;
+        }
 
         /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
-        fdirm |= 0x24;
-
         IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
 
-        fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
-        fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
-        fdircmd |= IXGBE_FDIRCMD_LAST;
-        fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
-        fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
+        /* store the TCP/UDP port masks, bit reversed from port layout */
+        fdirtcpm = ixgbe_get_fdirtcpm_82599(input_masks);
+
+        /* write both the same so that UDP and TCP use the same mask */
+        IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
+        IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
+
+        /* store source and destination IP masks (big-enian) */
+        IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
+                             ~input_masks->src_ip_mask[0]);
+        IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
+                             ~input_masks->dst_ip_mask[0]);
+
+        /* Apply masks to input data */
+        input->formatted.vlan_id &= input_masks->vlan_id_mask;
+        input->formatted.flex_bytes &= input_masks->flex_mask;
+        input->formatted.src_port &= input_masks->src_port_mask;
+        input->formatted.dst_port &= input_masks->dst_port_mask;
+        input->formatted.src_ip[0] &= input_masks->src_ip_mask[0];
+        input->formatted.dst_ip[0] &= input_masks->dst_ip_mask[0];
+
+        /* record vlan (little-endian) and flex_bytes(big-endian) */
+        fdirvlan =
+                IXGBE_STORE_AS_BE16(ntohs(input->formatted.flex_bytes));
+        fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
+        fdirvlan |= ntohs(input->formatted.vlan_id);
+        IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
+
+        /* record source and destination port (little-endian)*/
+        fdirport = ntohs(input->formatted.dst_port);
+        fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
+        fdirport |= ntohs(input->formatted.src_port);
+        IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
+
+        /* record the first 32 bits of the destination address (big-endian) */
+        IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
+
+        /* record the source address (big-endian) */
+        IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
+
+        /* configure FDIRCMD register */
+        fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
+                  IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
+        fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
+        fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
+
+        /* we only want the bucket hash so drop the upper 16 bits */
+        fdirhash = ixgbe_atr_compute_hash_82599(input,
+                                                IXGBE_ATR_BUCKET_HASH_KEY);
+        fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
 
         IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
         IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
 
         return 0;
 }
+
 /**
  *  ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
  *  @hw: pointer to hardware structure
diff --git a/drivers/net/ixgbe/ixgbe_ethtool.c b/drivers/net/ixgbe/ixgbe_ethtool.c
index 23ff23e8b393..2002ea88ca2a 100644
--- a/drivers/net/ixgbe/ixgbe_ethtool.c
+++ b/drivers/net/ixgbe/ixgbe_ethtool.c
@@ -1477,9 +1477,7 @@ static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
         reg_ctl &= ~IXGBE_RXCTRL_RXEN;
         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
-        reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rx_ring->reg_idx));
-        reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
-        IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rx_ring->reg_idx), reg_ctl);
+        ixgbe_disable_rx_queue(adapter, rx_ring);
 
         /* now Tx */
         reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
@@ -2279,10 +2277,11 @@ static int ixgbe_set_rx_ntuple(struct net_device *dev,
                                struct ethtool_rx_ntuple *cmd)
 {
         struct ixgbe_adapter *adapter = netdev_priv(dev);
-        struct ethtool_rx_ntuple_flow_spec fs = cmd->fs;
-        struct ixgbe_atr_input input_struct;
+        struct ethtool_rx_ntuple_flow_spec *fs = &cmd->fs;
+        union ixgbe_atr_input input_struct;
         struct ixgbe_atr_input_masks input_masks;
         int target_queue;
+        int err;
 
         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
                 return -EOPNOTSUPP;
@@ -2291,67 +2290,122 @@ static int ixgbe_set_rx_ntuple(struct net_device *dev,
          * Don't allow programming if the action is a queue greater than
          * the number of online Tx queues.
          */
-        if ((fs.action >= adapter->num_tx_queues) ||
-            (fs.action < ETHTOOL_RXNTUPLE_ACTION_DROP))
+        if ((fs->action >= adapter->num_tx_queues) ||
+            (fs->action < ETHTOOL_RXNTUPLE_ACTION_DROP))
                 return -EINVAL;
 
-        memset(&input_struct, 0, sizeof(struct ixgbe_atr_input));
+        memset(&input_struct, 0, sizeof(union ixgbe_atr_input));
         memset(&input_masks, 0, sizeof(struct ixgbe_atr_input_masks));
 
-        input_masks.src_ip_mask = fs.m_u.tcp_ip4_spec.ip4src;
-        input_masks.dst_ip_mask = fs.m_u.tcp_ip4_spec.ip4dst;
-        input_masks.src_port_mask = fs.m_u.tcp_ip4_spec.psrc;
-        input_masks.dst_port_mask = fs.m_u.tcp_ip4_spec.pdst;
-        input_masks.vlan_id_mask = fs.vlan_tag_mask;
-        /* only use the lowest 2 bytes for flex bytes */
-        input_masks.data_mask = (fs.data_mask & 0xffff);
-
-        switch (fs.flow_type) {
+        /* record flow type */
+        switch (fs->flow_type) {
+        case IPV4_FLOW:
+                input_struct.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
+                break;
         case TCP_V4_FLOW:
-                ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_TCP);
+                input_struct.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
                 break;
         case UDP_V4_FLOW:
-                ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_UDP);
+                input_struct.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
                 break;
         case SCTP_V4_FLOW:
-                ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_SCTP);
+                input_struct.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
                 break;
         default:
                 return -1;
         }
 
-        /* Mask bits from the inputs based on user-supplied mask */
-        ixgbe_atr_set_src_ipv4_82599(&input_struct,
-                    (fs.h_u.tcp_ip4_spec.ip4src & ~fs.m_u.tcp_ip4_spec.ip4src));
-        ixgbe_atr_set_dst_ipv4_82599(&input_struct,
-                    (fs.h_u.tcp_ip4_spec.ip4dst & ~fs.m_u.tcp_ip4_spec.ip4dst));
-        /* 82599 expects these to be byte-swapped for perfect filtering */
-        ixgbe_atr_set_src_port_82599(&input_struct,
-               ((ntohs(fs.h_u.tcp_ip4_spec.psrc)) & ~fs.m_u.tcp_ip4_spec.psrc));
-        ixgbe_atr_set_dst_port_82599(&input_struct,
-               ((ntohs(fs.h_u.tcp_ip4_spec.pdst)) & ~fs.m_u.tcp_ip4_spec.pdst));
-
-        /* VLAN and Flex bytes are either completely masked or not */
-        if (!fs.vlan_tag_mask)
-                ixgbe_atr_set_vlan_id_82599(&input_struct, fs.vlan_tag);
-
-        if (!input_masks.data_mask)
-                /* make sure we only use the first 2 bytes of user data */
-                ixgbe_atr_set_flex_byte_82599(&input_struct,
-                                              (fs.data & 0xffff));
+        /* copy vlan tag minus the CFI bit */
+        if ((fs->vlan_tag & 0xEFFF) || (~fs->vlan_tag_mask & 0xEFFF)) {
+                input_struct.formatted.vlan_id = htons(fs->vlan_tag & 0xEFFF);
+                if (!fs->vlan_tag_mask) {
+                        input_masks.vlan_id_mask = htons(0xEFFF);
+                } else {
+                        switch (~fs->vlan_tag_mask & 0xEFFF) {
+                        /* all of these are valid vlan-mask values */
+                        case 0xEFFF:
+                        case 0xE000:
+                        case 0x0FFF:
+                        case 0x0000:
+                                input_masks.vlan_id_mask =
+                                        htons(~fs->vlan_tag_mask);
+                                break;
+                        /* exit with error if vlan-mask is invalid */
+                        default:
+                                e_err(drv, "Partial VLAN ID or "
+                                      "priority mask in vlan-mask is not "
+                                      "supported by hardware\n");
+                                return -1;
+                        }
+                }
+        }
+
+        /* make sure we only use the first 2 bytes of user data */
+        if ((fs->data & 0xFFFF) || (~fs->data_mask & 0xFFFF)) {
+                input_struct.formatted.flex_bytes = htons(fs->data & 0xFFFF);
+                if (!(fs->data_mask & 0xFFFF)) {
+                        input_masks.flex_mask = 0xFFFF;
+                } else if (~fs->data_mask & 0xFFFF) {
+                        e_err(drv, "Partial user-def-mask is not "
+                              "supported by hardware\n");
+                        return -1;
+                }
+        }
+
+        /*
+         * Copy input into formatted structures
+         *
+         * These assignments are based on the following logic
+         * If neither input or mask are set assume value is masked out.
+         * If input is set, but mask is not mask should default to accept all.
+         * If input is not set, but mask is set then mask likely results in 0.
+         * If input is set and mask is set then assign both.
+         */
+        if (fs->h_u.tcp_ip4_spec.ip4src || ~fs->m_u.tcp_ip4_spec.ip4src) {
+                input_struct.formatted.src_ip[0] = fs->h_u.tcp_ip4_spec.ip4src;
+                if (!fs->m_u.tcp_ip4_spec.ip4src)
+                        input_masks.src_ip_mask[0] = 0xFFFFFFFF;
+                else
+                        input_masks.src_ip_mask[0] =
+                                ~fs->m_u.tcp_ip4_spec.ip4src;
+        }
+        if (fs->h_u.tcp_ip4_spec.ip4dst || ~fs->m_u.tcp_ip4_spec.ip4dst) {
+                input_struct.formatted.dst_ip[0] = fs->h_u.tcp_ip4_spec.ip4dst;
+                if (!fs->m_u.tcp_ip4_spec.ip4dst)
+                        input_masks.dst_ip_mask[0] = 0xFFFFFFFF;
+                else
+                        input_masks.dst_ip_mask[0] =
+                                ~fs->m_u.tcp_ip4_spec.ip4dst;
+        }
+        if (fs->h_u.tcp_ip4_spec.psrc || ~fs->m_u.tcp_ip4_spec.psrc) {
+                input_struct.formatted.src_port = fs->h_u.tcp_ip4_spec.psrc;
+                if (!fs->m_u.tcp_ip4_spec.psrc)
+                        input_masks.src_port_mask = 0xFFFF;
+                else
+                        input_masks.src_port_mask = ~fs->m_u.tcp_ip4_spec.psrc;
+        }
+        if (fs->h_u.tcp_ip4_spec.pdst || ~fs->m_u.tcp_ip4_spec.pdst) {
+                input_struct.formatted.dst_port = fs->h_u.tcp_ip4_spec.pdst;
+                if (!fs->m_u.tcp_ip4_spec.pdst)
+                        input_masks.dst_port_mask = 0xFFFF;
+                else
+                        input_masks.dst_port_mask = ~fs->m_u.tcp_ip4_spec.pdst;
+        }
 
         /* determine if we need to drop or route the packet */
-        if (fs.action == ETHTOOL_RXNTUPLE_ACTION_DROP)
+        if (fs->action == ETHTOOL_RXNTUPLE_ACTION_DROP)
                 target_queue = MAX_RX_QUEUES - 1;
         else
-                target_queue = fs.action;
+                target_queue = fs->action;
 
         spin_lock(&adapter->fdir_perfect_lock);
-        ixgbe_fdir_add_perfect_filter_82599(&adapter->hw, &input_struct,
-                                            &input_masks, 0, target_queue);
+        err = ixgbe_fdir_add_perfect_filter_82599(&adapter->hw,
+                                                  &input_struct,
+                                                  &input_masks, 0,
+                                                  target_queue);
         spin_unlock(&adapter->fdir_perfect_lock);
 
-        return 0;
+        return err ? -1 : 0;
 }
 
 static const struct ethtool_ops ixgbe_ethtool_ops = {
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index 38ab4f3f8197..a060610a42db 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -3024,6 +3024,36 @@ static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
         }
 }
 
+void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
+                            struct ixgbe_ring *ring)
+{
+        struct ixgbe_hw *hw = &adapter->hw;
+        int wait_loop = IXGBE_MAX_RX_DESC_POLL;
+        u32 rxdctl;
+        u8 reg_idx = ring->reg_idx;
+
+        rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
+        rxdctl &= ~IXGBE_RXDCTL_ENABLE;
+
+        /* write value back with RXDCTL.ENABLE bit cleared */
+        IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
+
+        if (hw->mac.type == ixgbe_mac_82598EB &&
+            !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
+                return;
+
+        /* the hardware may take up to 100us to really disable the rx queue */
+        do {
+                udelay(10);
+                rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
+        } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
+
+        if (!wait_loop) {
+                e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
+                      "the polling period\n", reg_idx);
+        }
+}
+
 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
                              struct ixgbe_ring *ring)
 {
@@ -3034,9 +3064,7 @@ void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
 
         /* disable queue to avoid issues while updating state */
         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
-        IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
-                        rxdctl & ~IXGBE_RXDCTL_ENABLE);
-        IXGBE_WRITE_FLUSH(hw);
+        ixgbe_disable_rx_queue(adapter, ring);
 
         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
@@ -4064,7 +4092,11 @@ void ixgbe_down(struct ixgbe_adapter *adapter)
         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
 
-        IXGBE_WRITE_FLUSH(hw);
+        /* disable all enabled rx queues */
+        for (i = 0; i < adapter->num_rx_queues; i++)
+                /* this call also flushes the previous write */
+                ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
+
         msleep(10);
 
         netif_tx_stop_all_queues(netdev);
@@ -4789,6 +4821,12 @@ static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
 
         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
+        if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE |
+                              IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
+                e_err(probe,
+                      "Flow Director is not supported while multiple "
+                      "queues are disabled.  Disabling Flow Director\n");
+        }
         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
         adapter->atr_sample_rate = 0;
@@ -5094,16 +5132,11 @@ static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
-                if (dev->features & NETIF_F_NTUPLE) {
-                        /* Flow Director perfect filter enabled */
-                        adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
-                        adapter->atr_sample_rate = 0;
-                        spin_lock_init(&adapter->fdir_perfect_lock);
-                } else {
-                        /* Flow Director hash filters enabled */
-                        adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
-                        adapter->atr_sample_rate = 20;
-                }
+                /* n-tuple support exists, always init our spinlock */
+                spin_lock_init(&adapter->fdir_perfect_lock);
+                /* Flow Director hash filters enabled */
+                adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
+                adapter->atr_sample_rate = 20;
                 adapter->ring_feature[RING_F_FDIR].indices =
                                                          IXGBE_MAX_FDIR_INDICES;
                 adapter->fdir_pballoc = 0;
@@ -6474,38 +6507,92 @@ static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
         writel(i, tx_ring->tail);
 }
 
-static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
-                      u8 queue, u32 tx_flags, __be16 protocol)
+static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
+                      u32 tx_flags, __be16 protocol)
 {
-        struct ixgbe_atr_input atr_input;
-        struct iphdr *iph = ip_hdr(skb);
-        struct ethhdr *eth = (struct ethhdr *)skb->data;
+        struct ixgbe_q_vector *q_vector = ring->q_vector;
+        union ixgbe_atr_hash_dword input = { .dword = 0 };
+        union ixgbe_atr_hash_dword common = { .dword = 0 };
+        union {
+                unsigned char *network;
+                struct iphdr *ipv4;
+                struct ipv6hdr *ipv6;
+        } hdr;
         struct tcphdr *th;
-        u16 vlan_id;
+        __be16 vlan_id;
 
-        /* Right now, we support IPv4 w/ TCP only */
-        if (protocol != htons(ETH_P_IP) ||
-            iph->protocol != IPPROTO_TCP)
+        /* if ring doesn't have a interrupt vector, cannot perform ATR */
+        if (!q_vector)
                 return;
 
-        memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
+        /* do nothing if sampling is disabled */
+        if (!ring->atr_sample_rate)
+                return;
 
-        vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
-                   IXGBE_TX_FLAGS_VLAN_SHIFT;
+        ring->atr_count++;
+
+        /* snag network header to get L4 type and address */
+        hdr.network = skb_network_header(skb);
+
+        /* Currently only IPv4/IPv6 with TCP is supported */
+        if ((protocol != __constant_htons(ETH_P_IPV6) ||
+             hdr.ipv6->nexthdr != IPPROTO_TCP) &&
+            (protocol != __constant_htons(ETH_P_IP) ||
+             hdr.ipv4->protocol != IPPROTO_TCP))
+                return;
 
         th = tcp_hdr(skb);
 
-        ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
-        ixgbe_atr_set_src_port_82599(&atr_input, th->dest);
-        ixgbe_atr_set_dst_port_82599(&atr_input, th->source);
-        ixgbe_atr_set_flex_byte_82599(&atr_input, eth->h_proto);
-        ixgbe_atr_set_l4type_82599(&atr_input, IXGBE_ATR_L4TYPE_TCP);
-        /* src and dst are inverted, think how the receiver sees them */
-        ixgbe_atr_set_src_ipv4_82599(&atr_input, iph->daddr);
-        ixgbe_atr_set_dst_ipv4_82599(&atr_input, iph->saddr);
+        /* skip this packet since the socket is closing */
+        if (th->fin)
+                return;
+
+        /* sample on all syn packets or once every atr sample count */
+        if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
+                return;
+
+        /* reset sample count */
+        ring->atr_count = 0;
+
+        vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
+
+        /*
+         * src and dst are inverted, think how the receiver sees them
+         *
+         * The input is broken into two sections, a non-compressed section
+         * containing vm_pool, vlan_id, and flow_type.  The rest of the data
+         * is XORed together and stored in the compressed dword.
+         */
+        input.formatted.vlan_id = vlan_id;
+
+        /*
+         * since src port and flex bytes occupy the same word XOR them together
+         * and write the value to source port portion of compressed dword
+         */
+        if (vlan_id)
+                common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
+        else
+                common.port.src ^= th->dest ^ protocol;
+        common.port.dst ^= th->source;
+
+        if (protocol == __constant_htons(ETH_P_IP)) {
+                input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
+                common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
+        } else {
+                input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
+                common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
+                             hdr.ipv6->saddr.s6_addr32[1] ^
+                             hdr.ipv6->saddr.s6_addr32[2] ^
+                             hdr.ipv6->saddr.s6_addr32[3] ^
+                             hdr.ipv6->daddr.s6_addr32[0] ^
+                             hdr.ipv6->daddr.s6_addr32[1] ^
+                             hdr.ipv6->daddr.s6_addr32[2] ^
+                             hdr.ipv6->daddr.s6_addr32[3];
+        }
 
         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
-        ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
+        ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
+                                              input, common, ring->queue_index);
 }
 
 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
@@ -6676,16 +6763,8 @@ netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
         if (count) {
                 /* add the ATR filter if ATR is on */
-                if (tx_ring->atr_sample_rate) {
-                        ++tx_ring->atr_count;
-                        if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
-                             test_bit(__IXGBE_TX_FDIR_INIT_DONE,
-                                      &tx_ring->state)) {
-                                ixgbe_atr(adapter, skb, tx_ring->queue_index,
-                                          tx_flags, protocol);
-                                tx_ring->atr_count = 0;
-                        }
-                }
+                if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
+                        ixgbe_atr(tx_ring, skb, tx_flags, protocol);
                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
                 txq->tx_bytes += skb->len;
                 txq->tx_packets++;
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index 446f3467d3c7..fd3358f54139 100644
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -1947,10 +1947,9 @@ enum ixgbe_fdir_pballoc_type {
 #define IXGBE_FDIRM_VLANID                      0x00000001
 #define IXGBE_FDIRM_VLANP                       0x00000002
 #define IXGBE_FDIRM_POOL                        0x00000004
-#define IXGBE_FDIRM_L3P                         0x00000008
-#define IXGBE_FDIRM_L4P                         0x00000010
-#define IXGBE_FDIRM_FLEX                        0x00000020
-#define IXGBE_FDIRM_DIPv6                       0x00000040
+#define IXGBE_FDIRM_L4P                         0x00000008
+#define IXGBE_FDIRM_FLEX                        0x00000010
+#define IXGBE_FDIRM_DIPv6                       0x00000020
 
 #define IXGBE_FDIRFREE_FREE_MASK                0xFFFF
 #define IXGBE_FDIRFREE_FREE_SHIFT               0
@@ -1990,6 +1989,7 @@ enum ixgbe_fdir_pballoc_type {
 #define IXGBE_FDIRCMD_LAST                      0x00000800
 #define IXGBE_FDIRCMD_COLLISION                 0x00001000
 #define IXGBE_FDIRCMD_QUEUE_EN                  0x00008000
+#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT           5
 #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT            16
 #define IXGBE_FDIRCMD_VT_POOL_SHIFT             24
 #define IXGBE_FDIR_INIT_DONE_POLL               10
@@ -2147,51 +2147,80 @@ typedef u32 ixgbe_physical_layer;
 #define FC_LOW_WATER(MTU)  (2 * (2 * PAUSE_MTU(MTU) + PAUSE_RTT))
 
 /* Software ATR hash keys */
-#define IXGBE_ATR_BUCKET_HASH_KEY    0xE214AD3D
-#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x14364D17
-
-/* Software ATR input stream offsets and masks */
-#define IXGBE_ATR_VLAN_OFFSET       0
-#define IXGBE_ATR_SRC_IPV6_OFFSET   2
-#define IXGBE_ATR_SRC_IPV4_OFFSET  14
-#define IXGBE_ATR_DST_IPV6_OFFSET  18
-#define IXGBE_ATR_DST_IPV4_OFFSET  30
-#define IXGBE_ATR_SRC_PORT_OFFSET  34
-#define IXGBE_ATR_DST_PORT_OFFSET  36
-#define IXGBE_ATR_FLEX_BYTE_OFFSET 38
-#define IXGBE_ATR_VM_POOL_OFFSET   40
-#define IXGBE_ATR_L4TYPE_OFFSET    41
+#define IXGBE_ATR_BUCKET_HASH_KEY    0x3DAD14E2
+#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
 
+/* Software ATR input stream values and masks */
+#define IXGBE_ATR_HASH_MASK     0x7fff
 #define IXGBE_ATR_L4TYPE_MASK      0x3
-#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
 #define IXGBE_ATR_L4TYPE_UDP       0x1
 #define IXGBE_ATR_L4TYPE_TCP       0x2
 #define IXGBE_ATR_L4TYPE_SCTP      0x3
-#define IXGBE_ATR_HASH_MASK     0x7fff
+#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
+enum ixgbe_atr_flow_type {
+        IXGBE_ATR_FLOW_TYPE_IPV4   = 0x0,
+        IXGBE_ATR_FLOW_TYPE_UDPV4  = 0x1,
+        IXGBE_ATR_FLOW_TYPE_TCPV4  = 0x2,
+        IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
+        IXGBE_ATR_FLOW_TYPE_IPV6   = 0x4,
+        IXGBE_ATR_FLOW_TYPE_UDPV6  = 0x5,
+        IXGBE_ATR_FLOW_TYPE_TCPV6  = 0x6,
+        IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
+};
 
 /* Flow Director ATR input struct. */
-struct ixgbe_atr_input {
-        /* Byte layout in order, all values with MSB first:
+union ixgbe_atr_input {
+        /*
+         * Byte layout in order, all values with MSB first:
          *
+         * vm_pool    - 1 byte
+         * flow_type  - 1 byte
          * vlan_id    - 2 bytes
          * src_ip     - 16 bytes
          * dst_ip     - 16 bytes
          * src_port   - 2 bytes
          * dst_port   - 2 bytes
          * flex_bytes - 2 bytes
-         * vm_pool    - 1 byte
-         * l4type     - 1 byte
+         * rsvd0      - 2 bytes - space reserved must be 0.
          */
-        u8 byte_stream[42];
+        struct {
+                u8     vm_pool;
+                u8     flow_type;
+                __be16 vlan_id;
+                __be32 dst_ip[4];
+                __be32 src_ip[4];
+                __be16 src_port;
+                __be16 dst_port;
+                __be16 flex_bytes;
+                __be16 rsvd0;
+        } formatted;
+        __be32 dword_stream[11];
+};
+
+/* Flow Director compressed ATR hash input struct */
+union ixgbe_atr_hash_dword {
+        struct {
+                u8 vm_pool;
+                u8 flow_type;
+                __be16 vlan_id;
+        } formatted;
+        __be32 ip;
+        struct {
+                __be16 src;
+                __be16 dst;
+        } port;
+        __be16 flex_bytes;
+        __be32 dword;
 };
 
 struct ixgbe_atr_input_masks {
-        u32 src_ip_mask;
-        u32 dst_ip_mask;
-        u16 src_port_mask;
-        u16 dst_port_mask;
-        u16 vlan_id_mask;
-        u16 data_mask;
+        __be16 rsvd0;
+        __be16 vlan_id_mask;
+        __be32 dst_ip_mask[4];
+        __be32 src_ip_mask[4];
+        __be16 src_port_mask;
+        __be16 dst_port_mask;
+        __be16 flex_mask;
 };
 
 enum ixgbe_eeprom_type {
diff --git a/drivers/net/mlx4/alloc.c b/drivers/net/mlx4/alloc.c
index 8f4bf1f07c11..3a4277f6fac4 100644
--- a/drivers/net/mlx4/alloc.c
+++ b/drivers/net/mlx4/alloc.c
@@ -178,6 +178,7 @@ int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
         } else {
                 int i;
 
+                buf->direct.buf  = NULL;
                 buf->nbufs       = (size + PAGE_SIZE - 1) / PAGE_SIZE;
                 buf->npages      = buf->nbufs;
                 buf->page_shift  = PAGE_SHIFT;
@@ -229,7 +230,7 @@ void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf)
                 dma_free_coherent(&dev->pdev->dev, size, buf->direct.buf,
                                   buf->direct.map);
         else {
-                if (BITS_PER_LONG == 64)
+                if (BITS_PER_LONG == 64 && buf->direct.buf)
                         vunmap(buf->direct.buf);
 
                 for (i = 0; i < buf->nbufs; ++i)
diff --git a/drivers/net/mlx4/en_netdev.c b/drivers/net/mlx4/en_netdev.c
index 6d6806b361e3..897f576b8b17 100644
--- a/drivers/net/mlx4/en_netdev.c
+++ b/drivers/net/mlx4/en_netdev.c
@@ -972,7 +972,8 @@ int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
         int i;
         int err;
 
-        dev = alloc_etherdev_mq(sizeof(struct mlx4_en_priv), prof->tx_ring_num);
+        dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),
+            prof->tx_ring_num, prof->rx_ring_num);
         if (dev == NULL) {
                 mlx4_err(mdev, "Net device allocation failed\n");
                 return -ENOMEM;
diff --git a/drivers/net/mlx4/fw.c b/drivers/net/mlx4/fw.c
index 7a7e18ba278a..5de1db897835 100644
--- a/drivers/net/mlx4/fw.c
+++ b/drivers/net/mlx4/fw.c
@@ -289,10 +289,8 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
                 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
                 dev_cap->bf_reg_size = 1 << (field & 0x1f);
                 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
-                if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) {
-                        mlx4_warn(dev, "firmware bug: log2 # of blue flame regs is invalid (%d), forcing 3\n", field & 0x1f);
+                if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
                         field = 3;
-                }
                 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
                 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
                          dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
diff --git a/drivers/net/pcmcia/pcnet_cs.c b/drivers/net/pcmcia/pcnet_cs.c
index 2c158910f7ea..e953793a33ff 100644
--- a/drivers/net/pcmcia/pcnet_cs.c
+++ b/drivers/net/pcmcia/pcnet_cs.c
@@ -1536,6 +1536,7 @@ static struct pcmcia_device_id pcnet_ids[] = {
         PCMCIA_DEVICE_PROD_ID12("CONTEC", "C-NET(PC)C-10L", 0x21cab552, 0xf6f90722),
         PCMCIA_DEVICE_PROD_ID12("corega", "FEther PCC-TXF", 0x0a21501a, 0xa51564a2),
         PCMCIA_DEVICE_PROD_ID12("corega", "Ether CF-TD", 0x0a21501a, 0x6589340a),
+        PCMCIA_DEVICE_PROD_ID12("corega K.K.", "corega Ether CF-TD LAN Card", 0x5261440f, 0x8797663b),
         PCMCIA_DEVICE_PROD_ID12("corega K.K.", "corega EtherII PCC-T", 0x5261440f, 0xfa9d85bd),
         PCMCIA_DEVICE_PROD_ID12("corega K.K.", "corega EtherII PCC-TD", 0x5261440f, 0xc49bd73d),
         PCMCIA_DEVICE_PROD_ID12("Corega K.K.", "corega EtherII PCC-TD", 0xd4fdcbd8, 0xc49bd73d),
diff --git a/drivers/net/ppp_async.c b/drivers/net/ppp_async.c
index 78d70a6481bf..a1b82c9c67d2 100644
--- a/drivers/net/ppp_async.c
+++ b/drivers/net/ppp_async.c
@@ -32,6 +32,7 @@
 #include <linux/init.h>
 #include <linux/jiffies.h>
 #include <linux/slab.h>
+#include <asm/unaligned.h>
 #include <asm/uaccess.h>
 #include <asm/string.h>
 
@@ -542,7 +543,7 @@ ppp_async_encode(struct asyncppp *ap)
         data = ap->tpkt->data;
         count = ap->tpkt->len;
         fcs = ap->tfcs;
-        proto = (data[0] << 8) + data[1];
+        proto = get_unaligned_be16(data);
 
         /*
          * LCP packets with code values between 1 (configure-reqest)
@@ -963,7 +964,7 @@ static void async_lcp_peek(struct asyncppp *ap, unsigned char *data,
         code = data[0];
         if (code != CONFACK && code != CONFREQ)
                 return;
-        dlen = (data[2] << 8) + data[3];
+        dlen = get_unaligned_be16(data + 2);
         if (len < dlen)
                 return;         /* packet got truncated or length is bogus */
 
@@ -997,15 +998,14 @@ static void async_lcp_peek(struct asyncppp *ap, unsigned char *data,
         while (dlen >= 2 && dlen >= data[1] && data[1] >= 2) {
                 switch (data[0]) {
                 case LCP_MRU:
-                        val = (data[2] << 8) + data[3];
+                        val = get_unaligned_be16(data + 2);
                         if (inbound)
                                 ap->mru = val;
                         else
                                 ap->chan.mtu = val;
                         break;
                 case LCP_ASYNCMAP:
-                        val = (data[2] << 24) + (data[3] << 16)
-                                + (data[4] << 8) + data[5];
+                        val = get_unaligned_be32(data + 2);
                         if (inbound)
                                 ap->raccm = val;
                         else
diff --git a/drivers/net/ppp_deflate.c b/drivers/net/ppp_deflate.c
index 695bc83e0cfd..43583309a65d 100644
--- a/drivers/net/ppp_deflate.c
+++ b/drivers/net/ppp_deflate.c
@@ -41,6 +41,7 @@
 #include <linux/ppp-comp.h>
 
 #include <linux/zlib.h>
+#include <asm/unaligned.h>
 
 /*
  * State for a Deflate (de)compressor.
@@ -232,11 +233,9 @@ static int z_compress(void *arg, unsigned char *rptr, unsigned char *obuf,
          */
         wptr[0] = PPP_ADDRESS(rptr);
         wptr[1] = PPP_CONTROL(rptr);
-        wptr[2] = PPP_COMP >> 8;
-        wptr[3] = PPP_COMP;
+        put_unaligned_be16(PPP_COMP, wptr + 2);
         wptr += PPP_HDRLEN;
-        wptr[0] = state->seqno >> 8;
-        wptr[1] = state->seqno;
+        put_unaligned_be16(state->seqno, wptr);
         wptr += DEFLATE_OVHD;
         olen = PPP_HDRLEN + DEFLATE_OVHD;
         state->strm.next_out = wptr;
@@ -451,7 +450,7 @@ static int z_decompress(void *arg, unsigned char *ibuf, int isize,
         }
 
         /* Check the sequence number. */
-        seq = (ibuf[PPP_HDRLEN] << 8) + ibuf[PPP_HDRLEN+1];
+        seq = get_unaligned_be16(ibuf + PPP_HDRLEN);
         if (seq != (state->seqno & 0xffff)) {
                 if (state->debug)
                         printk(KERN_DEBUG "z_decompress%d: bad seq # %d, expected %d\n",
diff --git a/drivers/net/ppp_generic.c b/drivers/net/ppp_generic.c
index 6456484c0299..c7a6c4466978 100644
--- a/drivers/net/ppp_generic.c
+++ b/drivers/net/ppp_generic.c
@@ -46,6 +46,7 @@
 #include <linux/device.h>
 #include <linux/mutex.h>
 #include <linux/slab.h>
+#include <asm/unaligned.h>
 #include <net/slhc_vj.h>
 #include <asm/atomic.h>
 
@@ -210,7 +211,7 @@ struct ppp_net {
 };
 
 /* Get the PPP protocol number from a skb */
-#define PPP_PROTO(skb)  (((skb)->data[0] << 8) + (skb)->data[1])
+#define PPP_PROTO(skb)  get_unaligned_be16((skb)->data)
 
 /* We limit the length of ppp->file.rq to this (arbitrary) value */
 #define PPP_MAX_RQLEN   32
@@ -964,8 +965,7 @@ ppp_start_xmit(struct sk_buff *skb, struct net_device *dev)
 
         pp = skb_push(skb, 2);
         proto = npindex_to_proto[npi];
-        pp[0] = proto >> 8;
-        pp[1] = proto;
+        put_unaligned_be16(proto, pp);
 
         netif_stop_queue(dev);
         skb_queue_tail(&ppp->file.xq, skb);
@@ -1473,8 +1473,7 @@ static int ppp_mp_explode(struct ppp *ppp, struct sk_buff *skb)
                 q = skb_put(frag, flen + hdrlen);
 
                 /* make the MP header */
-                q[0] = PPP_MP >> 8;
-                q[1] = PPP_MP;
+                put_unaligned_be16(PPP_MP, q);
                 if (ppp->flags & SC_MP_XSHORTSEQ) {
                         q[2] = bits + ((ppp->nxseq >> 8) & 0xf);
                         q[3] = ppp->nxseq;
diff --git a/drivers/net/ppp_mppe.c b/drivers/net/ppp_mppe.c
index 6d1a1b80cc3e..9a1849a83e2a 100644
--- a/drivers/net/ppp_mppe.c
+++ b/drivers/net/ppp_mppe.c
@@ -55,6 +55,7 @@
 #include <linux/ppp_defs.h>
 #include <linux/ppp-comp.h>
 #include <linux/scatterlist.h>
+#include <asm/unaligned.h>
 
 #include "ppp_mppe.h"
 
@@ -395,16 +396,14 @@ mppe_compress(void *arg, unsigned char *ibuf, unsigned char *obuf,
          */
         obuf[0] = PPP_ADDRESS(ibuf);
         obuf[1] = PPP_CONTROL(ibuf);
-        obuf[2] = PPP_COMP >> 8;        /* isize + MPPE_OVHD + 1 */
-        obuf[3] = PPP_COMP;     /* isize + MPPE_OVHD + 2 */
+        put_unaligned_be16(PPP_COMP, obuf + 2);
         obuf += PPP_HDRLEN;
 
         state->ccount = (state->ccount + 1) % MPPE_CCOUNT_SPACE;
         if (state->debug >= 7)
                 printk(KERN_DEBUG "mppe_compress[%d]: ccount %d\n", state->unit,
                        state->ccount);
-        obuf[0] = state->ccount >> 8;
-        obuf[1] = state->ccount & 0xff;
+        put_unaligned_be16(state->ccount, obuf);
 
         if (!state->stateful || /* stateless mode     */
             ((state->ccount & 0xff) == 0xff) || /* "flag" packet      */
diff --git a/drivers/net/ppp_synctty.c b/drivers/net/ppp_synctty.c
index 4c95ec3fb8d4..4e6b72f57de8 100644
--- a/drivers/net/ppp_synctty.c
+++ b/drivers/net/ppp_synctty.c
@@ -45,6 +45,7 @@
 #include <linux/completion.h>
 #include <linux/init.h>
 #include <linux/slab.h>
+#include <asm/unaligned.h>
 #include <asm/uaccess.h>
 
 #define PPP_VERSION     "2.4.2"
@@ -563,7 +564,7 @@ ppp_sync_txmunge(struct syncppp *ap, struct sk_buff *skb)
         int islcp;
 
         data  = skb->data;
-        proto = (data[0] << 8) + data[1];
+        proto = get_unaligned_be16(data);
 
         /* LCP packets with codes between 1 (configure-request)
          * and 7 (code-reject) must be sent as though no options
diff --git a/drivers/net/qlcnic/qlcnic.h b/drivers/net/qlcnic/qlcnic.h
index 9c2a02d204dc..44e316fd67b8 100644
--- a/drivers/net/qlcnic/qlcnic.h
+++ b/drivers/net/qlcnic/qlcnic.h
@@ -34,8 +34,8 @@
 
 #define _QLCNIC_LINUX_MAJOR 5
 #define _QLCNIC_LINUX_MINOR 0
-#define _QLCNIC_LINUX_SUBVERSION 14
-#define QLCNIC_LINUX_VERSIONID  "5.0.14"
+#define _QLCNIC_LINUX_SUBVERSION 15
+#define QLCNIC_LINUX_VERSIONID  "5.0.15"
 #define QLCNIC_DRV_IDC_VER  0x01
 #define QLCNIC_DRIVER_VERSION  ((_QLCNIC_LINUX_MAJOR << 16) |\
                  (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
@@ -289,6 +289,26 @@ struct uni_data_desc{
         u32     reserved[5];
 };
 
+/* Flash Defines and Structures */
+#define QLCNIC_FLT_LOCATION     0x3F1000
+#define QLCNIC_FW_IMAGE_REGION  0x74
+struct qlcnic_flt_header {
+        u16 version;
+        u16 len;
+        u16 checksum;
+        u16 reserved;
+};
+
+struct qlcnic_flt_entry {
+        u8 region;
+        u8 reserved0;
+        u8 attrib;
+        u8 reserved1;
+        u32 size;
+        u32 start_addr;
+        u32 end_add;
+};
+
 /* Magic number to let user know flash is programmed */
 #define QLCNIC_BDINFO_MAGIC 0x12345678
 
diff --git a/drivers/net/qlcnic/qlcnic_ethtool.c b/drivers/net/qlcnic/qlcnic_ethtool.c
index 1e7af709d395..4c14510e2a87 100644
--- a/drivers/net/qlcnic/qlcnic_ethtool.c
+++ b/drivers/net/qlcnic/qlcnic_ethtool.c
@@ -672,7 +672,7 @@ qlcnic_diag_test(struct net_device *dev, struct ethtool_test *eth_test,
         if (data[1])
                 eth_test->flags |= ETH_TEST_FL_FAILED;
 
-        if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
+        if (eth_test->flags & ETH_TEST_FL_OFFLINE) {
                 data[2] = qlcnic_irq_test(dev);
                 if (data[2])
                         eth_test->flags |= ETH_TEST_FL_FAILED;
diff --git a/drivers/net/qlcnic/qlcnic_init.c b/drivers/net/qlcnic/qlcnic_init.c
index 9b9c7c39d3ee..a7f1d5b7e811 100644
--- a/drivers/net/qlcnic/qlcnic_init.c
+++ b/drivers/net/qlcnic/qlcnic_init.c
@@ -627,12 +627,73 @@ qlcnic_setup_idc_param(struct qlcnic_adapter *adapter) {
         return 0;
 }
 
+static int qlcnic_get_flt_entry(struct qlcnic_adapter *adapter, u8 region,
+                                struct qlcnic_flt_entry *region_entry)
+{
+        struct qlcnic_flt_header flt_hdr;
+        struct qlcnic_flt_entry *flt_entry;
+        int i = 0, ret;
+        u32 entry_size;
+
+        memset(region_entry, 0, sizeof(struct qlcnic_flt_entry));
+        ret = qlcnic_rom_fast_read_words(adapter, QLCNIC_FLT_LOCATION,
+                                         (u8 *)&flt_hdr,
+                                         sizeof(struct qlcnic_flt_header));
+        if (ret) {
+                dev_warn(&adapter->pdev->dev,
+                         "error reading flash layout header\n");
+                return -EIO;
+        }
+
+        entry_size = flt_hdr.len - sizeof(struct qlcnic_flt_header);
+        flt_entry = (struct qlcnic_flt_entry *)vzalloc(entry_size);
+        if (flt_entry == NULL) {
+                dev_warn(&adapter->pdev->dev, "error allocating memory\n");
+                return -EIO;
+        }
+
+        ret = qlcnic_rom_fast_read_words(adapter, QLCNIC_FLT_LOCATION +
+                                         sizeof(struct qlcnic_flt_header),
+                                         (u8 *)flt_entry, entry_size);
+        if (ret) {
+                dev_warn(&adapter->pdev->dev,
+                         "error reading flash layout entries\n");
+                goto err_out;
+        }
+
+        while (i < (entry_size/sizeof(struct qlcnic_flt_entry))) {
+                if (flt_entry[i].region == region)
+                        break;
+                i++;
+        }
+        if (i >= (entry_size/sizeof(struct qlcnic_flt_entry))) {
+                dev_warn(&adapter->pdev->dev,
+                         "region=%x not found in %d regions\n", region, i);
+                ret = -EIO;
+                goto err_out;
+        }
+        memcpy(region_entry, &flt_entry[i], sizeof(struct qlcnic_flt_entry));
+
+err_out:
+        vfree(flt_entry);
+        return ret;
+}
+
 int
 qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter)
 {
+        struct qlcnic_flt_entry fw_entry;
         u32 ver = -1, min_ver;
+        int ret;
 
-        qlcnic_rom_fast_read(adapter, QLCNIC_FW_VERSION_OFFSET, (int *)&ver);
+        ret = qlcnic_get_flt_entry(adapter, QLCNIC_FW_IMAGE_REGION, &fw_entry);
+        if (!ret)
+                /* 0-4:-signature,  4-8:-fw version */
+                qlcnic_rom_fast_read(adapter, fw_entry.start_addr + 4,
+                                     (int *)&ver);
+        else
+                qlcnic_rom_fast_read(adapter, QLCNIC_FW_VERSION_OFFSET,
+                                     (int *)&ver);
 
         ver = QLCNIC_DECODE_VERSION(ver);
         min_ver = QLCNIC_MIN_FW_VERSION;
diff --git a/drivers/net/qlcnic/qlcnic_main.c b/drivers/net/qlcnic/qlcnic_main.c
index 11e3a46c0911..37c04b4fade3 100644
--- a/drivers/net/qlcnic/qlcnic_main.c
+++ b/drivers/net/qlcnic/qlcnic_main.c
@@ -31,15 +31,15 @@ static const char qlcnic_driver_string[] = "QLogic 1/10 GbE "
 
 static struct workqueue_struct *qlcnic_wq;
 static int qlcnic_mac_learn;
-module_param(qlcnic_mac_learn, int, 0644);
+module_param(qlcnic_mac_learn, int, 0444);
 MODULE_PARM_DESC(qlcnic_mac_learn, "Mac Filter (0=disabled, 1=enabled)");
 
 static int use_msi = 1;
-module_param(use_msi, int, 0644);
+module_param(use_msi, int, 0444);
 MODULE_PARM_DESC(use_msi, "MSI interrupt (0=disabled, 1=enabled");
 
 static int use_msi_x = 1;
-module_param(use_msi_x, int, 0644);
+module_param(use_msi_x, int, 0444);
 MODULE_PARM_DESC(use_msi_x, "MSI-X interrupt (0=disabled, 1=enabled");
 
 static int auto_fw_reset = AUTO_FW_RESET_ENABLED;
@@ -47,11 +47,11 @@ module_param(auto_fw_reset, int, 0644);
 MODULE_PARM_DESC(auto_fw_reset, "Auto firmware reset (0=disabled, 1=enabled");
 
 static int load_fw_file;
-module_param(load_fw_file, int, 0644);
+module_param(load_fw_file, int, 0444);
 MODULE_PARM_DESC(load_fw_file, "Load firmware from (0=flash, 1=file");
 
 static int qlcnic_config_npars;
-module_param(qlcnic_config_npars, int, 0644);
+module_param(qlcnic_config_npars, int, 0444);
 MODULE_PARM_DESC(qlcnic_config_npars, "Configure NPARs (0=disabled, 1=enabled");
 
 static int __devinit qlcnic_probe(struct pci_dev *pdev,
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index 27a7c20f64cd..bb8645ab247c 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -1632,36 +1632,134 @@ rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
 {
         __le32 *phytable = (__le32 *)fw->data;
         struct net_device *dev = tp->dev;
-        size_t i;
+        size_t index, fw_size = fw->size / sizeof(*phytable);
+        u32 predata, count;
 
         if (fw->size % sizeof(*phytable)) {
                 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
                 return;
         }
 
-        for (i = 0; i < fw->size / sizeof(*phytable); i++) {
-                u32 action = le32_to_cpu(phytable[i]);
+        for (index = 0; index < fw_size; index++) {
+                u32 action = le32_to_cpu(phytable[index]);
+                u32 regno = (action & 0x0fff0000) >> 16;
 
-                if (!action)
+                switch(action & 0xf0000000) {
+                case PHY_READ:
+                case PHY_DATA_OR:
+                case PHY_DATA_AND:
+                case PHY_READ_EFUSE:
+                case PHY_CLEAR_READCOUNT:
+                case PHY_WRITE:
+                case PHY_WRITE_PREVIOUS:
+                case PHY_DELAY_MS:
+                        break;
+
+                case PHY_BJMPN:
+                        if (regno > index) {
+                                netif_err(tp, probe, tp->dev,
+                                        "Out of range of firmware\n");
+                                return;
+                        }
+                        break;
+                case PHY_READCOUNT_EQ_SKIP:
+                        if (index + 2 >= fw_size) {
+                                netif_err(tp, probe, tp->dev,
+                                        "Out of range of firmware\n");
+                                return;
+                        }
+                        break;
+                case PHY_COMP_EQ_SKIPN:
+                case PHY_COMP_NEQ_SKIPN:
+                case PHY_SKIPN:
+                        if (index + 1 + regno >= fw_size) {
+                                netif_err(tp, probe, tp->dev,
+                                        "Out of range of firmware\n");
+                                return;
+                        }
                         break;
 
-                if ((action & 0xf0000000) != PHY_WRITE) {
-                        netif_err(tp, probe, dev,
-                                  "unknown action 0x%08x\n", action);
+                case PHY_READ_MAC_BYTE:
+                case PHY_WRITE_MAC_BYTE:
+                case PHY_WRITE_ERI_WORD:
+                default:
+                        netif_err(tp, probe, tp->dev,
+                                  "Invalid action 0x%08x\n", action);
                         return;
                 }
         }
 
-        while (i-- != 0) {
-                u32 action = le32_to_cpu(*phytable);
+        predata = 0;
+        count = 0;
+
+        for (index = 0; index < fw_size; ) {
+                u32 action = le32_to_cpu(phytable[index]);
                 u32 data = action & 0x0000ffff;
-                u32 reg = (action & 0x0fff0000) >> 16;
+                u32 regno = (action & 0x0fff0000) >> 16;
+
+                if (!action)
+                        break;
 
                 switch(action & 0xf0000000) {
+                case PHY_READ:
+                        predata = rtl_readphy(tp, regno);
+                        count++;
+                        index++;
+                        break;
+                case PHY_DATA_OR:
+                        predata |= data;
+                        index++;
+                        break;
+                case PHY_DATA_AND:
+                        predata &= data;
+                        index++;
+                        break;
+                case PHY_BJMPN:
+                        index -= regno;
+                        break;
+                case PHY_READ_EFUSE:
+                        predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
+                        index++;
+                        break;
+                case PHY_CLEAR_READCOUNT:
+                        count = 0;
+                        index++;
+                        break;
                 case PHY_WRITE:
-                        rtl_writephy(tp, reg, data);
-                        phytable++;
+                        rtl_writephy(tp, regno, data);
+                        index++;
+                        break;
+                case PHY_READCOUNT_EQ_SKIP:
+                        if (count == data)
+                                index += 2;
+                        else
+                                index += 1;
+                        break;
+                case PHY_COMP_EQ_SKIPN:
+                        if (predata == data)
+                                index += regno;
+                        index++;
                         break;
+                case PHY_COMP_NEQ_SKIPN:
+                        if (predata != data)
+                                index += regno;
+                        index++;
+                        break;
+                case PHY_WRITE_PREVIOUS:
+                        rtl_writephy(tp, regno, predata);
+                        index++;
+                        break;
+                case PHY_SKIPN:
+                        index += regno + 1;
+                        break;
+                case PHY_DELAY_MS:
+                        mdelay(data);
+                        index++;
+                        break;
+
+                case PHY_READ_MAC_BYTE:
+                case PHY_WRITE_MAC_BYTE:
+                case PHY_WRITE_ERI_WORD:
                 default:
                         BUG();
                 }
@@ -3069,15 +3167,6 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
                 rtl8168_driver_start(tp);
         }
 
-        rtl8169_init_phy(dev, tp);
-
-        /*
-         * Pretend we are using VLANs; This bypasses a nasty bug where
-         * Interrupts stop flowing on high load on 8110SCd controllers.
-         */
-        if (tp->mac_version == RTL_GIGA_MAC_VER_05)
-                RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
-
         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
 
         if (pci_dev_run_wake(pdev))
@@ -3127,6 +3216,7 @@ static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
 static int rtl8169_open(struct net_device *dev)
 {
         struct rtl8169_private *tp = netdev_priv(dev);
+        void __iomem *ioaddr = tp->mmio_addr;
         struct pci_dev *pdev = tp->pci_dev;
         int retval = -ENOMEM;
 
@@ -3162,6 +3252,15 @@ static int rtl8169_open(struct net_device *dev)
 
         napi_enable(&tp->napi);
 
+        rtl8169_init_phy(dev, tp);
+
+        /*
+         * Pretend we are using VLANs; This bypasses a nasty bug where
+         * Interrupts stop flowing on high load on 8110SCd controllers.
+         */
+        if (tp->mac_version == RTL_GIGA_MAC_VER_05)
+                RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
+
         rtl_pll_power_up(tp);
 
         rtl_hw_start(dev);
@@ -3171,7 +3270,7 @@ static int rtl8169_open(struct net_device *dev)
         tp->saved_wolopts = 0;
         pm_runtime_put_noidle(&pdev->dev);
 
-        rtl8169_check_link_status(dev, tp, tp->mmio_addr);
+        rtl8169_check_link_status(dev, tp, ioaddr);
 out:
         return retval;
 
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 39996bf3b247..7d85a38377a1 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -46,10 +46,6 @@
 
 #include <asm/irq.h>
 
-#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
-#define SKY2_VLAN_TAG_USED 1
-#endif
-
 #include "sky2.h"
 
 #define DRV_NAME                "sky2"
@@ -1326,40 +1322,35 @@ static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
         return err;
 }
 
-#ifdef SKY2_VLAN_TAG_USED
-static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
+#define NETIF_F_ALL_VLAN (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX)
+
+static void sky2_vlan_mode(struct net_device *dev)
 {
-        if (onoff) {
+        struct sky2_port *sky2 = netdev_priv(dev);
+        struct sky2_hw *hw = sky2->hw;
+        u16 port = sky2->port;
+
+        if (dev->features & NETIF_F_HW_VLAN_RX)
                 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
                              RX_VLAN_STRIP_ON);
-                sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
-                             TX_VLAN_TAG_ON);
-        } else {
+        else
                 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
                              RX_VLAN_STRIP_OFF);
+
+        dev->vlan_features = dev->features &~ NETIF_F_ALL_VLAN;
+        if (dev->features & NETIF_F_HW_VLAN_TX)
+                sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
+                             TX_VLAN_TAG_ON);
+        else {
                 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
                              TX_VLAN_TAG_OFF);
+
+                /* Can't do transmit offload of vlan without hw vlan */
+                dev->vlan_features &= ~(NETIF_F_TSO | NETIF_F_SG
+                                        | NETIF_F_ALL_CSUM);
         }
 }
 
-static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
-{
-        struct sky2_port *sky2 = netdev_priv(dev);
-        struct sky2_hw *hw = sky2->hw;
-        u16 port = sky2->port;
-
-        netif_tx_lock_bh(dev);
-        napi_disable(&hw->napi);
-
-        sky2->vlgrp = grp;
-        sky2_set_vlan_mode(hw, port, grp != NULL);
-
-        sky2_read32(hw, B0_Y2_SP_LISR);
-        napi_enable(&hw->napi);
-        netif_tx_unlock_bh(dev);
-}
-#endif
-
 /* Amount of required worst case padding in rx buffer */
 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
 {
@@ -1635,9 +1626,7 @@ static void sky2_hw_up(struct sky2_port *sky2)
         sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
                            sky2->tx_ring_size - 1);
 
-#ifdef SKY2_VLAN_TAG_USED
-        sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
-#endif
+        sky2_vlan_mode(sky2->netdev);
 
         sky2_rx_start(sky2);
 }
@@ -1780,7 +1769,7 @@ static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
         }
 
         ctrl = 0;
-#ifdef SKY2_VLAN_TAG_USED
+
         /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
         if (vlan_tx_tag_present(skb)) {
                 if (!le) {
@@ -1792,7 +1781,6 @@ static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
                 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
                 ctrl |= INS_VLAN;
         }
-#endif
 
         /* Handle TCP checksum offload */
         if (skb->ip_summed == CHECKSUM_PARTIAL) {
@@ -2432,11 +2420,8 @@ static struct sk_buff *sky2_receive(struct net_device *dev,
         struct sk_buff *skb = NULL;
         u16 count = (status & GMR_FS_LEN) >> 16;
 
-#ifdef SKY2_VLAN_TAG_USED
-        /* Account for vlan tag */
-        if (sky2->vlgrp && (status & GMR_FS_VLAN))
-                count -= VLAN_HLEN;
-#endif
+        if (status & GMR_FS_VLAN)
+                count -= VLAN_HLEN;     /* Account for vlan tag */
 
         netif_printk(sky2, rx_status, KERN_DEBUG, dev,
                      "rx slot %u status 0x%x len %d\n",
@@ -2504,17 +2489,9 @@ static inline void sky2_tx_done(struct net_device *dev, u16 last)
 static inline void sky2_skb_rx(const struct sky2_port *sky2,
                                u32 status, struct sk_buff *skb)
 {
-#ifdef SKY2_VLAN_TAG_USED
-        u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
-        if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
-                if (skb->ip_summed == CHECKSUM_NONE)
-                        vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
-                else
-                        vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
-                                         vlan_tag, skb);
-                return;
-        }
-#endif
+        if (status & GMR_FS_VLAN)
+                __vlan_hwaccel_put_tag(skb, be16_to_cpu(sky2->rx_tag));
+
         if (skb->ip_summed == CHECKSUM_NONE)
                 netif_receive_skb(skb);
         else
@@ -2631,7 +2608,6 @@ static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
                                 goto exit_loop;
                         break;
 
-#ifdef SKY2_VLAN_TAG_USED
                 case OP_RXVLAN:
                         sky2->rx_tag = length;
                         break;
@@ -2639,7 +2615,6 @@ static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
                 case OP_RXCHKSVLAN:
                         sky2->rx_tag = length;
                         /* fall through */
-#endif
                 case OP_RXCHKS:
                         if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
                                 sky2_rx_checksum(sky2, status);
@@ -3042,6 +3017,10 @@ static int __devinit sky2_init(struct sky2_hw *hw)
                         | SKY2_HW_NEW_LE
                         | SKY2_HW_AUTO_TX_SUM
                         | SKY2_HW_ADV_POWER_CTL;
+
+                /* The workaround for status conflicts VLAN tag detection. */
+                if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
+                        hw->flags |= SKY2_HW_VLAN_BROKEN;
                 break;
 
         case CHIP_ID_YUKON_SUPR:
@@ -3411,18 +3390,15 @@ static u32 sky2_supported_modes(const struct sky2_hw *hw)
                 u32 modes = SUPPORTED_10baseT_Half
                         | SUPPORTED_10baseT_Full
                         | SUPPORTED_100baseT_Half
-                        | SUPPORTED_100baseT_Full
-                        | SUPPORTED_Autoneg | SUPPORTED_TP;
+                        | SUPPORTED_100baseT_Full;
 
                 if (hw->flags & SKY2_HW_GIGABIT)
                         modes |= SUPPORTED_1000baseT_Half
                                 | SUPPORTED_1000baseT_Full;
                 return modes;
         } else
-                return  SUPPORTED_1000baseT_Half
-                        | SUPPORTED_1000baseT_Full
-                        | SUPPORTED_Autoneg
-                        | SUPPORTED_FIBRE;
+                return SUPPORTED_1000baseT_Half
+                        | SUPPORTED_1000baseT_Full;
 }
 
 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
@@ -3436,9 +3412,11 @@ static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
         if (sky2_is_copper(hw)) {
                 ecmd->port = PORT_TP;
                 ecmd->speed = sky2->speed;
+                ecmd->supported |=  SUPPORTED_Autoneg | SUPPORTED_TP;
         } else {
                 ecmd->speed = SPEED_1000;
                 ecmd->port = PORT_FIBRE;
+                ecmd->supported |=  SUPPORTED_Autoneg | SUPPORTED_FIBRE;
         }
 
         ecmd->advertising = sky2->advertising;
@@ -3455,8 +3433,19 @@ static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
         u32 supported = sky2_supported_modes(hw);
 
         if (ecmd->autoneg == AUTONEG_ENABLE) {
+                if (ecmd->advertising & ~supported)
+                        return -EINVAL;
+
+                if (sky2_is_copper(hw))
+                        sky2->advertising = ecmd->advertising |
+                                            ADVERTISED_TP |
+                                            ADVERTISED_Autoneg;
+                else
+                        sky2->advertising = ecmd->advertising |
+                                            ADVERTISED_FIBRE |
+                                            ADVERTISED_Autoneg;
+
                 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
-                ecmd->advertising = supported;
                 sky2->duplex = -1;
                 sky2->speed = -1;
         } else {
@@ -3500,8 +3489,6 @@ static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
                 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
         }
 
-        sky2->advertising = ecmd->advertising;
-
         if (netif_running(dev)) {
                 sky2_phy_reinit(sky2);
                 sky2_set_multicast(dev);
@@ -4229,15 +4216,28 @@ static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom
 static int sky2_set_flags(struct net_device *dev, u32 data)
 {
         struct sky2_port *sky2 = netdev_priv(dev);
-        u32 supported =
-                (sky2->hw->flags & SKY2_HW_RSS_BROKEN) ? 0 : ETH_FLAG_RXHASH;
+        unsigned long old_feat = dev->features;
+        u32 supported = 0;
         int rc;
 
+        if (!(sky2->hw->flags & SKY2_HW_RSS_BROKEN))
+                supported |= ETH_FLAG_RXHASH;
+
+        if (!(sky2->hw->flags & SKY2_HW_VLAN_BROKEN))
+                supported |= ETH_FLAG_RXVLAN | ETH_FLAG_TXVLAN;
+
+        printk(KERN_DEBUG "sky2 set_flags: supported %x data %x\n",
+               supported, data);
+
         rc = ethtool_op_set_flags(dev, data, supported);
         if (rc)
                 return rc;
 
-        rx_set_rss(dev);
+        if ((old_feat ^ dev->features) & NETIF_F_RXHASH)
+                rx_set_rss(dev);
+
+        if ((old_feat ^ dev->features) & NETIF_F_ALL_VLAN)
+                sky2_vlan_mode(dev);
 
         return 0;
 }
@@ -4273,6 +4273,7 @@ static const struct ethtool_ops sky2_ethtool_ops = {
         .get_sset_count = sky2_get_sset_count,
         .get_ethtool_stats = sky2_get_ethtool_stats,
         .set_flags      = sky2_set_flags,
+        .get_flags      = ethtool_op_get_flags,
 };
 
 #ifdef CONFIG_SKY2_DEBUG
@@ -4554,9 +4555,6 @@ static const struct net_device_ops sky2_netdev_ops[2] = {
         .ndo_change_mtu         = sky2_change_mtu,
         .ndo_tx_timeout         = sky2_tx_timeout,
         .ndo_get_stats64        = sky2_get_stats,
-#ifdef SKY2_VLAN_TAG_USED
-        .ndo_vlan_rx_register   = sky2_vlan_rx_register,
-#endif
 #ifdef CONFIG_NET_POLL_CONTROLLER
         .ndo_poll_controller    = sky2_netpoll,
 #endif
@@ -4572,9 +4570,6 @@ static const struct net_device_ops sky2_netdev_ops[2] = {
         .ndo_change_mtu         = sky2_change_mtu,
         .ndo_tx_timeout         = sky2_tx_timeout,
         .ndo_get_stats64        = sky2_get_stats,
-#ifdef SKY2_VLAN_TAG_USED
-        .ndo_vlan_rx_register   = sky2_vlan_rx_register,
-#endif
   },
 };
 
@@ -4625,7 +4620,8 @@ static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
         sky2->port = port;
 
         dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG
-                | NETIF_F_TSO  | NETIF_F_GRO;
+                | NETIF_F_TSO | NETIF_F_GRO;
+
         if (highmem)
                 dev->features |= NETIF_F_HIGHDMA;
 
@@ -4633,13 +4629,8 @@ static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
         if (!(hw->flags & SKY2_HW_RSS_BROKEN))
                 dev->features |= NETIF_F_RXHASH;
 
-#ifdef SKY2_VLAN_TAG_USED
-        /* The workaround for FE+ status conflicts with VLAN tag detection. */
-        if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
-              sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
+        if (!(hw->flags & SKY2_HW_VLAN_BROKEN))
                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
-        }
-#endif
 
         /* read the mac address */
         memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index 80bdc404f1ea..6861b0e8db9a 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -2236,11 +2236,8 @@ struct sky2_port {
         u16                  rx_pending;
         u16                  rx_data_size;
         u16                  rx_nfrags;
-
-#ifdef SKY2_VLAN_TAG_USED
         u16                  rx_tag;
-        struct vlan_group    *vlgrp;
-#endif
+
         struct {
                 unsigned long last;
                 u32     mac_rp;
@@ -2284,6 +2281,7 @@ struct sky2_hw {
 #define SKY2_HW_AUTO_TX_SUM     0x00000040      /* new IP decode for Tx */
 #define SKY2_HW_ADV_POWER_CTL   0x00000080      /* additional PHY power regs */
 #define SKY2_HW_RSS_BROKEN      0x00000100
+#define SKY2_HW_VLAN_BROKEN     0x00000200
 
         u8                   chip_id;
         u8                   chip_rev;
diff --git a/drivers/net/xen-netfront.c b/drivers/net/xen-netfront.c
index cdbeec9f83ea..546de5749824 100644
--- a/drivers/net/xen-netfront.c
+++ b/drivers/net/xen-netfront.c
@@ -488,7 +488,7 @@ static int xennet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 
         if (unlikely(!netif_carrier_ok(dev) ||
                      (frags > 1 && !xennet_can_sg(dev)) ||
-                     netif_needs_gso(dev, skb))) {
+                     netif_needs_gso(skb, netif_skb_features(skb)))) {
                 spin_unlock_irq(&np->tx_lock);
                 goto drop;
         }
diff --git a/drivers/ps3/Makefile b/drivers/ps3/Makefile
index ccea15c11c19..50cb1e1b4a12 100644
--- a/drivers/ps3/Makefile
+++ b/drivers/ps3/Makefile
@@ -1,6 +1,6 @@
 obj-$(CONFIG_PS3_VUART) += ps3-vuart.o
 obj-$(CONFIG_PS3_PS3AV) += ps3av_mod.o
-ps3av_mod-objs          += ps3av.o ps3av_cmd.o
+ps3av_mod-y             := ps3av.o ps3av_cmd.o
 obj-$(CONFIG_PPC_PS3) += sys-manager-core.o
 obj-$(CONFIG_PS3_SYS_MANAGER) += ps3-sys-manager.o
 obj-$(CONFIG_PS3_STORAGE) += ps3stor_lib.o
diff --git a/drivers/rtc/class.c b/drivers/rtc/class.c
index e6539cbabb35..9583cbcc6b79 100644
--- a/drivers/rtc/class.c
+++ b/drivers/rtc/class.c
@@ -16,6 +16,7 @@
 #include <linux/kdev_t.h>
 #include <linux/idr.h>
 #include <linux/slab.h>
+#include <linux/workqueue.h>
 
 #include "rtc-core.h"
 
@@ -152,6 +153,18 @@ struct rtc_device *rtc_device_register(const char *name, struct device *dev,
         spin_lock_init(&rtc->irq_task_lock);
         init_waitqueue_head(&rtc->irq_queue);
 
+        /* Init timerqueue */
+        timerqueue_init_head(&rtc->timerqueue);
+        INIT_WORK(&rtc->irqwork, rtc_timer_do_work);
+        /* Init aie timer */
+        rtc_timer_init(&rtc->aie_timer, rtc_aie_update_irq, (void *)rtc);
+        /* Init uie timer */
+        rtc_timer_init(&rtc->uie_rtctimer, rtc_uie_update_irq, (void *)rtc);
+        /* Init pie timer */
+        hrtimer_init(&rtc->pie_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+        rtc->pie_timer.function = rtc_pie_update_irq;
+        rtc->pie_enabled = 0;
+
         strlcpy(rtc->name, name, RTC_DEVICE_NAME_SIZE);
         dev_set_name(&rtc->dev, "rtc%d", id);
 
diff --git a/drivers/rtc/interface.c b/drivers/rtc/interface.c
index a0c816238aa9..90384b9f6b2c 100644
--- a/drivers/rtc/interface.c
+++ b/drivers/rtc/interface.c
@@ -14,15 +14,11 @@
 #include <linux/rtc.h>
 #include <linux/sched.h>
 #include <linux/log2.h>
+#include <linux/workqueue.h>
 
-int rtc_read_time(struct rtc_device *rtc, struct rtc_time *tm)
+static int __rtc_read_time(struct rtc_device *rtc, struct rtc_time *tm)
 {
         int err;
-
-        err = mutex_lock_interruptible(&rtc->ops_lock);
-        if (err)
-                return err;
-
         if (!rtc->ops)
                 err = -ENODEV;
         else if (!rtc->ops->read_time)
@@ -31,7 +27,18 @@ int rtc_read_time(struct rtc_device *rtc, struct rtc_time *tm)
                 memset(tm, 0, sizeof(struct rtc_time));
                 err = rtc->ops->read_time(rtc->dev.parent, tm);
         }
+        return err;
+}
+
+int rtc_read_time(struct rtc_device *rtc, struct rtc_time *tm)
+{
+        int err;
 
+        err = mutex_lock_interruptible(&rtc->ops_lock);
+        if (err)
+                return err;
+
+        err = __rtc_read_time(rtc, tm);
         mutex_unlock(&rtc->ops_lock);
         return err;
 }
@@ -106,188 +113,54 @@ int rtc_set_mmss(struct rtc_device *rtc, unsigned long secs)
 }
 EXPORT_SYMBOL_GPL(rtc_set_mmss);
 
-static int rtc_read_alarm_internal(struct rtc_device *rtc, struct rtc_wkalrm *alarm)
+int rtc_read_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm)
 {
         int err;
 
         err = mutex_lock_interruptible(&rtc->ops_lock);
         if (err)
                 return err;
-
-        if (rtc->ops == NULL)
-                err = -ENODEV;
-        else if (!rtc->ops->read_alarm)
-                err = -EINVAL;
-        else {
-                memset(alarm, 0, sizeof(struct rtc_wkalrm));
-                err = rtc->ops->read_alarm(rtc->dev.parent, alarm);
-        }
-
+        alarm->enabled = rtc->aie_timer.enabled;
+        if (alarm->enabled)
+                alarm->time = rtc_ktime_to_tm(rtc->aie_timer.node.expires);
         mutex_unlock(&rtc->ops_lock);
-        return err;
+
+        return 0;
 }
+EXPORT_SYMBOL_GPL(rtc_read_alarm);
 
-int rtc_read_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm)
+int __rtc_set_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm)
 {
+        struct rtc_time tm;
+        long now, scheduled;
         int err;
-        struct rtc_time before, now;
-        int first_time = 1;
-        unsigned long t_now, t_alm;
-        enum { none, day, month, year } missing = none;
-        unsigned days;
-
-        /* The lower level RTC driver may return -1 in some fields,
-         * creating invalid alarm->time values, for reasons like:
-         *
-         *   - The hardware may not be capable of filling them in;
-         *     many alarms match only on time-of-day fields, not
-         *     day/month/year calendar data.
-         *
-         *   - Some hardware uses illegal values as "wildcard" match
-         *     values, which non-Linux firmware (like a BIOS) may try
-         *     to set up as e.g. "alarm 15 minutes after each hour".
-         *     Linux uses only oneshot alarms.
-         *
-         * When we see that here, we deal with it by using values from
-         * a current RTC timestamp for any missing (-1) values.  The
-         * RTC driver prevents "periodic alarm" modes.
-         *
-         * But this can be racey, because some fields of the RTC timestamp
-         * may have wrapped in the interval since we read the RTC alarm,
-         * which would lead to us inserting inconsistent values in place
-         * of the -1 fields.
-         *
-         * Reading the alarm and timestamp in the reverse sequence
-         * would have the same race condition, and not solve the issue.
-         *
-         * So, we must first read the RTC timestamp,
-         * then read the RTC alarm value,
-         * and then read a second RTC timestamp.
-         *
-         * If any fields of the second timestamp have changed
-         * when compared with the first timestamp, then we know
-         * our timestamp may be inconsistent with that used by
-         * the low-level rtc_read_alarm_internal() function.
-         *
-         * So, when the two timestamps disagree, we just loop and do
-         * the process again to get a fully consistent set of values.
-         *
-         * This could all instead be done in the lower level driver,
-         * but since more than one lower level RTC implementation needs it,
-         * then it's probably best best to do it here instead of there..
-         */
 
-        /* Get the "before" timestamp */
-        err = rtc_read_time(rtc, &before);
-        if (err < 0)
+        err = rtc_valid_tm(&alarm->time);
+        if (err)
                 return err;
-        do {
-                if (!first_time)
-                        memcpy(&before, &now, sizeof(struct rtc_time));
-                first_time = 0;
-
-                /* get the RTC alarm values, which may be incomplete */
-                err = rtc_read_alarm_internal(rtc, alarm);
-                if (err)
-                        return err;
-                if (!alarm->enabled)
-                        return 0;
-
-                /* full-function RTCs won't have such missing fields */
-                if (rtc_valid_tm(&alarm->time) == 0)
-                        return 0;
-
-                /* get the "after" timestamp, to detect wrapped fields */
-                err = rtc_read_time(rtc, &now);
-                if (err < 0)
-                        return err;
-
-                /* note that tm_sec is a "don't care" value here: */
-        } while (   before.tm_min   != now.tm_min
-                 || before.tm_hour  != now.tm_hour
-                 || before.tm_mon   != now.tm_mon
-                 || before.tm_year  != now.tm_year);
-
-        /* Fill in the missing alarm fields using the timestamp; we
-         * know there's at least one since alarm->time is invalid.
-         */
-        if (alarm->time.tm_sec == -1)
-                alarm->time.tm_sec = now.tm_sec;
-        if (alarm->time.tm_min == -1)
-                alarm->time.tm_min = now.tm_min;
-        if (alarm->time.tm_hour == -1)
-                alarm->time.tm_hour = now.tm_hour;
-
-        /* For simplicity, only support date rollover for now */
-        if (alarm->time.tm_mday == -1) {
-                alarm->time.tm_mday = now.tm_mday;
-                missing = day;
-        }
-        if (alarm->time.tm_mon == -1) {
-                alarm->time.tm_mon = now.tm_mon;
-                if (missing == none)
-                        missing = month;
-        }
-        if (alarm->time.tm_year == -1) {
-                alarm->time.tm_year = now.tm_year;
-                if (missing == none)
-                        missing = year;
-        }
-
-        /* with luck, no rollover is needed */
-        rtc_tm_to_time(&now, &t_now);
-        rtc_tm_to_time(&alarm->time, &t_alm);
-        if (t_now < t_alm)
-                goto done;
-
-        switch (missing) {
+        rtc_tm_to_time(&alarm->time, &scheduled);
 
-        /* 24 hour rollover ... if it's now 10am Monday, an alarm that
-         * that will trigger at 5am will do so at 5am Tuesday, which
-         * could also be in the next month or year.  This is a common
-         * case, especially for PCs.
-         */
-        case day:
-                dev_dbg(&rtc->dev, "alarm rollover: %s\n", "day");
-                t_alm += 24 * 60 * 60;
-                rtc_time_to_tm(t_alm, &alarm->time);
-                break;
-
-        /* Month rollover ... if it's the 31th, an alarm on the 3rd will
-         * be next month.  An alarm matching on the 30th, 29th, or 28th
-         * may end up in the month after that!  Many newer PCs support
-         * this type of alarm.
+        /* Make sure we're not setting alarms in the past */
+        err = __rtc_read_time(rtc, &tm);
+        rtc_tm_to_time(&tm, &now);
+        if (scheduled <= now)
+                return -ETIME;
+        /*
+         * XXX - We just checked to make sure the alarm time is not
+         * in the past, but there is still a race window where if
+         * the is alarm set for the next second and the second ticks
+         * over right here, before we set the alarm.
          */
-        case month:
-                dev_dbg(&rtc->dev, "alarm rollover: %s\n", "month");
-                do {
-                        if (alarm->time.tm_mon < 11)
-                                alarm->time.tm_mon++;
-                        else {
-                                alarm->time.tm_mon = 0;
-                                alarm->time.tm_year++;
-                        }
-                        days = rtc_month_days(alarm->time.tm_mon,
-                                        alarm->time.tm_year);
-                } while (days < alarm->time.tm_mday);
-                break;
-
-        /* Year rollover ... easy except for leap years! */
-        case year:
-                dev_dbg(&rtc->dev, "alarm rollover: %s\n", "year");
-                do {
-                        alarm->time.tm_year++;
-                } while (rtc_valid_tm(&alarm->time) != 0);
-                break;
-
-        default:
-                dev_warn(&rtc->dev, "alarm rollover not handled\n");
-        }
 
-done:
-        return 0;
+        if (!rtc->ops)
+                err = -ENODEV;
+        else if (!rtc->ops->set_alarm)
+                err = -EINVAL;
+        else
+                err = rtc->ops->set_alarm(rtc->dev.parent, alarm);
+
+        return err;
 }
-EXPORT_SYMBOL_GPL(rtc_read_alarm);
 
 int rtc_set_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm)
 {
@@ -300,16 +173,18 @@ int rtc_set_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm)
         err = mutex_lock_interruptible(&rtc->ops_lock);
         if (err)
                 return err;
-
-        if (!rtc->ops)
-                err = -ENODEV;
-        else if (!rtc->ops->set_alarm)
-                err = -EINVAL;
-        else
-                err = rtc->ops->set_alarm(rtc->dev.parent, alarm);
-
+        if (rtc->aie_timer.enabled) {
+                rtc_timer_remove(rtc, &rtc->aie_timer);
+                rtc->aie_timer.enabled = 0;
+        }
+        rtc->aie_timer.node.expires = rtc_tm_to_ktime(alarm->time);
+        rtc->aie_timer.period = ktime_set(0, 0);
+        if (alarm->enabled) {
+                rtc->aie_timer.enabled = 1;
+                rtc_timer_enqueue(rtc, &rtc->aie_timer);
+        }
         mutex_unlock(&rtc->ops_lock);
-        return err;
+        return 0;
 }
 EXPORT_SYMBOL_GPL(rtc_set_alarm);
 
@@ -319,6 +194,16 @@ int rtc_alarm_irq_enable(struct rtc_device *rtc, unsigned int enabled)
         if (err)
                 return err;
 
+        if (rtc->aie_timer.enabled != enabled) {
+                if (enabled) {
+                        rtc->aie_timer.enabled = 1;
+                        rtc_timer_enqueue(rtc, &rtc->aie_timer);
+                } else {
+                        rtc_timer_remove(rtc, &rtc->aie_timer);
+                        rtc->aie_timer.enabled = 0;
+                }
+        }
+
         if (!rtc->ops)
                 err = -ENODEV;
         else if (!rtc->ops->alarm_irq_enable)
@@ -337,52 +222,53 @@ int rtc_update_irq_enable(struct rtc_device *rtc, unsigned int enabled)
         if (err)
                 return err;
 
-#ifdef CONFIG_RTC_INTF_DEV_UIE_EMUL
-        if (enabled == 0 && rtc->uie_irq_active) {
-                mutex_unlock(&rtc->ops_lock);
-                return rtc_dev_update_irq_enable_emul(rtc, enabled);
+        /* make sure we're changing state */
+        if (rtc->uie_rtctimer.enabled == enabled)
+                goto out;
+
+        if (enabled) {
+                struct rtc_time tm;
+                ktime_t now, onesec;
+
+                __rtc_read_time(rtc, &tm);
+                onesec = ktime_set(1, 0);
+                now = rtc_tm_to_ktime(tm);
+                rtc->uie_rtctimer.node.expires = ktime_add(now, onesec);
+                rtc->uie_rtctimer.period = ktime_set(1, 0);
+                rtc->uie_rtctimer.enabled = 1;
+                rtc_timer_enqueue(rtc, &rtc->uie_rtctimer);
+        } else {
+                rtc_timer_remove(rtc, &rtc->uie_rtctimer);
+                rtc->uie_rtctimer.enabled = 0;
         }
-#endif
-
-        if (!rtc->ops)
-                err = -ENODEV;
-        else if (!rtc->ops->update_irq_enable)
-                err = -EINVAL;
-        else
-                err = rtc->ops->update_irq_enable(rtc->dev.parent, enabled);
 
+out:
         mutex_unlock(&rtc->ops_lock);
-
-#ifdef CONFIG_RTC_INTF_DEV_UIE_EMUL
-        /*
-         * Enable emulation if the driver did not provide
-         * the update_irq_enable function pointer or if returned
-         * -EINVAL to signal that it has been configured without
-         * interrupts or that are not available at the moment.
-         */
-        if (err == -EINVAL)
-                err = rtc_dev_update_irq_enable_emul(rtc, enabled);
-#endif
         return err;
+
 }
 EXPORT_SYMBOL_GPL(rtc_update_irq_enable);
 
+
 /**
- * rtc_update_irq - report RTC periodic, alarm, and/or update irqs
- * @rtc: the rtc device
- * @num: how many irqs are being reported (usually one)
- * @events: mask of RTC_IRQF with one or more of RTC_PF, RTC_AF, RTC_UF
- * Context: any
+ * rtc_handle_legacy_irq - AIE, UIE and PIE event hook
+ * @rtc: pointer to the rtc device
+ *
+ * This function is called when an AIE, UIE or PIE mode interrupt
+ * has occured (or been emulated).
+ *
+ * Triggers the registered irq_task function callback.
  */
-void rtc_update_irq(struct rtc_device *rtc,
-                unsigned long num, unsigned long events)
+static void rtc_handle_legacy_irq(struct rtc_device *rtc, int num, int mode)
 {
         unsigned long flags;
 
+        /* mark one irq of the appropriate mode */
         spin_lock_irqsave(&rtc->irq_lock, flags);
-        rtc->irq_data = (rtc->irq_data + (num << 8)) | events;
+        rtc->irq_data = (rtc->irq_data + (num << 8)) | (RTC_IRQF|mode);
         spin_unlock_irqrestore(&rtc->irq_lock, flags);
 
+        /* call the task func */
         spin_lock_irqsave(&rtc->irq_task_lock, flags);
         if (rtc->irq_task)
                 rtc->irq_task->func(rtc->irq_task->private_data);
@@ -391,6 +277,69 @@ void rtc_update_irq(struct rtc_device *rtc,
         wake_up_interruptible(&rtc->irq_queue);
         kill_fasync(&rtc->async_queue, SIGIO, POLL_IN);
 }
+
+
+/**
+ * rtc_aie_update_irq - AIE mode rtctimer hook
+ * @private: pointer to the rtc_device
+ *
+ * This functions is called when the aie_timer expires.
+ */
+void rtc_aie_update_irq(void *private)
+{
+        struct rtc_device *rtc = (struct rtc_device *)private;
+        rtc_handle_legacy_irq(rtc, 1, RTC_AF);
+}
+
+
+/**
+ * rtc_uie_update_irq - UIE mode rtctimer hook
+ * @private: pointer to the rtc_device
+ *
+ * This functions is called when the uie_timer expires.
+ */
+void rtc_uie_update_irq(void *private)
+{
+        struct rtc_device *rtc = (struct rtc_device *)private;
+        rtc_handle_legacy_irq(rtc, 1,  RTC_UF);
+}
+
+
+/**
+ * rtc_pie_update_irq - PIE mode hrtimer hook
+ * @timer: pointer to the pie mode hrtimer
+ *
+ * This function is used to emulate PIE mode interrupts
+ * using an hrtimer. This function is called when the periodic
+ * hrtimer expires.
+ */
+enum hrtimer_restart rtc_pie_update_irq(struct hrtimer *timer)
+{
+        struct rtc_device *rtc;
+        ktime_t period;
+        int count;
+        rtc = container_of(timer, struct rtc_device, pie_timer);
+
+        period = ktime_set(0, NSEC_PER_SEC/rtc->irq_freq);
+        count = hrtimer_forward_now(timer, period);
+
+        rtc_handle_legacy_irq(rtc, count, RTC_PF);
+
+        return HRTIMER_RESTART;
+}
+
+/**
+ * rtc_update_irq - Triggered when a RTC interrupt occurs.
+ * @rtc: the rtc device
+ * @num: how many irqs are being reported (usually one)
+ * @events: mask of RTC_IRQF with one or more of RTC_PF, RTC_AF, RTC_UF
+ * Context: any
+ */
+void rtc_update_irq(struct rtc_device *rtc,
+                unsigned long num, unsigned long events)
+{
+        schedule_work(&rtc->irqwork);
+}
 EXPORT_SYMBOL_GPL(rtc_update_irq);
 
 static int __rtc_match(struct device *dev, void *data)
@@ -477,18 +426,20 @@ int rtc_irq_set_state(struct rtc_device *rtc, struct rtc_task *task, int enabled
         int err = 0;
         unsigned long flags;
 
-        if (rtc->ops->irq_set_state == NULL)
-                return -ENXIO;
-
         spin_lock_irqsave(&rtc->irq_task_lock, flags);
         if (rtc->irq_task != NULL && task == NULL)
                 err = -EBUSY;
         if (rtc->irq_task != task)
                 err = -EACCES;
-        spin_unlock_irqrestore(&rtc->irq_task_lock, flags);
 
-        if (err == 0)
-                err = rtc->ops->irq_set_state(rtc->dev.parent, enabled);
+        if (enabled) {
+                ktime_t period = ktime_set(0, NSEC_PER_SEC/rtc->irq_freq);
+                hrtimer_start(&rtc->pie_timer, period, HRTIMER_MODE_REL);
+        } else {
+                hrtimer_cancel(&rtc->pie_timer);
+        }
+        rtc->pie_enabled = enabled;
+        spin_unlock_irqrestore(&rtc->irq_task_lock, flags);
 
         return err;
 }
@@ -509,21 +460,194 @@ int rtc_irq_set_freq(struct rtc_device *rtc, struct rtc_task *task, int freq)
         int err = 0;
         unsigned long flags;
 
-        if (rtc->ops->irq_set_freq == NULL)
-                return -ENXIO;
-
         spin_lock_irqsave(&rtc->irq_task_lock, flags);
         if (rtc->irq_task != NULL && task == NULL)
                 err = -EBUSY;
         if (rtc->irq_task != task)
                 err = -EACCES;
-        spin_unlock_irqrestore(&rtc->irq_task_lock, flags);
-
         if (err == 0) {
-                err = rtc->ops->irq_set_freq(rtc->dev.parent, freq);
-                if (err == 0)
-                        rtc->irq_freq = freq;
+                rtc->irq_freq = freq;
+                if (rtc->pie_enabled) {
+                        ktime_t period;
+                        hrtimer_cancel(&rtc->pie_timer);
+                        period = ktime_set(0, NSEC_PER_SEC/rtc->irq_freq);
+                        hrtimer_start(&rtc->pie_timer, period,
+                                        HRTIMER_MODE_REL);
+                }
         }
+        spin_unlock_irqrestore(&rtc->irq_task_lock, flags);
         return err;
 }
 EXPORT_SYMBOL_GPL(rtc_irq_set_freq);
+
+/**
+ * rtc_timer_enqueue - Adds a rtc_timer to the rtc_device timerqueue
+ * @rtc rtc device
+ * @timer timer being added.
+ *
+ * Enqueues a timer onto the rtc devices timerqueue and sets
+ * the next alarm event appropriately.
+ *
+ * Must hold ops_lock for proper serialization of timerqueue
+ */
+void rtc_timer_enqueue(struct rtc_device *rtc, struct rtc_timer *timer)
+{
+        timerqueue_add(&rtc->timerqueue, &timer->node);
+        if (&timer->node == timerqueue_getnext(&rtc->timerqueue)) {
+                struct rtc_wkalrm alarm;
+                int err;
+                alarm.time = rtc_ktime_to_tm(timer->node.expires);
+                alarm.enabled = 1;
+                err = __rtc_set_alarm(rtc, &alarm);
+                if (err == -ETIME)
+                        schedule_work(&rtc->irqwork);
+        }
+}
+
+/**
+ * rtc_timer_remove - Removes a rtc_timer from the rtc_device timerqueue
+ * @rtc rtc device
+ * @timer timer being removed.
+ *
+ * Removes a timer onto the rtc devices timerqueue and sets
+ * the next alarm event appropriately.
+ *
+ * Must hold ops_lock for proper serialization of timerqueue
+ */
+void rtc_timer_remove(struct rtc_device *rtc, struct rtc_timer *timer)
+{
+        struct timerqueue_node *next = timerqueue_getnext(&rtc->timerqueue);
+        timerqueue_del(&rtc->timerqueue, &timer->node);
+
+        if (next == &timer->node) {
+                struct rtc_wkalrm alarm;
+                int err;
+                next = timerqueue_getnext(&rtc->timerqueue);
+                if (!next)
+                        return;
+                alarm.time = rtc_ktime_to_tm(next->expires);
+                alarm.enabled = 1;
+                err = __rtc_set_alarm(rtc, &alarm);
+                if (err == -ETIME)
+                        schedule_work(&rtc->irqwork);
+        }
+}
+
+/**
+ * rtc_timer_do_work - Expires rtc timers
+ * @rtc rtc device
+ * @timer timer being removed.
+ *
+ * Expires rtc timers. Reprograms next alarm event if needed.
+ * Called via worktask.
+ *
+ * Serializes access to timerqueue via ops_lock mutex
+ */
+void rtc_timer_do_work(struct work_struct *work)
+{
+        struct rtc_timer *timer;
+        struct timerqueue_node *next;
+        ktime_t now;
+        struct rtc_time tm;
+
+        struct rtc_device *rtc =
+                container_of(work, struct rtc_device, irqwork);
+
+        mutex_lock(&rtc->ops_lock);
+again:
+        __rtc_read_time(rtc, &tm);
+        now = rtc_tm_to_ktime(tm);
+        while ((next = timerqueue_getnext(&rtc->timerqueue))) {
+                if (next->expires.tv64 > now.tv64)
+                        break;
+
+                /* expire timer */
+                timer = container_of(next, struct rtc_timer, node);
+                timerqueue_del(&rtc->timerqueue, &timer->node);
+                timer->enabled = 0;
+                if (timer->task.func)
+                        timer->task.func(timer->task.private_data);
+
+                /* Re-add/fwd periodic timers */
+                if (ktime_to_ns(timer->period)) {
+                        timer->node.expires = ktime_add(timer->node.expires,
+                                                        timer->period);
+                        timer->enabled = 1;
+                        timerqueue_add(&rtc->timerqueue, &timer->node);
+                }
+        }
+
+        /* Set next alarm */
+        if (next) {
+                struct rtc_wkalrm alarm;
+                int err;
+                alarm.time = rtc_ktime_to_tm(next->expires);
+                alarm.enabled = 1;
+                err = __rtc_set_alarm(rtc, &alarm);
+                if (err == -ETIME)
+                        goto again;
+        }
+
+        mutex_unlock(&rtc->ops_lock);
+}
+
+
+/* rtc_timer_init - Initializes an rtc_timer
+ * @timer: timer to be intiialized
+ * @f: function pointer to be called when timer fires
+ * @data: private data passed to function pointer
+ *
+ * Kernel interface to initializing an rtc_timer.
+ */
+void rtc_timer_init(struct rtc_timer *timer, void (*f)(void* p), void* data)
+{
+        timerqueue_init(&timer->node);
+        timer->enabled = 0;
+        timer->task.func = f;
+        timer->task.private_data = data;
+}
+
+/* rtc_timer_start - Sets an rtc_timer to fire in the future
+ * @ rtc: rtc device to be used
+ * @ timer: timer being set
+ * @ expires: time at which to expire the timer
+ * @ period: period that the timer will recur
+ *
+ * Kernel interface to set an rtc_timer
+ */
+int rtc_timer_start(struct rtc_device *rtc, struct rtc_timer* timer,
+                        ktime_t expires, ktime_t period)
+{
+        int ret = 0;
+        mutex_lock(&rtc->ops_lock);
+        if (timer->enabled)
+                rtc_timer_remove(rtc, timer);
+
+        timer->node.expires = expires;
+        timer->period = period;
+
+        timer->enabled = 1;
+        rtc_timer_enqueue(rtc, timer);
+
+        mutex_unlock(&rtc->ops_lock);
+        return ret;
+}
+
+/* rtc_timer_cancel - Stops an rtc_timer
+ * @ rtc: rtc device to be used
+ * @ timer: timer being set
+ *
+ * Kernel interface to cancel an rtc_timer
+ */
+int rtc_timer_cancel(struct rtc_device *rtc, struct rtc_timer* timer)
+{
+        int ret = 0;
+        mutex_lock(&rtc->ops_lock);
+        if (timer->enabled)
+                rtc_timer_remove(rtc, timer);
+        timer->enabled = 0;
+        mutex_unlock(&rtc->ops_lock);
+        return ret;
+}
+
+
diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c
index 5856167a0c90..7e6ce626b7f1 100644
--- a/drivers/rtc/rtc-cmos.c
+++ b/drivers/rtc/rtc-cmos.c
@@ -687,7 +687,8 @@ cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq)
 #if     defined(CONFIG_ATARI)
         address_space = 64;
 #elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) \
-                        || defined(__sparc__) || defined(__mips__)
+                        || defined(__sparc__) || defined(__mips__) \
+                        || defined(__powerpc__)
         address_space = 128;
 #else
 #warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes.
diff --git a/drivers/rtc/rtc-dev.c b/drivers/rtc/rtc-dev.c
index 0cc0984d155b..212b16edafc0 100644
--- a/drivers/rtc/rtc-dev.c
+++ b/drivers/rtc/rtc-dev.c
@@ -46,105 +46,6 @@ static int rtc_dev_open(struct inode *inode, struct file *file)
         return err;
 }
 
-#ifdef CONFIG_RTC_INTF_DEV_UIE_EMUL
-/*
- * Routine to poll RTC seconds field for change as often as possible,
- * after first RTC_UIE use timer to reduce polling
- */
-static void rtc_uie_task(struct work_struct *work)
-{
-        struct rtc_device *rtc =
-                container_of(work, struct rtc_device, uie_task);
-        struct rtc_time tm;
-        int num = 0;
-        int err;
-
-        err = rtc_read_time(rtc, &tm);
-
-        spin_lock_irq(&rtc->irq_lock);
-        if (rtc->stop_uie_polling || err) {
-                rtc->uie_task_active = 0;
-        } else if (rtc->oldsecs != tm.tm_sec) {
-                num = (tm.tm_sec + 60 - rtc->oldsecs) % 60;
-                rtc->oldsecs = tm.tm_sec;
-                rtc->uie_timer.expires = jiffies + HZ - (HZ/10);
-                rtc->uie_timer_active = 1;
-                rtc->uie_task_active = 0;
-                add_timer(&rtc->uie_timer);
-        } else if (schedule_work(&rtc->uie_task) == 0) {
-                rtc->uie_task_active = 0;
-        }
-        spin_unlock_irq(&rtc->irq_lock);
-        if (num)
-                rtc_update_irq(rtc, num, RTC_UF | RTC_IRQF);
-}
-static void rtc_uie_timer(unsigned long data)
-{
-        struct rtc_device *rtc = (struct rtc_device *)data;
-        unsigned long flags;
-
-        spin_lock_irqsave(&rtc->irq_lock, flags);
-        rtc->uie_timer_active = 0;
-        rtc->uie_task_active = 1;
-        if ((schedule_work(&rtc->uie_task) == 0))
-                rtc->uie_task_active = 0;
-        spin_unlock_irqrestore(&rtc->irq_lock, flags);
-}
-
-static int clear_uie(struct rtc_device *rtc)
-{
-        spin_lock_irq(&rtc->irq_lock);
-        if (rtc->uie_irq_active) {
-                rtc->stop_uie_polling = 1;
-                if (rtc->uie_timer_active) {
-                        spin_unlock_irq(&rtc->irq_lock);
-                        del_timer_sync(&rtc->uie_timer);
-                        spin_lock_irq(&rtc->irq_lock);
-                        rtc->uie_timer_active = 0;
-                }
-                if (rtc->uie_task_active) {
-                        spin_unlock_irq(&rtc->irq_lock);
-                        flush_work_sync(&rtc->uie_task);
-                        spin_lock_irq(&rtc->irq_lock);
-                }
-                rtc->uie_irq_active = 0;
-        }
-        spin_unlock_irq(&rtc->irq_lock);
-        return 0;
-}
-
-static int set_uie(struct rtc_device *rtc)
-{
-        struct rtc_time tm;
-        int err;
-
-        err = rtc_read_time(rtc, &tm);
-        if (err)
-                return err;
-        spin_lock_irq(&rtc->irq_lock);
-        if (!rtc->uie_irq_active) {
-                rtc->uie_irq_active = 1;
-                rtc->stop_uie_polling = 0;
-                rtc->oldsecs = tm.tm_sec;
-                rtc->uie_task_active = 1;
-                if (schedule_work(&rtc->uie_task) == 0)
-                        rtc->uie_task_active = 0;
-        }
-        rtc->irq_data = 0;
-        spin_unlock_irq(&rtc->irq_lock);
-        return 0;
-}
-
-int rtc_dev_update_irq_enable_emul(struct rtc_device *rtc, unsigned int enabled)
-{
-        if (enabled)
-                return set_uie(rtc);
-        else
-                return clear_uie(rtc);
-}
-EXPORT_SYMBOL(rtc_dev_update_irq_enable_emul);
-
-#endif /* CONFIG_RTC_INTF_DEV_UIE_EMUL */
 
 static ssize_t
 rtc_dev_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
@@ -493,11 +394,6 @@ void rtc_dev_prepare(struct rtc_device *rtc)
 
         rtc->dev.devt = MKDEV(MAJOR(rtc_devt), rtc->id);
 
-#ifdef CONFIG_RTC_INTF_DEV_UIE_EMUL
-        INIT_WORK(&rtc->uie_task, rtc_uie_task);
-        setup_timer(&rtc->uie_timer, rtc_uie_timer, (unsigned long)rtc);
-#endif
-
         cdev_init(&rtc->char_dev, &rtc_dev_fops);
         rtc->char_dev.owner = rtc->owner;
 }
diff --git a/drivers/rtc/rtc-lib.c b/drivers/rtc/rtc-lib.c
index 773851f338b8..075f1708deae 100644
--- a/drivers/rtc/rtc-lib.c
+++ b/drivers/rtc/rtc-lib.c
@@ -117,4 +117,32 @@ int rtc_tm_to_time(struct rtc_time *tm, unsigned long *time)
 }
 EXPORT_SYMBOL(rtc_tm_to_time);
 
+/*
+ * Convert rtc_time to ktime
+ */
+ktime_t rtc_tm_to_ktime(struct rtc_time tm)
+{
+        time_t time;
+        rtc_tm_to_time(&tm, &time);
+        return ktime_set(time, 0);
+}
+EXPORT_SYMBOL_GPL(rtc_tm_to_ktime);
+
+/*
+ * Convert ktime to rtc_time
+ */
+struct rtc_time rtc_ktime_to_tm(ktime_t kt)
+{
+        struct timespec ts;
+        struct rtc_time ret;
+
+        ts = ktime_to_timespec(kt);
+        /* Round up any ns */
+        if (ts.tv_nsec)
+                ts.tv_sec++;
+        rtc_time_to_tm(ts.tv_sec, &ret);
+        return ret;
+}
+EXPORT_SYMBOL_GPL(rtc_ktime_to_tm);
+
 MODULE_LICENSE("GPL");
diff --git a/drivers/watchdog/hpwdt.c b/drivers/watchdog/hpwdt.c
index dea7b5bf6e2c..24b966d5061a 100644
--- a/drivers/watchdog/hpwdt.c
+++ b/drivers/watchdog/hpwdt.c
@@ -469,7 +469,7 @@ static int hpwdt_pretimeout(struct notifier_block *nb, unsigned long ulReason,
         unsigned long rom_pl;
         static int die_nmi_called;
 
-        if (ulReason != DIE_NMI && ulReason != DIE_NMI_IPI)
+        if (ulReason != DIE_NMIUNKNOWN)
                 goto out;
 
         if (!hpwdt_nmi_decoding)