diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/ide/pci/cmd64x.c | 114 |
1 files changed, 1 insertions, 113 deletions
diff --git a/drivers/ide/pci/cmd64x.c b/drivers/ide/pci/cmd64x.c index 0b1e9479f019..cd4eb9def151 100644 --- a/drivers/ide/pci/cmd64x.c +++ b/drivers/ide/pci/cmd64x.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * linux/drivers/ide/pci/cmd64x.c Version 1.52 Dec 24, 2007 | 2 | * linux/drivers/ide/pci/cmd64x.c Version 1.53 Dec 24, 2007 |
3 | * | 3 | * |
4 | * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. | 4 | * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. |
5 | * Due to massive hardware bugs, UltraDMA is only supported | 5 | * Due to massive hardware bugs, UltraDMA is only supported |
@@ -22,8 +22,6 @@ | |||
22 | 22 | ||
23 | #include <asm/io.h> | 23 | #include <asm/io.h> |
24 | 24 | ||
25 | #define DISPLAY_CMD64X_TIMINGS | ||
26 | |||
27 | #define CMD_DEBUG 0 | 25 | #define CMD_DEBUG 0 |
28 | 26 | ||
29 | #if CMD_DEBUG | 27 | #if CMD_DEBUG |
@@ -37,11 +35,6 @@ | |||
37 | */ | 35 | */ |
38 | #define CFR 0x50 | 36 | #define CFR 0x50 |
39 | #define CFR_INTR_CH0 0x04 | 37 | #define CFR_INTR_CH0 0x04 |
40 | #define CNTRL 0x51 | ||
41 | #define CNTRL_ENA_1ST 0x04 | ||
42 | #define CNTRL_ENA_2ND 0x08 | ||
43 | #define CNTRL_DIS_RA0 0x40 | ||
44 | #define CNTRL_DIS_RA1 0x80 | ||
45 | 38 | ||
46 | #define CMDTIM 0x52 | 39 | #define CMDTIM 0x52 |
47 | #define ARTTIM0 0x53 | 40 | #define ARTTIM0 0x53 |
@@ -60,108 +53,13 @@ | |||
60 | #define MRDMODE 0x71 | 53 | #define MRDMODE 0x71 |
61 | #define MRDMODE_INTR_CH0 0x04 | 54 | #define MRDMODE_INTR_CH0 0x04 |
62 | #define MRDMODE_INTR_CH1 0x08 | 55 | #define MRDMODE_INTR_CH1 0x08 |
63 | #define MRDMODE_BLK_CH0 0x10 | ||
64 | #define MRDMODE_BLK_CH1 0x20 | ||
65 | #define BMIDESR0 0x72 | ||
66 | #define UDIDETCR0 0x73 | 56 | #define UDIDETCR0 0x73 |
67 | #define DTPR0 0x74 | 57 | #define DTPR0 0x74 |
68 | #define BMIDECR1 0x78 | 58 | #define BMIDECR1 0x78 |
69 | #define BMIDECSR 0x79 | 59 | #define BMIDECSR 0x79 |
70 | #define BMIDESR1 0x7A | ||
71 | #define UDIDETCR1 0x7B | 60 | #define UDIDETCR1 0x7B |
72 | #define DTPR1 0x7C | 61 | #define DTPR1 0x7C |
73 | 62 | ||
74 | #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) | ||
75 | #include <linux/stat.h> | ||
76 | #include <linux/proc_fs.h> | ||
77 | |||
78 | static u8 cmd64x_proc = 0; | ||
79 | |||
80 | #define CMD_MAX_DEVS 5 | ||
81 | |||
82 | static struct pci_dev *cmd_devs[CMD_MAX_DEVS]; | ||
83 | static int n_cmd_devs; | ||
84 | |||
85 | static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index) | ||
86 | { | ||
87 | char *p = buf; | ||
88 | u8 reg72 = 0, reg73 = 0; /* primary */ | ||
89 | u8 reg7a = 0, reg7b = 0; /* secondary */ | ||
90 | u8 reg50 = 1, reg51 = 1, reg57 = 0, reg71 = 0; /* extra */ | ||
91 | |||
92 | p += sprintf(p, "\nController: %d\n", index); | ||
93 | p += sprintf(p, "PCI-%x Chipset.\n", dev->device); | ||
94 | |||
95 | (void) pci_read_config_byte(dev, CFR, ®50); | ||
96 | (void) pci_read_config_byte(dev, CNTRL, ®51); | ||
97 | (void) pci_read_config_byte(dev, ARTTIM23, ®57); | ||
98 | (void) pci_read_config_byte(dev, MRDMODE, ®71); | ||
99 | (void) pci_read_config_byte(dev, BMIDESR0, ®72); | ||
100 | (void) pci_read_config_byte(dev, UDIDETCR0, ®73); | ||
101 | (void) pci_read_config_byte(dev, BMIDESR1, ®7a); | ||
102 | (void) pci_read_config_byte(dev, UDIDETCR1, ®7b); | ||
103 | |||
104 | /* PCI0643/6 originally didn't have the primary channel enable bit */ | ||
105 | if ((dev->device == PCI_DEVICE_ID_CMD_643) || | ||
106 | (dev->device == PCI_DEVICE_ID_CMD_646 && dev->revision < 3)) | ||
107 | reg51 |= CNTRL_ENA_1ST; | ||
108 | |||
109 | p += sprintf(p, "---------------- Primary Channel " | ||
110 | "---------------- Secondary Channel ------------\n"); | ||
111 | p += sprintf(p, " %s %s\n", | ||
112 | (reg51 & CNTRL_ENA_1ST) ? "enabled " : "disabled", | ||
113 | (reg51 & CNTRL_ENA_2ND) ? "enabled " : "disabled"); | ||
114 | p += sprintf(p, "---------------- drive0 --------- drive1 " | ||
115 | "-------- drive0 --------- drive1 ------\n"); | ||
116 | p += sprintf(p, "DMA enabled: %s %s" | ||
117 | " %s %s\n", | ||
118 | (reg72 & 0x20) ? "yes" : "no ", (reg72 & 0x40) ? "yes" : "no ", | ||
119 | (reg7a & 0x20) ? "yes" : "no ", (reg7a & 0x40) ? "yes" : "no "); | ||
120 | p += sprintf(p, "UltraDMA mode: %s (%c) %s (%c)", | ||
121 | ( reg73 & 0x01) ? " on" : "off", | ||
122 | ((reg73 & 0x30) == 0x30) ? ((reg73 & 0x04) ? '3' : '0') : | ||
123 | ((reg73 & 0x30) == 0x20) ? ((reg73 & 0x04) ? '3' : '1') : | ||
124 | ((reg73 & 0x30) == 0x10) ? ((reg73 & 0x04) ? '4' : '2') : | ||
125 | ((reg73 & 0x30) == 0x00) ? ((reg73 & 0x04) ? '5' : '2') : '?', | ||
126 | ( reg73 & 0x02) ? " on" : "off", | ||
127 | ((reg73 & 0xC0) == 0xC0) ? ((reg73 & 0x08) ? '3' : '0') : | ||
128 | ((reg73 & 0xC0) == 0x80) ? ((reg73 & 0x08) ? '3' : '1') : | ||
129 | ((reg73 & 0xC0) == 0x40) ? ((reg73 & 0x08) ? '4' : '2') : | ||
130 | ((reg73 & 0xC0) == 0x00) ? ((reg73 & 0x08) ? '5' : '2') : '?'); | ||
131 | p += sprintf(p, " %s (%c) %s (%c)\n", | ||
132 | ( reg7b & 0x01) ? " on" : "off", | ||
133 | ((reg7b & 0x30) == 0x30) ? ((reg7b & 0x04) ? '3' : '0') : | ||
134 | ((reg7b & 0x30) == 0x20) ? ((reg7b & 0x04) ? '3' : '1') : | ||
135 | ((reg7b & 0x30) == 0x10) ? ((reg7b & 0x04) ? '4' : '2') : | ||
136 | ((reg7b & 0x30) == 0x00) ? ((reg7b & 0x04) ? '5' : '2') : '?', | ||
137 | ( reg7b & 0x02) ? " on" : "off", | ||
138 | ((reg7b & 0xC0) == 0xC0) ? ((reg7b & 0x08) ? '3' : '0') : | ||
139 | ((reg7b & 0xC0) == 0x80) ? ((reg7b & 0x08) ? '3' : '1') : | ||
140 | ((reg7b & 0xC0) == 0x40) ? ((reg7b & 0x08) ? '4' : '2') : | ||
141 | ((reg7b & 0xC0) == 0x00) ? ((reg7b & 0x08) ? '5' : '2') : '?'); | ||
142 | p += sprintf(p, "Interrupt: %s, %s %s, %s\n", | ||
143 | (reg71 & MRDMODE_BLK_CH0 ) ? "blocked" : "enabled", | ||
144 | (reg50 & CFR_INTR_CH0 ) ? "pending" : "clear ", | ||
145 | (reg71 & MRDMODE_BLK_CH1 ) ? "blocked" : "enabled", | ||
146 | (reg57 & ARTTIM23_INTR_CH1) ? "pending" : "clear "); | ||
147 | |||
148 | return (char *)p; | ||
149 | } | ||
150 | |||
151 | static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count) | ||
152 | { | ||
153 | char *p = buffer; | ||
154 | int i; | ||
155 | |||
156 | for (i = 0; i < n_cmd_devs; i++) { | ||
157 | struct pci_dev *dev = cmd_devs[i]; | ||
158 | p = print_cmd64x_get_info(p, dev, i); | ||
159 | } | ||
160 | return p-buffer; /* => must be less than 4k! */ | ||
161 | } | ||
162 | |||
163 | #endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */ | ||
164 | |||
165 | static u8 quantize_timing(int timing, int quant) | 63 | static u8 quantize_timing(int timing, int quant) |
166 | { | 64 | { |
167 | return (timing + quant - 1) / quant; | 65 | return (timing + quant - 1) / quant; |
@@ -472,16 +370,6 @@ static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const cha | |||
472 | mrdmode &= ~0x30; | 370 | mrdmode &= ~0x30; |
473 | (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02)); | 371 | (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02)); |
474 | 372 | ||
475 | #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) | ||
476 | |||
477 | cmd_devs[n_cmd_devs++] = dev; | ||
478 | |||
479 | if (!cmd64x_proc) { | ||
480 | cmd64x_proc = 1; | ||
481 | ide_pci_create_host_proc("cmd64x", cmd64x_get_info); | ||
482 | } | ||
483 | #endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_IDE_PROC_FS */ | ||
484 | |||
485 | return 0; | 373 | return 0; |
486 | } | 374 | } |
487 | 375 | ||