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-rw-r--r--drivers/mmc/host/Kconfig26
-rw-r--r--drivers/mmc/host/Makefile1
-rw-r--r--drivers/mmc/host/sdhci-of-core.c140
-rw-r--r--drivers/mmc/host/sdhci-of-esdhc.c143
-rw-r--r--drivers/mmc/host/sdhci-of.h41
5 files changed, 224 insertions, 127 deletions
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 9d405b181781..d9234648199a 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -44,6 +44,19 @@ config MMC_SDHCI_IO_ACCESSORS
44 This is silent Kconfig symbol that is selected by the drivers that 44 This is silent Kconfig symbol that is selected by the drivers that
45 need to overwrite SDHCI IO memory accessors. 45 need to overwrite SDHCI IO memory accessors.
46 46
47config MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
48 bool
49 select MMC_SDHCI_IO_ACCESSORS
50 help
51 This option is selected by drivers running on big endian hosts
52 and performing I/O to a SDHCI controller through a bus that
53 implements a hardware byte swapper using a 32-bit datum.
54 This endian mapping mode is called "data invariance" and
55 has the effect of scrambling the addresses and formats of data
56 accessed in sizes other than the datum size.
57
58 This is the case for the Freescale eSDHC.
59
47config MMC_SDHCI_PCI 60config MMC_SDHCI_PCI
48 tristate "SDHCI support on PCI bus" 61 tristate "SDHCI support on PCI bus"
49 depends on MMC_SDHCI && PCI 62 depends on MMC_SDHCI && PCI
@@ -75,11 +88,18 @@ config MMC_RICOH_MMC
75config MMC_SDHCI_OF 88config MMC_SDHCI_OF
76 tristate "SDHCI support on OpenFirmware platforms" 89 tristate "SDHCI support on OpenFirmware platforms"
77 depends on MMC_SDHCI && PPC_OF 90 depends on MMC_SDHCI && PPC_OF
78 select MMC_SDHCI_IO_ACCESSORS
79 help 91 help
80 This selects the OF support for Secure Digital Host Controller 92 This selects the OF support for Secure Digital Host Controller
81 Interfaces. So far, only the Freescale eSDHC controller is known 93 Interfaces.
82 to exist on OF platforms. 94
95 If unsure, say N.
96
97config MMC_SDHCI_OF_ESDHC
98 bool "SDHCI OF support for the Freescale eSDHC controller"
99 depends on MMC_SDHCI_OF
100 select MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
101 help
102 This selects the Freescale eSDHC controller support.
83 103
84 If unsure, say N. 104 If unsure, say N.
85 105
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 1efaaa4f45ad..cbda9b2b912b 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_SDH_BFIN) += bfin_sdh.o
38 38
39obj-$(CONFIG_MMC_SDHCI_OF) += sdhci-of.o 39obj-$(CONFIG_MMC_SDHCI_OF) += sdhci-of.o
40sdhci-of-y := sdhci-of-core.o 40sdhci-of-y := sdhci-of-core.o
41sdhci-of-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
41 42
42ifeq ($(CONFIG_CB710_DEBUG),y) 43ifeq ($(CONFIG_CB710_DEBUG),y)
43 CFLAGS-cb710-mmc += -DDEBUG 44 CFLAGS-cb710-mmc += -DDEBUG
diff --git a/drivers/mmc/host/sdhci-of-core.c b/drivers/mmc/host/sdhci-of-core.c
index 01ab916c2802..add2008d890d 100644
--- a/drivers/mmc/host/sdhci-of-core.c
+++ b/drivers/mmc/host/sdhci-of-core.c
@@ -22,62 +22,37 @@
22#include <linux/of_platform.h> 22#include <linux/of_platform.h>
23#include <linux/mmc/host.h> 23#include <linux/mmc/host.h>
24#include <asm/machdep.h> 24#include <asm/machdep.h>
25#include "sdhci-of.h"
25#include "sdhci.h" 26#include "sdhci.h"
26 27
27struct sdhci_of_data { 28#ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
28 unsigned int quirks;
29 struct sdhci_ops ops;
30};
31
32struct sdhci_of_host {
33 unsigned int clock;
34 u16 xfer_mode_shadow;
35};
36 29
37/* 30/*
38 * Ops and quirks for the Freescale eSDHC controller. 31 * These accessors are designed for big endian hosts doing I/O to
32 * little endian controllers incorporating a 32-bit hardware byte swapper.
39 */ 33 */
40 34
41#define ESDHC_DMA_SYSCTL 0x40c 35u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg)
42#define ESDHC_DMA_SNOOP 0x00000040
43
44#define ESDHC_SYSTEM_CONTROL 0x2c
45#define ESDHC_CLOCK_MASK 0x0000fff0
46#define ESDHC_PREDIV_SHIFT 8
47#define ESDHC_DIVIDER_SHIFT 4
48#define ESDHC_CLOCK_PEREN 0x00000004
49#define ESDHC_CLOCK_HCKEN 0x00000002
50#define ESDHC_CLOCK_IPGEN 0x00000001
51
52#define ESDHC_HOST_CONTROL_RES 0x05
53
54static u32 esdhc_readl(struct sdhci_host *host, int reg)
55{ 36{
56 return in_be32(host->ioaddr + reg); 37 return in_be32(host->ioaddr + reg);
57} 38}
58 39
59static u16 esdhc_readw(struct sdhci_host *host, int reg) 40u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg)
60{ 41{
61 u16 ret; 42 return in_be16(host->ioaddr + (reg ^ 0x2));
62
63 if (unlikely(reg == SDHCI_HOST_VERSION))
64 ret = in_be16(host->ioaddr + reg);
65 else
66 ret = in_be16(host->ioaddr + (reg ^ 0x2));
67 return ret;
68} 43}
69 44
70static u8 esdhc_readb(struct sdhci_host *host, int reg) 45u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg)
71{ 46{
72 return in_8(host->ioaddr + (reg ^ 0x3)); 47 return in_8(host->ioaddr + (reg ^ 0x3));
73} 48}
74 49
75static void esdhc_writel(struct sdhci_host *host, u32 val, int reg) 50void sdhci_be32bs_writel(struct sdhci_host *host, u32 val, int reg)
76{ 51{
77 out_be32(host->ioaddr + reg, val); 52 out_be32(host->ioaddr + reg, val);
78} 53}
79 54
80static void esdhc_writew(struct sdhci_host *host, u16 val, int reg) 55void sdhci_be32bs_writew(struct sdhci_host *host, u16 val, int reg)
81{ 56{
82 struct sdhci_of_host *of_host = sdhci_priv(host); 57 struct sdhci_of_host *of_host = sdhci_priv(host);
83 int base = reg & ~0x3; 58 int base = reg & ~0x3;
@@ -92,106 +67,21 @@ static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
92 of_host->xfer_mode_shadow = val; 67 of_host->xfer_mode_shadow = val;
93 return; 68 return;
94 case SDHCI_COMMAND: 69 case SDHCI_COMMAND:
95 esdhc_writel(host, val << 16 | of_host->xfer_mode_shadow, 70 sdhci_be32bs_writel(host, val << 16 | of_host->xfer_mode_shadow,
96 SDHCI_TRANSFER_MODE); 71 SDHCI_TRANSFER_MODE);
97 return; 72 return;
98 case SDHCI_BLOCK_SIZE:
99 /*
100 * Two last DMA bits are reserved, and first one is used for
101 * non-standard blksz of 4096 bytes that we don't support
102 * yet. So clear the DMA boundary bits.
103 */
104 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
105 /* fall through */
106 } 73 }
107 clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift); 74 clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift);
108} 75}
109 76
110static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg) 77void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg)
111{ 78{
112 int base = reg & ~0x3; 79 int base = reg & ~0x3;
113 int shift = (reg & 0x3) * 8; 80 int shift = (reg & 0x3) * 8;
114 81
115 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
116 if (reg == SDHCI_HOST_CONTROL)
117 val &= ~ESDHC_HOST_CONTROL_RES;
118
119 clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift); 82 clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift);
120} 83}
121 84#endif /* CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER */
122static void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
123{
124 int pre_div = 2;
125 int div = 1;
126
127 clrbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
128 ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);
129
130 if (clock == 0)
131 goto out;
132
133 while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
134 pre_div *= 2;
135
136 while (host->max_clk / pre_div / div > clock && div < 16)
137 div++;
138
139 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
140 clock, host->max_clk / pre_div / div);
141
142 pre_div >>= 1;
143 div--;
144
145 setbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
146 ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN |
147 div << ESDHC_DIVIDER_SHIFT | pre_div << ESDHC_PREDIV_SHIFT);
148 mdelay(100);
149out:
150 host->clock = clock;
151}
152
153static int esdhc_enable_dma(struct sdhci_host *host)
154{
155 setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP);
156 return 0;
157}
158
159static unsigned int esdhc_get_max_clock(struct sdhci_host *host)
160{
161 struct sdhci_of_host *of_host = sdhci_priv(host);
162
163 return of_host->clock;
164}
165
166static unsigned int esdhc_get_min_clock(struct sdhci_host *host)
167{
168 struct sdhci_of_host *of_host = sdhci_priv(host);
169
170 return of_host->clock / 256 / 16;
171}
172
173static struct sdhci_of_data sdhci_esdhc = {
174 .quirks = SDHCI_QUIRK_FORCE_BLK_SZ_2048 |
175 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
176 SDHCI_QUIRK_NO_BUSY_IRQ |
177 SDHCI_QUIRK_NONSTANDARD_CLOCK |
178 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
179 SDHCI_QUIRK_PIO_NEEDS_DELAY |
180 SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET |
181 SDHCI_QUIRK_NO_CARD_NO_RESET,
182 .ops = {
183 .readl = esdhc_readl,
184 .readw = esdhc_readw,
185 .readb = esdhc_readb,
186 .writel = esdhc_writel,
187 .writew = esdhc_writew,
188 .writeb = esdhc_writeb,
189 .set_clock = esdhc_set_clock,
190 .enable_dma = esdhc_enable_dma,
191 .get_max_clock = esdhc_get_max_clock,
192 .get_min_clock = esdhc_get_min_clock,
193 },
194};
195 85
196#ifdef CONFIG_PM 86#ifdef CONFIG_PM
197 87
@@ -301,9 +191,11 @@ static int __devexit sdhci_of_remove(struct of_device *ofdev)
301} 191}
302 192
303static const struct of_device_id sdhci_of_match[] = { 193static const struct of_device_id sdhci_of_match[] = {
194#ifdef CONFIG_MMC_SDHCI_OF_ESDHC
304 { .compatible = "fsl,mpc8379-esdhc", .data = &sdhci_esdhc, }, 195 { .compatible = "fsl,mpc8379-esdhc", .data = &sdhci_esdhc, },
305 { .compatible = "fsl,mpc8536-esdhc", .data = &sdhci_esdhc, }, 196 { .compatible = "fsl,mpc8536-esdhc", .data = &sdhci_esdhc, },
306 { .compatible = "fsl,esdhc", .data = &sdhci_esdhc, }, 197 { .compatible = "fsl,esdhc", .data = &sdhci_esdhc, },
198#endif
307 { .compatible = "generic-sdhci", }, 199 { .compatible = "generic-sdhci", },
308 {}, 200 {},
309}; 201};
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
new file mode 100644
index 000000000000..d5b11a17e648
--- /dev/null
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -0,0 +1,143 @@
1/*
2 * Freescale eSDHC controller driver.
3 *
4 * Copyright (c) 2007 Freescale Semiconductor, Inc.
5 * Copyright (c) 2009 MontaVista Software, Inc.
6 *
7 * Authors: Xiaobo Xie <X.Xie@freescale.com>
8 * Anton Vorontsov <avorontsov@ru.mvista.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
14 */
15
16#include <linux/io.h>
17#include <linux/delay.h>
18#include <linux/mmc/host.h>
19#include "sdhci-of.h"
20#include "sdhci.h"
21
22/*
23 * Ops and quirks for the Freescale eSDHC controller.
24 */
25
26#define ESDHC_DMA_SYSCTL 0x40c
27#define ESDHC_DMA_SNOOP 0x00000040
28
29#define ESDHC_SYSTEM_CONTROL 0x2c
30#define ESDHC_CLOCK_MASK 0x0000fff0
31#define ESDHC_PREDIV_SHIFT 8
32#define ESDHC_DIVIDER_SHIFT 4
33#define ESDHC_CLOCK_PEREN 0x00000004
34#define ESDHC_CLOCK_HCKEN 0x00000002
35#define ESDHC_CLOCK_IPGEN 0x00000001
36
37#define ESDHC_HOST_CONTROL_RES 0x05
38
39static u16 esdhc_readw(struct sdhci_host *host, int reg)
40{
41 u16 ret;
42
43 if (unlikely(reg == SDHCI_HOST_VERSION))
44 ret = in_be16(host->ioaddr + reg);
45 else
46 ret = sdhci_be32bs_readw(host, reg);
47 return ret;
48}
49
50static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
51{
52 if (reg == SDHCI_BLOCK_SIZE) {
53 /*
54 * Two last DMA bits are reserved, and first one is used for
55 * non-standard blksz of 4096 bytes that we don't support
56 * yet. So clear the DMA boundary bits.
57 */
58 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
59 }
60 sdhci_be32bs_writew(host, val, reg);
61}
62
63static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
64{
65 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
66 if (reg == SDHCI_HOST_CONTROL)
67 val &= ~ESDHC_HOST_CONTROL_RES;
68 sdhci_be32bs_writeb(host, val, reg);
69}
70
71static void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
72{
73 int pre_div = 2;
74 int div = 1;
75
76 clrbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
77 ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);
78
79 if (clock == 0)
80 goto out;
81
82 while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
83 pre_div *= 2;
84
85 while (host->max_clk / pre_div / div > clock && div < 16)
86 div++;
87
88 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
89 clock, host->max_clk / pre_div / div);
90
91 pre_div >>= 1;
92 div--;
93
94 setbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
95 ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN |
96 div << ESDHC_DIVIDER_SHIFT | pre_div << ESDHC_PREDIV_SHIFT);
97 mdelay(100);
98out:
99 host->clock = clock;
100}
101
102static int esdhc_enable_dma(struct sdhci_host *host)
103{
104 setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP);
105 return 0;
106}
107
108static unsigned int esdhc_get_max_clock(struct sdhci_host *host)
109{
110 struct sdhci_of_host *of_host = sdhci_priv(host);
111
112 return of_host->clock;
113}
114
115static unsigned int esdhc_get_min_clock(struct sdhci_host *host)
116{
117 struct sdhci_of_host *of_host = sdhci_priv(host);
118
119 return of_host->clock / 256 / 16;
120}
121
122struct sdhci_of_data sdhci_esdhc = {
123 .quirks = SDHCI_QUIRK_FORCE_BLK_SZ_2048 |
124 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
125 SDHCI_QUIRK_NO_BUSY_IRQ |
126 SDHCI_QUIRK_NONSTANDARD_CLOCK |
127 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
128 SDHCI_QUIRK_PIO_NEEDS_DELAY |
129 SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET |
130 SDHCI_QUIRK_NO_CARD_NO_RESET,
131 .ops = {
132 .readl = sdhci_be32bs_readl,
133 .readw = esdhc_readw,
134 .readb = sdhci_be32bs_readb,
135 .writel = sdhci_be32bs_writel,
136 .writew = esdhc_writew,
137 .writeb = esdhc_writeb,
138 .set_clock = esdhc_set_clock,
139 .enable_dma = esdhc_enable_dma,
140 .get_max_clock = esdhc_get_max_clock,
141 .get_min_clock = esdhc_get_min_clock,
142 },
143};
diff --git a/drivers/mmc/host/sdhci-of.h b/drivers/mmc/host/sdhci-of.h
new file mode 100644
index 000000000000..17e873d3baaf
--- /dev/null
+++ b/drivers/mmc/host/sdhci-of.h
@@ -0,0 +1,41 @@
1/*
2 * OpenFirmware bindings for Secure Digital Host Controller Interface.
3 *
4 * Copyright (c) 2007 Freescale Semiconductor, Inc.
5 * Copyright (c) 2009 MontaVista Software, Inc.
6 *
7 * Authors: Xiaobo Xie <X.Xie@freescale.com>
8 * Anton Vorontsov <avorontsov@ru.mvista.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
14 */
15
16#ifndef __SDHCI_OF_H
17#define __SDHCI_OF_H
18
19#include <linux/types.h>
20#include "sdhci.h"
21
22struct sdhci_of_data {
23 unsigned int quirks;
24 struct sdhci_ops ops;
25};
26
27struct sdhci_of_host {
28 unsigned int clock;
29 u16 xfer_mode_shadow;
30};
31
32extern u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg);
33extern u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg);
34extern u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg);
35extern void sdhci_be32bs_writel(struct sdhci_host *host, u32 val, int reg);
36extern void sdhci_be32bs_writew(struct sdhci_host *host, u16 val, int reg);
37extern void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg);
38
39extern struct sdhci_of_data sdhci_esdhc;
40
41#endif /* __SDHCI_OF_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 22:54:39 -0500