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-rw-r--r--drivers/gpu/drm/radeon/atom.c102
-rw-r--r--drivers/gpu/drm/radeon/atom.h1
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c257
-rw-r--r--drivers/gpu/drm/radeon/r100.c1
-rw-r--r--drivers/gpu/drm/radeon/r200.c7
-rw-r--r--drivers/gpu/drm/radeon/r600.c61
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c83
-rw-r--r--drivers/gpu/drm/radeon/r600d.h25
-rw-r--r--drivers/gpu/drm/radeon/radeon.h9
-rw-r--r--drivers/gpu/drm/radeon/radeon_clocks.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c41
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c77
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h28
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r2002
-rw-r--r--drivers/gpu/drm/radeon/rv770.c14
16 files changed, 472 insertions, 241 deletions
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index 388140a7e651..e3b44562d265 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -246,6 +246,9 @@ static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
246 case ATOM_WS_ATTRIBUTES: 246 case ATOM_WS_ATTRIBUTES:
247 val = gctx->io_attr; 247 val = gctx->io_attr;
248 break; 248 break;
249 case ATOM_WS_REGPTR:
250 val = gctx->reg_block;
251 break;
249 default: 252 default:
250 val = ctx->ws[idx]; 253 val = ctx->ws[idx];
251 } 254 }
@@ -385,6 +388,32 @@ static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)
385 return atom_get_src_int(ctx, attr, ptr, NULL, 1); 388 return atom_get_src_int(ctx, attr, ptr, NULL, 1);
386} 389}
387 390
391static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr)
392{
393 uint32_t val = 0xCDCDCDCD;
394
395 switch (align) {
396 case ATOM_SRC_DWORD:
397 val = U32(*ptr);
398 (*ptr) += 4;
399 break;
400 case ATOM_SRC_WORD0:
401 case ATOM_SRC_WORD8:
402 case ATOM_SRC_WORD16:
403 val = U16(*ptr);
404 (*ptr) += 2;
405 break;
406 case ATOM_SRC_BYTE0:
407 case ATOM_SRC_BYTE8:
408 case ATOM_SRC_BYTE16:
409 case ATOM_SRC_BYTE24:
410 val = U8(*ptr);
411 (*ptr)++;
412 break;
413 }
414 return val;
415}
416
388static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr, 417static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,
389 int *ptr, uint32_t *saved, int print) 418 int *ptr, uint32_t *saved, int print)
390{ 419{
@@ -482,6 +511,9 @@ static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,
482 case ATOM_WS_ATTRIBUTES: 511 case ATOM_WS_ATTRIBUTES:
483 gctx->io_attr = val; 512 gctx->io_attr = val;
484 break; 513 break;
514 case ATOM_WS_REGPTR:
515 gctx->reg_block = val;
516 break;
485 default: 517 default:
486 ctx->ws[idx] = val; 518 ctx->ws[idx] = val;
487 } 519 }
@@ -677,7 +709,7 @@ static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg)
677 SDEBUG(" dst: "); 709 SDEBUG(" dst: ");
678 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 710 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
679 SDEBUG(" src1: "); 711 SDEBUG(" src1: ");
680 src1 = atom_get_src(ctx, attr, ptr); 712 src1 = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr);
681 SDEBUG(" src2: "); 713 SDEBUG(" src2: ");
682 src2 = atom_get_src(ctx, attr, ptr); 714 src2 = atom_get_src(ctx, attr, ptr);
683 dst &= src1; 715 dst &= src1;
@@ -809,6 +841,38 @@ static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg)
809 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block); 841 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block);
810} 842}
811 843
844static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg)
845{
846 uint8_t attr = U8((*ptr)++), shift;
847 uint32_t saved, dst;
848 int dptr = *ptr;
849 attr &= 0x38;
850 attr |= atom_def_dst[attr >> 3] << 6;
851 SDEBUG(" dst: ");
852 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
853 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
854 SDEBUG(" shift: %d\n", shift);
855 dst <<= shift;
856 SDEBUG(" dst: ");
857 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
858}
859
860static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg)
861{
862 uint8_t attr = U8((*ptr)++), shift;
863 uint32_t saved, dst;
864 int dptr = *ptr;
865 attr &= 0x38;
866 attr |= atom_def_dst[attr >> 3] << 6;
867 SDEBUG(" dst: ");
868 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
869 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
870 SDEBUG(" shift: %d\n", shift);
871 dst >>= shift;
872 SDEBUG(" dst: ");
873 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
874}
875
812static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg) 876static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
813{ 877{
814 uint8_t attr = U8((*ptr)++), shift; 878 uint8_t attr = U8((*ptr)++), shift;
@@ -818,7 +882,7 @@ static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
818 attr |= atom_def_dst[attr >> 3] << 6; 882 attr |= atom_def_dst[attr >> 3] << 6;
819 SDEBUG(" dst: "); 883 SDEBUG(" dst: ");
820 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 884 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
821 shift = U8((*ptr)++); 885 shift = atom_get_src(ctx, attr, ptr);
822 SDEBUG(" shift: %d\n", shift); 886 SDEBUG(" shift: %d\n", shift);
823 dst <<= shift; 887 dst <<= shift;
824 SDEBUG(" dst: "); 888 SDEBUG(" dst: ");
@@ -834,7 +898,7 @@ static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg)
834 attr |= atom_def_dst[attr >> 3] << 6; 898 attr |= atom_def_dst[attr >> 3] << 6;
835 SDEBUG(" dst: "); 899 SDEBUG(" dst: ");
836 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 900 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
837 shift = U8((*ptr)++); 901 shift = atom_get_src(ctx, attr, ptr);
838 SDEBUG(" shift: %d\n", shift); 902 SDEBUG(" shift: %d\n", shift);
839 dst >>= shift; 903 dst >>= shift;
840 SDEBUG(" dst: "); 904 SDEBUG(" dst: ");
@@ -937,18 +1001,18 @@ static struct {
937 atom_op_or, ATOM_ARG_FB}, { 1001 atom_op_or, ATOM_ARG_FB}, {
938 atom_op_or, ATOM_ARG_PLL}, { 1002 atom_op_or, ATOM_ARG_PLL}, {
939 atom_op_or, ATOM_ARG_MC}, { 1003 atom_op_or, ATOM_ARG_MC}, {
940 atom_op_shl, ATOM_ARG_REG}, { 1004 atom_op_shift_left, ATOM_ARG_REG}, {
941 atom_op_shl, ATOM_ARG_PS}, { 1005 atom_op_shift_left, ATOM_ARG_PS}, {
942 atom_op_shl, ATOM_ARG_WS}, { 1006 atom_op_shift_left, ATOM_ARG_WS}, {
943 atom_op_shl, ATOM_ARG_FB}, { 1007 atom_op_shift_left, ATOM_ARG_FB}, {
944 atom_op_shl, ATOM_ARG_PLL}, { 1008 atom_op_shift_left, ATOM_ARG_PLL}, {
945 atom_op_shl, ATOM_ARG_MC}, { 1009 atom_op_shift_left, ATOM_ARG_MC}, {
946 atom_op_shr, ATOM_ARG_REG}, { 1010 atom_op_shift_right, ATOM_ARG_REG}, {
947 atom_op_shr, ATOM_ARG_PS}, { 1011 atom_op_shift_right, ATOM_ARG_PS}, {
948 atom_op_shr, ATOM_ARG_WS}, { 1012 atom_op_shift_right, ATOM_ARG_WS}, {
949 atom_op_shr, ATOM_ARG_FB}, { 1013 atom_op_shift_right, ATOM_ARG_FB}, {
950 atom_op_shr, ATOM_ARG_PLL}, { 1014 atom_op_shift_right, ATOM_ARG_PLL}, {
951 atom_op_shr, ATOM_ARG_MC}, { 1015 atom_op_shift_right, ATOM_ARG_MC}, {
952 atom_op_mul, ATOM_ARG_REG}, { 1016 atom_op_mul, ATOM_ARG_REG}, {
953 atom_op_mul, ATOM_ARG_PS}, { 1017 atom_op_mul, ATOM_ARG_PS}, {
954 atom_op_mul, ATOM_ARG_WS}, { 1018 atom_op_mul, ATOM_ARG_WS}, {
@@ -1058,8 +1122,6 @@ static void atom_execute_table_locked(struct atom_context *ctx, int index, uint3
1058 1122
1059 SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps); 1123 SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps);
1060 1124
1061 /* reset reg block */
1062 ctx->reg_block = 0;
1063 ectx.ctx = ctx; 1125 ectx.ctx = ctx;
1064 ectx.ps_shift = ps / 4; 1126 ectx.ps_shift = ps / 4;
1065 ectx.start = base; 1127 ectx.start = base;
@@ -1096,6 +1158,12 @@ static void atom_execute_table_locked(struct atom_context *ctx, int index, uint3
1096void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) 1158void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
1097{ 1159{
1098 mutex_lock(&ctx->mutex); 1160 mutex_lock(&ctx->mutex);
1161 /* reset reg block */
1162 ctx->reg_block = 0;
1163 /* reset fb window */
1164 ctx->fb_base = 0;
1165 /* reset io mode */
1166 ctx->io_mode = ATOM_IO_MM;
1099 atom_execute_table_locked(ctx, index, params); 1167 atom_execute_table_locked(ctx, index, params);
1100 mutex_unlock(&ctx->mutex); 1168 mutex_unlock(&ctx->mutex);
1101} 1169}
diff --git a/drivers/gpu/drm/radeon/atom.h b/drivers/gpu/drm/radeon/atom.h
index 47fd943f6d14..bc73781423a1 100644
--- a/drivers/gpu/drm/radeon/atom.h
+++ b/drivers/gpu/drm/radeon/atom.h
@@ -91,6 +91,7 @@
91#define ATOM_WS_AND_MASK 0x45 91#define ATOM_WS_AND_MASK 0x45
92#define ATOM_WS_FB_WINDOW 0x46 92#define ATOM_WS_FB_WINDOW 0x46
93#define ATOM_WS_ATTRIBUTES 0x47 93#define ATOM_WS_ATTRIBUTES 0x47
94#define ATOM_WS_REGPTR 0x48
94 95
95#define ATOM_IIO_NOP 0 96#define ATOM_IIO_NOP 0
96#define ATOM_IIO_START 1 97#define ATOM_IIO_START 1
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 260fcf59f00c..e619aca5423f 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -409,59 +409,57 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
409 } 409 }
410} 410}
411 411
412void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 412union adjust_pixel_clock {
413 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
414};
415
416static u32 atombios_adjust_pll(struct drm_crtc *crtc,
417 struct drm_display_mode *mode,
418 struct radeon_pll *pll)
413{ 419{
414 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
415 struct drm_device *dev = crtc->dev; 420 struct drm_device *dev = crtc->dev;
416 struct radeon_device *rdev = dev->dev_private; 421 struct radeon_device *rdev = dev->dev_private;
417 struct drm_encoder *encoder = NULL; 422 struct drm_encoder *encoder = NULL;
418 struct radeon_encoder *radeon_encoder = NULL; 423 struct radeon_encoder *radeon_encoder = NULL;
419 uint8_t frev, crev; 424 u32 adjusted_clock = mode->clock;
420 int index;
421 SET_PIXEL_CLOCK_PS_ALLOCATION args;
422 PIXEL_CLOCK_PARAMETERS *spc1_ptr;
423 PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
424 PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
425 uint32_t pll_clock = mode->clock;
426 uint32_t adjusted_clock;
427 uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
428 struct radeon_pll *pll;
429 int pll_flags = 0;
430 425
431 memset(&args, 0, sizeof(args)); 426 /* reset the pll flags */
427 pll->flags = 0;
432 428
433 if (ASIC_IS_AVIVO(rdev)) { 429 if (ASIC_IS_AVIVO(rdev)) {
434 if ((rdev->family == CHIP_RS600) || 430 if ((rdev->family == CHIP_RS600) ||
435 (rdev->family == CHIP_RS690) || 431 (rdev->family == CHIP_RS690) ||
436 (rdev->family == CHIP_RS740)) 432 (rdev->family == CHIP_RS740))
437 pll_flags |= (RADEON_PLL_USE_FRAC_FB_DIV | 433 pll->flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
438 RADEON_PLL_PREFER_CLOSEST_LOWER); 434 RADEON_PLL_PREFER_CLOSEST_LOWER);
439 435
440 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ 436 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
441 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 437 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
442 else 438 else
443 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 439 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
444 } else { 440 } else {
445 pll_flags |= RADEON_PLL_LEGACY; 441 pll->flags |= RADEON_PLL_LEGACY;
446 442
447 if (mode->clock > 200000) /* range limits??? */ 443 if (mode->clock > 200000) /* range limits??? */
448 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 444 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
449 else 445 else
450 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 446 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
451 447
452 } 448 }
453 449
454 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 450 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
455 if (encoder->crtc == crtc) { 451 if (encoder->crtc == crtc) {
456 if (!ASIC_IS_AVIVO(rdev)) {
457 if (encoder->encoder_type !=
458 DRM_MODE_ENCODER_DAC)
459 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
460 if (encoder->encoder_type ==
461 DRM_MODE_ENCODER_LVDS)
462 pll_flags |= RADEON_PLL_USE_REF_DIV;
463 }
464 radeon_encoder = to_radeon_encoder(encoder); 452 radeon_encoder = to_radeon_encoder(encoder);
453 if (ASIC_IS_AVIVO(rdev)) {
454 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
455 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
456 adjusted_clock = mode->clock * 2;
457 } else {
458 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
459 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
460 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
461 pll->flags |= RADEON_PLL_USE_REF_DIV;
462 }
465 break; 463 break;
466 } 464 }
467 } 465 }
@@ -471,46 +469,101 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
471 * special hw requirements. 469 * special hw requirements.
472 */ 470 */
473 if (ASIC_IS_DCE3(rdev)) { 471 if (ASIC_IS_DCE3(rdev)) {
474 ADJUST_DISPLAY_PLL_PS_ALLOCATION adjust_pll_args; 472 union adjust_pixel_clock args;
473 struct radeon_encoder_atom_dig *dig;
474 u8 frev, crev;
475 int index;
475 476
476 if (!encoder) 477 if (!radeon_encoder->enc_priv)
477 return; 478 return adjusted_clock;
478 479 dig = radeon_encoder->enc_priv;
479 memset(&adjust_pll_args, 0, sizeof(adjust_pll_args));
480 adjust_pll_args.usPixelClock = cpu_to_le16(mode->clock / 10);
481 adjust_pll_args.ucTransmitterID = radeon_encoder->encoder_id;
482 adjust_pll_args.ucEncodeMode = atombios_get_encoder_mode(encoder);
483 480
484 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 481 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
485 atom_execute_table(rdev->mode_info.atom_context, 482 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
486 index, (uint32_t *)&adjust_pll_args); 483 &crev);
487 adjusted_clock = le16_to_cpu(adjust_pll_args.usPixelClock) * 10; 484
488 } else { 485 memset(&args, 0, sizeof(args));
489 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 486
490 if (ASIC_IS_AVIVO(rdev) && 487 switch (frev) {
491 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 488 case 1:
492 adjusted_clock = mode->clock * 2; 489 switch (crev) {
493 else 490 case 1:
494 adjusted_clock = mode->clock; 491 case 2:
492 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
493 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
494 args.v1.ucEncodeMode = atombios_get_encoder_mode(encoder);
495
496 atom_execute_table(rdev->mode_info.atom_context,
497 index, (uint32_t *)&args);
498 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
499 break;
500 default:
501 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
502 return adjusted_clock;
503 }
504 break;
505 default:
506 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
507 return adjusted_clock;
508 }
495 } 509 }
510 return adjusted_clock;
511}
512
513union set_pixel_clock {
514 SET_PIXEL_CLOCK_PS_ALLOCATION base;
515 PIXEL_CLOCK_PARAMETERS v1;
516 PIXEL_CLOCK_PARAMETERS_V2 v2;
517 PIXEL_CLOCK_PARAMETERS_V3 v3;
518};
519
520void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
521{
522 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
523 struct drm_device *dev = crtc->dev;
524 struct radeon_device *rdev = dev->dev_private;
525 struct drm_encoder *encoder = NULL;
526 struct radeon_encoder *radeon_encoder = NULL;
527 u8 frev, crev;
528 int index;
529 union set_pixel_clock args;
530 u32 pll_clock = mode->clock;
531 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
532 struct radeon_pll *pll;
533 u32 adjusted_clock;
534
535 memset(&args, 0, sizeof(args));
536
537 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
538 if (encoder->crtc == crtc) {
539 radeon_encoder = to_radeon_encoder(encoder);
540 break;
541 }
542 }
543
544 if (!radeon_encoder)
545 return;
496 546
497 if (radeon_crtc->crtc_id == 0) 547 if (radeon_crtc->crtc_id == 0)
498 pll = &rdev->clock.p1pll; 548 pll = &rdev->clock.p1pll;
499 else 549 else
500 pll = &rdev->clock.p2pll; 550 pll = &rdev->clock.p2pll;
501 551
552 /* adjust pixel clock as needed */
553 adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
554
502 if (ASIC_IS_AVIVO(rdev)) { 555 if (ASIC_IS_AVIVO(rdev)) {
503 if (radeon_new_pll) 556 if (radeon_new_pll)
504 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, 557 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock,
505 &fb_div, &frac_fb_div, 558 &fb_div, &frac_fb_div,
506 &ref_div, &post_div, pll_flags); 559 &ref_div, &post_div);
507 else 560 else
508 radeon_compute_pll(pll, adjusted_clock, &pll_clock, 561 radeon_compute_pll(pll, adjusted_clock, &pll_clock,
509 &fb_div, &frac_fb_div, 562 &fb_div, &frac_fb_div,
510 &ref_div, &post_div, pll_flags); 563 &ref_div, &post_div);
511 } else 564 } else
512 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, 565 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
513 &ref_div, &post_div, pll_flags); 566 &ref_div, &post_div);
514 567
515 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 568 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
516 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 569 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
@@ -520,45 +573,38 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
520 case 1: 573 case 1:
521 switch (crev) { 574 switch (crev) {
522 case 1: 575 case 1:
523 spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput; 576 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
524 spc1_ptr->usPixelClock = cpu_to_le16(mode->clock / 10); 577 args.v1.usRefDiv = cpu_to_le16(ref_div);
525 spc1_ptr->usRefDiv = cpu_to_le16(ref_div); 578 args.v1.usFbDiv = cpu_to_le16(fb_div);
526 spc1_ptr->usFbDiv = cpu_to_le16(fb_div); 579 args.v1.ucFracFbDiv = frac_fb_div;
527 spc1_ptr->ucFracFbDiv = frac_fb_div; 580 args.v1.ucPostDiv = post_div;
528 spc1_ptr->ucPostDiv = post_div; 581 args.v1.ucPpll =
529 spc1_ptr->ucPpll =
530 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; 582 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
531 spc1_ptr->ucCRTC = radeon_crtc->crtc_id; 583 args.v1.ucCRTC = radeon_crtc->crtc_id;
532 spc1_ptr->ucRefDivSrc = 1; 584 args.v1.ucRefDivSrc = 1;
533 break; 585 break;
534 case 2: 586 case 2:
535 spc2_ptr = 587 args.v2.usPixelClock = cpu_to_le16(mode->clock / 10);
536 (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput; 588 args.v2.usRefDiv = cpu_to_le16(ref_div);
537 spc2_ptr->usPixelClock = cpu_to_le16(mode->clock / 10); 589 args.v2.usFbDiv = cpu_to_le16(fb_div);
538 spc2_ptr->usRefDiv = cpu_to_le16(ref_div); 590 args.v2.ucFracFbDiv = frac_fb_div;
539 spc2_ptr->usFbDiv = cpu_to_le16(fb_div); 591 args.v2.ucPostDiv = post_div;
540 spc2_ptr->ucFracFbDiv = frac_fb_div; 592 args.v2.ucPpll =
541 spc2_ptr->ucPostDiv = post_div;
542 spc2_ptr->ucPpll =
543 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; 593 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
544 spc2_ptr->ucCRTC = radeon_crtc->crtc_id; 594 args.v2.ucCRTC = radeon_crtc->crtc_id;
545 spc2_ptr->ucRefDivSrc = 1; 595 args.v2.ucRefDivSrc = 1;
546 break; 596 break;
547 case 3: 597 case 3:
548 if (!encoder) 598 args.v3.usPixelClock = cpu_to_le16(mode->clock / 10);
549 return; 599 args.v3.usRefDiv = cpu_to_le16(ref_div);
550 spc3_ptr = 600 args.v3.usFbDiv = cpu_to_le16(fb_div);
551 (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput; 601 args.v3.ucFracFbDiv = frac_fb_div;
552 spc3_ptr->usPixelClock = cpu_to_le16(mode->clock / 10); 602 args.v3.ucPostDiv = post_div;
553 spc3_ptr->usRefDiv = cpu_to_le16(ref_div); 603 args.v3.ucPpll =
554 spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
555 spc3_ptr->ucFracFbDiv = frac_fb_div;
556 spc3_ptr->ucPostDiv = post_div;
557 spc3_ptr->ucPpll =
558 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; 604 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
559 spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2); 605 args.v3.ucMiscInfo = (radeon_crtc->crtc_id << 2);
560 spc3_ptr->ucTransmitterId = radeon_encoder->encoder_id; 606 args.v3.ucTransmitterId = radeon_encoder->encoder_id;
561 spc3_ptr->ucEncoderMode = 607 args.v3.ucEncoderMode =
562 atombios_get_encoder_mode(encoder); 608 atombios_get_encoder_mode(encoder);
563 break; 609 break;
564 default: 610 default:
@@ -571,12 +617,11 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
571 return; 617 return;
572 } 618 }
573 619
574 printk("executing set pll\n");
575 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 620 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
576} 621}
577 622
578int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 623static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
579 struct drm_framebuffer *old_fb) 624 struct drm_framebuffer *old_fb)
580{ 625{
581 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 626 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
582 struct drm_device *dev = crtc->dev; 627 struct drm_device *dev = crtc->dev;
@@ -706,6 +751,42 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
706 return 0; 751 return 0;
707} 752}
708 753
754int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
755 struct drm_framebuffer *old_fb)
756{
757 struct drm_device *dev = crtc->dev;
758 struct radeon_device *rdev = dev->dev_private;
759
760 if (ASIC_IS_AVIVO(rdev))
761 return avivo_crtc_set_base(crtc, x, y, old_fb);
762 else
763 return radeon_crtc_set_base(crtc, x, y, old_fb);
764}
765
766/* properly set additional regs when using atombios */
767static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
768{
769 struct drm_device *dev = crtc->dev;
770 struct radeon_device *rdev = dev->dev_private;
771 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
772 u32 disp_merge_cntl;
773
774 switch (radeon_crtc->crtc_id) {
775 case 0:
776 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
777 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
778 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
779 break;
780 case 1:
781 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
782 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
783 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
784 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
785 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
786 break;
787 }
788}
789
709int atombios_crtc_mode_set(struct drm_crtc *crtc, 790int atombios_crtc_mode_set(struct drm_crtc *crtc,
710 struct drm_display_mode *mode, 791 struct drm_display_mode *mode,
711 struct drm_display_mode *adjusted_mode, 792 struct drm_display_mode *adjusted_mode,
@@ -727,8 +808,8 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
727 else { 808 else {
728 if (radeon_crtc->crtc_id == 0) 809 if (radeon_crtc->crtc_id == 0)
729 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 810 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
730 radeon_crtc_set_base(crtc, x, y, old_fb); 811 atombios_crtc_set_base(crtc, x, y, old_fb);
731 radeon_legacy_atom_set_surface(crtc); 812 radeon_legacy_atom_fixup(crtc);
732 } 813 }
733 atombios_overscan_setup(crtc, mode, adjusted_mode); 814 atombios_overscan_setup(crtc, mode, adjusted_mode);
734 atombios_scaler_setup(crtc); 815 atombios_scaler_setup(crtc);
@@ -746,8 +827,8 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
746 827
747static void atombios_crtc_prepare(struct drm_crtc *crtc) 828static void atombios_crtc_prepare(struct drm_crtc *crtc)
748{ 829{
749 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
750 atombios_lock_crtc(crtc, 1); 830 atombios_lock_crtc(crtc, 1);
831 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
751} 832}
752 833
753static void atombios_crtc_commit(struct drm_crtc *crtc) 834static void atombios_crtc_commit(struct drm_crtc *crtc)
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 62b27bede651..11c9a3fe6810 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1504,6 +1504,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1504 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1504 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1505 return -EINVAL; 1505 return -EINVAL;
1506 } 1506 }
1507 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1507 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1508 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1508 track->immd_dwords = pkt->count - 1; 1509 track->immd_dwords = pkt->count - 1;
1509 r = r100_cs_track_check(p->rdev, track); 1510 r = r100_cs_track_check(p->rdev, track);
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
index 20942127c46b..ff1e0cd608bf 100644
--- a/drivers/gpu/drm/radeon/r200.c
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -371,13 +371,16 @@ int r200_packet0_check(struct radeon_cs_parser *p,
371 case 5: 371 case 5:
372 case 6: 372 case 6:
373 case 7: 373 case 7:
374 /* 1D/2D */
374 track->textures[i].tex_coord_type = 0; 375 track->textures[i].tex_coord_type = 0;
375 break; 376 break;
376 case 1: 377 case 1:
377 track->textures[i].tex_coord_type = 1; 378 /* CUBE */
379 track->textures[i].tex_coord_type = 2;
378 break; 380 break;
379 case 2: 381 case 2:
380 track->textures[i].tex_coord_type = 2; 382 /* 3D */
383 track->textures[i].tex_coord_type = 1;
381 break; 384 break;
382 } 385 }
383 break; 386 break;
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index b3713f61964c..d0bd117a463a 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1954,6 +1954,7 @@ int r600_suspend(struct radeon_device *rdev)
1954 /* FIXME: we should wait for ring to be empty */ 1954 /* FIXME: we should wait for ring to be empty */
1955 r600_cp_stop(rdev); 1955 r600_cp_stop(rdev);
1956 rdev->cp.ready = false; 1956 rdev->cp.ready = false;
1957 r600_irq_suspend(rdev);
1957 r600_wb_disable(rdev); 1958 r600_wb_disable(rdev);
1958 r600_pcie_gart_disable(rdev); 1959 r600_pcie_gart_disable(rdev);
1959 /* unpin shaders bo */ 1960 /* unpin shaders bo */
@@ -2063,13 +2064,14 @@ int r600_init(struct radeon_device *rdev)
2063 if (rdev->accel_working) { 2064 if (rdev->accel_working) {
2064 r = radeon_ib_pool_init(rdev); 2065 r = radeon_ib_pool_init(rdev);
2065 if (r) { 2066 if (r) {
2066 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); 2067 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2067 rdev->accel_working = false;
2068 }
2069 r = r600_ib_test(rdev);
2070 if (r) {
2071 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2072 rdev->accel_working = false; 2068 rdev->accel_working = false;
2069 } else {
2070 r = r600_ib_test(rdev);
2071 if (r) {
2072 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2073 rdev->accel_working = false;
2074 }
2073 } 2075 }
2074 } 2076 }
2075 2077
@@ -2200,14 +2202,14 @@ void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2200 rb_bufsz = drm_order(ring_size / 4); 2202 rb_bufsz = drm_order(ring_size / 4);
2201 ring_size = (1 << rb_bufsz) * 4; 2203 ring_size = (1 << rb_bufsz) * 4;
2202 rdev->ih.ring_size = ring_size; 2204 rdev->ih.ring_size = ring_size;
2203 rdev->ih.align_mask = 4 - 1; 2205 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2206 rdev->ih.rptr = 0;
2204} 2207}
2205 2208
2206static int r600_ih_ring_alloc(struct radeon_device *rdev, unsigned ring_size) 2209static int r600_ih_ring_alloc(struct radeon_device *rdev)
2207{ 2210{
2208 int r; 2211 int r;
2209 2212
2210 rdev->ih.ring_size = ring_size;
2211 /* Allocate ring buffer */ 2213 /* Allocate ring buffer */
2212 if (rdev->ih.ring_obj == NULL) { 2214 if (rdev->ih.ring_obj == NULL) {
2213 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size, 2215 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
@@ -2237,9 +2239,6 @@ static int r600_ih_ring_alloc(struct radeon_device *rdev, unsigned ring_size)
2237 return r; 2239 return r;
2238 } 2240 }
2239 } 2241 }
2240 rdev->ih.ptr_mask = (rdev->cp.ring_size / 4) - 1;
2241 rdev->ih.rptr = 0;
2242
2243 return 0; 2242 return 0;
2244} 2243}
2245 2244
@@ -2389,7 +2388,7 @@ int r600_irq_init(struct radeon_device *rdev)
2389 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 2388 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2390 2389
2391 /* allocate ring */ 2390 /* allocate ring */
2392 ret = r600_ih_ring_alloc(rdev, rdev->ih.ring_size); 2391 ret = r600_ih_ring_alloc(rdev);
2393 if (ret) 2392 if (ret)
2394 return ret; 2393 return ret;
2395 2394
@@ -2452,10 +2451,15 @@ int r600_irq_init(struct radeon_device *rdev)
2452 return ret; 2451 return ret;
2453} 2452}
2454 2453
2455void r600_irq_fini(struct radeon_device *rdev) 2454void r600_irq_suspend(struct radeon_device *rdev)
2456{ 2455{
2457 r600_disable_interrupts(rdev); 2456 r600_disable_interrupts(rdev);
2458 r600_rlc_stop(rdev); 2457 r600_rlc_stop(rdev);
2458}
2459
2460void r600_irq_fini(struct radeon_device *rdev)
2461{
2462 r600_irq_suspend(rdev);
2459 r600_ih_ring_fini(rdev); 2463 r600_ih_ring_fini(rdev);
2460} 2464}
2461 2465
@@ -2470,8 +2474,12 @@ int r600_irq_set(struct radeon_device *rdev)
2470 return -EINVAL; 2474 return -EINVAL;
2471 } 2475 }
2472 /* don't enable anything if the ih is disabled */ 2476 /* don't enable anything if the ih is disabled */
2473 if (!rdev->ih.enabled) 2477 if (!rdev->ih.enabled) {
2478 r600_disable_interrupts(rdev);
2479 /* force the active interrupt state to all disabled */
2480 r600_disable_interrupt_state(rdev);
2474 return 0; 2481 return 0;
2482 }
2475 2483
2476 if (ASIC_IS_DCE3(rdev)) { 2484 if (ASIC_IS_DCE3(rdev)) {
2477 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 2485 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
@@ -2641,16 +2649,18 @@ static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2641 wptr = RREG32(IH_RB_WPTR); 2649 wptr = RREG32(IH_RB_WPTR);
2642 2650
2643 if (wptr & RB_OVERFLOW) { 2651 if (wptr & RB_OVERFLOW) {
2644 WARN_ON(1); 2652 /* When a ring buffer overflow happen start parsing interrupt
2645 /* XXX deal with overflow */ 2653 * from the last not overwritten vector (wptr + 16). Hopefully
2646 DRM_ERROR("IH RB overflow\n"); 2654 * this should allow us to catchup.
2655 */
2656 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2657 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2658 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2647 tmp = RREG32(IH_RB_CNTL); 2659 tmp = RREG32(IH_RB_CNTL);
2648 tmp |= IH_WPTR_OVERFLOW_CLEAR; 2660 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2649 WREG32(IH_RB_CNTL, tmp); 2661 WREG32(IH_RB_CNTL, tmp);
2650 } 2662 }
2651 wptr = wptr & WPTR_OFFSET_MASK; 2663 return (wptr & rdev->ih.ptr_mask);
2652
2653 return wptr;
2654} 2664}
2655 2665
2656/* r600 IV Ring 2666/* r600 IV Ring
@@ -2686,12 +2696,13 @@ int r600_irq_process(struct radeon_device *rdev)
2686 u32 wptr = r600_get_ih_wptr(rdev); 2696 u32 wptr = r600_get_ih_wptr(rdev);
2687 u32 rptr = rdev->ih.rptr; 2697 u32 rptr = rdev->ih.rptr;
2688 u32 src_id, src_data; 2698 u32 src_id, src_data;
2689 u32 last_entry = rdev->ih.ring_size - 16;
2690 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2; 2699 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
2691 unsigned long flags; 2700 unsigned long flags;
2692 bool queue_hotplug = false; 2701 bool queue_hotplug = false;
2693 2702
2694 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 2703 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2704 if (!rdev->ih.enabled)
2705 return IRQ_NONE;
2695 2706
2696 spin_lock_irqsave(&rdev->ih.lock, flags); 2707 spin_lock_irqsave(&rdev->ih.lock, flags);
2697 2708
@@ -2820,10 +2831,8 @@ restart_ih:
2820 } 2831 }
2821 2832
2822 /* wptr/rptr are in bytes! */ 2833 /* wptr/rptr are in bytes! */
2823 if (rptr == last_entry) 2834 rptr += 16;
2824 rptr = 0; 2835 rptr &= rdev->ih.ptr_mask;
2825 else
2826 rptr += 16;
2827 } 2836 }
2828 /* make sure wptr hasn't changed while processing */ 2837 /* make sure wptr hasn't changed while processing */
2829 wptr = r600_get_ih_wptr(rdev); 2838 wptr = r600_get_ih_wptr(rdev);
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 44060b92d9e6..9cc4ba8d03d5 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -36,6 +36,10 @@ static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
36typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**); 36typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
37static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm; 37static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
38 38
39struct r600_cs_track {
40 u32 cb_color0_base_last;
41};
42
39/** 43/**
40 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet 44 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
41 * @parser: parser structure holding parsing context. 45 * @parser: parser structure holding parsing context.
@@ -177,6 +181,28 @@ static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
177} 181}
178 182
179/** 183/**
184 * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
185 * @parser: parser structure holding parsing context.
186 *
187 * Check next packet is relocation packet3, do bo validation and compute
188 * GPU offset using the provided start.
189 **/
190static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
191{
192 struct radeon_cs_packet p3reloc;
193 int r;
194
195 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
196 if (r) {
197 return 0;
198 }
199 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
200 return 0;
201 }
202 return 1;
203}
204
205/**
180 * r600_cs_packet_next_vline() - parse userspace VLINE packet 206 * r600_cs_packet_next_vline() - parse userspace VLINE packet
181 * @parser: parser structure holding parsing context. 207 * @parser: parser structure holding parsing context.
182 * 208 *
@@ -337,6 +363,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
337 struct radeon_cs_packet *pkt) 363 struct radeon_cs_packet *pkt)
338{ 364{
339 struct radeon_cs_reloc *reloc; 365 struct radeon_cs_reloc *reloc;
366 struct r600_cs_track *track;
340 volatile u32 *ib; 367 volatile u32 *ib;
341 unsigned idx; 368 unsigned idx;
342 unsigned i; 369 unsigned i;
@@ -344,6 +371,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
344 int r; 371 int r;
345 u32 idx_value; 372 u32 idx_value;
346 373
374 track = (struct r600_cs_track *)p->track;
347 ib = p->ib->ptr; 375 ib = p->ib->ptr;
348 idx = pkt->idx + 1; 376 idx = pkt->idx + 1;
349 idx_value = radeon_get_ib_value(p, idx); 377 idx_value = radeon_get_ib_value(p, idx);
@@ -503,9 +531,60 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
503 for (i = 0; i < pkt->count; i++) { 531 for (i = 0; i < pkt->count; i++) {
504 reg = start_reg + (4 * i); 532 reg = start_reg + (4 * i);
505 switch (reg) { 533 switch (reg) {
534 /* This register were added late, there is userspace
535 * which does provide relocation for those but set
536 * 0 offset. In order to avoid breaking old userspace
537 * we detect this and set address to point to last
538 * CB_COLOR0_BASE, note that if userspace doesn't set
539 * CB_COLOR0_BASE before this register we will report
540 * error. Old userspace always set CB_COLOR0_BASE
541 * before any of this.
542 */
543 case R_0280E0_CB_COLOR0_FRAG:
544 case R_0280E4_CB_COLOR1_FRAG:
545 case R_0280E8_CB_COLOR2_FRAG:
546 case R_0280EC_CB_COLOR3_FRAG:
547 case R_0280F0_CB_COLOR4_FRAG:
548 case R_0280F4_CB_COLOR5_FRAG:
549 case R_0280F8_CB_COLOR6_FRAG:
550 case R_0280FC_CB_COLOR7_FRAG:
551 case R_0280C0_CB_COLOR0_TILE:
552 case R_0280C4_CB_COLOR1_TILE:
553 case R_0280C8_CB_COLOR2_TILE:
554 case R_0280CC_CB_COLOR3_TILE:
555 case R_0280D0_CB_COLOR4_TILE:
556 case R_0280D4_CB_COLOR5_TILE:
557 case R_0280D8_CB_COLOR6_TILE:
558 case R_0280DC_CB_COLOR7_TILE:
559 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
560 if (!track->cb_color0_base_last) {
561 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
562 return -EINVAL;
563 }
564 ib[idx+1+i] = track->cb_color0_base_last;
565 printk_once(KERN_WARNING "You have old & broken userspace "
566 "please consider updating mesa & xf86-video-ati\n");
567 } else {
568 r = r600_cs_packet_next_reloc(p, &reloc);
569 if (r) {
570 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
571 return -EINVAL;
572 }
573 ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
574 }
575 break;
506 case DB_DEPTH_BASE: 576 case DB_DEPTH_BASE:
507 case DB_HTILE_DATA_BASE: 577 case DB_HTILE_DATA_BASE:
508 case CB_COLOR0_BASE: 578 case CB_COLOR0_BASE:
579 r = r600_cs_packet_next_reloc(p, &reloc);
580 if (r) {
581 DRM_ERROR("bad SET_CONTEXT_REG "
582 "0x%04X\n", reg);
583 return -EINVAL;
584 }
585 ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
586 track->cb_color0_base_last = ib[idx+1+i];
587 break;
509 case CB_COLOR1_BASE: 588 case CB_COLOR1_BASE:
510 case CB_COLOR2_BASE: 589 case CB_COLOR2_BASE:
511 case CB_COLOR3_BASE: 590 case CB_COLOR3_BASE:
@@ -678,8 +757,11 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
678int r600_cs_parse(struct radeon_cs_parser *p) 757int r600_cs_parse(struct radeon_cs_parser *p)
679{ 758{
680 struct radeon_cs_packet pkt; 759 struct radeon_cs_packet pkt;
760 struct r600_cs_track *track;
681 int r; 761 int r;
682 762
763 track = kzalloc(sizeof(*track), GFP_KERNEL);
764 p->track = track;
683 do { 765 do {
684 r = r600_cs_packet_parse(p, &pkt, p->idx); 766 r = r600_cs_packet_parse(p, &pkt, p->idx);
685 if (r) { 767 if (r) {
@@ -757,6 +839,7 @@ int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
757 /* initialize parser */ 839 /* initialize parser */
758 memset(&parser, 0, sizeof(struct radeon_cs_parser)); 840 memset(&parser, 0, sizeof(struct radeon_cs_parser));
759 parser.filp = filp; 841 parser.filp = filp;
842 parser.dev = &dev->pdev->dev;
760 parser.rdev = NULL; 843 parser.rdev = NULL;
761 parser.family = family; 844 parser.family = family;
762 parser.ib = &fake_ib; 845 parser.ib = &fake_ib;
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 05894edadab4..30480881aed1 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -882,4 +882,29 @@
882#define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) 882#define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17)
883 883
884#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 884#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
885
886#define R_0280E0_CB_COLOR0_FRAG 0x0280E0
887#define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
888#define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
889#define C_0280E0_BASE_256B 0x00000000
890#define R_0280E4_CB_COLOR1_FRAG 0x0280E4
891#define R_0280E8_CB_COLOR2_FRAG 0x0280E8
892#define R_0280EC_CB_COLOR3_FRAG 0x0280EC
893#define R_0280F0_CB_COLOR4_FRAG 0x0280F0
894#define R_0280F4_CB_COLOR5_FRAG 0x0280F4
895#define R_0280F8_CB_COLOR6_FRAG 0x0280F8
896#define R_0280FC_CB_COLOR7_FRAG 0x0280FC
897#define R_0280C0_CB_COLOR0_TILE 0x0280C0
898#define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
899#define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
900#define C_0280C0_BASE_256B 0x00000000
901#define R_0280C4_CB_COLOR1_TILE 0x0280C4
902#define R_0280C8_CB_COLOR2_TILE 0x0280C8
903#define R_0280CC_CB_COLOR3_TILE 0x0280CC
904#define R_0280D0_CB_COLOR4_TILE 0x0280D0
905#define R_0280D4_CB_COLOR5_TILE 0x0280D4
906#define R_0280D8_CB_COLOR6_TILE 0x0280D8
907#define R_0280DC_CB_COLOR7_TILE 0x0280DC
908
909
885#endif 910#endif
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index ab37dd0f2e71..f7df1a7e4413 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -410,7 +410,6 @@ struct r600_ih {
410 unsigned wptr_old; 410 unsigned wptr_old;
411 unsigned ring_size; 411 unsigned ring_size;
412 uint64_t gpu_addr; 412 uint64_t gpu_addr;
413 uint32_t align_mask;
414 uint32_t ptr_mask; 413 uint32_t ptr_mask;
415 spinlock_t lock; 414 spinlock_t lock;
416 bool enabled; 415 bool enabled;
@@ -465,6 +464,7 @@ struct radeon_cs_chunk {
465}; 464};
466 465
467struct radeon_cs_parser { 466struct radeon_cs_parser {
467 struct device *dev;
468 struct radeon_device *rdev; 468 struct radeon_device *rdev;
469 struct drm_file *filp; 469 struct drm_file *filp;
470 /* chunks */ 470 /* chunks */
@@ -847,7 +847,7 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
847 847
848static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) 848static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
849{ 849{
850 if (reg < 0x10000) 850 if (reg < rdev->rmmio_size)
851 return readl(((void __iomem *)rdev->rmmio) + reg); 851 return readl(((void __iomem *)rdev->rmmio) + reg);
852 else { 852 else {
853 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 853 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
@@ -857,7 +857,7 @@ static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
857 857
858static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 858static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
859{ 859{
860 if (reg < 0x10000) 860 if (reg < rdev->rmmio_size)
861 writel(v, ((void __iomem *)rdev->rmmio) + reg); 861 writel(v, ((void __iomem *)rdev->rmmio) + reg);
862 else { 862 else {
863 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 863 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
@@ -1162,7 +1162,8 @@ extern int r600_irq_init(struct radeon_device *rdev);
1162extern void r600_irq_fini(struct radeon_device *rdev); 1162extern void r600_irq_fini(struct radeon_device *rdev);
1163extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 1163extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1164extern int r600_irq_set(struct radeon_device *rdev); 1164extern int r600_irq_set(struct radeon_device *rdev);
1165 1165extern void r600_irq_suspend(struct radeon_device *rdev);
1166/* r600 audio */
1166extern int r600_audio_init(struct radeon_device *rdev); 1167extern int r600_audio_init(struct radeon_device *rdev);
1167extern int r600_audio_tmds_index(struct drm_encoder *encoder); 1168extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1168extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); 1169extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index 812f24dbc2a8..73c4405bf42f 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -56,7 +56,7 @@ uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
56 else if (post_div == 3) 56 else if (post_div == 3)
57 sclk >>= 2; 57 sclk >>= 2;
58 else if (post_div == 4) 58 else if (post_div == 4)
59 sclk >>= 4; 59 sclk >>= 3;
60 60
61 return sclk; 61 return sclk;
62} 62}
@@ -86,7 +86,7 @@ uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
86 else if (post_div == 3) 86 else if (post_div == 3)
87 mclk >>= 2; 87 mclk >>= 2;
88 else if (post_div == 4) 88 else if (post_div == 4)
89 mclk >>= 4; 89 mclk >>= 3;
90 90
91 return mclk; 91 return mclk;
92} 92}
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index 65590a0f1d93..1496cb8658ef 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -231,6 +231,7 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
231 memset(&parser, 0, sizeof(struct radeon_cs_parser)); 231 memset(&parser, 0, sizeof(struct radeon_cs_parser));
232 parser.filp = filp; 232 parser.filp = filp;
233 parser.rdev = rdev; 233 parser.rdev = rdev;
234 parser.dev = rdev->dev;
234 r = radeon_cs_parser_init(&parser, data); 235 r = radeon_cs_parser_init(&parser, data);
235 if (r) { 236 if (r) {
236 DRM_ERROR("Failed to initialize parser !\n"); 237 DRM_ERROR("Failed to initialize parser !\n");
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 49f3c69cf240..6a92f994cc26 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -411,11 +411,12 @@ void radeon_compute_pll(struct radeon_pll *pll,
411 uint32_t *fb_div_p, 411 uint32_t *fb_div_p,
412 uint32_t *frac_fb_div_p, 412 uint32_t *frac_fb_div_p,
413 uint32_t *ref_div_p, 413 uint32_t *ref_div_p,
414 uint32_t *post_div_p, 414 uint32_t *post_div_p)
415 int flags)
416{ 415{
417 uint32_t min_ref_div = pll->min_ref_div; 416 uint32_t min_ref_div = pll->min_ref_div;
418 uint32_t max_ref_div = pll->max_ref_div; 417 uint32_t max_ref_div = pll->max_ref_div;
418 uint32_t min_post_div = pll->min_post_div;
419 uint32_t max_post_div = pll->max_post_div;
419 uint32_t min_fractional_feed_div = 0; 420 uint32_t min_fractional_feed_div = 0;
420 uint32_t max_fractional_feed_div = 0; 421 uint32_t max_fractional_feed_div = 0;
421 uint32_t best_vco = pll->best_vco; 422 uint32_t best_vco = pll->best_vco;
@@ -431,7 +432,7 @@ void radeon_compute_pll(struct radeon_pll *pll,
431 DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 432 DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
432 freq = freq * 1000; 433 freq = freq * 1000;
433 434
434 if (flags & RADEON_PLL_USE_REF_DIV) 435 if (pll->flags & RADEON_PLL_USE_REF_DIV)
435 min_ref_div = max_ref_div = pll->reference_div; 436 min_ref_div = max_ref_div = pll->reference_div;
436 else { 437 else {
437 while (min_ref_div < max_ref_div-1) { 438 while (min_ref_div < max_ref_div-1) {
@@ -446,19 +447,22 @@ void radeon_compute_pll(struct radeon_pll *pll,
446 } 447 }
447 } 448 }
448 449
449 if (flags & RADEON_PLL_USE_FRAC_FB_DIV) { 450 if (pll->flags & RADEON_PLL_USE_POST_DIV)
451 min_post_div = max_post_div = pll->post_div;
452
453 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
450 min_fractional_feed_div = pll->min_frac_feedback_div; 454 min_fractional_feed_div = pll->min_frac_feedback_div;
451 max_fractional_feed_div = pll->max_frac_feedback_div; 455 max_fractional_feed_div = pll->max_frac_feedback_div;
452 } 456 }
453 457
454 for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) { 458 for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
455 uint32_t ref_div; 459 uint32_t ref_div;
456 460
457 if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 461 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
458 continue; 462 continue;
459 463
460 /* legacy radeons only have a few post_divs */ 464 /* legacy radeons only have a few post_divs */
461 if (flags & RADEON_PLL_LEGACY) { 465 if (pll->flags & RADEON_PLL_LEGACY) {
462 if ((post_div == 5) || 466 if ((post_div == 5) ||
463 (post_div == 7) || 467 (post_div == 7) ||
464 (post_div == 9) || 468 (post_div == 9) ||
@@ -505,7 +509,7 @@ void radeon_compute_pll(struct radeon_pll *pll,
505 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 509 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
506 current_freq = radeon_div(tmp, ref_div * post_div); 510 current_freq = radeon_div(tmp, ref_div * post_div);
507 511
508 if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 512 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
509 error = freq - current_freq; 513 error = freq - current_freq;
510 error = error < 0 ? 0xffffffff : error; 514 error = error < 0 ? 0xffffffff : error;
511 } else 515 } else
@@ -532,12 +536,12 @@ void radeon_compute_pll(struct radeon_pll *pll,
532 best_freq = current_freq; 536 best_freq = current_freq;
533 best_error = error; 537 best_error = error;
534 best_vco_diff = vco_diff; 538 best_vco_diff = vco_diff;
535 } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 539 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
536 ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 540 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
537 ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 541 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
538 ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 542 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
539 ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 543 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
540 ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 544 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
541 best_post_div = post_div; 545 best_post_div = post_div;
542 best_ref_div = ref_div; 546 best_ref_div = ref_div;
543 best_feedback_div = feedback_div; 547 best_feedback_div = feedback_div;
@@ -573,8 +577,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
573 uint32_t *fb_div_p, 577 uint32_t *fb_div_p,
574 uint32_t *frac_fb_div_p, 578 uint32_t *frac_fb_div_p,
575 uint32_t *ref_div_p, 579 uint32_t *ref_div_p,
576 uint32_t *post_div_p, 580 uint32_t *post_div_p)
577 int flags)
578{ 581{
579 fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq; 582 fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq;
580 fixed20_12 pll_out_max, pll_out_min; 583 fixed20_12 pll_out_max, pll_out_min;
@@ -715,7 +718,11 @@ radeon_user_framebuffer_create(struct drm_device *dev,
715 struct drm_gem_object *obj; 718 struct drm_gem_object *obj;
716 719
717 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle); 720 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
718 721 if (obj == NULL) {
722 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
723 "can't create framebuffer\n", mode_cmd->handle);
724 return NULL;
725 }
719 return radeon_framebuffer_create(dev, mode_cmd, obj); 726 return radeon_framebuffer_create(dev, mode_cmd, obj);
720} 727}
721 728
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index cc27485a07ad..b6d8081e1246 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -339,69 +339,6 @@ void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
339 } 339 }
340} 340}
341 341
342/* properly set crtc bpp when using atombios */
343void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
344{
345 struct drm_device *dev = crtc->dev;
346 struct radeon_device *rdev = dev->dev_private;
347 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
348 int format;
349 uint32_t crtc_gen_cntl;
350 uint32_t disp_merge_cntl;
351 uint32_t crtc_pitch;
352
353 switch (crtc->fb->bits_per_pixel) {
354 case 8:
355 format = 2;
356 break;
357 case 15: /* 555 */
358 format = 3;
359 break;
360 case 16: /* 565 */
361 format = 4;
362 break;
363 case 24: /* RGB */
364 format = 5;
365 break;
366 case 32: /* xRGB */
367 format = 6;
368 break;
369 default:
370 return;
371 }
372
373 crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
374 ((crtc->fb->bits_per_pixel * 8) - 1)) /
375 (crtc->fb->bits_per_pixel * 8));
376 crtc_pitch |= crtc_pitch << 16;
377
378 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
379
380 switch (radeon_crtc->crtc_id) {
381 case 0:
382 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
383 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
384 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
385
386 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
387 crtc_gen_cntl |= (format << 8);
388 crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
389 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
390 break;
391 case 1:
392 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
393 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
394 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
395
396 crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
397 crtc_gen_cntl |= (format << 8);
398 WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
399 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
400 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
401 break;
402 }
403}
404
405int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 342int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
406 struct drm_framebuffer *old_fb) 343 struct drm_framebuffer *old_fb)
407{ 344{
@@ -755,7 +692,6 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
755 uint32_t post_divider = 0; 692 uint32_t post_divider = 0;
756 uint32_t freq = 0; 693 uint32_t freq = 0;
757 uint8_t pll_gain; 694 uint8_t pll_gain;
758 int pll_flags = RADEON_PLL_LEGACY;
759 bool use_bios_divs = false; 695 bool use_bios_divs = false;
760 /* PLL registers */ 696 /* PLL registers */
761 uint32_t pll_ref_div = 0; 697 uint32_t pll_ref_div = 0;
@@ -789,10 +725,12 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
789 else 725 else
790 pll = &rdev->clock.p1pll; 726 pll = &rdev->clock.p1pll;
791 727
728 pll->flags = RADEON_PLL_LEGACY;
729
792 if (mode->clock > 200000) /* range limits??? */ 730 if (mode->clock > 200000) /* range limits??? */
793 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 731 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
794 else 732 else
795 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 733 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
796 734
797 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 735 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
798 if (encoder->crtc == crtc) { 736 if (encoder->crtc == crtc) {
@@ -804,7 +742,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
804 } 742 }
805 743
806 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 744 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
807 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; 745 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
808 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { 746 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
809 if (!rdev->is_atom_bios) { 747 if (!rdev->is_atom_bios) {
810 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 748 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
@@ -819,7 +757,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
819 } 757 }
820 } 758 }
821 } 759 }
822 pll_flags |= RADEON_PLL_USE_REF_DIV; 760 pll->flags |= RADEON_PLL_USE_REF_DIV;
823 } 761 }
824 } 762 }
825 } 763 }
@@ -829,8 +767,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
829 if (!use_bios_divs) { 767 if (!use_bios_divs) {
830 radeon_compute_pll(pll, mode->clock, 768 radeon_compute_pll(pll, mode->clock,
831 &freq, &feedback_div, &frac_fb_div, 769 &freq, &feedback_div, &frac_fb_div,
832 &reference_div, &post_divider, 770 &reference_div, &post_divider);
833 pll_flags);
834 771
835 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 772 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
836 if (post_div->divider == post_divider) 773 if (post_div->divider == post_divider)
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 91cb041cb40d..96b851f92f4c 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -125,16 +125,24 @@ struct radeon_tmds_pll {
125#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 125#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
126#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 126#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
127#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 127#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
128#define RADEON_PLL_USE_POST_DIV (1 << 12)
128 129
129struct radeon_pll { 130struct radeon_pll {
130 uint16_t reference_freq; 131 /* reference frequency */
131 uint16_t reference_div; 132 uint32_t reference_freq;
133
134 /* fixed dividers */
135 uint32_t reference_div;
136 uint32_t post_div;
137
138 /* pll in/out limits */
132 uint32_t pll_in_min; 139 uint32_t pll_in_min;
133 uint32_t pll_in_max; 140 uint32_t pll_in_max;
134 uint32_t pll_out_min; 141 uint32_t pll_out_min;
135 uint32_t pll_out_max; 142 uint32_t pll_out_max;
136 uint16_t xclk; 143 uint32_t best_vco;
137 144
145 /* divider limits */
138 uint32_t min_ref_div; 146 uint32_t min_ref_div;
139 uint32_t max_ref_div; 147 uint32_t max_ref_div;
140 uint32_t min_post_div; 148 uint32_t min_post_div;
@@ -143,7 +151,12 @@ struct radeon_pll {
143 uint32_t max_feedback_div; 151 uint32_t max_feedback_div;
144 uint32_t min_frac_feedback_div; 152 uint32_t min_frac_feedback_div;
145 uint32_t max_frac_feedback_div; 153 uint32_t max_frac_feedback_div;
146 uint32_t best_vco; 154
155 /* flags for the current clock */
156 uint32_t flags;
157
158 /* pll id */
159 uint32_t id;
147}; 160};
148 161
149struct radeon_i2c_chan { 162struct radeon_i2c_chan {
@@ -417,8 +430,7 @@ extern void radeon_compute_pll(struct radeon_pll *pll,
417 uint32_t *fb_div_p, 430 uint32_t *fb_div_p,
418 uint32_t *frac_fb_div_p, 431 uint32_t *frac_fb_div_p,
419 uint32_t *ref_div_p, 432 uint32_t *ref_div_p,
420 uint32_t *post_div_p, 433 uint32_t *post_div_p);
421 int flags);
422 434
423extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 435extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
424 uint64_t freq, 436 uint64_t freq,
@@ -426,8 +438,7 @@ extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
426 uint32_t *fb_div_p, 438 uint32_t *fb_div_p,
427 uint32_t *frac_fb_div_p, 439 uint32_t *frac_fb_div_p,
428 uint32_t *ref_div_p, 440 uint32_t *ref_div_p,
429 uint32_t *post_div_p, 441 uint32_t *post_div_p);
430 int flags);
431 442
432extern void radeon_setup_encoder_clones(struct drm_device *dev); 443extern void radeon_setup_encoder_clones(struct drm_device *dev);
433 444
@@ -453,7 +464,6 @@ extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
453 464
454extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 465extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
455 struct drm_framebuffer *old_fb); 466 struct drm_framebuffer *old_fb);
456extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc);
457 467
458extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 468extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
459 struct drm_file *file_priv, 469 struct drm_file *file_priv,
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r200 b/drivers/gpu/drm/radeon/reg_srcs/r200
index 6021c8849a16..c29ac434ac9c 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r200
+++ b/drivers/gpu/drm/radeon/reg_srcs/r200
@@ -91,6 +91,8 @@ r200 0x3294
910x22b8 SE_TCL_TEX_CYL_WRAP_CTL 910x22b8 SE_TCL_TEX_CYL_WRAP_CTL
920x22c0 SE_TCL_UCP_VERT_BLEND_CNTL 920x22c0 SE_TCL_UCP_VERT_BLEND_CNTL
930x22c4 SE_TCL_POINT_SPRITE_CNTL 930x22c4 SE_TCL_POINT_SPRITE_CNTL
940x22d0 SE_PVS_CNTL
950x22d4 SE_PVS_CONST_CNTL
940x2648 RE_POINTSIZE 960x2648 RE_POINTSIZE
950x26c0 RE_TOP_LEFT 970x26c0 RE_TOP_LEFT
960x26c4 RE_MISC 980x26c4 RE_MISC
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index eb065bbe1eeb..cf8f2b17d627 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -968,6 +968,7 @@ int rv770_suspend(struct radeon_device *rdev)
968 /* FIXME: we should wait for ring to be empty */ 968 /* FIXME: we should wait for ring to be empty */
969 r700_cp_stop(rdev); 969 r700_cp_stop(rdev);
970 rdev->cp.ready = false; 970 rdev->cp.ready = false;
971 r600_irq_suspend(rdev);
971 r600_wb_disable(rdev); 972 r600_wb_disable(rdev);
972 rv770_pcie_gart_disable(rdev); 973 rv770_pcie_gart_disable(rdev);
973 /* unpin shaders bo */ 974 /* unpin shaders bo */
@@ -1074,13 +1075,14 @@ int rv770_init(struct radeon_device *rdev)
1074 if (rdev->accel_working) { 1075 if (rdev->accel_working) {
1075 r = radeon_ib_pool_init(rdev); 1076 r = radeon_ib_pool_init(rdev);
1076 if (r) { 1077 if (r) {
1077 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); 1078 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1078 rdev->accel_working = false;
1079 }
1080 r = r600_ib_test(rdev);
1081 if (r) {
1082 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1083 rdev->accel_working = false; 1079 rdev->accel_working = false;
1080 } else {
1081 r = r600_ib_test(rdev);
1082 if (r) {
1083 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1084 rdev->accel_working = false;
1085 }
1084 } 1086 }
1085 } 1087 }
1086 return 0; 1088 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 03:09:24 -0500