aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
Diffstat (limited to 'drivers')
-rw-r--r--drivers/ide/Makefile1
-rw-r--r--drivers/ide/ide-dma-sff.c356
-rw-r--r--drivers/ide/ide-dma.c363
3 files changed, 358 insertions, 362 deletions
diff --git a/drivers/ide/Makefile b/drivers/ide/Makefile
index e6e7811812d2..0c30adb115c8 100644
--- a/drivers/ide/Makefile
+++ b/drivers/ide/Makefile
@@ -12,6 +12,7 @@ ide-core-$(CONFIG_IDE_TIMINGS) += ide-timings.o
12ide-core-$(CONFIG_IDE_ATAPI) += ide-atapi.o 12ide-core-$(CONFIG_IDE_ATAPI) += ide-atapi.o
13ide-core-$(CONFIG_BLK_DEV_IDEPCI) += setup-pci.o 13ide-core-$(CONFIG_BLK_DEV_IDEPCI) += setup-pci.o
14ide-core-$(CONFIG_BLK_DEV_IDEDMA) += ide-dma.o 14ide-core-$(CONFIG_BLK_DEV_IDEDMA) += ide-dma.o
15ide-core-$(CONFIG_BLK_DEV_IDEDMA_SFF) += ide-dma-sff.o
15ide-core-$(CONFIG_IDE_PROC_FS) += ide-proc.o 16ide-core-$(CONFIG_IDE_PROC_FS) += ide-proc.o
16ide-core-$(CONFIG_BLK_DEV_IDEACPI) += ide-acpi.o 17ide-core-$(CONFIG_BLK_DEV_IDEACPI) += ide-acpi.o
17 18
diff --git a/drivers/ide/ide-dma-sff.c b/drivers/ide/ide-dma-sff.c
new file mode 100644
index 000000000000..0903782689e9
--- /dev/null
+++ b/drivers/ide/ide-dma-sff.c
@@ -0,0 +1,356 @@
1#include <linux/types.h>
2#include <linux/kernel.h>
3#include <linux/ide.h>
4#include <linux/scatterlist.h>
5#include <linux/dma-mapping.h>
6#include <linux/io.h>
7
8/**
9 * config_drive_for_dma - attempt to activate IDE DMA
10 * @drive: the drive to place in DMA mode
11 *
12 * If the drive supports at least mode 2 DMA or UDMA of any kind
13 * then attempt to place it into DMA mode. Drives that are known to
14 * support DMA but predate the DMA properties or that are known
15 * to have DMA handling bugs are also set up appropriately based
16 * on the good/bad drive lists.
17 */
18
19int config_drive_for_dma(ide_drive_t *drive)
20{
21 ide_hwif_t *hwif = drive->hwif;
22 u16 *id = drive->id;
23
24 if (drive->media != ide_disk) {
25 if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA)
26 return 0;
27 }
28
29 /*
30 * Enable DMA on any drive that has
31 * UltraDMA (mode 0/1/2/3/4/5/6) enabled
32 */
33 if ((id[ATA_ID_FIELD_VALID] & 4) &&
34 ((id[ATA_ID_UDMA_MODES] >> 8) & 0x7f))
35 return 1;
36
37 /*
38 * Enable DMA on any drive that has mode2 DMA
39 * (multi or single) enabled
40 */
41 if (id[ATA_ID_FIELD_VALID] & 2) /* regular DMA */
42 if ((id[ATA_ID_MWDMA_MODES] & 0x404) == 0x404 ||
43 (id[ATA_ID_SWDMA_MODES] & 0x404) == 0x404)
44 return 1;
45
46 /* Consult the list of known "good" drives */
47 if (ide_dma_good_drive(drive))
48 return 1;
49
50 return 0;
51}
52
53/**
54 * ide_dma_host_set - Enable/disable DMA on a host
55 * @drive: drive to control
56 *
57 * Enable/disable DMA on an IDE controller following generic
58 * bus-mastering IDE controller behaviour.
59 */
60
61void ide_dma_host_set(ide_drive_t *drive, int on)
62{
63 ide_hwif_t *hwif = drive->hwif;
64 u8 unit = drive->dn & 1;
65 u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
66
67 if (on)
68 dma_stat |= (1 << (5 + unit));
69 else
70 dma_stat &= ~(1 << (5 + unit));
71
72 if (hwif->host_flags & IDE_HFLAG_MMIO)
73 writeb(dma_stat,
74 (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
75 else
76 outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS);
77}
78EXPORT_SYMBOL_GPL(ide_dma_host_set);
79
80/**
81 * ide_build_dmatable - build IDE DMA table
82 *
83 * ide_build_dmatable() prepares a dma request. We map the command
84 * to get the pci bus addresses of the buffers and then build up
85 * the PRD table that the IDE layer wants to be fed.
86 *
87 * Most chipsets correctly interpret a length of 0x0000 as 64KB,
88 * but at least one (e.g. CS5530) misinterprets it as zero (!).
89 * So we break the 64KB entry into two 32KB entries instead.
90 *
91 * Returns the number of built PRD entries if all went okay,
92 * returns 0 otherwise.
93 *
94 * May also be invoked from trm290.c
95 */
96
97int ide_build_dmatable(ide_drive_t *drive, struct request *rq)
98{
99 ide_hwif_t *hwif = drive->hwif;
100 __le32 *table = (__le32 *)hwif->dmatable_cpu;
101 unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0;
102 unsigned int count = 0;
103 int i;
104 struct scatterlist *sg;
105
106 hwif->sg_nents = ide_build_sglist(drive, rq);
107 if (hwif->sg_nents == 0)
108 return 0;
109
110 for_each_sg(hwif->sg_table, sg, hwif->sg_nents, i) {
111 u32 cur_addr, cur_len, xcount, bcount;
112
113 cur_addr = sg_dma_address(sg);
114 cur_len = sg_dma_len(sg);
115
116 /*
117 * Fill in the dma table, without crossing any 64kB boundaries.
118 * Most hardware requires 16-bit alignment of all blocks,
119 * but the trm290 requires 32-bit alignment.
120 */
121
122 while (cur_len) {
123 if (count++ >= PRD_ENTRIES)
124 goto use_pio_instead;
125
126 bcount = 0x10000 - (cur_addr & 0xffff);
127 if (bcount > cur_len)
128 bcount = cur_len;
129 *table++ = cpu_to_le32(cur_addr);
130 xcount = bcount & 0xffff;
131 if (is_trm290)
132 xcount = ((xcount >> 2) - 1) << 16;
133 if (xcount == 0x0000) {
134 if (count++ >= PRD_ENTRIES)
135 goto use_pio_instead;
136 *table++ = cpu_to_le32(0x8000);
137 *table++ = cpu_to_le32(cur_addr + 0x8000);
138 xcount = 0x8000;
139 }
140 *table++ = cpu_to_le32(xcount);
141 cur_addr += bcount;
142 cur_len -= bcount;
143 }
144 }
145
146 if (count) {
147 if (!is_trm290)
148 *--table |= cpu_to_le32(0x80000000);
149 return count;
150 }
151
152use_pio_instead:
153 printk(KERN_ERR "%s: %s\n", drive->name,
154 count ? "DMA table too small" : "empty DMA table?");
155
156 ide_destroy_dmatable(drive);
157
158 return 0; /* revert to PIO for this request */
159}
160EXPORT_SYMBOL_GPL(ide_build_dmatable);
161
162/**
163 * ide_dma_setup - begin a DMA phase
164 * @drive: target device
165 *
166 * Build an IDE DMA PRD (IDE speak for scatter gather table)
167 * and then set up the DMA transfer registers for a device
168 * that follows generic IDE PCI DMA behaviour. Controllers can
169 * override this function if they need to
170 *
171 * Returns 0 on success. If a PIO fallback is required then 1
172 * is returned.
173 */
174
175int ide_dma_setup(ide_drive_t *drive)
176{
177 ide_hwif_t *hwif = drive->hwif;
178 struct request *rq = hwif->hwgroup->rq;
179 unsigned int reading;
180 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
181 u8 dma_stat;
182
183 if (rq_data_dir(rq))
184 reading = 0;
185 else
186 reading = 1 << 3;
187
188 /* fall back to pio! */
189 if (!ide_build_dmatable(drive, rq)) {
190 ide_map_sg(drive, rq);
191 return 1;
192 }
193
194 /* PRD table */
195 if (hwif->host_flags & IDE_HFLAG_MMIO)
196 writel(hwif->dmatable_dma,
197 (void __iomem *)(hwif->dma_base + ATA_DMA_TABLE_OFS));
198 else
199 outl(hwif->dmatable_dma, hwif->dma_base + ATA_DMA_TABLE_OFS);
200
201 /* specify r/w */
202 if (mmio)
203 writeb(reading, (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
204 else
205 outb(reading, hwif->dma_base + ATA_DMA_CMD);
206
207 /* read DMA status for INTR & ERROR flags */
208 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
209
210 /* clear INTR & ERROR flags */
211 if (mmio)
212 writeb(dma_stat | 6,
213 (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
214 else
215 outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
216
217 drive->waiting_for_dma = 1;
218 return 0;
219}
220EXPORT_SYMBOL_GPL(ide_dma_setup);
221
222/**
223 * dma_timer_expiry - handle a DMA timeout
224 * @drive: Drive that timed out
225 *
226 * An IDE DMA transfer timed out. In the event of an error we ask
227 * the driver to resolve the problem, if a DMA transfer is still
228 * in progress we continue to wait (arguably we need to add a
229 * secondary 'I don't care what the drive thinks' timeout here)
230 * Finally if we have an interrupt we let it complete the I/O.
231 * But only one time - we clear expiry and if it's still not
232 * completed after WAIT_CMD, we error and retry in PIO.
233 * This can occur if an interrupt is lost or due to hang or bugs.
234 */
235
236static int dma_timer_expiry(ide_drive_t *drive)
237{
238 ide_hwif_t *hwif = drive->hwif;
239 u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
240
241 printk(KERN_WARNING "%s: %s: DMA status (0x%02x)\n",
242 drive->name, __func__, dma_stat);
243
244 if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */
245 return WAIT_CMD;
246
247 hwif->hwgroup->expiry = NULL; /* one free ride for now */
248
249 /* 1 dmaing, 2 error, 4 intr */
250 if (dma_stat & 2) /* ERROR */
251 return -1;
252
253 if (dma_stat & 1) /* DMAing */
254 return WAIT_CMD;
255
256 if (dma_stat & 4) /* Got an Interrupt */
257 return WAIT_CMD;
258
259 return 0; /* Status is unknown -- reset the bus */
260}
261
262void ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
263{
264 /* issue cmd to drive */
265 ide_execute_command(drive, command, &ide_dma_intr, 2 * WAIT_CMD,
266 dma_timer_expiry);
267}
268EXPORT_SYMBOL_GPL(ide_dma_exec_cmd);
269
270void ide_dma_start(ide_drive_t *drive)
271{
272 ide_hwif_t *hwif = drive->hwif;
273 u8 dma_cmd;
274
275 /* Note that this is done *after* the cmd has
276 * been issued to the drive, as per the BM-IDE spec.
277 * The Promise Ultra33 doesn't work correctly when
278 * we do this part before issuing the drive cmd.
279 */
280 if (hwif->host_flags & IDE_HFLAG_MMIO) {
281 dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
282 /* start DMA */
283 writeb(dma_cmd | 1,
284 (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
285 } else {
286 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
287 outb(dma_cmd | 1, hwif->dma_base + ATA_DMA_CMD);
288 }
289
290 wmb();
291}
292EXPORT_SYMBOL_GPL(ide_dma_start);
293
294/* returns 1 on error, 0 otherwise */
295int ide_dma_end(ide_drive_t *drive)
296{
297 ide_hwif_t *hwif = drive->hwif;
298 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
299 u8 dma_stat = 0, dma_cmd = 0;
300
301 drive->waiting_for_dma = 0;
302
303 if (mmio) {
304 /* get DMA command mode */
305 dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
306 /* stop DMA */
307 writeb(dma_cmd & ~1,
308 (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
309 } else {
310 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
311 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
312 }
313
314 /* get DMA status */
315 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
316
317 if (mmio)
318 /* clear the INTR & ERROR bits */
319 writeb(dma_stat | 6,
320 (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
321 else
322 outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
323
324 /* purge DMA mappings */
325 ide_destroy_dmatable(drive);
326 /* verify good DMA status */
327 wmb();
328 return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
329}
330EXPORT_SYMBOL_GPL(ide_dma_end);
331
332/* returns 1 if dma irq issued, 0 otherwise */
333int ide_dma_test_irq(ide_drive_t *drive)
334{
335 ide_hwif_t *hwif = drive->hwif;
336 u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
337
338 /* return 1 if INTR asserted */
339 if ((dma_stat & 4) == 4)
340 return 1;
341
342 return 0;
343}
344EXPORT_SYMBOL_GPL(ide_dma_test_irq);
345
346const struct ide_dma_ops sff_dma_ops = {
347 .dma_host_set = ide_dma_host_set,
348 .dma_setup = ide_dma_setup,
349 .dma_exec_cmd = ide_dma_exec_cmd,
350 .dma_start = ide_dma_start,
351 .dma_end = ide_dma_end,
352 .dma_test_irq = ide_dma_test_irq,
353 .dma_timeout = ide_dma_timeout,
354 .dma_lost_irq = ide_dma_lost_irq,
355};
356EXPORT_SYMBOL_GPL(sff_dma_ops);
diff --git a/drivers/ide/ide-dma.c b/drivers/ide/ide-dma.c
index d935a6ec022f..fffd11717b2d 100644
--- a/drivers/ide/ide-dma.c
+++ b/drivers/ide/ide-dma.c
@@ -33,7 +33,6 @@
33#include <linux/ide.h> 33#include <linux/ide.h>
34#include <linux/scatterlist.h> 34#include <linux/scatterlist.h>
35#include <linux/dma-mapping.h> 35#include <linux/dma-mapping.h>
36#include <linux/io.h>
37 36
38static const struct drive_list_entry drive_whitelist[] = { 37static const struct drive_list_entry drive_whitelist[] = {
39 { "Micropolis 2112A" , NULL }, 38 { "Micropolis 2112A" , NULL },
@@ -109,7 +108,7 @@ ide_startstop_t ide_dma_intr(ide_drive_t *drive)
109} 108}
110EXPORT_SYMBOL_GPL(ide_dma_intr); 109EXPORT_SYMBOL_GPL(ide_dma_intr);
111 110
112static int ide_dma_good_drive(ide_drive_t *drive) 111int ide_dma_good_drive(ide_drive_t *drive)
113{ 112{
114 return ide_in_drive_list(drive->id, drive_whitelist); 113 return ide_in_drive_list(drive->id, drive_whitelist);
115} 114}
@@ -142,90 +141,6 @@ int ide_build_sglist(ide_drive_t *drive, struct request *rq)
142} 141}
143EXPORT_SYMBOL_GPL(ide_build_sglist); 142EXPORT_SYMBOL_GPL(ide_build_sglist);
144 143
145#ifdef CONFIG_BLK_DEV_IDEDMA_SFF
146/**
147 * ide_build_dmatable - build IDE DMA table
148 *
149 * ide_build_dmatable() prepares a dma request. We map the command
150 * to get the pci bus addresses of the buffers and then build up
151 * the PRD table that the IDE layer wants to be fed.
152 *
153 * Most chipsets correctly interpret a length of 0x0000 as 64KB,
154 * but at least one (e.g. CS5530) misinterprets it as zero (!).
155 * So we break the 64KB entry into two 32KB entries instead.
156 *
157 * Returns the number of built PRD entries if all went okay,
158 * returns 0 otherwise.
159 *
160 * May also be invoked from trm290.c
161 */
162
163int ide_build_dmatable(ide_drive_t *drive, struct request *rq)
164{
165 ide_hwif_t *hwif = drive->hwif;
166 __le32 *table = (__le32 *)hwif->dmatable_cpu;
167 unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0;
168 unsigned int count = 0;
169 int i;
170 struct scatterlist *sg;
171
172 hwif->sg_nents = ide_build_sglist(drive, rq);
173 if (hwif->sg_nents == 0)
174 return 0;
175
176 for_each_sg(hwif->sg_table, sg, hwif->sg_nents, i) {
177 u32 cur_addr, cur_len, xcount, bcount;
178
179 cur_addr = sg_dma_address(sg);
180 cur_len = sg_dma_len(sg);
181
182 /*
183 * Fill in the dma table, without crossing any 64kB boundaries.
184 * Most hardware requires 16-bit alignment of all blocks,
185 * but the trm290 requires 32-bit alignment.
186 */
187
188 while (cur_len) {
189 if (count++ >= PRD_ENTRIES)
190 goto use_pio_instead;
191
192 bcount = 0x10000 - (cur_addr & 0xffff);
193 if (bcount > cur_len)
194 bcount = cur_len;
195 *table++ = cpu_to_le32(cur_addr);
196 xcount = bcount & 0xffff;
197 if (is_trm290)
198 xcount = ((xcount >> 2) - 1) << 16;
199 if (xcount == 0x0000) {
200 if (count++ >= PRD_ENTRIES)
201 goto use_pio_instead;
202 *table++ = cpu_to_le32(0x8000);
203 *table++ = cpu_to_le32(cur_addr + 0x8000);
204 xcount = 0x8000;
205 }
206 *table++ = cpu_to_le32(xcount);
207 cur_addr += bcount;
208 cur_len -= bcount;
209 }
210 }
211
212 if (count) {
213 if (!is_trm290)
214 *--table |= cpu_to_le32(0x80000000);
215 return count;
216 }
217
218use_pio_instead:
219 printk(KERN_ERR "%s: %s\n", drive->name,
220 count ? "DMA table too small" : "empty DMA table?");
221
222 ide_destroy_dmatable(drive);
223
224 return 0; /* revert to PIO for this request */
225}
226EXPORT_SYMBOL_GPL(ide_build_dmatable);
227#endif
228
229/** 144/**
230 * ide_destroy_dmatable - clean up DMA mapping 145 * ide_destroy_dmatable - clean up DMA mapping
231 * @drive: The drive to unmap 146 * @drive: The drive to unmap
@@ -246,120 +161,6 @@ void ide_destroy_dmatable(ide_drive_t *drive)
246} 161}
247EXPORT_SYMBOL_GPL(ide_destroy_dmatable); 162EXPORT_SYMBOL_GPL(ide_destroy_dmatable);
248 163
249#ifdef CONFIG_BLK_DEV_IDEDMA_SFF
250/**
251 * config_drive_for_dma - attempt to activate IDE DMA
252 * @drive: the drive to place in DMA mode
253 *
254 * If the drive supports at least mode 2 DMA or UDMA of any kind
255 * then attempt to place it into DMA mode. Drives that are known to
256 * support DMA but predate the DMA properties or that are known
257 * to have DMA handling bugs are also set up appropriately based
258 * on the good/bad drive lists.
259 */
260
261static int config_drive_for_dma(ide_drive_t *drive)
262{
263 ide_hwif_t *hwif = drive->hwif;
264 u16 *id = drive->id;
265
266 if (drive->media != ide_disk) {
267 if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA)
268 return 0;
269 }
270
271 /*
272 * Enable DMA on any drive that has
273 * UltraDMA (mode 0/1/2/3/4/5/6) enabled
274 */
275 if ((id[ATA_ID_FIELD_VALID] & 4) &&
276 ((id[ATA_ID_UDMA_MODES] >> 8) & 0x7f))
277 return 1;
278
279 /*
280 * Enable DMA on any drive that has mode2 DMA
281 * (multi or single) enabled
282 */
283 if (id[ATA_ID_FIELD_VALID] & 2) /* regular DMA */
284 if ((id[ATA_ID_MWDMA_MODES] & 0x404) == 0x404 ||
285 (id[ATA_ID_SWDMA_MODES] & 0x404) == 0x404)
286 return 1;
287
288 /* Consult the list of known "good" drives */
289 if (ide_dma_good_drive(drive))
290 return 1;
291
292 return 0;
293}
294
295/**
296 * dma_timer_expiry - handle a DMA timeout
297 * @drive: Drive that timed out
298 *
299 * An IDE DMA transfer timed out. In the event of an error we ask
300 * the driver to resolve the problem, if a DMA transfer is still
301 * in progress we continue to wait (arguably we need to add a
302 * secondary 'I don't care what the drive thinks' timeout here)
303 * Finally if we have an interrupt we let it complete the I/O.
304 * But only one time - we clear expiry and if it's still not
305 * completed after WAIT_CMD, we error and retry in PIO.
306 * This can occur if an interrupt is lost or due to hang or bugs.
307 */
308
309static int dma_timer_expiry(ide_drive_t *drive)
310{
311 ide_hwif_t *hwif = drive->hwif;
312 u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
313
314 printk(KERN_WARNING "%s: %s: DMA status (0x%02x)\n",
315 drive->name, __func__, dma_stat);
316
317 if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */
318 return WAIT_CMD;
319
320 hwif->hwgroup->expiry = NULL; /* one free ride for now */
321
322 /* 1 dmaing, 2 error, 4 intr */
323 if (dma_stat & 2) /* ERROR */
324 return -1;
325
326 if (dma_stat & 1) /* DMAing */
327 return WAIT_CMD;
328
329 if (dma_stat & 4) /* Got an Interrupt */
330 return WAIT_CMD;
331
332 return 0; /* Status is unknown -- reset the bus */
333}
334
335/**
336 * ide_dma_host_set - Enable/disable DMA on a host
337 * @drive: drive to control
338 *
339 * Enable/disable DMA on an IDE controller following generic
340 * bus-mastering IDE controller behaviour.
341 */
342
343void ide_dma_host_set(ide_drive_t *drive, int on)
344{
345 ide_hwif_t *hwif = drive->hwif;
346 u8 unit = drive->dn & 1;
347 u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
348
349 if (on)
350 dma_stat |= (1 << (5 + unit));
351 else
352 dma_stat &= ~(1 << (5 + unit));
353
354 if (hwif->host_flags & IDE_HFLAG_MMIO)
355 writeb(dma_stat,
356 (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
357 else
358 outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS);
359}
360EXPORT_SYMBOL_GPL(ide_dma_host_set);
361#endif /* CONFIG_BLK_DEV_IDEDMA_SFF */
362
363/** 164/**
364 * ide_dma_off_quietly - Generic DMA kill 165 * ide_dma_off_quietly - Generic DMA kill
365 * @drive: drive to control 166 * @drive: drive to control
@@ -406,154 +207,6 @@ void ide_dma_on(ide_drive_t *drive)
406 drive->hwif->dma_ops->dma_host_set(drive, 1); 207 drive->hwif->dma_ops->dma_host_set(drive, 1);
407} 208}
408 209
409#ifdef CONFIG_BLK_DEV_IDEDMA_SFF
410/**
411 * ide_dma_setup - begin a DMA phase
412 * @drive: target device
413 *
414 * Build an IDE DMA PRD (IDE speak for scatter gather table)
415 * and then set up the DMA transfer registers for a device
416 * that follows generic IDE PCI DMA behaviour. Controllers can
417 * override this function if they need to
418 *
419 * Returns 0 on success. If a PIO fallback is required then 1
420 * is returned.
421 */
422
423int ide_dma_setup(ide_drive_t *drive)
424{
425 ide_hwif_t *hwif = drive->hwif;
426 struct request *rq = hwif->hwgroup->rq;
427 unsigned int reading;
428 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
429 u8 dma_stat;
430
431 if (rq_data_dir(rq))
432 reading = 0;
433 else
434 reading = 1 << 3;
435
436 /* fall back to pio! */
437 if (!ide_build_dmatable(drive, rq)) {
438 ide_map_sg(drive, rq);
439 return 1;
440 }
441
442 /* PRD table */
443 if (hwif->host_flags & IDE_HFLAG_MMIO)
444 writel(hwif->dmatable_dma,
445 (void __iomem *)(hwif->dma_base + ATA_DMA_TABLE_OFS));
446 else
447 outl(hwif->dmatable_dma, hwif->dma_base + ATA_DMA_TABLE_OFS);
448
449 /* specify r/w */
450 if (mmio)
451 writeb(reading, (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
452 else
453 outb(reading, hwif->dma_base + ATA_DMA_CMD);
454
455 /* read DMA status for INTR & ERROR flags */
456 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
457
458 /* clear INTR & ERROR flags */
459 if (mmio)
460 writeb(dma_stat | 6,
461 (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
462 else
463 outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
464
465 drive->waiting_for_dma = 1;
466 return 0;
467}
468EXPORT_SYMBOL_GPL(ide_dma_setup);
469
470void ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
471{
472 /* issue cmd to drive */
473 ide_execute_command(drive, command, &ide_dma_intr, 2 * WAIT_CMD,
474 dma_timer_expiry);
475}
476EXPORT_SYMBOL_GPL(ide_dma_exec_cmd);
477
478void ide_dma_start(ide_drive_t *drive)
479{
480 ide_hwif_t *hwif = drive->hwif;
481 u8 dma_cmd;
482
483 /* Note that this is done *after* the cmd has
484 * been issued to the drive, as per the BM-IDE spec.
485 * The Promise Ultra33 doesn't work correctly when
486 * we do this part before issuing the drive cmd.
487 */
488 if (hwif->host_flags & IDE_HFLAG_MMIO) {
489 dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
490 /* start DMA */
491 writeb(dma_cmd | 1,
492 (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
493 } else {
494 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
495 outb(dma_cmd | 1, hwif->dma_base + ATA_DMA_CMD);
496 }
497
498 wmb();
499}
500EXPORT_SYMBOL_GPL(ide_dma_start);
501
502/* returns 1 on error, 0 otherwise */
503int ide_dma_end(ide_drive_t *drive)
504{
505 ide_hwif_t *hwif = drive->hwif;
506 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
507 u8 dma_stat = 0, dma_cmd = 0;
508
509 drive->waiting_for_dma = 0;
510
511 if (mmio) {
512 /* get DMA command mode */
513 dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
514 /* stop DMA */
515 writeb(dma_cmd & ~1,
516 (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
517 } else {
518 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
519 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
520 }
521
522 /* get DMA status */
523 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
524
525 if (mmio)
526 /* clear the INTR & ERROR bits */
527 writeb(dma_stat | 6,
528 (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
529 else
530 outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
531
532 /* purge DMA mappings */
533 ide_destroy_dmatable(drive);
534 /* verify good DMA status */
535 wmb();
536 return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
537}
538EXPORT_SYMBOL_GPL(ide_dma_end);
539
540/* returns 1 if dma irq issued, 0 otherwise */
541int ide_dma_test_irq(ide_drive_t *drive)
542{
543 ide_hwif_t *hwif = drive->hwif;
544 u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
545
546 /* return 1 if INTR asserted */
547 if ((dma_stat & 4) == 4)
548 return 1;
549
550 return 0;
551}
552EXPORT_SYMBOL_GPL(ide_dma_test_irq);
553#else
554static inline int config_drive_for_dma(ide_drive_t *drive) { return 0; }
555#endif /* CONFIG_BLK_DEV_IDEDMA_SFF */
556
557int __ide_dma_bad_drive(ide_drive_t *drive) 210int __ide_dma_bad_drive(ide_drive_t *drive)
558{ 211{
559 u16 *id = drive->id; 212 u16 *id = drive->id;
@@ -846,17 +499,3 @@ int ide_allocate_dma_engine(ide_hwif_t *hwif)
846 return 0; 499 return 0;
847} 500}
848EXPORT_SYMBOL_GPL(ide_allocate_dma_engine); 501EXPORT_SYMBOL_GPL(ide_allocate_dma_engine);
849
850#ifdef CONFIG_BLK_DEV_IDEDMA_SFF
851const struct ide_dma_ops sff_dma_ops = {
852 .dma_host_set = ide_dma_host_set,
853 .dma_setup = ide_dma_setup,
854 .dma_exec_cmd = ide_dma_exec_cmd,
855 .dma_start = ide_dma_start,
856 .dma_end = ide_dma_end,
857 .dma_test_irq = ide_dma_test_irq,
858 .dma_timeout = ide_dma_timeout,
859 .dma_lost_irq = ide_dma_lost_irq,
860};
861EXPORT_SYMBOL_GPL(sff_dma_ops);
862#endif /* CONFIG_BLK_DEV_IDEDMA_SFF */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 01:57:52 -0500