diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/wan/Kconfig | 7 | ||||
-rw-r--r-- | drivers/net/wan/Makefile | 1 | ||||
-rw-r--r-- | drivers/net/wan/ixp4xx_hss.c | 1357 |
3 files changed, 1365 insertions, 0 deletions
diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig index 0725161aa27c..d08ce6a264cb 100644 --- a/drivers/net/wan/Kconfig +++ b/drivers/net/wan/Kconfig | |||
@@ -335,6 +335,13 @@ config DSCC4_PCI_RST | |||
335 | 335 | ||
336 | Say Y if your card supports this feature. | 336 | Say Y if your card supports this feature. |
337 | 337 | ||
338 | config IXP4XX_HSS | ||
339 | tristate "Intel IXP4xx HSS (synchronous serial port) support" | ||
340 | depends on HDLC && ARM && ARCH_IXP4XX && IXP4XX_NPE && IXP4XX_QMGR | ||
341 | help | ||
342 | Say Y here if you want to use built-in HSS ports | ||
343 | on IXP4xx processor. | ||
344 | |||
338 | config DLCI | 345 | config DLCI |
339 | tristate "Frame Relay DLCI support" | 346 | tristate "Frame Relay DLCI support" |
340 | ---help--- | 347 | ---help--- |
diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile index cec16818a130..19d14bc28356 100644 --- a/drivers/net/wan/Makefile +++ b/drivers/net/wan/Makefile | |||
@@ -41,6 +41,7 @@ obj-$(CONFIG_C101) += c101.o | |||
41 | obj-$(CONFIG_WANXL) += wanxl.o | 41 | obj-$(CONFIG_WANXL) += wanxl.o |
42 | obj-$(CONFIG_PCI200SYN) += pci200syn.o | 42 | obj-$(CONFIG_PCI200SYN) += pci200syn.o |
43 | obj-$(CONFIG_PC300TOO) += pc300too.o | 43 | obj-$(CONFIG_PC300TOO) += pc300too.o |
44 | obj-$(CONFIG_IXP4XX_HSS) += ixp4xx_hss.o | ||
44 | 45 | ||
45 | clean-files := wanxlfw.inc | 46 | clean-files := wanxlfw.inc |
46 | $(obj)/wanxl.o: $(obj)/wanxlfw.inc | 47 | $(obj)/wanxl.o: $(obj)/wanxlfw.inc |
diff --git a/drivers/net/wan/ixp4xx_hss.c b/drivers/net/wan/ixp4xx_hss.c new file mode 100644 index 000000000000..fa3ce81f4cfc --- /dev/null +++ b/drivers/net/wan/ixp4xx_hss.c | |||
@@ -0,0 +1,1357 @@ | |||
1 | /* | ||
2 | * Intel IXP4xx HSS (synchronous serial port) driver for Linux | ||
3 | * | ||
4 | * Copyright (C) 2007-2008 Krzysztof HaĆasa <khc@pm.waw.pl> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of version 2 of the GNU General Public License | ||
8 | * as published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #include <linux/bitops.h> | ||
12 | #include <linux/cdev.h> | ||
13 | #include <linux/dma-mapping.h> | ||
14 | #include <linux/dmapool.h> | ||
15 | #include <linux/fs.h> | ||
16 | #include <linux/hdlc.h> | ||
17 | #include <linux/io.h> | ||
18 | #include <linux/kernel.h> | ||
19 | #include <linux/platform_device.h> | ||
20 | #include <linux/poll.h> | ||
21 | #include <mach/npe.h> | ||
22 | #include <mach/qmgr.h> | ||
23 | |||
24 | #define DEBUG_QUEUES 0 | ||
25 | #define DEBUG_DESC 0 | ||
26 | #define DEBUG_RX 0 | ||
27 | #define DEBUG_TX 0 | ||
28 | #define DEBUG_PKT_BYTES 0 | ||
29 | #define DEBUG_CLOSE 0 | ||
30 | |||
31 | #define DRV_NAME "ixp4xx_hss" | ||
32 | |||
33 | #define PKT_EXTRA_FLAGS 0 /* orig 1 */ | ||
34 | #define PKT_NUM_PIPES 1 /* 1, 2 or 4 */ | ||
35 | #define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */ | ||
36 | |||
37 | #define RX_DESCS 16 /* also length of all RX queues */ | ||
38 | #define TX_DESCS 16 /* also length of all TX queues */ | ||
39 | |||
40 | #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) | ||
41 | #define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */ | ||
42 | #define MAX_CLOSE_WAIT 1000 /* microseconds */ | ||
43 | #define HSS_COUNT 2 | ||
44 | #define FRAME_SIZE 256 /* doesn't matter at this point */ | ||
45 | #define FRAME_OFFSET 0 | ||
46 | #define MAX_CHANNELS (FRAME_SIZE / 8) | ||
47 | |||
48 | #define NAPI_WEIGHT 16 | ||
49 | |||
50 | /* Queue IDs */ | ||
51 | #define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */ | ||
52 | #define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */ | ||
53 | #define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */ | ||
54 | #define HSS0_PKT_TX1_QUEUE 15 | ||
55 | #define HSS0_PKT_TX2_QUEUE 16 | ||
56 | #define HSS0_PKT_TX3_QUEUE 17 | ||
57 | #define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */ | ||
58 | #define HSS0_PKT_RXFREE1_QUEUE 19 | ||
59 | #define HSS0_PKT_RXFREE2_QUEUE 20 | ||
60 | #define HSS0_PKT_RXFREE3_QUEUE 21 | ||
61 | #define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */ | ||
62 | |||
63 | #define HSS1_CHL_RXTRIG_QUEUE 10 | ||
64 | #define HSS1_PKT_RX_QUEUE 0 | ||
65 | #define HSS1_PKT_TX0_QUEUE 5 | ||
66 | #define HSS1_PKT_TX1_QUEUE 6 | ||
67 | #define HSS1_PKT_TX2_QUEUE 7 | ||
68 | #define HSS1_PKT_TX3_QUEUE 8 | ||
69 | #define HSS1_PKT_RXFREE0_QUEUE 1 | ||
70 | #define HSS1_PKT_RXFREE1_QUEUE 2 | ||
71 | #define HSS1_PKT_RXFREE2_QUEUE 3 | ||
72 | #define HSS1_PKT_RXFREE3_QUEUE 4 | ||
73 | #define HSS1_PKT_TXDONE_QUEUE 9 | ||
74 | |||
75 | #define NPE_PKT_MODE_HDLC 0 | ||
76 | #define NPE_PKT_MODE_RAW 1 | ||
77 | #define NPE_PKT_MODE_56KMODE 2 | ||
78 | #define NPE_PKT_MODE_56KENDIAN_MSB 4 | ||
79 | |||
80 | /* PKT_PIPE_HDLC_CFG_WRITE flags */ | ||
81 | #define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */ | ||
82 | #define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */ | ||
83 | #define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */ | ||
84 | |||
85 | |||
86 | /* hss_config, PCRs */ | ||
87 | /* Frame sync sampling, default = active low */ | ||
88 | #define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000 | ||
89 | #define PCR_FRM_SYNC_FALLINGEDGE 0x80000000 | ||
90 | #define PCR_FRM_SYNC_RISINGEDGE 0xC0000000 | ||
91 | |||
92 | /* Frame sync pin: input (default) or output generated off a given clk edge */ | ||
93 | #define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000 | ||
94 | #define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000 | ||
95 | |||
96 | /* Frame and data clock sampling on edge, default = falling */ | ||
97 | #define PCR_FCLK_EDGE_RISING 0x08000000 | ||
98 | #define PCR_DCLK_EDGE_RISING 0x04000000 | ||
99 | |||
100 | /* Clock direction, default = input */ | ||
101 | #define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000 | ||
102 | |||
103 | /* Generate/Receive frame pulses, default = enabled */ | ||
104 | #define PCR_FRM_PULSE_DISABLED 0x01000000 | ||
105 | |||
106 | /* Data rate is full (default) or half the configured clk speed */ | ||
107 | #define PCR_HALF_CLK_RATE 0x00200000 | ||
108 | |||
109 | /* Invert data between NPE and HSS FIFOs? (default = no) */ | ||
110 | #define PCR_DATA_POLARITY_INVERT 0x00100000 | ||
111 | |||
112 | /* TX/RX endianness, default = LSB */ | ||
113 | #define PCR_MSB_ENDIAN 0x00080000 | ||
114 | |||
115 | /* Normal (default) / open drain mode (TX only) */ | ||
116 | #define PCR_TX_PINS_OPEN_DRAIN 0x00040000 | ||
117 | |||
118 | /* No framing bit transmitted and expected on RX? (default = framing bit) */ | ||
119 | #define PCR_SOF_NO_FBIT 0x00020000 | ||
120 | |||
121 | /* Drive data pins? */ | ||
122 | #define PCR_TX_DATA_ENABLE 0x00010000 | ||
123 | |||
124 | /* Voice 56k type: drive the data pins low (default), high, high Z */ | ||
125 | #define PCR_TX_V56K_HIGH 0x00002000 | ||
126 | #define PCR_TX_V56K_HIGH_IMP 0x00004000 | ||
127 | |||
128 | /* Unassigned type: drive the data pins low (default), high, high Z */ | ||
129 | #define PCR_TX_UNASS_HIGH 0x00000800 | ||
130 | #define PCR_TX_UNASS_HIGH_IMP 0x00001000 | ||
131 | |||
132 | /* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */ | ||
133 | #define PCR_TX_FB_HIGH_IMP 0x00000400 | ||
134 | |||
135 | /* 56k data endiannes - which bit unused: high (default) or low */ | ||
136 | #define PCR_TX_56KE_BIT_0_UNUSED 0x00000200 | ||
137 | |||
138 | /* 56k data transmission type: 32/8 bit data (default) or 56K data */ | ||
139 | #define PCR_TX_56KS_56K_DATA 0x00000100 | ||
140 | |||
141 | /* hss_config, cCR */ | ||
142 | /* Number of packetized clients, default = 1 */ | ||
143 | #define CCR_NPE_HFIFO_2_HDLC 0x04000000 | ||
144 | #define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000 | ||
145 | |||
146 | /* default = no loopback */ | ||
147 | #define CCR_LOOPBACK 0x02000000 | ||
148 | |||
149 | /* HSS number, default = 0 (first) */ | ||
150 | #define CCR_SECOND_HSS 0x01000000 | ||
151 | |||
152 | |||
153 | /* hss_config, clkCR: main:10, num:10, denom:12 */ | ||
154 | #define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/ | ||
155 | |||
156 | #define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15) | ||
157 | #define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47) | ||
158 | #define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192) | ||
159 | #define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63) | ||
160 | #define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127) | ||
161 | #define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255) | ||
162 | |||
163 | #define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127) | ||
164 | #define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383) | ||
165 | #define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385) | ||
166 | #define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511) | ||
167 | #define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023) | ||
168 | #define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047) | ||
169 | |||
170 | |||
171 | /* hss_config, LUT entries */ | ||
172 | #define TDMMAP_UNASSIGNED 0 | ||
173 | #define TDMMAP_HDLC 1 /* HDLC - packetized */ | ||
174 | #define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */ | ||
175 | #define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */ | ||
176 | |||
177 | /* offsets into HSS config */ | ||
178 | #define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */ | ||
179 | #define HSS_CONFIG_RX_PCR 0x04 | ||
180 | #define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */ | ||
181 | #define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */ | ||
182 | #define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */ | ||
183 | #define HSS_CONFIG_RX_FCR 0x14 | ||
184 | #define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */ | ||
185 | #define HSS_CONFIG_RX_LUT 0x38 | ||
186 | |||
187 | |||
188 | /* NPE command codes */ | ||
189 | /* writes the ConfigWord value to the location specified by offset */ | ||
190 | #define PORT_CONFIG_WRITE 0x40 | ||
191 | |||
192 | /* triggers the NPE to load the contents of the configuration table */ | ||
193 | #define PORT_CONFIG_LOAD 0x41 | ||
194 | |||
195 | /* triggers the NPE to return an HssErrorReadResponse message */ | ||
196 | #define PORT_ERROR_READ 0x42 | ||
197 | |||
198 | /* triggers the NPE to reset internal status and enable the HssPacketized | ||
199 | operation for the flow specified by pPipe */ | ||
200 | #define PKT_PIPE_FLOW_ENABLE 0x50 | ||
201 | #define PKT_PIPE_FLOW_DISABLE 0x51 | ||
202 | #define PKT_NUM_PIPES_WRITE 0x52 | ||
203 | #define PKT_PIPE_FIFO_SIZEW_WRITE 0x53 | ||
204 | #define PKT_PIPE_HDLC_CFG_WRITE 0x54 | ||
205 | #define PKT_PIPE_IDLE_PATTERN_WRITE 0x55 | ||
206 | #define PKT_PIPE_RX_SIZE_WRITE 0x56 | ||
207 | #define PKT_PIPE_MODE_WRITE 0x57 | ||
208 | |||
209 | /* HDLC packet status values - desc->status */ | ||
210 | #define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */ | ||
211 | #define ERR_HDLC_ALIGN 2 /* HDLC alignment error */ | ||
212 | #define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */ | ||
213 | #define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving | ||
214 | this packet (if buf_len < pkt_len) */ | ||
215 | #define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */ | ||
216 | #define ERR_HDLC_ABORT 6 /* abort sequence received */ | ||
217 | #define ERR_DISCONNECTING 7 /* disconnect is in progress */ | ||
218 | |||
219 | |||
220 | #ifdef __ARMEB__ | ||
221 | typedef struct sk_buff buffer_t; | ||
222 | #define free_buffer dev_kfree_skb | ||
223 | #define free_buffer_irq dev_kfree_skb_irq | ||
224 | #else | ||
225 | typedef void buffer_t; | ||
226 | #define free_buffer kfree | ||
227 | #define free_buffer_irq kfree | ||
228 | #endif | ||
229 | |||
230 | struct port { | ||
231 | struct device *dev; | ||
232 | struct npe *npe; | ||
233 | struct net_device *netdev; | ||
234 | struct napi_struct napi; | ||
235 | struct hss_plat_info *plat; | ||
236 | buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS]; | ||
237 | struct desc *desc_tab; /* coherent */ | ||
238 | u32 desc_tab_phys; | ||
239 | unsigned int id; | ||
240 | unsigned int clock_type, clock_rate, loopback; | ||
241 | unsigned int initialized, carrier; | ||
242 | u8 hdlc_cfg; | ||
243 | }; | ||
244 | |||
245 | /* NPE message structure */ | ||
246 | struct msg { | ||
247 | #ifdef __ARMEB__ | ||
248 | u8 cmd, unused, hss_port, index; | ||
249 | union { | ||
250 | struct { u8 data8a, data8b, data8c, data8d; }; | ||
251 | struct { u16 data16a, data16b; }; | ||
252 | struct { u32 data32; }; | ||
253 | }; | ||
254 | #else | ||
255 | u8 index, hss_port, unused, cmd; | ||
256 | union { | ||
257 | struct { u8 data8d, data8c, data8b, data8a; }; | ||
258 | struct { u16 data16b, data16a; }; | ||
259 | struct { u32 data32; }; | ||
260 | }; | ||
261 | #endif | ||
262 | }; | ||
263 | |||
264 | /* HDLC packet descriptor */ | ||
265 | struct desc { | ||
266 | u32 next; /* pointer to next buffer, unused */ | ||
267 | |||
268 | #ifdef __ARMEB__ | ||
269 | u16 buf_len; /* buffer length */ | ||
270 | u16 pkt_len; /* packet length */ | ||
271 | u32 data; /* pointer to data buffer in RAM */ | ||
272 | u8 status; | ||
273 | u8 error_count; | ||
274 | u16 __reserved; | ||
275 | #else | ||
276 | u16 pkt_len; /* packet length */ | ||
277 | u16 buf_len; /* buffer length */ | ||
278 | u32 data; /* pointer to data buffer in RAM */ | ||
279 | u16 __reserved; | ||
280 | u8 error_count; | ||
281 | u8 status; | ||
282 | #endif | ||
283 | u32 __reserved1[4]; | ||
284 | }; | ||
285 | |||
286 | |||
287 | #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \ | ||
288 | (n) * sizeof(struct desc)) | ||
289 | #define rx_desc_ptr(port, n) (&(port)->desc_tab[n]) | ||
290 | |||
291 | #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \ | ||
292 | ((n) + RX_DESCS) * sizeof(struct desc)) | ||
293 | #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS]) | ||
294 | |||
295 | /***************************************************************************** | ||
296 | * global variables | ||
297 | ****************************************************************************/ | ||
298 | |||
299 | static int ports_open; | ||
300 | static struct dma_pool *dma_pool; | ||
301 | static spinlock_t npe_lock; | ||
302 | |||
303 | static const struct { | ||
304 | int tx, txdone, rx, rxfree; | ||
305 | }queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE, | ||
306 | HSS0_PKT_RXFREE0_QUEUE}, | ||
307 | {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE, | ||
308 | HSS1_PKT_RXFREE0_QUEUE}, | ||
309 | }; | ||
310 | |||
311 | /***************************************************************************** | ||
312 | * utility functions | ||
313 | ****************************************************************************/ | ||
314 | |||
315 | static inline struct port* dev_to_port(struct net_device *dev) | ||
316 | { | ||
317 | return dev_to_hdlc(dev)->priv; | ||
318 | } | ||
319 | |||
320 | #ifndef __ARMEB__ | ||
321 | static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) | ||
322 | { | ||
323 | int i; | ||
324 | for (i = 0; i < cnt; i++) | ||
325 | dest[i] = swab32(src[i]); | ||
326 | } | ||
327 | #endif | ||
328 | |||
329 | /***************************************************************************** | ||
330 | * HSS access | ||
331 | ****************************************************************************/ | ||
332 | |||
333 | static void hss_npe_send(struct port *port, struct msg *msg, const char* what) | ||
334 | { | ||
335 | u32 *val = (u32*)msg; | ||
336 | if (npe_send_message(port->npe, msg, what)) { | ||
337 | printk(KERN_CRIT "HSS-%i: unable to send command [%08X:%08X]" | ||
338 | " to %s\n", port->id, val[0], val[1], | ||
339 | npe_name(port->npe)); | ||
340 | BUG(); | ||
341 | } | ||
342 | } | ||
343 | |||
344 | static void hss_config_set_lut(struct port *port) | ||
345 | { | ||
346 | struct msg msg; | ||
347 | int ch; | ||
348 | |||
349 | memset(&msg, 0, sizeof(msg)); | ||
350 | msg.cmd = PORT_CONFIG_WRITE; | ||
351 | msg.hss_port = port->id; | ||
352 | |||
353 | for (ch = 0; ch < MAX_CHANNELS; ch++) { | ||
354 | msg.data32 >>= 2; | ||
355 | msg.data32 |= TDMMAP_HDLC << 30; | ||
356 | |||
357 | if (ch % 16 == 15) { | ||
358 | msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3); | ||
359 | hss_npe_send(port, &msg, "HSS_SET_TX_LUT"); | ||
360 | |||
361 | msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT; | ||
362 | hss_npe_send(port, &msg, "HSS_SET_RX_LUT"); | ||
363 | } | ||
364 | } | ||
365 | } | ||
366 | |||
367 | static void hss_config(struct port *port) | ||
368 | { | ||
369 | struct msg msg; | ||
370 | |||
371 | memset(&msg, 0, sizeof(msg)); | ||
372 | msg.cmd = PORT_CONFIG_WRITE; | ||
373 | msg.hss_port = port->id; | ||
374 | msg.index = HSS_CONFIG_TX_PCR; | ||
375 | msg.data32 = PCR_FRM_SYNC_OUTPUT_RISING | PCR_MSB_ENDIAN | | ||
376 | PCR_TX_DATA_ENABLE | PCR_SOF_NO_FBIT; | ||
377 | if (port->clock_type == CLOCK_INT) | ||
378 | msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT; | ||
379 | hss_npe_send(port, &msg, "HSS_SET_TX_PCR"); | ||
380 | |||
381 | msg.index = HSS_CONFIG_RX_PCR; | ||
382 | msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING; | ||
383 | hss_npe_send(port, &msg, "HSS_SET_RX_PCR"); | ||
384 | |||
385 | memset(&msg, 0, sizeof(msg)); | ||
386 | msg.cmd = PORT_CONFIG_WRITE; | ||
387 | msg.hss_port = port->id; | ||
388 | msg.index = HSS_CONFIG_CORE_CR; | ||
389 | msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) | | ||
390 | (port->id ? CCR_SECOND_HSS : 0); | ||
391 | hss_npe_send(port, &msg, "HSS_SET_CORE_CR"); | ||
392 | |||
393 | memset(&msg, 0, sizeof(msg)); | ||
394 | msg.cmd = PORT_CONFIG_WRITE; | ||
395 | msg.hss_port = port->id; | ||
396 | msg.index = HSS_CONFIG_CLOCK_CR; | ||
397 | msg.data32 = CLK42X_SPEED_2048KHZ /* FIXME */; | ||
398 | hss_npe_send(port, &msg, "HSS_SET_CLOCK_CR"); | ||
399 | |||
400 | memset(&msg, 0, sizeof(msg)); | ||
401 | msg.cmd = PORT_CONFIG_WRITE; | ||
402 | msg.hss_port = port->id; | ||
403 | msg.index = HSS_CONFIG_TX_FCR; | ||
404 | msg.data16a = FRAME_OFFSET; | ||
405 | msg.data16b = FRAME_SIZE - 1; | ||
406 | hss_npe_send(port, &msg, "HSS_SET_TX_FCR"); | ||
407 | |||
408 | memset(&msg, 0, sizeof(msg)); | ||
409 | msg.cmd = PORT_CONFIG_WRITE; | ||
410 | msg.hss_port = port->id; | ||
411 | msg.index = HSS_CONFIG_RX_FCR; | ||
412 | msg.data16a = FRAME_OFFSET; | ||
413 | msg.data16b = FRAME_SIZE - 1; | ||
414 | hss_npe_send(port, &msg, "HSS_SET_RX_FCR"); | ||
415 | |||
416 | hss_config_set_lut(port); | ||
417 | |||
418 | memset(&msg, 0, sizeof(msg)); | ||
419 | msg.cmd = PORT_CONFIG_LOAD; | ||
420 | msg.hss_port = port->id; | ||
421 | hss_npe_send(port, &msg, "HSS_LOAD_CONFIG"); | ||
422 | |||
423 | if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG") || | ||
424 | /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */ | ||
425 | msg.cmd != PORT_CONFIG_LOAD || msg.data32) { | ||
426 | printk(KERN_CRIT "HSS-%i: HSS_LOAD_CONFIG failed\n", | ||
427 | port->id); | ||
428 | BUG(); | ||
429 | } | ||
430 | |||
431 | /* HDLC may stop working without this - check FIXME */ | ||
432 | npe_recv_message(port->npe, &msg, "FLUSH_IT"); | ||
433 | } | ||
434 | |||
435 | static void hss_set_hdlc_cfg(struct port *port) | ||
436 | { | ||
437 | struct msg msg; | ||
438 | |||
439 | memset(&msg, 0, sizeof(msg)); | ||
440 | msg.cmd = PKT_PIPE_HDLC_CFG_WRITE; | ||
441 | msg.hss_port = port->id; | ||
442 | msg.data8a = port->hdlc_cfg; /* rx_cfg */ | ||
443 | msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */ | ||
444 | hss_npe_send(port, &msg, "HSS_SET_HDLC_CFG"); | ||
445 | } | ||
446 | |||
447 | static u32 hss_get_status(struct port *port) | ||
448 | { | ||
449 | struct msg msg; | ||
450 | |||
451 | memset(&msg, 0, sizeof(msg)); | ||
452 | msg.cmd = PORT_ERROR_READ; | ||
453 | msg.hss_port = port->id; | ||
454 | hss_npe_send(port, &msg, "PORT_ERROR_READ"); | ||
455 | if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ")) { | ||
456 | printk(KERN_CRIT "HSS-%i: unable to read HSS status\n", | ||
457 | port->id); | ||
458 | BUG(); | ||
459 | } | ||
460 | |||
461 | return msg.data32; | ||
462 | } | ||
463 | |||
464 | static void hss_start_hdlc(struct port *port) | ||
465 | { | ||
466 | struct msg msg; | ||
467 | |||
468 | memset(&msg, 0, sizeof(msg)); | ||
469 | msg.cmd = PKT_PIPE_FLOW_ENABLE; | ||
470 | msg.hss_port = port->id; | ||
471 | msg.data32 = 0; | ||
472 | hss_npe_send(port, &msg, "HSS_ENABLE_PKT_PIPE"); | ||
473 | } | ||
474 | |||
475 | static void hss_stop_hdlc(struct port *port) | ||
476 | { | ||
477 | struct msg msg; | ||
478 | |||
479 | memset(&msg, 0, sizeof(msg)); | ||
480 | msg.cmd = PKT_PIPE_FLOW_DISABLE; | ||
481 | msg.hss_port = port->id; | ||
482 | hss_npe_send(port, &msg, "HSS_DISABLE_PKT_PIPE"); | ||
483 | hss_get_status(port); /* make sure it's halted */ | ||
484 | } | ||
485 | |||
486 | static int hss_load_firmware(struct port *port) | ||
487 | { | ||
488 | struct msg msg; | ||
489 | int err; | ||
490 | |||
491 | if (port->initialized) | ||
492 | return 0; | ||
493 | |||
494 | if (!npe_running(port->npe) && | ||
495 | (err = npe_load_firmware(port->npe, npe_name(port->npe), | ||
496 | port->dev))) | ||
497 | return err; | ||
498 | |||
499 | /* HDLC mode configuration */ | ||
500 | memset(&msg, 0, sizeof(msg)); | ||
501 | msg.cmd = PKT_NUM_PIPES_WRITE; | ||
502 | msg.hss_port = port->id; | ||
503 | msg.data8a = PKT_NUM_PIPES; | ||
504 | hss_npe_send(port, &msg, "HSS_SET_PKT_PIPES"); | ||
505 | |||
506 | msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE; | ||
507 | msg.data8a = PKT_PIPE_FIFO_SIZEW; | ||
508 | hss_npe_send(port, &msg, "HSS_SET_PKT_FIFO"); | ||
509 | |||
510 | msg.cmd = PKT_PIPE_MODE_WRITE; | ||
511 | msg.data8a = NPE_PKT_MODE_HDLC; | ||
512 | /* msg.data8b = inv_mask */ | ||
513 | /* msg.data8c = or_mask */ | ||
514 | hss_npe_send(port, &msg, "HSS_SET_PKT_MODE"); | ||
515 | |||
516 | msg.cmd = PKT_PIPE_RX_SIZE_WRITE; | ||
517 | msg.data16a = HDLC_MAX_MRU; /* including CRC */ | ||
518 | hss_npe_send(port, &msg, "HSS_SET_PKT_RX_SIZE"); | ||
519 | |||
520 | msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE; | ||
521 | msg.data32 = 0x7F7F7F7F; /* ??? FIXME */ | ||
522 | hss_npe_send(port, &msg, "HSS_SET_PKT_IDLE"); | ||
523 | |||
524 | port->initialized = 1; | ||
525 | return 0; | ||
526 | } | ||
527 | |||
528 | /***************************************************************************** | ||
529 | * packetized (HDLC) operation | ||
530 | ****************************************************************************/ | ||
531 | |||
532 | static inline void debug_pkt(struct net_device *dev, const char *func, | ||
533 | u8 *data, int len) | ||
534 | { | ||
535 | #if DEBUG_PKT_BYTES | ||
536 | int i; | ||
537 | |||
538 | printk(KERN_DEBUG "%s: %s(%i)", dev->name, func, len); | ||
539 | for (i = 0; i < len; i++) { | ||
540 | if (i >= DEBUG_PKT_BYTES) | ||
541 | break; | ||
542 | printk("%s%02X", !(i % 4) ? " " : "", data[i]); | ||
543 | } | ||
544 | printk("\n"); | ||
545 | #endif | ||
546 | } | ||
547 | |||
548 | |||
549 | static inline void debug_desc(u32 phys, struct desc *desc) | ||
550 | { | ||
551 | #if DEBUG_DESC | ||
552 | printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n", | ||
553 | phys, desc->next, desc->buf_len, desc->pkt_len, | ||
554 | desc->data, desc->status, desc->error_count); | ||
555 | #endif | ||
556 | } | ||
557 | |||
558 | static inline void debug_queue(unsigned int queue, int is_get, u32 phys) | ||
559 | { | ||
560 | #if DEBUG_QUEUES | ||
561 | static struct { | ||
562 | int queue; | ||
563 | char *name; | ||
564 | } names[] = { | ||
565 | { HSS0_PKT_TX0_QUEUE, "TX#0 " }, | ||
566 | { HSS0_PKT_TXDONE_QUEUE, "TX-done#0 " }, | ||
567 | { HSS0_PKT_RX_QUEUE, "RX#0 " }, | ||
568 | { HSS0_PKT_RXFREE0_QUEUE, "RX-free#0 " }, | ||
569 | { HSS1_PKT_TX0_QUEUE, "TX#1 " }, | ||
570 | { HSS1_PKT_TXDONE_QUEUE, "TX-done#1 " }, | ||
571 | { HSS1_PKT_RX_QUEUE, "RX#1 " }, | ||
572 | { HSS1_PKT_RXFREE0_QUEUE, "RX-free#1 " }, | ||
573 | }; | ||
574 | int i; | ||
575 | |||
576 | for (i = 0; i < ARRAY_SIZE(names); i++) | ||
577 | if (names[i].queue == queue) | ||
578 | break; | ||
579 | |||
580 | printk(KERN_DEBUG "Queue %i %s%s %X\n", queue, | ||
581 | i < ARRAY_SIZE(names) ? names[i].name : "", | ||
582 | is_get ? "->" : "<-", phys); | ||
583 | #endif | ||
584 | } | ||
585 | |||
586 | static inline u32 queue_get_entry(unsigned int queue) | ||
587 | { | ||
588 | u32 phys = qmgr_get_entry(queue); | ||
589 | debug_queue(queue, 1, phys); | ||
590 | return phys; | ||
591 | } | ||
592 | |||
593 | static inline int queue_get_desc(unsigned int queue, struct port *port, | ||
594 | int is_tx) | ||
595 | { | ||
596 | u32 phys, tab_phys, n_desc; | ||
597 | struct desc *tab; | ||
598 | |||
599 | if (!(phys = queue_get_entry(queue))) | ||
600 | return -1; | ||
601 | |||
602 | BUG_ON(phys & 0x1F); | ||
603 | tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0); | ||
604 | tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0); | ||
605 | n_desc = (phys - tab_phys) / sizeof(struct desc); | ||
606 | BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS)); | ||
607 | debug_desc(phys, &tab[n_desc]); | ||
608 | BUG_ON(tab[n_desc].next); | ||
609 | return n_desc; | ||
610 | } | ||
611 | |||
612 | static inline void queue_put_desc(unsigned int queue, u32 phys, | ||
613 | struct desc *desc) | ||
614 | { | ||
615 | debug_queue(queue, 0, phys); | ||
616 | debug_desc(phys, desc); | ||
617 | BUG_ON(phys & 0x1F); | ||
618 | qmgr_put_entry(queue, phys); | ||
619 | BUG_ON(qmgr_stat_overflow(queue)); | ||
620 | } | ||
621 | |||
622 | |||
623 | static inline void dma_unmap_tx(struct port *port, struct desc *desc) | ||
624 | { | ||
625 | #ifdef __ARMEB__ | ||
626 | dma_unmap_single(&port->netdev->dev, desc->data, | ||
627 | desc->buf_len, DMA_TO_DEVICE); | ||
628 | #else | ||
629 | dma_unmap_single(&port->netdev->dev, desc->data & ~3, | ||
630 | ALIGN((desc->data & 3) + desc->buf_len, 4), | ||
631 | DMA_TO_DEVICE); | ||
632 | #endif | ||
633 | } | ||
634 | |||
635 | |||
636 | static void hss_hdlc_set_carrier(void *pdev, int carrier) | ||
637 | { | ||
638 | struct net_device *netdev = pdev; | ||
639 | struct port *port = dev_to_port(netdev); | ||
640 | unsigned long flags; | ||
641 | |||
642 | spin_lock_irqsave(&npe_lock, flags); | ||
643 | port->carrier = carrier; | ||
644 | if (!port->loopback) { | ||
645 | if (carrier) | ||
646 | netif_carrier_on(netdev); | ||
647 | else | ||
648 | netif_carrier_off(netdev); | ||
649 | } | ||
650 | spin_unlock_irqrestore(&npe_lock, flags); | ||
651 | } | ||
652 | |||
653 | static void hss_hdlc_rx_irq(void *pdev) | ||
654 | { | ||
655 | struct net_device *dev = pdev; | ||
656 | struct port *port = dev_to_port(dev); | ||
657 | |||
658 | #if DEBUG_RX | ||
659 | printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name); | ||
660 | #endif | ||
661 | qmgr_disable_irq(queue_ids[port->id].rx); | ||
662 | netif_rx_schedule(dev, &port->napi); | ||
663 | } | ||
664 | |||
665 | static int hss_hdlc_poll(struct napi_struct *napi, int budget) | ||
666 | { | ||
667 | struct port *port = container_of(napi, struct port, napi); | ||
668 | struct net_device *dev = port->netdev; | ||
669 | unsigned int rxq = queue_ids[port->id].rx; | ||
670 | unsigned int rxfreeq = queue_ids[port->id].rxfree; | ||
671 | int received = 0; | ||
672 | |||
673 | #if DEBUG_RX | ||
674 | printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name); | ||
675 | #endif | ||
676 | |||
677 | while (received < budget) { | ||
678 | struct sk_buff *skb; | ||
679 | struct desc *desc; | ||
680 | int n; | ||
681 | #ifdef __ARMEB__ | ||
682 | struct sk_buff *temp; | ||
683 | u32 phys; | ||
684 | #endif | ||
685 | |||
686 | if ((n = queue_get_desc(rxq, port, 0)) < 0) { | ||
687 | #if DEBUG_RX | ||
688 | printk(KERN_DEBUG "%s: hss_hdlc_poll" | ||
689 | " netif_rx_complete\n", dev->name); | ||
690 | #endif | ||
691 | netif_rx_complete(dev, napi); | ||
692 | qmgr_enable_irq(rxq); | ||
693 | if (!qmgr_stat_empty(rxq) && | ||
694 | netif_rx_reschedule(dev, napi)) { | ||
695 | #if DEBUG_RX | ||
696 | printk(KERN_DEBUG "%s: hss_hdlc_poll" | ||
697 | " netif_rx_reschedule succeeded\n", | ||
698 | dev->name); | ||
699 | #endif | ||
700 | qmgr_disable_irq(rxq); | ||
701 | continue; | ||
702 | } | ||
703 | #if DEBUG_RX | ||
704 | printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n", | ||
705 | dev->name); | ||
706 | #endif | ||
707 | return received; /* all work done */ | ||
708 | } | ||
709 | |||
710 | desc = rx_desc_ptr(port, n); | ||
711 | #if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */ | ||
712 | if (desc->error_count) | ||
713 | printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X" | ||
714 | " errors %u\n", dev->name, desc->status, | ||
715 | desc->error_count); | ||
716 | #endif | ||
717 | skb = NULL; | ||
718 | switch (desc->status) { | ||
719 | case 0: | ||
720 | #ifdef __ARMEB__ | ||
721 | if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) { | ||
722 | phys = dma_map_single(&dev->dev, skb->data, | ||
723 | RX_SIZE, | ||
724 | DMA_FROM_DEVICE); | ||
725 | if (dma_mapping_error(&dev->dev, phys)) { | ||
726 | dev_kfree_skb(skb); | ||
727 | skb = NULL; | ||
728 | } | ||
729 | } | ||
730 | #else | ||
731 | skb = netdev_alloc_skb(dev, desc->pkt_len); | ||
732 | #endif | ||
733 | if (!skb) | ||
734 | dev->stats.rx_dropped++; | ||
735 | break; | ||
736 | case ERR_HDLC_ALIGN: | ||
737 | case ERR_HDLC_ABORT: | ||
738 | dev->stats.rx_frame_errors++; | ||
739 | dev->stats.rx_errors++; | ||
740 | break; | ||
741 | case ERR_HDLC_FCS: | ||
742 | dev->stats.rx_crc_errors++; | ||
743 | dev->stats.rx_errors++; | ||
744 | break; | ||
745 | case ERR_HDLC_TOO_LONG: | ||
746 | dev->stats.rx_length_errors++; | ||
747 | dev->stats.rx_errors++; | ||
748 | break; | ||
749 | default: /* FIXME - remove printk */ | ||
750 | printk(KERN_ERR "%s: hss_hdlc_poll: status 0x%02X" | ||
751 | " errors %u\n", dev->name, desc->status, | ||
752 | desc->error_count); | ||
753 | dev->stats.rx_errors++; | ||
754 | } | ||
755 | |||
756 | if (!skb) { | ||
757 | /* put the desc back on RX-ready queue */ | ||
758 | desc->buf_len = RX_SIZE; | ||
759 | desc->pkt_len = desc->status = 0; | ||
760 | queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); | ||
761 | continue; | ||
762 | } | ||
763 | |||
764 | /* process received frame */ | ||
765 | #ifdef __ARMEB__ | ||
766 | temp = skb; | ||
767 | skb = port->rx_buff_tab[n]; | ||
768 | dma_unmap_single(&dev->dev, desc->data, | ||
769 | RX_SIZE, DMA_FROM_DEVICE); | ||
770 | #else | ||
771 | dma_sync_single(&dev->dev, desc->data, | ||
772 | RX_SIZE, DMA_FROM_DEVICE); | ||
773 | memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n], | ||
774 | ALIGN(desc->pkt_len, 4) / 4); | ||
775 | #endif | ||
776 | skb_put(skb, desc->pkt_len); | ||
777 | |||
778 | debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len); | ||
779 | |||
780 | skb->protocol = hdlc_type_trans(skb, dev); | ||
781 | dev->stats.rx_packets++; | ||
782 | dev->stats.rx_bytes += skb->len; | ||
783 | netif_receive_skb(skb); | ||
784 | |||
785 | /* put the new buffer on RX-free queue */ | ||
786 | #ifdef __ARMEB__ | ||
787 | port->rx_buff_tab[n] = temp; | ||
788 | desc->data = phys; | ||
789 | #endif | ||
790 | desc->buf_len = RX_SIZE; | ||
791 | desc->pkt_len = 0; | ||
792 | queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); | ||
793 | received++; | ||
794 | } | ||
795 | #if DEBUG_RX | ||
796 | printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n"); | ||
797 | #endif | ||
798 | return received; /* not all work done */ | ||
799 | } | ||
800 | |||
801 | |||
802 | static void hss_hdlc_txdone_irq(void *pdev) | ||
803 | { | ||
804 | struct net_device *dev = pdev; | ||
805 | struct port *port = dev_to_port(dev); | ||
806 | int n_desc; | ||
807 | |||
808 | #if DEBUG_TX | ||
809 | printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n"); | ||
810 | #endif | ||
811 | while ((n_desc = queue_get_desc(queue_ids[port->id].txdone, | ||
812 | port, 1)) >= 0) { | ||
813 | struct desc *desc; | ||
814 | int start; | ||
815 | |||
816 | desc = tx_desc_ptr(port, n_desc); | ||
817 | |||
818 | dev->stats.tx_packets++; | ||
819 | dev->stats.tx_bytes += desc->pkt_len; | ||
820 | |||
821 | dma_unmap_tx(port, desc); | ||
822 | #if DEBUG_TX | ||
823 | printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n", | ||
824 | dev->name, port->tx_buff_tab[n_desc]); | ||
825 | #endif | ||
826 | free_buffer_irq(port->tx_buff_tab[n_desc]); | ||
827 | port->tx_buff_tab[n_desc] = NULL; | ||
828 | |||
829 | start = qmgr_stat_empty(port->plat->txreadyq); | ||
830 | queue_put_desc(port->plat->txreadyq, | ||
831 | tx_desc_phys(port, n_desc), desc); | ||
832 | if (start) { | ||
833 | #if DEBUG_TX | ||
834 | printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit" | ||
835 | " ready\n", dev->name); | ||
836 | #endif | ||
837 | netif_wake_queue(dev); | ||
838 | } | ||
839 | } | ||
840 | } | ||
841 | |||
842 | static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev) | ||
843 | { | ||
844 | struct port *port = dev_to_port(dev); | ||
845 | unsigned int txreadyq = port->plat->txreadyq; | ||
846 | int len, offset, bytes, n; | ||
847 | void *mem; | ||
848 | u32 phys; | ||
849 | struct desc *desc; | ||
850 | |||
851 | #if DEBUG_TX | ||
852 | printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name); | ||
853 | #endif | ||
854 | |||
855 | if (unlikely(skb->len > HDLC_MAX_MRU)) { | ||
856 | dev_kfree_skb(skb); | ||
857 | dev->stats.tx_errors++; | ||
858 | return NETDEV_TX_OK; | ||
859 | } | ||
860 | |||
861 | debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len); | ||
862 | |||
863 | len = skb->len; | ||
864 | #ifdef __ARMEB__ | ||
865 | offset = 0; /* no need to keep alignment */ | ||
866 | bytes = len; | ||
867 | mem = skb->data; | ||
868 | #else | ||
869 | offset = (int)skb->data & 3; /* keep 32-bit alignment */ | ||
870 | bytes = ALIGN(offset + len, 4); | ||
871 | if (!(mem = kmalloc(bytes, GFP_ATOMIC))) { | ||
872 | dev_kfree_skb(skb); | ||
873 | dev->stats.tx_dropped++; | ||
874 | return NETDEV_TX_OK; | ||
875 | } | ||
876 | memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4); | ||
877 | dev_kfree_skb(skb); | ||
878 | #endif | ||
879 | |||
880 | phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); | ||
881 | if (dma_mapping_error(&dev->dev, phys)) { | ||
882 | #ifdef __ARMEB__ | ||
883 | dev_kfree_skb(skb); | ||
884 | #else | ||
885 | kfree(mem); | ||
886 | #endif | ||
887 | dev->stats.tx_dropped++; | ||
888 | return NETDEV_TX_OK; | ||
889 | } | ||
890 | |||
891 | n = queue_get_desc(txreadyq, port, 1); | ||
892 | BUG_ON(n < 0); | ||
893 | desc = tx_desc_ptr(port, n); | ||
894 | |||
895 | #ifdef __ARMEB__ | ||
896 | port->tx_buff_tab[n] = skb; | ||
897 | #else | ||
898 | port->tx_buff_tab[n] = mem; | ||
899 | #endif | ||
900 | desc->data = phys + offset; | ||
901 | desc->buf_len = desc->pkt_len = len; | ||
902 | |||
903 | wmb(); | ||
904 | queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc); | ||
905 | dev->trans_start = jiffies; | ||
906 | |||
907 | if (qmgr_stat_empty(txreadyq)) { | ||
908 | #if DEBUG_TX | ||
909 | printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name); | ||
910 | #endif | ||
911 | netif_stop_queue(dev); | ||
912 | /* we could miss TX ready interrupt */ | ||
913 | if (!qmgr_stat_empty(txreadyq)) { | ||
914 | #if DEBUG_TX | ||
915 | printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n", | ||
916 | dev->name); | ||
917 | #endif | ||
918 | netif_wake_queue(dev); | ||
919 | } | ||
920 | } | ||
921 | |||
922 | #if DEBUG_TX | ||
923 | printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name); | ||
924 | #endif | ||
925 | return NETDEV_TX_OK; | ||
926 | } | ||
927 | |||
928 | |||
929 | static int request_hdlc_queues(struct port *port) | ||
930 | { | ||
931 | int err; | ||
932 | |||
933 | err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0); | ||
934 | if (err) | ||
935 | return err; | ||
936 | |||
937 | err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0); | ||
938 | if (err) | ||
939 | goto rel_rxfree; | ||
940 | |||
941 | err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0); | ||
942 | if (err) | ||
943 | goto rel_rx; | ||
944 | |||
945 | err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0); | ||
946 | if (err) | ||
947 | goto rel_tx; | ||
948 | |||
949 | err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0); | ||
950 | if (err) | ||
951 | goto rel_txready; | ||
952 | return 0; | ||
953 | |||
954 | rel_txready: | ||
955 | qmgr_release_queue(port->plat->txreadyq); | ||
956 | rel_tx: | ||
957 | qmgr_release_queue(queue_ids[port->id].tx); | ||
958 | rel_rx: | ||
959 | qmgr_release_queue(queue_ids[port->id].rx); | ||
960 | rel_rxfree: | ||
961 | qmgr_release_queue(queue_ids[port->id].rxfree); | ||
962 | printk(KERN_DEBUG "%s: unable to request hardware queues\n", | ||
963 | port->netdev->name); | ||
964 | return err; | ||
965 | } | ||
966 | |||
967 | static void release_hdlc_queues(struct port *port) | ||
968 | { | ||
969 | qmgr_release_queue(queue_ids[port->id].rxfree); | ||
970 | qmgr_release_queue(queue_ids[port->id].rx); | ||
971 | qmgr_release_queue(queue_ids[port->id].txdone); | ||
972 | qmgr_release_queue(queue_ids[port->id].tx); | ||
973 | qmgr_release_queue(port->plat->txreadyq); | ||
974 | } | ||
975 | |||
976 | static int init_hdlc_queues(struct port *port) | ||
977 | { | ||
978 | int i; | ||
979 | |||
980 | if (!ports_open) | ||
981 | if (!(dma_pool = dma_pool_create(DRV_NAME, NULL, | ||
982 | POOL_ALLOC_SIZE, 32, 0))) | ||
983 | return -ENOMEM; | ||
984 | |||
985 | if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL, | ||
986 | &port->desc_tab_phys))) | ||
987 | return -ENOMEM; | ||
988 | memset(port->desc_tab, 0, POOL_ALLOC_SIZE); | ||
989 | memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */ | ||
990 | memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab)); | ||
991 | |||
992 | /* Setup RX buffers */ | ||
993 | for (i = 0; i < RX_DESCS; i++) { | ||
994 | struct desc *desc = rx_desc_ptr(port, i); | ||
995 | buffer_t *buff; | ||
996 | void *data; | ||
997 | #ifdef __ARMEB__ | ||
998 | if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE))) | ||
999 | return -ENOMEM; | ||
1000 | data = buff->data; | ||
1001 | #else | ||
1002 | if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL))) | ||
1003 | return -ENOMEM; | ||
1004 | data = buff; | ||
1005 | #endif | ||
1006 | desc->buf_len = RX_SIZE; | ||
1007 | desc->data = dma_map_single(&port->netdev->dev, data, | ||
1008 | RX_SIZE, DMA_FROM_DEVICE); | ||
1009 | if (dma_mapping_error(&port->netdev->dev, desc->data)) { | ||
1010 | free_buffer(buff); | ||
1011 | return -EIO; | ||
1012 | } | ||
1013 | port->rx_buff_tab[i] = buff; | ||
1014 | } | ||
1015 | |||
1016 | return 0; | ||
1017 | } | ||
1018 | |||
1019 | static void destroy_hdlc_queues(struct port *port) | ||
1020 | { | ||
1021 | int i; | ||
1022 | |||
1023 | if (port->desc_tab) { | ||
1024 | for (i = 0; i < RX_DESCS; i++) { | ||
1025 | struct desc *desc = rx_desc_ptr(port, i); | ||
1026 | buffer_t *buff = port->rx_buff_tab[i]; | ||
1027 | if (buff) { | ||
1028 | dma_unmap_single(&port->netdev->dev, | ||
1029 | desc->data, RX_SIZE, | ||
1030 | DMA_FROM_DEVICE); | ||
1031 | free_buffer(buff); | ||
1032 | } | ||
1033 | } | ||
1034 | for (i = 0; i < TX_DESCS; i++) { | ||
1035 | struct desc *desc = tx_desc_ptr(port, i); | ||
1036 | buffer_t *buff = port->tx_buff_tab[i]; | ||
1037 | if (buff) { | ||
1038 | dma_unmap_tx(port, desc); | ||
1039 | free_buffer(buff); | ||
1040 | } | ||
1041 | } | ||
1042 | dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys); | ||
1043 | port->desc_tab = NULL; | ||
1044 | } | ||
1045 | |||
1046 | if (!ports_open && dma_pool) { | ||
1047 | dma_pool_destroy(dma_pool); | ||
1048 | dma_pool = NULL; | ||
1049 | } | ||
1050 | } | ||
1051 | |||
1052 | static int hss_hdlc_open(struct net_device *dev) | ||
1053 | { | ||
1054 | struct port *port = dev_to_port(dev); | ||
1055 | unsigned long flags; | ||
1056 | int i, err = 0; | ||
1057 | |||
1058 | if ((err = hdlc_open(dev))) | ||
1059 | return err; | ||
1060 | |||
1061 | if ((err = hss_load_firmware(port))) | ||
1062 | goto err_hdlc_close; | ||
1063 | |||
1064 | if ((err = request_hdlc_queues(port))) | ||
1065 | goto err_hdlc_close; | ||
1066 | |||
1067 | if ((err = init_hdlc_queues(port))) | ||
1068 | goto err_destroy_queues; | ||
1069 | |||
1070 | spin_lock_irqsave(&npe_lock, flags); | ||
1071 | if (port->plat->open) | ||
1072 | if ((err = port->plat->open(port->id, dev, | ||
1073 | hss_hdlc_set_carrier))) | ||
1074 | goto err_unlock; | ||
1075 | spin_unlock_irqrestore(&npe_lock, flags); | ||
1076 | |||
1077 | /* Populate queues with buffers, no failure after this point */ | ||
1078 | for (i = 0; i < TX_DESCS; i++) | ||
1079 | queue_put_desc(port->plat->txreadyq, | ||
1080 | tx_desc_phys(port, i), tx_desc_ptr(port, i)); | ||
1081 | |||
1082 | for (i = 0; i < RX_DESCS; i++) | ||
1083 | queue_put_desc(queue_ids[port->id].rxfree, | ||
1084 | rx_desc_phys(port, i), rx_desc_ptr(port, i)); | ||
1085 | |||
1086 | napi_enable(&port->napi); | ||
1087 | netif_start_queue(dev); | ||
1088 | |||
1089 | qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY, | ||
1090 | hss_hdlc_rx_irq, dev); | ||
1091 | |||
1092 | qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY, | ||
1093 | hss_hdlc_txdone_irq, dev); | ||
1094 | qmgr_enable_irq(queue_ids[port->id].txdone); | ||
1095 | |||
1096 | ports_open++; | ||
1097 | |||
1098 | hss_set_hdlc_cfg(port); | ||
1099 | hss_config(port); | ||
1100 | |||
1101 | hss_start_hdlc(port); | ||
1102 | |||
1103 | /* we may already have RX data, enables IRQ */ | ||
1104 | netif_rx_schedule(dev, &port->napi); | ||
1105 | return 0; | ||
1106 | |||
1107 | err_unlock: | ||
1108 | spin_unlock_irqrestore(&npe_lock, flags); | ||
1109 | err_destroy_queues: | ||
1110 | destroy_hdlc_queues(port); | ||
1111 | release_hdlc_queues(port); | ||
1112 | err_hdlc_close: | ||
1113 | hdlc_close(dev); | ||
1114 | return err; | ||
1115 | } | ||
1116 | |||
1117 | static int hss_hdlc_close(struct net_device *dev) | ||
1118 | { | ||
1119 | struct port *port = dev_to_port(dev); | ||
1120 | unsigned long flags; | ||
1121 | int i, buffs = RX_DESCS; /* allocated RX buffers */ | ||
1122 | |||
1123 | spin_lock_irqsave(&npe_lock, flags); | ||
1124 | ports_open--; | ||
1125 | qmgr_disable_irq(queue_ids[port->id].rx); | ||
1126 | netif_stop_queue(dev); | ||
1127 | napi_disable(&port->napi); | ||
1128 | |||
1129 | hss_stop_hdlc(port); | ||
1130 | |||
1131 | while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0) | ||
1132 | buffs--; | ||
1133 | while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0) | ||
1134 | buffs--; | ||
1135 | |||
1136 | if (buffs) | ||
1137 | printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)" | ||
1138 | " left in NPE\n", dev->name, buffs); | ||
1139 | |||
1140 | buffs = TX_DESCS; | ||
1141 | while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0) | ||
1142 | buffs--; /* cancel TX */ | ||
1143 | |||
1144 | i = 0; | ||
1145 | do { | ||
1146 | while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0) | ||
1147 | buffs--; | ||
1148 | if (!buffs) | ||
1149 | break; | ||
1150 | } while (++i < MAX_CLOSE_WAIT); | ||
1151 | |||
1152 | if (buffs) | ||
1153 | printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) " | ||
1154 | "left in NPE\n", dev->name, buffs); | ||
1155 | #if DEBUG_CLOSE | ||
1156 | if (!buffs) | ||
1157 | printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i); | ||
1158 | #endif | ||
1159 | qmgr_disable_irq(queue_ids[port->id].txdone); | ||
1160 | |||
1161 | if (port->plat->close) | ||
1162 | port->plat->close(port->id, dev); | ||
1163 | spin_unlock_irqrestore(&npe_lock, flags); | ||
1164 | |||
1165 | destroy_hdlc_queues(port); | ||
1166 | release_hdlc_queues(port); | ||
1167 | hdlc_close(dev); | ||
1168 | return 0; | ||
1169 | } | ||
1170 | |||
1171 | |||
1172 | static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding, | ||
1173 | unsigned short parity) | ||
1174 | { | ||
1175 | struct port *port = dev_to_port(dev); | ||
1176 | |||
1177 | if (encoding != ENCODING_NRZ) | ||
1178 | return -EINVAL; | ||
1179 | |||
1180 | switch(parity) { | ||
1181 | case PARITY_CRC16_PR1_CCITT: | ||
1182 | port->hdlc_cfg = 0; | ||
1183 | return 0; | ||
1184 | |||
1185 | case PARITY_CRC32_PR1_CCITT: | ||
1186 | port->hdlc_cfg = PKT_HDLC_CRC_32; | ||
1187 | return 0; | ||
1188 | |||
1189 | default: | ||
1190 | return -EINVAL; | ||
1191 | } | ||
1192 | } | ||
1193 | |||
1194 | |||
1195 | static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | ||
1196 | { | ||
1197 | const size_t size = sizeof(sync_serial_settings); | ||
1198 | sync_serial_settings new_line; | ||
1199 | sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; | ||
1200 | struct port *port = dev_to_port(dev); | ||
1201 | unsigned long flags; | ||
1202 | int clk; | ||
1203 | |||
1204 | if (cmd != SIOCWANDEV) | ||
1205 | return hdlc_ioctl(dev, ifr, cmd); | ||
1206 | |||
1207 | switch(ifr->ifr_settings.type) { | ||
1208 | case IF_GET_IFACE: | ||
1209 | ifr->ifr_settings.type = IF_IFACE_V35; | ||
1210 | if (ifr->ifr_settings.size < size) { | ||
1211 | ifr->ifr_settings.size = size; /* data size wanted */ | ||
1212 | return -ENOBUFS; | ||
1213 | } | ||
1214 | memset(&new_line, 0, sizeof(new_line)); | ||
1215 | new_line.clock_type = port->clock_type; | ||
1216 | new_line.clock_rate = 2048000; /* FIXME */ | ||
1217 | new_line.loopback = port->loopback; | ||
1218 | if (copy_to_user(line, &new_line, size)) | ||
1219 | return -EFAULT; | ||
1220 | return 0; | ||
1221 | |||
1222 | case IF_IFACE_SYNC_SERIAL: | ||
1223 | case IF_IFACE_V35: | ||
1224 | if(!capable(CAP_NET_ADMIN)) | ||
1225 | return -EPERM; | ||
1226 | if (copy_from_user(&new_line, line, size)) | ||
1227 | return -EFAULT; | ||
1228 | |||
1229 | clk = new_line.clock_type; | ||
1230 | if (port->plat->set_clock) | ||
1231 | clk = port->plat->set_clock(port->id, clk); | ||
1232 | |||
1233 | if (clk != CLOCK_EXT && clk != CLOCK_INT) | ||
1234 | return -EINVAL; /* No such clock setting */ | ||
1235 | |||
1236 | if (new_line.loopback != 0 && new_line.loopback != 1) | ||
1237 | return -EINVAL; | ||
1238 | |||
1239 | port->clock_type = clk; /* Update settings */ | ||
1240 | /* FIXME port->clock_rate = new_line.clock_rate */; | ||
1241 | port->loopback = new_line.loopback; | ||
1242 | |||
1243 | spin_lock_irqsave(&npe_lock, flags); | ||
1244 | |||
1245 | if (dev->flags & IFF_UP) | ||
1246 | hss_config(port); | ||
1247 | |||
1248 | if (port->loopback || port->carrier) | ||
1249 | netif_carrier_on(port->netdev); | ||
1250 | else | ||
1251 | netif_carrier_off(port->netdev); | ||
1252 | spin_unlock_irqrestore(&npe_lock, flags); | ||
1253 | |||
1254 | return 0; | ||
1255 | |||
1256 | default: | ||
1257 | return hdlc_ioctl(dev, ifr, cmd); | ||
1258 | } | ||
1259 | } | ||
1260 | |||
1261 | /***************************************************************************** | ||
1262 | * initialization | ||
1263 | ****************************************************************************/ | ||
1264 | |||
1265 | static int __devinit hss_init_one(struct platform_device *pdev) | ||
1266 | { | ||
1267 | struct port *port; | ||
1268 | struct net_device *dev; | ||
1269 | hdlc_device *hdlc; | ||
1270 | int err; | ||
1271 | |||
1272 | if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL) | ||
1273 | return -ENOMEM; | ||
1274 | |||
1275 | if ((port->npe = npe_request(0)) == NULL) { | ||
1276 | err = -ENOSYS; | ||
1277 | goto err_free; | ||
1278 | } | ||
1279 | |||
1280 | if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) { | ||
1281 | err = -ENOMEM; | ||
1282 | goto err_plat; | ||
1283 | } | ||
1284 | |||
1285 | SET_NETDEV_DEV(dev, &pdev->dev); | ||
1286 | hdlc = dev_to_hdlc(dev); | ||
1287 | hdlc->attach = hss_hdlc_attach; | ||
1288 | hdlc->xmit = hss_hdlc_xmit; | ||
1289 | dev->open = hss_hdlc_open; | ||
1290 | dev->stop = hss_hdlc_close; | ||
1291 | dev->do_ioctl = hss_hdlc_ioctl; | ||
1292 | dev->tx_queue_len = 100; | ||
1293 | port->clock_type = CLOCK_EXT; | ||
1294 | port->clock_rate = 2048000; | ||
1295 | port->id = pdev->id; | ||
1296 | port->dev = &pdev->dev; | ||
1297 | port->plat = pdev->dev.platform_data; | ||
1298 | netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT); | ||
1299 | |||
1300 | if ((err = register_hdlc_device(dev))) | ||
1301 | goto err_free_netdev; | ||
1302 | |||
1303 | platform_set_drvdata(pdev, port); | ||
1304 | |||
1305 | printk(KERN_INFO "%s: HSS-%i\n", dev->name, port->id); | ||
1306 | return 0; | ||
1307 | |||
1308 | err_free_netdev: | ||
1309 | free_netdev(dev); | ||
1310 | err_plat: | ||
1311 | npe_release(port->npe); | ||
1312 | err_free: | ||
1313 | kfree(port); | ||
1314 | return err; | ||
1315 | } | ||
1316 | |||
1317 | static int __devexit hss_remove_one(struct platform_device *pdev) | ||
1318 | { | ||
1319 | struct port *port = platform_get_drvdata(pdev); | ||
1320 | |||
1321 | unregister_hdlc_device(port->netdev); | ||
1322 | free_netdev(port->netdev); | ||
1323 | npe_release(port->npe); | ||
1324 | platform_set_drvdata(pdev, NULL); | ||
1325 | kfree(port); | ||
1326 | return 0; | ||
1327 | } | ||
1328 | |||
1329 | static struct platform_driver ixp4xx_hss_driver = { | ||
1330 | .driver.name = DRV_NAME, | ||
1331 | .probe = hss_init_one, | ||
1332 | .remove = hss_remove_one, | ||
1333 | }; | ||
1334 | |||
1335 | static int __init hss_init_module(void) | ||
1336 | { | ||
1337 | if ((ixp4xx_read_feature_bits() & | ||
1338 | (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) != | ||
1339 | (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) | ||
1340 | return -ENOSYS; | ||
1341 | |||
1342 | spin_lock_init(&npe_lock); | ||
1343 | |||
1344 | return platform_driver_register(&ixp4xx_hss_driver); | ||
1345 | } | ||
1346 | |||
1347 | static void __exit hss_cleanup_module(void) | ||
1348 | { | ||
1349 | platform_driver_unregister(&ixp4xx_hss_driver); | ||
1350 | } | ||
1351 | |||
1352 | MODULE_AUTHOR("Krzysztof Halasa"); | ||
1353 | MODULE_DESCRIPTION("Intel IXP4xx HSS driver"); | ||
1354 | MODULE_LICENSE("GPL v2"); | ||
1355 | MODULE_ALIAS("platform:ixp4xx_hss"); | ||
1356 | module_init(hss_init_module); | ||
1357 | module_exit(hss_cleanup_module); | ||