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-rw-r--r--drivers/ata/libata-core.c1884
-rw-r--r--drivers/ata/libata-sff.c1859
-rw-r--r--drivers/ata/libata.h8
3 files changed, 1870 insertions, 1881 deletions
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 7860d9f60ae4..34c068f18350 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -46,7 +46,6 @@
46#include <linux/init.h> 46#include <linux/init.h>
47#include <linux/list.h> 47#include <linux/list.h>
48#include <linux/mm.h> 48#include <linux/mm.h>
49#include <linux/highmem.h>
50#include <linux/spinlock.h> 49#include <linux/spinlock.h>
51#include <linux/blkdev.h> 50#include <linux/blkdev.h>
52#include <linux/delay.h> 51#include <linux/delay.h>
@@ -98,41 +97,6 @@ const struct ata_port_operations sata_pmp_port_ops = {
98 .error_handler = sata_pmp_error_handler, 97 .error_handler = sata_pmp_error_handler,
99}; 98};
100 99
101const struct ata_port_operations ata_sff_port_ops = {
102 .inherits = &ata_base_port_ops,
103
104 .qc_prep = ata_qc_prep,
105 .qc_issue = ata_qc_issue_prot,
106
107 .freeze = ata_bmdma_freeze,
108 .thaw = ata_bmdma_thaw,
109 .softreset = ata_std_softreset,
110 .error_handler = ata_bmdma_error_handler,
111 .post_internal_cmd = ata_bmdma_post_internal_cmd,
112
113 .dev_select = ata_std_dev_select,
114 .check_status = ata_check_status,
115 .tf_load = ata_tf_load,
116 .tf_read = ata_tf_read,
117 .exec_command = ata_exec_command,
118 .data_xfer = ata_data_xfer,
119 .irq_on = ata_irq_on,
120
121 .port_start = ata_sff_port_start,
122};
123
124const struct ata_port_operations ata_bmdma_port_ops = {
125 .inherits = &ata_sff_port_ops,
126
127 .mode_filter = ata_pci_default_filter,
128
129 .bmdma_setup = ata_bmdma_setup,
130 .bmdma_start = ata_bmdma_start,
131 .bmdma_stop = ata_bmdma_stop,
132 .bmdma_status = ata_bmdma_status,
133 .irq_clear = ata_bmdma_irq_clear,
134};
135
136static unsigned int ata_dev_init_params(struct ata_device *dev, 100static unsigned int ata_dev_init_params(struct ata_device *dev,
137 u16 heads, u16 sectors); 101 u16 heads, u16 sectors);
138static unsigned int ata_dev_set_xfermode(struct ata_device *dev); 102static unsigned int ata_dev_set_xfermode(struct ata_device *dev);
@@ -423,6 +387,14 @@ int atapi_cmd_type(u8 opcode)
423} 387}
424 388
425/** 389/**
390 * ata_noop_irq_clear - Noop placeholder for irq_clear
391 * @ap: Port associated with this ATA transaction.
392 */
393void ata_noop_irq_clear(struct ata_port *ap)
394{
395}
396
397/**
426 * ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure 398 * ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure
427 * @tf: Taskfile to convert 399 * @tf: Taskfile to convert
428 * @pmp: Port multiplier port 400 * @pmp: Port multiplier port
@@ -1102,50 +1074,6 @@ static void ata_lpm_disable(struct ata_host *host)
1102} 1074}
1103#endif /* CONFIG_PM */ 1075#endif /* CONFIG_PM */
1104 1076
1105
1106/**
1107 * ata_devchk - PATA device presence detection
1108 * @ap: ATA channel to examine
1109 * @device: Device to examine (starting at zero)
1110 *
1111 * This technique was originally described in
1112 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1113 * later found its way into the ATA/ATAPI spec.
1114 *
1115 * Write a pattern to the ATA shadow registers,
1116 * and if a device is present, it will respond by
1117 * correctly storing and echoing back the
1118 * ATA shadow register contents.
1119 *
1120 * LOCKING:
1121 * caller.
1122 */
1123
1124static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
1125{
1126 struct ata_ioports *ioaddr = &ap->ioaddr;
1127 u8 nsect, lbal;
1128
1129 ap->ops->dev_select(ap, device);
1130
1131 iowrite8(0x55, ioaddr->nsect_addr);
1132 iowrite8(0xaa, ioaddr->lbal_addr);
1133
1134 iowrite8(0xaa, ioaddr->nsect_addr);
1135 iowrite8(0x55, ioaddr->lbal_addr);
1136
1137 iowrite8(0x55, ioaddr->nsect_addr);
1138 iowrite8(0xaa, ioaddr->lbal_addr);
1139
1140 nsect = ioread8(ioaddr->nsect_addr);
1141 lbal = ioread8(ioaddr->lbal_addr);
1142
1143 if ((nsect == 0x55) && (lbal == 0xaa))
1144 return 1; /* we found a device */
1145
1146 return 0; /* nothing found */
1147}
1148
1149/** 1077/**
1150 * ata_dev_classify - determine device type based on ATA-spec signature 1078 * ata_dev_classify - determine device type based on ATA-spec signature
1151 * @tf: ATA taskfile register set for device to be identified 1079 * @tf: ATA taskfile register set for device to be identified
@@ -1206,75 +1134,6 @@ unsigned int ata_dev_classify(const struct ata_taskfile *tf)
1206} 1134}
1207 1135
1208/** 1136/**
1209 * ata_dev_try_classify - Parse returned ATA device signature
1210 * @dev: ATA device to classify (starting at zero)
1211 * @present: device seems present
1212 * @r_err: Value of error register on completion
1213 *
1214 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1215 * an ATA/ATAPI-defined set of values is placed in the ATA
1216 * shadow registers, indicating the results of device detection
1217 * and diagnostics.
1218 *
1219 * Select the ATA device, and read the values from the ATA shadow
1220 * registers. Then parse according to the Error register value,
1221 * and the spec-defined values examined by ata_dev_classify().
1222 *
1223 * LOCKING:
1224 * caller.
1225 *
1226 * RETURNS:
1227 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1228 */
1229unsigned int ata_dev_try_classify(struct ata_device *dev, int present,
1230 u8 *r_err)
1231{
1232 struct ata_port *ap = dev->link->ap;
1233 struct ata_taskfile tf;
1234 unsigned int class;
1235 u8 err;
1236
1237 ap->ops->dev_select(ap, dev->devno);
1238
1239 memset(&tf, 0, sizeof(tf));
1240
1241 ap->ops->tf_read(ap, &tf);
1242 err = tf.feature;
1243 if (r_err)
1244 *r_err = err;
1245
1246 /* see if device passed diags: continue and warn later */
1247 if (err == 0)
1248 /* diagnostic fail : do nothing _YET_ */
1249 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1250 else if (err == 1)
1251 /* do nothing */ ;
1252 else if ((dev->devno == 0) && (err == 0x81))
1253 /* do nothing */ ;
1254 else
1255 return ATA_DEV_NONE;
1256
1257 /* determine if device is ATA or ATAPI */
1258 class = ata_dev_classify(&tf);
1259
1260 if (class == ATA_DEV_UNKNOWN) {
1261 /* If the device failed diagnostic, it's likely to
1262 * have reported incorrect device signature too.
1263 * Assume ATA device if the device seems present but
1264 * device signature is invalid with diagnostic
1265 * failure.
1266 */
1267 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1268 class = ATA_DEV_ATA;
1269 else
1270 class = ATA_DEV_NONE;
1271 } else if ((class == ATA_DEV_ATA) && (ata_chk_status(ap) == 0))
1272 class = ATA_DEV_NONE;
1273
1274 return class;
1275}
1276
1277/**
1278 * ata_id_string - Convert IDENTIFY DEVICE page into string 1137 * ata_id_string - Convert IDENTIFY DEVICE page into string
1279 * @id: IDENTIFY DEVICE results we will examine 1138 * @id: IDENTIFY DEVICE results we will examine
1280 * @s: string into which data is output 1139 * @s: string into which data is output
@@ -1597,73 +1456,6 @@ void ata_noop_dev_select(struct ata_port *ap, unsigned int device)
1597{ 1456{
1598} 1457}
1599 1458
1600
1601/**
1602 * ata_std_dev_select - Select device 0/1 on ATA bus
1603 * @ap: ATA channel to manipulate
1604 * @device: ATA device (numbered from zero) to select
1605 *
1606 * Use the method defined in the ATA specification to
1607 * make either device 0, or device 1, active on the
1608 * ATA channel. Works with both PIO and MMIO.
1609 *
1610 * May be used as the dev_select() entry in ata_port_operations.
1611 *
1612 * LOCKING:
1613 * caller.
1614 */
1615
1616void ata_std_dev_select(struct ata_port *ap, unsigned int device)
1617{
1618 u8 tmp;
1619
1620 if (device == 0)
1621 tmp = ATA_DEVICE_OBS;
1622 else
1623 tmp = ATA_DEVICE_OBS | ATA_DEV1;
1624
1625 iowrite8(tmp, ap->ioaddr.device_addr);
1626 ata_pause(ap); /* needed; also flushes, for mmio */
1627}
1628
1629/**
1630 * ata_dev_select - Select device 0/1 on ATA bus
1631 * @ap: ATA channel to manipulate
1632 * @device: ATA device (numbered from zero) to select
1633 * @wait: non-zero to wait for Status register BSY bit to clear
1634 * @can_sleep: non-zero if context allows sleeping
1635 *
1636 * Use the method defined in the ATA specification to
1637 * make either device 0, or device 1, active on the
1638 * ATA channel.
1639 *
1640 * This is a high-level version of ata_std_dev_select(),
1641 * which additionally provides the services of inserting
1642 * the proper pauses and status polling, where needed.
1643 *
1644 * LOCKING:
1645 * caller.
1646 */
1647
1648void ata_dev_select(struct ata_port *ap, unsigned int device,
1649 unsigned int wait, unsigned int can_sleep)
1650{
1651 if (ata_msg_probe(ap))
1652 ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, "
1653 "device %u, wait %u\n", device, wait);
1654
1655 if (wait)
1656 ata_wait_idle(ap);
1657
1658 ap->ops->dev_select(ap, device);
1659
1660 if (wait) {
1661 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
1662 msleep(150);
1663 ata_wait_idle(ap);
1664 }
1665}
1666
1667/** 1459/**
1668 * ata_dump_id - IDENTIFY DEVICE info debugging output 1460 * ata_dump_id - IDENTIFY DEVICE info debugging output
1669 * @id: IDENTIFY DEVICE page to dump 1461 * @id: IDENTIFY DEVICE page to dump
@@ -1791,8 +1583,7 @@ unsigned long ata_id_xfermask(const u16 *id)
1791 * LOCKING: 1583 * LOCKING:
1792 * Inherited from caller. 1584 * Inherited from caller.
1793 */ 1585 */
1794static void ata_pio_queue_task(struct ata_port *ap, void *data, 1586void ata_pio_queue_task(struct ata_port *ap, void *data, unsigned long delay)
1795 unsigned long delay)
1796{ 1587{
1797 ap->port_task_data = data; 1588 ap->port_task_data = data;
1798 1589
@@ -3532,353 +3323,6 @@ int ata_do_set_mode(struct ata_link *link, struct ata_device **r_failed_dev)
3532} 3323}
3533 3324
3534/** 3325/**
3535 * ata_tf_to_host - issue ATA taskfile to host controller
3536 * @ap: port to which command is being issued
3537 * @tf: ATA taskfile register set
3538 *
3539 * Issues ATA taskfile register set to ATA host controller,
3540 * with proper synchronization with interrupt handler and
3541 * other threads.
3542 *
3543 * LOCKING:
3544 * spin_lock_irqsave(host lock)
3545 */
3546
3547static inline void ata_tf_to_host(struct ata_port *ap,
3548 const struct ata_taskfile *tf)
3549{
3550 ap->ops->tf_load(ap, tf);
3551 ap->ops->exec_command(ap, tf);
3552}
3553
3554/**
3555 * ata_busy_sleep - sleep until BSY clears, or timeout
3556 * @ap: port containing status register to be polled
3557 * @tmout_pat: impatience timeout
3558 * @tmout: overall timeout
3559 *
3560 * Sleep until ATA Status register bit BSY clears,
3561 * or a timeout occurs.
3562 *
3563 * LOCKING:
3564 * Kernel thread context (may sleep).
3565 *
3566 * RETURNS:
3567 * 0 on success, -errno otherwise.
3568 */
3569int ata_busy_sleep(struct ata_port *ap,
3570 unsigned long tmout_pat, unsigned long tmout)
3571{
3572 unsigned long timer_start, timeout;
3573 u8 status;
3574
3575 status = ata_busy_wait(ap, ATA_BUSY, 300);
3576 timer_start = jiffies;
3577 timeout = timer_start + tmout_pat;
3578 while (status != 0xff && (status & ATA_BUSY) &&
3579 time_before(jiffies, timeout)) {
3580 msleep(50);
3581 status = ata_busy_wait(ap, ATA_BUSY, 3);
3582 }
3583
3584 if (status != 0xff && (status & ATA_BUSY))
3585 ata_port_printk(ap, KERN_WARNING,
3586 "port is slow to respond, please be patient "
3587 "(Status 0x%x)\n", status);
3588
3589 timeout = timer_start + tmout;
3590 while (status != 0xff && (status & ATA_BUSY) &&
3591 time_before(jiffies, timeout)) {
3592 msleep(50);
3593 status = ata_chk_status(ap);
3594 }
3595
3596 if (status == 0xff)
3597 return -ENODEV;
3598
3599 if (status & ATA_BUSY) {
3600 ata_port_printk(ap, KERN_ERR, "port failed to respond "
3601 "(%lu secs, Status 0x%x)\n",
3602 tmout / HZ, status);
3603 return -EBUSY;
3604 }
3605
3606 return 0;
3607}
3608
3609/**
3610 * ata_wait_after_reset - wait before checking status after reset
3611 * @ap: port containing status register to be polled
3612 * @deadline: deadline jiffies for the operation
3613 *
3614 * After reset, we need to pause a while before reading status.
3615 * Also, certain combination of controller and device report 0xff
3616 * for some duration (e.g. until SATA PHY is up and running)
3617 * which is interpreted as empty port in ATA world. This
3618 * function also waits for such devices to get out of 0xff
3619 * status.
3620 *
3621 * LOCKING:
3622 * Kernel thread context (may sleep).
3623 */
3624void ata_wait_after_reset(struct ata_port *ap, unsigned long deadline)
3625{
3626 unsigned long until = jiffies + ATA_TMOUT_FF_WAIT;
3627
3628 if (time_before(until, deadline))
3629 deadline = until;
3630
3631 /* Spec mandates ">= 2ms" before checking status. We wait
3632 * 150ms, because that was the magic delay used for ATAPI
3633 * devices in Hale Landis's ATADRVR, for the period of time
3634 * between when the ATA command register is written, and then
3635 * status is checked. Because waiting for "a while" before
3636 * checking status is fine, post SRST, we perform this magic
3637 * delay here as well.
3638 *
3639 * Old drivers/ide uses the 2mS rule and then waits for ready.
3640 */
3641 msleep(150);
3642
3643 /* Wait for 0xff to clear. Some SATA devices take a long time
3644 * to clear 0xff after reset. For example, HHD424020F7SV00
3645 * iVDR needs >= 800ms while. Quantum GoVault needs even more
3646 * than that.
3647 *
3648 * Note that some PATA controllers (pata_ali) explode if
3649 * status register is read more than once when there's no
3650 * device attached.
3651 */
3652 if (ap->flags & ATA_FLAG_SATA) {
3653 while (1) {
3654 u8 status = ata_chk_status(ap);
3655
3656 if (status != 0xff || time_after(jiffies, deadline))
3657 return;
3658
3659 msleep(50);
3660 }
3661 }
3662}
3663
3664/**
3665 * ata_wait_ready - sleep until BSY clears, or timeout
3666 * @ap: port containing status register to be polled
3667 * @deadline: deadline jiffies for the operation
3668 *
3669 * Sleep until ATA Status register bit BSY clears, or timeout
3670 * occurs.
3671 *
3672 * LOCKING:
3673 * Kernel thread context (may sleep).
3674 *
3675 * RETURNS:
3676 * 0 on success, -errno otherwise.
3677 */
3678int ata_wait_ready(struct ata_port *ap, unsigned long deadline)
3679{
3680 unsigned long start = jiffies;
3681 int warned = 0;
3682
3683 while (1) {
3684 u8 status = ata_chk_status(ap);
3685 unsigned long now = jiffies;
3686
3687 if (!(status & ATA_BUSY))
3688 return 0;
3689 if (!ata_link_online(&ap->link) && status == 0xff)
3690 return -ENODEV;
3691 if (time_after(now, deadline))
3692 return -EBUSY;
3693
3694 if (!warned && time_after(now, start + 5 * HZ) &&
3695 (deadline - now > 3 * HZ)) {
3696 ata_port_printk(ap, KERN_WARNING,
3697 "port is slow to respond, please be patient "
3698 "(Status 0x%x)\n", status);
3699 warned = 1;
3700 }
3701
3702 msleep(50);
3703 }
3704}
3705
3706static int ata_bus_post_reset(struct ata_port *ap, unsigned int devmask,
3707 unsigned long deadline)
3708{
3709 struct ata_ioports *ioaddr = &ap->ioaddr;
3710 unsigned int dev0 = devmask & (1 << 0);
3711 unsigned int dev1 = devmask & (1 << 1);
3712 int rc, ret = 0;
3713
3714 /* if device 0 was found in ata_devchk, wait for its
3715 * BSY bit to clear
3716 */
3717 if (dev0) {
3718 rc = ata_wait_ready(ap, deadline);
3719 if (rc) {
3720 if (rc != -ENODEV)
3721 return rc;
3722 ret = rc;
3723 }
3724 }
3725
3726 /* if device 1 was found in ata_devchk, wait for register
3727 * access briefly, then wait for BSY to clear.
3728 */
3729 if (dev1) {
3730 int i;
3731
3732 ap->ops->dev_select(ap, 1);
3733
3734 /* Wait for register access. Some ATAPI devices fail
3735 * to set nsect/lbal after reset, so don't waste too
3736 * much time on it. We're gonna wait for !BSY anyway.
3737 */
3738 for (i = 0; i < 2; i++) {
3739 u8 nsect, lbal;
3740
3741 nsect = ioread8(ioaddr->nsect_addr);
3742 lbal = ioread8(ioaddr->lbal_addr);
3743 if ((nsect == 1) && (lbal == 1))
3744 break;
3745 msleep(50); /* give drive a breather */
3746 }
3747
3748 rc = ata_wait_ready(ap, deadline);
3749 if (rc) {
3750 if (rc != -ENODEV)
3751 return rc;
3752 ret = rc;
3753 }
3754 }
3755
3756 /* is all this really necessary? */
3757 ap->ops->dev_select(ap, 0);
3758 if (dev1)
3759 ap->ops->dev_select(ap, 1);
3760 if (dev0)
3761 ap->ops->dev_select(ap, 0);
3762
3763 return ret;
3764}
3765
3766static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
3767 unsigned long deadline)
3768{
3769 struct ata_ioports *ioaddr = &ap->ioaddr;
3770
3771 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
3772
3773 /* software reset. causes dev0 to be selected */
3774 iowrite8(ap->ctl, ioaddr->ctl_addr);
3775 udelay(20); /* FIXME: flush */
3776 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
3777 udelay(20); /* FIXME: flush */
3778 iowrite8(ap->ctl, ioaddr->ctl_addr);
3779
3780 /* wait a while before checking status */
3781 ata_wait_after_reset(ap, deadline);
3782
3783 /* Before we perform post reset processing we want to see if
3784 * the bus shows 0xFF because the odd clown forgets the D7
3785 * pulldown resistor.
3786 */
3787 if (ata_chk_status(ap) == 0xFF)
3788 return -ENODEV;
3789
3790 return ata_bus_post_reset(ap, devmask, deadline);
3791}
3792
3793/**
3794 * ata_bus_reset - reset host port and associated ATA channel
3795 * @ap: port to reset
3796 *
3797 * This is typically the first time we actually start issuing
3798 * commands to the ATA channel. We wait for BSY to clear, then
3799 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
3800 * result. Determine what devices, if any, are on the channel
3801 * by looking at the device 0/1 error register. Look at the signature
3802 * stored in each device's taskfile registers, to determine if
3803 * the device is ATA or ATAPI.
3804 *
3805 * LOCKING:
3806 * PCI/etc. bus probe sem.
3807 * Obtains host lock.
3808 *
3809 * SIDE EFFECTS:
3810 * Sets ATA_FLAG_DISABLED if bus reset fails.
3811 */
3812
3813void ata_bus_reset(struct ata_port *ap)
3814{
3815 struct ata_device *device = ap->link.device;
3816 struct ata_ioports *ioaddr = &ap->ioaddr;
3817 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
3818 u8 err;
3819 unsigned int dev0, dev1 = 0, devmask = 0;
3820 int rc;
3821
3822 DPRINTK("ENTER, host %u, port %u\n", ap->print_id, ap->port_no);
3823
3824 /* determine if device 0/1 are present */
3825 if (ap->flags & ATA_FLAG_SATA_RESET)
3826 dev0 = 1;
3827 else {
3828 dev0 = ata_devchk(ap, 0);
3829 if (slave_possible)
3830 dev1 = ata_devchk(ap, 1);
3831 }
3832
3833 if (dev0)
3834 devmask |= (1 << 0);
3835 if (dev1)
3836 devmask |= (1 << 1);
3837
3838 /* select device 0 again */
3839 ap->ops->dev_select(ap, 0);
3840
3841 /* issue bus reset */
3842 if (ap->flags & ATA_FLAG_SRST) {
3843 rc = ata_bus_softreset(ap, devmask, jiffies + 40 * HZ);
3844 if (rc && rc != -ENODEV)
3845 goto err_out;
3846 }
3847
3848 /*
3849 * determine by signature whether we have ATA or ATAPI devices
3850 */
3851 device[0].class = ata_dev_try_classify(&device[0], dev0, &err);
3852 if ((slave_possible) && (err != 0x81))
3853 device[1].class = ata_dev_try_classify(&device[1], dev1, &err);
3854
3855 /* is double-select really necessary? */
3856 if (device[1].class != ATA_DEV_NONE)
3857 ap->ops->dev_select(ap, 1);
3858 if (device[0].class != ATA_DEV_NONE)
3859 ap->ops->dev_select(ap, 0);
3860
3861 /* if no devices were detected, disable this port */
3862 if ((device[0].class == ATA_DEV_NONE) &&
3863 (device[1].class == ATA_DEV_NONE))
3864 goto err_out;
3865
3866 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
3867 /* set up device control for ATA_FLAG_SATA_RESET */
3868 iowrite8(ap->ctl, ioaddr->ctl_addr);
3869 }
3870
3871 DPRINTK("EXIT\n");
3872 return;
3873
3874err_out:
3875 ata_port_printk(ap, KERN_ERR, "disabling port\n");
3876 ata_port_disable(ap);
3877
3878 DPRINTK("EXIT\n");
3879}
3880
3881/**
3882 * sata_link_debounce - debounce SATA phy status 3326 * sata_link_debounce - debounce SATA phy status
3883 * @link: ATA link to debounce SATA phy status for 3327 * @link: ATA link to debounce SATA phy status for
3884 * @params: timing parameters { interval, duratinon, timeout } in msec 3328 * @params: timing parameters { interval, duratinon, timeout } in msec
@@ -4034,66 +3478,6 @@ int ata_std_prereset(struct ata_link *link, unsigned long deadline)
4034} 3478}
4035 3479
4036/** 3480/**
4037 * ata_std_softreset - reset host port via ATA SRST
4038 * @link: ATA link to reset
4039 * @classes: resulting classes of attached devices
4040 * @deadline: deadline jiffies for the operation
4041 *
4042 * Reset host port using ATA SRST.
4043 *
4044 * LOCKING:
4045 * Kernel thread context (may sleep)
4046 *
4047 * RETURNS:
4048 * 0 on success, -errno otherwise.
4049 */
4050int ata_std_softreset(struct ata_link *link, unsigned int *classes,
4051 unsigned long deadline)
4052{
4053 struct ata_port *ap = link->ap;
4054 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
4055 unsigned int devmask = 0;
4056 int rc;
4057 u8 err;
4058
4059 DPRINTK("ENTER\n");
4060
4061 if (ata_link_offline(link)) {
4062 classes[0] = ATA_DEV_NONE;
4063 goto out;
4064 }
4065
4066 /* determine if device 0/1 are present */
4067 if (ata_devchk(ap, 0))
4068 devmask |= (1 << 0);
4069 if (slave_possible && ata_devchk(ap, 1))
4070 devmask |= (1 << 1);
4071
4072 /* select device 0 again */
4073 ap->ops->dev_select(ap, 0);
4074
4075 /* issue bus reset */
4076 DPRINTK("about to softreset, devmask=%x\n", devmask);
4077 rc = ata_bus_softreset(ap, devmask, deadline);
4078 /* if link is occupied, -ENODEV too is an error */
4079 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
4080 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
4081 return rc;
4082 }
4083
4084 /* determine by signature whether we have ATA or ATAPI devices */
4085 classes[0] = ata_dev_try_classify(&link->device[0],
4086 devmask & (1 << 0), &err);
4087 if (slave_possible && err != 0x81)
4088 classes[1] = ata_dev_try_classify(&link->device[1],
4089 devmask & (1 << 1), &err);
4090
4091 out:
4092 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
4093 return 0;
4094}
4095
4096/**
4097 * sata_link_hardreset - reset link via SATA phy reset 3481 * sata_link_hardreset - reset link via SATA phy reset
4098 * @link: link to reset 3482 * @link: link to reset
4099 * @timing: timing parameters { interval, duratinon, timeout } in msec 3483 * @timing: timing parameters { interval, duratinon, timeout } in msec
@@ -4154,74 +3538,6 @@ int sata_link_hardreset(struct ata_link *link, const unsigned long *timing,
4154} 3538}
4155 3539
4156/** 3540/**
4157 * sata_std_hardreset - reset host port via SATA phy reset
4158 * @link: link to reset
4159 * @class: resulting class of attached device
4160 * @deadline: deadline jiffies for the operation
4161 *
4162 * SATA phy-reset host port using DET bits of SControl register,
4163 * wait for !BSY and classify the attached device.
4164 *
4165 * LOCKING:
4166 * Kernel thread context (may sleep)
4167 *
4168 * RETURNS:
4169 * 0 on success, -errno otherwise.
4170 */
4171int sata_std_hardreset(struct ata_link *link, unsigned int *class,
4172 unsigned long deadline)
4173{
4174 struct ata_port *ap = link->ap;
4175 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
4176 int rc;
4177
4178 DPRINTK("ENTER\n");
4179
4180 /* do hardreset */
4181 rc = sata_link_hardreset(link, timing, deadline);
4182 if (rc) {
4183 ata_link_printk(link, KERN_ERR,
4184 "COMRESET failed (errno=%d)\n", rc);
4185 return rc;
4186 }
4187
4188 /* TODO: phy layer with polling, timeouts, etc. */
4189 if (ata_link_offline(link)) {
4190 *class = ATA_DEV_NONE;
4191 DPRINTK("EXIT, link offline\n");
4192 return 0;
4193 }
4194
4195 /* wait a while before checking status */
4196 ata_wait_after_reset(ap, deadline);
4197
4198 /* If PMP is supported, we have to do follow-up SRST. Note
4199 * that some PMPs don't send D2H Reg FIS after hardreset at
4200 * all if the first port is empty. Wait for it just for a
4201 * second and request follow-up SRST.
4202 */
4203 if (ap->flags & ATA_FLAG_PMP) {
4204 ata_wait_ready(ap, jiffies + HZ);
4205 return -EAGAIN;
4206 }
4207
4208 rc = ata_wait_ready(ap, deadline);
4209 /* link occupied, -ENODEV too is an error */
4210 if (rc) {
4211 ata_link_printk(link, KERN_ERR,
4212 "COMRESET failed (errno=%d)\n", rc);
4213 return rc;
4214 }
4215
4216 ap->ops->dev_select(ap, 0); /* probably unnecessary */
4217
4218 *class = ata_dev_try_classify(link->device, 1, NULL);
4219
4220 DPRINTK("EXIT, class=%u\n", *class);
4221 return 0;
4222}
4223
4224/**
4225 * ata_std_postreset - standard postreset callback 3541 * ata_std_postreset - standard postreset callback
4226 * @link: the target ata_link 3542 * @link: the target ata_link
4227 * @classes: classes of attached devices 3543 * @classes: classes of attached devices
@@ -4804,112 +4120,6 @@ void ata_sg_clean(struct ata_queued_cmd *qc)
4804} 4120}
4805 4121
4806/** 4122/**
4807 * ata_fill_sg - Fill PCI IDE PRD table
4808 * @qc: Metadata associated with taskfile to be transferred
4809 *
4810 * Fill PCI IDE PRD (scatter-gather) table with segments
4811 * associated with the current disk command.
4812 *
4813 * LOCKING:
4814 * spin_lock_irqsave(host lock)
4815 *
4816 */
4817static void ata_fill_sg(struct ata_queued_cmd *qc)
4818{
4819 struct ata_port *ap = qc->ap;
4820 struct scatterlist *sg;
4821 unsigned int si, pi;
4822
4823 pi = 0;
4824 for_each_sg(qc->sg, sg, qc->n_elem, si) {
4825 u32 addr, offset;
4826 u32 sg_len, len;
4827
4828 /* determine if physical DMA addr spans 64K boundary.
4829 * Note h/w doesn't support 64-bit, so we unconditionally
4830 * truncate dma_addr_t to u32.
4831 */
4832 addr = (u32) sg_dma_address(sg);
4833 sg_len = sg_dma_len(sg);
4834
4835 while (sg_len) {
4836 offset = addr & 0xffff;
4837 len = sg_len;
4838 if ((offset + sg_len) > 0x10000)
4839 len = 0x10000 - offset;
4840
4841 ap->prd[pi].addr = cpu_to_le32(addr);
4842 ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff);
4843 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
4844
4845 pi++;
4846 sg_len -= len;
4847 addr += len;
4848 }
4849 }
4850
4851 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
4852}
4853
4854/**
4855 * ata_fill_sg_dumb - Fill PCI IDE PRD table
4856 * @qc: Metadata associated with taskfile to be transferred
4857 *
4858 * Fill PCI IDE PRD (scatter-gather) table with segments
4859 * associated with the current disk command. Perform the fill
4860 * so that we avoid writing any length 64K records for
4861 * controllers that don't follow the spec.
4862 *
4863 * LOCKING:
4864 * spin_lock_irqsave(host lock)
4865 *
4866 */
4867static void ata_fill_sg_dumb(struct ata_queued_cmd *qc)
4868{
4869 struct ata_port *ap = qc->ap;
4870 struct scatterlist *sg;
4871 unsigned int si, pi;
4872
4873 pi = 0;
4874 for_each_sg(qc->sg, sg, qc->n_elem, si) {
4875 u32 addr, offset;
4876 u32 sg_len, len, blen;
4877
4878 /* determine if physical DMA addr spans 64K boundary.
4879 * Note h/w doesn't support 64-bit, so we unconditionally
4880 * truncate dma_addr_t to u32.
4881 */
4882 addr = (u32) sg_dma_address(sg);
4883 sg_len = sg_dma_len(sg);
4884
4885 while (sg_len) {
4886 offset = addr & 0xffff;
4887 len = sg_len;
4888 if ((offset + sg_len) > 0x10000)
4889 len = 0x10000 - offset;
4890
4891 blen = len & 0xffff;
4892 ap->prd[pi].addr = cpu_to_le32(addr);
4893 if (blen == 0) {
4894 /* Some PATA chipsets like the CS5530 can't
4895 cope with 0x0000 meaning 64K as the spec says */
4896 ap->prd[pi].flags_len = cpu_to_le32(0x8000);
4897 blen = 0x8000;
4898 ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000);
4899 }
4900 ap->prd[pi].flags_len = cpu_to_le32(blen);
4901 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
4902
4903 pi++;
4904 sg_len -= len;
4905 addr += len;
4906 }
4907 }
4908
4909 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
4910}
4911
4912/**
4913 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported 4123 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported
4914 * @qc: Metadata associated with taskfile to check 4124 * @qc: Metadata associated with taskfile to check
4915 * 4125 *
@@ -4969,40 +4179,6 @@ int ata_std_qc_defer(struct ata_queued_cmd *qc)
4969 return ATA_DEFER_LINK; 4179 return ATA_DEFER_LINK;
4970} 4180}
4971 4181
4972/**
4973 * ata_qc_prep - Prepare taskfile for submission
4974 * @qc: Metadata associated with taskfile to be prepared
4975 *
4976 * Prepare ATA taskfile for submission.
4977 *
4978 * LOCKING:
4979 * spin_lock_irqsave(host lock)
4980 */
4981void ata_qc_prep(struct ata_queued_cmd *qc)
4982{
4983 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
4984 return;
4985
4986 ata_fill_sg(qc);
4987}
4988
4989/**
4990 * ata_dumb_qc_prep - Prepare taskfile for submission
4991 * @qc: Metadata associated with taskfile to be prepared
4992 *
4993 * Prepare ATA taskfile for submission.
4994 *
4995 * LOCKING:
4996 * spin_lock_irqsave(host lock)
4997 */
4998void ata_dumb_qc_prep(struct ata_queued_cmd *qc)
4999{
5000 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
5001 return;
5002
5003 ata_fill_sg_dumb(qc);
5004}
5005
5006void ata_noop_qc_prep(struct ata_queued_cmd *qc) { } 4182void ata_noop_qc_prep(struct ata_queued_cmd *qc) { }
5007 4183
5008/** 4184/**
@@ -5081,698 +4257,6 @@ void swap_buf_le16(u16 *buf, unsigned int buf_words)
5081} 4257}
5082 4258
5083/** 4259/**
5084 * ata_data_xfer - Transfer data by PIO
5085 * @dev: device to target
5086 * @buf: data buffer
5087 * @buflen: buffer length
5088 * @rw: read/write
5089 *
5090 * Transfer data from/to the device data register by PIO.
5091 *
5092 * LOCKING:
5093 * Inherited from caller.
5094 *
5095 * RETURNS:
5096 * Bytes consumed.
5097 */
5098unsigned int ata_data_xfer(struct ata_device *dev, unsigned char *buf,
5099 unsigned int buflen, int rw)
5100{
5101 struct ata_port *ap = dev->link->ap;
5102 void __iomem *data_addr = ap->ioaddr.data_addr;
5103 unsigned int words = buflen >> 1;
5104
5105 /* Transfer multiple of 2 bytes */
5106 if (rw == READ)
5107 ioread16_rep(data_addr, buf, words);
5108 else
5109 iowrite16_rep(data_addr, buf, words);
5110
5111 /* Transfer trailing 1 byte, if any. */
5112 if (unlikely(buflen & 0x01)) {
5113 __le16 align_buf[1] = { 0 };
5114 unsigned char *trailing_buf = buf + buflen - 1;
5115
5116 if (rw == READ) {
5117 align_buf[0] = cpu_to_le16(ioread16(data_addr));
5118 memcpy(trailing_buf, align_buf, 1);
5119 } else {
5120 memcpy(align_buf, trailing_buf, 1);
5121 iowrite16(le16_to_cpu(align_buf[0]), data_addr);
5122 }
5123 words++;
5124 }
5125
5126 return words << 1;
5127}
5128
5129/**
5130 * ata_data_xfer_noirq - Transfer data by PIO
5131 * @dev: device to target
5132 * @buf: data buffer
5133 * @buflen: buffer length
5134 * @rw: read/write
5135 *
5136 * Transfer data from/to the device data register by PIO. Do the
5137 * transfer with interrupts disabled.
5138 *
5139 * LOCKING:
5140 * Inherited from caller.
5141 *
5142 * RETURNS:
5143 * Bytes consumed.
5144 */
5145unsigned int ata_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
5146 unsigned int buflen, int rw)
5147{
5148 unsigned long flags;
5149 unsigned int consumed;
5150
5151 local_irq_save(flags);
5152 consumed = ata_data_xfer(dev, buf, buflen, rw);
5153 local_irq_restore(flags);
5154
5155 return consumed;
5156}
5157
5158
5159/**
5160 * ata_pio_sector - Transfer a sector of data.
5161 * @qc: Command on going
5162 *
5163 * Transfer qc->sect_size bytes of data from/to the ATA device.
5164 *
5165 * LOCKING:
5166 * Inherited from caller.
5167 */
5168
5169static void ata_pio_sector(struct ata_queued_cmd *qc)
5170{
5171 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
5172 struct ata_port *ap = qc->ap;
5173 struct page *page;
5174 unsigned int offset;
5175 unsigned char *buf;
5176
5177 if (qc->curbytes == qc->nbytes - qc->sect_size)
5178 ap->hsm_task_state = HSM_ST_LAST;
5179
5180 page = sg_page(qc->cursg);
5181 offset = qc->cursg->offset + qc->cursg_ofs;
5182
5183 /* get the current page and offset */
5184 page = nth_page(page, (offset >> PAGE_SHIFT));
5185 offset %= PAGE_SIZE;
5186
5187 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
5188
5189 if (PageHighMem(page)) {
5190 unsigned long flags;
5191
5192 /* FIXME: use a bounce buffer */
5193 local_irq_save(flags);
5194 buf = kmap_atomic(page, KM_IRQ0);
5195
5196 /* do the actual data transfer */
5197 ap->ops->data_xfer(qc->dev, buf + offset, qc->sect_size, do_write);
5198
5199 kunmap_atomic(buf, KM_IRQ0);
5200 local_irq_restore(flags);
5201 } else {
5202 buf = page_address(page);
5203 ap->ops->data_xfer(qc->dev, buf + offset, qc->sect_size, do_write);
5204 }
5205
5206 qc->curbytes += qc->sect_size;
5207 qc->cursg_ofs += qc->sect_size;
5208
5209 if (qc->cursg_ofs == qc->cursg->length) {
5210 qc->cursg = sg_next(qc->cursg);
5211 qc->cursg_ofs = 0;
5212 }
5213}
5214
5215/**
5216 * ata_pio_sectors - Transfer one or many sectors.
5217 * @qc: Command on going
5218 *
5219 * Transfer one or many sectors of data from/to the
5220 * ATA device for the DRQ request.
5221 *
5222 * LOCKING:
5223 * Inherited from caller.
5224 */
5225
5226static void ata_pio_sectors(struct ata_queued_cmd *qc)
5227{
5228 if (is_multi_taskfile(&qc->tf)) {
5229 /* READ/WRITE MULTIPLE */
5230 unsigned int nsect;
5231
5232 WARN_ON(qc->dev->multi_count == 0);
5233
5234 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
5235 qc->dev->multi_count);
5236 while (nsect--)
5237 ata_pio_sector(qc);
5238 } else
5239 ata_pio_sector(qc);
5240
5241 ata_altstatus(qc->ap); /* flush */
5242}
5243
5244/**
5245 * atapi_send_cdb - Write CDB bytes to hardware
5246 * @ap: Port to which ATAPI device is attached.
5247 * @qc: Taskfile currently active
5248 *
5249 * When device has indicated its readiness to accept
5250 * a CDB, this function is called. Send the CDB.
5251 *
5252 * LOCKING:
5253 * caller.
5254 */
5255
5256static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
5257{
5258 /* send SCSI cdb */
5259 DPRINTK("send cdb\n");
5260 WARN_ON(qc->dev->cdb_len < 12);
5261
5262 ap->ops->data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
5263 ata_altstatus(ap); /* flush */
5264
5265 switch (qc->tf.protocol) {
5266 case ATAPI_PROT_PIO:
5267 ap->hsm_task_state = HSM_ST;
5268 break;
5269 case ATAPI_PROT_NODATA:
5270 ap->hsm_task_state = HSM_ST_LAST;
5271 break;
5272 case ATAPI_PROT_DMA:
5273 ap->hsm_task_state = HSM_ST_LAST;
5274 /* initiate bmdma */
5275 ap->ops->bmdma_start(qc);
5276 break;
5277 }
5278}
5279
5280/**
5281 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
5282 * @qc: Command on going
5283 * @bytes: number of bytes
5284 *
5285 * Transfer Transfer data from/to the ATAPI device.
5286 *
5287 * LOCKING:
5288 * Inherited from caller.
5289 *
5290 */
5291static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
5292{
5293 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
5294 struct ata_port *ap = qc->ap;
5295 struct ata_device *dev = qc->dev;
5296 struct ata_eh_info *ehi = &dev->link->eh_info;
5297 struct scatterlist *sg;
5298 struct page *page;
5299 unsigned char *buf;
5300 unsigned int offset, count, consumed;
5301
5302next_sg:
5303 sg = qc->cursg;
5304 if (unlikely(!sg)) {
5305 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
5306 "buf=%u cur=%u bytes=%u",
5307 qc->nbytes, qc->curbytes, bytes);
5308 return -1;
5309 }
5310
5311 page = sg_page(sg);
5312 offset = sg->offset + qc->cursg_ofs;
5313
5314 /* get the current page and offset */
5315 page = nth_page(page, (offset >> PAGE_SHIFT));
5316 offset %= PAGE_SIZE;
5317
5318 /* don't overrun current sg */
5319 count = min(sg->length - qc->cursg_ofs, bytes);
5320
5321 /* don't cross page boundaries */
5322 count = min(count, (unsigned int)PAGE_SIZE - offset);
5323
5324 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
5325
5326 if (PageHighMem(page)) {
5327 unsigned long flags;
5328
5329 /* FIXME: use bounce buffer */
5330 local_irq_save(flags);
5331 buf = kmap_atomic(page, KM_IRQ0);
5332
5333 /* do the actual data transfer */
5334 consumed = ap->ops->data_xfer(dev, buf + offset, count, rw);
5335
5336 kunmap_atomic(buf, KM_IRQ0);
5337 local_irq_restore(flags);
5338 } else {
5339 buf = page_address(page);
5340 consumed = ap->ops->data_xfer(dev, buf + offset, count, rw);
5341 }
5342
5343 bytes -= min(bytes, consumed);
5344 qc->curbytes += count;
5345 qc->cursg_ofs += count;
5346
5347 if (qc->cursg_ofs == sg->length) {
5348 qc->cursg = sg_next(qc->cursg);
5349 qc->cursg_ofs = 0;
5350 }
5351
5352 /* consumed can be larger than count only for the last transfer */
5353 WARN_ON(qc->cursg && count != consumed);
5354
5355 if (bytes)
5356 goto next_sg;
5357 return 0;
5358}
5359
5360/**
5361 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
5362 * @qc: Command on going
5363 *
5364 * Transfer Transfer data from/to the ATAPI device.
5365 *
5366 * LOCKING:
5367 * Inherited from caller.
5368 */
5369
5370static void atapi_pio_bytes(struct ata_queued_cmd *qc)
5371{
5372 struct ata_port *ap = qc->ap;
5373 struct ata_device *dev = qc->dev;
5374 struct ata_eh_info *ehi = &dev->link->eh_info;
5375 unsigned int ireason, bc_lo, bc_hi, bytes;
5376 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
5377
5378 /* Abuse qc->result_tf for temp storage of intermediate TF
5379 * here to save some kernel stack usage.
5380 * For normal completion, qc->result_tf is not relevant. For
5381 * error, qc->result_tf is later overwritten by ata_qc_complete().
5382 * So, the correctness of qc->result_tf is not affected.
5383 */
5384 ap->ops->tf_read(ap, &qc->result_tf);
5385 ireason = qc->result_tf.nsect;
5386 bc_lo = qc->result_tf.lbam;
5387 bc_hi = qc->result_tf.lbah;
5388 bytes = (bc_hi << 8) | bc_lo;
5389
5390 /* shall be cleared to zero, indicating xfer of data */
5391 if (unlikely(ireason & (1 << 0)))
5392 goto atapi_check;
5393
5394 /* make sure transfer direction matches expected */
5395 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
5396 if (unlikely(do_write != i_write))
5397 goto atapi_check;
5398
5399 if (unlikely(!bytes))
5400 goto atapi_check;
5401
5402 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
5403
5404 if (unlikely(__atapi_pio_bytes(qc, bytes)))
5405 goto err_out;
5406 ata_altstatus(ap); /* flush */
5407
5408 return;
5409
5410 atapi_check:
5411 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
5412 ireason, bytes);
5413 err_out:
5414 qc->err_mask |= AC_ERR_HSM;
5415 ap->hsm_task_state = HSM_ST_ERR;
5416}
5417
5418/**
5419 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
5420 * @ap: the target ata_port
5421 * @qc: qc on going
5422 *
5423 * RETURNS:
5424 * 1 if ok in workqueue, 0 otherwise.
5425 */
5426
5427static inline int ata_hsm_ok_in_wq(struct ata_port *ap, struct ata_queued_cmd *qc)
5428{
5429 if (qc->tf.flags & ATA_TFLAG_POLLING)
5430 return 1;
5431
5432 if (ap->hsm_task_state == HSM_ST_FIRST) {
5433 if (qc->tf.protocol == ATA_PROT_PIO &&
5434 (qc->tf.flags & ATA_TFLAG_WRITE))
5435 return 1;
5436
5437 if (ata_is_atapi(qc->tf.protocol) &&
5438 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
5439 return 1;
5440 }
5441
5442 return 0;
5443}
5444
5445/**
5446 * ata_hsm_qc_complete - finish a qc running on standard HSM
5447 * @qc: Command to complete
5448 * @in_wq: 1 if called from workqueue, 0 otherwise
5449 *
5450 * Finish @qc which is running on standard HSM.
5451 *
5452 * LOCKING:
5453 * If @in_wq is zero, spin_lock_irqsave(host lock).
5454 * Otherwise, none on entry and grabs host lock.
5455 */
5456static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
5457{
5458 struct ata_port *ap = qc->ap;
5459 unsigned long flags;
5460
5461 if (ap->ops->error_handler) {
5462 if (in_wq) {
5463 spin_lock_irqsave(ap->lock, flags);
5464
5465 /* EH might have kicked in while host lock is
5466 * released.
5467 */
5468 qc = ata_qc_from_tag(ap, qc->tag);
5469 if (qc) {
5470 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
5471 ap->ops->irq_on(ap);
5472 ata_qc_complete(qc);
5473 } else
5474 ata_port_freeze(ap);
5475 }
5476
5477 spin_unlock_irqrestore(ap->lock, flags);
5478 } else {
5479 if (likely(!(qc->err_mask & AC_ERR_HSM)))
5480 ata_qc_complete(qc);
5481 else
5482 ata_port_freeze(ap);
5483 }
5484 } else {
5485 if (in_wq) {
5486 spin_lock_irqsave(ap->lock, flags);
5487 ap->ops->irq_on(ap);
5488 ata_qc_complete(qc);
5489 spin_unlock_irqrestore(ap->lock, flags);
5490 } else
5491 ata_qc_complete(qc);
5492 }
5493}
5494
5495/**
5496 * ata_hsm_move - move the HSM to the next state.
5497 * @ap: the target ata_port
5498 * @qc: qc on going
5499 * @status: current device status
5500 * @in_wq: 1 if called from workqueue, 0 otherwise
5501 *
5502 * RETURNS:
5503 * 1 when poll next status needed, 0 otherwise.
5504 */
5505int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
5506 u8 status, int in_wq)
5507{
5508 unsigned long flags = 0;
5509 int poll_next;
5510
5511 WARN_ON((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
5512
5513 /* Make sure ata_qc_issue_prot() does not throw things
5514 * like DMA polling into the workqueue. Notice that
5515 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
5516 */
5517 WARN_ON(in_wq != ata_hsm_ok_in_wq(ap, qc));
5518
5519fsm_start:
5520 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
5521 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
5522
5523 switch (ap->hsm_task_state) {
5524 case HSM_ST_FIRST:
5525 /* Send first data block or PACKET CDB */
5526
5527 /* If polling, we will stay in the work queue after
5528 * sending the data. Otherwise, interrupt handler
5529 * takes over after sending the data.
5530 */
5531 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
5532
5533 /* check device status */
5534 if (unlikely((status & ATA_DRQ) == 0)) {
5535 /* handle BSY=0, DRQ=0 as error */
5536 if (likely(status & (ATA_ERR | ATA_DF)))
5537 /* device stops HSM for abort/error */
5538 qc->err_mask |= AC_ERR_DEV;
5539 else
5540 /* HSM violation. Let EH handle this */
5541 qc->err_mask |= AC_ERR_HSM;
5542
5543 ap->hsm_task_state = HSM_ST_ERR;
5544 goto fsm_start;
5545 }
5546
5547 /* Device should not ask for data transfer (DRQ=1)
5548 * when it finds something wrong.
5549 * We ignore DRQ here and stop the HSM by
5550 * changing hsm_task_state to HSM_ST_ERR and
5551 * let the EH abort the command or reset the device.
5552 */
5553 if (unlikely(status & (ATA_ERR | ATA_DF))) {
5554 /* Some ATAPI tape drives forget to clear the ERR bit
5555 * when doing the next command (mostly request sense).
5556 * We ignore ERR here to workaround and proceed sending
5557 * the CDB.
5558 */
5559 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
5560 ata_port_printk(ap, KERN_WARNING,
5561 "DRQ=1 with device error, "
5562 "dev_stat 0x%X\n", status);
5563 qc->err_mask |= AC_ERR_HSM;
5564 ap->hsm_task_state = HSM_ST_ERR;
5565 goto fsm_start;
5566 }
5567 }
5568
5569 /* Send the CDB (atapi) or the first data block (ata pio out).
5570 * During the state transition, interrupt handler shouldn't
5571 * be invoked before the data transfer is complete and
5572 * hsm_task_state is changed. Hence, the following locking.
5573 */
5574 if (in_wq)
5575 spin_lock_irqsave(ap->lock, flags);
5576
5577 if (qc->tf.protocol == ATA_PROT_PIO) {
5578 /* PIO data out protocol.
5579 * send first data block.
5580 */
5581
5582 /* ata_pio_sectors() might change the state
5583 * to HSM_ST_LAST. so, the state is changed here
5584 * before ata_pio_sectors().
5585 */
5586 ap->hsm_task_state = HSM_ST;
5587 ata_pio_sectors(qc);
5588 } else
5589 /* send CDB */
5590 atapi_send_cdb(ap, qc);
5591
5592 if (in_wq)
5593 spin_unlock_irqrestore(ap->lock, flags);
5594
5595 /* if polling, ata_pio_task() handles the rest.
5596 * otherwise, interrupt handler takes over from here.
5597 */
5598 break;
5599
5600 case HSM_ST:
5601 /* complete command or read/write the data register */
5602 if (qc->tf.protocol == ATAPI_PROT_PIO) {
5603 /* ATAPI PIO protocol */
5604 if ((status & ATA_DRQ) == 0) {
5605 /* No more data to transfer or device error.
5606 * Device error will be tagged in HSM_ST_LAST.
5607 */
5608 ap->hsm_task_state = HSM_ST_LAST;
5609 goto fsm_start;
5610 }
5611
5612 /* Device should not ask for data transfer (DRQ=1)
5613 * when it finds something wrong.
5614 * We ignore DRQ here and stop the HSM by
5615 * changing hsm_task_state to HSM_ST_ERR and
5616 * let the EH abort the command or reset the device.
5617 */
5618 if (unlikely(status & (ATA_ERR | ATA_DF))) {
5619 ata_port_printk(ap, KERN_WARNING, "DRQ=1 with "
5620 "device error, dev_stat 0x%X\n",
5621 status);
5622 qc->err_mask |= AC_ERR_HSM;
5623 ap->hsm_task_state = HSM_ST_ERR;
5624 goto fsm_start;
5625 }
5626
5627 atapi_pio_bytes(qc);
5628
5629 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
5630 /* bad ireason reported by device */
5631 goto fsm_start;
5632
5633 } else {
5634 /* ATA PIO protocol */
5635 if (unlikely((status & ATA_DRQ) == 0)) {
5636 /* handle BSY=0, DRQ=0 as error */
5637 if (likely(status & (ATA_ERR | ATA_DF)))
5638 /* device stops HSM for abort/error */
5639 qc->err_mask |= AC_ERR_DEV;
5640 else
5641 /* HSM violation. Let EH handle this.
5642 * Phantom devices also trigger this
5643 * condition. Mark hint.
5644 */
5645 qc->err_mask |= AC_ERR_HSM |
5646 AC_ERR_NODEV_HINT;
5647
5648 ap->hsm_task_state = HSM_ST_ERR;
5649 goto fsm_start;
5650 }
5651
5652 /* For PIO reads, some devices may ask for
5653 * data transfer (DRQ=1) alone with ERR=1.
5654 * We respect DRQ here and transfer one
5655 * block of junk data before changing the
5656 * hsm_task_state to HSM_ST_ERR.
5657 *
5658 * For PIO writes, ERR=1 DRQ=1 doesn't make
5659 * sense since the data block has been
5660 * transferred to the device.
5661 */
5662 if (unlikely(status & (ATA_ERR | ATA_DF))) {
5663 /* data might be corrputed */
5664 qc->err_mask |= AC_ERR_DEV;
5665
5666 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
5667 ata_pio_sectors(qc);
5668 status = ata_wait_idle(ap);
5669 }
5670
5671 if (status & (ATA_BUSY | ATA_DRQ))
5672 qc->err_mask |= AC_ERR_HSM;
5673
5674 /* ata_pio_sectors() might change the
5675 * state to HSM_ST_LAST. so, the state
5676 * is changed after ata_pio_sectors().
5677 */
5678 ap->hsm_task_state = HSM_ST_ERR;
5679 goto fsm_start;
5680 }
5681
5682 ata_pio_sectors(qc);
5683
5684 if (ap->hsm_task_state == HSM_ST_LAST &&
5685 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
5686 /* all data read */
5687 status = ata_wait_idle(ap);
5688 goto fsm_start;
5689 }
5690 }
5691
5692 poll_next = 1;
5693 break;
5694
5695 case HSM_ST_LAST:
5696 if (unlikely(!ata_ok(status))) {
5697 qc->err_mask |= __ac_err_mask(status);
5698 ap->hsm_task_state = HSM_ST_ERR;
5699 goto fsm_start;
5700 }
5701
5702 /* no more data to transfer */
5703 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
5704 ap->print_id, qc->dev->devno, status);
5705
5706 WARN_ON(qc->err_mask);
5707
5708 ap->hsm_task_state = HSM_ST_IDLE;
5709
5710 /* complete taskfile transaction */
5711 ata_hsm_qc_complete(qc, in_wq);
5712
5713 poll_next = 0;
5714 break;
5715
5716 case HSM_ST_ERR:
5717 /* make sure qc->err_mask is available to
5718 * know what's wrong and recover
5719 */
5720 WARN_ON(qc->err_mask == 0);
5721
5722 ap->hsm_task_state = HSM_ST_IDLE;
5723
5724 /* complete taskfile transaction */
5725 ata_hsm_qc_complete(qc, in_wq);
5726
5727 poll_next = 0;
5728 break;
5729 default:
5730 poll_next = 0;
5731 BUG();
5732 }
5733
5734 return poll_next;
5735}
5736
5737static void ata_pio_task(struct work_struct *work)
5738{
5739 struct ata_port *ap =
5740 container_of(work, struct ata_port, port_task.work);
5741 struct ata_queued_cmd *qc = ap->port_task_data;
5742 u8 status;
5743 int poll_next;
5744
5745fsm_start:
5746 WARN_ON(ap->hsm_task_state == HSM_ST_IDLE);
5747
5748 /*
5749 * This is purely heuristic. This is a fast path.
5750 * Sometimes when we enter, BSY will be cleared in
5751 * a chk-status or two. If not, the drive is probably seeking
5752 * or something. Snooze for a couple msecs, then
5753 * chk-status again. If still busy, queue delayed work.
5754 */
5755 status = ata_busy_wait(ap, ATA_BUSY, 5);
5756 if (status & ATA_BUSY) {
5757 msleep(2);
5758 status = ata_busy_wait(ap, ATA_BUSY, 10);
5759 if (status & ATA_BUSY) {
5760 ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
5761 return;
5762 }
5763 }
5764
5765 /* move the HSM */
5766 poll_next = ata_hsm_move(ap, qc, status, 1);
5767
5768 /* another command or interrupt handler
5769 * may be running at this point.
5770 */
5771 if (poll_next)
5772 goto fsm_start;
5773}
5774
5775/**
5776 * ata_qc_new - Request an available ATA command, for queueing 4260 * ata_qc_new - Request an available ATA command, for queueing
5777 * @ap: Port associated with device @dev 4261 * @ap: Port associated with device @dev
5778 * @dev: Device from whom we request an available command structure 4262 * @dev: Device from whom we request an available command structure
@@ -6122,285 +4606,6 @@ err:
6122} 4606}
6123 4607
6124/** 4608/**
6125 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
6126 * @qc: command to issue to device
6127 *
6128 * Using various libata functions and hooks, this function
6129 * starts an ATA command. ATA commands are grouped into
6130 * classes called "protocols", and issuing each type of protocol
6131 * is slightly different.
6132 *
6133 * May be used as the qc_issue() entry in ata_port_operations.
6134 *
6135 * LOCKING:
6136 * spin_lock_irqsave(host lock)
6137 *
6138 * RETURNS:
6139 * Zero on success, AC_ERR_* mask on failure
6140 */
6141
6142unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
6143{
6144 struct ata_port *ap = qc->ap;
6145
6146 /* Use polling pio if the LLD doesn't handle
6147 * interrupt driven pio and atapi CDB interrupt.
6148 */
6149 if (ap->flags & ATA_FLAG_PIO_POLLING) {
6150 switch (qc->tf.protocol) {
6151 case ATA_PROT_PIO:
6152 case ATA_PROT_NODATA:
6153 case ATAPI_PROT_PIO:
6154 case ATAPI_PROT_NODATA:
6155 qc->tf.flags |= ATA_TFLAG_POLLING;
6156 break;
6157 case ATAPI_PROT_DMA:
6158 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
6159 /* see ata_dma_blacklisted() */
6160 BUG();
6161 break;
6162 default:
6163 break;
6164 }
6165 }
6166
6167 /* select the device */
6168 ata_dev_select(ap, qc->dev->devno, 1, 0);
6169
6170 /* start the command */
6171 switch (qc->tf.protocol) {
6172 case ATA_PROT_NODATA:
6173 if (qc->tf.flags & ATA_TFLAG_POLLING)
6174 ata_qc_set_polling(qc);
6175
6176 ata_tf_to_host(ap, &qc->tf);
6177 ap->hsm_task_state = HSM_ST_LAST;
6178
6179 if (qc->tf.flags & ATA_TFLAG_POLLING)
6180 ata_pio_queue_task(ap, qc, 0);
6181
6182 break;
6183
6184 case ATA_PROT_DMA:
6185 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
6186
6187 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
6188 ap->ops->bmdma_setup(qc); /* set up bmdma */
6189 ap->ops->bmdma_start(qc); /* initiate bmdma */
6190 ap->hsm_task_state = HSM_ST_LAST;
6191 break;
6192
6193 case ATA_PROT_PIO:
6194 if (qc->tf.flags & ATA_TFLAG_POLLING)
6195 ata_qc_set_polling(qc);
6196
6197 ata_tf_to_host(ap, &qc->tf);
6198
6199 if (qc->tf.flags & ATA_TFLAG_WRITE) {
6200 /* PIO data out protocol */
6201 ap->hsm_task_state = HSM_ST_FIRST;
6202 ata_pio_queue_task(ap, qc, 0);
6203
6204 /* always send first data block using
6205 * the ata_pio_task() codepath.
6206 */
6207 } else {
6208 /* PIO data in protocol */
6209 ap->hsm_task_state = HSM_ST;
6210
6211 if (qc->tf.flags & ATA_TFLAG_POLLING)
6212 ata_pio_queue_task(ap, qc, 0);
6213
6214 /* if polling, ata_pio_task() handles the rest.
6215 * otherwise, interrupt handler takes over from here.
6216 */
6217 }
6218
6219 break;
6220
6221 case ATAPI_PROT_PIO:
6222 case ATAPI_PROT_NODATA:
6223 if (qc->tf.flags & ATA_TFLAG_POLLING)
6224 ata_qc_set_polling(qc);
6225
6226 ata_tf_to_host(ap, &qc->tf);
6227
6228 ap->hsm_task_state = HSM_ST_FIRST;
6229
6230 /* send cdb by polling if no cdb interrupt */
6231 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
6232 (qc->tf.flags & ATA_TFLAG_POLLING))
6233 ata_pio_queue_task(ap, qc, 0);
6234 break;
6235
6236 case ATAPI_PROT_DMA:
6237 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
6238
6239 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
6240 ap->ops->bmdma_setup(qc); /* set up bmdma */
6241 ap->hsm_task_state = HSM_ST_FIRST;
6242
6243 /* send cdb by polling if no cdb interrupt */
6244 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
6245 ata_pio_queue_task(ap, qc, 0);
6246 break;
6247
6248 default:
6249 WARN_ON(1);
6250 return AC_ERR_SYSTEM;
6251 }
6252
6253 return 0;
6254}
6255
6256/**
6257 * ata_host_intr - Handle host interrupt for given (port, task)
6258 * @ap: Port on which interrupt arrived (possibly...)
6259 * @qc: Taskfile currently active in engine
6260 *
6261 * Handle host interrupt for given queued command. Currently,
6262 * only DMA interrupts are handled. All other commands are
6263 * handled via polling with interrupts disabled (nIEN bit).
6264 *
6265 * LOCKING:
6266 * spin_lock_irqsave(host lock)
6267 *
6268 * RETURNS:
6269 * One if interrupt was handled, zero if not (shared irq).
6270 */
6271
6272inline unsigned int ata_host_intr(struct ata_port *ap,
6273 struct ata_queued_cmd *qc)
6274{
6275 struct ata_eh_info *ehi = &ap->link.eh_info;
6276 u8 status, host_stat = 0;
6277
6278 VPRINTK("ata%u: protocol %d task_state %d\n",
6279 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
6280
6281 /* Check whether we are expecting interrupt in this state */
6282 switch (ap->hsm_task_state) {
6283 case HSM_ST_FIRST:
6284 /* Some pre-ATAPI-4 devices assert INTRQ
6285 * at this state when ready to receive CDB.
6286 */
6287
6288 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
6289 * The flag was turned on only for atapi devices. No
6290 * need to check ata_is_atapi(qc->tf.protocol) again.
6291 */
6292 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
6293 goto idle_irq;
6294 break;
6295 case HSM_ST_LAST:
6296 if (qc->tf.protocol == ATA_PROT_DMA ||
6297 qc->tf.protocol == ATAPI_PROT_DMA) {
6298 /* check status of DMA engine */
6299 host_stat = ap->ops->bmdma_status(ap);
6300 VPRINTK("ata%u: host_stat 0x%X\n",
6301 ap->print_id, host_stat);
6302
6303 /* if it's not our irq... */
6304 if (!(host_stat & ATA_DMA_INTR))
6305 goto idle_irq;
6306
6307 /* before we do anything else, clear DMA-Start bit */
6308 ap->ops->bmdma_stop(qc);
6309
6310 if (unlikely(host_stat & ATA_DMA_ERR)) {
6311 /* error when transfering data to/from memory */
6312 qc->err_mask |= AC_ERR_HOST_BUS;
6313 ap->hsm_task_state = HSM_ST_ERR;
6314 }
6315 }
6316 break;
6317 case HSM_ST:
6318 break;
6319 default:
6320 goto idle_irq;
6321 }
6322
6323 /* check altstatus */
6324 status = ata_altstatus(ap);
6325 if (status & ATA_BUSY)
6326 goto idle_irq;
6327
6328 /* check main status, clearing INTRQ */
6329 status = ata_chk_status(ap);
6330 if (unlikely(status & ATA_BUSY))
6331 goto idle_irq;
6332
6333 /* ack bmdma irq events */
6334 ap->ops->irq_clear(ap);
6335
6336 ata_hsm_move(ap, qc, status, 0);
6337
6338 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
6339 qc->tf.protocol == ATAPI_PROT_DMA))
6340 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
6341
6342 return 1; /* irq handled */
6343
6344idle_irq:
6345 ap->stats.idle_irq++;
6346
6347#ifdef ATA_IRQ_TRAP
6348 if ((ap->stats.idle_irq % 1000) == 0) {
6349 ata_chk_status(ap);
6350 ap->ops->irq_clear(ap);
6351 ata_port_printk(ap, KERN_WARNING, "irq trap\n");
6352 return 1;
6353 }
6354#endif
6355 return 0; /* irq not handled */
6356}
6357
6358/**
6359 * ata_interrupt - Default ATA host interrupt handler
6360 * @irq: irq line (unused)
6361 * @dev_instance: pointer to our ata_host information structure
6362 *
6363 * Default interrupt handler for PCI IDE devices. Calls
6364 * ata_host_intr() for each port that is not disabled.
6365 *
6366 * LOCKING:
6367 * Obtains host lock during operation.
6368 *
6369 * RETURNS:
6370 * IRQ_NONE or IRQ_HANDLED.
6371 */
6372
6373irqreturn_t ata_interrupt(int irq, void *dev_instance)
6374{
6375 struct ata_host *host = dev_instance;
6376 unsigned int i;
6377 unsigned int handled = 0;
6378 unsigned long flags;
6379
6380 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
6381 spin_lock_irqsave(&host->lock, flags);
6382
6383 for (i = 0; i < host->n_ports; i++) {
6384 struct ata_port *ap;
6385
6386 ap = host->ports[i];
6387 if (ap &&
6388 !(ap->flags & ATA_FLAG_DISABLED)) {
6389 struct ata_queued_cmd *qc;
6390
6391 qc = ata_qc_from_tag(ap, ap->link.active_tag);
6392 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
6393 (qc->flags & ATA_QCFLAG_ACTIVE))
6394 handled |= ata_host_intr(ap, qc);
6395 }
6396 }
6397
6398 spin_unlock_irqrestore(&host->lock, flags);
6399
6400 return IRQ_RETVAL(handled);
6401}
6402
6403/**
6404 * sata_scr_valid - test whether SCRs are accessible 4609 * sata_scr_valid - test whether SCRs are accessible
6405 * @link: ATA link to test SCR accessibility for 4610 * @link: ATA link to test SCR accessibility for
6406 * 4611 *
@@ -7432,33 +5637,6 @@ void ata_host_detach(struct ata_host *host)
7432 ata_acpi_dissociate(host); 5637 ata_acpi_dissociate(host);
7433} 5638}
7434 5639
7435/**
7436 * ata_std_ports - initialize ioaddr with standard port offsets.
7437 * @ioaddr: IO address structure to be initialized
7438 *
7439 * Utility function which initializes data_addr, error_addr,
7440 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
7441 * device_addr, status_addr, and command_addr to standard offsets
7442 * relative to cmd_addr.
7443 *
7444 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
7445 */
7446
7447void ata_std_ports(struct ata_ioports *ioaddr)
7448{
7449 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
7450 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
7451 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
7452 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
7453 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
7454 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
7455 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
7456 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
7457 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
7458 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
7459}
7460
7461
7462#ifdef CONFIG_PCI 5640#ifdef CONFIG_PCI
7463 5641
7464/** 5642/**
@@ -7890,12 +6068,9 @@ EXPORT_SYMBOL_GPL(sata_deb_timing_long);
7890EXPORT_SYMBOL_GPL(ata_base_port_ops); 6068EXPORT_SYMBOL_GPL(ata_base_port_ops);
7891EXPORT_SYMBOL_GPL(sata_port_ops); 6069EXPORT_SYMBOL_GPL(sata_port_ops);
7892EXPORT_SYMBOL_GPL(sata_pmp_port_ops); 6070EXPORT_SYMBOL_GPL(sata_pmp_port_ops);
7893EXPORT_SYMBOL_GPL(ata_sff_port_ops);
7894EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
7895EXPORT_SYMBOL_GPL(ata_dummy_port_ops); 6071EXPORT_SYMBOL_GPL(ata_dummy_port_ops);
7896EXPORT_SYMBOL_GPL(ata_dummy_port_info); 6072EXPORT_SYMBOL_GPL(ata_dummy_port_info);
7897EXPORT_SYMBOL_GPL(ata_std_bios_param); 6073EXPORT_SYMBOL_GPL(ata_std_bios_param);
7898EXPORT_SYMBOL_GPL(ata_std_ports);
7899EXPORT_SYMBOL_GPL(ata_host_init); 6074EXPORT_SYMBOL_GPL(ata_host_init);
7900EXPORT_SYMBOL_GPL(ata_host_alloc); 6075EXPORT_SYMBOL_GPL(ata_host_alloc);
7901EXPORT_SYMBOL_GPL(ata_host_alloc_pinfo); 6076EXPORT_SYMBOL_GPL(ata_host_alloc_pinfo);
@@ -7904,14 +6079,9 @@ EXPORT_SYMBOL_GPL(ata_host_register);
7904EXPORT_SYMBOL_GPL(ata_host_activate); 6079EXPORT_SYMBOL_GPL(ata_host_activate);
7905EXPORT_SYMBOL_GPL(ata_host_detach); 6080EXPORT_SYMBOL_GPL(ata_host_detach);
7906EXPORT_SYMBOL_GPL(ata_sg_init); 6081EXPORT_SYMBOL_GPL(ata_sg_init);
7907EXPORT_SYMBOL_GPL(ata_hsm_move);
7908EXPORT_SYMBOL_GPL(ata_qc_complete); 6082EXPORT_SYMBOL_GPL(ata_qc_complete);
7909EXPORT_SYMBOL_GPL(ata_qc_complete_multiple); 6083EXPORT_SYMBOL_GPL(ata_qc_complete_multiple);
7910EXPORT_SYMBOL_GPL(ata_qc_issue_prot);
7911EXPORT_SYMBOL_GPL(ata_tf_load);
7912EXPORT_SYMBOL_GPL(ata_tf_read);
7913EXPORT_SYMBOL_GPL(ata_noop_dev_select); 6084EXPORT_SYMBOL_GPL(ata_noop_dev_select);
7914EXPORT_SYMBOL_GPL(ata_std_dev_select);
7915EXPORT_SYMBOL_GPL(sata_print_link_status); 6085EXPORT_SYMBOL_GPL(sata_print_link_status);
7916EXPORT_SYMBOL_GPL(atapi_cmd_type); 6086EXPORT_SYMBOL_GPL(atapi_cmd_type);
7917EXPORT_SYMBOL_GPL(ata_tf_to_fis); 6087EXPORT_SYMBOL_GPL(ata_tf_to_fis);
@@ -7923,54 +6093,27 @@ EXPORT_SYMBOL_GPL(ata_xfer_mode2mask);
7923EXPORT_SYMBOL_GPL(ata_xfer_mode2shift); 6093EXPORT_SYMBOL_GPL(ata_xfer_mode2shift);
7924EXPORT_SYMBOL_GPL(ata_mode_string); 6094EXPORT_SYMBOL_GPL(ata_mode_string);
7925EXPORT_SYMBOL_GPL(ata_id_xfermask); 6095EXPORT_SYMBOL_GPL(ata_id_xfermask);
7926EXPORT_SYMBOL_GPL(ata_check_status);
7927EXPORT_SYMBOL_GPL(ata_altstatus);
7928EXPORT_SYMBOL_GPL(ata_exec_command);
7929EXPORT_SYMBOL_GPL(ata_port_start); 6096EXPORT_SYMBOL_GPL(ata_port_start);
7930EXPORT_SYMBOL_GPL(ata_sff_port_start);
7931EXPORT_SYMBOL_GPL(ata_interrupt);
7932EXPORT_SYMBOL_GPL(ata_do_set_mode); 6097EXPORT_SYMBOL_GPL(ata_do_set_mode);
7933EXPORT_SYMBOL_GPL(ata_data_xfer);
7934EXPORT_SYMBOL_GPL(ata_data_xfer_noirq);
7935EXPORT_SYMBOL_GPL(ata_std_qc_defer); 6098EXPORT_SYMBOL_GPL(ata_std_qc_defer);
7936EXPORT_SYMBOL_GPL(ata_qc_prep);
7937EXPORT_SYMBOL_GPL(ata_dumb_qc_prep);
7938EXPORT_SYMBOL_GPL(ata_noop_qc_prep); 6099EXPORT_SYMBOL_GPL(ata_noop_qc_prep);
7939EXPORT_SYMBOL_GPL(ata_bmdma_setup);
7940EXPORT_SYMBOL_GPL(ata_bmdma_start);
7941EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
7942EXPORT_SYMBOL_GPL(ata_noop_irq_clear); 6100EXPORT_SYMBOL_GPL(ata_noop_irq_clear);
7943EXPORT_SYMBOL_GPL(ata_bmdma_status);
7944EXPORT_SYMBOL_GPL(ata_bmdma_stop);
7945EXPORT_SYMBOL_GPL(ata_bmdma_freeze);
7946EXPORT_SYMBOL_GPL(ata_bmdma_thaw);
7947EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
7948EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
7949EXPORT_SYMBOL_GPL(ata_port_probe); 6101EXPORT_SYMBOL_GPL(ata_port_probe);
7950EXPORT_SYMBOL_GPL(ata_dev_disable); 6102EXPORT_SYMBOL_GPL(ata_dev_disable);
7951EXPORT_SYMBOL_GPL(sata_set_spd); 6103EXPORT_SYMBOL_GPL(sata_set_spd);
7952EXPORT_SYMBOL_GPL(sata_link_debounce); 6104EXPORT_SYMBOL_GPL(sata_link_debounce);
7953EXPORT_SYMBOL_GPL(sata_link_resume); 6105EXPORT_SYMBOL_GPL(sata_link_resume);
7954EXPORT_SYMBOL_GPL(ata_bus_reset);
7955EXPORT_SYMBOL_GPL(ata_std_prereset);
7956EXPORT_SYMBOL_GPL(ata_std_softreset);
7957EXPORT_SYMBOL_GPL(sata_link_hardreset); 6106EXPORT_SYMBOL_GPL(sata_link_hardreset);
7958EXPORT_SYMBOL_GPL(sata_std_hardreset);
7959EXPORT_SYMBOL_GPL(ata_std_postreset);
7960EXPORT_SYMBOL_GPL(ata_dev_classify); 6107EXPORT_SYMBOL_GPL(ata_dev_classify);
7961EXPORT_SYMBOL_GPL(ata_dev_pair); 6108EXPORT_SYMBOL_GPL(ata_dev_pair);
7962EXPORT_SYMBOL_GPL(ata_port_disable); 6109EXPORT_SYMBOL_GPL(ata_port_disable);
7963EXPORT_SYMBOL_GPL(ata_ratelimit); 6110EXPORT_SYMBOL_GPL(ata_ratelimit);
7964EXPORT_SYMBOL_GPL(ata_wait_register); 6111EXPORT_SYMBOL_GPL(ata_wait_register);
7965EXPORT_SYMBOL_GPL(ata_busy_sleep);
7966EXPORT_SYMBOL_GPL(ata_wait_after_reset);
7967EXPORT_SYMBOL_GPL(ata_wait_ready);
7968EXPORT_SYMBOL_GPL(ata_scsi_ioctl); 6112EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
7969EXPORT_SYMBOL_GPL(ata_scsi_queuecmd); 6113EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
7970EXPORT_SYMBOL_GPL(ata_scsi_slave_config); 6114EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
7971EXPORT_SYMBOL_GPL(ata_scsi_slave_destroy); 6115EXPORT_SYMBOL_GPL(ata_scsi_slave_destroy);
7972EXPORT_SYMBOL_GPL(ata_scsi_change_queue_depth); 6116EXPORT_SYMBOL_GPL(ata_scsi_change_queue_depth);
7973EXPORT_SYMBOL_GPL(ata_host_intr);
7974EXPORT_SYMBOL_GPL(sata_scr_valid); 6117EXPORT_SYMBOL_GPL(sata_scr_valid);
7975EXPORT_SYMBOL_GPL(sata_scr_read); 6118EXPORT_SYMBOL_GPL(sata_scr_read);
7976EXPORT_SYMBOL_GPL(sata_scr_write); 6119EXPORT_SYMBOL_GPL(sata_scr_write);
@@ -7993,11 +6136,6 @@ EXPORT_SYMBOL_GPL(ata_timing_cycle2mode);
7993 6136
7994#ifdef CONFIG_PCI 6137#ifdef CONFIG_PCI
7995EXPORT_SYMBOL_GPL(pci_test_config_bits); 6138EXPORT_SYMBOL_GPL(pci_test_config_bits);
7996EXPORT_SYMBOL_GPL(ata_pci_init_sff_host);
7997EXPORT_SYMBOL_GPL(ata_pci_init_bmdma);
7998EXPORT_SYMBOL_GPL(ata_pci_prepare_sff_host);
7999EXPORT_SYMBOL_GPL(ata_pci_activate_sff_host);
8000EXPORT_SYMBOL_GPL(ata_pci_init_one);
8001EXPORT_SYMBOL_GPL(ata_pci_remove_one); 6139EXPORT_SYMBOL_GPL(ata_pci_remove_one);
8002#ifdef CONFIG_PM 6140#ifdef CONFIG_PM
8003EXPORT_SYMBOL_GPL(ata_pci_device_do_suspend); 6141EXPORT_SYMBOL_GPL(ata_pci_device_do_suspend);
@@ -8005,8 +6143,6 @@ EXPORT_SYMBOL_GPL(ata_pci_device_do_resume);
8005EXPORT_SYMBOL_GPL(ata_pci_device_suspend); 6143EXPORT_SYMBOL_GPL(ata_pci_device_suspend);
8006EXPORT_SYMBOL_GPL(ata_pci_device_resume); 6144EXPORT_SYMBOL_GPL(ata_pci_device_resume);
8007#endif /* CONFIG_PM */ 6145#endif /* CONFIG_PM */
8008EXPORT_SYMBOL_GPL(ata_pci_default_filter);
8009EXPORT_SYMBOL_GPL(ata_pci_clear_simplex);
8010#endif /* CONFIG_PCI */ 6146#endif /* CONFIG_PCI */
8011 6147
8012EXPORT_SYMBOL_GPL(sata_pmp_qc_defer_cmd_switch); 6148EXPORT_SYMBOL_GPL(sata_pmp_qc_defer_cmd_switch);
@@ -8033,8 +6169,6 @@ EXPORT_SYMBOL_GPL(ata_eh_qc_complete);
8033EXPORT_SYMBOL_GPL(ata_eh_qc_retry); 6169EXPORT_SYMBOL_GPL(ata_eh_qc_retry);
8034EXPORT_SYMBOL_GPL(ata_do_eh); 6170EXPORT_SYMBOL_GPL(ata_do_eh);
8035EXPORT_SYMBOL_GPL(ata_std_error_handler); 6171EXPORT_SYMBOL_GPL(ata_std_error_handler);
8036EXPORT_SYMBOL_GPL(ata_irq_on);
8037EXPORT_SYMBOL_GPL(ata_dev_try_classify);
8038 6172
8039EXPORT_SYMBOL_GPL(ata_cable_40wire); 6173EXPORT_SYMBOL_GPL(ata_cable_40wire);
8040EXPORT_SYMBOL_GPL(ata_cable_80wire); 6174EXPORT_SYMBOL_GPL(ata_cable_80wire);
diff --git a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c
index 40645ed125b1..840ae6da59bc 100644
--- a/drivers/ata/libata-sff.c
+++ b/drivers/ata/libata-sff.c
@@ -35,9 +35,185 @@
35#include <linux/kernel.h> 35#include <linux/kernel.h>
36#include <linux/pci.h> 36#include <linux/pci.h>
37#include <linux/libata.h> 37#include <linux/libata.h>
38#include <linux/highmem.h>
38 39
39#include "libata.h" 40#include "libata.h"
40 41
42const struct ata_port_operations ata_sff_port_ops = {
43 .inherits = &ata_base_port_ops,
44
45 .qc_prep = ata_qc_prep,
46 .qc_issue = ata_qc_issue_prot,
47
48 .freeze = ata_bmdma_freeze,
49 .thaw = ata_bmdma_thaw,
50 .softreset = ata_std_softreset,
51 .error_handler = ata_bmdma_error_handler,
52 .post_internal_cmd = ata_bmdma_post_internal_cmd,
53
54 .dev_select = ata_std_dev_select,
55 .check_status = ata_check_status,
56 .tf_load = ata_tf_load,
57 .tf_read = ata_tf_read,
58 .exec_command = ata_exec_command,
59 .data_xfer = ata_data_xfer,
60 .irq_on = ata_irq_on,
61
62 .port_start = ata_sff_port_start,
63};
64
65const struct ata_port_operations ata_bmdma_port_ops = {
66 .inherits = &ata_sff_port_ops,
67
68 .mode_filter = ata_pci_default_filter,
69
70 .bmdma_setup = ata_bmdma_setup,
71 .bmdma_start = ata_bmdma_start,
72 .bmdma_stop = ata_bmdma_stop,
73 .bmdma_status = ata_bmdma_status,
74 .irq_clear = ata_bmdma_irq_clear,
75};
76
77/**
78 * ata_fill_sg - Fill PCI IDE PRD table
79 * @qc: Metadata associated with taskfile to be transferred
80 *
81 * Fill PCI IDE PRD (scatter-gather) table with segments
82 * associated with the current disk command.
83 *
84 * LOCKING:
85 * spin_lock_irqsave(host lock)
86 *
87 */
88static void ata_fill_sg(struct ata_queued_cmd *qc)
89{
90 struct ata_port *ap = qc->ap;
91 struct scatterlist *sg;
92 unsigned int si, pi;
93
94 pi = 0;
95 for_each_sg(qc->sg, sg, qc->n_elem, si) {
96 u32 addr, offset;
97 u32 sg_len, len;
98
99 /* determine if physical DMA addr spans 64K boundary.
100 * Note h/w doesn't support 64-bit, so we unconditionally
101 * truncate dma_addr_t to u32.
102 */
103 addr = (u32) sg_dma_address(sg);
104 sg_len = sg_dma_len(sg);
105
106 while (sg_len) {
107 offset = addr & 0xffff;
108 len = sg_len;
109 if ((offset + sg_len) > 0x10000)
110 len = 0x10000 - offset;
111
112 ap->prd[pi].addr = cpu_to_le32(addr);
113 ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff);
114 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
115
116 pi++;
117 sg_len -= len;
118 addr += len;
119 }
120 }
121
122 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
123}
124
125/**
126 * ata_fill_sg_dumb - Fill PCI IDE PRD table
127 * @qc: Metadata associated with taskfile to be transferred
128 *
129 * Fill PCI IDE PRD (scatter-gather) table with segments
130 * associated with the current disk command. Perform the fill
131 * so that we avoid writing any length 64K records for
132 * controllers that don't follow the spec.
133 *
134 * LOCKING:
135 * spin_lock_irqsave(host lock)
136 *
137 */
138static void ata_fill_sg_dumb(struct ata_queued_cmd *qc)
139{
140 struct ata_port *ap = qc->ap;
141 struct scatterlist *sg;
142 unsigned int si, pi;
143
144 pi = 0;
145 for_each_sg(qc->sg, sg, qc->n_elem, si) {
146 u32 addr, offset;
147 u32 sg_len, len, blen;
148
149 /* determine if physical DMA addr spans 64K boundary.
150 * Note h/w doesn't support 64-bit, so we unconditionally
151 * truncate dma_addr_t to u32.
152 */
153 addr = (u32) sg_dma_address(sg);
154 sg_len = sg_dma_len(sg);
155
156 while (sg_len) {
157 offset = addr & 0xffff;
158 len = sg_len;
159 if ((offset + sg_len) > 0x10000)
160 len = 0x10000 - offset;
161
162 blen = len & 0xffff;
163 ap->prd[pi].addr = cpu_to_le32(addr);
164 if (blen == 0) {
165 /* Some PATA chipsets like the CS5530 can't
166 cope with 0x0000 meaning 64K as the spec says */
167 ap->prd[pi].flags_len = cpu_to_le32(0x8000);
168 blen = 0x8000;
169 ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000);
170 }
171 ap->prd[pi].flags_len = cpu_to_le32(blen);
172 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
173
174 pi++;
175 sg_len -= len;
176 addr += len;
177 }
178 }
179
180 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
181}
182
183/**
184 * ata_qc_prep - Prepare taskfile for submission
185 * @qc: Metadata associated with taskfile to be prepared
186 *
187 * Prepare ATA taskfile for submission.
188 *
189 * LOCKING:
190 * spin_lock_irqsave(host lock)
191 */
192void ata_qc_prep(struct ata_queued_cmd *qc)
193{
194 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
195 return;
196
197 ata_fill_sg(qc);
198}
199
200/**
201 * ata_dumb_qc_prep - Prepare taskfile for submission
202 * @qc: Metadata associated with taskfile to be prepared
203 *
204 * Prepare ATA taskfile for submission.
205 *
206 * LOCKING:
207 * spin_lock_irqsave(host lock)
208 */
209void ata_dumb_qc_prep(struct ata_queued_cmd *qc)
210{
211 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
212 return;
213
214 ata_fill_sg_dumb(qc);
215}
216
41/** 217/**
42 * ata_check_status - Read device status reg & clear interrupt 218 * ata_check_status - Read device status reg & clear interrupt
43 * @ap: port where the device is 219 * @ap: port where the device is
@@ -76,6 +252,167 @@ u8 ata_altstatus(struct ata_port *ap)
76} 252}
77 253
78/** 254/**
255 * ata_busy_sleep - sleep until BSY clears, or timeout
256 * @ap: port containing status register to be polled
257 * @tmout_pat: impatience timeout
258 * @tmout: overall timeout
259 *
260 * Sleep until ATA Status register bit BSY clears,
261 * or a timeout occurs.
262 *
263 * LOCKING:
264 * Kernel thread context (may sleep).
265 *
266 * RETURNS:
267 * 0 on success, -errno otherwise.
268 */
269int ata_busy_sleep(struct ata_port *ap,
270 unsigned long tmout_pat, unsigned long tmout)
271{
272 unsigned long timer_start, timeout;
273 u8 status;
274
275 status = ata_busy_wait(ap, ATA_BUSY, 300);
276 timer_start = jiffies;
277 timeout = timer_start + tmout_pat;
278 while (status != 0xff && (status & ATA_BUSY) &&
279 time_before(jiffies, timeout)) {
280 msleep(50);
281 status = ata_busy_wait(ap, ATA_BUSY, 3);
282 }
283
284 if (status != 0xff && (status & ATA_BUSY))
285 ata_port_printk(ap, KERN_WARNING,
286 "port is slow to respond, please be patient "
287 "(Status 0x%x)\n", status);
288
289 timeout = timer_start + tmout;
290 while (status != 0xff && (status & ATA_BUSY) &&
291 time_before(jiffies, timeout)) {
292 msleep(50);
293 status = ata_chk_status(ap);
294 }
295
296 if (status == 0xff)
297 return -ENODEV;
298
299 if (status & ATA_BUSY) {
300 ata_port_printk(ap, KERN_ERR, "port failed to respond "
301 "(%lu secs, Status 0x%x)\n",
302 tmout / HZ, status);
303 return -EBUSY;
304 }
305
306 return 0;
307}
308
309/**
310 * ata_wait_ready - sleep until BSY clears, or timeout
311 * @ap: port containing status register to be polled
312 * @deadline: deadline jiffies for the operation
313 *
314 * Sleep until ATA Status register bit BSY clears, or timeout
315 * occurs.
316 *
317 * LOCKING:
318 * Kernel thread context (may sleep).
319 *
320 * RETURNS:
321 * 0 on success, -errno otherwise.
322 */
323int ata_wait_ready(struct ata_port *ap, unsigned long deadline)
324{
325 unsigned long start = jiffies;
326 int warned = 0;
327
328 while (1) {
329 u8 status = ata_chk_status(ap);
330 unsigned long now = jiffies;
331
332 if (!(status & ATA_BUSY))
333 return 0;
334 if (!ata_link_online(&ap->link) && status == 0xff)
335 return -ENODEV;
336 if (time_after(now, deadline))
337 return -EBUSY;
338
339 if (!warned && time_after(now, start + 5 * HZ) &&
340 (deadline - now > 3 * HZ)) {
341 ata_port_printk(ap, KERN_WARNING,
342 "port is slow to respond, please be patient "
343 "(Status 0x%x)\n", status);
344 warned = 1;
345 }
346
347 msleep(50);
348 }
349}
350
351/**
352 * ata_std_dev_select - Select device 0/1 on ATA bus
353 * @ap: ATA channel to manipulate
354 * @device: ATA device (numbered from zero) to select
355 *
356 * Use the method defined in the ATA specification to
357 * make either device 0, or device 1, active on the
358 * ATA channel. Works with both PIO and MMIO.
359 *
360 * May be used as the dev_select() entry in ata_port_operations.
361 *
362 * LOCKING:
363 * caller.
364 */
365void ata_std_dev_select(struct ata_port *ap, unsigned int device)
366{
367 u8 tmp;
368
369 if (device == 0)
370 tmp = ATA_DEVICE_OBS;
371 else
372 tmp = ATA_DEVICE_OBS | ATA_DEV1;
373
374 iowrite8(tmp, ap->ioaddr.device_addr);
375 ata_pause(ap); /* needed; also flushes, for mmio */
376}
377
378/**
379 * ata_dev_select - Select device 0/1 on ATA bus
380 * @ap: ATA channel to manipulate
381 * @device: ATA device (numbered from zero) to select
382 * @wait: non-zero to wait for Status register BSY bit to clear
383 * @can_sleep: non-zero if context allows sleeping
384 *
385 * Use the method defined in the ATA specification to
386 * make either device 0, or device 1, active on the
387 * ATA channel.
388 *
389 * This is a high-level version of ata_std_dev_select(),
390 * which additionally provides the services of inserting
391 * the proper pauses and status polling, where needed.
392 *
393 * LOCKING:
394 * caller.
395 */
396void ata_dev_select(struct ata_port *ap, unsigned int device,
397 unsigned int wait, unsigned int can_sleep)
398{
399 if (ata_msg_probe(ap))
400 ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, "
401 "device %u, wait %u\n", device, wait);
402
403 if (wait)
404 ata_wait_idle(ap);
405
406 ap->ops->dev_select(ap, device);
407
408 if (wait) {
409 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
410 msleep(150);
411 ata_wait_idle(ap);
412 }
413}
414
415/**
79 * ata_irq_on - Enable interrupts on a port. 416 * ata_irq_on - Enable interrupts on a port.
80 * @ap: Port on which interrupts are enabled. 417 * @ap: Port on which interrupts are enabled.
81 * 418 *
@@ -242,6 +579,987 @@ void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
242} 579}
243 580
244/** 581/**
582 * ata_tf_to_host - issue ATA taskfile to host controller
583 * @ap: port to which command is being issued
584 * @tf: ATA taskfile register set
585 *
586 * Issues ATA taskfile register set to ATA host controller,
587 * with proper synchronization with interrupt handler and
588 * other threads.
589 *
590 * LOCKING:
591 * spin_lock_irqsave(host lock)
592 */
593static inline void ata_tf_to_host(struct ata_port *ap,
594 const struct ata_taskfile *tf)
595{
596 ap->ops->tf_load(ap, tf);
597 ap->ops->exec_command(ap, tf);
598}
599
600/**
601 * ata_data_xfer - Transfer data by PIO
602 * @dev: device to target
603 * @buf: data buffer
604 * @buflen: buffer length
605 * @rw: read/write
606 *
607 * Transfer data from/to the device data register by PIO.
608 *
609 * LOCKING:
610 * Inherited from caller.
611 *
612 * RETURNS:
613 * Bytes consumed.
614 */
615unsigned int ata_data_xfer(struct ata_device *dev, unsigned char *buf,
616 unsigned int buflen, int rw)
617{
618 struct ata_port *ap = dev->link->ap;
619 void __iomem *data_addr = ap->ioaddr.data_addr;
620 unsigned int words = buflen >> 1;
621
622 /* Transfer multiple of 2 bytes */
623 if (rw == READ)
624 ioread16_rep(data_addr, buf, words);
625 else
626 iowrite16_rep(data_addr, buf, words);
627
628 /* Transfer trailing 1 byte, if any. */
629 if (unlikely(buflen & 0x01)) {
630 __le16 align_buf[1] = { 0 };
631 unsigned char *trailing_buf = buf + buflen - 1;
632
633 if (rw == READ) {
634 align_buf[0] = cpu_to_le16(ioread16(data_addr));
635 memcpy(trailing_buf, align_buf, 1);
636 } else {
637 memcpy(align_buf, trailing_buf, 1);
638 iowrite16(le16_to_cpu(align_buf[0]), data_addr);
639 }
640 words++;
641 }
642
643 return words << 1;
644}
645
646/**
647 * ata_data_xfer_noirq - Transfer data by PIO
648 * @dev: device to target
649 * @buf: data buffer
650 * @buflen: buffer length
651 * @rw: read/write
652 *
653 * Transfer data from/to the device data register by PIO. Do the
654 * transfer with interrupts disabled.
655 *
656 * LOCKING:
657 * Inherited from caller.
658 *
659 * RETURNS:
660 * Bytes consumed.
661 */
662unsigned int ata_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
663 unsigned int buflen, int rw)
664{
665 unsigned long flags;
666 unsigned int consumed;
667
668 local_irq_save(flags);
669 consumed = ata_data_xfer(dev, buf, buflen, rw);
670 local_irq_restore(flags);
671
672 return consumed;
673}
674
675/**
676 * ata_pio_sector - Transfer a sector of data.
677 * @qc: Command on going
678 *
679 * Transfer qc->sect_size bytes of data from/to the ATA device.
680 *
681 * LOCKING:
682 * Inherited from caller.
683 */
684static void ata_pio_sector(struct ata_queued_cmd *qc)
685{
686 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
687 struct ata_port *ap = qc->ap;
688 struct page *page;
689 unsigned int offset;
690 unsigned char *buf;
691
692 if (qc->curbytes == qc->nbytes - qc->sect_size)
693 ap->hsm_task_state = HSM_ST_LAST;
694
695 page = sg_page(qc->cursg);
696 offset = qc->cursg->offset + qc->cursg_ofs;
697
698 /* get the current page and offset */
699 page = nth_page(page, (offset >> PAGE_SHIFT));
700 offset %= PAGE_SIZE;
701
702 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
703
704 if (PageHighMem(page)) {
705 unsigned long flags;
706
707 /* FIXME: use a bounce buffer */
708 local_irq_save(flags);
709 buf = kmap_atomic(page, KM_IRQ0);
710
711 /* do the actual data transfer */
712 ap->ops->data_xfer(qc->dev, buf + offset, qc->sect_size, do_write);
713
714 kunmap_atomic(buf, KM_IRQ0);
715 local_irq_restore(flags);
716 } else {
717 buf = page_address(page);
718 ap->ops->data_xfer(qc->dev, buf + offset, qc->sect_size, do_write);
719 }
720
721 qc->curbytes += qc->sect_size;
722 qc->cursg_ofs += qc->sect_size;
723
724 if (qc->cursg_ofs == qc->cursg->length) {
725 qc->cursg = sg_next(qc->cursg);
726 qc->cursg_ofs = 0;
727 }
728}
729
730/**
731 * ata_pio_sectors - Transfer one or many sectors.
732 * @qc: Command on going
733 *
734 * Transfer one or many sectors of data from/to the
735 * ATA device for the DRQ request.
736 *
737 * LOCKING:
738 * Inherited from caller.
739 */
740static void ata_pio_sectors(struct ata_queued_cmd *qc)
741{
742 if (is_multi_taskfile(&qc->tf)) {
743 /* READ/WRITE MULTIPLE */
744 unsigned int nsect;
745
746 WARN_ON(qc->dev->multi_count == 0);
747
748 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
749 qc->dev->multi_count);
750 while (nsect--)
751 ata_pio_sector(qc);
752 } else
753 ata_pio_sector(qc);
754
755 ata_altstatus(qc->ap); /* flush */
756}
757
758/**
759 * atapi_send_cdb - Write CDB bytes to hardware
760 * @ap: Port to which ATAPI device is attached.
761 * @qc: Taskfile currently active
762 *
763 * When device has indicated its readiness to accept
764 * a CDB, this function is called. Send the CDB.
765 *
766 * LOCKING:
767 * caller.
768 */
769static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
770{
771 /* send SCSI cdb */
772 DPRINTK("send cdb\n");
773 WARN_ON(qc->dev->cdb_len < 12);
774
775 ap->ops->data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
776 ata_altstatus(ap); /* flush */
777
778 switch (qc->tf.protocol) {
779 case ATAPI_PROT_PIO:
780 ap->hsm_task_state = HSM_ST;
781 break;
782 case ATAPI_PROT_NODATA:
783 ap->hsm_task_state = HSM_ST_LAST;
784 break;
785 case ATAPI_PROT_DMA:
786 ap->hsm_task_state = HSM_ST_LAST;
787 /* initiate bmdma */
788 ap->ops->bmdma_start(qc);
789 break;
790 }
791}
792
793/**
794 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
795 * @qc: Command on going
796 * @bytes: number of bytes
797 *
798 * Transfer Transfer data from/to the ATAPI device.
799 *
800 * LOCKING:
801 * Inherited from caller.
802 *
803 */
804static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
805{
806 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
807 struct ata_port *ap = qc->ap;
808 struct ata_device *dev = qc->dev;
809 struct ata_eh_info *ehi = &dev->link->eh_info;
810 struct scatterlist *sg;
811 struct page *page;
812 unsigned char *buf;
813 unsigned int offset, count, consumed;
814
815next_sg:
816 sg = qc->cursg;
817 if (unlikely(!sg)) {
818 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
819 "buf=%u cur=%u bytes=%u",
820 qc->nbytes, qc->curbytes, bytes);
821 return -1;
822 }
823
824 page = sg_page(sg);
825 offset = sg->offset + qc->cursg_ofs;
826
827 /* get the current page and offset */
828 page = nth_page(page, (offset >> PAGE_SHIFT));
829 offset %= PAGE_SIZE;
830
831 /* don't overrun current sg */
832 count = min(sg->length - qc->cursg_ofs, bytes);
833
834 /* don't cross page boundaries */
835 count = min(count, (unsigned int)PAGE_SIZE - offset);
836
837 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
838
839 if (PageHighMem(page)) {
840 unsigned long flags;
841
842 /* FIXME: use bounce buffer */
843 local_irq_save(flags);
844 buf = kmap_atomic(page, KM_IRQ0);
845
846 /* do the actual data transfer */
847 consumed = ap->ops->data_xfer(dev, buf + offset, count, rw);
848
849 kunmap_atomic(buf, KM_IRQ0);
850 local_irq_restore(flags);
851 } else {
852 buf = page_address(page);
853 consumed = ap->ops->data_xfer(dev, buf + offset, count, rw);
854 }
855
856 bytes -= min(bytes, consumed);
857 qc->curbytes += count;
858 qc->cursg_ofs += count;
859
860 if (qc->cursg_ofs == sg->length) {
861 qc->cursg = sg_next(qc->cursg);
862 qc->cursg_ofs = 0;
863 }
864
865 /* consumed can be larger than count only for the last transfer */
866 WARN_ON(qc->cursg && count != consumed);
867
868 if (bytes)
869 goto next_sg;
870 return 0;
871}
872
873/**
874 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
875 * @qc: Command on going
876 *
877 * Transfer Transfer data from/to the ATAPI device.
878 *
879 * LOCKING:
880 * Inherited from caller.
881 */
882static void atapi_pio_bytes(struct ata_queued_cmd *qc)
883{
884 struct ata_port *ap = qc->ap;
885 struct ata_device *dev = qc->dev;
886 struct ata_eh_info *ehi = &dev->link->eh_info;
887 unsigned int ireason, bc_lo, bc_hi, bytes;
888 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
889
890 /* Abuse qc->result_tf for temp storage of intermediate TF
891 * here to save some kernel stack usage.
892 * For normal completion, qc->result_tf is not relevant. For
893 * error, qc->result_tf is later overwritten by ata_qc_complete().
894 * So, the correctness of qc->result_tf is not affected.
895 */
896 ap->ops->tf_read(ap, &qc->result_tf);
897 ireason = qc->result_tf.nsect;
898 bc_lo = qc->result_tf.lbam;
899 bc_hi = qc->result_tf.lbah;
900 bytes = (bc_hi << 8) | bc_lo;
901
902 /* shall be cleared to zero, indicating xfer of data */
903 if (unlikely(ireason & (1 << 0)))
904 goto atapi_check;
905
906 /* make sure transfer direction matches expected */
907 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
908 if (unlikely(do_write != i_write))
909 goto atapi_check;
910
911 if (unlikely(!bytes))
912 goto atapi_check;
913
914 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
915
916 if (unlikely(__atapi_pio_bytes(qc, bytes)))
917 goto err_out;
918 ata_altstatus(ap); /* flush */
919
920 return;
921
922 atapi_check:
923 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
924 ireason, bytes);
925 err_out:
926 qc->err_mask |= AC_ERR_HSM;
927 ap->hsm_task_state = HSM_ST_ERR;
928}
929
930/**
931 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
932 * @ap: the target ata_port
933 * @qc: qc on going
934 *
935 * RETURNS:
936 * 1 if ok in workqueue, 0 otherwise.
937 */
938static inline int ata_hsm_ok_in_wq(struct ata_port *ap, struct ata_queued_cmd *qc)
939{
940 if (qc->tf.flags & ATA_TFLAG_POLLING)
941 return 1;
942
943 if (ap->hsm_task_state == HSM_ST_FIRST) {
944 if (qc->tf.protocol == ATA_PROT_PIO &&
945 (qc->tf.flags & ATA_TFLAG_WRITE))
946 return 1;
947
948 if (ata_is_atapi(qc->tf.protocol) &&
949 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
950 return 1;
951 }
952
953 return 0;
954}
955
956/**
957 * ata_hsm_qc_complete - finish a qc running on standard HSM
958 * @qc: Command to complete
959 * @in_wq: 1 if called from workqueue, 0 otherwise
960 *
961 * Finish @qc which is running on standard HSM.
962 *
963 * LOCKING:
964 * If @in_wq is zero, spin_lock_irqsave(host lock).
965 * Otherwise, none on entry and grabs host lock.
966 */
967static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
968{
969 struct ata_port *ap = qc->ap;
970 unsigned long flags;
971
972 if (ap->ops->error_handler) {
973 if (in_wq) {
974 spin_lock_irqsave(ap->lock, flags);
975
976 /* EH might have kicked in while host lock is
977 * released.
978 */
979 qc = ata_qc_from_tag(ap, qc->tag);
980 if (qc) {
981 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
982 ap->ops->irq_on(ap);
983 ata_qc_complete(qc);
984 } else
985 ata_port_freeze(ap);
986 }
987
988 spin_unlock_irqrestore(ap->lock, flags);
989 } else {
990 if (likely(!(qc->err_mask & AC_ERR_HSM)))
991 ata_qc_complete(qc);
992 else
993 ata_port_freeze(ap);
994 }
995 } else {
996 if (in_wq) {
997 spin_lock_irqsave(ap->lock, flags);
998 ap->ops->irq_on(ap);
999 ata_qc_complete(qc);
1000 spin_unlock_irqrestore(ap->lock, flags);
1001 } else
1002 ata_qc_complete(qc);
1003 }
1004}
1005
1006/**
1007 * ata_hsm_move - move the HSM to the next state.
1008 * @ap: the target ata_port
1009 * @qc: qc on going
1010 * @status: current device status
1011 * @in_wq: 1 if called from workqueue, 0 otherwise
1012 *
1013 * RETURNS:
1014 * 1 when poll next status needed, 0 otherwise.
1015 */
1016int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
1017 u8 status, int in_wq)
1018{
1019 unsigned long flags = 0;
1020 int poll_next;
1021
1022 WARN_ON((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
1023
1024 /* Make sure ata_qc_issue_prot() does not throw things
1025 * like DMA polling into the workqueue. Notice that
1026 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
1027 */
1028 WARN_ON(in_wq != ata_hsm_ok_in_wq(ap, qc));
1029
1030fsm_start:
1031 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
1032 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
1033
1034 switch (ap->hsm_task_state) {
1035 case HSM_ST_FIRST:
1036 /* Send first data block or PACKET CDB */
1037
1038 /* If polling, we will stay in the work queue after
1039 * sending the data. Otherwise, interrupt handler
1040 * takes over after sending the data.
1041 */
1042 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1043
1044 /* check device status */
1045 if (unlikely((status & ATA_DRQ) == 0)) {
1046 /* handle BSY=0, DRQ=0 as error */
1047 if (likely(status & (ATA_ERR | ATA_DF)))
1048 /* device stops HSM for abort/error */
1049 qc->err_mask |= AC_ERR_DEV;
1050 else
1051 /* HSM violation. Let EH handle this */
1052 qc->err_mask |= AC_ERR_HSM;
1053
1054 ap->hsm_task_state = HSM_ST_ERR;
1055 goto fsm_start;
1056 }
1057
1058 /* Device should not ask for data transfer (DRQ=1)
1059 * when it finds something wrong.
1060 * We ignore DRQ here and stop the HSM by
1061 * changing hsm_task_state to HSM_ST_ERR and
1062 * let the EH abort the command or reset the device.
1063 */
1064 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1065 /* Some ATAPI tape drives forget to clear the ERR bit
1066 * when doing the next command (mostly request sense).
1067 * We ignore ERR here to workaround and proceed sending
1068 * the CDB.
1069 */
1070 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
1071 ata_port_printk(ap, KERN_WARNING,
1072 "DRQ=1 with device error, "
1073 "dev_stat 0x%X\n", status);
1074 qc->err_mask |= AC_ERR_HSM;
1075 ap->hsm_task_state = HSM_ST_ERR;
1076 goto fsm_start;
1077 }
1078 }
1079
1080 /* Send the CDB (atapi) or the first data block (ata pio out).
1081 * During the state transition, interrupt handler shouldn't
1082 * be invoked before the data transfer is complete and
1083 * hsm_task_state is changed. Hence, the following locking.
1084 */
1085 if (in_wq)
1086 spin_lock_irqsave(ap->lock, flags);
1087
1088 if (qc->tf.protocol == ATA_PROT_PIO) {
1089 /* PIO data out protocol.
1090 * send first data block.
1091 */
1092
1093 /* ata_pio_sectors() might change the state
1094 * to HSM_ST_LAST. so, the state is changed here
1095 * before ata_pio_sectors().
1096 */
1097 ap->hsm_task_state = HSM_ST;
1098 ata_pio_sectors(qc);
1099 } else
1100 /* send CDB */
1101 atapi_send_cdb(ap, qc);
1102
1103 if (in_wq)
1104 spin_unlock_irqrestore(ap->lock, flags);
1105
1106 /* if polling, ata_pio_task() handles the rest.
1107 * otherwise, interrupt handler takes over from here.
1108 */
1109 break;
1110
1111 case HSM_ST:
1112 /* complete command or read/write the data register */
1113 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1114 /* ATAPI PIO protocol */
1115 if ((status & ATA_DRQ) == 0) {
1116 /* No more data to transfer or device error.
1117 * Device error will be tagged in HSM_ST_LAST.
1118 */
1119 ap->hsm_task_state = HSM_ST_LAST;
1120 goto fsm_start;
1121 }
1122
1123 /* Device should not ask for data transfer (DRQ=1)
1124 * when it finds something wrong.
1125 * We ignore DRQ here and stop the HSM by
1126 * changing hsm_task_state to HSM_ST_ERR and
1127 * let the EH abort the command or reset the device.
1128 */
1129 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1130 ata_port_printk(ap, KERN_WARNING, "DRQ=1 with "
1131 "device error, dev_stat 0x%X\n",
1132 status);
1133 qc->err_mask |= AC_ERR_HSM;
1134 ap->hsm_task_state = HSM_ST_ERR;
1135 goto fsm_start;
1136 }
1137
1138 atapi_pio_bytes(qc);
1139
1140 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1141 /* bad ireason reported by device */
1142 goto fsm_start;
1143
1144 } else {
1145 /* ATA PIO protocol */
1146 if (unlikely((status & ATA_DRQ) == 0)) {
1147 /* handle BSY=0, DRQ=0 as error */
1148 if (likely(status & (ATA_ERR | ATA_DF)))
1149 /* device stops HSM for abort/error */
1150 qc->err_mask |= AC_ERR_DEV;
1151 else
1152 /* HSM violation. Let EH handle this.
1153 * Phantom devices also trigger this
1154 * condition. Mark hint.
1155 */
1156 qc->err_mask |= AC_ERR_HSM |
1157 AC_ERR_NODEV_HINT;
1158
1159 ap->hsm_task_state = HSM_ST_ERR;
1160 goto fsm_start;
1161 }
1162
1163 /* For PIO reads, some devices may ask for
1164 * data transfer (DRQ=1) alone with ERR=1.
1165 * We respect DRQ here and transfer one
1166 * block of junk data before changing the
1167 * hsm_task_state to HSM_ST_ERR.
1168 *
1169 * For PIO writes, ERR=1 DRQ=1 doesn't make
1170 * sense since the data block has been
1171 * transferred to the device.
1172 */
1173 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1174 /* data might be corrputed */
1175 qc->err_mask |= AC_ERR_DEV;
1176
1177 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1178 ata_pio_sectors(qc);
1179 status = ata_wait_idle(ap);
1180 }
1181
1182 if (status & (ATA_BUSY | ATA_DRQ))
1183 qc->err_mask |= AC_ERR_HSM;
1184
1185 /* ata_pio_sectors() might change the
1186 * state to HSM_ST_LAST. so, the state
1187 * is changed after ata_pio_sectors().
1188 */
1189 ap->hsm_task_state = HSM_ST_ERR;
1190 goto fsm_start;
1191 }
1192
1193 ata_pio_sectors(qc);
1194
1195 if (ap->hsm_task_state == HSM_ST_LAST &&
1196 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1197 /* all data read */
1198 status = ata_wait_idle(ap);
1199 goto fsm_start;
1200 }
1201 }
1202
1203 poll_next = 1;
1204 break;
1205
1206 case HSM_ST_LAST:
1207 if (unlikely(!ata_ok(status))) {
1208 qc->err_mask |= __ac_err_mask(status);
1209 ap->hsm_task_state = HSM_ST_ERR;
1210 goto fsm_start;
1211 }
1212
1213 /* no more data to transfer */
1214 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1215 ap->print_id, qc->dev->devno, status);
1216
1217 WARN_ON(qc->err_mask);
1218
1219 ap->hsm_task_state = HSM_ST_IDLE;
1220
1221 /* complete taskfile transaction */
1222 ata_hsm_qc_complete(qc, in_wq);
1223
1224 poll_next = 0;
1225 break;
1226
1227 case HSM_ST_ERR:
1228 /* make sure qc->err_mask is available to
1229 * know what's wrong and recover
1230 */
1231 WARN_ON(qc->err_mask == 0);
1232
1233 ap->hsm_task_state = HSM_ST_IDLE;
1234
1235 /* complete taskfile transaction */
1236 ata_hsm_qc_complete(qc, in_wq);
1237
1238 poll_next = 0;
1239 break;
1240 default:
1241 poll_next = 0;
1242 BUG();
1243 }
1244
1245 return poll_next;
1246}
1247
1248void ata_pio_task(struct work_struct *work)
1249{
1250 struct ata_port *ap =
1251 container_of(work, struct ata_port, port_task.work);
1252 struct ata_queued_cmd *qc = ap->port_task_data;
1253 u8 status;
1254 int poll_next;
1255
1256fsm_start:
1257 WARN_ON(ap->hsm_task_state == HSM_ST_IDLE);
1258
1259 /*
1260 * This is purely heuristic. This is a fast path.
1261 * Sometimes when we enter, BSY will be cleared in
1262 * a chk-status or two. If not, the drive is probably seeking
1263 * or something. Snooze for a couple msecs, then
1264 * chk-status again. If still busy, queue delayed work.
1265 */
1266 status = ata_busy_wait(ap, ATA_BUSY, 5);
1267 if (status & ATA_BUSY) {
1268 msleep(2);
1269 status = ata_busy_wait(ap, ATA_BUSY, 10);
1270 if (status & ATA_BUSY) {
1271 ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
1272 return;
1273 }
1274 }
1275
1276 /* move the HSM */
1277 poll_next = ata_hsm_move(ap, qc, status, 1);
1278
1279 /* another command or interrupt handler
1280 * may be running at this point.
1281 */
1282 if (poll_next)
1283 goto fsm_start;
1284}
1285
1286/**
1287 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
1288 * @qc: command to issue to device
1289 *
1290 * Using various libata functions and hooks, this function
1291 * starts an ATA command. ATA commands are grouped into
1292 * classes called "protocols", and issuing each type of protocol
1293 * is slightly different.
1294 *
1295 * May be used as the qc_issue() entry in ata_port_operations.
1296 *
1297 * LOCKING:
1298 * spin_lock_irqsave(host lock)
1299 *
1300 * RETURNS:
1301 * Zero on success, AC_ERR_* mask on failure
1302 */
1303unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
1304{
1305 struct ata_port *ap = qc->ap;
1306
1307 /* Use polling pio if the LLD doesn't handle
1308 * interrupt driven pio and atapi CDB interrupt.
1309 */
1310 if (ap->flags & ATA_FLAG_PIO_POLLING) {
1311 switch (qc->tf.protocol) {
1312 case ATA_PROT_PIO:
1313 case ATA_PROT_NODATA:
1314 case ATAPI_PROT_PIO:
1315 case ATAPI_PROT_NODATA:
1316 qc->tf.flags |= ATA_TFLAG_POLLING;
1317 break;
1318 case ATAPI_PROT_DMA:
1319 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1320 /* see ata_dma_blacklisted() */
1321 BUG();
1322 break;
1323 default:
1324 break;
1325 }
1326 }
1327
1328 /* select the device */
1329 ata_dev_select(ap, qc->dev->devno, 1, 0);
1330
1331 /* start the command */
1332 switch (qc->tf.protocol) {
1333 case ATA_PROT_NODATA:
1334 if (qc->tf.flags & ATA_TFLAG_POLLING)
1335 ata_qc_set_polling(qc);
1336
1337 ata_tf_to_host(ap, &qc->tf);
1338 ap->hsm_task_state = HSM_ST_LAST;
1339
1340 if (qc->tf.flags & ATA_TFLAG_POLLING)
1341 ata_pio_queue_task(ap, qc, 0);
1342
1343 break;
1344
1345 case ATA_PROT_DMA:
1346 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
1347
1348 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
1349 ap->ops->bmdma_setup(qc); /* set up bmdma */
1350 ap->ops->bmdma_start(qc); /* initiate bmdma */
1351 ap->hsm_task_state = HSM_ST_LAST;
1352 break;
1353
1354 case ATA_PROT_PIO:
1355 if (qc->tf.flags & ATA_TFLAG_POLLING)
1356 ata_qc_set_polling(qc);
1357
1358 ata_tf_to_host(ap, &qc->tf);
1359
1360 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1361 /* PIO data out protocol */
1362 ap->hsm_task_state = HSM_ST_FIRST;
1363 ata_pio_queue_task(ap, qc, 0);
1364
1365 /* always send first data block using
1366 * the ata_pio_task() codepath.
1367 */
1368 } else {
1369 /* PIO data in protocol */
1370 ap->hsm_task_state = HSM_ST;
1371
1372 if (qc->tf.flags & ATA_TFLAG_POLLING)
1373 ata_pio_queue_task(ap, qc, 0);
1374
1375 /* if polling, ata_pio_task() handles the rest.
1376 * otherwise, interrupt handler takes over from here.
1377 */
1378 }
1379
1380 break;
1381
1382 case ATAPI_PROT_PIO:
1383 case ATAPI_PROT_NODATA:
1384 if (qc->tf.flags & ATA_TFLAG_POLLING)
1385 ata_qc_set_polling(qc);
1386
1387 ata_tf_to_host(ap, &qc->tf);
1388
1389 ap->hsm_task_state = HSM_ST_FIRST;
1390
1391 /* send cdb by polling if no cdb interrupt */
1392 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1393 (qc->tf.flags & ATA_TFLAG_POLLING))
1394 ata_pio_queue_task(ap, qc, 0);
1395 break;
1396
1397 case ATAPI_PROT_DMA:
1398 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
1399
1400 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
1401 ap->ops->bmdma_setup(qc); /* set up bmdma */
1402 ap->hsm_task_state = HSM_ST_FIRST;
1403
1404 /* send cdb by polling if no cdb interrupt */
1405 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1406 ata_pio_queue_task(ap, qc, 0);
1407 break;
1408
1409 default:
1410 WARN_ON(1);
1411 return AC_ERR_SYSTEM;
1412 }
1413
1414 return 0;
1415}
1416
1417/**
1418 * ata_host_intr - Handle host interrupt for given (port, task)
1419 * @ap: Port on which interrupt arrived (possibly...)
1420 * @qc: Taskfile currently active in engine
1421 *
1422 * Handle host interrupt for given queued command. Currently,
1423 * only DMA interrupts are handled. All other commands are
1424 * handled via polling with interrupts disabled (nIEN bit).
1425 *
1426 * LOCKING:
1427 * spin_lock_irqsave(host lock)
1428 *
1429 * RETURNS:
1430 * One if interrupt was handled, zero if not (shared irq).
1431 */
1432inline unsigned int ata_host_intr(struct ata_port *ap,
1433 struct ata_queued_cmd *qc)
1434{
1435 struct ata_eh_info *ehi = &ap->link.eh_info;
1436 u8 status, host_stat = 0;
1437
1438 VPRINTK("ata%u: protocol %d task_state %d\n",
1439 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1440
1441 /* Check whether we are expecting interrupt in this state */
1442 switch (ap->hsm_task_state) {
1443 case HSM_ST_FIRST:
1444 /* Some pre-ATAPI-4 devices assert INTRQ
1445 * at this state when ready to receive CDB.
1446 */
1447
1448 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1449 * The flag was turned on only for atapi devices. No
1450 * need to check ata_is_atapi(qc->tf.protocol) again.
1451 */
1452 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1453 goto idle_irq;
1454 break;
1455 case HSM_ST_LAST:
1456 if (qc->tf.protocol == ATA_PROT_DMA ||
1457 qc->tf.protocol == ATAPI_PROT_DMA) {
1458 /* check status of DMA engine */
1459 host_stat = ap->ops->bmdma_status(ap);
1460 VPRINTK("ata%u: host_stat 0x%X\n",
1461 ap->print_id, host_stat);
1462
1463 /* if it's not our irq... */
1464 if (!(host_stat & ATA_DMA_INTR))
1465 goto idle_irq;
1466
1467 /* before we do anything else, clear DMA-Start bit */
1468 ap->ops->bmdma_stop(qc);
1469
1470 if (unlikely(host_stat & ATA_DMA_ERR)) {
1471 /* error when transfering data to/from memory */
1472 qc->err_mask |= AC_ERR_HOST_BUS;
1473 ap->hsm_task_state = HSM_ST_ERR;
1474 }
1475 }
1476 break;
1477 case HSM_ST:
1478 break;
1479 default:
1480 goto idle_irq;
1481 }
1482
1483 /* check altstatus */
1484 status = ata_altstatus(ap);
1485 if (status & ATA_BUSY)
1486 goto idle_irq;
1487
1488 /* check main status, clearing INTRQ */
1489 status = ata_chk_status(ap);
1490 if (unlikely(status & ATA_BUSY))
1491 goto idle_irq;
1492
1493 /* ack bmdma irq events */
1494 ap->ops->irq_clear(ap);
1495
1496 ata_hsm_move(ap, qc, status, 0);
1497
1498 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
1499 qc->tf.protocol == ATAPI_PROT_DMA))
1500 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
1501
1502 return 1; /* irq handled */
1503
1504idle_irq:
1505 ap->stats.idle_irq++;
1506
1507#ifdef ATA_IRQ_TRAP
1508 if ((ap->stats.idle_irq % 1000) == 0) {
1509 ata_chk_status(ap);
1510 ap->ops->irq_clear(ap);
1511 ata_port_printk(ap, KERN_WARNING, "irq trap\n");
1512 return 1;
1513 }
1514#endif
1515 return 0; /* irq not handled */
1516}
1517
1518/**
1519 * ata_interrupt - Default ATA host interrupt handler
1520 * @irq: irq line (unused)
1521 * @dev_instance: pointer to our ata_host information structure
1522 *
1523 * Default interrupt handler for PCI IDE devices. Calls
1524 * ata_host_intr() for each port that is not disabled.
1525 *
1526 * LOCKING:
1527 * Obtains host lock during operation.
1528 *
1529 * RETURNS:
1530 * IRQ_NONE or IRQ_HANDLED.
1531 */
1532irqreturn_t ata_interrupt(int irq, void *dev_instance)
1533{
1534 struct ata_host *host = dev_instance;
1535 unsigned int i;
1536 unsigned int handled = 0;
1537 unsigned long flags;
1538
1539 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1540 spin_lock_irqsave(&host->lock, flags);
1541
1542 for (i = 0; i < host->n_ports; i++) {
1543 struct ata_port *ap;
1544
1545 ap = host->ports[i];
1546 if (ap &&
1547 !(ap->flags & ATA_FLAG_DISABLED)) {
1548 struct ata_queued_cmd *qc;
1549
1550 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1551 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
1552 (qc->flags & ATA_QCFLAG_ACTIVE))
1553 handled |= ata_host_intr(ap, qc);
1554 }
1555 }
1556
1557 spin_unlock_irqrestore(&host->lock, flags);
1558
1559 return IRQ_RETVAL(handled);
1560}
1561
1562/**
245 * ata_bmdma_freeze - Freeze BMDMA controller port 1563 * ata_bmdma_freeze - Freeze BMDMA controller port
246 * @ap: port to freeze 1564 * @ap: port to freeze
247 * 1565 *
@@ -287,6 +1605,387 @@ void ata_bmdma_thaw(struct ata_port *ap)
287} 1605}
288 1606
289/** 1607/**
1608 * ata_devchk - PATA device presence detection
1609 * @ap: ATA channel to examine
1610 * @device: Device to examine (starting at zero)
1611 *
1612 * This technique was originally described in
1613 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1614 * later found its way into the ATA/ATAPI spec.
1615 *
1616 * Write a pattern to the ATA shadow registers,
1617 * and if a device is present, it will respond by
1618 * correctly storing and echoing back the
1619 * ATA shadow register contents.
1620 *
1621 * LOCKING:
1622 * caller.
1623 */
1624static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
1625{
1626 struct ata_ioports *ioaddr = &ap->ioaddr;
1627 u8 nsect, lbal;
1628
1629 ap->ops->dev_select(ap, device);
1630
1631 iowrite8(0x55, ioaddr->nsect_addr);
1632 iowrite8(0xaa, ioaddr->lbal_addr);
1633
1634 iowrite8(0xaa, ioaddr->nsect_addr);
1635 iowrite8(0x55, ioaddr->lbal_addr);
1636
1637 iowrite8(0x55, ioaddr->nsect_addr);
1638 iowrite8(0xaa, ioaddr->lbal_addr);
1639
1640 nsect = ioread8(ioaddr->nsect_addr);
1641 lbal = ioread8(ioaddr->lbal_addr);
1642
1643 if ((nsect == 0x55) && (lbal == 0xaa))
1644 return 1; /* we found a device */
1645
1646 return 0; /* nothing found */
1647}
1648
1649/**
1650 * ata_dev_try_classify - Parse returned ATA device signature
1651 * @dev: ATA device to classify (starting at zero)
1652 * @present: device seems present
1653 * @r_err: Value of error register on completion
1654 *
1655 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1656 * an ATA/ATAPI-defined set of values is placed in the ATA
1657 * shadow registers, indicating the results of device detection
1658 * and diagnostics.
1659 *
1660 * Select the ATA device, and read the values from the ATA shadow
1661 * registers. Then parse according to the Error register value,
1662 * and the spec-defined values examined by ata_dev_classify().
1663 *
1664 * LOCKING:
1665 * caller.
1666 *
1667 * RETURNS:
1668 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1669 */
1670unsigned int ata_dev_try_classify(struct ata_device *dev, int present,
1671 u8 *r_err)
1672{
1673 struct ata_port *ap = dev->link->ap;
1674 struct ata_taskfile tf;
1675 unsigned int class;
1676 u8 err;
1677
1678 ap->ops->dev_select(ap, dev->devno);
1679
1680 memset(&tf, 0, sizeof(tf));
1681
1682 ap->ops->tf_read(ap, &tf);
1683 err = tf.feature;
1684 if (r_err)
1685 *r_err = err;
1686
1687 /* see if device passed diags: continue and warn later */
1688 if (err == 0)
1689 /* diagnostic fail : do nothing _YET_ */
1690 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1691 else if (err == 1)
1692 /* do nothing */ ;
1693 else if ((dev->devno == 0) && (err == 0x81))
1694 /* do nothing */ ;
1695 else
1696 return ATA_DEV_NONE;
1697
1698 /* determine if device is ATA or ATAPI */
1699 class = ata_dev_classify(&tf);
1700
1701 if (class == ATA_DEV_UNKNOWN) {
1702 /* If the device failed diagnostic, it's likely to
1703 * have reported incorrect device signature too.
1704 * Assume ATA device if the device seems present but
1705 * device signature is invalid with diagnostic
1706 * failure.
1707 */
1708 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1709 class = ATA_DEV_ATA;
1710 else
1711 class = ATA_DEV_NONE;
1712 } else if ((class == ATA_DEV_ATA) && (ata_chk_status(ap) == 0))
1713 class = ATA_DEV_NONE;
1714
1715 return class;
1716}
1717
1718static int ata_bus_post_reset(struct ata_port *ap, unsigned int devmask,
1719 unsigned long deadline)
1720{
1721 struct ata_ioports *ioaddr = &ap->ioaddr;
1722 unsigned int dev0 = devmask & (1 << 0);
1723 unsigned int dev1 = devmask & (1 << 1);
1724 int rc, ret = 0;
1725
1726 /* if device 0 was found in ata_devchk, wait for its
1727 * BSY bit to clear
1728 */
1729 if (dev0) {
1730 rc = ata_wait_ready(ap, deadline);
1731 if (rc) {
1732 if (rc != -ENODEV)
1733 return rc;
1734 ret = rc;
1735 }
1736 }
1737
1738 /* if device 1 was found in ata_devchk, wait for register
1739 * access briefly, then wait for BSY to clear.
1740 */
1741 if (dev1) {
1742 int i;
1743
1744 ap->ops->dev_select(ap, 1);
1745
1746 /* Wait for register access. Some ATAPI devices fail
1747 * to set nsect/lbal after reset, so don't waste too
1748 * much time on it. We're gonna wait for !BSY anyway.
1749 */
1750 for (i = 0; i < 2; i++) {
1751 u8 nsect, lbal;
1752
1753 nsect = ioread8(ioaddr->nsect_addr);
1754 lbal = ioread8(ioaddr->lbal_addr);
1755 if ((nsect == 1) && (lbal == 1))
1756 break;
1757 msleep(50); /* give drive a breather */
1758 }
1759
1760 rc = ata_wait_ready(ap, deadline);
1761 if (rc) {
1762 if (rc != -ENODEV)
1763 return rc;
1764 ret = rc;
1765 }
1766 }
1767
1768 /* is all this really necessary? */
1769 ap->ops->dev_select(ap, 0);
1770 if (dev1)
1771 ap->ops->dev_select(ap, 1);
1772 if (dev0)
1773 ap->ops->dev_select(ap, 0);
1774
1775 return ret;
1776}
1777
1778/**
1779 * ata_wait_after_reset - wait before checking status after reset
1780 * @ap: port containing status register to be polled
1781 * @deadline: deadline jiffies for the operation
1782 *
1783 * After reset, we need to pause a while before reading status.
1784 * Also, certain combination of controller and device report 0xff
1785 * for some duration (e.g. until SATA PHY is up and running)
1786 * which is interpreted as empty port in ATA world. This
1787 * function also waits for such devices to get out of 0xff
1788 * status.
1789 *
1790 * LOCKING:
1791 * Kernel thread context (may sleep).
1792 */
1793void ata_wait_after_reset(struct ata_port *ap, unsigned long deadline)
1794{
1795 unsigned long until = jiffies + ATA_TMOUT_FF_WAIT;
1796
1797 if (time_before(until, deadline))
1798 deadline = until;
1799
1800 /* Spec mandates ">= 2ms" before checking status. We wait
1801 * 150ms, because that was the magic delay used for ATAPI
1802 * devices in Hale Landis's ATADRVR, for the period of time
1803 * between when the ATA command register is written, and then
1804 * status is checked. Because waiting for "a while" before
1805 * checking status is fine, post SRST, we perform this magic
1806 * delay here as well.
1807 *
1808 * Old drivers/ide uses the 2mS rule and then waits for ready.
1809 */
1810 msleep(150);
1811
1812 /* Wait for 0xff to clear. Some SATA devices take a long time
1813 * to clear 0xff after reset. For example, HHD424020F7SV00
1814 * iVDR needs >= 800ms while. Quantum GoVault needs even more
1815 * than that.
1816 *
1817 * Note that some PATA controllers (pata_ali) explode if
1818 * status register is read more than once when there's no
1819 * device attached.
1820 */
1821 if (ap->flags & ATA_FLAG_SATA) {
1822 while (1) {
1823 u8 status = ata_chk_status(ap);
1824
1825 if (status != 0xff || time_after(jiffies, deadline))
1826 return;
1827
1828 msleep(50);
1829 }
1830 }
1831}
1832
1833static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
1834 unsigned long deadline)
1835{
1836 struct ata_ioports *ioaddr = &ap->ioaddr;
1837
1838 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
1839
1840 /* software reset. causes dev0 to be selected */
1841 iowrite8(ap->ctl, ioaddr->ctl_addr);
1842 udelay(20); /* FIXME: flush */
1843 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1844 udelay(20); /* FIXME: flush */
1845 iowrite8(ap->ctl, ioaddr->ctl_addr);
1846
1847 /* wait a while before checking status */
1848 ata_wait_after_reset(ap, deadline);
1849
1850 /* Before we perform post reset processing we want to see if
1851 * the bus shows 0xFF because the odd clown forgets the D7
1852 * pulldown resistor.
1853 */
1854 if (ata_chk_status(ap) == 0xFF)
1855 return -ENODEV;
1856
1857 return ata_bus_post_reset(ap, devmask, deadline);
1858}
1859
1860/**
1861 * ata_std_softreset - reset host port via ATA SRST
1862 * @link: ATA link to reset
1863 * @classes: resulting classes of attached devices
1864 * @deadline: deadline jiffies for the operation
1865 *
1866 * Reset host port using ATA SRST.
1867 *
1868 * LOCKING:
1869 * Kernel thread context (may sleep)
1870 *
1871 * RETURNS:
1872 * 0 on success, -errno otherwise.
1873 */
1874int ata_std_softreset(struct ata_link *link, unsigned int *classes,
1875 unsigned long deadline)
1876{
1877 struct ata_port *ap = link->ap;
1878 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1879 unsigned int devmask = 0;
1880 int rc;
1881 u8 err;
1882
1883 DPRINTK("ENTER\n");
1884
1885 if (ata_link_offline(link)) {
1886 classes[0] = ATA_DEV_NONE;
1887 goto out;
1888 }
1889
1890 /* determine if device 0/1 are present */
1891 if (ata_devchk(ap, 0))
1892 devmask |= (1 << 0);
1893 if (slave_possible && ata_devchk(ap, 1))
1894 devmask |= (1 << 1);
1895
1896 /* select device 0 again */
1897 ap->ops->dev_select(ap, 0);
1898
1899 /* issue bus reset */
1900 DPRINTK("about to softreset, devmask=%x\n", devmask);
1901 rc = ata_bus_softreset(ap, devmask, deadline);
1902 /* if link is occupied, -ENODEV too is an error */
1903 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
1904 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
1905 return rc;
1906 }
1907
1908 /* determine by signature whether we have ATA or ATAPI devices */
1909 classes[0] = ata_dev_try_classify(&link->device[0],
1910 devmask & (1 << 0), &err);
1911 if (slave_possible && err != 0x81)
1912 classes[1] = ata_dev_try_classify(&link->device[1],
1913 devmask & (1 << 1), &err);
1914
1915 out:
1916 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
1917 return 0;
1918}
1919
1920/**
1921 * sata_std_hardreset - reset host port via SATA phy reset
1922 * @link: link to reset
1923 * @class: resulting class of attached device
1924 * @deadline: deadline jiffies for the operation
1925 *
1926 * SATA phy-reset host port using DET bits of SControl register,
1927 * wait for !BSY and classify the attached device.
1928 *
1929 * LOCKING:
1930 * Kernel thread context (may sleep)
1931 *
1932 * RETURNS:
1933 * 0 on success, -errno otherwise.
1934 */
1935int sata_std_hardreset(struct ata_link *link, unsigned int *class,
1936 unsigned long deadline)
1937{
1938 struct ata_port *ap = link->ap;
1939 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1940 int rc;
1941
1942 DPRINTK("ENTER\n");
1943
1944 /* do hardreset */
1945 rc = sata_link_hardreset(link, timing, deadline);
1946 if (rc) {
1947 ata_link_printk(link, KERN_ERR,
1948 "COMRESET failed (errno=%d)\n", rc);
1949 return rc;
1950 }
1951
1952 /* TODO: phy layer with polling, timeouts, etc. */
1953 if (ata_link_offline(link)) {
1954 *class = ATA_DEV_NONE;
1955 DPRINTK("EXIT, link offline\n");
1956 return 0;
1957 }
1958
1959 /* wait a while before checking status */
1960 ata_wait_after_reset(ap, deadline);
1961
1962 /* If PMP is supported, we have to do follow-up SRST. Note
1963 * that some PMPs don't send D2H Reg FIS after hardreset at
1964 * all if the first port is empty. Wait for it just for a
1965 * second and request follow-up SRST.
1966 */
1967 if (ap->flags & ATA_FLAG_PMP) {
1968 ata_wait_ready(ap, jiffies + HZ);
1969 return -EAGAIN;
1970 }
1971
1972 rc = ata_wait_ready(ap, deadline);
1973 /* link occupied, -ENODEV too is an error */
1974 if (rc) {
1975 ata_link_printk(link, KERN_ERR,
1976 "COMRESET failed (errno=%d)\n", rc);
1977 return rc;
1978 }
1979
1980 ap->ops->dev_select(ap, 0); /* probably unnecessary */
1981
1982 *class = ata_dev_try_classify(link->device, 1, NULL);
1983
1984 DPRINTK("EXIT, class=%u\n", *class);
1985 return 0;
1986}
1987
1988/**
290 * ata_bmdma_error_handler - Stock error handler for BMDMA controller 1989 * ata_bmdma_error_handler - Stock error handler for BMDMA controller
291 * @ap: port to handle error for 1990 * @ap: port to handle error for
292 * 1991 *
@@ -394,6 +2093,31 @@ int ata_sff_port_start(struct ata_port *ap)
394} 2093}
395 2094
396/** 2095/**
2096 * ata_std_ports - initialize ioaddr with standard port offsets.
2097 * @ioaddr: IO address structure to be initialized
2098 *
2099 * Utility function which initializes data_addr, error_addr,
2100 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2101 * device_addr, status_addr, and command_addr to standard offsets
2102 * relative to cmd_addr.
2103 *
2104 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2105 */
2106void ata_std_ports(struct ata_ioports *ioaddr)
2107{
2108 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2109 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2110 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2111 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2112 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2113 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2114 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2115 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2116 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2117 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2118}
2119
2120/**
397 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction 2121 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
398 * @qc: Info associated with this ATA transaction. 2122 * @qc: Info associated with this ATA transaction.
399 * 2123 *
@@ -494,11 +2218,94 @@ u8 ata_bmdma_status(struct ata_port *ap)
494} 2218}
495 2219
496/** 2220/**
497 * ata_noop_irq_clear - Noop placeholder for irq_clear 2221 * ata_bus_reset - reset host port and associated ATA channel
498 * @ap: Port associated with this ATA transaction. 2222 * @ap: port to reset
2223 *
2224 * This is typically the first time we actually start issuing
2225 * commands to the ATA channel. We wait for BSY to clear, then
2226 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
2227 * result. Determine what devices, if any, are on the channel
2228 * by looking at the device 0/1 error register. Look at the signature
2229 * stored in each device's taskfile registers, to determine if
2230 * the device is ATA or ATAPI.
2231 *
2232 * LOCKING:
2233 * PCI/etc. bus probe sem.
2234 * Obtains host lock.
2235 *
2236 * SIDE EFFECTS:
2237 * Sets ATA_FLAG_DISABLED if bus reset fails.
2238 *
2239 * DEPRECATED:
2240 * This function is only for drivers which still use old EH and
2241 * will be removed soon.
499 */ 2242 */
500void ata_noop_irq_clear(struct ata_port *ap) 2243void ata_bus_reset(struct ata_port *ap)
501{ 2244{
2245 struct ata_device *device = ap->link.device;
2246 struct ata_ioports *ioaddr = &ap->ioaddr;
2247 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2248 u8 err;
2249 unsigned int dev0, dev1 = 0, devmask = 0;
2250 int rc;
2251
2252 DPRINTK("ENTER, host %u, port %u\n", ap->print_id, ap->port_no);
2253
2254 /* determine if device 0/1 are present */
2255 if (ap->flags & ATA_FLAG_SATA_RESET)
2256 dev0 = 1;
2257 else {
2258 dev0 = ata_devchk(ap, 0);
2259 if (slave_possible)
2260 dev1 = ata_devchk(ap, 1);
2261 }
2262
2263 if (dev0)
2264 devmask |= (1 << 0);
2265 if (dev1)
2266 devmask |= (1 << 1);
2267
2268 /* select device 0 again */
2269 ap->ops->dev_select(ap, 0);
2270
2271 /* issue bus reset */
2272 if (ap->flags & ATA_FLAG_SRST) {
2273 rc = ata_bus_softreset(ap, devmask, jiffies + 40 * HZ);
2274 if (rc && rc != -ENODEV)
2275 goto err_out;
2276 }
2277
2278 /*
2279 * determine by signature whether we have ATA or ATAPI devices
2280 */
2281 device[0].class = ata_dev_try_classify(&device[0], dev0, &err);
2282 if ((slave_possible) && (err != 0x81))
2283 device[1].class = ata_dev_try_classify(&device[1], dev1, &err);
2284
2285 /* is double-select really necessary? */
2286 if (device[1].class != ATA_DEV_NONE)
2287 ap->ops->dev_select(ap, 1);
2288 if (device[0].class != ATA_DEV_NONE)
2289 ap->ops->dev_select(ap, 0);
2290
2291 /* if no devices were detected, disable this port */
2292 if ((device[0].class == ATA_DEV_NONE) &&
2293 (device[1].class == ATA_DEV_NONE))
2294 goto err_out;
2295
2296 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2297 /* set up device control for ATA_FLAG_SATA_RESET */
2298 iowrite8(ap->ctl, ioaddr->ctl_addr);
2299 }
2300
2301 DPRINTK("EXIT\n");
2302 return;
2303
2304err_out:
2305 ata_port_printk(ap, KERN_ERR, "disabling port\n");
2306 ata_port_disable(ap);
2307
2308 DPRINTK("EXIT\n");
502} 2309}
503 2310
504#ifdef CONFIG_PCI 2311#ifdef CONFIG_PCI
@@ -914,3 +2721,49 @@ int ata_pci_init_one(struct pci_dev *pdev,
914 2721
915#endif /* CONFIG_PCI */ 2722#endif /* CONFIG_PCI */
916 2723
2724EXPORT_SYMBOL_GPL(ata_sff_port_ops);
2725EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
2726EXPORT_SYMBOL_GPL(ata_qc_prep);
2727EXPORT_SYMBOL_GPL(ata_dumb_qc_prep);
2728EXPORT_SYMBOL_GPL(ata_std_dev_select);
2729EXPORT_SYMBOL_GPL(ata_check_status);
2730EXPORT_SYMBOL_GPL(ata_altstatus);
2731EXPORT_SYMBOL_GPL(ata_busy_sleep);
2732EXPORT_SYMBOL_GPL(ata_wait_ready);
2733EXPORT_SYMBOL_GPL(ata_tf_load);
2734EXPORT_SYMBOL_GPL(ata_tf_read);
2735EXPORT_SYMBOL_GPL(ata_exec_command);
2736EXPORT_SYMBOL_GPL(ata_data_xfer);
2737EXPORT_SYMBOL_GPL(ata_data_xfer_noirq);
2738EXPORT_SYMBOL_GPL(ata_irq_on);
2739EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
2740EXPORT_SYMBOL_GPL(ata_hsm_move);
2741EXPORT_SYMBOL_GPL(ata_qc_issue_prot);
2742EXPORT_SYMBOL_GPL(ata_host_intr);
2743EXPORT_SYMBOL_GPL(ata_interrupt);
2744EXPORT_SYMBOL_GPL(ata_bmdma_freeze);
2745EXPORT_SYMBOL_GPL(ata_bmdma_thaw);
2746EXPORT_SYMBOL_GPL(ata_std_prereset);
2747EXPORT_SYMBOL_GPL(ata_dev_try_classify);
2748EXPORT_SYMBOL_GPL(ata_wait_after_reset);
2749EXPORT_SYMBOL_GPL(ata_std_softreset);
2750EXPORT_SYMBOL_GPL(sata_std_hardreset);
2751EXPORT_SYMBOL_GPL(ata_std_postreset);
2752EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
2753EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
2754EXPORT_SYMBOL_GPL(ata_sff_port_start);
2755EXPORT_SYMBOL_GPL(ata_std_ports);
2756EXPORT_SYMBOL_GPL(ata_bmdma_setup);
2757EXPORT_SYMBOL_GPL(ata_bmdma_start);
2758EXPORT_SYMBOL_GPL(ata_bmdma_stop);
2759EXPORT_SYMBOL_GPL(ata_bmdma_status);
2760EXPORT_SYMBOL_GPL(ata_bus_reset);
2761#ifdef CONFIG_PCI
2762EXPORT_SYMBOL_GPL(ata_pci_clear_simplex);
2763EXPORT_SYMBOL_GPL(ata_pci_default_filter);
2764EXPORT_SYMBOL_GPL(ata_pci_init_bmdma);
2765EXPORT_SYMBOL_GPL(ata_pci_init_sff_host);
2766EXPORT_SYMBOL_GPL(ata_pci_prepare_sff_host);
2767EXPORT_SYMBOL_GPL(ata_pci_activate_sff_host);
2768EXPORT_SYMBOL_GPL(ata_pci_init_one);
2769#endif /* CONFIG_PCI */
diff --git a/drivers/ata/libata.h b/drivers/ata/libata.h
index aa884f71a12a..a69f663c7402 100644
--- a/drivers/ata/libata.h
+++ b/drivers/ata/libata.h
@@ -67,6 +67,8 @@ extern int ata_build_rw_tf(struct ata_taskfile *tf, struct ata_device *dev,
67 unsigned int tag); 67 unsigned int tag);
68extern u64 ata_tf_read_block(struct ata_taskfile *tf, struct ata_device *dev); 68extern u64 ata_tf_read_block(struct ata_taskfile *tf, struct ata_device *dev);
69extern void ata_dev_disable(struct ata_device *dev); 69extern void ata_dev_disable(struct ata_device *dev);
70extern void ata_pio_queue_task(struct ata_port *ap, void *data,
71 unsigned long delay);
70extern void ata_port_flush_task(struct ata_port *ap); 72extern void ata_port_flush_task(struct ata_port *ap);
71extern unsigned ata_exec_internal(struct ata_device *dev, 73extern unsigned ata_exec_internal(struct ata_device *dev,
72 struct ata_taskfile *tf, const u8 *cdb, 74 struct ata_taskfile *tf, const u8 *cdb,
@@ -91,8 +93,6 @@ extern void ata_qc_free(struct ata_queued_cmd *qc);
91extern void ata_qc_issue(struct ata_queued_cmd *qc); 93extern void ata_qc_issue(struct ata_queued_cmd *qc);
92extern void __ata_qc_complete(struct ata_queued_cmd *qc); 94extern void __ata_qc_complete(struct ata_queued_cmd *qc);
93extern int ata_check_atapi_dma(struct ata_queued_cmd *qc); 95extern int ata_check_atapi_dma(struct ata_queued_cmd *qc);
94extern void ata_dev_select(struct ata_port *ap, unsigned int device,
95 unsigned int wait, unsigned int can_sleep);
96extern void swap_buf_le16(u16 *buf, unsigned int buf_words); 96extern void swap_buf_le16(u16 *buf, unsigned int buf_words);
97extern int ata_flush_cache(struct ata_device *dev); 97extern int ata_flush_cache(struct ata_device *dev);
98extern void ata_dev_init(struct ata_device *dev); 98extern void ata_dev_init(struct ata_device *dev);
@@ -194,7 +194,9 @@ extern int ata_eh_recover(struct ata_port *ap, ata_prereset_fn_t prereset,
194extern void ata_eh_finish(struct ata_port *ap); 194extern void ata_eh_finish(struct ata_port *ap);
195 195
196/* libata-sff.c */ 196/* libata-sff.c */
197extern void ata_dev_select(struct ata_port *ap, unsigned int device,
198 unsigned int wait, unsigned int can_sleep);
197extern u8 ata_irq_on(struct ata_port *ap); 199extern u8 ata_irq_on(struct ata_port *ap);
198 200extern void ata_pio_task(struct work_struct *work);
199 201
200#endif /* __LIBATA_H__ */ 202#endif /* __LIBATA_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-08 00:46:40 -0400