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-rw-r--r--drivers/rtc/rtc-sa1100.c12
-rw-r--r--drivers/video/Kconfig5
-rw-r--r--drivers/video/pxafb.c859
-rw-r--r--drivers/video/pxafb.h79
-rw-r--r--drivers/watchdog/sa1100_wdt.c11
5 files changed, 693 insertions, 273 deletions
diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c
index 66a9bb85bbe8..d26a5f82aaba 100644
--- a/drivers/rtc/rtc-sa1100.c
+++ b/drivers/rtc/rtc-sa1100.c
@@ -38,11 +38,11 @@
38#include <mach/pxa-regs.h> 38#include <mach/pxa-regs.h>
39#endif 39#endif
40 40
41#define TIMER_FREQ CLOCK_TICK_RATE
42#define RTC_DEF_DIVIDER 32768 - 1 41#define RTC_DEF_DIVIDER 32768 - 1
43#define RTC_DEF_TRIM 0 42#define RTC_DEF_TRIM 0
44 43
45static unsigned long rtc_freq = 1024; 44static unsigned long rtc_freq = 1024;
45static unsigned long timer_freq;
46static struct rtc_time rtc_alarm; 46static struct rtc_time rtc_alarm;
47static DEFINE_SPINLOCK(sa1100_rtc_lock); 47static DEFINE_SPINLOCK(sa1100_rtc_lock);
48 48
@@ -157,7 +157,7 @@ static irqreturn_t timer1_interrupt(int irq, void *dev_id)
157 rtc_update_irq(rtc, rtc_timer1_count, RTC_PF | RTC_IRQF); 157 rtc_update_irq(rtc, rtc_timer1_count, RTC_PF | RTC_IRQF);
158 158
159 if (rtc_timer1_count == 1) 159 if (rtc_timer1_count == 1)
160 rtc_timer1_count = (rtc_freq * ((1<<30)/(TIMER_FREQ>>2))); 160 rtc_timer1_count = (rtc_freq * ((1 << 30) / (timer_freq >> 2)));
161 161
162 return IRQ_HANDLED; 162 return IRQ_HANDLED;
163} 163}
@@ -166,7 +166,7 @@ static int sa1100_rtc_read_callback(struct device *dev, int data)
166{ 166{
167 if (data & RTC_PF) { 167 if (data & RTC_PF) {
168 /* interpolate missed periods and set match for the next */ 168 /* interpolate missed periods and set match for the next */
169 unsigned long period = TIMER_FREQ/rtc_freq; 169 unsigned long period = timer_freq / rtc_freq;
170 unsigned long oscr = OSCR; 170 unsigned long oscr = OSCR;
171 unsigned long osmr1 = OSMR1; 171 unsigned long osmr1 = OSMR1;
172 unsigned long missed = (oscr - osmr1)/period; 172 unsigned long missed = (oscr - osmr1)/period;
@@ -263,7 +263,7 @@ static int sa1100_rtc_ioctl(struct device *dev, unsigned int cmd,
263 return 0; 263 return 0;
264 case RTC_PIE_ON: 264 case RTC_PIE_ON:
265 spin_lock_irq(&sa1100_rtc_lock); 265 spin_lock_irq(&sa1100_rtc_lock);
266 OSMR1 = TIMER_FREQ/rtc_freq + OSCR; 266 OSMR1 = timer_freq / rtc_freq + OSCR;
267 OIER |= OIER_E1; 267 OIER |= OIER_E1;
268 rtc_timer1_count = 1; 268 rtc_timer1_count = 1;
269 spin_unlock_irq(&sa1100_rtc_lock); 269 spin_unlock_irq(&sa1100_rtc_lock);
@@ -271,7 +271,7 @@ static int sa1100_rtc_ioctl(struct device *dev, unsigned int cmd,
271 case RTC_IRQP_READ: 271 case RTC_IRQP_READ:
272 return put_user(rtc_freq, (unsigned long *)arg); 272 return put_user(rtc_freq, (unsigned long *)arg);
273 case RTC_IRQP_SET: 273 case RTC_IRQP_SET:
274 if (arg < 1 || arg > TIMER_FREQ) 274 if (arg < 1 || arg > timer_freq)
275 return -EINVAL; 275 return -EINVAL;
276 rtc_freq = arg; 276 rtc_freq = arg;
277 return 0; 277 return 0;
@@ -352,6 +352,8 @@ static int sa1100_rtc_probe(struct platform_device *pdev)
352{ 352{
353 struct rtc_device *rtc; 353 struct rtc_device *rtc;
354 354
355 timer_freq = get_clock_tick_rate();
356
355 /* 357 /*
356 * According to the manual we should be able to let RTTR be zero 358 * According to the manual we should be able to let RTTR be zero
357 * and then a default diviser for a 32.768KHz clock is used. 359 * and then a default diviser for a 32.768KHz clock is used.
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 237301849075..bc2645db1587 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1817,6 +1817,11 @@ config FB_PXA
1817 1817
1818 If unsure, say N. 1818 If unsure, say N.
1819 1819
1820config FB_PXA_OVERLAY
1821 bool "Support PXA27x/PXA3xx Overlay(s) as framebuffer"
1822 default n
1823 depends on FB_PXA && (PXA27x || PXA3xx)
1824
1820config FB_PXA_SMARTPANEL 1825config FB_PXA_SMARTPANEL
1821 bool "PXA Smartpanel LCD support" 1826 bool "PXA Smartpanel LCD support"
1822 default n 1827 default n
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index d0fd22e06737..48ff701d3a72 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -20,6 +20,16 @@
20 * 20 *
21 * linux-arm-kernel@lists.arm.linux.org.uk 21 * linux-arm-kernel@lists.arm.linux.org.uk
22 * 22 *
23 * Add support for overlay1 and overlay2 based on pxafb_overlay.c:
24 *
25 * Copyright (C) 2004, Intel Corporation
26 *
27 * 2003/08/27: <yu.tang@intel.com>
28 * 2004/03/10: <stanley.cai@intel.com>
29 * 2004/10/28: <yan.yin@intel.com>
30 *
31 * Copyright (C) 2006-2008 Marvell International Ltd.
32 * All Rights Reserved
23 */ 33 */
24 34
25#include <linux/module.h> 35#include <linux/module.h>
@@ -66,11 +76,16 @@
66 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB) 76 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
67 77
68#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\ 78#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
69 LCCR3_PCD | LCCR3_BPP) 79 LCCR3_PCD | LCCR3_BPP(0xf))
70 80
71static int pxafb_activate_var(struct fb_var_screeninfo *var, 81static int pxafb_activate_var(struct fb_var_screeninfo *var,
72 struct pxafb_info *); 82 struct pxafb_info *);
73static void set_ctrlr_state(struct pxafb_info *fbi, u_int state); 83static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
84static void setup_base_frame(struct pxafb_info *fbi, int branch);
85static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
86 unsigned long offset, size_t size);
87
88static unsigned long video_mem_size = 0;
74 89
75static inline unsigned long 90static inline unsigned long
76lcd_readl(struct pxafb_info *fbi, unsigned int off) 91lcd_readl(struct pxafb_info *fbi, unsigned int off)
@@ -152,6 +167,12 @@ pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
152 val |= ((blue >> 8) & 0x000000fc); 167 val |= ((blue >> 8) & 0x000000fc);
153 ((u32 *)(fbi->palette_cpu))[regno] = val; 168 ((u32 *)(fbi->palette_cpu))[regno] = val;
154 break; 169 break;
170 case LCCR4_PAL_FOR_3:
171 val = ((red << 8) & 0x00ff0000);
172 val |= ((green >> 0) & 0x0000ff00);
173 val |= ((blue >> 8) & 0x000000ff);
174 ((u32 *)(fbi->palette_cpu))[regno] = val;
175 break;
155 } 176 }
156 177
157 return 0; 178 return 0;
@@ -212,37 +233,110 @@ pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
212 return ret; 233 return ret;
213} 234}
214 235
215/* 236/* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
216 * pxafb_bpp_to_lccr3(): 237static inline int var_to_depth(struct fb_var_screeninfo *var)
217 * Convert a bits per pixel value to the correct bit pattern for LCCR3
218 */
219static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
220{ 238{
221 int ret = 0; 239 return var->red.length + var->green.length +
240 var->blue.length + var->transp.length;
241}
242
243/* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
244static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
245{
246 int bpp = -EINVAL;
247
222 switch (var->bits_per_pixel) { 248 switch (var->bits_per_pixel) {
223 case 1: ret = LCCR3_1BPP; break; 249 case 1: bpp = 0; break;
224 case 2: ret = LCCR3_2BPP; break; 250 case 2: bpp = 1; break;
225 case 4: ret = LCCR3_4BPP; break; 251 case 4: bpp = 2; break;
226 case 8: ret = LCCR3_8BPP; break; 252 case 8: bpp = 3; break;
227 case 16: ret = LCCR3_16BPP; break; 253 case 16: bpp = 4; break;
228 case 24: 254 case 24:
229 switch (var->red.length + var->green.length + 255 switch (var_to_depth(var)) {
230 var->blue.length + var->transp.length) { 256 case 18: bpp = 6; break; /* 18-bits/pixel packed */
231 case 18: ret = LCCR3_18BPP_P | LCCR3_PDFOR_3; break; 257 case 19: bpp = 8; break; /* 19-bits/pixel packed */
232 case 19: ret = LCCR3_19BPP_P; break; 258 case 24: bpp = 9; break;
233 } 259 }
234 break; 260 break;
235 case 32: 261 case 32:
236 switch (var->red.length + var->green.length + 262 switch (var_to_depth(var)) {
237 var->blue.length + var->transp.length) { 263 case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
238 case 18: ret = LCCR3_18BPP | LCCR3_PDFOR_3; break; 264 case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
239 case 19: ret = LCCR3_19BPP; break; 265 case 25: bpp = 10; break;
240 case 24: ret = LCCR3_24BPP | LCCR3_PDFOR_3; break;
241 case 25: ret = LCCR3_25BPP; break;
242 } 266 }
243 break; 267 break;
244 } 268 }
245 return ret; 269 return bpp;
270}
271
272/*
273 * pxafb_var_to_lccr3():
274 * Convert a bits per pixel value to the correct bit pattern for LCCR3
275 *
276 * NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
277 * implication of the acutal use of transparency bit, which we handle it
278 * here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
279 * Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
280 *
281 * Transparency for palette pixel formats is not supported at the moment.
282 */
283static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
284{
285 int bpp = pxafb_var_to_bpp(var);
286 uint32_t lccr3;
287
288 if (bpp < 0)
289 return 0;
290
291 lccr3 = LCCR3_BPP(bpp);
292
293 switch (var_to_depth(var)) {
294 case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
295 case 18: lccr3 |= LCCR3_PDFOR_3; break;
296 case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
297 break;
298 case 19:
299 case 25: lccr3 |= LCCR3_PDFOR_0; break;
300 }
301 return lccr3;
302}
303
304#define SET_PIXFMT(v, r, g, b, t) \
305({ \
306 (v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \
307 (v)->transp.length = (t) ? (t) : 0; \
308 (v)->blue.length = (b); (v)->blue.offset = 0; \
309 (v)->green.length = (g); (v)->green.offset = (b); \
310 (v)->red.length = (r); (v)->red.offset = (b) + (g); \
311})
312
313/* set the RGBT bitfields of fb_var_screeninf according to
314 * var->bits_per_pixel and given depth
315 */
316static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
317{
318 if (depth == 0)
319 depth = var->bits_per_pixel;
320
321 if (var->bits_per_pixel < 16) {
322 /* indexed pixel formats */
323 var->red.offset = 0; var->red.length = 8;
324 var->green.offset = 0; var->green.length = 8;
325 var->blue.offset = 0; var->blue.length = 8;
326 var->transp.offset = 0; var->transp.length = 8;
327 }
328
329 switch (depth) {
330 case 16: var->transp.length ?
331 SET_PIXFMT(var, 5, 5, 5, 1) : /* RGBT555 */
332 SET_PIXFMT(var, 5, 6, 5, 0); break; /* RGB565 */
333 case 18: SET_PIXFMT(var, 6, 6, 6, 0); break; /* RGB666 */
334 case 19: SET_PIXFMT(var, 6, 6, 6, 1); break; /* RGBT666 */
335 case 24: var->transp.length ?
336 SET_PIXFMT(var, 8, 8, 7, 1) : /* RGBT887 */
337 SET_PIXFMT(var, 8, 8, 8, 0); break; /* RGB888 */
338 case 25: SET_PIXFMT(var, 8, 8, 8, 1); break; /* RGBT888 */
339 }
246} 340}
247 341
248#ifdef CONFIG_CPU_FREQ 342#ifdef CONFIG_CPU_FREQ
@@ -304,8 +398,49 @@ static void pxafb_setmode(struct fb_var_screeninfo *var,
304 var->lower_margin = mode->lower_margin; 398 var->lower_margin = mode->lower_margin;
305 var->sync = mode->sync; 399 var->sync = mode->sync;
306 var->grayscale = mode->cmap_greyscale; 400 var->grayscale = mode->cmap_greyscale;
307 var->xres_virtual = var->xres; 401
308 var->yres_virtual = var->yres; 402 /* set the initial RGBA bitfields */
403 pxafb_set_pixfmt(var, mode->depth);
404}
405
406static int pxafb_adjust_timing(struct pxafb_info *fbi,
407 struct fb_var_screeninfo *var)
408{
409 int line_length;
410
411 var->xres = max_t(int, var->xres, MIN_XRES);
412 var->yres = max_t(int, var->yres, MIN_YRES);
413
414 if (!(fbi->lccr0 & LCCR0_LCDT)) {
415 clamp_val(var->hsync_len, 1, 64);
416 clamp_val(var->vsync_len, 1, 64);
417 clamp_val(var->left_margin, 1, 255);
418 clamp_val(var->right_margin, 1, 255);
419 clamp_val(var->upper_margin, 1, 255);
420 clamp_val(var->lower_margin, 1, 255);
421 }
422
423 /* make sure each line is aligned on word boundary */
424 line_length = var->xres * var->bits_per_pixel / 8;
425 line_length = ALIGN(line_length, 4);
426 var->xres = line_length * 8 / var->bits_per_pixel;
427
428 /* we don't support xpan, force xres_virtual to be equal to xres */
429 var->xres_virtual = var->xres;
430
431 if (var->accel_flags & FB_ACCELF_TEXT)
432 var->yres_virtual = fbi->fb.fix.smem_len / line_length;
433 else
434 var->yres_virtual = max(var->yres_virtual, var->yres);
435
436 /* check for limits */
437 if (var->xres > MAX_XRES || var->yres > MAX_YRES)
438 return -EINVAL;
439
440 if (var->yres > var->yres_virtual)
441 return -EINVAL;
442
443 return 0;
309} 444}
310 445
311/* 446/*
@@ -321,11 +456,7 @@ static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
321{ 456{
322 struct pxafb_info *fbi = (struct pxafb_info *)info; 457 struct pxafb_info *fbi = (struct pxafb_info *)info;
323 struct pxafb_mach_info *inf = fbi->dev->platform_data; 458 struct pxafb_mach_info *inf = fbi->dev->platform_data;
324 459 int err;
325 if (var->xres < MIN_XRES)
326 var->xres = MIN_XRES;
327 if (var->yres < MIN_YRES)
328 var->yres = MIN_YRES;
329 460
330 if (inf->fixed_modes) { 461 if (inf->fixed_modes) {
331 struct pxafb_mode_info *mode; 462 struct pxafb_mode_info *mode;
@@ -334,74 +465,18 @@ static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
334 if (!mode) 465 if (!mode)
335 return -EINVAL; 466 return -EINVAL;
336 pxafb_setmode(var, mode); 467 pxafb_setmode(var, mode);
337 } else {
338 if (var->xres > inf->modes->xres)
339 return -EINVAL;
340 if (var->yres > inf->modes->yres)
341 return -EINVAL;
342 if (var->bits_per_pixel > inf->modes->bpp)
343 return -EINVAL;
344 } 468 }
345 469
346 var->xres_virtual = 470 /* do a test conversion to BPP fields to check the color formats */
347 max(var->xres_virtual, var->xres); 471 err = pxafb_var_to_bpp(var);
348 var->yres_virtual = 472 if (err < 0)
349 max(var->yres_virtual, var->yres); 473 return err;
350 474
351 /* 475 pxafb_set_pixfmt(var, var_to_depth(var));
352 * Setup the RGB parameters for this display.
353 *
354 * The pixel packing format is described on page 7-11 of the
355 * PXA2XX Developer's Manual.
356 */
357 if (var->bits_per_pixel == 16) {
358 var->red.offset = 11; var->red.length = 5;
359 var->green.offset = 5; var->green.length = 6;
360 var->blue.offset = 0; var->blue.length = 5;
361 var->transp.offset = var->transp.length = 0;
362 } else if (var->bits_per_pixel > 16) {
363 struct pxafb_mode_info *mode;
364
365 mode = pxafb_getmode(inf, var);
366 if (!mode)
367 return -EINVAL;
368 476
369 switch (mode->depth) { 477 err = pxafb_adjust_timing(fbi, var);
370 case 18: /* RGB666 */ 478 if (err)
371 var->transp.offset = var->transp.length = 0; 479 return err;
372 var->red.offset = 12; var->red.length = 6;
373 var->green.offset = 6; var->green.length = 6;
374 var->blue.offset = 0; var->blue.length = 6;
375 break;
376 case 19: /* RGBT666 */
377 var->transp.offset = 18; var->transp.length = 1;
378 var->red.offset = 12; var->red.length = 6;
379 var->green.offset = 6; var->green.length = 6;
380 var->blue.offset = 0; var->blue.length = 6;
381 break;
382 case 24: /* RGB888 */
383 var->transp.offset = var->transp.length = 0;
384 var->red.offset = 16; var->red.length = 8;
385 var->green.offset = 8; var->green.length = 8;
386 var->blue.offset = 0; var->blue.length = 8;
387 break;
388 case 25: /* RGBT888 */
389 var->transp.offset = 24; var->transp.length = 1;
390 var->red.offset = 16; var->red.length = 8;
391 var->green.offset = 8; var->green.length = 8;
392 var->blue.offset = 0; var->blue.length = 8;
393 break;
394 default:
395 return -EINVAL;
396 }
397 } else {
398 var->red.offset = var->green.offset = 0;
399 var->blue.offset = var->transp.offset = 0;
400 var->red.length = 8;
401 var->green.length = 8;
402 var->blue.length = 8;
403 var->transp.length = 0;
404 }
405 480
406#ifdef CONFIG_CPU_FREQ 481#ifdef CONFIG_CPU_FREQ
407 pr_debug("pxafb: dma period = %d ps\n", 482 pr_debug("pxafb: dma period = %d ps\n",
@@ -411,11 +486,6 @@ static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
411 return 0; 486 return 0;
412} 487}
413 488
414static inline void pxafb_set_truecolor(u_int is_true_color)
415{
416 /* do your machine-specific setup if needed */
417}
418
419/* 489/*
420 * pxafb_set_par(): 490 * pxafb_set_par():
421 * Set the user defined part of the display for the specified console 491 * Set the user defined part of the display for the specified console
@@ -448,11 +518,6 @@ static int pxafb_set_par(struct fb_info *info)
448 518
449 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0]; 519 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
450 520
451 /*
452 * Set (any) board control register to handle new color depth
453 */
454 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
455
456 if (fbi->fb.var.bits_per_pixel >= 16) 521 if (fbi->fb.var.bits_per_pixel >= 16)
457 fb_dealloc_cmap(&fbi->fb.cmap); 522 fb_dealloc_cmap(&fbi->fb.cmap);
458 else 523 else
@@ -463,6 +528,24 @@ static int pxafb_set_par(struct fb_info *info)
463 return 0; 528 return 0;
464} 529}
465 530
531static int pxafb_pan_display(struct fb_var_screeninfo *var,
532 struct fb_info *info)
533{
534 struct pxafb_info *fbi = (struct pxafb_info *)info;
535 int dma = DMA_MAX + DMA_BASE;
536
537 if (fbi->state != C_ENABLE)
538 return 0;
539
540 setup_base_frame(fbi, 1);
541
542 if (fbi->lccr0 & LCCR0_SDS)
543 lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
544
545 lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
546 return 0;
547}
548
466/* 549/*
467 * pxafb_blank(): 550 * pxafb_blank():
468 * Blank the display by setting all palette values to zero. Note, the 551 * Blank the display by setting all palette values to zero. Note, the
@@ -498,32 +581,342 @@ static int pxafb_blank(int blank, struct fb_info *info)
498 return 0; 581 return 0;
499} 582}
500 583
501static int pxafb_mmap(struct fb_info *info,
502 struct vm_area_struct *vma)
503{
504 struct pxafb_info *fbi = (struct pxafb_info *)info;
505 unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
506
507 if (off < info->fix.smem_len) {
508 vma->vm_pgoff += fbi->video_offset / PAGE_SIZE;
509 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
510 fbi->map_dma, fbi->map_size);
511 }
512 return -EINVAL;
513}
514
515static struct fb_ops pxafb_ops = { 584static struct fb_ops pxafb_ops = {
516 .owner = THIS_MODULE, 585 .owner = THIS_MODULE,
517 .fb_check_var = pxafb_check_var, 586 .fb_check_var = pxafb_check_var,
518 .fb_set_par = pxafb_set_par, 587 .fb_set_par = pxafb_set_par,
588 .fb_pan_display = pxafb_pan_display,
519 .fb_setcolreg = pxafb_setcolreg, 589 .fb_setcolreg = pxafb_setcolreg,
520 .fb_fillrect = cfb_fillrect, 590 .fb_fillrect = cfb_fillrect,
521 .fb_copyarea = cfb_copyarea, 591 .fb_copyarea = cfb_copyarea,
522 .fb_imageblit = cfb_imageblit, 592 .fb_imageblit = cfb_imageblit,
523 .fb_blank = pxafb_blank, 593 .fb_blank = pxafb_blank,
524 .fb_mmap = pxafb_mmap,
525}; 594};
526 595
596#ifdef CONFIG_FB_PXA_OVERLAY
597static void overlay1fb_setup(struct pxafb_layer *ofb)
598{
599 int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
600 unsigned long start = ofb->video_mem_phys;
601 setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size);
602}
603
604/* Depending on the enable status of overlay1/2, the DMA should be
605 * updated from FDADRx (when disabled) or FBRx (when enabled).
606 */
607static void overlay1fb_enable(struct pxafb_layer *ofb)
608{
609 int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN;
610 uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0);
611
612 lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1);
613 lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]);
614 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN);
615}
616
617static void overlay1fb_disable(struct pxafb_layer *ofb)
618{
619 uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5);
620
621 lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN);
622
623 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1));
624 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1));
625 lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3);
626
627 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
628 pr_warning("%s: timeout disabling overlay1\n", __func__);
629
630 lcd_writel(ofb->fbi, LCCR5, lccr5);
631}
632
633static void overlay2fb_setup(struct pxafb_layer *ofb)
634{
635 int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
636 unsigned long start[3] = { ofb->video_mem_phys, 0, 0 };
637
638 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) {
639 size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
640 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
641 } else {
642 size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual;
643 switch (pfor) {
644 case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break;
645 case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break;
646 case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break;
647 }
648 start[1] = start[0] + size;
649 start[2] = start[1] + size / div;
650 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
651 setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div);
652 setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div);
653 }
654}
655
656static void overlay2fb_enable(struct pxafb_layer *ofb)
657{
658 int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
659 int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN;
660 uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y] | (enabled ? 0x1 : 0);
661 uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0);
662 uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0);
663
664 if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED)
665 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
666 else {
667 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
668 lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3);
669 lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4);
670 }
671 lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]);
672 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN);
673}
674
675static void overlay2fb_disable(struct pxafb_layer *ofb)
676{
677 uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5);
678
679 lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN);
680
681 lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2));
682 lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2));
683 lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y] | 0x3);
684 lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3);
685 lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3);
686
687 if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
688 pr_warning("%s: timeout disabling overlay2\n", __func__);
689}
690
691static struct pxafb_layer_ops ofb_ops[] = {
692 [0] = {
693 .enable = overlay1fb_enable,
694 .disable = overlay1fb_disable,
695 .setup = overlay1fb_setup,
696 },
697 [1] = {
698 .enable = overlay2fb_enable,
699 .disable = overlay2fb_disable,
700 .setup = overlay2fb_setup,
701 },
702};
703
704static int overlayfb_open(struct fb_info *info, int user)
705{
706 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
707
708 /* no support for framebuffer console on overlay */
709 if (user == 0)
710 return -ENODEV;
711
712 /* allow only one user at a time */
713 if (atomic_inc_and_test(&ofb->usage))
714 return -EBUSY;
715
716 /* unblank the base framebuffer */
717 fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK);
718 return 0;
719}
720
721static int overlayfb_release(struct fb_info *info, int user)
722{
723 struct pxafb_layer *ofb = (struct pxafb_layer*) info;
724
725 atomic_dec(&ofb->usage);
726 ofb->ops->disable(ofb);
727
728 free_pages_exact(ofb->video_mem, ofb->video_mem_size);
729 ofb->video_mem = NULL;
730 ofb->video_mem_size = 0;
731 return 0;
732}
733
734static int overlayfb_check_var(struct fb_var_screeninfo *var,
735 struct fb_info *info)
736{
737 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
738 struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var;
739 int xpos, ypos, pfor, bpp;
740
741 xpos = NONSTD_TO_XPOS(var->nonstd);
742 ypos = NONSTD_TO_XPOS(var->nonstd);
743 pfor = NONSTD_TO_PFOR(var->nonstd);
744
745 bpp = pxafb_var_to_bpp(var);
746 if (bpp < 0)
747 return -EINVAL;
748
749 /* no support for YUV format on overlay1 */
750 if (ofb->id == OVERLAY1 && pfor != 0)
751 return -EINVAL;
752
753 /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */
754 switch (pfor) {
755 case OVERLAY_FORMAT_RGB:
756 bpp = pxafb_var_to_bpp(var);
757 if (bpp < 0)
758 return -EINVAL;
759
760 pxafb_set_pixfmt(var, var_to_depth(var));
761 break;
762 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
763 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break;
764 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break;
765 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break;
766 default:
767 return -EINVAL;
768 }
769
770 /* each line must start at a 32-bit word boundary */
771 if ((xpos * bpp) % 32)
772 return -EINVAL;
773
774 /* xres must align on 32-bit word boundary */
775 var->xres = roundup(var->xres * bpp, 32) / bpp;
776
777 if ((xpos + var->xres > base_var->xres) ||
778 (ypos + var->yres > base_var->yres))
779 return -EINVAL;
780
781 var->xres_virtual = var->xres;
782 var->yres_virtual = max(var->yres, var->yres_virtual);
783 return 0;
784}
785
786static int overlayfb_map_video_memory(struct pxafb_layer *ofb)
787{
788 struct fb_var_screeninfo *var = &ofb->fb.var;
789 int pfor = NONSTD_TO_PFOR(var->nonstd);
790 int size, bpp = 0;
791
792 switch (pfor) {
793 case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break;
794 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
795 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break;
796 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break;
797 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break;
798 }
799
800 ofb->fb.fix.line_length = var->xres_virtual * bpp / 8;
801
802 size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual);
803
804 /* don't re-allocate if the original video memory is enough */
805 if (ofb->video_mem) {
806 if (ofb->video_mem_size >= size)
807 return 0;
808
809 free_pages_exact(ofb->video_mem, ofb->video_mem_size);
810 }
811
812 ofb->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
813 if (ofb->video_mem == NULL)
814 return -ENOMEM;
815
816 ofb->video_mem_phys = virt_to_phys(ofb->video_mem);
817 ofb->video_mem_size = size;
818
819 ofb->fb.fix.smem_start = ofb->video_mem_phys;
820 ofb->fb.fix.smem_len = ofb->fb.fix.line_length * var->yres_virtual;
821 ofb->fb.screen_base = ofb->video_mem;
822 return 0;
823}
824
825static int overlayfb_set_par(struct fb_info *info)
826{
827 struct pxafb_layer *ofb = (struct pxafb_layer *)info;
828 struct fb_var_screeninfo *var = &info->var;
829 int xpos, ypos, pfor, bpp, ret;
830
831 ret = overlayfb_map_video_memory(ofb);
832 if (ret)
833 return ret;
834
835 bpp = pxafb_var_to_bpp(var);
836 xpos = NONSTD_TO_XPOS(var->nonstd);
837 ypos = NONSTD_TO_XPOS(var->nonstd);
838 pfor = NONSTD_TO_PFOR(var->nonstd);
839
840 ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) |
841 OVLxC1_BPP(bpp);
842 ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos);
843
844 if (ofb->id == OVERLAY2)
845 ofb->control[1] |= OVL2C2_PFOR(pfor);
846
847 ofb->ops->setup(ofb);
848 ofb->ops->enable(ofb);
849 return 0;
850}
851
852static struct fb_ops overlay_fb_ops = {
853 .owner = THIS_MODULE,
854 .fb_open = overlayfb_open,
855 .fb_release = overlayfb_release,
856 .fb_check_var = overlayfb_check_var,
857 .fb_set_par = overlayfb_set_par,
858};
859
860static void __devinit init_pxafb_overlay(struct pxafb_info *fbi,
861 struct pxafb_layer *ofb, int id)
862{
863 sprintf(ofb->fb.fix.id, "overlay%d", id + 1);
864
865 ofb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
866 ofb->fb.fix.xpanstep = 0;
867 ofb->fb.fix.ypanstep = 1;
868
869 ofb->fb.var.activate = FB_ACTIVATE_NOW;
870 ofb->fb.var.height = -1;
871 ofb->fb.var.width = -1;
872 ofb->fb.var.vmode = FB_VMODE_NONINTERLACED;
873
874 ofb->fb.fbops = &overlay_fb_ops;
875 ofb->fb.flags = FBINFO_FLAG_DEFAULT;
876 ofb->fb.node = -1;
877 ofb->fb.pseudo_palette = NULL;
878
879 ofb->id = id;
880 ofb->ops = &ofb_ops[id];
881 atomic_set(&ofb->usage, 0);
882 ofb->fbi = fbi;
883 init_completion(&ofb->branch_done);
884}
885
886static int __devinit pxafb_overlay_init(struct pxafb_info *fbi)
887{
888 int i, ret;
889
890 for (i = 0; i < 2; i++) {
891 init_pxafb_overlay(fbi, &fbi->overlay[i], i);
892 ret = register_framebuffer(&fbi->overlay[i].fb);
893 if (ret) {
894 dev_err(fbi->dev, "failed to register overlay %d\n", i);
895 return ret;
896 }
897 }
898
899 /* mask all IU/BS/EOF/SOF interrupts */
900 lcd_writel(fbi, LCCR5, ~0);
901
902 /* place overlay(s) on top of base */
903 fbi->lccr0 |= LCCR0_OUC;
904 pr_info("PXA Overlay driver loaded successfully!\n");
905 return 0;
906}
907
908static void __devexit pxafb_overlay_exit(struct pxafb_info *fbi)
909{
910 int i;
911
912 for (i = 0; i < 2; i++)
913 unregister_framebuffer(&fbi->overlay[i].fb);
914}
915#else
916static inline void pxafb_overlay_init(struct pxafb_info *fbi) {}
917static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {}
918#endif /* CONFIG_FB_PXA_OVERLAY */
919
527/* 920/*
528 * Calculate the PCD value from the clock rate (in picoseconds). 921 * Calculate the PCD value from the clock rate (in picoseconds).
529 * We take account of the PPCR clock setting. 922 * We take account of the PPCR clock setting.
@@ -603,22 +996,22 @@ unsigned long pxafb_get_hsync_time(struct device *dev)
603EXPORT_SYMBOL(pxafb_get_hsync_time); 996EXPORT_SYMBOL(pxafb_get_hsync_time);
604 997
605static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal, 998static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
606 unsigned int offset, size_t size) 999 unsigned long start, size_t size)
607{ 1000{
608 struct pxafb_dma_descriptor *dma_desc, *pal_desc; 1001 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
609 unsigned int dma_desc_off, pal_desc_off; 1002 unsigned int dma_desc_off, pal_desc_off;
610 1003
611 if (dma < 0 || dma >= DMA_MAX) 1004 if (dma < 0 || dma >= DMA_MAX * 2)
612 return -EINVAL; 1005 return -EINVAL;
613 1006
614 dma_desc = &fbi->dma_buff->dma_desc[dma]; 1007 dma_desc = &fbi->dma_buff->dma_desc[dma];
615 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]); 1008 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
616 1009
617 dma_desc->fsadr = fbi->screen_dma + offset; 1010 dma_desc->fsadr = start;
618 dma_desc->fidr = 0; 1011 dma_desc->fidr = 0;
619 dma_desc->ldcmd = size; 1012 dma_desc->ldcmd = size;
620 1013
621 if (pal < 0 || pal >= PAL_MAX) { 1014 if (pal < 0 || pal >= PAL_MAX * 2) {
622 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; 1015 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
623 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off; 1016 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
624 } else { 1017 } else {
@@ -644,6 +1037,27 @@ static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
644 return 0; 1037 return 0;
645} 1038}
646 1039
1040static void setup_base_frame(struct pxafb_info *fbi, int branch)
1041{
1042 struct fb_var_screeninfo *var = &fbi->fb.var;
1043 struct fb_fix_screeninfo *fix = &fbi->fb.fix;
1044 int nbytes, dma, pal, bpp = var->bits_per_pixel;
1045 unsigned long offset;
1046
1047 dma = DMA_BASE + (branch ? DMA_MAX : 0);
1048 pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
1049
1050 nbytes = fix->line_length * var->yres;
1051 offset = fix->line_length * var->yoffset + fbi->video_mem_phys;
1052
1053 if (fbi->lccr0 & LCCR0_SDS) {
1054 nbytes = nbytes / 2;
1055 setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
1056 }
1057
1058 setup_frame_dma(fbi, dma, pal, offset, nbytes);
1059}
1060
647#ifdef CONFIG_FB_PXA_SMARTPANEL 1061#ifdef CONFIG_FB_PXA_SMARTPANEL
648static int setup_smart_dma(struct pxafb_info *fbi) 1062static int setup_smart_dma(struct pxafb_info *fbi)
649{ 1063{
@@ -697,6 +1111,7 @@ int pxafb_smart_flush(struct fb_info *info)
697 lcd_writel(fbi, LCCR1, fbi->reg_lccr1); 1111 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
698 lcd_writel(fbi, LCCR2, fbi->reg_lccr2); 1112 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
699 lcd_writel(fbi, LCCR3, fbi->reg_lccr3); 1113 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1114 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
700 lcd_writel(fbi, FDADR0, fbi->fdadr[0]); 1115 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
701 lcd_writel(fbi, FDADR6, fbi->fdadr[6]); 1116 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
702 1117
@@ -891,51 +1306,7 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
891 struct pxafb_info *fbi) 1306 struct pxafb_info *fbi)
892{ 1307{
893 u_long flags; 1308 u_long flags;
894 size_t nbytes;
895 1309
896#if DEBUG_VAR
897 if (!(fbi->lccr0 & LCCR0_LCDT)) {
898 if (var->xres < 16 || var->xres > 1024)
899 printk(KERN_ERR "%s: invalid xres %d\n",
900 fbi->fb.fix.id, var->xres);
901 switch (var->bits_per_pixel) {
902 case 1:
903 case 2:
904 case 4:
905 case 8:
906 case 16:
907 case 24:
908 case 32:
909 break;
910 default:
911 printk(KERN_ERR "%s: invalid bit depth %d\n",
912 fbi->fb.fix.id, var->bits_per_pixel);
913 break;
914 }
915
916 if (var->hsync_len < 1 || var->hsync_len > 64)
917 printk(KERN_ERR "%s: invalid hsync_len %d\n",
918 fbi->fb.fix.id, var->hsync_len);
919 if (var->left_margin < 1 || var->left_margin > 255)
920 printk(KERN_ERR "%s: invalid left_margin %d\n",
921 fbi->fb.fix.id, var->left_margin);
922 if (var->right_margin < 1 || var->right_margin > 255)
923 printk(KERN_ERR "%s: invalid right_margin %d\n",
924 fbi->fb.fix.id, var->right_margin);
925 if (var->yres < 1 || var->yres > 1024)
926 printk(KERN_ERR "%s: invalid yres %d\n",
927 fbi->fb.fix.id, var->yres);
928 if (var->vsync_len < 1 || var->vsync_len > 64)
929 printk(KERN_ERR "%s: invalid vsync_len %d\n",
930 fbi->fb.fix.id, var->vsync_len);
931 if (var->upper_margin < 0 || var->upper_margin > 255)
932 printk(KERN_ERR "%s: invalid upper_margin %d\n",
933 fbi->fb.fix.id, var->upper_margin);
934 if (var->lower_margin < 0 || var->lower_margin > 255)
935 printk(KERN_ERR "%s: invalid lower_margin %d\n",
936 fbi->fb.fix.id, var->lower_margin);
937 }
938#endif
939 /* Update shadow copy atomically */ 1310 /* Update shadow copy atomically */
940 local_irq_save(flags); 1311 local_irq_save(flags);
941 1312
@@ -946,23 +1317,13 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
946#endif 1317#endif
947 setup_parallel_timing(fbi, var); 1318 setup_parallel_timing(fbi, var);
948 1319
1320 setup_base_frame(fbi, 0);
1321
949 fbi->reg_lccr0 = fbi->lccr0 | 1322 fbi->reg_lccr0 = fbi->lccr0 |
950 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM | 1323 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
951 LCCR0_QDM | LCCR0_BM | LCCR0_OUM); 1324 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
952 1325
953 fbi->reg_lccr3 |= pxafb_bpp_to_lccr3(var); 1326 fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
954
955 nbytes = var->yres * fbi->fb.fix.line_length;
956
957 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) {
958 nbytes = nbytes / 2;
959 setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes);
960 }
961
962 if ((var->bits_per_pixel >= 16) || (fbi->lccr0 & LCCR0_LCDT))
963 setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes);
964 else
965 setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes);
966 1327
967 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK; 1328 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
968 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK); 1329 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
@@ -976,6 +1337,7 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
976 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) || 1337 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
977 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) || 1338 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
978 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) || 1339 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
1340 (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
979 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) || 1341 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
980 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1])) 1342 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
981 pxafb_schedule_work(fbi, C_REENABLE); 1343 pxafb_schedule_work(fbi, C_REENABLE);
@@ -1022,6 +1384,7 @@ static void pxafb_enable_controller(struct pxafb_info *fbi)
1022 return; 1384 return;
1023 1385
1024 /* Sequence from 11.7.10 */ 1386 /* Sequence from 11.7.10 */
1387 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1025 lcd_writel(fbi, LCCR3, fbi->reg_lccr3); 1388 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1026 lcd_writel(fbi, LCCR2, fbi->reg_lccr2); 1389 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1027 lcd_writel(fbi, LCCR1, fbi->reg_lccr1); 1390 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
@@ -1063,8 +1426,9 @@ static void pxafb_disable_controller(struct pxafb_info *fbi)
1063static irqreturn_t pxafb_handle_irq(int irq, void *dev_id) 1426static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1064{ 1427{
1065 struct pxafb_info *fbi = dev_id; 1428 struct pxafb_info *fbi = dev_id;
1066 unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR); 1429 unsigned int lccr0, lcsr, lcsr1;
1067 1430
1431 lcsr = lcd_readl(fbi, LCSR);
1068 if (lcsr & LCSR_LDD) { 1432 if (lcsr & LCSR_LDD) {
1069 lccr0 = lcd_readl(fbi, LCCR0); 1433 lccr0 = lcd_readl(fbi, LCCR0);
1070 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM); 1434 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
@@ -1075,8 +1439,18 @@ static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1075 if (lcsr & LCSR_CMD_INT) 1439 if (lcsr & LCSR_CMD_INT)
1076 complete(&fbi->command_done); 1440 complete(&fbi->command_done);
1077#endif 1441#endif
1078
1079 lcd_writel(fbi, LCSR, lcsr); 1442 lcd_writel(fbi, LCSR, lcsr);
1443
1444#ifdef CONFIG_FB_PXA_OVERLAY
1445 lcsr1 = lcd_readl(fbi, LCSR1);
1446 if (lcsr1 & LCSR1_BS(1))
1447 complete(&fbi->overlay[0].branch_done);
1448
1449 if (lcsr1 & LCSR1_BS(2))
1450 complete(&fbi->overlay[1].branch_done);
1451
1452 lcd_writel(fbi, LCSR1, lcsr1);
1453#endif
1080 return IRQ_HANDLED; 1454 return IRQ_HANDLED;
1081} 1455}
1082 1456
@@ -1267,72 +1641,34 @@ static int pxafb_resume(struct platform_device *dev)
1267#define pxafb_resume NULL 1641#define pxafb_resume NULL
1268#endif 1642#endif
1269 1643
1270/* 1644static int __devinit pxafb_init_video_memory(struct pxafb_info *fbi)
1271 * pxafb_map_video_memory():
1272 * Allocates the DRAM memory for the frame buffer. This buffer is
1273 * remapped into a non-cached, non-buffered, memory region to
1274 * allow palette and pixel writes to occur without flushing the
1275 * cache. Once this area is remapped, all virtual memory
1276 * access to the video memory should occur at the new region.
1277 */
1278static int __devinit pxafb_map_video_memory(struct pxafb_info *fbi)
1279{ 1645{
1280 /* 1646 int size = PAGE_ALIGN(fbi->video_mem_size);
1281 * We reserve one page for the palette, plus the size
1282 * of the framebuffer.
1283 */
1284 fbi->video_offset = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
1285 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + fbi->video_offset);
1286 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1287 &fbi->map_dma, GFP_KERNEL);
1288
1289 if (fbi->map_cpu) {
1290 /* prevent initial garbage on screen */
1291 memset(fbi->map_cpu, 0, fbi->map_size);
1292 fbi->fb.screen_base = fbi->map_cpu + fbi->video_offset;
1293 fbi->screen_dma = fbi->map_dma + fbi->video_offset;
1294
1295 /*
1296 * FIXME: this is actually the wrong thing to place in
1297 * smem_start. But fbdev suffers from the problem that
1298 * it needs an API which doesn't exist (in this case,
1299 * dma_writecombine_mmap)
1300 */
1301 fbi->fb.fix.smem_start = fbi->screen_dma;
1302 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1303
1304 fbi->dma_buff = (void *) fbi->map_cpu;
1305 fbi->dma_buff_phys = fbi->map_dma;
1306 fbi->palette_cpu = (u16 *) fbi->dma_buff->palette;
1307 1647
1308 pr_debug("pxafb: palette_mem_size = 0x%08x\n", fbi->palette_size*sizeof(u16)); 1648 fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1309 } 1649 if (fbi->video_mem == NULL)
1650 return -ENOMEM;
1310 1651
1311 return fbi->map_cpu ? 0 : -ENOMEM; 1652 fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
1312} 1653 fbi->video_mem_size = size;
1313 1654
1314static void pxafb_decode_mode_info(struct pxafb_info *fbi, 1655 fbi->fb.fix.smem_start = fbi->video_mem_phys;
1315 struct pxafb_mode_info *modes, 1656 fbi->fb.fix.smem_len = fbi->video_mem_size;
1316 unsigned int num_modes) 1657 fbi->fb.screen_base = fbi->video_mem;
1317{
1318 unsigned int i, smemlen;
1319 1658
1320 pxafb_setmode(&fbi->fb.var, &modes[0]); 1659 return fbi->video_mem ? 0 : -ENOMEM;
1321
1322 for (i = 0; i < num_modes; i++) {
1323 smemlen = modes[i].xres * modes[i].yres * modes[i].bpp / 8;
1324 if (smemlen > fbi->fb.fix.smem_len)
1325 fbi->fb.fix.smem_len = smemlen;
1326 }
1327} 1660}
1328 1661
1329static void pxafb_decode_mach_info(struct pxafb_info *fbi, 1662static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1330 struct pxafb_mach_info *inf) 1663 struct pxafb_mach_info *inf)
1331{ 1664{
1332 unsigned int lcd_conn = inf->lcd_conn; 1665 unsigned int lcd_conn = inf->lcd_conn;
1666 struct pxafb_mode_info *m;
1667 int i;
1333 1668
1334 fbi->cmap_inverse = inf->cmap_inverse; 1669 fbi->cmap_inverse = inf->cmap_inverse;
1335 fbi->cmap_static = inf->cmap_static; 1670 fbi->cmap_static = inf->cmap_static;
1671 fbi->lccr4 = inf->lccr4;
1336 1672
1337 switch (lcd_conn & LCD_TYPE_MASK) { 1673 switch (lcd_conn & LCD_TYPE_MASK) {
1338 case LCD_TYPE_MONO_STN: 1674 case LCD_TYPE_MONO_STN:
@@ -1357,7 +1693,6 @@ static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1357 /* fall back to backward compatibility way */ 1693 /* fall back to backward compatibility way */
1358 fbi->lccr0 = inf->lccr0; 1694 fbi->lccr0 = inf->lccr0;
1359 fbi->lccr3 = inf->lccr3; 1695 fbi->lccr3 = inf->lccr3;
1360 fbi->lccr4 = inf->lccr4;
1361 goto decode_mode; 1696 goto decode_mode;
1362 } 1697 }
1363 1698
@@ -1371,7 +1706,22 @@ static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1371 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0; 1706 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1372 1707
1373decode_mode: 1708decode_mode:
1374 pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes); 1709 pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
1710
1711 /* decide video memory size as follows:
1712 * 1. default to mode of maximum resolution
1713 * 2. allow platform to override
1714 * 3. allow module parameter to override
1715 */
1716 for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1717 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1718 m->xres * m->yres * m->bpp / 8);
1719
1720 if (inf->video_mem_size > fbi->video_mem_size)
1721 fbi->video_mem_size = inf->video_mem_size;
1722
1723 if (video_mem_size > fbi->video_mem_size)
1724 fbi->video_mem_size = video_mem_size;
1375} 1725}
1376 1726
1377static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev) 1727static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
@@ -1399,7 +1749,7 @@ static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1399 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS; 1749 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1400 fbi->fb.fix.type_aux = 0; 1750 fbi->fb.fix.type_aux = 0;
1401 fbi->fb.fix.xpanstep = 0; 1751 fbi->fb.fix.xpanstep = 0;
1402 fbi->fb.fix.ypanstep = 0; 1752 fbi->fb.fix.ypanstep = 1;
1403 fbi->fb.fix.ywrapstep = 0; 1753 fbi->fb.fix.ywrapstep = 0;
1404 fbi->fb.fix.accel = FB_ACCEL_NONE; 1754 fbi->fb.fix.accel = FB_ACCEL_NONE;
1405 1755
@@ -1407,7 +1757,7 @@ static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1407 fbi->fb.var.activate = FB_ACTIVATE_NOW; 1757 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1408 fbi->fb.var.height = -1; 1758 fbi->fb.var.height = -1;
1409 fbi->fb.var.width = -1; 1759 fbi->fb.var.width = -1;
1410 fbi->fb.var.accel_flags = 0; 1760 fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
1411 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED; 1761 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1412 1762
1413 fbi->fb.fbops = &pxafb_ops; 1763 fbi->fb.fbops = &pxafb_ops;
@@ -1499,7 +1849,9 @@ static int __devinit parse_opt(struct device *dev, char *this_opt)
1499 1849
1500 s[0] = '\0'; 1850 s[0] = '\0';
1501 1851
1502 if (!strncmp(this_opt, "mode:", 5)) { 1852 if (!strncmp(this_opt, "vmem:", 5)) {
1853 video_mem_size = memparse(this_opt + 5, NULL);
1854 } else if (!strncmp(this_opt, "mode:", 5)) {
1503 return parse_opt_mode(dev, this_opt); 1855 return parse_opt_mode(dev, this_opt);
1504 } else if (!strncmp(this_opt, "pixclock:", 9)) { 1856 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1505 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0); 1857 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
@@ -1736,12 +2088,20 @@ static int __devinit pxafb_probe(struct platform_device *dev)
1736 goto failed_free_res; 2088 goto failed_free_res;
1737 } 2089 }
1738 2090
1739 /* Initialize video memory */ 2091 fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
1740 ret = pxafb_map_video_memory(fbi); 2092 fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
2093 &fbi->dma_buff_phys, GFP_KERNEL);
2094 if (fbi->dma_buff == NULL) {
2095 dev_err(&dev->dev, "failed to allocate memory for DMA\n");
2096 ret = -ENOMEM;
2097 goto failed_free_io;
2098 }
2099
2100 ret = pxafb_init_video_memory(fbi);
1741 if (ret) { 2101 if (ret) {
1742 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret); 2102 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1743 ret = -ENOMEM; 2103 ret = -ENOMEM;
1744 goto failed_free_io; 2104 goto failed_free_dma;
1745 } 2105 }
1746 2106
1747 irq = platform_get_irq(dev, 0); 2107 irq = platform_get_irq(dev, 0);
@@ -1789,6 +2149,8 @@ static int __devinit pxafb_probe(struct platform_device *dev)
1789 goto failed_free_cmap; 2149 goto failed_free_cmap;
1790 } 2150 }
1791 2151
2152 pxafb_overlay_init(fbi);
2153
1792#ifdef CONFIG_CPU_FREQ 2154#ifdef CONFIG_CPU_FREQ
1793 fbi->freq_transition.notifier_call = pxafb_freq_transition; 2155 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1794 fbi->freq_policy.notifier_call = pxafb_freq_policy; 2156 fbi->freq_policy.notifier_call = pxafb_freq_policy;
@@ -1811,8 +2173,10 @@ failed_free_cmap:
1811failed_free_irq: 2173failed_free_irq:
1812 free_irq(irq, fbi); 2174 free_irq(irq, fbi);
1813failed_free_mem: 2175failed_free_mem:
1814 dma_free_writecombine(&dev->dev, fbi->map_size, 2176 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
1815 fbi->map_cpu, fbi->map_dma); 2177failed_free_dma:
2178 dma_free_coherent(&dev->dev, fbi->dma_buff_size,
2179 fbi->dma_buff, fbi->dma_buff_phys);
1816failed_free_io: 2180failed_free_io:
1817 iounmap(fbi->mmio_base); 2181 iounmap(fbi->mmio_base);
1818failed_free_res: 2182failed_free_res:
@@ -1837,6 +2201,7 @@ static int __devexit pxafb_remove(struct platform_device *dev)
1837 2201
1838 info = &fbi->fb; 2202 info = &fbi->fb;
1839 2203
2204 pxafb_overlay_exit(fbi);
1840 unregister_framebuffer(info); 2205 unregister_framebuffer(info);
1841 2206
1842 pxafb_disable_controller(fbi); 2207 pxafb_disable_controller(fbi);
@@ -1847,8 +2212,10 @@ static int __devexit pxafb_remove(struct platform_device *dev)
1847 irq = platform_get_irq(dev, 0); 2212 irq = platform_get_irq(dev, 0);
1848 free_irq(irq, fbi); 2213 free_irq(irq, fbi);
1849 2214
1850 dma_free_writecombine(&dev->dev, fbi->map_size, 2215 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
1851 fbi->map_cpu, fbi->map_dma); 2216
2217 dma_free_writecombine(&dev->dev, fbi->dma_buff_size,
2218 fbi->dma_buff, fbi->dma_buff_phys);
1852 2219
1853 iounmap(fbi->mmio_base); 2220 iounmap(fbi->mmio_base);
1854 2221
diff --git a/drivers/video/pxafb.h b/drivers/video/pxafb.h
index d8eb93fa03a3..2353521c5c8c 100644
--- a/drivers/video/pxafb.h
+++ b/drivers/video/pxafb.h
@@ -54,11 +54,55 @@ enum {
54#define PALETTE_SIZE (256 * 4) 54#define PALETTE_SIZE (256 * 4)
55#define CMD_BUFF_SIZE (1024 * 50) 55#define CMD_BUFF_SIZE (1024 * 50)
56 56
57/* NOTE: the palette and frame dma descriptors are doubled to allow
58 * the 2nd set for branch settings (FBRx)
59 */
57struct pxafb_dma_buff { 60struct pxafb_dma_buff {
58 unsigned char palette[PAL_MAX * PALETTE_SIZE]; 61 unsigned char palette[PAL_MAX * PALETTE_SIZE];
59 uint16_t cmd_buff[CMD_BUFF_SIZE]; 62 uint16_t cmd_buff[CMD_BUFF_SIZE];
60 struct pxafb_dma_descriptor pal_desc[PAL_MAX]; 63 struct pxafb_dma_descriptor pal_desc[PAL_MAX * 2];
61 struct pxafb_dma_descriptor dma_desc[DMA_MAX]; 64 struct pxafb_dma_descriptor dma_desc[DMA_MAX * 2];
65};
66
67enum {
68 OVERLAY1,
69 OVERLAY2,
70};
71
72enum {
73 OVERLAY_FORMAT_RGB = 0,
74 OVERLAY_FORMAT_YUV444_PACKED,
75 OVERLAY_FORMAT_YUV444_PLANAR,
76 OVERLAY_FORMAT_YUV422_PLANAR,
77 OVERLAY_FORMAT_YUV420_PLANAR,
78};
79
80#define NONSTD_TO_XPOS(x) (((x) >> 0) & 0x3ff)
81#define NONSTD_TO_YPOS(x) (((x) >> 10) & 0x3ff)
82#define NONSTD_TO_PFOR(x) (((x) >> 20) & 0x7)
83
84struct pxafb_layer;
85
86struct pxafb_layer_ops {
87 void (*enable)(struct pxafb_layer *);
88 void (*disable)(struct pxafb_layer *);
89 void (*setup)(struct pxafb_layer *);
90};
91
92struct pxafb_layer {
93 struct fb_info fb;
94 int id;
95 atomic_t usage;
96 uint32_t control[2];
97
98 struct pxafb_layer_ops *ops;
99
100 void __iomem *video_mem;
101 unsigned long video_mem_phys;
102 size_t video_mem_size;
103 struct completion branch_done;
104
105 struct pxafb_info *fbi;
62}; 106};
63 107
64struct pxafb_info { 108struct pxafb_info {
@@ -69,24 +113,15 @@ struct pxafb_info {
69 void __iomem *mmio_base; 113 void __iomem *mmio_base;
70 114
71 struct pxafb_dma_buff *dma_buff; 115 struct pxafb_dma_buff *dma_buff;
116 size_t dma_buff_size;
72 dma_addr_t dma_buff_phys; 117 dma_addr_t dma_buff_phys;
73 dma_addr_t fdadr[DMA_MAX]; 118 dma_addr_t fdadr[DMA_MAX * 2];
74 119
75 /* 120 void __iomem *video_mem; /* virtual address of frame buffer */
76 * These are the addresses we mapped 121 unsigned long video_mem_phys; /* physical address of frame buffer */
77 * the framebuffer memory region to. 122 size_t video_mem_size; /* size of the frame buffer */
78 */
79 /* raw memory addresses */
80 dma_addr_t map_dma; /* physical */
81 u_char * map_cpu; /* virtual */
82 u_int map_size;
83
84 /* addresses of pieces placed in raw buffer */
85 u_char * screen_cpu; /* virtual address of frame buffer */
86 dma_addr_t screen_dma; /* physical address of frame buffer */
87 u16 * palette_cpu; /* virtual address of palette memory */ 123 u16 * palette_cpu; /* virtual address of palette memory */
88 u_int palette_size; 124 u_int palette_size;
89 ssize_t video_offset;
90 125
91 u_int lccr0; 126 u_int lccr0;
92 u_int lccr3; 127 u_int lccr3;
@@ -120,6 +155,10 @@ struct pxafb_info {
120 struct task_struct *smart_thread; 155 struct task_struct *smart_thread;
121#endif 156#endif
122 157
158#ifdef CONFIG_FB_PXA_OVERLAY
159 struct pxafb_layer overlay[2];
160#endif
161
123#ifdef CONFIG_CPU_FREQ 162#ifdef CONFIG_CPU_FREQ
124 struct notifier_block freq_transition; 163 struct notifier_block freq_transition;
125 struct notifier_block freq_policy; 164 struct notifier_block freq_policy;
@@ -151,4 +190,10 @@ struct pxafb_info {
151#define MIN_XRES 64 190#define MIN_XRES 64
152#define MIN_YRES 64 191#define MIN_YRES 64
153 192
193/* maximum X and Y resolutions - note these are limits from the register
194 * bits length instead of the real ones
195 */
196#define MAX_XRES 1024
197#define MAX_YRES 1024
198
154#endif /* __PXAFB_H__ */ 199#endif /* __PXAFB_H__ */
diff --git a/drivers/watchdog/sa1100_wdt.c b/drivers/watchdog/sa1100_wdt.c
index d6fbb4657210..e19b45794717 100644
--- a/drivers/watchdog/sa1100_wdt.c
+++ b/drivers/watchdog/sa1100_wdt.c
@@ -36,8 +36,7 @@
36#include <mach/reset.h> 36#include <mach/reset.h>
37#include <mach/hardware.h> 37#include <mach/hardware.h>
38 38
39#define OSCR_FREQ CLOCK_TICK_RATE 39static unsigned long oscr_freq;
40
41static unsigned long sa1100wdt_users; 40static unsigned long sa1100wdt_users;
42static int pre_margin; 41static int pre_margin;
43static int boot_status; 42static int boot_status;
@@ -124,12 +123,12 @@ static long sa1100dog_ioctl(struct file *file, unsigned int cmd,
124 break; 123 break;
125 } 124 }
126 125
127 pre_margin = OSCR_FREQ * time; 126 pre_margin = oscr_freq * time;
128 OSMR3 = OSCR + pre_margin; 127 OSMR3 = OSCR + pre_margin;
129 /*fall through*/ 128 /*fall through*/
130 129
131 case WDIOC_GETTIMEOUT: 130 case WDIOC_GETTIMEOUT:
132 ret = put_user(pre_margin / OSCR_FREQ, p); 131 ret = put_user(pre_margin / oscr_freq, p);
133 break; 132 break;
134 } 133 }
135 return ret; 134 return ret;
@@ -156,6 +155,8 @@ static int __init sa1100dog_init(void)
156{ 155{
157 int ret; 156 int ret;
158 157
158 oscr_freq = get_clock_tick_rate();
159
159 /* 160 /*
160 * Read the reset status, and save it for later. If 161 * Read the reset status, and save it for later. If
161 * we suspend, RCSR will be cleared, and the watchdog 162 * we suspend, RCSR will be cleared, and the watchdog
@@ -163,7 +164,7 @@ static int __init sa1100dog_init(void)
163 */ 164 */
164 boot_status = (reset_status & RESET_STATUS_WATCHDOG) ? 165 boot_status = (reset_status & RESET_STATUS_WATCHDOG) ?
165 WDIOF_CARDRESET : 0; 166 WDIOF_CARDRESET : 0;
166 pre_margin = OSCR_FREQ * margin; 167 pre_margin = oscr_freq * margin;
167 168
168 ret = misc_register(&sa1100dog_miscdev); 169 ret = misc_register(&sa1100dog_miscdev);
169 if (ret == 0) 170 if (ret == 0)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 19:22:28 -0500