1 files changed, 3 insertions, 3 deletions

diff --git a/drivers/ata/pata_bf54x.c b/drivers/ata/pata_bf54x.c
index d66f7733b796..7f87f105c2f6 100644
--- a/drivers/ata/pata_bf54x.c
+++ b/drivers/ata/pata_bf54x.c
@@ -299,7 +299,7 @@ static void bfin_set_piomode(struct ata_port *ap, struct ata_device *adev)
         */
         n6 = num_clocks_min(t6min, fsclk);
         if (mode >= 0 && mode <= 4 && n6 >= 1) {
-                dev_dbg(adev->ap->dev, "set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);
+                dev_dbg(adev->link->ap->dev, "set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);
                 /* calculate the timing values for register transfers. */
                 while (mode > 0 && pio_fsclk[mode] > fsclk)
                         mode--;
@@ -376,7 +376,7 @@ static void bfin_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 
         mode = adev->dma_mode - XFER_UDMA_0;
         if (mode >= 0 && mode <= 5) {
-                dev_dbg(adev->ap->dev, "set udmamode: mode=%d\n", mode);
+                dev_dbg(adev->link->ap->dev, "set udmamode: mode=%d\n", mode);
                 /* the most restrictive timing value is t6 and tc,
                  * the DIOW - data hold. If one SCLK pulse is longer
                  * than this minimum value then register
@@ -433,7 +433,7 @@ static void bfin_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 
         mode = adev->dma_mode - XFER_MW_DMA_0;
         if (mode >= 0 && mode <= 2) {
-                dev_dbg(adev->ap->dev, "set mdmamode: mode=%d\n", mode);
+                dev_dbg(adev->link->ap->dev, "set mdmamode: mode=%d\n", mode);
                 /* the most restrictive timing value is tf, the DMACK to
                  * read data released. If one SCLK pulse is longer than
                  * this maximum value then the MDMA mode