diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/e1000e/defines.h | 2 | ||||
| -rw-r--r-- | drivers/net/e1000e/ich8lan.c | 20 |
2 files changed, 22 insertions, 0 deletions
diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h index e301e26d6897..7f760aa9efe5 100644 --- a/drivers/net/e1000e/defines.h +++ b/drivers/net/e1000e/defines.h | |||
| @@ -214,6 +214,8 @@ | |||
| 214 | #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ | 214 | #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ |
| 215 | #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ | 215 | #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ |
| 216 | #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ | 216 | #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ |
| 217 | #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ | ||
| 218 | #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ | ||
| 217 | #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ | 219 | #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ |
| 218 | #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ | 220 | #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ |
| 219 | #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ | 221 | #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ |
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index 5059c22155d9..0bfef8e16a7b 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c | |||
| @@ -83,6 +83,8 @@ | |||
| 83 | 83 | ||
| 84 | 84 | ||
| 85 | #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ | 85 | #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ |
| 86 | /* FW established a valid mode */ | ||
| 87 | #define E1000_ICH_FWSM_FW_VALID 0x00008000 | ||
| 86 | 88 | ||
| 87 | #define E1000_ICH_MNG_IAMT_MODE 0x2 | 89 | #define E1000_ICH_MNG_IAMT_MODE 0x2 |
| 88 | 90 | ||
| @@ -259,6 +261,7 @@ static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) | |||
| 259 | static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) | 261 | static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) |
| 260 | { | 262 | { |
| 261 | struct e1000_phy_info *phy = &hw->phy; | 263 | struct e1000_phy_info *phy = &hw->phy; |
| 264 | u32 ctrl; | ||
| 262 | s32 ret_val = 0; | 265 | s32 ret_val = 0; |
| 263 | 266 | ||
| 264 | phy->addr = 1; | 267 | phy->addr = 1; |
| @@ -274,6 +277,23 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) | |||
| 274 | phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; | 277 | phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; |
| 275 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | 278 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
| 276 | 279 | ||
| 280 | if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { | ||
| 281 | /* | ||
| 282 | * The MAC-PHY interconnect may still be in SMBus mode | ||
| 283 | * after Sx->S0. Toggle the LANPHYPC Value bit to force | ||
| 284 | * the interconnect to PCIe mode, but only if there is no | ||
| 285 | * firmware present otherwise firmware will have done it. | ||
| 286 | */ | ||
| 287 | ctrl = er32(CTRL); | ||
| 288 | ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; | ||
| 289 | ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; | ||
| 290 | ew32(CTRL, ctrl); | ||
| 291 | udelay(10); | ||
| 292 | ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; | ||
| 293 | ew32(CTRL, ctrl); | ||
| 294 | msleep(50); | ||
| 295 | } | ||
| 296 | |||
| 277 | phy->id = e1000_phy_unknown; | 297 | phy->id = e1000_phy_unknown; |
| 278 | ret_val = e1000e_get_phy_id(hw); | 298 | ret_val = e1000e_get_phy_id(hw); |
| 279 | if (ret_val) | 299 | if (ret_val) |
