diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/dl2k.c | 40 | ||||
| -rw-r--r-- | drivers/net/dl2k.h | 40 |
2 files changed, 22 insertions, 58 deletions
diff --git a/drivers/net/dl2k.c b/drivers/net/dl2k.c index 4468e0f5d16e..2e13eaad1708 100644 --- a/drivers/net/dl2k.c +++ b/drivers/net/dl2k.c | |||
| @@ -1455,8 +1455,8 @@ mii_get_media (struct net_device *dev) | |||
| 1455 | { | 1455 | { |
| 1456 | __u16 negotiate; | 1456 | __u16 negotiate; |
| 1457 | __u16 bmsr; | 1457 | __u16 bmsr; |
| 1458 | MSCR_t mscr; | 1458 | __u16 mscr; |
| 1459 | MSSR_t mssr; | 1459 | __u16 mssr; |
| 1460 | int phy_addr; | 1460 | int phy_addr; |
| 1461 | struct netdev_private *np; | 1461 | struct netdev_private *np; |
| 1462 | 1462 | ||
| @@ -1471,13 +1471,13 @@ mii_get_media (struct net_device *dev) | |||
| 1471 | } | 1471 | } |
| 1472 | negotiate = mii_read (dev, phy_addr, MII_ANAR) & | 1472 | negotiate = mii_read (dev, phy_addr, MII_ANAR) & |
| 1473 | mii_read (dev, phy_addr, MII_ANLPAR); | 1473 | mii_read (dev, phy_addr, MII_ANLPAR); |
| 1474 | mscr.image = mii_read (dev, phy_addr, MII_MSCR); | 1474 | mscr = mii_read (dev, phy_addr, MII_MSCR); |
| 1475 | mssr.image = mii_read (dev, phy_addr, MII_MSSR); | 1475 | mssr = mii_read (dev, phy_addr, MII_MSSR); |
| 1476 | if (mscr.bits.media_1000BT_FD & mssr.bits.lp_1000BT_FD) { | 1476 | if (mscr & MII_MSCR_1000BT_FD && mssr & MII_MSSR_LP_1000BT_FD) { |
| 1477 | np->speed = 1000; | 1477 | np->speed = 1000; |
| 1478 | np->full_duplex = 1; | 1478 | np->full_duplex = 1; |
| 1479 | printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n"); | 1479 | printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n"); |
| 1480 | } else if (mscr.bits.media_1000BT_HD & mssr.bits.lp_1000BT_HD) { | 1480 | } else if (mscr & MII_MSCR_1000BT_HD && mssr & MII_MSSR_LP_1000BT_HD) { |
| 1481 | np->speed = 1000; | 1481 | np->speed = 1000; |
| 1482 | np->full_duplex = 0; | 1482 | np->full_duplex = 0; |
| 1483 | printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n"); | 1483 | printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n"); |
| @@ -1539,7 +1539,7 @@ mii_get_media (struct net_device *dev) | |||
| 1539 | static int | 1539 | static int |
| 1540 | mii_set_media (struct net_device *dev) | 1540 | mii_set_media (struct net_device *dev) |
| 1541 | { | 1541 | { |
| 1542 | PHY_SCR_t pscr; | 1542 | __u16 pscr; |
| 1543 | __u16 bmcr; | 1543 | __u16 bmcr; |
| 1544 | __u16 bmsr; | 1544 | __u16 bmsr; |
| 1545 | __u16 anar; | 1545 | __u16 anar; |
| @@ -1572,9 +1572,9 @@ mii_set_media (struct net_device *dev) | |||
| 1572 | mii_write (dev, phy_addr, MII_ANAR, anar); | 1572 | mii_write (dev, phy_addr, MII_ANAR, anar); |
| 1573 | 1573 | ||
| 1574 | /* Enable Auto crossover */ | 1574 | /* Enable Auto crossover */ |
| 1575 | pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR); | 1575 | pscr = mii_read (dev, phy_addr, MII_PHY_SCR); |
| 1576 | pscr.bits.mdi_crossover_mode = 3; /* 11'b */ | 1576 | pscr |= 3 << 5; /* 11'b */ |
| 1577 | mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image); | 1577 | mii_write (dev, phy_addr, MII_PHY_SCR, pscr); |
| 1578 | 1578 | ||
| 1579 | /* Soft reset PHY */ | 1579 | /* Soft reset PHY */ |
| 1580 | mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET); | 1580 | mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET); |
| @@ -1584,9 +1584,9 @@ mii_set_media (struct net_device *dev) | |||
| 1584 | } else { | 1584 | } else { |
| 1585 | /* Force speed setting */ | 1585 | /* Force speed setting */ |
| 1586 | /* 1) Disable Auto crossover */ | 1586 | /* 1) Disable Auto crossover */ |
| 1587 | pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR); | 1587 | pscr = mii_read (dev, phy_addr, MII_PHY_SCR); |
| 1588 | pscr.bits.mdi_crossover_mode = 0; | 1588 | pscr &= ~(3 << 5); |
| 1589 | mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image); | 1589 | mii_write (dev, phy_addr, MII_PHY_SCR, pscr); |
| 1590 | 1590 | ||
| 1591 | /* 2) PHY Reset */ | 1591 | /* 2) PHY Reset */ |
| 1592 | bmcr = mii_read (dev, phy_addr, MII_BMCR); | 1592 | bmcr = mii_read (dev, phy_addr, MII_BMCR); |
| @@ -1617,9 +1617,9 @@ mii_set_media (struct net_device *dev) | |||
| 1617 | } | 1617 | } |
| 1618 | #if 0 | 1618 | #if 0 |
| 1619 | /* Set 1000BaseT Master/Slave setting */ | 1619 | /* Set 1000BaseT Master/Slave setting */ |
| 1620 | mscr.image = mii_read (dev, phy_addr, MII_MSCR); | 1620 | mscr = mii_read (dev, phy_addr, MII_MSCR); |
| 1621 | mscr.bits.cfg_enable = 1; | 1621 | mscr |= MII_MSCR_CFG_ENABLE; |
| 1622 | mscr.bits.cfg_value = 0; | 1622 | mscr &= ~MII_MSCR_CFG_VALUE = 0; |
| 1623 | #endif | 1623 | #endif |
| 1624 | mii_write (dev, phy_addr, MII_BMCR, bmcr); | 1624 | mii_write (dev, phy_addr, MII_BMCR, bmcr); |
| 1625 | mdelay(10); | 1625 | mdelay(10); |
| @@ -1687,7 +1687,7 @@ static int | |||
| 1687 | mii_set_media_pcs (struct net_device *dev) | 1687 | mii_set_media_pcs (struct net_device *dev) |
| 1688 | { | 1688 | { |
| 1689 | __u16 bmcr; | 1689 | __u16 bmcr; |
| 1690 | ESR_t esr; | 1690 | __u16 esr; |
| 1691 | __u16 anar; | 1691 | __u16 anar; |
| 1692 | int phy_addr; | 1692 | int phy_addr; |
| 1693 | struct netdev_private *np; | 1693 | struct netdev_private *np; |
| @@ -1697,13 +1697,13 @@ mii_set_media_pcs (struct net_device *dev) | |||
| 1697 | /* Auto-Negotiation? */ | 1697 | /* Auto-Negotiation? */ |
| 1698 | if (np->an_enable) { | 1698 | if (np->an_enable) { |
| 1699 | /* Advertise capabilities */ | 1699 | /* Advertise capabilities */ |
| 1700 | esr.image = mii_read (dev, phy_addr, PCS_ESR); | 1700 | esr = mii_read (dev, phy_addr, PCS_ESR); |
| 1701 | anar = mii_read (dev, phy_addr, MII_ANAR) & | 1701 | anar = mii_read (dev, phy_addr, MII_ANAR) & |
| 1702 | ~PCS_ANAR_HALF_DUPLEX & | 1702 | ~PCS_ANAR_HALF_DUPLEX & |
| 1703 | ~PCS_ANAR_FULL_DUPLEX; | 1703 | ~PCS_ANAR_FULL_DUPLEX; |
| 1704 | if (esr.bits.media_1000BT_HD | esr.bits.media_1000BX_HD) | 1704 | if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD)) |
| 1705 | anar |= PCS_ANAR_HALF_DUPLEX; | 1705 | anar |= PCS_ANAR_HALF_DUPLEX; |
| 1706 | if (esr.bits.media_1000BT_FD | esr.bits.media_1000BX_FD) | 1706 | if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD)) |
| 1707 | anar |= PCS_ANAR_FULL_DUPLEX; | 1707 | anar |= PCS_ANAR_FULL_DUPLEX; |
| 1708 | anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC; | 1708 | anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC; |
| 1709 | mii_write (dev, phy_addr, MII_ANAR, anar); | 1709 | mii_write (dev, phy_addr, MII_ANAR, anar); |
diff --git a/drivers/net/dl2k.h b/drivers/net/dl2k.h index c8aacf2ff8da..5f00ecb4a280 100644 --- a/drivers/net/dl2k.h +++ b/drivers/net/dl2k.h | |||
| @@ -385,19 +385,6 @@ enum _mii_aner { | |||
| 385 | }; | 385 | }; |
| 386 | 386 | ||
| 387 | /* MASTER-SLAVE Control Register */ | 387 | /* MASTER-SLAVE Control Register */ |
| 388 | typedef union t_MII_MSCR { | ||
| 389 | u16 image; | ||
| 390 | struct { | ||
| 391 | u16 _bit_7_0:8; // bit 7:0 | ||
| 392 | u16 media_1000BT_HD:1; // bit 8 | ||
| 393 | u16 media_1000BT_FD:1; // bit 9 | ||
| 394 | u16 port_type:1; // bit 10 | ||
| 395 | u16 cfg_value:1; // bit 11 | ||
| 396 | u16 cfg_enable:1; // bit 12 | ||
| 397 | u16 test_mode:3; // bit 15:13 | ||
| 398 | } bits; | ||
| 399 | } MSCR_t, *PMSCR_t; | ||
| 400 | |||
| 401 | enum _mii_mscr { | 388 | enum _mii_mscr { |
| 402 | MII_MSCR_TEST_MODE = 0xe000, | 389 | MII_MSCR_TEST_MODE = 0xe000, |
| 403 | MII_MSCR_CFG_ENABLE = 0x1000, | 390 | MII_MSCR_CFG_ENABLE = 0x1000, |
| @@ -408,20 +395,6 @@ enum _mii_mscr { | |||
| 408 | }; | 395 | }; |
| 409 | 396 | ||
| 410 | /* MASTER-SLAVE Status Register */ | 397 | /* MASTER-SLAVE Status Register */ |
| 411 | typedef union t_MII_MSSR { | ||
| 412 | u16 image; | ||
| 413 | struct { | ||
| 414 | u16 idle_err_count:8; // bit 7:0 | ||
| 415 | u16 _bit_9_8:2; // bit 9:8 | ||
| 416 | u16 lp_1000BT_HD:1; // bit 10 | ||
| 417 | u16 lp_1000BT_FD:1; // bit 11 | ||
| 418 | u16 remote_rcv_status:1; // bit 12 | ||
| 419 | u16 local_rcv_status:1; // bit 13 | ||
| 420 | u16 cfg_resolution:1; // bit 14 | ||
| 421 | u16 cfg_fault:1; // bit 15 | ||
| 422 | } bits; | ||
| 423 | } MSSR_t, *PMSSR_t; | ||
| 424 | |||
| 425 | enum _mii_mssr { | 398 | enum _mii_mssr { |
| 426 | MII_MSSR_CFG_FAULT = 0x8000, | 399 | MII_MSSR_CFG_FAULT = 0x8000, |
| 427 | MII_MSSR_CFG_RES = 0x4000, | 400 | MII_MSSR_CFG_RES = 0x4000, |
| @@ -433,17 +406,6 @@ enum _mii_mssr { | |||
| 433 | }; | 406 | }; |
| 434 | 407 | ||
| 435 | /* IEEE Extened Status Register */ | 408 | /* IEEE Extened Status Register */ |
| 436 | typedef union t_MII_ESR { | ||
| 437 | u16 image; | ||
| 438 | struct { | ||
| 439 | u16 _bit_11_0:12; // bit 11:0 | ||
| 440 | u16 media_1000BT_HD:2; // bit 12 | ||
| 441 | u16 media_1000BT_FD:1; // bit 13 | ||
| 442 | u16 media_1000BX_HD:1; // bit 14 | ||
| 443 | u16 media_1000BX_FD:1; // bit 15 | ||
| 444 | } bits; | ||
| 445 | } ESR_t, *PESR_t; | ||
| 446 | |||
| 447 | enum _mii_esr { | 409 | enum _mii_esr { |
| 448 | MII_ESR_1000BX_FD = 0x8000, | 410 | MII_ESR_1000BX_FD = 0x8000, |
| 449 | MII_ESR_1000BX_HD = 0x4000, | 411 | MII_ESR_1000BX_HD = 0x4000, |
| @@ -451,6 +413,7 @@ enum _mii_esr { | |||
| 451 | MII_ESR_1000BT_HD = 0x1000, | 413 | MII_ESR_1000BT_HD = 0x1000, |
| 452 | }; | 414 | }; |
| 453 | /* PHY Specific Control Register */ | 415 | /* PHY Specific Control Register */ |
| 416 | #if 0 | ||
| 454 | typedef union t_MII_PHY_SCR { | 417 | typedef union t_MII_PHY_SCR { |
| 455 | u16 image; | 418 | u16 image; |
| 456 | struct { | 419 | struct { |
| @@ -468,6 +431,7 @@ typedef union t_MII_PHY_SCR { | |||
| 468 | u16 xmit_fifo_depth:2; // bit 15:14 | 431 | u16 xmit_fifo_depth:2; // bit 15:14 |
| 469 | } bits; | 432 | } bits; |
| 470 | } PHY_SCR_t, *PPHY_SCR_t; | 433 | } PHY_SCR_t, *PPHY_SCR_t; |
| 434 | #endif | ||
| 471 | 435 | ||
| 472 | typedef enum t_MII_ADMIN_STATUS { | 436 | typedef enum t_MII_ADMIN_STATUS { |
| 473 | adm_reset, | 437 | adm_reset, |
