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-rw-r--r--drivers/mtd/nand/Kconfig8
-rw-r--r--drivers/mtd/nand/Makefile1
-rw-r--r--drivers/mtd/nand/excite_nandflash.c248
-rw-r--r--drivers/net/Kconfig2
-rw-r--r--drivers/net/Makefile2
-rw-r--r--drivers/net/octeon/Kconfig10
-rw-r--r--drivers/net/octeon/Makefile2
-rw-r--r--drivers/net/octeon/octeon_mgmt.c1176
-rw-r--r--drivers/net/phy/Kconfig11
-rw-r--r--drivers/net/phy/Makefile1
-rw-r--r--drivers/net/phy/mdio-octeon.c180
-rw-r--r--drivers/rtc/rtc-cmos.c3
-rw-r--r--drivers/staging/octeon/Kconfig3
-rw-r--r--drivers/staging/octeon/ethernet-mdio.c204
-rw-r--r--drivers/staging/octeon/ethernet-mdio.h2
-rw-r--r--drivers/staging/octeon/ethernet-proc.c112
-rw-r--r--drivers/staging/octeon/ethernet-rgmii.c52
-rw-r--r--drivers/staging/octeon/ethernet-sgmii.c2
-rw-r--r--drivers/staging/octeon/ethernet-xaui.c2
-rw-r--r--drivers/staging/octeon/ethernet.c23
-rw-r--r--drivers/staging/octeon/octeon-ethernet.h6
-rw-r--r--drivers/watchdog/Kconfig10
-rw-r--r--drivers/watchdog/Makefile1
-rw-r--r--drivers/watchdog/rm9k_wdt.c419
24 files changed, 1511 insertions, 969 deletions
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 7678538344f4..677cd53f18c3 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -291,14 +291,6 @@ config MTD_NAND_SHARPSL
291 tristate "Support for NAND Flash on Sharp SL Series (C7xx + others)" 291 tristate "Support for NAND Flash on Sharp SL Series (C7xx + others)"
292 depends on ARCH_PXA 292 depends on ARCH_PXA
293 293
294config MTD_NAND_BASLER_EXCITE
295 tristate "Support for NAND Flash on Basler eXcite"
296 depends on BASLER_EXCITE
297 help
298 This enables the driver for the NAND flash device found on the
299 Basler eXcite Smart Camera. If built as a module, the driver
300 will be named excite_nandflash.
301
302config MTD_NAND_CAFE 294config MTD_NAND_CAFE
303 tristate "NAND support for OLPC CAFÉ chip" 295 tristate "NAND support for OLPC CAFÉ chip"
304 depends on PCI 296 depends on PCI
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 460a1f39a8d1..1407bd144015 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -27,7 +27,6 @@ obj-$(CONFIG_MTD_NAND_ATMEL) += atmel_nand.o
27obj-$(CONFIG_MTD_NAND_GPIO) += gpio.o 27obj-$(CONFIG_MTD_NAND_GPIO) += gpio.o
28obj-$(CONFIG_MTD_NAND_OMAP2) += omap2.o 28obj-$(CONFIG_MTD_NAND_OMAP2) += omap2.o
29obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o 29obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o
30obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) += excite_nandflash.o
31obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o 30obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
32obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o 31obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
33obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o 32obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
diff --git a/drivers/mtd/nand/excite_nandflash.c b/drivers/mtd/nand/excite_nandflash.c
deleted file mode 100644
index af6a6a5399e1..000000000000
--- a/drivers/mtd/nand/excite_nandflash.c
+++ /dev/null
@@ -1,248 +0,0 @@
1/*
2* Copyright (C) 2005 - 2007 by Basler Vision Technologies AG
3* Author: Thomas Koeller <thomas.koeller.qbaslerweb.com>
4* Original code by Thies Moeller <thies.moeller@baslerweb.com>
5*
6* This program is free software; you can redistribute it and/or modify
7* it under the terms of the GNU General Public License as published by
8* the Free Software Foundation; either version 2 of the License, or
9* (at your option) any later version.
10*
11* This program is distributed in the hope that it will be useful,
12* but WITHOUT ANY WARRANTY; without even the implied warranty of
13* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14* GNU General Public License for more details.
15*
16* You should have received a copy of the GNU General Public License
17* along with this program; if not, write to the Free Software
18* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19*/
20
21#include <linux/module.h>
22#include <linux/types.h>
23#include <linux/init.h>
24#include <linux/kernel.h>
25#include <linux/string.h>
26#include <linux/ioport.h>
27#include <linux/platform_device.h>
28#include <linux/delay.h>
29#include <linux/err.h>
30
31#include <linux/mtd/mtd.h>
32#include <linux/mtd/nand.h>
33#include <linux/mtd/nand_ecc.h>
34#include <linux/mtd/partitions.h>
35
36#include <asm/io.h>
37#include <asm/rm9k-ocd.h>
38
39#include <excite_nandflash.h>
40
41#define EXCITE_NANDFLASH_VERSION "0.1"
42
43/* I/O register offsets */
44#define EXCITE_NANDFLASH_DATA_BYTE 0x00
45#define EXCITE_NANDFLASH_STATUS_BYTE 0x0c
46#define EXCITE_NANDFLASH_ADDR_BYTE 0x10
47#define EXCITE_NANDFLASH_CMD_BYTE 0x14
48
49/* prefix for debug output */
50static const char module_id[] = "excite_nandflash";
51
52/*
53 * partition definition
54 */
55static const struct mtd_partition partition_info[] = {
56 {
57 .name = "eXcite RootFS",
58 .offset = 0,
59 .size = MTDPART_SIZ_FULL
60 }
61};
62
63static inline const struct resource *
64excite_nand_get_resource(struct platform_device *d, unsigned long flags,
65 const char *basename)
66{
67 char buf[80];
68
69 if (snprintf(buf, sizeof buf, "%s_%u", basename, d->id) >= sizeof buf)
70 return NULL;
71 return platform_get_resource_byname(d, flags, buf);
72}
73
74static inline void __iomem *
75excite_nand_map_regs(struct platform_device *d, const char *basename)
76{
77 void *result = NULL;
78 const struct resource *const r =
79 excite_nand_get_resource(d, IORESOURCE_MEM, basename);
80
81 if (r)
82 result = ioremap_nocache(r->start, r->end + 1 - r->start);
83 return result;
84}
85
86/* controller and mtd information */
87struct excite_nand_drvdata {
88 struct mtd_info board_mtd;
89 struct nand_chip board_chip;
90 void __iomem *regs;
91 void __iomem *tgt;
92};
93
94/* Control function */
95static void excite_nand_control(struct mtd_info *mtd, int cmd,
96 unsigned int ctrl)
97{
98 struct excite_nand_drvdata * const d =
99 container_of(mtd, struct excite_nand_drvdata, board_mtd);
100
101 switch (ctrl) {
102 case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
103 d->tgt = d->regs + EXCITE_NANDFLASH_CMD_BYTE;
104 break;
105 case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
106 d->tgt = d->regs + EXCITE_NANDFLASH_ADDR_BYTE;
107 break;
108 case NAND_CTRL_CHANGE | NAND_NCE:
109 d->tgt = d->regs + EXCITE_NANDFLASH_DATA_BYTE;
110 break;
111 }
112
113 if (cmd != NAND_CMD_NONE)
114 __raw_writeb(cmd, d->tgt);
115}
116
117/* Return 0 if flash is busy, 1 if ready */
118static int excite_nand_devready(struct mtd_info *mtd)
119{
120 struct excite_nand_drvdata * const drvdata =
121 container_of(mtd, struct excite_nand_drvdata, board_mtd);
122
123 return __raw_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS_BYTE);
124}
125
126/*
127 * Called by device layer to remove the driver.
128 * The binding to the mtd and all allocated
129 * resources are released.
130 */
131static int __devexit excite_nand_remove(struct platform_device *dev)
132{
133 struct excite_nand_drvdata * const this = platform_get_drvdata(dev);
134
135 platform_set_drvdata(dev, NULL);
136
137 if (unlikely(!this)) {
138 printk(KERN_ERR "%s: called %s without private data!!",
139 module_id, __func__);
140 return -EINVAL;
141 }
142
143 /* first thing we need to do is release our mtd
144 * then go through freeing the resource used
145 */
146 nand_release(&this->board_mtd);
147
148 /* free the common resources */
149 iounmap(this->regs);
150 kfree(this);
151
152 DEBUG(MTD_DEBUG_LEVEL1, "%s: removed\n", module_id);
153 return 0;
154}
155
156/*
157 * Called by device layer when it finds a device matching
158 * one our driver can handle. This code checks to see if
159 * it can allocate all necessary resources then calls the
160 * nand layer to look for devices.
161*/
162static int __init excite_nand_probe(struct platform_device *pdev)
163{
164 struct excite_nand_drvdata *drvdata; /* private driver data */
165 struct nand_chip *board_chip; /* private flash chip data */
166 struct mtd_info *board_mtd; /* mtd info for this board */
167 int scan_res;
168
169 drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
170 if (unlikely(!drvdata)) {
171 printk(KERN_ERR "%s: no memory for drvdata\n",
172 module_id);
173 return -ENOMEM;
174 }
175
176 /* bind private data into driver */
177 platform_set_drvdata(pdev, drvdata);
178
179 /* allocate and map the resource */
180 drvdata->regs =
181 excite_nand_map_regs(pdev, EXCITE_NANDFLASH_RESOURCE_REGS);
182
183 if (unlikely(!drvdata->regs)) {
184 printk(KERN_ERR "%s: cannot reserve register region\n",
185 module_id);
186 kfree(drvdata);
187 return -ENXIO;
188 }
189
190 drvdata->tgt = drvdata->regs + EXCITE_NANDFLASH_DATA_BYTE;
191
192 /* initialise our chip */
193 board_chip = &drvdata->board_chip;
194 board_chip->IO_ADDR_R = board_chip->IO_ADDR_W =
195 drvdata->regs + EXCITE_NANDFLASH_DATA_BYTE;
196 board_chip->cmd_ctrl = excite_nand_control;
197 board_chip->dev_ready = excite_nand_devready;
198 board_chip->chip_delay = 25;
199 board_chip->ecc.mode = NAND_ECC_SOFT;
200
201 /* link chip to mtd */
202 board_mtd = &drvdata->board_mtd;
203 board_mtd->priv = board_chip;
204
205 DEBUG(MTD_DEBUG_LEVEL2, "%s: device scan\n", module_id);
206 scan_res = nand_scan(&drvdata->board_mtd, 1);
207
208 if (likely(!scan_res)) {
209 DEBUG(MTD_DEBUG_LEVEL2, "%s: register partitions\n", module_id);
210 add_mtd_partitions(&drvdata->board_mtd, partition_info,
211 ARRAY_SIZE(partition_info));
212 } else {
213 iounmap(drvdata->regs);
214 kfree(drvdata);
215 printk(KERN_ERR "%s: device scan failed\n", module_id);
216 return -EIO;
217 }
218 return 0;
219}
220
221static struct platform_driver excite_nand_driver = {
222 .driver = {
223 .name = "excite_nand",
224 .owner = THIS_MODULE,
225 },
226 .probe = excite_nand_probe,
227 .remove = __devexit_p(excite_nand_remove)
228};
229
230static int __init excite_nand_init(void)
231{
232 pr_info("Basler eXcite nand flash driver Version "
233 EXCITE_NANDFLASH_VERSION "\n");
234 return platform_driver_register(&excite_nand_driver);
235}
236
237static void __exit excite_nand_exit(void)
238{
239 platform_driver_unregister(&excite_nand_driver);
240}
241
242module_init(excite_nand_init);
243module_exit(excite_nand_exit);
244
245MODULE_AUTHOR("Thomas Koeller <thomas.koeller@baslerweb.com>");
246MODULE_DESCRIPTION("Basler eXcite NAND-Flash driver");
247MODULE_LICENSE("GPL");
248MODULE_VERSION(EXCITE_NANDFLASH_VERSION)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index a5be9ac6405c..e58a65391ad2 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1953,6 +1953,8 @@ config BCM63XX_ENET
1953 1953
1954source "drivers/net/fs_enet/Kconfig" 1954source "drivers/net/fs_enet/Kconfig"
1955 1955
1956source "drivers/net/octeon/Kconfig"
1957
1956endif # NET_ETHERNET 1958endif # NET_ETHERNET
1957 1959
1958# 1960#
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 246323d7f161..ad1346dd9da9 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -285,3 +285,5 @@ obj-$(CONFIG_VIRTIO_NET) += virtio_net.o
285obj-$(CONFIG_SFC) += sfc/ 285obj-$(CONFIG_SFC) += sfc/
286 286
287obj-$(CONFIG_WIMAX) += wimax/ 287obj-$(CONFIG_WIMAX) += wimax/
288
289obj-$(CONFIG_OCTEON_MGMT_ETHERNET) += octeon/
diff --git a/drivers/net/octeon/Kconfig b/drivers/net/octeon/Kconfig
new file mode 100644
index 000000000000..1e56bbf3f5c0
--- /dev/null
+++ b/drivers/net/octeon/Kconfig
@@ -0,0 +1,10 @@
1config OCTEON_MGMT_ETHERNET
2 tristate "Octeon Management port ethernet driver (CN5XXX, CN6XXX)"
3 depends on CPU_CAVIUM_OCTEON
4 select PHYLIB
5 select MDIO_OCTEON
6 default y
7 help
8 This option enables the ethernet driver for the management
9 port on Cavium Networks' Octeon CN57XX, CN56XX, CN55XX,
10 CN54XX, CN52XX, and CN6XXX chips.
diff --git a/drivers/net/octeon/Makefile b/drivers/net/octeon/Makefile
new file mode 100644
index 000000000000..906edecacfd3
--- /dev/null
+++ b/drivers/net/octeon/Makefile
@@ -0,0 +1,2 @@
1
2obj-$(CONFIG_OCTEON_MGMT_ETHERNET) += octeon_mgmt.o
diff --git a/drivers/net/octeon/octeon_mgmt.c b/drivers/net/octeon/octeon_mgmt.c
new file mode 100644
index 000000000000..050538bf155a
--- /dev/null
+++ b/drivers/net/octeon/octeon_mgmt.c
@@ -0,0 +1,1176 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2009 Cavium Networks
7 */
8
9#include <linux/capability.h>
10#include <linux/dma-mapping.h>
11#include <linux/init.h>
12#include <linux/platform_device.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/if_vlan.h>
16#include <linux/phy.h>
17#include <linux/spinlock.h>
18
19#include <asm/octeon/octeon.h>
20#include <asm/octeon/cvmx-mixx-defs.h>
21#include <asm/octeon/cvmx-agl-defs.h>
22
23#define DRV_NAME "octeon_mgmt"
24#define DRV_VERSION "2.0"
25#define DRV_DESCRIPTION \
26 "Cavium Networks Octeon MII (management) port Network Driver"
27
28#define OCTEON_MGMT_NAPI_WEIGHT 16
29
30/*
31 * Ring sizes that are powers of two allow for more efficient modulo
32 * opertions.
33 */
34#define OCTEON_MGMT_RX_RING_SIZE 512
35#define OCTEON_MGMT_TX_RING_SIZE 128
36
37/* Allow 8 bytes for vlan and FCS. */
38#define OCTEON_MGMT_RX_HEADROOM (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
39
40union mgmt_port_ring_entry {
41 u64 d64;
42 struct {
43 u64 reserved_62_63:2;
44 /* Length of the buffer/packet in bytes */
45 u64 len:14;
46 /* For TX, signals that the packet should be timestamped */
47 u64 tstamp:1;
48 /* The RX error code */
49 u64 code:7;
50#define RING_ENTRY_CODE_DONE 0xf
51#define RING_ENTRY_CODE_MORE 0x10
52 /* Physical address of the buffer */
53 u64 addr:40;
54 } s;
55};
56
57struct octeon_mgmt {
58 struct net_device *netdev;
59 int port;
60 int irq;
61 u64 *tx_ring;
62 dma_addr_t tx_ring_handle;
63 unsigned int tx_next;
64 unsigned int tx_next_clean;
65 unsigned int tx_current_fill;
66 /* The tx_list lock also protects the ring related variables */
67 struct sk_buff_head tx_list;
68
69 /* RX variables only touched in napi_poll. No locking necessary. */
70 u64 *rx_ring;
71 dma_addr_t rx_ring_handle;
72 unsigned int rx_next;
73 unsigned int rx_next_fill;
74 unsigned int rx_current_fill;
75 struct sk_buff_head rx_list;
76
77 spinlock_t lock;
78 unsigned int last_duplex;
79 unsigned int last_link;
80 struct device *dev;
81 struct napi_struct napi;
82 struct tasklet_struct tx_clean_tasklet;
83 struct phy_device *phydev;
84};
85
86static void octeon_mgmt_set_rx_irq(struct octeon_mgmt *p, int enable)
87{
88 int port = p->port;
89 union cvmx_mixx_intena mix_intena;
90 unsigned long flags;
91
92 spin_lock_irqsave(&p->lock, flags);
93 mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port));
94 mix_intena.s.ithena = enable ? 1 : 0;
95 cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64);
96 spin_unlock_irqrestore(&p->lock, flags);
97}
98
99static void octeon_mgmt_set_tx_irq(struct octeon_mgmt *p, int enable)
100{
101 int port = p->port;
102 union cvmx_mixx_intena mix_intena;
103 unsigned long flags;
104
105 spin_lock_irqsave(&p->lock, flags);
106 mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port));
107 mix_intena.s.othena = enable ? 1 : 0;
108 cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64);
109 spin_unlock_irqrestore(&p->lock, flags);
110}
111
112static inline void octeon_mgmt_enable_rx_irq(struct octeon_mgmt *p)
113{
114 octeon_mgmt_set_rx_irq(p, 1);
115}
116
117static inline void octeon_mgmt_disable_rx_irq(struct octeon_mgmt *p)
118{
119 octeon_mgmt_set_rx_irq(p, 0);
120}
121
122static inline void octeon_mgmt_enable_tx_irq(struct octeon_mgmt *p)
123{
124 octeon_mgmt_set_tx_irq(p, 1);
125}
126
127static inline void octeon_mgmt_disable_tx_irq(struct octeon_mgmt *p)
128{
129 octeon_mgmt_set_tx_irq(p, 0);
130}
131
132static unsigned int ring_max_fill(unsigned int ring_size)
133{
134 return ring_size - 8;
135}
136
137static unsigned int ring_size_to_bytes(unsigned int ring_size)
138{
139 return ring_size * sizeof(union mgmt_port_ring_entry);
140}
141
142static void octeon_mgmt_rx_fill_ring(struct net_device *netdev)
143{
144 struct octeon_mgmt *p = netdev_priv(netdev);
145 int port = p->port;
146
147 while (p->rx_current_fill < ring_max_fill(OCTEON_MGMT_RX_RING_SIZE)) {
148 unsigned int size;
149 union mgmt_port_ring_entry re;
150 struct sk_buff *skb;
151
152 /* CN56XX pass 1 needs 8 bytes of padding. */
153 size = netdev->mtu + OCTEON_MGMT_RX_HEADROOM + 8 + NET_IP_ALIGN;
154
155 skb = netdev_alloc_skb(netdev, size);
156 if (!skb)
157 break;
158 skb_reserve(skb, NET_IP_ALIGN);
159 __skb_queue_tail(&p->rx_list, skb);
160
161 re.d64 = 0;
162 re.s.len = size;
163 re.s.addr = dma_map_single(p->dev, skb->data,
164 size,
165 DMA_FROM_DEVICE);
166
167 /* Put it in the ring. */
168 p->rx_ring[p->rx_next_fill] = re.d64;
169 dma_sync_single_for_device(p->dev, p->rx_ring_handle,
170 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
171 DMA_BIDIRECTIONAL);
172 p->rx_next_fill =
173 (p->rx_next_fill + 1) % OCTEON_MGMT_RX_RING_SIZE;
174 p->rx_current_fill++;
175 /* Ring the bell. */
176 cvmx_write_csr(CVMX_MIXX_IRING2(port), 1);
177 }
178}
179
180static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p)
181{
182 int port = p->port;
183 union cvmx_mixx_orcnt mix_orcnt;
184 union mgmt_port_ring_entry re;
185 struct sk_buff *skb;
186 int cleaned = 0;
187 unsigned long flags;
188
189 mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port));
190 while (mix_orcnt.s.orcnt) {
191 dma_sync_single_for_cpu(p->dev, p->tx_ring_handle,
192 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
193 DMA_BIDIRECTIONAL);
194
195 spin_lock_irqsave(&p->tx_list.lock, flags);
196
197 re.d64 = p->tx_ring[p->tx_next_clean];
198 p->tx_next_clean =
199 (p->tx_next_clean + 1) % OCTEON_MGMT_TX_RING_SIZE;
200 skb = __skb_dequeue(&p->tx_list);
201
202 mix_orcnt.u64 = 0;
203 mix_orcnt.s.orcnt = 1;
204
205 /* Acknowledge to hardware that we have the buffer. */
206 cvmx_write_csr(CVMX_MIXX_ORCNT(port), mix_orcnt.u64);
207 p->tx_current_fill--;
208
209 spin_unlock_irqrestore(&p->tx_list.lock, flags);
210
211 dma_unmap_single(p->dev, re.s.addr, re.s.len,
212 DMA_TO_DEVICE);
213 dev_kfree_skb_any(skb);
214 cleaned++;
215
216 mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port));
217 }
218
219 if (cleaned && netif_queue_stopped(p->netdev))
220 netif_wake_queue(p->netdev);
221}
222
223static void octeon_mgmt_clean_tx_tasklet(unsigned long arg)
224{
225 struct octeon_mgmt *p = (struct octeon_mgmt *)arg;
226 octeon_mgmt_clean_tx_buffers(p);
227 octeon_mgmt_enable_tx_irq(p);
228}
229
230static void octeon_mgmt_update_rx_stats(struct net_device *netdev)
231{
232 struct octeon_mgmt *p = netdev_priv(netdev);
233 int port = p->port;
234 unsigned long flags;
235 u64 drop, bad;
236
237 /* These reads also clear the count registers. */
238 drop = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port));
239 bad = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port));
240
241 if (drop || bad) {
242 /* Do an atomic update. */
243 spin_lock_irqsave(&p->lock, flags);
244 netdev->stats.rx_errors += bad;
245 netdev->stats.rx_dropped += drop;
246 spin_unlock_irqrestore(&p->lock, flags);
247 }
248}
249
250static void octeon_mgmt_update_tx_stats(struct net_device *netdev)
251{
252 struct octeon_mgmt *p = netdev_priv(netdev);
253 int port = p->port;
254 unsigned long flags;
255
256 union cvmx_agl_gmx_txx_stat0 s0;
257 union cvmx_agl_gmx_txx_stat1 s1;
258
259 /* These reads also clear the count registers. */
260 s0.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT0(port));
261 s1.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT1(port));
262
263 if (s0.s.xsdef || s0.s.xscol || s1.s.scol || s1.s.mcol) {
264 /* Do an atomic update. */
265 spin_lock_irqsave(&p->lock, flags);
266 netdev->stats.tx_errors += s0.s.xsdef + s0.s.xscol;
267 netdev->stats.collisions += s1.s.scol + s1.s.mcol;
268 spin_unlock_irqrestore(&p->lock, flags);
269 }
270}
271
272/*
273 * Dequeue a receive skb and its corresponding ring entry. The ring
274 * entry is returned, *pskb is updated to point to the skb.
275 */
276static u64 octeon_mgmt_dequeue_rx_buffer(struct octeon_mgmt *p,
277 struct sk_buff **pskb)
278{
279 union mgmt_port_ring_entry re;
280
281 dma_sync_single_for_cpu(p->dev, p->rx_ring_handle,
282 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
283 DMA_BIDIRECTIONAL);
284
285 re.d64 = p->rx_ring[p->rx_next];
286 p->rx_next = (p->rx_next + 1) % OCTEON_MGMT_RX_RING_SIZE;
287 p->rx_current_fill--;
288 *pskb = __skb_dequeue(&p->rx_list);
289
290 dma_unmap_single(p->dev, re.s.addr,
291 ETH_FRAME_LEN + OCTEON_MGMT_RX_HEADROOM,
292 DMA_FROM_DEVICE);
293
294 return re.d64;
295}
296
297
298static int octeon_mgmt_receive_one(struct octeon_mgmt *p)
299{
300 int port = p->port;
301 struct net_device *netdev = p->netdev;
302 union cvmx_mixx_ircnt mix_ircnt;
303 union mgmt_port_ring_entry re;
304 struct sk_buff *skb;
305 struct sk_buff *skb2;
306 struct sk_buff *skb_new;
307 union mgmt_port_ring_entry re2;
308 int rc = 1;
309
310
311 re.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb);
312 if (likely(re.s.code == RING_ENTRY_CODE_DONE)) {
313 /* A good packet, send it up. */
314 skb_put(skb, re.s.len);
315good:
316 skb->protocol = eth_type_trans(skb, netdev);
317 netdev->stats.rx_packets++;
318 netdev->stats.rx_bytes += skb->len;
319 netdev->last_rx = jiffies;
320 netif_receive_skb(skb);
321 rc = 0;
322 } else if (re.s.code == RING_ENTRY_CODE_MORE) {
323 /*
324 * Packet split across skbs. This can happen if we
325 * increase the MTU. Buffers that are already in the
326 * rx ring can then end up being too small. As the rx
327 * ring is refilled, buffers sized for the new MTU
328 * will be used and we should go back to the normal
329 * non-split case.
330 */
331 skb_put(skb, re.s.len);
332 do {
333 re2.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb2);
334 if (re2.s.code != RING_ENTRY_CODE_MORE
335 && re2.s.code != RING_ENTRY_CODE_DONE)
336 goto split_error;
337 skb_put(skb2, re2.s.len);
338 skb_new = skb_copy_expand(skb, 0, skb2->len,
339 GFP_ATOMIC);
340 if (!skb_new)
341 goto split_error;
342 if (skb_copy_bits(skb2, 0, skb_tail_pointer(skb_new),
343 skb2->len))
344 goto split_error;
345 skb_put(skb_new, skb2->len);
346 dev_kfree_skb_any(skb);
347 dev_kfree_skb_any(skb2);
348 skb = skb_new;
349 } while (re2.s.code == RING_ENTRY_CODE_MORE);
350 goto good;
351 } else {
352 /* Some other error, discard it. */
353 dev_kfree_skb_any(skb);
354 /*
355 * Error statistics are accumulated in
356 * octeon_mgmt_update_rx_stats.
357 */
358 }
359 goto done;
360split_error:
361 /* Discard the whole mess. */
362 dev_kfree_skb_any(skb);
363 dev_kfree_skb_any(skb2);
364 while (re2.s.code == RING_ENTRY_CODE_MORE) {
365 re2.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb2);
366 dev_kfree_skb_any(skb2);
367 }
368 netdev->stats.rx_errors++;
369
370done:
371 /* Tell the hardware we processed a packet. */
372 mix_ircnt.u64 = 0;
373 mix_ircnt.s.ircnt = 1;
374 cvmx_write_csr(CVMX_MIXX_IRCNT(port), mix_ircnt.u64);
375 return rc;
376
377}
378
379static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget)
380{
381 int port = p->port;
382 unsigned int work_done = 0;
383 union cvmx_mixx_ircnt mix_ircnt;
384 int rc;
385
386
387 mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port));
388 while (work_done < budget && mix_ircnt.s.ircnt) {
389
390 rc = octeon_mgmt_receive_one(p);
391 if (!rc)
392 work_done++;
393
394 /* Check for more packets. */
395 mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port));
396 }
397
398 octeon_mgmt_rx_fill_ring(p->netdev);
399
400 return work_done;
401}
402
403static int octeon_mgmt_napi_poll(struct napi_struct *napi, int budget)
404{
405 struct octeon_mgmt *p = container_of(napi, struct octeon_mgmt, napi);
406 struct net_device *netdev = p->netdev;
407 unsigned int work_done = 0;
408
409 work_done = octeon_mgmt_receive_packets(p, budget);
410
411 if (work_done < budget) {
412 /* We stopped because no more packets were available. */
413 napi_complete(napi);
414 octeon_mgmt_enable_rx_irq(p);
415 }
416 octeon_mgmt_update_rx_stats(netdev);
417
418 return work_done;
419}
420
421/* Reset the hardware to clean state. */
422static void octeon_mgmt_reset_hw(struct octeon_mgmt *p)
423{
424 union cvmx_mixx_ctl mix_ctl;
425 union cvmx_mixx_bist mix_bist;
426 union cvmx_agl_gmx_bist agl_gmx_bist;
427
428 mix_ctl.u64 = 0;
429 cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64);
430 do {
431 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(p->port));
432 } while (mix_ctl.s.busy);
433 mix_ctl.s.reset = 1;
434 cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64);
435 cvmx_read_csr(CVMX_MIXX_CTL(p->port));
436 cvmx_wait(64);
437
438 mix_bist.u64 = cvmx_read_csr(CVMX_MIXX_BIST(p->port));
439 if (mix_bist.u64)
440 dev_warn(p->dev, "MIX failed BIST (0x%016llx)\n",
441 (unsigned long long)mix_bist.u64);
442
443 agl_gmx_bist.u64 = cvmx_read_csr(CVMX_AGL_GMX_BIST);
444 if (agl_gmx_bist.u64)
445 dev_warn(p->dev, "AGL failed BIST (0x%016llx)\n",
446 (unsigned long long)agl_gmx_bist.u64);
447}
448
449struct octeon_mgmt_cam_state {
450 u64 cam[6];
451 u64 cam_mask;
452 int cam_index;
453};
454
455static void octeon_mgmt_cam_state_add(struct octeon_mgmt_cam_state *cs,
456 unsigned char *addr)
457{
458 int i;
459
460 for (i = 0; i < 6; i++)
461 cs->cam[i] |= (u64)addr[i] << (8 * (cs->cam_index));
462 cs->cam_mask |= (1ULL << cs->cam_index);
463 cs->cam_index++;
464}
465
466static void octeon_mgmt_set_rx_filtering(struct net_device *netdev)
467{
468 struct octeon_mgmt *p = netdev_priv(netdev);
469 int port = p->port;
470 int i;
471 union cvmx_agl_gmx_rxx_adr_ctl adr_ctl;
472 union cvmx_agl_gmx_prtx_cfg agl_gmx_prtx;
473 unsigned long flags;
474 unsigned int prev_packet_enable;
475 unsigned int cam_mode = 1; /* 1 - Accept on CAM match */
476 unsigned int multicast_mode = 1; /* 1 - Reject all multicast. */
477 struct octeon_mgmt_cam_state cam_state;
478 struct dev_addr_list *list;
479 struct list_head *pos;
480 int available_cam_entries;
481
482 memset(&cam_state, 0, sizeof(cam_state));
483
484 if ((netdev->flags & IFF_PROMISC) || netdev->dev_addrs.count > 7) {
485 cam_mode = 0;
486 available_cam_entries = 8;
487 } else {
488 /*
489 * One CAM entry for the primary address, leaves seven
490 * for the secondary addresses.
491 */
492 available_cam_entries = 7 - netdev->dev_addrs.count;
493 }
494
495 if (netdev->flags & IFF_MULTICAST) {
496 if (cam_mode == 0 || (netdev->flags & IFF_ALLMULTI)
497 || netdev->mc_count > available_cam_entries)
498 multicast_mode = 2; /* 1 - Accept all multicast. */
499 else
500 multicast_mode = 0; /* 0 - Use CAM. */
501 }
502
503 if (cam_mode == 1) {
504 /* Add primary address. */
505 octeon_mgmt_cam_state_add(&cam_state, netdev->dev_addr);
506 list_for_each(pos, &netdev->dev_addrs.list) {
507 struct netdev_hw_addr *hw_addr;
508 hw_addr = list_entry(pos, struct netdev_hw_addr, list);
509 octeon_mgmt_cam_state_add(&cam_state, hw_addr->addr);
510 list = list->next;
511 }
512 }
513 if (multicast_mode == 0) {
514 i = netdev->mc_count;
515 list = netdev->mc_list;
516 while (i--) {
517 octeon_mgmt_cam_state_add(&cam_state, list->da_addr);
518 list = list->next;
519 }
520 }
521
522
523 spin_lock_irqsave(&p->lock, flags);
524
525 /* Disable packet I/O. */
526 agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
527 prev_packet_enable = agl_gmx_prtx.s.en;
528 agl_gmx_prtx.s.en = 0;
529 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
530
531
532 adr_ctl.u64 = 0;
533 adr_ctl.s.cam_mode = cam_mode;
534 adr_ctl.s.mcst = multicast_mode;
535 adr_ctl.s.bcst = 1; /* Allow broadcast */
536
537 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port), adr_ctl.u64);
538
539 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM0(port), cam_state.cam[0]);
540 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM1(port), cam_state.cam[1]);
541 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM2(port), cam_state.cam[2]);
542 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM3(port), cam_state.cam[3]);
543 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM4(port), cam_state.cam[4]);
544 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM5(port), cam_state.cam[5]);
545 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), cam_state.cam_mask);
546
547 /* Restore packet I/O. */
548 agl_gmx_prtx.s.en = prev_packet_enable;
549 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
550
551 spin_unlock_irqrestore(&p->lock, flags);
552}
553
554static int octeon_mgmt_set_mac_address(struct net_device *netdev, void *addr)
555{
556 struct sockaddr *sa = addr;
557
558 if (!is_valid_ether_addr(sa->sa_data))
559 return -EADDRNOTAVAIL;
560
561 memcpy(netdev->dev_addr, sa->sa_data, ETH_ALEN);
562
563 octeon_mgmt_set_rx_filtering(netdev);
564
565 return 0;
566}
567
568static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu)
569{
570 struct octeon_mgmt *p = netdev_priv(netdev);
571 int port = p->port;
572 int size_without_fcs = new_mtu + OCTEON_MGMT_RX_HEADROOM;
573
574 /*
575 * Limit the MTU to make sure the ethernet packets are between
576 * 64 bytes and 16383 bytes.
577 */
578 if (size_without_fcs < 64 || size_without_fcs > 16383) {
579 dev_warn(p->dev, "MTU must be between %d and %d.\n",
580 64 - OCTEON_MGMT_RX_HEADROOM,
581 16383 - OCTEON_MGMT_RX_HEADROOM);
582 return -EINVAL;
583 }
584
585 netdev->mtu = new_mtu;
586
587 cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_MAX(port), size_without_fcs);
588 cvmx_write_csr(CVMX_AGL_GMX_RXX_JABBER(port),
589 (size_without_fcs + 7) & 0xfff8);
590
591 return 0;
592}
593
594static irqreturn_t octeon_mgmt_interrupt(int cpl, void *dev_id)
595{
596 struct net_device *netdev = dev_id;
597 struct octeon_mgmt *p = netdev_priv(netdev);
598 int port = p->port;
599 union cvmx_mixx_isr mixx_isr;
600
601 mixx_isr.u64 = cvmx_read_csr(CVMX_MIXX_ISR(port));
602
603 /* Clear any pending interrupts */
604 cvmx_write_csr(CVMX_MIXX_ISR(port),
605 cvmx_read_csr(CVMX_MIXX_ISR(port)));
606 cvmx_read_csr(CVMX_MIXX_ISR(port));
607
608 if (mixx_isr.s.irthresh) {
609 octeon_mgmt_disable_rx_irq(p);
610 napi_schedule(&p->napi);
611 }
612 if (mixx_isr.s.orthresh) {
613 octeon_mgmt_disable_tx_irq(p);
614 tasklet_schedule(&p->tx_clean_tasklet);
615 }
616
617 return IRQ_HANDLED;
618}
619
620static int octeon_mgmt_ioctl(struct net_device *netdev,
621 struct ifreq *rq, int cmd)
622{
623 struct octeon_mgmt *p = netdev_priv(netdev);
624
625 if (!netif_running(netdev))
626 return -EINVAL;
627
628 if (!p->phydev)
629 return -EINVAL;
630
631 return phy_mii_ioctl(p->phydev, if_mii(rq), cmd);
632}
633
634static void octeon_mgmt_adjust_link(struct net_device *netdev)
635{
636 struct octeon_mgmt *p = netdev_priv(netdev);
637 int port = p->port;
638 union cvmx_agl_gmx_prtx_cfg prtx_cfg;
639 unsigned long flags;
640 int link_changed = 0;
641
642 spin_lock_irqsave(&p->lock, flags);
643 if (p->phydev->link) {
644 if (!p->last_link)
645 link_changed = 1;
646 if (p->last_duplex != p->phydev->duplex) {
647 p->last_duplex = p->phydev->duplex;
648 prtx_cfg.u64 =
649 cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
650 prtx_cfg.s.duplex = p->phydev->duplex;
651 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port),
652 prtx_cfg.u64);
653 }
654 } else {
655 if (p->last_link)
656 link_changed = -1;
657 }
658 p->last_link = p->phydev->link;
659 spin_unlock_irqrestore(&p->lock, flags);
660
661 if (link_changed != 0) {
662 if (link_changed > 0) {
663 netif_carrier_on(netdev);
664 pr_info("%s: Link is up - %d/%s\n", netdev->name,
665 p->phydev->speed,
666 DUPLEX_FULL == p->phydev->duplex ?
667 "Full" : "Half");
668 } else {
669 netif_carrier_off(netdev);
670 pr_info("%s: Link is down\n", netdev->name);
671 }
672 }
673}
674
675static int octeon_mgmt_init_phy(struct net_device *netdev)
676{
677 struct octeon_mgmt *p = netdev_priv(netdev);
678 char phy_id[20];
679
680 if (octeon_is_simulation()) {
681 /* No PHYs in the simulator. */
682 netif_carrier_on(netdev);
683 return 0;
684 }
685
686 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "0", p->port);
687
688 p->phydev = phy_connect(netdev, phy_id, octeon_mgmt_adjust_link, 0,
689 PHY_INTERFACE_MODE_MII);
690
691 if (IS_ERR(p->phydev)) {
692 p->phydev = NULL;
693 return -1;
694 }
695
696 phy_start_aneg(p->phydev);
697
698 return 0;
699}
700
701static int octeon_mgmt_open(struct net_device *netdev)
702{
703 struct octeon_mgmt *p = netdev_priv(netdev);
704 int port = p->port;
705 union cvmx_mixx_ctl mix_ctl;
706 union cvmx_agl_gmx_inf_mode agl_gmx_inf_mode;
707 union cvmx_mixx_oring1 oring1;
708 union cvmx_mixx_iring1 iring1;
709 union cvmx_agl_gmx_prtx_cfg prtx_cfg;
710 union cvmx_agl_gmx_rxx_frm_ctl rxx_frm_ctl;
711 union cvmx_mixx_irhwm mix_irhwm;
712 union cvmx_mixx_orhwm mix_orhwm;
713 union cvmx_mixx_intena mix_intena;
714 struct sockaddr sa;
715
716 /* Allocate ring buffers. */
717 p->tx_ring = kzalloc(ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
718 GFP_KERNEL);
719 if (!p->tx_ring)
720 return -ENOMEM;
721 p->tx_ring_handle =
722 dma_map_single(p->dev, p->tx_ring,
723 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
724 DMA_BIDIRECTIONAL);
725 p->tx_next = 0;
726 p->tx_next_clean = 0;
727 p->tx_current_fill = 0;
728
729
730 p->rx_ring = kzalloc(ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
731 GFP_KERNEL);
732 if (!p->rx_ring)
733 goto err_nomem;
734 p->rx_ring_handle =
735 dma_map_single(p->dev, p->rx_ring,
736 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
737 DMA_BIDIRECTIONAL);
738
739 p->rx_next = 0;
740 p->rx_next_fill = 0;
741 p->rx_current_fill = 0;
742
743 octeon_mgmt_reset_hw(p);
744
745 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port));
746
747 /* Bring it out of reset if needed. */
748 if (mix_ctl.s.reset) {
749 mix_ctl.s.reset = 0;
750 cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);
751 do {
752 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port));
753 } while (mix_ctl.s.reset);
754 }
755
756 agl_gmx_inf_mode.u64 = 0;
757 agl_gmx_inf_mode.s.en = 1;
758 cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);
759
760 oring1.u64 = 0;
761 oring1.s.obase = p->tx_ring_handle >> 3;
762 oring1.s.osize = OCTEON_MGMT_TX_RING_SIZE;
763 cvmx_write_csr(CVMX_MIXX_ORING1(port), oring1.u64);
764
765 iring1.u64 = 0;
766 iring1.s.ibase = p->rx_ring_handle >> 3;
767 iring1.s.isize = OCTEON_MGMT_RX_RING_SIZE;
768 cvmx_write_csr(CVMX_MIXX_IRING1(port), iring1.u64);
769
770 /* Disable packet I/O. */
771 prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
772 prtx_cfg.s.en = 0;
773 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64);
774
775 memcpy(sa.sa_data, netdev->dev_addr, ETH_ALEN);
776 octeon_mgmt_set_mac_address(netdev, &sa);
777
778 octeon_mgmt_change_mtu(netdev, netdev->mtu);
779
780 /*
781 * Enable the port HW. Packets are not allowed until
782 * cvmx_mgmt_port_enable() is called.
783 */
784 mix_ctl.u64 = 0;
785 mix_ctl.s.crc_strip = 1; /* Strip the ending CRC */
786 mix_ctl.s.en = 1; /* Enable the port */
787 mix_ctl.s.nbtarb = 0; /* Arbitration mode */
788 /* MII CB-request FIFO programmable high watermark */
789 mix_ctl.s.mrq_hwm = 1;
790 cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);
791
792 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
793 || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
794 /*
795 * Force compensation values, as they are not
796 * determined properly by HW
797 */
798 union cvmx_agl_gmx_drv_ctl drv_ctl;
799
800 drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL);
801 if (port) {
802 drv_ctl.s.byp_en1 = 1;
803 drv_ctl.s.nctl1 = 6;
804 drv_ctl.s.pctl1 = 6;
805 } else {
806 drv_ctl.s.byp_en = 1;
807 drv_ctl.s.nctl = 6;
808 drv_ctl.s.pctl = 6;
809 }
810 cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64);
811 }
812
813 octeon_mgmt_rx_fill_ring(netdev);
814
815 /* Clear statistics. */
816 /* Clear on read. */
817 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_CTL(port), 1);
818 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port), 0);
819 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port), 0);
820
821 cvmx_write_csr(CVMX_AGL_GMX_TXX_STATS_CTL(port), 1);
822 cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT0(port), 0);
823 cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT1(port), 0);
824
825 /* Clear any pending interrupts */
826 cvmx_write_csr(CVMX_MIXX_ISR(port), cvmx_read_csr(CVMX_MIXX_ISR(port)));
827
828 if (request_irq(p->irq, octeon_mgmt_interrupt, 0, netdev->name,
829 netdev)) {
830 dev_err(p->dev, "request_irq(%d) failed.\n", p->irq);
831 goto err_noirq;
832 }
833
834 /* Interrupt every single RX packet */
835 mix_irhwm.u64 = 0;
836 mix_irhwm.s.irhwm = 0;
837 cvmx_write_csr(CVMX_MIXX_IRHWM(port), mix_irhwm.u64);
838
839 /* Interrupt when we have 5 or more packets to clean. */
840 mix_orhwm.u64 = 0;
841 mix_orhwm.s.orhwm = 5;
842 cvmx_write_csr(CVMX_MIXX_ORHWM(port), mix_orhwm.u64);
843
844 /* Enable receive and transmit interrupts */
845 mix_intena.u64 = 0;
846 mix_intena.s.ithena = 1;
847 mix_intena.s.othena = 1;
848 cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64);
849
850
851 /* Enable packet I/O. */
852
853 rxx_frm_ctl.u64 = 0;
854 rxx_frm_ctl.s.pre_align = 1;
855 /*
856 * When set, disables the length check for non-min sized pkts
857 * with padding in the client data.
858 */
859 rxx_frm_ctl.s.pad_len = 1;
860 /* When set, disables the length check for VLAN pkts */
861 rxx_frm_ctl.s.vlan_len = 1;
862 /* When set, PREAMBLE checking is less strict */
863 rxx_frm_ctl.s.pre_free = 1;
864 /* Control Pause Frames can match station SMAC */
865 rxx_frm_ctl.s.ctl_smac = 0;
866 /* Control Pause Frames can match globally assign Multicast address */
867 rxx_frm_ctl.s.ctl_mcst = 1;
868 /* Forward pause information to TX block */
869 rxx_frm_ctl.s.ctl_bck = 1;
870 /* Drop Control Pause Frames */
871 rxx_frm_ctl.s.ctl_drp = 1;
872 /* Strip off the preamble */
873 rxx_frm_ctl.s.pre_strp = 1;
874 /*
875 * This port is configured to send PREAMBLE+SFD to begin every
876 * frame. GMX checks that the PREAMBLE is sent correctly.
877 */
878 rxx_frm_ctl.s.pre_chk = 1;
879 cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_CTL(port), rxx_frm_ctl.u64);
880
881 /* Enable the AGL block */
882 agl_gmx_inf_mode.u64 = 0;
883 agl_gmx_inf_mode.s.en = 1;
884 cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);
885
886 /* Configure the port duplex and enables */
887 prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
888 prtx_cfg.s.tx_en = 1;
889 prtx_cfg.s.rx_en = 1;
890 prtx_cfg.s.en = 1;
891 p->last_duplex = 1;
892 prtx_cfg.s.duplex = p->last_duplex;
893 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64);
894
895 p->last_link = 0;
896 netif_carrier_off(netdev);
897
898 if (octeon_mgmt_init_phy(netdev)) {
899 dev_err(p->dev, "Cannot initialize PHY.\n");
900 goto err_noirq;
901 }
902
903 netif_wake_queue(netdev);
904 napi_enable(&p->napi);
905
906 return 0;
907err_noirq:
908 octeon_mgmt_reset_hw(p);
909 dma_unmap_single(p->dev, p->rx_ring_handle,
910 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
911 DMA_BIDIRECTIONAL);
912 kfree(p->rx_ring);
913err_nomem:
914 dma_unmap_single(p->dev, p->tx_ring_handle,
915 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
916 DMA_BIDIRECTIONAL);
917 kfree(p->tx_ring);
918 return -ENOMEM;
919}
920
921static int octeon_mgmt_stop(struct net_device *netdev)
922{
923 struct octeon_mgmt *p = netdev_priv(netdev);
924
925 napi_disable(&p->napi);
926 netif_stop_queue(netdev);
927
928 if (p->phydev)
929 phy_disconnect(p->phydev);
930
931 netif_carrier_off(netdev);
932
933 octeon_mgmt_reset_hw(p);
934
935
936 free_irq(p->irq, netdev);
937
938 /* dma_unmap is a nop on Octeon, so just free everything. */
939 skb_queue_purge(&p->tx_list);
940 skb_queue_purge(&p->rx_list);
941
942 dma_unmap_single(p->dev, p->rx_ring_handle,
943 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
944 DMA_BIDIRECTIONAL);
945 kfree(p->rx_ring);
946
947 dma_unmap_single(p->dev, p->tx_ring_handle,
948 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
949 DMA_BIDIRECTIONAL);
950 kfree(p->tx_ring);
951
952
953 return 0;
954}
955
956static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev)
957{
958 struct octeon_mgmt *p = netdev_priv(netdev);
959 int port = p->port;
960 union mgmt_port_ring_entry re;
961 unsigned long flags;
962
963 re.d64 = 0;
964 re.s.len = skb->len;
965 re.s.addr = dma_map_single(p->dev, skb->data,
966 skb->len,
967 DMA_TO_DEVICE);
968
969 spin_lock_irqsave(&p->tx_list.lock, flags);
970
971 if (unlikely(p->tx_current_fill >=
972 ring_max_fill(OCTEON_MGMT_TX_RING_SIZE))) {
973 spin_unlock_irqrestore(&p->tx_list.lock, flags);
974
975 dma_unmap_single(p->dev, re.s.addr, re.s.len,
976 DMA_TO_DEVICE);
977
978 netif_stop_queue(netdev);
979 return NETDEV_TX_BUSY;
980 }
981
982 __skb_queue_tail(&p->tx_list, skb);
983
984 /* Put it in the ring. */
985 p->tx_ring[p->tx_next] = re.d64;
986 p->tx_next = (p->tx_next + 1) % OCTEON_MGMT_TX_RING_SIZE;
987 p->tx_current_fill++;
988
989 spin_unlock_irqrestore(&p->tx_list.lock, flags);
990
991 dma_sync_single_for_device(p->dev, p->tx_ring_handle,
992 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
993 DMA_BIDIRECTIONAL);
994
995 netdev->stats.tx_packets++;
996 netdev->stats.tx_bytes += skb->len;
997
998 /* Ring the bell. */
999 cvmx_write_csr(CVMX_MIXX_ORING2(port), 1);
1000
1001 netdev->trans_start = jiffies;
1002 octeon_mgmt_clean_tx_buffers(p);
1003 octeon_mgmt_update_tx_stats(netdev);
1004 return NETDEV_TX_OK;
1005}
1006
1007#ifdef CONFIG_NET_POLL_CONTROLLER
1008static void octeon_mgmt_poll_controller(struct net_device *netdev)
1009{
1010 struct octeon_mgmt *p = netdev_priv(netdev);
1011
1012 octeon_mgmt_receive_packets(p, 16);
1013 octeon_mgmt_update_rx_stats(netdev);
1014 return;
1015}
1016#endif
1017
1018static void octeon_mgmt_get_drvinfo(struct net_device *netdev,
1019 struct ethtool_drvinfo *info)
1020{
1021 strncpy(info->driver, DRV_NAME, sizeof(info->driver));
1022 strncpy(info->version, DRV_VERSION, sizeof(info->version));
1023 strncpy(info->fw_version, "N/A", sizeof(info->fw_version));
1024 strncpy(info->bus_info, "N/A", sizeof(info->bus_info));
1025 info->n_stats = 0;
1026 info->testinfo_len = 0;
1027 info->regdump_len = 0;
1028 info->eedump_len = 0;
1029}
1030
1031static int octeon_mgmt_get_settings(struct net_device *netdev,
1032 struct ethtool_cmd *cmd)
1033{
1034 struct octeon_mgmt *p = netdev_priv(netdev);
1035
1036 if (p->phydev)
1037 return phy_ethtool_gset(p->phydev, cmd);
1038
1039 return -EINVAL;
1040}
1041
1042static int octeon_mgmt_set_settings(struct net_device *netdev,
1043 struct ethtool_cmd *cmd)
1044{
1045 struct octeon_mgmt *p = netdev_priv(netdev);
1046
1047 if (!capable(CAP_NET_ADMIN))
1048 return -EPERM;
1049
1050 if (p->phydev)
1051 return phy_ethtool_sset(p->phydev, cmd);
1052
1053 return -EINVAL;
1054}
1055
1056static const struct ethtool_ops octeon_mgmt_ethtool_ops = {
1057 .get_drvinfo = octeon_mgmt_get_drvinfo,
1058 .get_link = ethtool_op_get_link,
1059 .get_settings = octeon_mgmt_get_settings,
1060 .set_settings = octeon_mgmt_set_settings
1061};
1062
1063static const struct net_device_ops octeon_mgmt_ops = {
1064 .ndo_open = octeon_mgmt_open,
1065 .ndo_stop = octeon_mgmt_stop,
1066 .ndo_start_xmit = octeon_mgmt_xmit,
1067 .ndo_set_rx_mode = octeon_mgmt_set_rx_filtering,
1068 .ndo_set_multicast_list = octeon_mgmt_set_rx_filtering,
1069 .ndo_set_mac_address = octeon_mgmt_set_mac_address,
1070 .ndo_do_ioctl = octeon_mgmt_ioctl,
1071 .ndo_change_mtu = octeon_mgmt_change_mtu,
1072#ifdef CONFIG_NET_POLL_CONTROLLER
1073 .ndo_poll_controller = octeon_mgmt_poll_controller,
1074#endif
1075};
1076
1077static int __init octeon_mgmt_probe(struct platform_device *pdev)
1078{
1079 struct resource *res_irq;
1080 struct net_device *netdev;
1081 struct octeon_mgmt *p;
1082 int i;
1083
1084 netdev = alloc_etherdev(sizeof(struct octeon_mgmt));
1085 if (netdev == NULL)
1086 return -ENOMEM;
1087
1088 dev_set_drvdata(&pdev->dev, netdev);
1089 p = netdev_priv(netdev);
1090 netif_napi_add(netdev, &p->napi, octeon_mgmt_napi_poll,
1091 OCTEON_MGMT_NAPI_WEIGHT);
1092
1093 p->netdev = netdev;
1094 p->dev = &pdev->dev;
1095
1096 p->port = pdev->id;
1097 snprintf(netdev->name, IFNAMSIZ, "mgmt%d", p->port);
1098
1099 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1100 if (!res_irq)
1101 goto err;
1102
1103 p->irq = res_irq->start;
1104 spin_lock_init(&p->lock);
1105
1106 skb_queue_head_init(&p->tx_list);
1107 skb_queue_head_init(&p->rx_list);
1108 tasklet_init(&p->tx_clean_tasklet,
1109 octeon_mgmt_clean_tx_tasklet, (unsigned long)p);
1110
1111 netdev->netdev_ops = &octeon_mgmt_ops;
1112 netdev->ethtool_ops = &octeon_mgmt_ethtool_ops;
1113
1114
1115 /* The mgmt ports get the first N MACs. */
1116 for (i = 0; i < 6; i++)
1117 netdev->dev_addr[i] = octeon_bootinfo->mac_addr_base[i];
1118 netdev->dev_addr[5] += p->port;
1119
1120 if (p->port >= octeon_bootinfo->mac_addr_count)
1121 dev_err(&pdev->dev,
1122 "Error %s: Using MAC outside of the assigned range: "
1123 "%02x:%02x:%02x:%02x:%02x:%02x\n", netdev->name,
1124 netdev->dev_addr[0], netdev->dev_addr[1],
1125 netdev->dev_addr[2], netdev->dev_addr[3],
1126 netdev->dev_addr[4], netdev->dev_addr[5]);
1127
1128 if (register_netdev(netdev))
1129 goto err;
1130
1131 dev_info(&pdev->dev, "Version " DRV_VERSION "\n");
1132 return 0;
1133err:
1134 free_netdev(netdev);
1135 return -ENOENT;
1136}
1137
1138static int __exit octeon_mgmt_remove(struct platform_device *pdev)
1139{
1140 struct net_device *netdev = dev_get_drvdata(&pdev->dev);
1141
1142 unregister_netdev(netdev);
1143 free_netdev(netdev);
1144 return 0;
1145}
1146
1147static struct platform_driver octeon_mgmt_driver = {
1148 .driver = {
1149 .name = "octeon_mgmt",
1150 .owner = THIS_MODULE,
1151 },
1152 .probe = octeon_mgmt_probe,
1153 .remove = __exit_p(octeon_mgmt_remove),
1154};
1155
1156extern void octeon_mdiobus_force_mod_depencency(void);
1157
1158static int __init octeon_mgmt_mod_init(void)
1159{
1160 /* Force our mdiobus driver module to be loaded first. */
1161 octeon_mdiobus_force_mod_depencency();
1162 return platform_driver_register(&octeon_mgmt_driver);
1163}
1164
1165static void __exit octeon_mgmt_mod_exit(void)
1166{
1167 platform_driver_unregister(&octeon_mgmt_driver);
1168}
1169
1170module_init(octeon_mgmt_mod_init);
1171module_exit(octeon_mgmt_mod_exit);
1172
1173MODULE_DESCRIPTION(DRV_DESCRIPTION);
1174MODULE_AUTHOR("David Daney");
1175MODULE_LICENSE("GPL");
1176MODULE_VERSION(DRV_VERSION);
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index d5d8e1c5bc91..fc5938ba3d78 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -115,4 +115,15 @@ config MDIO_GPIO
115 To compile this driver as a module, choose M here: the module 115 To compile this driver as a module, choose M here: the module
116 will be called mdio-gpio. 116 will be called mdio-gpio.
117 117
118config MDIO_OCTEON
119 tristate "Support for MDIO buses on Octeon SOCs"
120 depends on CPU_CAVIUM_OCTEON
121 default y
122 help
123
124 This module provides a driver for the Octeon MDIO busses.
125 It is required by the Octeon Ethernet device drivers.
126
127 If in doubt, say Y.
128
118endif # PHYLIB 129endif # PHYLIB
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index edfaac48cbd5..1342585af381 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
20obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o 20obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
21obj-$(CONFIG_NATIONAL_PHY) += national.o 21obj-$(CONFIG_NATIONAL_PHY) += national.o
22obj-$(CONFIG_STE10XP) += ste10Xp.o 22obj-$(CONFIG_STE10XP) += ste10Xp.o
23obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
diff --git a/drivers/net/phy/mdio-octeon.c b/drivers/net/phy/mdio-octeon.c
new file mode 100644
index 000000000000..61a4461cbda5
--- /dev/null
+++ b/drivers/net/phy/mdio-octeon.c
@@ -0,0 +1,180 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2009 Cavium Networks
7 */
8
9#include <linux/init.h>
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <linux/phy.h>
13
14#include <asm/octeon/octeon.h>
15#include <asm/octeon/cvmx-smix-defs.h>
16
17#define DRV_VERSION "1.0"
18#define DRV_DESCRIPTION "Cavium Networks Octeon SMI/MDIO driver"
19
20struct octeon_mdiobus {
21 struct mii_bus *mii_bus;
22 int unit;
23 int phy_irq[PHY_MAX_ADDR];
24};
25
26static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
27{
28 struct octeon_mdiobus *p = bus->priv;
29 union cvmx_smix_cmd smi_cmd;
30 union cvmx_smix_rd_dat smi_rd;
31 int timeout = 1000;
32
33 smi_cmd.u64 = 0;
34 smi_cmd.s.phy_op = 1; /* MDIO_CLAUSE_22_READ */
35 smi_cmd.s.phy_adr = phy_id;
36 smi_cmd.s.reg_adr = regnum;
37 cvmx_write_csr(CVMX_SMIX_CMD(p->unit), smi_cmd.u64);
38
39 do {
40 /*
41 * Wait 1000 clocks so we don't saturate the RSL bus
42 * doing reads.
43 */
44 cvmx_wait(1000);
45 smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(p->unit));
46 } while (smi_rd.s.pending && --timeout);
47
48 if (smi_rd.s.val)
49 return smi_rd.s.dat;
50 else
51 return -EIO;
52}
53
54static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id,
55 int regnum, u16 val)
56{
57 struct octeon_mdiobus *p = bus->priv;
58 union cvmx_smix_cmd smi_cmd;
59 union cvmx_smix_wr_dat smi_wr;
60 int timeout = 1000;
61
62 smi_wr.u64 = 0;
63 smi_wr.s.dat = val;
64 cvmx_write_csr(CVMX_SMIX_WR_DAT(p->unit), smi_wr.u64);
65
66 smi_cmd.u64 = 0;
67 smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_22_WRITE */
68 smi_cmd.s.phy_adr = phy_id;
69 smi_cmd.s.reg_adr = regnum;
70 cvmx_write_csr(CVMX_SMIX_CMD(p->unit), smi_cmd.u64);
71
72 do {
73 /*
74 * Wait 1000 clocks so we don't saturate the RSL bus
75 * doing reads.
76 */
77 cvmx_wait(1000);
78 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(p->unit));
79 } while (smi_wr.s.pending && --timeout);
80
81 if (timeout <= 0)
82 return -EIO;
83
84 return 0;
85}
86
87static int __init octeon_mdiobus_probe(struct platform_device *pdev)
88{
89 struct octeon_mdiobus *bus;
90 int i;
91 int err = -ENOENT;
92
93 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
94 if (!bus)
95 return -ENOMEM;
96
97 /* The platform_device id is our unit number. */
98 bus->unit = pdev->id;
99
100 bus->mii_bus = mdiobus_alloc();
101
102 if (!bus->mii_bus)
103 goto err;
104
105 /*
106 * Standard Octeon evaluation boards don't support phy
107 * interrupts, we need to poll.
108 */
109 for (i = 0; i < PHY_MAX_ADDR; i++)
110 bus->phy_irq[i] = PHY_POLL;
111
112 bus->mii_bus->priv = bus;
113 bus->mii_bus->irq = bus->phy_irq;
114 bus->mii_bus->name = "mdio-octeon";
115 snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%x", bus->unit);
116 bus->mii_bus->parent = &pdev->dev;
117
118 bus->mii_bus->read = octeon_mdiobus_read;
119 bus->mii_bus->write = octeon_mdiobus_write;
120
121 dev_set_drvdata(&pdev->dev, bus);
122
123 err = mdiobus_register(bus->mii_bus);
124 if (err)
125 goto err_register;
126
127 dev_info(&pdev->dev, "Version " DRV_VERSION "\n");
128
129 return 0;
130err_register:
131 mdiobus_free(bus->mii_bus);
132
133err:
134 devm_kfree(&pdev->dev, bus);
135 return err;
136}
137
138static int __exit octeon_mdiobus_remove(struct platform_device *pdev)
139{
140 struct octeon_mdiobus *bus;
141
142 bus = dev_get_drvdata(&pdev->dev);
143
144 mdiobus_unregister(bus->mii_bus);
145 mdiobus_free(bus->mii_bus);
146 return 0;
147}
148
149static struct platform_driver octeon_mdiobus_driver = {
150 .driver = {
151 .name = "mdio-octeon",
152 .owner = THIS_MODULE,
153 },
154 .probe = octeon_mdiobus_probe,
155 .remove = __exit_p(octeon_mdiobus_remove),
156};
157
158void octeon_mdiobus_force_mod_depencency(void)
159{
160 /* Let ethernet drivers force us to be loaded. */
161}
162EXPORT_SYMBOL(octeon_mdiobus_force_mod_depencency);
163
164static int __init octeon_mdiobus_mod_init(void)
165{
166 return platform_driver_register(&octeon_mdiobus_driver);
167}
168
169static void __exit octeon_mdiobus_mod_exit(void)
170{
171 platform_driver_unregister(&octeon_mdiobus_driver);
172}
173
174module_init(octeon_mdiobus_mod_init);
175module_exit(octeon_mdiobus_mod_exit);
176
177MODULE_DESCRIPTION(DRV_DESCRIPTION);
178MODULE_VERSION(DRV_VERSION);
179MODULE_AUTHOR("David Daney");
180MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c
index eb154dc57164..c8c12325e69b 100644
--- a/drivers/rtc/rtc-cmos.c
+++ b/drivers/rtc/rtc-cmos.c
@@ -686,7 +686,8 @@ cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq)
686 */ 686 */
687#if defined(CONFIG_ATARI) 687#if defined(CONFIG_ATARI)
688 address_space = 64; 688 address_space = 64;
689#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) || defined(__sparc__) 689#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) \
690 || defined(__sparc__) || defined(__mips__)
690 address_space = 128; 691 address_space = 128;
691#else 692#else
692#warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes. 693#warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes.
diff --git a/drivers/staging/octeon/Kconfig b/drivers/staging/octeon/Kconfig
index 536e2382de54..638ad6b35891 100644
--- a/drivers/staging/octeon/Kconfig
+++ b/drivers/staging/octeon/Kconfig
@@ -1,7 +1,8 @@
1config OCTEON_ETHERNET 1config OCTEON_ETHERNET
2 tristate "Cavium Networks Octeon Ethernet support" 2 tristate "Cavium Networks Octeon Ethernet support"
3 depends on CPU_CAVIUM_OCTEON 3 depends on CPU_CAVIUM_OCTEON
4 select MII 4 select PHYLIB
5 select MDIO_OCTEON
5 help 6 help
6 This driver supports the builtin ethernet ports on Cavium 7 This driver supports the builtin ethernet ports on Cavium
7 Networks' products in the Octeon family. This driver supports the 8 Networks' products in the Octeon family. This driver supports the
diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c
index 31a58e508924..05a5cc0f43ed 100644
--- a/drivers/staging/octeon/ethernet-mdio.c
+++ b/drivers/staging/octeon/ethernet-mdio.c
@@ -26,7 +26,8 @@
26**********************************************************************/ 26**********************************************************************/
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/ethtool.h> 28#include <linux/ethtool.h>
29#include <linux/mii.h> 29#include <linux/phy.h>
30
30#include <net/dst.h> 31#include <net/dst.h>
31 32
32#include <asm/octeon/octeon.h> 33#include <asm/octeon/octeon.h>
@@ -34,86 +35,12 @@
34#include "ethernet-defines.h" 35#include "ethernet-defines.h"
35#include "octeon-ethernet.h" 36#include "octeon-ethernet.h"
36#include "ethernet-mdio.h" 37#include "ethernet-mdio.h"
38#include "ethernet-util.h"
37 39
38#include "cvmx-helper-board.h" 40#include "cvmx-helper-board.h"
39 41
40#include "cvmx-smix-defs.h" 42#include "cvmx-smix-defs.h"
41 43
42DECLARE_MUTEX(mdio_sem);
43
44/**
45 * Perform an MII read. Called by the generic MII routines
46 *
47 * @dev: Device to perform read for
48 * @phy_id: The MII phy id
49 * @location: Register location to read
50 * Returns Result from the read or zero on failure
51 */
52static int cvm_oct_mdio_read(struct net_device *dev, int phy_id, int location)
53{
54 union cvmx_smix_cmd smi_cmd;
55 union cvmx_smix_rd_dat smi_rd;
56
57 smi_cmd.u64 = 0;
58 smi_cmd.s.phy_op = 1;
59 smi_cmd.s.phy_adr = phy_id;
60 smi_cmd.s.reg_adr = location;
61 cvmx_write_csr(CVMX_SMIX_CMD(0), smi_cmd.u64);
62
63 do {
64 if (!in_interrupt())
65 yield();
66 smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(0));
67 } while (smi_rd.s.pending);
68
69 if (smi_rd.s.val)
70 return smi_rd.s.dat;
71 else
72 return 0;
73}
74
75static int cvm_oct_mdio_dummy_read(struct net_device *dev, int phy_id,
76 int location)
77{
78 return 0xffff;
79}
80
81/**
82 * Perform an MII write. Called by the generic MII routines
83 *
84 * @dev: Device to perform write for
85 * @phy_id: The MII phy id
86 * @location: Register location to write
87 * @val: Value to write
88 */
89static void cvm_oct_mdio_write(struct net_device *dev, int phy_id, int location,
90 int val)
91{
92 union cvmx_smix_cmd smi_cmd;
93 union cvmx_smix_wr_dat smi_wr;
94
95 smi_wr.u64 = 0;
96 smi_wr.s.dat = val;
97 cvmx_write_csr(CVMX_SMIX_WR_DAT(0), smi_wr.u64);
98
99 smi_cmd.u64 = 0;
100 smi_cmd.s.phy_op = 0;
101 smi_cmd.s.phy_adr = phy_id;
102 smi_cmd.s.reg_adr = location;
103 cvmx_write_csr(CVMX_SMIX_CMD(0), smi_cmd.u64);
104
105 do {
106 if (!in_interrupt())
107 yield();
108 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(0));
109 } while (smi_wr.s.pending);
110}
111
112static void cvm_oct_mdio_dummy_write(struct net_device *dev, int phy_id,
113 int location, int val)
114{
115}
116
117static void cvm_oct_get_drvinfo(struct net_device *dev, 44static void cvm_oct_get_drvinfo(struct net_device *dev,
118 struct ethtool_drvinfo *info) 45 struct ethtool_drvinfo *info)
119{ 46{
@@ -125,49 +52,37 @@ static void cvm_oct_get_drvinfo(struct net_device *dev,
125static int cvm_oct_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 52static int cvm_oct_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
126{ 53{
127 struct octeon_ethernet *priv = netdev_priv(dev); 54 struct octeon_ethernet *priv = netdev_priv(dev);
128 int ret;
129 55
130 down(&mdio_sem); 56 if (priv->phydev)
131 ret = mii_ethtool_gset(&priv->mii_info, cmd); 57 return phy_ethtool_gset(priv->phydev, cmd);
132 up(&mdio_sem);
133 58
134 return ret; 59 return -EINVAL;
135} 60}
136 61
137static int cvm_oct_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 62static int cvm_oct_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
138{ 63{
139 struct octeon_ethernet *priv = netdev_priv(dev); 64 struct octeon_ethernet *priv = netdev_priv(dev);
140 int ret;
141 65
142 down(&mdio_sem); 66 if (!capable(CAP_NET_ADMIN))
143 ret = mii_ethtool_sset(&priv->mii_info, cmd); 67 return -EPERM;
144 up(&mdio_sem); 68
69 if (priv->phydev)
70 return phy_ethtool_sset(priv->phydev, cmd);
145 71
146 return ret; 72 return -EINVAL;
147} 73}
148 74
149static int cvm_oct_nway_reset(struct net_device *dev) 75static int cvm_oct_nway_reset(struct net_device *dev)
150{ 76{
151 struct octeon_ethernet *priv = netdev_priv(dev); 77 struct octeon_ethernet *priv = netdev_priv(dev);
152 int ret;
153 78
154 down(&mdio_sem); 79 if (!capable(CAP_NET_ADMIN))
155 ret = mii_nway_restart(&priv->mii_info); 80 return -EPERM;
156 up(&mdio_sem);
157 81
158 return ret; 82 if (priv->phydev)
159} 83 return phy_start_aneg(priv->phydev);
160 84
161static u32 cvm_oct_get_link(struct net_device *dev) 85 return -EINVAL;
162{
163 struct octeon_ethernet *priv = netdev_priv(dev);
164 u32 ret;
165
166 down(&mdio_sem);
167 ret = mii_link_ok(&priv->mii_info);
168 up(&mdio_sem);
169
170 return ret;
171} 86}
172 87
173const struct ethtool_ops cvm_oct_ethtool_ops = { 88const struct ethtool_ops cvm_oct_ethtool_ops = {
@@ -175,7 +90,7 @@ const struct ethtool_ops cvm_oct_ethtool_ops = {
175 .get_settings = cvm_oct_get_settings, 90 .get_settings = cvm_oct_get_settings,
176 .set_settings = cvm_oct_set_settings, 91 .set_settings = cvm_oct_set_settings,
177 .nway_reset = cvm_oct_nway_reset, 92 .nway_reset = cvm_oct_nway_reset,
178 .get_link = cvm_oct_get_link, 93 .get_link = ethtool_op_get_link,
179 .get_sg = ethtool_op_get_sg, 94 .get_sg = ethtool_op_get_sg,
180 .get_tx_csum = ethtool_op_get_tx_csum, 95 .get_tx_csum = ethtool_op_get_tx_csum,
181}; 96};
@@ -191,41 +106,78 @@ const struct ethtool_ops cvm_oct_ethtool_ops = {
191int cvm_oct_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 106int cvm_oct_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
192{ 107{
193 struct octeon_ethernet *priv = netdev_priv(dev); 108 struct octeon_ethernet *priv = netdev_priv(dev);
194 struct mii_ioctl_data *data = if_mii(rq);
195 unsigned int duplex_chg;
196 int ret;
197 109
198 down(&mdio_sem); 110 if (!netif_running(dev))
199 ret = generic_mii_ioctl(&priv->mii_info, data, cmd, &duplex_chg); 111 return -EINVAL;
200 up(&mdio_sem); 112
113 if (!priv->phydev)
114 return -EINVAL;
115
116 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
117}
201 118
202 return ret; 119static void cvm_oct_adjust_link(struct net_device *dev)
120{
121 struct octeon_ethernet *priv = netdev_priv(dev);
122 cvmx_helper_link_info_t link_info;
123
124 if (priv->last_link != priv->phydev->link) {
125 priv->last_link = priv->phydev->link;
126 link_info.u64 = 0;
127 link_info.s.link_up = priv->last_link ? 1 : 0;
128 link_info.s.full_duplex = priv->phydev->duplex ? 1 : 0;
129 link_info.s.speed = priv->phydev->speed;
130 cvmx_helper_link_set( priv->port, link_info);
131 if (priv->last_link) {
132 netif_carrier_on(dev);
133 if (priv->queue != -1)
134 DEBUGPRINT("%s: %u Mbps %s duplex, "
135 "port %2d, queue %2d\n",
136 dev->name, priv->phydev->speed,
137 priv->phydev->duplex ?
138 "Full" : "Half",
139 priv->port, priv->queue);
140 else
141 DEBUGPRINT("%s: %u Mbps %s duplex, "
142 "port %2d, POW\n",
143 dev->name, priv->phydev->speed,
144 priv->phydev->duplex ?
145 "Full" : "Half",
146 priv->port);
147 } else {
148 netif_carrier_off(dev);
149 DEBUGPRINT("%s: Link down\n", dev->name);
150 }
151 }
203} 152}
204 153
154
205/** 155/**
206 * Setup the MDIO device structures 156 * Setup the PHY
207 * 157 *
208 * @dev: Device to setup 158 * @dev: Device to setup
209 * 159 *
210 * Returns Zero on success, negative on failure 160 * Returns Zero on success, negative on failure
211 */ 161 */
212int cvm_oct_mdio_setup_device(struct net_device *dev) 162int cvm_oct_phy_setup_device(struct net_device *dev)
213{ 163{
214 struct octeon_ethernet *priv = netdev_priv(dev); 164 struct octeon_ethernet *priv = netdev_priv(dev);
215 int phy_id = cvmx_helper_board_get_mii_address(priv->port); 165
216 if (phy_id != -1) { 166 int phy_addr = cvmx_helper_board_get_mii_address(priv->port);
217 priv->mii_info.dev = dev; 167 if (phy_addr != -1) {
218 priv->mii_info.phy_id = phy_id; 168 char phy_id[20];
219 priv->mii_info.phy_id_mask = 0xff; 169
220 priv->mii_info.supports_gmii = 1; 170 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "0", phy_addr);
221 priv->mii_info.reg_num_mask = 0x1f; 171
222 priv->mii_info.mdio_read = cvm_oct_mdio_read; 172 priv->phydev = phy_connect(dev, phy_id, cvm_oct_adjust_link, 0,
223 priv->mii_info.mdio_write = cvm_oct_mdio_write; 173 PHY_INTERFACE_MODE_GMII);
224 } else { 174
225 /* Supply dummy MDIO routines so the kernel won't crash 175 if (IS_ERR(priv->phydev)) {
226 if the user tries to read them */ 176 priv->phydev = NULL;
227 priv->mii_info.mdio_read = cvm_oct_mdio_dummy_read; 177 return -1;
228 priv->mii_info.mdio_write = cvm_oct_mdio_dummy_write; 178 }
179 priv->last_link = 0;
180 phy_start_aneg(priv->phydev);
229 } 181 }
230 return 0; 182 return 0;
231} 183}
diff --git a/drivers/staging/octeon/ethernet-mdio.h b/drivers/staging/octeon/ethernet-mdio.h
index b3328aeec2df..55d0614a7cd9 100644
--- a/drivers/staging/octeon/ethernet-mdio.h
+++ b/drivers/staging/octeon/ethernet-mdio.h
@@ -43,4 +43,4 @@
43 43
44extern const struct ethtool_ops cvm_oct_ethtool_ops; 44extern const struct ethtool_ops cvm_oct_ethtool_ops;
45int cvm_oct_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 45int cvm_oct_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
46int cvm_oct_mdio_setup_device(struct net_device *dev); 46int cvm_oct_phy_setup_device(struct net_device *dev);
diff --git a/drivers/staging/octeon/ethernet-proc.c b/drivers/staging/octeon/ethernet-proc.c
index 8fa88fc419b7..16308d484d3b 100644
--- a/drivers/staging/octeon/ethernet-proc.c
+++ b/drivers/staging/octeon/ethernet-proc.c
@@ -25,7 +25,6 @@
25 * Contact Cavium Networks for more information 25 * Contact Cavium Networks for more information
26**********************************************************************/ 26**********************************************************************/
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/mii.h>
29#include <linux/seq_file.h> 28#include <linux/seq_file.h>
30#include <linux/proc_fs.h> 29#include <linux/proc_fs.h>
31#include <net/dst.h> 30#include <net/dst.h>
@@ -38,112 +37,6 @@
38#include "cvmx-helper.h" 37#include "cvmx-helper.h"
39#include "cvmx-pip.h" 38#include "cvmx-pip.h"
40 39
41static unsigned long long cvm_oct_stats_read_switch(struct net_device *dev,
42 int phy_id, int offset)
43{
44 struct octeon_ethernet *priv = netdev_priv(dev);
45
46 priv->mii_info.mdio_write(dev, phy_id, 0x1d, 0xcc00 | offset);
47 return ((uint64_t) priv->mii_info.
48 mdio_read(dev, phy_id,
49 0x1e) << 16) | (uint64_t) priv->mii_info.
50 mdio_read(dev, phy_id, 0x1f);
51}
52
53static int cvm_oct_stats_switch_show(struct seq_file *m, void *v)
54{
55 static const int ports[] = { 0, 1, 2, 3, 9, -1 };
56 struct net_device *dev = cvm_oct_device[0];
57 int index = 0;
58
59 while (ports[index] != -1) {
60
61 /* Latch port */
62 struct octeon_ethernet *priv = netdev_priv(dev);
63
64 priv->mii_info.mdio_write(dev, 0x1b, 0x1d,
65 0xdc00 | ports[index]);
66 seq_printf(m, "\nSwitch Port %d\n", ports[index]);
67 seq_printf(m, "InGoodOctets: %12llu\t"
68 "OutOctets: %12llu\t"
69 "64 Octets: %12llu\n",
70 cvm_oct_stats_read_switch(dev, 0x1b,
71 0x00) |
72 (cvm_oct_stats_read_switch(dev, 0x1b, 0x01) << 32),
73 cvm_oct_stats_read_switch(dev, 0x1b,
74 0x0E) |
75 (cvm_oct_stats_read_switch(dev, 0x1b, 0x0F) << 32),
76 cvm_oct_stats_read_switch(dev, 0x1b, 0x08));
77
78 seq_printf(m, "InBadOctets: %12llu\t"
79 "OutUnicast: %12llu\t"
80 "65-127 Octets: %12llu\n",
81 cvm_oct_stats_read_switch(dev, 0x1b, 0x02),
82 cvm_oct_stats_read_switch(dev, 0x1b, 0x10),
83 cvm_oct_stats_read_switch(dev, 0x1b, 0x09));
84
85 seq_printf(m, "InUnicast: %12llu\t"
86 "OutBroadcasts: %12llu\t"
87 "128-255 Octets: %12llu\n",
88 cvm_oct_stats_read_switch(dev, 0x1b, 0x04),
89 cvm_oct_stats_read_switch(dev, 0x1b, 0x13),
90 cvm_oct_stats_read_switch(dev, 0x1b, 0x0A));
91
92 seq_printf(m, "InBroadcasts: %12llu\t"
93 "OutMulticasts: %12llu\t"
94 "256-511 Octets: %12llu\n",
95 cvm_oct_stats_read_switch(dev, 0x1b, 0x06),
96 cvm_oct_stats_read_switch(dev, 0x1b, 0x12),
97 cvm_oct_stats_read_switch(dev, 0x1b, 0x0B));
98
99 seq_printf(m, "InMulticasts: %12llu\t"
100 "OutPause: %12llu\t"
101 "512-1023 Octets:%12llu\n",
102 cvm_oct_stats_read_switch(dev, 0x1b, 0x07),
103 cvm_oct_stats_read_switch(dev, 0x1b, 0x15),
104 cvm_oct_stats_read_switch(dev, 0x1b, 0x0C));
105
106 seq_printf(m, "InPause: %12llu\t"
107 "Excessive: %12llu\t"
108 "1024-Max Octets:%12llu\n",
109 cvm_oct_stats_read_switch(dev, 0x1b, 0x16),
110 cvm_oct_stats_read_switch(dev, 0x1b, 0x11),
111 cvm_oct_stats_read_switch(dev, 0x1b, 0x0D));
112
113 seq_printf(m, "InUndersize: %12llu\t"
114 "Collisions: %12llu\n",
115 cvm_oct_stats_read_switch(dev, 0x1b, 0x18),
116 cvm_oct_stats_read_switch(dev, 0x1b, 0x1E));
117
118 seq_printf(m, "InFragments: %12llu\t"
119 "Deferred: %12llu\n",
120 cvm_oct_stats_read_switch(dev, 0x1b, 0x19),
121 cvm_oct_stats_read_switch(dev, 0x1b, 0x05));
122
123 seq_printf(m, "InOversize: %12llu\t"
124 "Single: %12llu\n",
125 cvm_oct_stats_read_switch(dev, 0x1b, 0x1A),
126 cvm_oct_stats_read_switch(dev, 0x1b, 0x14));
127
128 seq_printf(m, "InJabber: %12llu\t"
129 "Multiple: %12llu\n",
130 cvm_oct_stats_read_switch(dev, 0x1b, 0x1B),
131 cvm_oct_stats_read_switch(dev, 0x1b, 0x17));
132
133 seq_printf(m, "In RxErr: %12llu\t"
134 "OutFCSErr: %12llu\n",
135 cvm_oct_stats_read_switch(dev, 0x1b, 0x1C),
136 cvm_oct_stats_read_switch(dev, 0x1b, 0x03));
137
138 seq_printf(m, "InFCSErr: %12llu\t"
139 "Late: %12llu\n",
140 cvm_oct_stats_read_switch(dev, 0x1b, 0x1D),
141 cvm_oct_stats_read_switch(dev, 0x1b, 0x1F));
142 index++;
143 }
144 return 0;
145}
146
147/** 40/**
148 * User is reading /proc/octeon_ethernet_stats 41 * User is reading /proc/octeon_ethernet_stats
149 * 42 *
@@ -215,11 +108,6 @@ static int cvm_oct_stats_show(struct seq_file *m, void *v)
215 } 108 }
216 } 109 }
217 110
218 if (cvm_oct_device[0]) {
219 priv = netdev_priv(cvm_oct_device[0]);
220 if (priv->imode == CVMX_HELPER_INTERFACE_MODE_GMII)
221 cvm_oct_stats_switch_show(m, v);
222 }
223 return 0; 111 return 0;
224} 112}
225 113
diff --git a/drivers/staging/octeon/ethernet-rgmii.c b/drivers/staging/octeon/ethernet-rgmii.c
index fbaa465d2fac..3820f1ec11d1 100644
--- a/drivers/staging/octeon/ethernet-rgmii.c
+++ b/drivers/staging/octeon/ethernet-rgmii.c
@@ -147,32 +147,36 @@ static void cvm_oct_rgmii_poll(struct net_device *dev)
147 cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface), 147 cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface),
148 gmxx_rxx_int_reg.u64); 148 gmxx_rxx_int_reg.u64);
149 } 149 }
150 150 if (priv->phydev == NULL) {
151 link_info = cvmx_helper_link_autoconf(priv->port); 151 link_info = cvmx_helper_link_autoconf(priv->port);
152 priv->link_info = link_info.u64; 152 priv->link_info = link_info.u64;
153 }
153 spin_unlock_irqrestore(&global_register_lock, flags); 154 spin_unlock_irqrestore(&global_register_lock, flags);
154 155
155 /* Tell Linux */ 156 if (priv->phydev == NULL) {
156 if (link_info.s.link_up) { 157 /* Tell core. */
157 158 if (link_info.s.link_up) {
158 if (!netif_carrier_ok(dev)) 159 if (!netif_carrier_ok(dev))
159 netif_carrier_on(dev); 160 netif_carrier_on(dev);
160 if (priv->queue != -1) 161 if (priv->queue != -1)
161 DEBUGPRINT 162 DEBUGPRINT("%s: %u Mbps %s duplex, "
162 ("%s: %u Mbps %s duplex, port %2d, queue %2d\n", 163 "port %2d, queue %2d\n",
163 dev->name, link_info.s.speed, 164 dev->name, link_info.s.speed,
164 (link_info.s.full_duplex) ? "Full" : "Half", 165 (link_info.s.full_duplex) ?
165 priv->port, priv->queue); 166 "Full" : "Half",
166 else 167 priv->port, priv->queue);
167 DEBUGPRINT("%s: %u Mbps %s duplex, port %2d, POW\n", 168 else
168 dev->name, link_info.s.speed, 169 DEBUGPRINT("%s: %u Mbps %s duplex, "
169 (link_info.s.full_duplex) ? "Full" : "Half", 170 "port %2d, POW\n",
170 priv->port); 171 dev->name, link_info.s.speed,
171 } else { 172 (link_info.s.full_duplex) ?
172 173 "Full" : "Half",
173 if (netif_carrier_ok(dev)) 174 priv->port);
174 netif_carrier_off(dev); 175 } else {
175 DEBUGPRINT("%s: Link down\n", dev->name); 176 if (netif_carrier_ok(dev))
177 netif_carrier_off(dev);
178 DEBUGPRINT("%s: Link down\n", dev->name);
179 }
176 } 180 }
177} 181}
178 182
diff --git a/drivers/staging/octeon/ethernet-sgmii.c b/drivers/staging/octeon/ethernet-sgmii.c
index 2b54996bd85d..6061d01eca2d 100644
--- a/drivers/staging/octeon/ethernet-sgmii.c
+++ b/drivers/staging/octeon/ethernet-sgmii.c
@@ -113,7 +113,7 @@ int cvm_oct_sgmii_init(struct net_device *dev)
113 struct octeon_ethernet *priv = netdev_priv(dev); 113 struct octeon_ethernet *priv = netdev_priv(dev);
114 cvm_oct_common_init(dev); 114 cvm_oct_common_init(dev);
115 dev->netdev_ops->ndo_stop(dev); 115 dev->netdev_ops->ndo_stop(dev);
116 if (!octeon_is_simulation()) 116 if (!octeon_is_simulation() && priv->phydev == NULL)
117 priv->poll = cvm_oct_sgmii_poll; 117 priv->poll = cvm_oct_sgmii_poll;
118 118
119 /* FIXME: Need autoneg logic */ 119 /* FIXME: Need autoneg logic */
diff --git a/drivers/staging/octeon/ethernet-xaui.c b/drivers/staging/octeon/ethernet-xaui.c
index 0c2e7cc40f35..ee3dc41b2c53 100644
--- a/drivers/staging/octeon/ethernet-xaui.c
+++ b/drivers/staging/octeon/ethernet-xaui.c
@@ -112,7 +112,7 @@ int cvm_oct_xaui_init(struct net_device *dev)
112 struct octeon_ethernet *priv = netdev_priv(dev); 112 struct octeon_ethernet *priv = netdev_priv(dev);
113 cvm_oct_common_init(dev); 113 cvm_oct_common_init(dev);
114 dev->netdev_ops->ndo_stop(dev); 114 dev->netdev_ops->ndo_stop(dev);
115 if (!octeon_is_simulation()) 115 if (!octeon_is_simulation() && priv->phydev == NULL)
116 priv->poll = cvm_oct_xaui_poll; 116 priv->poll = cvm_oct_xaui_poll;
117 117
118 return 0; 118 return 0;
diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c
index 492c5029992d..4cfd4b136b32 100644
--- a/drivers/staging/octeon/ethernet.c
+++ b/drivers/staging/octeon/ethernet.c
@@ -30,7 +30,7 @@
30#include <linux/netdevice.h> 30#include <linux/netdevice.h>
31#include <linux/etherdevice.h> 31#include <linux/etherdevice.h>
32#include <linux/delay.h> 32#include <linux/delay.h>
33#include <linux/mii.h> 33#include <linux/phy.h>
34 34
35#include <net/dst.h> 35#include <net/dst.h>
36 36
@@ -132,8 +132,6 @@ static struct timer_list cvm_oct_poll_timer;
132 */ 132 */
133struct net_device *cvm_oct_device[TOTAL_NUMBER_OF_PORTS]; 133struct net_device *cvm_oct_device[TOTAL_NUMBER_OF_PORTS];
134 134
135extern struct semaphore mdio_sem;
136
137/** 135/**
138 * Periodic timer tick for slow management operations 136 * Periodic timer tick for slow management operations
139 * 137 *
@@ -160,13 +158,8 @@ static void cvm_do_timer(unsigned long arg)
160 goto out; 158 goto out;
161 159
162 priv = netdev_priv(cvm_oct_device[port]); 160 priv = netdev_priv(cvm_oct_device[port]);
163 if (priv->poll) { 161 if (priv->poll)
164 /* skip polling if we don't get the lock */ 162 priv->poll(cvm_oct_device[port]);
165 if (!down_trylock(&mdio_sem)) {
166 priv->poll(cvm_oct_device[port]);
167 up(&mdio_sem);
168 }
169 }
170 163
171 queues_per_port = cvmx_pko_get_num_queues(port); 164 queues_per_port = cvmx_pko_get_num_queues(port);
172 /* Drain any pending packets in the free list */ 165 /* Drain any pending packets in the free list */
@@ -524,7 +517,7 @@ int cvm_oct_common_init(struct net_device *dev)
524 dev->features |= NETIF_F_LLTX; 517 dev->features |= NETIF_F_LLTX;
525 SET_ETHTOOL_OPS(dev, &cvm_oct_ethtool_ops); 518 SET_ETHTOOL_OPS(dev, &cvm_oct_ethtool_ops);
526 519
527 cvm_oct_mdio_setup_device(dev); 520 cvm_oct_phy_setup_device(dev);
528 dev->netdev_ops->ndo_set_mac_address(dev, &sa); 521 dev->netdev_ops->ndo_set_mac_address(dev, &sa);
529 dev->netdev_ops->ndo_change_mtu(dev, dev->mtu); 522 dev->netdev_ops->ndo_change_mtu(dev, dev->mtu);
530 523
@@ -540,7 +533,10 @@ int cvm_oct_common_init(struct net_device *dev)
540 533
541void cvm_oct_common_uninit(struct net_device *dev) 534void cvm_oct_common_uninit(struct net_device *dev)
542{ 535{
543 /* Currently nothing to do */ 536 struct octeon_ethernet *priv = netdev_priv(dev);
537
538 if (priv->phydev)
539 phy_disconnect(priv->phydev);
544} 540}
545 541
546static const struct net_device_ops cvm_oct_npi_netdev_ops = { 542static const struct net_device_ops cvm_oct_npi_netdev_ops = {
@@ -627,6 +623,8 @@ static const struct net_device_ops cvm_oct_pow_netdev_ops = {
627#endif 623#endif
628}; 624};
629 625
626extern void octeon_mdiobus_force_mod_depencency(void);
627
630/** 628/**
631 * Module/ driver initialization. Creates the linux network 629 * Module/ driver initialization. Creates the linux network
632 * devices. 630 * devices.
@@ -640,6 +638,7 @@ static int __init cvm_oct_init_module(void)
640 int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE; 638 int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE;
641 int qos; 639 int qos;
642 640
641 octeon_mdiobus_force_mod_depencency();
643 pr_notice("cavium-ethernet %s\n", OCTEON_ETHERNET_VERSION); 642 pr_notice("cavium-ethernet %s\n", OCTEON_ETHERNET_VERSION);
644 643
645 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) 644 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
diff --git a/drivers/staging/octeon/octeon-ethernet.h b/drivers/staging/octeon/octeon-ethernet.h
index 3aef9878fc0a..402a15b9bb0e 100644
--- a/drivers/staging/octeon/octeon-ethernet.h
+++ b/drivers/staging/octeon/octeon-ethernet.h
@@ -50,9 +50,9 @@ struct octeon_ethernet {
50 /* List of outstanding tx buffers per queue */ 50 /* List of outstanding tx buffers per queue */
51 struct sk_buff_head tx_free_list[16]; 51 struct sk_buff_head tx_free_list[16];
52 /* Device statistics */ 52 /* Device statistics */
53 struct net_device_stats stats 53 struct net_device_stats stats;
54; /* Generic MII info structure */ 54 struct phy_device *phydev;
55 struct mii_if_info mii_info; 55 unsigned int last_link;
56 /* Last negotiated link state */ 56 /* Last negotiated link state */
57 uint64_t link_info; 57 uint64_t link_info;
58 /* Called periodically to check link status */ 58 /* Called periodically to check link status */
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index d958b76430a2..da84fd03850f 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -815,16 +815,6 @@ config PNX833X_WDT
815 timer has expired and no process has written to /dev/watchdog during 815 timer has expired and no process has written to /dev/watchdog during
816 that time. 816 that time.
817 817
818config WDT_RM9K_GPI
819 tristate "RM9000/GPI hardware watchdog"
820 depends on CPU_RM9000
821 help
822 Watchdog implementation using the GPI hardware found on
823 PMC-Sierra RM9xxx CPUs.
824
825 To compile this driver as a module, choose M here: the
826 module will be called rm9k_wdt.
827
828config SIBYTE_WDOG 818config SIBYTE_WDOG
829 tristate "Sibyte SoC hardware watchdog" 819 tristate "Sibyte SoC hardware watchdog"
830 depends on CPU_SB1 820 depends on CPU_SB1
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 89c045dc468e..475c61100069 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -109,7 +109,6 @@ obj-$(CONFIG_RC32434_WDT) += rc32434_wdt.o
109obj-$(CONFIG_INDYDOG) += indydog.o 109obj-$(CONFIG_INDYDOG) += indydog.o
110obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o 110obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o
111obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o 111obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o
112obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o
113obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o 112obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
114obj-$(CONFIG_AR7_WDT) += ar7_wdt.o 113obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
115obj-$(CONFIG_TXX9_WDT) += txx9wdt.o 114obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
diff --git a/drivers/watchdog/rm9k_wdt.c b/drivers/watchdog/rm9k_wdt.c
deleted file mode 100644
index bb66958b9433..000000000000
--- a/drivers/watchdog/rm9k_wdt.c
+++ /dev/null
@@ -1,419 +0,0 @@
1/*
2 * Watchdog implementation for GPI h/w found on PMC-Sierra RM9xxx
3 * chips.
4 *
5 * Copyright (C) 2004 by Basler Vision Technologies AG
6 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/platform_device.h>
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/interrupt.h>
27#include <linux/fs.h>
28#include <linux/reboot.h>
29#include <linux/notifier.h>
30#include <linux/miscdevice.h>
31#include <linux/watchdog.h>
32#include <linux/io.h>
33#include <linux/uaccess.h>
34#include <asm/atomic.h>
35#include <asm/processor.h>
36#include <asm/system.h>
37#include <asm/rm9k-ocd.h>
38
39#include <rm9k_wdt.h>
40
41
42#define CLOCK 125000000
43#define MAX_TIMEOUT_SECONDS 32
44#define CPCCR 0x0080
45#define CPGIG1SR 0x0044
46#define CPGIG1ER 0x0054
47
48
49/* Function prototypes */
50static irqreturn_t wdt_gpi_irqhdl(int, void *);
51static void wdt_gpi_start(void);
52static void wdt_gpi_stop(void);
53static void wdt_gpi_set_timeout(unsigned int);
54static int wdt_gpi_open(struct inode *, struct file *);
55static int wdt_gpi_release(struct inode *, struct file *);
56static ssize_t wdt_gpi_write(struct file *, const char __user *, size_t,
57 loff_t *);
58static long wdt_gpi_ioctl(struct file *, unsigned int, unsigned long);
59static int wdt_gpi_notify(struct notifier_block *, unsigned long, void *);
60static const struct resource *wdt_gpi_get_resource(struct platform_device *,
61 const char *, unsigned int);
62static int __init wdt_gpi_probe(struct platform_device *);
63static int __exit wdt_gpi_remove(struct platform_device *);
64
65
66static const char wdt_gpi_name[] = "wdt_gpi";
67static atomic_t opencnt;
68static int expect_close;
69static int locked;
70
71
72/* These are set from device resources */
73static void __iomem *wd_regs;
74static unsigned int wd_irq, wd_ctr;
75
76
77/* Module arguments */
78static int timeout = MAX_TIMEOUT_SECONDS;
79module_param(timeout, int, 0444);
80MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");
81
82static unsigned long resetaddr = 0xbffdc200;
83module_param(resetaddr, ulong, 0444);
84MODULE_PARM_DESC(resetaddr, "Address to write to to force a reset");
85
86static unsigned long flagaddr = 0xbffdc104;
87module_param(flagaddr, ulong, 0444);
88MODULE_PARM_DESC(flagaddr, "Address to write to boot flags to");
89
90static int powercycle;
91module_param(powercycle, bool, 0444);
92MODULE_PARM_DESC(powercycle, "Cycle power if watchdog expires");
93
94static int nowayout = WATCHDOG_NOWAYOUT;
95module_param(nowayout, bool, 0444);
96MODULE_PARM_DESC(nowayout, "Watchdog cannot be disabled once started");
97
98
99/* Kernel interfaces */
100static const struct file_operations fops = {
101 .owner = THIS_MODULE,
102 .open = wdt_gpi_open,
103 .release = wdt_gpi_release,
104 .write = wdt_gpi_write,
105 .unlocked_ioctl = wdt_gpi_ioctl,
106};
107
108static struct miscdevice miscdev = {
109 .minor = WATCHDOG_MINOR,
110 .name = wdt_gpi_name,
111 .fops = &fops,
112};
113
114static struct notifier_block wdt_gpi_shutdown = {
115 .notifier_call = wdt_gpi_notify,
116};
117
118
119/* Interrupt handler */
120static irqreturn_t wdt_gpi_irqhdl(int irq, void *ctxt)
121{
122 if (!unlikely(__raw_readl(wd_regs + 0x0008) & 0x1))
123 return IRQ_NONE;
124 __raw_writel(0x1, wd_regs + 0x0008);
125
126
127 printk(KERN_CRIT "%s: watchdog expired - resetting system\n",
128 wdt_gpi_name);
129
130 *(volatile char *) flagaddr |= 0x01;
131 *(volatile char *) resetaddr = powercycle ? 0x01 : 0x2;
132 iob();
133 while (1)
134 cpu_relax();
135}
136
137
138/* Watchdog functions */
139static void wdt_gpi_start(void)
140{
141 u32 reg;
142
143 lock_titan_regs();
144 reg = titan_readl(CPGIG1ER);
145 titan_writel(reg | (0x100 << wd_ctr), CPGIG1ER);
146 iob();
147 unlock_titan_regs();
148}
149
150static void wdt_gpi_stop(void)
151{
152 u32 reg;
153
154 lock_titan_regs();
155 reg = titan_readl(CPCCR) & ~(0xf << (wd_ctr * 4));
156 titan_writel(reg, CPCCR);
157 reg = titan_readl(CPGIG1ER);
158 titan_writel(reg & ~(0x100 << wd_ctr), CPGIG1ER);
159 iob();
160 unlock_titan_regs();
161}
162
163static void wdt_gpi_set_timeout(unsigned int to)
164{
165 u32 reg;
166 const u32 wdval = (to * CLOCK) & ~0x0000000f;
167
168 lock_titan_regs();
169 reg = titan_readl(CPCCR) & ~(0xf << (wd_ctr * 4));
170 titan_writel(reg, CPCCR);
171 wmb();
172 __raw_writel(wdval, wd_regs + 0x0000);
173 wmb();
174 titan_writel(reg | (0x2 << (wd_ctr * 4)), CPCCR);
175 wmb();
176 titan_writel(reg | (0x5 << (wd_ctr * 4)), CPCCR);
177 iob();
178 unlock_titan_regs();
179}
180
181
182/* /dev/watchdog operations */
183static int wdt_gpi_open(struct inode *inode, struct file *file)
184{
185 int res;
186
187 if (unlikely(atomic_dec_if_positive(&opencnt) < 0))
188 return -EBUSY;
189
190 expect_close = 0;
191 if (locked) {
192 module_put(THIS_MODULE);
193 free_irq(wd_irq, &miscdev);
194 locked = 0;
195 }
196
197 res = request_irq(wd_irq, wdt_gpi_irqhdl, IRQF_SHARED | IRQF_DISABLED,
198 wdt_gpi_name, &miscdev);
199 if (unlikely(res))
200 return res;
201
202 wdt_gpi_set_timeout(timeout);
203 wdt_gpi_start();
204
205 printk(KERN_INFO "%s: watchdog started, timeout = %u seconds\n",
206 wdt_gpi_name, timeout);
207 return nonseekable_open(inode, file);
208}
209
210static int wdt_gpi_release(struct inode *inode, struct file *file)
211{
212 if (nowayout) {
213 printk(KERN_INFO "%s: no way out - watchdog left running\n",
214 wdt_gpi_name);
215 __module_get(THIS_MODULE);
216 locked = 1;
217 } else {
218 if (expect_close) {
219 wdt_gpi_stop();
220 free_irq(wd_irq, &miscdev);
221 printk(KERN_INFO "%s: watchdog stopped\n",
222 wdt_gpi_name);
223 } else {
224 printk(KERN_CRIT "%s: unexpected close() -"
225 " watchdog left running\n",
226 wdt_gpi_name);
227 wdt_gpi_set_timeout(timeout);
228 __module_get(THIS_MODULE);
229 locked = 1;
230 }
231 }
232
233 atomic_inc(&opencnt);
234 return 0;
235}
236
237static ssize_t wdt_gpi_write(struct file *f, const char __user *d, size_t s,
238 loff_t *o)
239{
240 char val;
241
242 wdt_gpi_set_timeout(timeout);
243 expect_close = (s > 0) && !get_user(val, d) && (val == 'V');
244 return s ? 1 : 0;
245}
246
247static long wdt_gpi_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
248{
249 long res = -ENOTTY;
250 const long size = _IOC_SIZE(cmd);
251 int stat;
252 void __user *argp = (void __user *)arg;
253 static struct watchdog_info wdinfo = {
254 .identity = "RM9xxx/GPI watchdog",
255 .firmware_version = 0,
256 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING
257 };
258
259 if (unlikely(_IOC_TYPE(cmd) != WATCHDOG_IOCTL_BASE))
260 return -ENOTTY;
261
262 if ((_IOC_DIR(cmd) & _IOC_READ)
263 && !access_ok(VERIFY_WRITE, arg, size))
264 return -EFAULT;
265
266 if ((_IOC_DIR(cmd) & _IOC_WRITE)
267 && !access_ok(VERIFY_READ, arg, size))
268 return -EFAULT;
269
270 expect_close = 0;
271
272 switch (cmd) {
273 case WDIOC_GETSUPPORT:
274 wdinfo.options = nowayout ?
275 WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING :
276 WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
277 WDIOF_MAGICCLOSE;
278 res = __copy_to_user(argp, &wdinfo, size) ? -EFAULT : size;
279 break;
280
281 case WDIOC_GETSTATUS:
282 break;
283
284 case WDIOC_GETBOOTSTATUS:
285 stat = (*(volatile char *) flagaddr & 0x01)
286 ? WDIOF_CARDRESET : 0;
287 res = __copy_to_user(argp, &stat, size) ?
288 -EFAULT : size;
289 break;
290
291 case WDIOC_SETOPTIONS:
292 break;
293
294 case WDIOC_KEEPALIVE:
295 wdt_gpi_set_timeout(timeout);
296 res = size;
297 break;
298
299 case WDIOC_SETTIMEOUT:
300 {
301 int val;
302 if (unlikely(__copy_from_user(&val, argp, size))) {
303 res = -EFAULT;
304 break;
305 }
306
307 if (val > MAX_TIMEOUT_SECONDS)
308 val = MAX_TIMEOUT_SECONDS;
309 timeout = val;
310 wdt_gpi_set_timeout(val);
311 res = size;
312 printk(KERN_INFO "%s: timeout set to %u seconds\n",
313 wdt_gpi_name, timeout);
314 }
315 break;
316
317 case WDIOC_GETTIMEOUT:
318 res = __copy_to_user(argp, &timeout, size) ?
319 -EFAULT : size;
320 break;
321 }
322
323 return res;
324}
325
326
327/* Shutdown notifier */
328static int wdt_gpi_notify(struct notifier_block *this, unsigned long code,
329 void *unused)
330{
331 if (code == SYS_DOWN || code == SYS_HALT)
332 wdt_gpi_stop();
333
334 return NOTIFY_DONE;
335}
336
337
338/* Init & exit procedures */
339static const struct resource *wdt_gpi_get_resource(struct platform_device *pdv,
340 const char *name, unsigned int type)
341{
342 char buf[80];
343 if (snprintf(buf, sizeof(buf), "%s_0", name) >= sizeof(buf))
344 return NULL;
345 return platform_get_resource_byname(pdv, type, buf);
346}
347
348/* No hotplugging on the platform bus - use __devinit */
349static int __devinit wdt_gpi_probe(struct platform_device *pdv)
350{
351 int res;
352 const struct resource
353 * const rr = wdt_gpi_get_resource(pdv, WDT_RESOURCE_REGS,
354 IORESOURCE_MEM),
355 * const ri = wdt_gpi_get_resource(pdv, WDT_RESOURCE_IRQ,
356 IORESOURCE_IRQ),
357 * const rc = wdt_gpi_get_resource(pdv, WDT_RESOURCE_COUNTER,
358 0);
359
360 if (unlikely(!rr || !ri || !rc))
361 return -ENXIO;
362
363 wd_regs = ioremap_nocache(rr->start, rr->end + 1 - rr->start);
364 if (unlikely(!wd_regs))
365 return -ENOMEM;
366 wd_irq = ri->start;
367 wd_ctr = rc->start;
368 res = misc_register(&miscdev);
369 if (res)
370 iounmap(wd_regs);
371 else
372 register_reboot_notifier(&wdt_gpi_shutdown);
373 return res;
374}
375
376static int __devexit wdt_gpi_remove(struct platform_device *dev)
377{
378 int res;
379
380 unregister_reboot_notifier(&wdt_gpi_shutdown);
381 res = misc_deregister(&miscdev);
382 iounmap(wd_regs);
383 wd_regs = NULL;
384 return res;
385}
386
387
388/* Device driver init & exit */
389static struct platform_driver wgt_gpi_driver = {
390 .driver = {
391 .name = wdt_gpi_name,
392 .owner = THIS_MODULE,
393 },
394 .probe = wdt_gpi_probe,
395 .remove = __devexit_p(wdt_gpi_remove),
396};
397
398static int __init wdt_gpi_init_module(void)
399{
400 atomic_set(&opencnt, 1);
401 if (timeout > MAX_TIMEOUT_SECONDS)
402 timeout = MAX_TIMEOUT_SECONDS;
403 return platform_driver_register(&wdt_gpi_driver);
404}
405
406static void __exit wdt_gpi_cleanup_module(void)
407{
408 platform_driver_unregister(&wdt_gpi_driver);
409}
410
411module_init(wdt_gpi_init_module);
412module_exit(wdt_gpi_cleanup_module);
413
414MODULE_AUTHOR("Thomas Koeller <thomas.koeller@baslerweb.com>");
415MODULE_DESCRIPTION("Basler eXcite watchdog driver for gpi devices");
416MODULE_VERSION("0.1");
417MODULE_LICENSE("GPL");
418MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
419
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-25 16:57:04 -0500