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-rw-r--r--drivers/gpu/drm/nouveau/Kconfig5
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bo.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fence.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_gem.c7
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_mem.c4
-rw-r--r--drivers/gpu/drm/nouveau/nv40_graph.c20
-rw-r--r--drivers/gpu/drm/radeon/Makefile2
-rw-r--r--drivers/gpu/drm/radeon/r100.c54
-rw-r--r--drivers/gpu/drm/radeon/r100_track.h5
-rw-r--r--drivers/gpu/drm/radeon/r200.c10
-rw-r--r--drivers/gpu/drm/radeon/r300.c24
-rw-r--r--drivers/gpu/drm/radeon/r600.c19
-rw-r--r--drivers/gpu/drm/radeon/r600_audio.c267
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c506
-rw-r--r--drivers/gpu/drm/radeon/r600_reg.h74
-rw-r--r--drivers/gpu/drm/radeon/radeon.h25
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c16
-rw-r--r--drivers/gpu/drm/radeon/radeon_gem.c8
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h3
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c21
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.h16
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c7
-rw-r--r--drivers/gpu/drm/radeon/radeon_ttm.c14
-rw-r--r--drivers/gpu/drm/radeon/rs400.c2
-rw-r--r--drivers/gpu/drm/radeon/rv770.c14
-rw-r--r--drivers/gpu/drm/ttm/ttm_bo.c77
-rw-r--r--drivers/gpu/drm/ttm/ttm_bo_vm.c2
28 files changed, 1118 insertions, 92 deletions
diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig
index d823e6319516..b1bc1ea182b8 100644
--- a/drivers/gpu/drm/nouveau/Kconfig
+++ b/drivers/gpu/drm/nouveau/Kconfig
@@ -30,11 +30,12 @@ config DRM_NOUVEAU_DEBUG
30 via debugfs. 30 via debugfs.
31 31
32menu "I2C encoder or helper chips" 32menu "I2C encoder or helper chips"
33 depends on DRM 33 depends on DRM && I2C
34 34
35config DRM_I2C_CH7006 35config DRM_I2C_CH7006
36 tristate "Chrontel ch7006 TV encoder" 36 tristate "Chrontel ch7006 TV encoder"
37 default m if DRM_NOUVEAU 37 depends on DRM_NOUVEAU
38 default m
38 help 39 help
39 Support for Chrontel ch7006 and similar TV encoders, found 40 Support for Chrontel ch7006 and similar TV encoders, found
40 on some nVidia video cards. 41 on some nVidia video cards.
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 320a14bceb99..aa2dfbc3e351 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -311,8 +311,10 @@ nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
311 struct drm_device *dev = dev_priv->dev; 311 struct drm_device *dev = dev_priv->dev;
312 312
313 switch (dev_priv->gart_info.type) { 313 switch (dev_priv->gart_info.type) {
314#if __OS_HAS_AGP
314 case NOUVEAU_GART_AGP: 315 case NOUVEAU_GART_AGP:
315 return ttm_agp_backend_init(bdev, dev->agp->bridge); 316 return ttm_agp_backend_init(bdev, dev->agp->bridge);
317#endif
316 case NOUVEAU_GART_SGDMA: 318 case NOUVEAU_GART_SGDMA:
317 return nouveau_sgdma_init_ttm(dev); 319 return nouveau_sgdma_init_ttm(dev);
318 default: 320 default:
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c
index 0cff7eb3690a..dacac9a0842a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.c
@@ -205,7 +205,7 @@ nouveau_fence_wait(void *sync_obj, void *sync_arg, bool lazy, bool intr)
205 schedule_timeout(1); 205 schedule_timeout(1);
206 206
207 if (intr && signal_pending(current)) { 207 if (intr && signal_pending(current)) {
208 ret = -ERESTART; 208 ret = -ERESTARTSYS;
209 break; 209 break;
210 } 210 }
211 } 211 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index 11f831f0ddc5..18fd8ac9fca7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -342,8 +342,6 @@ retry:
342 } 342 }
343 343
344 ret = ttm_bo_wait_cpu(&nvbo->bo, false); 344 ret = ttm_bo_wait_cpu(&nvbo->bo, false);
345 if (ret == -ERESTART)
346 ret = -EAGAIN;
347 if (ret) 345 if (ret)
348 return ret; 346 return ret;
349 goto retry; 347 goto retry;
@@ -915,8 +913,6 @@ nouveau_gem_ioctl_cpu_prep(struct drm_device *dev, void *data,
915 goto out; 913 goto out;
916 914
917 ret = ttm_bo_wait_cpu(&nvbo->bo, no_wait); 915 ret = ttm_bo_wait_cpu(&nvbo->bo, no_wait);
918 if (ret == -ERESTART)
919 ret = -EAGAIN;
920 if (ret) 916 if (ret)
921 goto out; 917 goto out;
922 } 918 }
@@ -925,9 +921,6 @@ nouveau_gem_ioctl_cpu_prep(struct drm_device *dev, void *data,
925 ret = ttm_bo_wait(&nvbo->bo, false, false, no_wait); 921 ret = ttm_bo_wait(&nvbo->bo, false, false, no_wait);
926 } else { 922 } else {
927 ret = ttm_bo_synccpu_write_grab(&nvbo->bo, no_wait); 923 ret = ttm_bo_synccpu_write_grab(&nvbo->bo, no_wait);
928 if (ret == -ERESTART)
929 ret = -EAGAIN;
930 else
931 if (ret == 0) 924 if (ret == 0)
932 nvbo->cpu_filp = file_priv; 925 nvbo->cpu_filp = file_priv;
933 } 926 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 02755712ed3d..5158a12f7844 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -407,6 +407,7 @@ uint64_t nouveau_mem_fb_amount(struct drm_device *dev)
407 return 0; 407 return 0;
408} 408}
409 409
410#if __OS_HAS_AGP
410static void nouveau_mem_reset_agp(struct drm_device *dev) 411static void nouveau_mem_reset_agp(struct drm_device *dev)
411{ 412{
412 uint32_t saved_pci_nv_1, saved_pci_nv_19, pmc_enable; 413 uint32_t saved_pci_nv_1, saved_pci_nv_19, pmc_enable;
@@ -432,10 +433,12 @@ static void nouveau_mem_reset_agp(struct drm_device *dev)
432 nv_wr32(dev, NV04_PBUS_PCI_NV_19, saved_pci_nv_19); 433 nv_wr32(dev, NV04_PBUS_PCI_NV_19, saved_pci_nv_19);
433 nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1); 434 nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
434} 435}
436#endif
435 437
436int 438int
437nouveau_mem_init_agp(struct drm_device *dev) 439nouveau_mem_init_agp(struct drm_device *dev)
438{ 440{
441#if __OS_HAS_AGP
439 struct drm_nouveau_private *dev_priv = dev->dev_private; 442 struct drm_nouveau_private *dev_priv = dev->dev_private;
440 struct drm_agp_info info; 443 struct drm_agp_info info;
441 struct drm_agp_mode mode; 444 struct drm_agp_mode mode;
@@ -471,6 +474,7 @@ nouveau_mem_init_agp(struct drm_device *dev)
471 dev_priv->gart_info.type = NOUVEAU_GART_AGP; 474 dev_priv->gart_info.type = NOUVEAU_GART_AGP;
472 dev_priv->gart_info.aper_base = info.aperture_base; 475 dev_priv->gart_info.aper_base = info.aperture_base;
473 dev_priv->gart_info.aper_size = info.aperture_size; 476 dev_priv->gart_info.aper_size = info.aperture_size;
477#endif
474 return 0; 478 return 0;
475} 479}
476 480
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
index d3e0a2a6acf8..7e8547cb5833 100644
--- a/drivers/gpu/drm/nouveau/nv40_graph.c
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
@@ -252,8 +252,9 @@ nv40_grctx_init(struct drm_device *dev)
252 memcpy(pgraph->ctxprog, fw->data, fw->size); 252 memcpy(pgraph->ctxprog, fw->data, fw->size);
253 253
254 cp = pgraph->ctxprog; 254 cp = pgraph->ctxprog;
255 if (cp->signature != 0x5043564e || cp->version != 0 || 255 if (le32_to_cpu(cp->signature) != 0x5043564e ||
256 cp->length != ((fw->size - 7) / 4)) { 256 cp->version != 0 ||
257 le16_to_cpu(cp->length) != ((fw->size - 7) / 4)) {
257 NV_ERROR(dev, "ctxprog invalid\n"); 258 NV_ERROR(dev, "ctxprog invalid\n");
258 release_firmware(fw); 259 release_firmware(fw);
259 nv40_grctx_fini(dev); 260 nv40_grctx_fini(dev);
@@ -281,8 +282,9 @@ nv40_grctx_init(struct drm_device *dev)
281 memcpy(pgraph->ctxvals, fw->data, fw->size); 282 memcpy(pgraph->ctxvals, fw->data, fw->size);
282 283
283 cv = (void *)pgraph->ctxvals; 284 cv = (void *)pgraph->ctxvals;
284 if (cv->signature != 0x5643564e || cv->version != 0 || 285 if (le32_to_cpu(cv->signature) != 0x5643564e ||
285 cv->length != ((fw->size - 9) / 8)) { 286 cv->version != 0 ||
287 le32_to_cpu(cv->length) != ((fw->size - 9) / 8)) {
286 NV_ERROR(dev, "ctxvals invalid\n"); 288 NV_ERROR(dev, "ctxvals invalid\n");
287 release_firmware(fw); 289 release_firmware(fw);
288 nv40_grctx_fini(dev); 290 nv40_grctx_fini(dev);
@@ -294,8 +296,9 @@ nv40_grctx_init(struct drm_device *dev)
294 cp = pgraph->ctxprog; 296 cp = pgraph->ctxprog;
295 297
296 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0); 298 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
297 for (i = 0; i < cp->length; i++) 299 for (i = 0; i < le16_to_cpu(cp->length); i++)
298 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp->data[i]); 300 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA,
301 le32_to_cpu(cp->data[i]));
299 302
300 pgraph->accel_blocked = false; 303 pgraph->accel_blocked = false;
301 return 0; 304 return 0;
@@ -329,8 +332,9 @@ nv40_grctx_vals_load(struct drm_device *dev, struct nouveau_gpuobj *ctx)
329 if (!cv) 332 if (!cv)
330 return; 333 return;
331 334
332 for (i = 0; i < cv->length; i++) 335 for (i = 0; i < le32_to_cpu(cv->length); i++)
333 nv_wo32(dev, ctx, cv->data[i].offset, cv->data[i].value); 336 nv_wo32(dev, ctx, le32_to_cpu(cv->data[i].offset),
337 le32_to_cpu(cv->data[i].value));
334} 338}
335 339
336/* 340/*
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index feb52eee4314..b5f5fe75e6af 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -49,7 +49,7 @@ radeon-y += radeon_device.o radeon_kms.o \
49 radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \ 49 radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \
50 rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \ 50 rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \
51 r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \ 51 r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \
52 r600_blit_kms.o radeon_pm.o atombios_dp.o 52 r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o
53 53
54radeon-$(CONFIG_COMPAT) += radeon_ioc32.o 54radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
55 55
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 824cc6480a06..84e5df766d3f 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1374,7 +1374,6 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1374 case RADEON_TXFORMAT_ARGB4444: 1374 case RADEON_TXFORMAT_ARGB4444:
1375 case RADEON_TXFORMAT_VYUY422: 1375 case RADEON_TXFORMAT_VYUY422:
1376 case RADEON_TXFORMAT_YVYU422: 1376 case RADEON_TXFORMAT_YVYU422:
1377 case RADEON_TXFORMAT_DXT1:
1378 case RADEON_TXFORMAT_SHADOW16: 1377 case RADEON_TXFORMAT_SHADOW16:
1379 case RADEON_TXFORMAT_LDUDV655: 1378 case RADEON_TXFORMAT_LDUDV655:
1380 case RADEON_TXFORMAT_DUDV88: 1379 case RADEON_TXFORMAT_DUDV88:
@@ -1382,12 +1381,19 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1382 break; 1381 break;
1383 case RADEON_TXFORMAT_ARGB8888: 1382 case RADEON_TXFORMAT_ARGB8888:
1384 case RADEON_TXFORMAT_RGBA8888: 1383 case RADEON_TXFORMAT_RGBA8888:
1385 case RADEON_TXFORMAT_DXT23:
1386 case RADEON_TXFORMAT_DXT45:
1387 case RADEON_TXFORMAT_SHADOW32: 1384 case RADEON_TXFORMAT_SHADOW32:
1388 case RADEON_TXFORMAT_LDUDUV8888: 1385 case RADEON_TXFORMAT_LDUDUV8888:
1389 track->textures[i].cpp = 4; 1386 track->textures[i].cpp = 4;
1390 break; 1387 break;
1388 case RADEON_TXFORMAT_DXT1:
1389 track->textures[i].cpp = 1;
1390 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1391 break;
1392 case RADEON_TXFORMAT_DXT23:
1393 case RADEON_TXFORMAT_DXT45:
1394 track->textures[i].cpp = 1;
1395 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1396 break;
1391 } 1397 }
1392 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1398 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1393 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 1399 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
@@ -2731,6 +2737,7 @@ static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2731 DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 2737 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2732 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 2738 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2733 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 2739 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2740 DRM_ERROR("compress format %d\n", t->compress_format);
2734} 2741}
2735 2742
2736static int r100_cs_track_cube(struct radeon_device *rdev, 2743static int r100_cs_track_cube(struct radeon_device *rdev,
@@ -2760,6 +2767,36 @@ static int r100_cs_track_cube(struct radeon_device *rdev,
2760 return 0; 2767 return 0;
2761} 2768}
2762 2769
2770static int r100_track_compress_size(int compress_format, int w, int h)
2771{
2772 int block_width, block_height, block_bytes;
2773 int wblocks, hblocks;
2774 int min_wblocks;
2775 int sz;
2776
2777 block_width = 4;
2778 block_height = 4;
2779
2780 switch (compress_format) {
2781 case R100_TRACK_COMP_DXT1:
2782 block_bytes = 8;
2783 min_wblocks = 4;
2784 break;
2785 default:
2786 case R100_TRACK_COMP_DXT35:
2787 block_bytes = 16;
2788 min_wblocks = 2;
2789 break;
2790 }
2791
2792 hblocks = (h + block_height - 1) / block_height;
2793 wblocks = (w + block_width - 1) / block_width;
2794 if (wblocks < min_wblocks)
2795 wblocks = min_wblocks;
2796 sz = wblocks * hblocks * block_bytes;
2797 return sz;
2798}
2799
2763static int r100_cs_track_texture_check(struct radeon_device *rdev, 2800static int r100_cs_track_texture_check(struct radeon_device *rdev,
2764 struct r100_cs_track *track) 2801 struct r100_cs_track *track)
2765{ 2802{
@@ -2797,9 +2834,15 @@ static int r100_cs_track_texture_check(struct radeon_device *rdev,
2797 h = h / (1 << i); 2834 h = h / (1 << i);
2798 if (track->textures[u].roundup_h) 2835 if (track->textures[u].roundup_h)
2799 h = roundup_pow_of_two(h); 2836 h = roundup_pow_of_two(h);
2800 size += w * h; 2837 if (track->textures[u].compress_format) {
2838
2839 size += r100_track_compress_size(track->textures[u].compress_format, w, h);
2840 /* compressed textures are block based */
2841 } else
2842 size += w * h;
2801 } 2843 }
2802 size *= track->textures[u].cpp; 2844 size *= track->textures[u].cpp;
2845
2803 switch (track->textures[u].tex_coord_type) { 2846 switch (track->textures[u].tex_coord_type) {
2804 case 0: 2847 case 0:
2805 break; 2848 break;
@@ -2967,6 +3010,7 @@ void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track
2967 track->arrays[i].esize = 0x7F; 3010 track->arrays[i].esize = 0x7F;
2968 } 3011 }
2969 for (i = 0; i < track->num_texture; i++) { 3012 for (i = 0; i < track->num_texture; i++) {
3013 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2970 track->textures[i].pitch = 16536; 3014 track->textures[i].pitch = 16536;
2971 track->textures[i].width = 16536; 3015 track->textures[i].width = 16536;
2972 track->textures[i].height = 16536; 3016 track->textures[i].height = 16536;
@@ -3399,6 +3443,8 @@ int r100_init(struct radeon_device *rdev)
3399 r100_errata(rdev); 3443 r100_errata(rdev);
3400 /* Initialize clocks */ 3444 /* Initialize clocks */
3401 radeon_get_clock_info(rdev->ddev); 3445 radeon_get_clock_info(rdev->ddev);
3446 /* Initialize power management */
3447 radeon_pm_init(rdev);
3402 /* Get vram informations */ 3448 /* Get vram informations */
3403 r100_vram_info(rdev); 3449 r100_vram_info(rdev);
3404 /* Initialize memory controller (also test AGP) */ 3450 /* Initialize memory controller (also test AGP) */
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
index ca50903dd2bb..7188c3778ee2 100644
--- a/drivers/gpu/drm/radeon/r100_track.h
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -28,6 +28,10 @@ struct r100_cs_cube_info {
28 unsigned height; 28 unsigned height;
29}; 29};
30 30
31#define R100_TRACK_COMP_NONE 0
32#define R100_TRACK_COMP_DXT1 1
33#define R100_TRACK_COMP_DXT35 2
34
31struct r100_cs_track_texture { 35struct r100_cs_track_texture {
32 struct radeon_bo *robj; 36 struct radeon_bo *robj;
33 struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */ 37 struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
@@ -44,6 +48,7 @@ struct r100_cs_track_texture {
44 bool enabled; 48 bool enabled;
45 bool roundup_w; 49 bool roundup_w;
46 bool roundup_h; 50 bool roundup_h;
51 unsigned compress_format;
47}; 52};
48 53
49struct r100_cs_track_limits { 54struct r100_cs_track_limits {
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
index eb740fc3549f..20942127c46b 100644
--- a/drivers/gpu/drm/radeon/r200.c
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -401,7 +401,6 @@ int r200_packet0_check(struct radeon_cs_parser *p,
401 case R200_TXFORMAT_Y8: 401 case R200_TXFORMAT_Y8:
402 track->textures[i].cpp = 1; 402 track->textures[i].cpp = 1;
403 break; 403 break;
404 case R200_TXFORMAT_DXT1:
405 case R200_TXFORMAT_AI88: 404 case R200_TXFORMAT_AI88:
406 case R200_TXFORMAT_ARGB1555: 405 case R200_TXFORMAT_ARGB1555:
407 case R200_TXFORMAT_RGB565: 406 case R200_TXFORMAT_RGB565:
@@ -418,9 +417,16 @@ int r200_packet0_check(struct radeon_cs_parser *p,
418 case R200_TXFORMAT_ABGR8888: 417 case R200_TXFORMAT_ABGR8888:
419 case R200_TXFORMAT_BGR111110: 418 case R200_TXFORMAT_BGR111110:
420 case R200_TXFORMAT_LDVDU8888: 419 case R200_TXFORMAT_LDVDU8888:
420 track->textures[i].cpp = 4;
421 break;
422 case R200_TXFORMAT_DXT1:
423 track->textures[i].cpp = 1;
424 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
425 break;
421 case R200_TXFORMAT_DXT23: 426 case R200_TXFORMAT_DXT23:
422 case R200_TXFORMAT_DXT45: 427 case R200_TXFORMAT_DXT45:
423 track->textures[i].cpp = 4; 428 track->textures[i].cpp = 1;
429 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
424 break; 430 break;
425 } 431 }
426 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 432 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 83378c39d0e3..83490c2b5061 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -686,7 +686,15 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
686 r100_cs_dump_packet(p, pkt); 686 r100_cs_dump_packet(p, pkt);
687 return r; 687 return r;
688 } 688 }
689 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 689
690 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
691 tile_flags |= R300_TXO_MACRO_TILE;
692 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
693 tile_flags |= R300_TXO_MICRO_TILE;
694
695 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
696 tmp |= tile_flags;
697 ib[idx] = tmp;
690 track->textures[i].robj = reloc->robj; 698 track->textures[i].robj = reloc->robj;
691 break; 699 break;
692 /* Tracked registers */ 700 /* Tracked registers */
@@ -852,7 +860,6 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
852 case R300_TX_FORMAT_Z6Y5X5: 860 case R300_TX_FORMAT_Z6Y5X5:
853 case R300_TX_FORMAT_W4Z4Y4X4: 861 case R300_TX_FORMAT_W4Z4Y4X4:
854 case R300_TX_FORMAT_W1Z5Y5X5: 862 case R300_TX_FORMAT_W1Z5Y5X5:
855 case R300_TX_FORMAT_DXT1:
856 case R300_TX_FORMAT_D3DMFT_CxV8U8: 863 case R300_TX_FORMAT_D3DMFT_CxV8U8:
857 case R300_TX_FORMAT_B8G8_B8G8: 864 case R300_TX_FORMAT_B8G8_B8G8:
858 case R300_TX_FORMAT_G8R8_G8B8: 865 case R300_TX_FORMAT_G8R8_G8B8:
@@ -866,8 +873,6 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
866 case 0x17: 873 case 0x17:
867 case R300_TX_FORMAT_FL_I32: 874 case R300_TX_FORMAT_FL_I32:
868 case 0x1e: 875 case 0x1e:
869 case R300_TX_FORMAT_DXT3:
870 case R300_TX_FORMAT_DXT5:
871 track->textures[i].cpp = 4; 876 track->textures[i].cpp = 4;
872 break; 877 break;
873 case R300_TX_FORMAT_W16Z16Y16X16: 878 case R300_TX_FORMAT_W16Z16Y16X16:
@@ -878,6 +883,15 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
878 case R300_TX_FORMAT_FL_R32G32B32A32: 883 case R300_TX_FORMAT_FL_R32G32B32A32:
879 track->textures[i].cpp = 16; 884 track->textures[i].cpp = 16;
880 break; 885 break;
886 case R300_TX_FORMAT_DXT1:
887 track->textures[i].cpp = 1;
888 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
889 break;
890 case R300_TX_FORMAT_DXT3:
891 case R300_TX_FORMAT_DXT5:
892 track->textures[i].cpp = 1;
893 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
894 break;
881 default: 895 default:
882 DRM_ERROR("Invalid texture format %u\n", 896 DRM_ERROR("Invalid texture format %u\n",
883 (idx_value & 0x1F)); 897 (idx_value & 0x1F));
@@ -1324,6 +1338,8 @@ int r300_init(struct radeon_device *rdev)
1324 r300_errata(rdev); 1338 r300_errata(rdev);
1325 /* Initialize clocks */ 1339 /* Initialize clocks */
1326 radeon_get_clock_info(rdev->ddev); 1340 radeon_get_clock_info(rdev->ddev);
1341 /* Initialize power management */
1342 radeon_pm_init(rdev);
1327 /* Get vram informations */ 1343 /* Get vram informations */
1328 r300_vram_info(rdev); 1344 r300_vram_info(rdev);
1329 /* Initialize memory controller (also test AGP) */ 1345 /* Initialize memory controller (also test AGP) */
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 36656bd110bf..a0ac3c134b1b 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1863,6 +1863,14 @@ int r600_startup(struct radeon_device *rdev)
1863 } 1863 }
1864 r600_gpu_init(rdev); 1864 r600_gpu_init(rdev);
1865 1865
1866 if (!rdev->r600_blit.shader_obj) {
1867 r = r600_blit_init(rdev);
1868 if (r) {
1869 DRM_ERROR("radeon: failed blitter (%d).\n", r);
1870 return r;
1871 }
1872 }
1873
1866 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 1874 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1867 if (unlikely(r != 0)) 1875 if (unlikely(r != 0))
1868 return r; 1876 return r;
@@ -2038,12 +2046,6 @@ int r600_init(struct radeon_device *rdev)
2038 if (r) 2046 if (r)
2039 return r; 2047 return r;
2040 2048
2041 r = r600_blit_init(rdev);
2042 if (r) {
2043 DRM_ERROR("radeon: failed blitter (%d).\n", r);
2044 return r;
2045 }
2046
2047 rdev->accel_working = true; 2049 rdev->accel_working = true;
2048 r = r600_startup(rdev); 2050 r = r600_startup(rdev);
2049 if (r) { 2051 if (r) {
@@ -2065,6 +2067,10 @@ int r600_init(struct radeon_device *rdev)
2065 rdev->accel_working = false; 2067 rdev->accel_working = false;
2066 } 2068 }
2067 } 2069 }
2070
2071 r = r600_audio_init(rdev);
2072 if (r)
2073 return r; /* TODO error handling */
2068 return 0; 2074 return 0;
2069} 2075}
2070 2076
@@ -2073,6 +2079,7 @@ void r600_fini(struct radeon_device *rdev)
2073 /* Suspend operations */ 2079 /* Suspend operations */
2074 r600_suspend(rdev); 2080 r600_suspend(rdev);
2075 2081
2082 r600_audio_fini(rdev);
2076 r600_blit_fini(rdev); 2083 r600_blit_fini(rdev);
2077 r600_irq_fini(rdev); 2084 r600_irq_fini(rdev);
2078 radeon_irq_kms_fini(rdev); 2085 radeon_irq_kms_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c
new file mode 100644
index 000000000000..99e2c3891a7d
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600_audio.c
@@ -0,0 +1,267 @@
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Christian König
25 */
26#include "drmP.h"
27#include "radeon.h"
28#include "radeon_reg.h"
29#include "atom.h"
30
31#define AUDIO_TIMER_INTERVALL 100 /* 1/10 sekund should be enough */
32
33/*
34 * check if the chipset is supported
35 */
36static int r600_audio_chipset_supported(struct radeon_device *rdev)
37{
38 return rdev->family >= CHIP_R600
39 || rdev->family == CHIP_RS600
40 || rdev->family == CHIP_RS690
41 || rdev->family == CHIP_RS740;
42}
43
44/*
45 * current number of channels
46 */
47static int r600_audio_channels(struct radeon_device *rdev)
48{
49 return (RREG32(R600_AUDIO_RATE_BPS_CHANNEL) & 0x7) + 1;
50}
51
52/*
53 * current bits per sample
54 */
55static int r600_audio_bits_per_sample(struct radeon_device *rdev)
56{
57 uint32_t value = (RREG32(R600_AUDIO_RATE_BPS_CHANNEL) & 0xF0) >> 4;
58 switch (value) {
59 case 0x0: return 8;
60 case 0x1: return 16;
61 case 0x2: return 20;
62 case 0x3: return 24;
63 case 0x4: return 32;
64 }
65
66 DRM_ERROR("Unknown bits per sample 0x%x using 16 instead.\n", (int)value);
67
68 return 16;
69}
70
71/*
72 * current sampling rate in HZ
73 */
74static int r600_audio_rate(struct radeon_device *rdev)
75{
76 uint32_t value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL);
77 uint32_t result;
78
79 if (value & 0x4000)
80 result = 44100;
81 else
82 result = 48000;
83
84 result *= ((value >> 11) & 0x7) + 1;
85 result /= ((value >> 8) & 0x7) + 1;
86
87 return result;
88}
89
90/*
91 * iec 60958 status bits
92 */
93static uint8_t r600_audio_status_bits(struct radeon_device *rdev)
94{
95 return RREG32(R600_AUDIO_STATUS_BITS) & 0xff;
96}
97
98/*
99 * iec 60958 category code
100 */
101static uint8_t r600_audio_category_code(struct radeon_device *rdev)
102{
103 return (RREG32(R600_AUDIO_STATUS_BITS) >> 8) & 0xff;
104}
105
106/*
107 * update all hdmi interfaces with current audio parameters
108 */
109static void r600_audio_update_hdmi(unsigned long param)
110{
111 struct radeon_device *rdev = (struct radeon_device *)param;
112 struct drm_device *dev = rdev->ddev;
113
114 int channels = r600_audio_channels(rdev);
115 int rate = r600_audio_rate(rdev);
116 int bps = r600_audio_bits_per_sample(rdev);
117 uint8_t status_bits = r600_audio_status_bits(rdev);
118 uint8_t category_code = r600_audio_category_code(rdev);
119
120 struct drm_encoder *encoder;
121 int changes = 0;
122
123 changes |= channels != rdev->audio_channels;
124 changes |= rate != rdev->audio_rate;
125 changes |= bps != rdev->audio_bits_per_sample;
126 changes |= status_bits != rdev->audio_status_bits;
127 changes |= category_code != rdev->audio_category_code;
128
129 if (changes) {
130 rdev->audio_channels = channels;
131 rdev->audio_rate = rate;
132 rdev->audio_bits_per_sample = bps;
133 rdev->audio_status_bits = status_bits;
134 rdev->audio_category_code = category_code;
135 }
136
137 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
138 if (changes || r600_hdmi_buffer_status_changed(encoder))
139 r600_hdmi_update_audio_settings(
140 encoder, channels,
141 rate, bps, status_bits,
142 category_code);
143 }
144
145 mod_timer(&rdev->audio_timer,
146 jiffies + msecs_to_jiffies(AUDIO_TIMER_INTERVALL));
147}
148
149/*
150 * initialize the audio vars and register the update timer
151 */
152int r600_audio_init(struct radeon_device *rdev)
153{
154 if (!r600_audio_chipset_supported(rdev))
155 return 0;
156
157 DRM_INFO("%s audio support", radeon_audio ? "Enabling" : "Disabling");
158 WREG32_P(R600_AUDIO_ENABLE, radeon_audio ? 0x81000000 : 0x0, ~0x81000000);
159
160 rdev->audio_channels = -1;
161 rdev->audio_rate = -1;
162 rdev->audio_bits_per_sample = -1;
163 rdev->audio_status_bits = 0;
164 rdev->audio_category_code = 0;
165
166 setup_timer(
167 &rdev->audio_timer,
168 r600_audio_update_hdmi,
169 (unsigned long)rdev);
170
171 mod_timer(&rdev->audio_timer, jiffies + 1);
172
173 return 0;
174}
175
176/*
177 * determin how the encoders and audio interface is wired together
178 */
179int r600_audio_tmds_index(struct drm_encoder *encoder)
180{
181 struct drm_device *dev = encoder->dev;
182 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
183 struct drm_encoder *other;
184
185 switch (radeon_encoder->encoder_id) {
186 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
187 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
188 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
189 return 0;
190
191 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
192 /* special case check if an TMDS1 is present */
193 list_for_each_entry(other, &dev->mode_config.encoder_list, head) {
194 if (to_radeon_encoder(other)->encoder_id ==
195 ENCODER_OBJECT_ID_INTERNAL_TMDS1)
196 return 1;
197 }
198 return 0;
199
200 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
201 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
202 return 1;
203
204 default:
205 DRM_ERROR("Unsupported encoder type 0x%02X\n",
206 radeon_encoder->encoder_id);
207 return -1;
208 }
209}
210
211/*
212 * atach the audio codec to the clock source of the encoder
213 */
214void r600_audio_set_clock(struct drm_encoder *encoder, int clock)
215{
216 struct drm_device *dev = encoder->dev;
217 struct radeon_device *rdev = dev->dev_private;
218 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
219 int base_rate = 48000;
220
221 switch (radeon_encoder->encoder_id) {
222 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
223 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
224 WREG32_P(R600_AUDIO_TIMING, 0, ~0x301);
225 break;
226
227 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
228 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
229 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
230 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
231 WREG32_P(R600_AUDIO_TIMING, 0x100, ~0x301);
232 break;
233
234 default:
235 DRM_ERROR("Unsupported encoder type 0x%02X\n",
236 radeon_encoder->encoder_id);
237 return;
238 }
239
240 switch (r600_audio_tmds_index(encoder)) {
241 case 0:
242 WREG32(R600_AUDIO_PLL1_MUL, base_rate*50);
243 WREG32(R600_AUDIO_PLL1_DIV, clock*100);
244 WREG32(R600_AUDIO_CLK_SRCSEL, 0);
245 break;
246
247 case 1:
248 WREG32(R600_AUDIO_PLL2_MUL, base_rate*50);
249 WREG32(R600_AUDIO_PLL2_DIV, clock*100);
250 WREG32(R600_AUDIO_CLK_SRCSEL, 1);
251 break;
252 }
253}
254
255/*
256 * release the audio timer
257 * TODO: How to do this correctly on SMP systems?
258 */
259void r600_audio_fini(struct radeon_device *rdev)
260{
261 if (!r600_audio_chipset_supported(rdev))
262 return;
263
264 WREG32_P(R600_AUDIO_ENABLE, 0x0, ~0x81000000);
265
266 del_timer(&rdev->audio_timer);
267}
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
new file mode 100644
index 000000000000..fcc949df0e5d
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -0,0 +1,506 @@
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Christian König
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29#include "atom.h"
30
31/*
32 * HDMI color format
33 */
34enum r600_hdmi_color_format {
35 RGB = 0,
36 YCC_422 = 1,
37 YCC_444 = 2
38};
39
40/*
41 * IEC60958 status bits
42 */
43enum r600_hdmi_iec_status_bits {
44 AUDIO_STATUS_DIG_ENABLE = 0x01,
45 AUDIO_STATUS_V = 0x02,
46 AUDIO_STATUS_VCFG = 0x04,
47 AUDIO_STATUS_EMPHASIS = 0x08,
48 AUDIO_STATUS_COPYRIGHT = 0x10,
49 AUDIO_STATUS_NONAUDIO = 0x20,
50 AUDIO_STATUS_PROFESSIONAL = 0x40,
51 AUDIO_STATUS_LEVEL = 0x80
52};
53
54struct {
55 uint32_t Clock;
56
57 int N_32kHz;
58 int CTS_32kHz;
59
60 int N_44_1kHz;
61 int CTS_44_1kHz;
62
63 int N_48kHz;
64 int CTS_48kHz;
65
66} r600_hdmi_ACR[] = {
67 /* 32kHz 44.1kHz 48kHz */
68 /* Clock N CTS N CTS N CTS */
69 { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */
70 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
71 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
72 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
73 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
74 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
75 { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */
76 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
77 { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */
78 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
79 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */
80};
81
82/*
83 * calculate CTS value if it's not found in the table
84 */
85static void r600_hdmi_calc_CTS(uint32_t clock, int *CTS, int N, int freq)
86{
87 if (*CTS == 0)
88 *CTS = clock*N/(128*freq)*1000;
89 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
90 N, *CTS, freq);
91}
92
93/*
94 * update the N and CTS parameters for a given pixel clock rate
95 */
96static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
97{
98 struct drm_device *dev = encoder->dev;
99 struct radeon_device *rdev = dev->dev_private;
100 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
101 int CTS;
102 int N;
103 int i;
104
105 for (i = 0; r600_hdmi_ACR[i].Clock != clock && r600_hdmi_ACR[i].Clock != 0; i++);
106
107 CTS = r600_hdmi_ACR[i].CTS_32kHz;
108 N = r600_hdmi_ACR[i].N_32kHz;
109 r600_hdmi_calc_CTS(clock, &CTS, N, 32000);
110 WREG32(offset+R600_HDMI_32kHz_CTS, CTS << 12);
111 WREG32(offset+R600_HDMI_32kHz_N, N);
112
113 CTS = r600_hdmi_ACR[i].CTS_44_1kHz;
114 N = r600_hdmi_ACR[i].N_44_1kHz;
115 r600_hdmi_calc_CTS(clock, &CTS, N, 44100);
116 WREG32(offset+R600_HDMI_44_1kHz_CTS, CTS << 12);
117 WREG32(offset+R600_HDMI_44_1kHz_N, N);
118
119 CTS = r600_hdmi_ACR[i].CTS_48kHz;
120 N = r600_hdmi_ACR[i].N_48kHz;
121 r600_hdmi_calc_CTS(clock, &CTS, N, 48000);
122 WREG32(offset+R600_HDMI_48kHz_CTS, CTS << 12);
123 WREG32(offset+R600_HDMI_48kHz_N, N);
124}
125
126/*
127 * calculate the crc for a given info frame
128 */
129static void r600_hdmi_infoframe_checksum(uint8_t packetType,
130 uint8_t versionNumber,
131 uint8_t length,
132 uint8_t *frame)
133{
134 int i;
135 frame[0] = packetType + versionNumber + length;
136 for (i = 1; i <= length; i++)
137 frame[0] += frame[i];
138 frame[0] = 0x100 - frame[0];
139}
140
141/*
142 * build a HDMI Video Info Frame
143 */
144static void r600_hdmi_videoinfoframe(
145 struct drm_encoder *encoder,
146 enum r600_hdmi_color_format color_format,
147 int active_information_present,
148 uint8_t active_format_aspect_ratio,
149 uint8_t scan_information,
150 uint8_t colorimetry,
151 uint8_t ex_colorimetry,
152 uint8_t quantization,
153 int ITC,
154 uint8_t picture_aspect_ratio,
155 uint8_t video_format_identification,
156 uint8_t pixel_repetition,
157 uint8_t non_uniform_picture_scaling,
158 uint8_t bar_info_data_valid,
159 uint16_t top_bar,
160 uint16_t bottom_bar,
161 uint16_t left_bar,
162 uint16_t right_bar
163)
164{
165 struct drm_device *dev = encoder->dev;
166 struct radeon_device *rdev = dev->dev_private;
167 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
168
169 uint8_t frame[14];
170
171 frame[0x0] = 0;
172 frame[0x1] =
173 (scan_information & 0x3) |
174 ((bar_info_data_valid & 0x3) << 2) |
175 ((active_information_present & 0x1) << 4) |
176 ((color_format & 0x3) << 5);
177 frame[0x2] =
178 (active_format_aspect_ratio & 0xF) |
179 ((picture_aspect_ratio & 0x3) << 4) |
180 ((colorimetry & 0x3) << 6);
181 frame[0x3] =
182 (non_uniform_picture_scaling & 0x3) |
183 ((quantization & 0x3) << 2) |
184 ((ex_colorimetry & 0x7) << 4) |
185 ((ITC & 0x1) << 7);
186 frame[0x4] = (video_format_identification & 0x7F);
187 frame[0x5] = (pixel_repetition & 0xF);
188 frame[0x6] = (top_bar & 0xFF);
189 frame[0x7] = (top_bar >> 8);
190 frame[0x8] = (bottom_bar & 0xFF);
191 frame[0x9] = (bottom_bar >> 8);
192 frame[0xA] = (left_bar & 0xFF);
193 frame[0xB] = (left_bar >> 8);
194 frame[0xC] = (right_bar & 0xFF);
195 frame[0xD] = (right_bar >> 8);
196
197 r600_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame);
198
199 WREG32(offset+R600_HDMI_VIDEOINFOFRAME_0,
200 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
201 WREG32(offset+R600_HDMI_VIDEOINFOFRAME_1,
202 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
203 WREG32(offset+R600_HDMI_VIDEOINFOFRAME_2,
204 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
205 WREG32(offset+R600_HDMI_VIDEOINFOFRAME_3,
206 frame[0xC] | (frame[0xD] << 8));
207}
208
209/*
210 * build a Audio Info Frame
211 */
212static void r600_hdmi_audioinfoframe(
213 struct drm_encoder *encoder,
214 uint8_t channel_count,
215 uint8_t coding_type,
216 uint8_t sample_size,
217 uint8_t sample_frequency,
218 uint8_t format,
219 uint8_t channel_allocation,
220 uint8_t level_shift,
221 int downmix_inhibit
222)
223{
224 struct drm_device *dev = encoder->dev;
225 struct radeon_device *rdev = dev->dev_private;
226 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
227
228 uint8_t frame[11];
229
230 frame[0x0] = 0;
231 frame[0x1] = (channel_count & 0x7) | ((coding_type & 0xF) << 4);
232 frame[0x2] = (sample_size & 0x3) | ((sample_frequency & 0x7) << 2);
233 frame[0x3] = format;
234 frame[0x4] = channel_allocation;
235 frame[0x5] = ((level_shift & 0xF) << 3) | ((downmix_inhibit & 0x1) << 7);
236 frame[0x6] = 0;
237 frame[0x7] = 0;
238 frame[0x8] = 0;
239 frame[0x9] = 0;
240 frame[0xA] = 0;
241
242 r600_hdmi_infoframe_checksum(0x84, 0x01, 0x0A, frame);
243
244 WREG32(offset+R600_HDMI_AUDIOINFOFRAME_0,
245 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
246 WREG32(offset+R600_HDMI_AUDIOINFOFRAME_1,
247 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
248}
249
250/*
251 * test if audio buffer is filled enough to start playing
252 */
253static int r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
254{
255 struct drm_device *dev = encoder->dev;
256 struct radeon_device *rdev = dev->dev_private;
257 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
258
259 return (RREG32(offset+R600_HDMI_STATUS) & 0x10) != 0;
260}
261
262/*
263 * have buffer status changed since last call?
264 */
265int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
266{
267 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
268 int status, result;
269
270 if (!radeon_encoder->hdmi_offset)
271 return 0;
272
273 status = r600_hdmi_is_audio_buffer_filled(encoder);
274 result = radeon_encoder->hdmi_buffer_status != status;
275 radeon_encoder->hdmi_buffer_status = status;
276
277 return result;
278}
279
280/*
281 * write the audio workaround status to the hardware
282 */
283void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
284{
285 struct drm_device *dev = encoder->dev;
286 struct radeon_device *rdev = dev->dev_private;
287 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
288 uint32_t offset = radeon_encoder->hdmi_offset;
289
290 if (!offset)
291 return;
292
293 if (r600_hdmi_is_audio_buffer_filled(encoder)) {
294 /* disable audio workaround and start delivering of audio frames */
295 WREG32_P(offset+R600_HDMI_CNTL, 0x00000001, ~0x00001001);
296
297 } else if (radeon_encoder->hdmi_audio_workaround) {
298 /* enable audio workaround and start delivering of audio frames */
299 WREG32_P(offset+R600_HDMI_CNTL, 0x00001001, ~0x00001001);
300
301 } else {
302 /* disable audio workaround and stop delivering of audio frames */
303 WREG32_P(offset+R600_HDMI_CNTL, 0x00000000, ~0x00001001);
304 }
305}
306
307
308/*
309 * update the info frames with the data from the current display mode
310 */
311void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
312{
313 struct drm_device *dev = encoder->dev;
314 struct radeon_device *rdev = dev->dev_private;
315 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
316
317 if (!offset)
318 return;
319
320 r600_audio_set_clock(encoder, mode->clock);
321
322 WREG32(offset+R600_HDMI_UNKNOWN_0, 0x1000);
323 WREG32(offset+R600_HDMI_UNKNOWN_1, 0x0);
324 WREG32(offset+R600_HDMI_UNKNOWN_2, 0x1000);
325
326 r600_hdmi_update_ACR(encoder, mode->clock);
327
328 WREG32(offset+R600_HDMI_VIDEOCNTL, 0x13);
329
330 WREG32(offset+R600_HDMI_VERSION, 0x202);
331
332 r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0,
333 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
334
335 /* it's unknown what these bits do excatly, but it's indeed quite usefull for debugging */
336 WREG32(offset+R600_HDMI_AUDIO_DEBUG_0, 0x00FFFFFF);
337 WREG32(offset+R600_HDMI_AUDIO_DEBUG_1, 0x007FFFFF);
338 WREG32(offset+R600_HDMI_AUDIO_DEBUG_2, 0x00000001);
339 WREG32(offset+R600_HDMI_AUDIO_DEBUG_3, 0x00000001);
340
341 r600_hdmi_audio_workaround(encoder);
342
343 /* audio packets per line, does anyone know how to calc this ? */
344 WREG32_P(offset+R600_HDMI_CNTL, 0x00040000, ~0x001F0000);
345
346 /* update? reset? don't realy know */
347 WREG32_P(offset+R600_HDMI_CNTL, 0x14000000, ~0x14000000);
348}
349
350/*
351 * update settings with current parameters from audio engine
352 */
353void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
354 int channels,
355 int rate,
356 int bps,
357 uint8_t status_bits,
358 uint8_t category_code)
359{
360 struct drm_device *dev = encoder->dev;
361 struct radeon_device *rdev = dev->dev_private;
362 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
363
364 uint32_t iec;
365
366 if (!offset)
367 return;
368
369 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
370 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
371 channels, rate, bps);
372 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
373 (int)status_bits, (int)category_code);
374
375 iec = 0;
376 if (status_bits & AUDIO_STATUS_PROFESSIONAL)
377 iec |= 1 << 0;
378 if (status_bits & AUDIO_STATUS_NONAUDIO)
379 iec |= 1 << 1;
380 if (status_bits & AUDIO_STATUS_COPYRIGHT)
381 iec |= 1 << 2;
382 if (status_bits & AUDIO_STATUS_EMPHASIS)
383 iec |= 1 << 3;
384
385 iec |= category_code << 8;
386
387 switch (rate) {
388 case 32000: iec |= 0x3 << 24; break;
389 case 44100: iec |= 0x0 << 24; break;
390 case 88200: iec |= 0x8 << 24; break;
391 case 176400: iec |= 0xc << 24; break;
392 case 48000: iec |= 0x2 << 24; break;
393 case 96000: iec |= 0xa << 24; break;
394 case 192000: iec |= 0xe << 24; break;
395 }
396
397 WREG32(offset+R600_HDMI_IEC60958_1, iec);
398
399 iec = 0;
400 switch (bps) {
401 case 16: iec |= 0x2; break;
402 case 20: iec |= 0x3; break;
403 case 24: iec |= 0xb; break;
404 }
405 if (status_bits & AUDIO_STATUS_V)
406 iec |= 0x5 << 16;
407
408 WREG32_P(offset+R600_HDMI_IEC60958_2, iec, ~0x5000f);
409
410 /* 0x021 or 0x031 sets the audio frame length */
411 WREG32(offset+R600_HDMI_AUDIOCNTL, 0x31);
412 r600_hdmi_audioinfoframe(encoder, channels-1, 0, 0, 0, 0, 0, 0, 0);
413
414 r600_hdmi_audio_workaround(encoder);
415
416 /* update? reset? don't realy know */
417 WREG32_P(offset+R600_HDMI_CNTL, 0x04000000, ~0x04000000);
418}
419
420/*
421 * enable/disable the HDMI engine
422 */
423void r600_hdmi_enable(struct drm_encoder *encoder, int enable)
424{
425 struct drm_device *dev = encoder->dev;
426 struct radeon_device *rdev = dev->dev_private;
427 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
428 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
429
430 if (!offset)
431 return;
432
433 DRM_DEBUG("%s HDMI interface @ 0x%04X\n", enable ? "Enabling" : "Disabling", offset);
434
435 /* some version of atombios ignore the enable HDMI flag
436 * so enabling/disabling HDMI was moved here for TMDS1+2 */
437 switch (radeon_encoder->encoder_id) {
438 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
439 WREG32_P(AVIVO_TMDSA_CNTL, enable ? 0x4 : 0x0, ~0x4);
440 WREG32(offset+R600_HDMI_ENABLE, enable ? 0x101 : 0x0);
441 break;
442
443 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
444 WREG32_P(AVIVO_LVTMA_CNTL, enable ? 0x4 : 0x0, ~0x4);
445 WREG32(offset+R600_HDMI_ENABLE, enable ? 0x105 : 0x0);
446 break;
447
448 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
449 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
450 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
451 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
452 /* This part is doubtfull in my opinion */
453 WREG32(offset+R600_HDMI_ENABLE, enable ? 0x110 : 0x0);
454 break;
455
456 default:
457 DRM_ERROR("unknown HDMI output type\n");
458 break;
459 }
460}
461
462/*
463 * determin at which register offset the HDMI encoder is
464 */
465void r600_hdmi_init(struct drm_encoder *encoder)
466{
467 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
468
469 switch (radeon_encoder->encoder_id) {
470 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
471 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
472 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
473 radeon_encoder->hdmi_offset = R600_HDMI_TMDS1;
474 break;
475
476 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
477 switch (r600_audio_tmds_index(encoder)) {
478 case 0:
479 radeon_encoder->hdmi_offset = R600_HDMI_TMDS1;
480 break;
481 case 1:
482 radeon_encoder->hdmi_offset = R600_HDMI_TMDS2;
483 break;
484 default:
485 radeon_encoder->hdmi_offset = 0;
486 break;
487 }
488 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
489 radeon_encoder->hdmi_offset = R600_HDMI_TMDS2;
490 break;
491
492 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
493 radeon_encoder->hdmi_offset = R600_HDMI_DIG;
494 break;
495
496 default:
497 radeon_encoder->hdmi_offset = 0;
498 break;
499 }
500
501 DRM_DEBUG("using HDMI engine at offset 0x%04X for encoder 0x%x\n",
502 radeon_encoder->hdmi_offset, radeon_encoder->encoder_id);
503
504 /* TODO: make this configureable */
505 radeon_encoder->hdmi_audio_workaround = 0;
506}
diff --git a/drivers/gpu/drm/radeon/r600_reg.h b/drivers/gpu/drm/radeon/r600_reg.h
index e2d1f5f33f7e..d0e28ffdeda9 100644
--- a/drivers/gpu/drm/radeon/r600_reg.h
+++ b/drivers/gpu/drm/radeon/r600_reg.h
@@ -110,5 +110,79 @@
110#define R600_BIOS_6_SCRATCH 0x173c 110#define R600_BIOS_6_SCRATCH 0x173c
111#define R600_BIOS_7_SCRATCH 0x1740 111#define R600_BIOS_7_SCRATCH 0x1740
112 112
113/* Audio, these regs were reverse enginered,
114 * so the chance is high that the naming is wrong
115 * R6xx+ ??? */
116
117/* Audio clocks */
118#define R600_AUDIO_PLL1_MUL 0x0514
119#define R600_AUDIO_PLL1_DIV 0x0518
120#define R600_AUDIO_PLL2_MUL 0x0524
121#define R600_AUDIO_PLL2_DIV 0x0528
122#define R600_AUDIO_CLK_SRCSEL 0x0534
123
124/* Audio general */
125#define R600_AUDIO_ENABLE 0x7300
126#define R600_AUDIO_TIMING 0x7344
127
128/* Audio params */
129#define R600_AUDIO_VENDOR_ID 0x7380
130#define R600_AUDIO_REVISION_ID 0x7384
131#define R600_AUDIO_ROOT_NODE_COUNT 0x7388
132#define R600_AUDIO_NID1_NODE_COUNT 0x738c
133#define R600_AUDIO_NID1_TYPE 0x7390
134#define R600_AUDIO_SUPPORTED_SIZE_RATE 0x7394
135#define R600_AUDIO_SUPPORTED_CODEC 0x7398
136#define R600_AUDIO_SUPPORTED_POWER_STATES 0x739c
137#define R600_AUDIO_NID2_CAPS 0x73a0
138#define R600_AUDIO_NID3_CAPS 0x73a4
139#define R600_AUDIO_NID3_PIN_CAPS 0x73a8
140
141/* Audio conn list */
142#define R600_AUDIO_CONN_LIST_LEN 0x73ac
143#define R600_AUDIO_CONN_LIST 0x73b0
144
145/* Audio verbs */
146#define R600_AUDIO_RATE_BPS_CHANNEL 0x73c0
147#define R600_AUDIO_PLAYING 0x73c4
148#define R600_AUDIO_IMPLEMENTATION_ID 0x73c8
149#define R600_AUDIO_CONFIG_DEFAULT 0x73cc
150#define R600_AUDIO_PIN_SENSE 0x73d0
151#define R600_AUDIO_PIN_WIDGET_CNTL 0x73d4
152#define R600_AUDIO_STATUS_BITS 0x73d8
153
154/* HDMI base register addresses */
155#define R600_HDMI_TMDS1 0x7400
156#define R600_HDMI_TMDS2 0x7700
157#define R600_HDMI_DIG 0x7800
158
159/* HDMI registers */
160#define R600_HDMI_ENABLE 0x00
161#define R600_HDMI_STATUS 0x04
162#define R600_HDMI_CNTL 0x08
163#define R600_HDMI_UNKNOWN_0 0x0C
164#define R600_HDMI_AUDIOCNTL 0x10
165#define R600_HDMI_VIDEOCNTL 0x14
166#define R600_HDMI_VERSION 0x18
167#define R600_HDMI_UNKNOWN_1 0x28
168#define R600_HDMI_VIDEOINFOFRAME_0 0x54
169#define R600_HDMI_VIDEOINFOFRAME_1 0x58
170#define R600_HDMI_VIDEOINFOFRAME_2 0x5c
171#define R600_HDMI_VIDEOINFOFRAME_3 0x60
172#define R600_HDMI_32kHz_CTS 0xac
173#define R600_HDMI_32kHz_N 0xb0
174#define R600_HDMI_44_1kHz_CTS 0xb4
175#define R600_HDMI_44_1kHz_N 0xb8
176#define R600_HDMI_48kHz_CTS 0xbc
177#define R600_HDMI_48kHz_N 0xc0
178#define R600_HDMI_AUDIOINFOFRAME_0 0xcc
179#define R600_HDMI_AUDIOINFOFRAME_1 0xd0
180#define R600_HDMI_IEC60958_1 0xd4
181#define R600_HDMI_IEC60958_2 0xd8
182#define R600_HDMI_UNKNOWN_2 0xdc
183#define R600_HDMI_AUDIO_DEBUG_0 0xe0
184#define R600_HDMI_AUDIO_DEBUG_1 0xe4
185#define R600_HDMI_AUDIO_DEBUG_2 0xe8
186#define R600_HDMI_AUDIO_DEBUG_3 0xec
113 187
114#endif 188#endif
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index c938bb54123c..cd650fd3964e 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -89,6 +89,7 @@ extern int radeon_testing;
89extern int radeon_connector_table; 89extern int radeon_connector_table;
90extern int radeon_tv; 90extern int radeon_tv;
91extern int radeon_new_pll; 91extern int radeon_new_pll;
92extern int radeon_audio;
92 93
93/* 94/*
94 * Copy from radeon_drv.h so we don't have to include both and have conflicting 95 * Copy from radeon_drv.h so we don't have to include both and have conflicting
@@ -814,6 +815,14 @@ struct radeon_device {
814 struct r600_ih ih; /* r6/700 interrupt ring */ 815 struct r600_ih ih; /* r6/700 interrupt ring */
815 struct workqueue_struct *wq; 816 struct workqueue_struct *wq;
816 struct work_struct hotplug_work; 817 struct work_struct hotplug_work;
818
819 /* audio stuff */
820 struct timer_list audio_timer;
821 int audio_channels;
822 int audio_rate;
823 int audio_bits_per_sample;
824 uint8_t audio_status_bits;
825 uint8_t audio_category_code;
817}; 826};
818 827
819int radeon_device_init(struct radeon_device *rdev, 828int radeon_device_init(struct radeon_device *rdev,
@@ -1016,6 +1025,7 @@ extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1016extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 1025extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1017extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 1026extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1018extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 1027extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1028extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1019 1029
1020/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ 1030/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1021struct r100_mc_save { 1031struct r100_mc_save {
@@ -1146,6 +1156,21 @@ extern void r600_irq_fini(struct radeon_device *rdev);
1146extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 1156extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1147extern int r600_irq_set(struct radeon_device *rdev); 1157extern int r600_irq_set(struct radeon_device *rdev);
1148 1158
1159extern int r600_audio_init(struct radeon_device *rdev);
1160extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1161extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1162extern void r600_audio_fini(struct radeon_device *rdev);
1163extern void r600_hdmi_init(struct drm_encoder *encoder);
1164extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable);
1165extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1166extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1167extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
1168 int channels,
1169 int rate,
1170 int bps,
1171 uint8_t status_bits,
1172 uint8_t category_code);
1173
1149#include "radeon_object.h" 1174#include "radeon_object.h"
1150 1175
1151#endif 1176#endif
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index c5c45e626d74..dbd56ef82f9c 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -87,6 +87,7 @@ int radeon_testing = 0;
87int radeon_connector_table = 0; 87int radeon_connector_table = 0;
88int radeon_tv = 1; 88int radeon_tv = 1;
89int radeon_new_pll = 1; 89int radeon_new_pll = 1;
90int radeon_audio = 1;
90 91
91MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 92MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
92module_param_named(no_wb, radeon_no_wb, int, 0444); 93module_param_named(no_wb, radeon_no_wb, int, 0444);
@@ -124,6 +125,9 @@ module_param_named(tv, radeon_tv, int, 0444);
124MODULE_PARM_DESC(new_pll, "Select new PLL code for AVIVO chips"); 125MODULE_PARM_DESC(new_pll, "Select new PLL code for AVIVO chips");
125module_param_named(new_pll, radeon_new_pll, int, 0444); 126module_param_named(new_pll, radeon_new_pll, int, 0444);
126 127
128MODULE_PARM_DESC(audio, "Audio enable (0 = disable)");
129module_param_named(audio, radeon_audio, int, 0444);
130
127static int radeon_suspend(struct drm_device *dev, pm_message_t state) 131static int radeon_suspend(struct drm_device *dev, pm_message_t state)
128{ 132{
129 drm_radeon_private_t *dev_priv = dev->dev_private; 133 drm_radeon_private_t *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index b4f23ec93201..0d1d908e5225 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -438,6 +438,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
438 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 438 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
439 union lvds_encoder_control args; 439 union lvds_encoder_control args;
440 int index = 0; 440 int index = 0;
441 int hdmi_detected = 0;
441 uint8_t frev, crev; 442 uint8_t frev, crev;
442 struct radeon_encoder_atom_dig *dig; 443 struct radeon_encoder_atom_dig *dig;
443 struct drm_connector *connector; 444 struct drm_connector *connector;
@@ -458,6 +459,9 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
458 if (!radeon_connector->con_priv) 459 if (!radeon_connector->con_priv)
459 return; 460 return;
460 461
462 if (drm_detect_hdmi_monitor(radeon_connector->edid))
463 hdmi_detected = 1;
464
461 dig_connector = radeon_connector->con_priv; 465 dig_connector = radeon_connector->con_priv;
462 466
463 memset(&args, 0, sizeof(args)); 467 memset(&args, 0, sizeof(args));
@@ -487,7 +491,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
487 case 1: 491 case 1:
488 args.v1.ucMisc = 0; 492 args.v1.ucMisc = 0;
489 args.v1.ucAction = action; 493 args.v1.ucAction = action;
490 if (drm_detect_hdmi_monitor(radeon_connector->edid)) 494 if (hdmi_detected)
491 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 495 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
492 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 496 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
493 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 497 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
@@ -512,7 +516,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
512 if (dig->coherent_mode) 516 if (dig->coherent_mode)
513 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 517 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
514 } 518 }
515 if (drm_detect_hdmi_monitor(radeon_connector->edid)) 519 if (hdmi_detected)
516 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 520 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
517 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 521 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
518 args.v2.ucTruncate = 0; 522 args.v2.ucTruncate = 0;
@@ -552,7 +556,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
552 } 556 }
553 557
554 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 558 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
555 559 r600_hdmi_enable(encoder, hdmi_detected);
556} 560}
557 561
558int 562int
@@ -893,7 +897,6 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
893 } 897 }
894 898
895 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 899 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
896
897} 900}
898 901
899static void 902static void
@@ -1162,7 +1165,6 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1162 } 1165 }
1163 1166
1164 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1167 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1165
1166} 1168}
1167 1169
1168static void 1170static void
@@ -1265,6 +1267,8 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1265 break; 1267 break;
1266 } 1268 }
1267 atombios_apply_encoder_quirks(encoder, adjusted_mode); 1269 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1270
1271 r600_hdmi_setmode(encoder, adjusted_mode);
1268} 1272}
1269 1273
1270static bool 1274static bool
@@ -1510,4 +1514,6 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
1510 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 1514 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1511 break; 1515 break;
1512 } 1516 }
1517
1518 r600_hdmi_init(encoder);
1513} 1519}
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index 2944486871b0..60df2d7e7e4c 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -66,8 +66,9 @@ int radeon_gem_object_create(struct radeon_device *rdev, int size,
66 } 66 }
67 r = radeon_bo_create(rdev, gobj, size, kernel, initial_domain, &robj); 67 r = radeon_bo_create(rdev, gobj, size, kernel, initial_domain, &robj);
68 if (r) { 68 if (r) {
69 DRM_ERROR("Failed to allocate GEM object (%d, %d, %u)\n", 69 if (r != -ERESTARTSYS)
70 size, initial_domain, alignment); 70 DRM_ERROR("Failed to allocate GEM object (%d, %d, %u, %d)\n",
71 size, initial_domain, alignment, r);
71 mutex_lock(&rdev->ddev->struct_mutex); 72 mutex_lock(&rdev->ddev->struct_mutex);
72 drm_gem_object_unreference(gobj); 73 drm_gem_object_unreference(gobj);
73 mutex_unlock(&rdev->ddev->struct_mutex); 74 mutex_unlock(&rdev->ddev->struct_mutex);
@@ -350,9 +351,10 @@ int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
350 rbo = gobj->driver_private; 351 rbo = gobj->driver_private;
351 r = radeon_bo_reserve(rbo, false); 352 r = radeon_bo_reserve(rbo, false);
352 if (unlikely(r != 0)) 353 if (unlikely(r != 0))
353 return r; 354 goto out;
354 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); 355 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch);
355 radeon_bo_unreserve(rbo); 356 radeon_bo_unreserve(rbo);
357out:
356 mutex_lock(&dev->struct_mutex); 358 mutex_lock(&dev->struct_mutex);
357 drm_gem_object_unreference(gobj); 359 drm_gem_object_unreference(gobj);
358 mutex_unlock(&dev->struct_mutex); 360 mutex_unlock(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 44d4b652ea12..3dcbe130c422 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -334,6 +334,9 @@ struct radeon_encoder {
334 enum radeon_rmx_type rmx_type; 334 enum radeon_rmx_type rmx_type;
335 struct drm_display_mode native_mode; 335 struct drm_display_mode native_mode;
336 void *enc_priv; 336 void *enc_priv;
337 int hdmi_offset;
338 int hdmi_audio_workaround;
339 int hdmi_buffer_status;
337}; 340};
338 341
339struct radeon_connector_atom_dig { 342struct radeon_connector_atom_dig {
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 544e18ffaf22..d9ffe1f56e8f 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -56,6 +56,13 @@ static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
56 kfree(bo); 56 kfree(bo);
57} 57}
58 58
59bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
60{
61 if (bo->destroy == &radeon_ttm_bo_destroy)
62 return true;
63 return false;
64}
65
59void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) 66void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
60{ 67{
61 u32 c = 0; 68 u32 c = 0;
@@ -71,6 +78,8 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
71 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 78 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
72 if (domain & RADEON_GEM_DOMAIN_CPU) 79 if (domain & RADEON_GEM_DOMAIN_CPU)
73 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 80 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
81 if (!c)
82 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
74 rbo->placement.num_placement = c; 83 rbo->placement.num_placement = c;
75 rbo->placement.num_busy_placement = c; 84 rbo->placement.num_busy_placement = c;
76} 85}
@@ -481,14 +490,20 @@ int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
481} 490}
482 491
483void radeon_bo_move_notify(struct ttm_buffer_object *bo, 492void radeon_bo_move_notify(struct ttm_buffer_object *bo,
484 struct ttm_mem_reg *mem) 493 struct ttm_mem_reg *mem)
485{ 494{
486 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); 495 struct radeon_bo *rbo;
496 if (!radeon_ttm_bo_is_radeon_bo(bo))
497 return;
498 rbo = container_of(bo, struct radeon_bo, tbo);
487 radeon_bo_check_tiling(rbo, 0, 1); 499 radeon_bo_check_tiling(rbo, 0, 1);
488} 500}
489 501
490void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 502void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
491{ 503{
492 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); 504 struct radeon_bo *rbo;
505 if (!radeon_ttm_bo_is_radeon_bo(bo))
506 return;
507 rbo = container_of(bo, struct radeon_bo, tbo);
493 radeon_bo_check_tiling(rbo, 0, 0); 508 radeon_bo_check_tiling(rbo, 0, 0);
494} 509}
diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h
index f6b69c2c0d00..a02f18011ad1 100644
--- a/drivers/gpu/drm/radeon/radeon_object.h
+++ b/drivers/gpu/drm/radeon/radeon_object.h
@@ -59,19 +59,17 @@ static inline unsigned radeon_mem_type_to_domain(u32 mem_type)
59 * 59 *
60 * Returns: 60 * Returns:
61 * -EBUSY: buffer is busy and @no_wait is true 61 * -EBUSY: buffer is busy and @no_wait is true
62 * -ERESTART: A wait for the buffer to become unreserved was interrupted by 62 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
63 * a signal. Release all buffer reservations and return to user-space. 63 * a signal. Release all buffer reservations and return to user-space.
64 */ 64 */
65static inline int radeon_bo_reserve(struct radeon_bo *bo, bool no_wait) 65static inline int radeon_bo_reserve(struct radeon_bo *bo, bool no_wait)
66{ 66{
67 int r; 67 int r;
68 68
69retry:
70 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0); 69 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
71 if (unlikely(r != 0)) { 70 if (unlikely(r != 0)) {
72 if (r == -ERESTART) 71 if (r != -ERESTARTSYS)
73 goto retry; 72 dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
74 dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
75 return r; 73 return r;
76 } 74 }
77 return 0; 75 return 0;
@@ -125,12 +123,10 @@ static inline int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type,
125{ 123{
126 int r; 124 int r;
127 125
128retry:
129 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0); 126 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
130 if (unlikely(r != 0)) { 127 if (unlikely(r != 0)) {
131 if (r == -ERESTART) 128 if (r != -ERESTARTSYS)
132 goto retry; 129 dev_err(bo->rdev->dev, "%p reserve failed for wait\n", bo);
133 dev_err(bo->rdev->dev, "%p reserve failed for wait\n", bo);
134 return r; 130 return r;
135 } 131 }
136 spin_lock(&bo->tbo.lock); 132 spin_lock(&bo->tbo.lock);
@@ -140,8 +136,6 @@ retry:
140 r = ttm_bo_wait(&bo->tbo, true, true, no_wait); 136 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
141 spin_unlock(&bo->tbo.lock); 137 spin_unlock(&bo->tbo.lock);
142 ttm_bo_unreserve(&bo->tbo); 138 ttm_bo_unreserve(&bo->tbo);
143 if (unlikely(r == -ERESTART))
144 goto retry;
145 return r; 139 return r;
146} 140}
147 141
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 34b08d307c81..8bce64cdc320 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -44,8 +44,11 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
44 struct drm_device *dev = node->minor->dev; 44 struct drm_device *dev = node->minor->dev;
45 struct radeon_device *rdev = dev->dev_private; 45 struct radeon_device *rdev = dev->dev_private;
46 46
47 seq_printf(m, "engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); 47 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
48 seq_printf(m, "memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); 48 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
49 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
50 if (rdev->asic->get_memory_clock)
51 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
49 52
50 return 0; 53 return 0;
51} 54}
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 5a19d529d1c0..d7fd160cc671 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -200,7 +200,19 @@ static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
200static void radeon_evict_flags(struct ttm_buffer_object *bo, 200static void radeon_evict_flags(struct ttm_buffer_object *bo,
201 struct ttm_placement *placement) 201 struct ttm_placement *placement)
202{ 202{
203 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); 203 struct radeon_bo *rbo;
204 static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
205
206 if (!radeon_ttm_bo_is_radeon_bo(bo)) {
207 placement->fpfn = 0;
208 placement->lpfn = 0;
209 placement->placement = &placements;
210 placement->busy_placement = &placements;
211 placement->num_placement = 1;
212 placement->num_busy_placement = 1;
213 return;
214 }
215 rbo = container_of(bo, struct radeon_bo, tbo);
204 switch (bo->mem.mem_type) { 216 switch (bo->mem.mem_type) {
205 case TTM_PL_VRAM: 217 case TTM_PL_VRAM:
206 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 218 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index c1fcdddb6be6..368415df5f3a 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -497,6 +497,8 @@ int rs400_init(struct radeon_device *rdev)
497 497
498 /* Initialize clocks */ 498 /* Initialize clocks */
499 radeon_get_clock_info(rdev->ddev); 499 radeon_get_clock_info(rdev->ddev);
500 /* Initialize power management */
501 radeon_pm_init(rdev);
500 /* Get vram informations */ 502 /* Get vram informations */
501 rs400_vram_info(rdev); 503 rs400_vram_info(rdev);
502 /* Initialize memory controller (also test AGP) */ 504 /* Initialize memory controller (also test AGP) */
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index fbb0357f1ec3..3bcb66e52786 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -892,6 +892,14 @@ static int rv770_startup(struct radeon_device *rdev)
892 } 892 }
893 rv770_gpu_init(rdev); 893 rv770_gpu_init(rdev);
894 894
895 if (!rdev->r600_blit.shader_obj) {
896 r = r600_blit_init(rdev);
897 if (r) {
898 DRM_ERROR("radeon: failed blitter (%d).\n", r);
899 return r;
900 }
901 }
902
895 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 903 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
896 if (unlikely(r != 0)) 904 if (unlikely(r != 0))
897 return r; 905 return r;
@@ -1051,12 +1059,6 @@ int rv770_init(struct radeon_device *rdev)
1051 if (r) 1059 if (r)
1052 return r; 1060 return r;
1053 1061
1054 r = r600_blit_init(rdev);
1055 if (r) {
1056 DRM_ERROR("radeon: failed blitter (%d).\n", r);
1057 return r;
1058 }
1059
1060 rdev->accel_working = true; 1062 rdev->accel_working = true;
1061 r = rv770_startup(rdev); 1063 r = rv770_startup(rdev);
1062 if (r) { 1064 if (r) {
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 1fbb2eea5e88..2920f9a279e1 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -71,34 +71,34 @@ static inline int ttm_mem_type_from_flags(uint32_t flags, uint32_t *mem_type)
71 return -EINVAL; 71 return -EINVAL;
72} 72}
73 73
74static void ttm_mem_type_manager_debug(struct ttm_bo_global *glob, 74static void ttm_mem_type_debug(struct ttm_bo_device *bdev, int mem_type)
75 struct ttm_mem_type_manager *man)
76{ 75{
76 struct ttm_mem_type_manager *man = &bdev->man[mem_type];
77
77 printk(KERN_ERR TTM_PFX " has_type: %d\n", man->has_type); 78 printk(KERN_ERR TTM_PFX " has_type: %d\n", man->has_type);
78 printk(KERN_ERR TTM_PFX " use_type: %d\n", man->use_type); 79 printk(KERN_ERR TTM_PFX " use_type: %d\n", man->use_type);
79 printk(KERN_ERR TTM_PFX " flags: 0x%08X\n", man->flags); 80 printk(KERN_ERR TTM_PFX " flags: 0x%08X\n", man->flags);
80 printk(KERN_ERR TTM_PFX " gpu_offset: 0x%08lX\n", man->gpu_offset); 81 printk(KERN_ERR TTM_PFX " gpu_offset: 0x%08lX\n", man->gpu_offset);
81 printk(KERN_ERR TTM_PFX " io_offset: 0x%08lX\n", man->io_offset); 82 printk(KERN_ERR TTM_PFX " io_offset: 0x%08lX\n", man->io_offset);
82 printk(KERN_ERR TTM_PFX " io_size: %ld\n", man->io_size); 83 printk(KERN_ERR TTM_PFX " io_size: %ld\n", man->io_size);
83 printk(KERN_ERR TTM_PFX " size: %ld\n", (unsigned long)man->size); 84 printk(KERN_ERR TTM_PFX " size: %llu\n", man->size);
84 printk(KERN_ERR TTM_PFX " available_caching: 0x%08X\n", 85 printk(KERN_ERR TTM_PFX " available_caching: 0x%08X\n",
85 man->available_caching); 86 man->available_caching);
86 printk(KERN_ERR TTM_PFX " default_caching: 0x%08X\n", 87 printk(KERN_ERR TTM_PFX " default_caching: 0x%08X\n",
87 man->default_caching); 88 man->default_caching);
88 spin_lock(&glob->lru_lock); 89 if (mem_type != TTM_PL_SYSTEM) {
89 drm_mm_debug_table(&man->manager, TTM_PFX); 90 spin_lock(&bdev->glob->lru_lock);
90 spin_unlock(&glob->lru_lock); 91 drm_mm_debug_table(&man->manager, TTM_PFX);
92 spin_unlock(&bdev->glob->lru_lock);
93 }
91} 94}
92 95
93static void ttm_bo_mem_space_debug(struct ttm_buffer_object *bo, 96static void ttm_bo_mem_space_debug(struct ttm_buffer_object *bo,
94 struct ttm_placement *placement) 97 struct ttm_placement *placement)
95{ 98{
96 struct ttm_bo_device *bdev = bo->bdev;
97 struct ttm_bo_global *glob = bo->glob;
98 struct ttm_mem_type_manager *man;
99 int i, ret, mem_type; 99 int i, ret, mem_type;
100 100
101 printk(KERN_ERR TTM_PFX "No space for %p (%ld pages, %ldK, %ldM)\n", 101 printk(KERN_ERR TTM_PFX "No space for %p (%lu pages, %luK, %luM)\n",
102 bo, bo->mem.num_pages, bo->mem.size >> 10, 102 bo, bo->mem.num_pages, bo->mem.size >> 10,
103 bo->mem.size >> 20); 103 bo->mem.size >> 20);
104 for (i = 0; i < placement->num_placement; i++) { 104 for (i = 0; i < placement->num_placement; i++) {
@@ -106,10 +106,9 @@ static void ttm_bo_mem_space_debug(struct ttm_buffer_object *bo,
106 &mem_type); 106 &mem_type);
107 if (ret) 107 if (ret)
108 return; 108 return;
109 man = &bdev->man[mem_type];
110 printk(KERN_ERR TTM_PFX " placement[%d]=0x%08X (%d)\n", 109 printk(KERN_ERR TTM_PFX " placement[%d]=0x%08X (%d)\n",
111 i, placement->placement[i], mem_type); 110 i, placement->placement[i], mem_type);
112 ttm_mem_type_manager_debug(glob, man); 111 ttm_mem_type_debug(bo->bdev, mem_type);
113 } 112 }
114} 113}
115 114
@@ -465,6 +464,8 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all)
465 spin_unlock(&bo->lock); 464 spin_unlock(&bo->lock);
466 465
467 spin_lock(&glob->lru_lock); 466 spin_lock(&glob->lru_lock);
467 put_count = ttm_bo_del_from_lru(bo);
468
468 ret = ttm_bo_reserve_locked(bo, false, false, false, 0); 469 ret = ttm_bo_reserve_locked(bo, false, false, false, 0);
469 BUG_ON(ret); 470 BUG_ON(ret);
470 if (bo->ttm) 471 if (bo->ttm)
@@ -472,20 +473,19 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all)
472 473
473 if (!list_empty(&bo->ddestroy)) { 474 if (!list_empty(&bo->ddestroy)) {
474 list_del_init(&bo->ddestroy); 475 list_del_init(&bo->ddestroy);
475 kref_put(&bo->list_kref, ttm_bo_ref_bug); 476 ++put_count;
476 } 477 }
477 if (bo->mem.mm_node) { 478 if (bo->mem.mm_node) {
478 bo->mem.mm_node->private = NULL; 479 bo->mem.mm_node->private = NULL;
479 drm_mm_put_block(bo->mem.mm_node); 480 drm_mm_put_block(bo->mem.mm_node);
480 bo->mem.mm_node = NULL; 481 bo->mem.mm_node = NULL;
481 } 482 }
482 put_count = ttm_bo_del_from_lru(bo);
483 spin_unlock(&glob->lru_lock); 483 spin_unlock(&glob->lru_lock);
484 484
485 atomic_set(&bo->reserved, 0); 485 atomic_set(&bo->reserved, 0);
486 486
487 while (put_count--) 487 while (put_count--)
488 kref_put(&bo->list_kref, ttm_bo_release_list); 488 kref_put(&bo->list_kref, ttm_bo_ref_bug);
489 489
490 return 0; 490 return 0;
491 } 491 }
@@ -684,19 +684,45 @@ static int ttm_mem_evict_first(struct ttm_bo_device *bdev,
684 struct ttm_buffer_object *bo; 684 struct ttm_buffer_object *bo;
685 int ret, put_count = 0; 685 int ret, put_count = 0;
686 686
687retry:
687 spin_lock(&glob->lru_lock); 688 spin_lock(&glob->lru_lock);
689 if (list_empty(&man->lru)) {
690 spin_unlock(&glob->lru_lock);
691 return -EBUSY;
692 }
693
688 bo = list_first_entry(&man->lru, struct ttm_buffer_object, lru); 694 bo = list_first_entry(&man->lru, struct ttm_buffer_object, lru);
689 kref_get(&bo->list_kref); 695 kref_get(&bo->list_kref);
690 ret = ttm_bo_reserve_locked(bo, interruptible, no_wait, false, 0); 696
691 if (likely(ret == 0)) 697 ret = ttm_bo_reserve_locked(bo, false, true, false, 0);
692 put_count = ttm_bo_del_from_lru(bo); 698
699 if (unlikely(ret == -EBUSY)) {
700 spin_unlock(&glob->lru_lock);
701 if (likely(!no_wait))
702 ret = ttm_bo_wait_unreserved(bo, interruptible);
703
704 kref_put(&bo->list_kref, ttm_bo_release_list);
705
706 /**
707 * We *need* to retry after releasing the lru lock.
708 */
709
710 if (unlikely(ret != 0))
711 return ret;
712 goto retry;
713 }
714
715 put_count = ttm_bo_del_from_lru(bo);
693 spin_unlock(&glob->lru_lock); 716 spin_unlock(&glob->lru_lock);
694 if (unlikely(ret != 0)) 717
695 return ret; 718 BUG_ON(ret != 0);
719
696 while (put_count--) 720 while (put_count--)
697 kref_put(&bo->list_kref, ttm_bo_ref_bug); 721 kref_put(&bo->list_kref, ttm_bo_ref_bug);
722
698 ret = ttm_bo_evict(bo, interruptible, no_wait); 723 ret = ttm_bo_evict(bo, interruptible, no_wait);
699 ttm_bo_unreserve(bo); 724 ttm_bo_unreserve(bo);
725
700 kref_put(&bo->list_kref, ttm_bo_release_list); 726 kref_put(&bo->list_kref, ttm_bo_release_list);
701 return ret; 727 return ret;
702} 728}
@@ -849,7 +875,7 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
849 int i, ret; 875 int i, ret;
850 876
851 mem->mm_node = NULL; 877 mem->mm_node = NULL;
852 for (i = 0; i <= placement->num_placement; ++i) { 878 for (i = 0; i < placement->num_placement; ++i) {
853 ret = ttm_mem_type_from_flags(placement->placement[i], 879 ret = ttm_mem_type_from_flags(placement->placement[i],
854 &mem_type); 880 &mem_type);
855 if (ret) 881 if (ret)
@@ -900,8 +926,8 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
900 if (!type_found) 926 if (!type_found)
901 return -EINVAL; 927 return -EINVAL;
902 928
903 for (i = 0; i <= placement->num_busy_placement; ++i) { 929 for (i = 0; i < placement->num_busy_placement; ++i) {
904 ret = ttm_mem_type_from_flags(placement->placement[i], 930 ret = ttm_mem_type_from_flags(placement->busy_placement[i],
905 &mem_type); 931 &mem_type);
906 if (ret) 932 if (ret)
907 return ret; 933 return ret;
@@ -911,7 +937,7 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
911 if (!ttm_bo_mt_compatible(man, 937 if (!ttm_bo_mt_compatible(man,
912 bo->type == ttm_bo_type_user, 938 bo->type == ttm_bo_type_user,
913 mem_type, 939 mem_type,
914 placement->placement[i], 940 placement->busy_placement[i],
915 &cur_flags)) 941 &cur_flags))
916 continue; 942 continue;
917 943
@@ -921,7 +947,7 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo,
921 * Use the access and other non-mapping-related flag bits from 947 * Use the access and other non-mapping-related flag bits from
922 * the memory placement flags to the current flags 948 * the memory placement flags to the current flags
923 */ 949 */
924 ttm_flag_masked(&cur_flags, placement->placement[i], 950 ttm_flag_masked(&cur_flags, placement->busy_placement[i],
925 ~TTM_PL_MASK_MEMTYPE); 951 ~TTM_PL_MASK_MEMTYPE);
926 952
927 ret = ttm_bo_mem_force_space(bo, mem_type, placement, mem, 953 ret = ttm_bo_mem_force_space(bo, mem_type, placement, mem,
@@ -1115,6 +1141,7 @@ int ttm_bo_init(struct ttm_bo_device *bdev,
1115 bo->glob = bdev->glob; 1141 bo->glob = bdev->glob;
1116 bo->type = type; 1142 bo->type = type;
1117 bo->num_pages = num_pages; 1143 bo->num_pages = num_pages;
1144 bo->mem.size = num_pages << PAGE_SHIFT;
1118 bo->mem.mem_type = TTM_PL_SYSTEM; 1145 bo->mem.mem_type = TTM_PL_SYSTEM;
1119 bo->mem.num_pages = bo->num_pages; 1146 bo->mem.num_pages = bo->num_pages;
1120 bo->mem.mm_node = NULL; 1147 bo->mem.mm_node = NULL;
diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c
index 609a85a4d855..668dbe8b8dd3 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_vm.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c
@@ -320,7 +320,7 @@ ssize_t ttm_bo_io(struct ttm_bo_device *bdev, struct file *filp,
320 return -EFAULT; 320 return -EFAULT;
321 321
322 driver = bo->bdev->driver; 322 driver = bo->bdev->driver;
323 if (unlikely(driver->verify_access)) { 323 if (unlikely(!driver->verify_access)) {
324 ret = -EPERM; 324 ret = -EPERM;
325 goto out_unref; 325 goto out_unref;
326 } 326 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-08 14:42:22 -0500