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-rw-r--r--drivers/gpu/drm/i915/i915_gem.c39
1 files changed, 12 insertions, 27 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f7e9f2c2934c..50c75327d567 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -33,10 +33,10 @@
33 33
34#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 34#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
35 35
36static int 36static void
37i915_gem_object_set_domain(struct drm_gem_object *obj, 37i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
38 uint32_t read_domains, 38 uint32_t read_domains,
39 uint32_t write_domain); 39 uint32_t write_domain);
40static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); 40static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
41static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); 41static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
42static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); 42static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
@@ -1477,10 +1477,10 @@ i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
1477 * MI_FLUSH 1477 * MI_FLUSH
1478 * drm_agp_chipset_flush 1478 * drm_agp_chipset_flush
1479 */ 1479 */
1480static int 1480static void
1481i915_gem_object_set_domain(struct drm_gem_object *obj, 1481i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
1482 uint32_t read_domains, 1482 uint32_t read_domains,
1483 uint32_t write_domain) 1483 uint32_t write_domain)
1484{ 1484{
1485 struct drm_device *dev = obj->dev; 1485 struct drm_device *dev = obj->dev;
1486 struct drm_i915_gem_object *obj_priv = obj->driver_private; 1486 struct drm_i915_gem_object *obj_priv = obj->driver_private;
@@ -1540,7 +1540,6 @@ i915_gem_object_set_domain(struct drm_gem_object *obj,
1540 obj->read_domains, obj->write_domain, 1540 obj->read_domains, obj->write_domain,
1541 dev->invalidate_domains, dev->flush_domains); 1541 dev->invalidate_domains, dev->flush_domains);
1542#endif 1542#endif
1543 return 0;
1544} 1543}
1545 1544
1546/** 1545/**
@@ -2043,24 +2042,10 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
2043 for (i = 0; i < args->buffer_count; i++) { 2042 for (i = 0; i < args->buffer_count; i++) {
2044 struct drm_gem_object *obj = object_list[i]; 2043 struct drm_gem_object *obj = object_list[i];
2045 2044
2046 /* make sure all previous memory operations have passed */ 2045 /* Compute new gpu domains and update invalidate/flushing */
2047 ret = i915_gem_object_set_domain(obj, 2046 i915_gem_object_set_to_gpu_domain(obj,
2048 obj->pending_read_domains, 2047 obj->pending_read_domains,
2049 obj->pending_write_domain); 2048 obj->pending_write_domain);
2050 if (ret) {
2051 /* As we've partially updated domains on our buffers,
2052 * we have to emit the flush we've accumulated
2053 * before exiting, or we'll have broken the
2054 * active/flushing/inactive invariants.
2055 *
2056 * We'll potentially have some things marked as
2057 * being in write domains that they actually aren't,
2058 * but that should be merely a minor performance loss.
2059 */
2060 flush_domains = i915_gem_dev_set_domain(dev);
2061 (void)i915_add_request(dev, flush_domains);
2062 goto err;
2063 }
2064 } 2049 }
2065 2050
2066 i915_verify_inactive(dev, __FILE__, __LINE__); 2051 i915_verify_inactive(dev, __FILE__, __LINE__);