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-rw-r--r--drivers/clocksource/sh_cmt.c22
-rw-r--r--drivers/clocksource/sh_tmu.c20
-rw-r--r--drivers/input/serio/Kconfig3
-rw-r--r--drivers/mmc/host/sh_mmcif.c125
-rw-r--r--drivers/sh/intc.c12
-rw-r--r--drivers/usb/gadget/m66592-udc.h22
-rw-r--r--drivers/usb/gadget/r8a66597-udc.c4
-rw-r--r--drivers/usb/gadget/r8a66597-udc.h24
-rw-r--r--drivers/usb/host/r8a66597-hcd.c4
-rw-r--r--drivers/usb/host/r8a66597.h26
-rw-r--r--drivers/video/sh_mobile_lcdcfb.c6
11 files changed, 126 insertions, 142 deletions
diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
index f6677cb19789..f3d3898898ed 100644
--- a/drivers/clocksource/sh_cmt.c
+++ b/drivers/clocksource/sh_cmt.c
@@ -412,18 +412,10 @@ static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
412static int sh_cmt_clocksource_enable(struct clocksource *cs) 412static int sh_cmt_clocksource_enable(struct clocksource *cs)
413{ 413{
414 struct sh_cmt_priv *p = cs_to_sh_cmt(cs); 414 struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
415 int ret;
416 415
417 p->total_cycles = 0; 416 p->total_cycles = 0;
418 417
419 ret = sh_cmt_start(p, FLAG_CLOCKSOURCE); 418 return sh_cmt_start(p, FLAG_CLOCKSOURCE);
420 if (ret)
421 return ret;
422
423 /* TODO: calculate good shift from rate and counter bit width */
424 cs->shift = 0;
425 cs->mult = clocksource_hz2mult(p->rate, cs->shift);
426 return 0;
427} 419}
428 420
429static void sh_cmt_clocksource_disable(struct clocksource *cs) 421static void sh_cmt_clocksource_disable(struct clocksource *cs)
@@ -450,8 +442,20 @@ static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
450 cs->resume = sh_cmt_clocksource_resume; 442 cs->resume = sh_cmt_clocksource_resume;
451 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); 443 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
452 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; 444 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
445
446 /* clk_get_rate() needs an enabled clock */
447 clk_enable(p->clk);
448 p->rate = clk_get_rate(p->clk) / (p->width == 16) ? 512 : 8;
449 clk_disable(p->clk);
450
451 /* TODO: calculate good shift from rate and counter bit width */
452 cs->shift = 10;
453 cs->mult = clocksource_hz2mult(p->rate, cs->shift);
454
453 dev_info(&p->pdev->dev, "used as clock source\n"); 455 dev_info(&p->pdev->dev, "used as clock source\n");
456
454 clocksource_register(cs); 457 clocksource_register(cs);
458
455 return 0; 459 return 0;
456} 460}
457 461
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
index 8e44e14ec4c2..de715901b82a 100644
--- a/drivers/clocksource/sh_tmu.c
+++ b/drivers/clocksource/sh_tmu.c
@@ -199,16 +199,8 @@ static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
199static int sh_tmu_clocksource_enable(struct clocksource *cs) 199static int sh_tmu_clocksource_enable(struct clocksource *cs)
200{ 200{
201 struct sh_tmu_priv *p = cs_to_sh_tmu(cs); 201 struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
202 int ret;
203
204 ret = sh_tmu_enable(p);
205 if (ret)
206 return ret;
207 202
208 /* TODO: calculate good shift from rate and counter bit width */ 203 return sh_tmu_enable(p);
209 cs->shift = 10;
210 cs->mult = clocksource_hz2mult(p->rate, cs->shift);
211 return 0;
212} 204}
213 205
214static void sh_tmu_clocksource_disable(struct clocksource *cs) 206static void sh_tmu_clocksource_disable(struct clocksource *cs)
@@ -228,6 +220,16 @@ static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
228 cs->disable = sh_tmu_clocksource_disable; 220 cs->disable = sh_tmu_clocksource_disable;
229 cs->mask = CLOCKSOURCE_MASK(32); 221 cs->mask = CLOCKSOURCE_MASK(32);
230 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; 222 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
223
224 /* clk_get_rate() needs an enabled clock */
225 clk_enable(p->clk);
226 /* channel will be configured at parent clock / 4 */
227 p->rate = clk_get_rate(p->clk) / 4;
228 clk_disable(p->clk);
229 /* TODO: calculate good shift from rate and counter bit width */
230 cs->shift = 10;
231 cs->mult = clocksource_hz2mult(p->rate, cs->shift);
232
231 dev_info(&p->pdev->dev, "used as clock source\n"); 233 dev_info(&p->pdev->dev, "used as clock source\n");
232 clocksource_register(cs); 234 clocksource_register(cs);
233 return 0; 235 return 0;
diff --git a/drivers/input/serio/Kconfig b/drivers/input/serio/Kconfig
index f34f1dbeb577..3bfe8fafc6ad 100644
--- a/drivers/input/serio/Kconfig
+++ b/drivers/input/serio/Kconfig
@@ -21,7 +21,8 @@ if SERIO
21config SERIO_I8042 21config SERIO_I8042
22 tristate "i8042 PC Keyboard controller" if EMBEDDED || !X86 22 tristate "i8042 PC Keyboard controller" if EMBEDDED || !X86
23 default y 23 default y
24 depends on !PARISC && (!ARM || ARCH_SHARK || FOOTBRIDGE_HOST) && !M68K && !BLACKFIN 24 depends on !PARISC && (!ARM || ARCH_SHARK || FOOTBRIDGE_HOST) && \
25 (!SUPERH || SH_CAYMAN) && !M68K && !BLACKFIN
25 help 26 help
26 i8042 is the chip over which the standard AT keyboard and PS/2 27 i8042 is the chip over which the standard AT keyboard and PS/2
27 mouse are connected to the computer. If you use these devices, 28 mouse are connected to the computer. If you use these devices,
diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c
index eb97830c0344..5d3f824bb5a3 100644
--- a/drivers/mmc/host/sh_mmcif.c
+++ b/drivers/mmc/host/sh_mmcif.c
@@ -30,25 +30,6 @@
30#define DRIVER_NAME "sh_mmcif" 30#define DRIVER_NAME "sh_mmcif"
31#define DRIVER_VERSION "2010-04-28" 31#define DRIVER_VERSION "2010-04-28"
32 32
33#define MMCIF_CE_CMD_SET 0x00000000
34#define MMCIF_CE_ARG 0x00000008
35#define MMCIF_CE_ARG_CMD12 0x0000000C
36#define MMCIF_CE_CMD_CTRL 0x00000010
37#define MMCIF_CE_BLOCK_SET 0x00000014
38#define MMCIF_CE_CLK_CTRL 0x00000018
39#define MMCIF_CE_BUF_ACC 0x0000001C
40#define MMCIF_CE_RESP3 0x00000020
41#define MMCIF_CE_RESP2 0x00000024
42#define MMCIF_CE_RESP1 0x00000028
43#define MMCIF_CE_RESP0 0x0000002C
44#define MMCIF_CE_RESP_CMD12 0x00000030
45#define MMCIF_CE_DATA 0x00000034
46#define MMCIF_CE_INT 0x00000040
47#define MMCIF_CE_INT_MASK 0x00000044
48#define MMCIF_CE_HOST_STS1 0x00000048
49#define MMCIF_CE_HOST_STS2 0x0000004C
50#define MMCIF_CE_VERSION 0x0000007C
51
52/* CE_CMD_SET */ 33/* CE_CMD_SET */
53#define CMD_MASK 0x3f000000 34#define CMD_MASK 0x3f000000
54#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 35#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
@@ -207,27 +188,17 @@ struct sh_mmcif_host {
207 wait_queue_head_t intr_wait; 188 wait_queue_head_t intr_wait;
208}; 189};
209 190
210static inline u32 sh_mmcif_readl(struct sh_mmcif_host *host, unsigned int reg)
211{
212 return readl(host->addr + reg);
213}
214
215static inline void sh_mmcif_writel(struct sh_mmcif_host *host,
216 unsigned int reg, u32 val)
217{
218 writel(val, host->addr + reg);
219}
220 191
221static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 192static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
222 unsigned int reg, u32 val) 193 unsigned int reg, u32 val)
223{ 194{
224 writel(val | sh_mmcif_readl(host, reg), host->addr + reg); 195 writel(val | readl(host->addr + reg), host->addr + reg);
225} 196}
226 197
227static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 198static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
228 unsigned int reg, u32 val) 199 unsigned int reg, u32 val)
229{ 200{
230 writel(~val & sh_mmcif_readl(host, reg), host->addr + reg); 201 writel(~val & readl(host->addr + reg), host->addr + reg);
231} 202}
232 203
233 204
@@ -253,10 +224,10 @@ static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
253{ 224{
254 u32 tmp; 225 u32 tmp;
255 226
256 tmp = 0x010f0000 & sh_mmcif_readl(host, MMCIF_CE_CLK_CTRL); 227 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
257 228
258 sh_mmcif_writel(host, MMCIF_CE_VERSION, SOFT_RST_ON); 229 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
259 sh_mmcif_writel(host, MMCIF_CE_VERSION, SOFT_RST_OFF); 230 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
260 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 231 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
261 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); 232 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
262 /* byte swap on */ 233 /* byte swap on */
@@ -271,12 +242,10 @@ static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
271 host->sd_error = 0; 242 host->sd_error = 0;
272 host->wait_int = 0; 243 host->wait_int = 0;
273 244
274 state1 = sh_mmcif_readl(host, MMCIF_CE_HOST_STS1); 245 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
275 state2 = sh_mmcif_readl(host, MMCIF_CE_HOST_STS2); 246 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
276 pr_debug("%s: ERR HOST_STS1 = %08x\n", \ 247 pr_debug("%s: ERR HOST_STS1 = %08x\n", DRIVER_NAME, state1);
277 DRIVER_NAME, sh_mmcif_readl(host, MMCIF_CE_HOST_STS1)); 248 pr_debug("%s: ERR HOST_STS2 = %08x\n", DRIVER_NAME, state2);
278 pr_debug("%s: ERR HOST_STS2 = %08x\n", \
279 DRIVER_NAME, sh_mmcif_readl(host, MMCIF_CE_HOST_STS2));
280 249
281 if (state1 & STS1_CMDSEQ) { 250 if (state1 & STS1_CMDSEQ) {
282 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 251 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
@@ -288,7 +257,7 @@ static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
288 "command sequence timeout err\n"); 257 "command sequence timeout err\n");
289 return -EIO; 258 return -EIO;
290 } 259 }
291 if (!(sh_mmcif_readl(host, MMCIF_CE_HOST_STS1) 260 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
292 & STS1_CMDSEQ)) 261 & STS1_CMDSEQ))
293 break; 262 break;
294 mdelay(1); 263 mdelay(1);
@@ -330,9 +299,9 @@ static int sh_mmcif_single_read(struct sh_mmcif_host *host,
330 299
331 host->wait_int = 0; 300 host->wait_int = 0;
332 blocksize = (BLOCK_SIZE_MASK & 301 blocksize = (BLOCK_SIZE_MASK &
333 sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET)) + 3; 302 sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
334 for (i = 0; i < blocksize / 4; i++) 303 for (i = 0; i < blocksize / 4; i++)
335 *p++ = sh_mmcif_readl(host, MMCIF_CE_DATA); 304 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
336 305
337 /* buffer read end */ 306 /* buffer read end */
338 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 307 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
@@ -353,7 +322,8 @@ static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
353 long time; 322 long time;
354 u32 blocksize, i, j, sec, *p; 323 u32 blocksize, i, j, sec, *p;
355 324
356 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET); 325 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
326 MMCIF_CE_BLOCK_SET);
357 for (j = 0; j < data->sg_len; j++) { 327 for (j = 0; j < data->sg_len; j++) {
358 p = sg_virt(data->sg); 328 p = sg_virt(data->sg);
359 host->wait_int = 0; 329 host->wait_int = 0;
@@ -370,7 +340,8 @@ static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
370 340
371 host->wait_int = 0; 341 host->wait_int = 0;
372 for (i = 0; i < blocksize / 4; i++) 342 for (i = 0; i < blocksize / 4; i++)
373 *p++ = sh_mmcif_readl(host, MMCIF_CE_DATA); 343 *p++ = sh_mmcif_readl(host->addr,
344 MMCIF_CE_DATA);
374 } 345 }
375 if (j < data->sg_len - 1) 346 if (j < data->sg_len - 1)
376 data->sg++; 347 data->sg++;
@@ -397,9 +368,9 @@ static int sh_mmcif_single_write(struct sh_mmcif_host *host,
397 368
398 host->wait_int = 0; 369 host->wait_int = 0;
399 blocksize = (BLOCK_SIZE_MASK & 370 blocksize = (BLOCK_SIZE_MASK &
400 sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET)) + 3; 371 sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
401 for (i = 0; i < blocksize / 4; i++) 372 for (i = 0; i < blocksize / 4; i++)
402 sh_mmcif_writel(host, MMCIF_CE_DATA, *p++); 373 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
403 374
404 /* buffer write end */ 375 /* buffer write end */
405 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 376 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
@@ -421,7 +392,8 @@ static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
421 long time; 392 long time;
422 u32 i, sec, j, blocksize, *p; 393 u32 i, sec, j, blocksize, *p;
423 394
424 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET); 395 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
396 MMCIF_CE_BLOCK_SET);
425 397
426 for (j = 0; j < data->sg_len; j++) { 398 for (j = 0; j < data->sg_len; j++) {
427 p = sg_virt(data->sg); 399 p = sg_virt(data->sg);
@@ -439,7 +411,8 @@ static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
439 411
440 host->wait_int = 0; 412 host->wait_int = 0;
441 for (i = 0; i < blocksize / 4; i++) 413 for (i = 0; i < blocksize / 4; i++)
442 sh_mmcif_writel(host, MMCIF_CE_DATA, *p++); 414 sh_mmcif_writel(host->addr,
415 MMCIF_CE_DATA, *p++);
443 } 416 }
444 if (j < data->sg_len - 1) 417 if (j < data->sg_len - 1)
445 data->sg++; 418 data->sg++;
@@ -451,18 +424,18 @@ static void sh_mmcif_get_response(struct sh_mmcif_host *host,
451 struct mmc_command *cmd) 424 struct mmc_command *cmd)
452{ 425{
453 if (cmd->flags & MMC_RSP_136) { 426 if (cmd->flags & MMC_RSP_136) {
454 cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP3); 427 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
455 cmd->resp[1] = sh_mmcif_readl(host, MMCIF_CE_RESP2); 428 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
456 cmd->resp[2] = sh_mmcif_readl(host, MMCIF_CE_RESP1); 429 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
457 cmd->resp[3] = sh_mmcif_readl(host, MMCIF_CE_RESP0); 430 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
458 } else 431 } else
459 cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP0); 432 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
460} 433}
461 434
462static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 435static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
463 struct mmc_command *cmd) 436 struct mmc_command *cmd)
464{ 437{
465 cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP_CMD12); 438 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
466} 439}
467 440
468static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 441static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
@@ -596,18 +569,19 @@ static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
596 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO; 569 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
597 570
598 if (host->data) { 571 if (host->data) {
599 sh_mmcif_writel(host, MMCIF_CE_BLOCK_SET, 0); 572 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
600 sh_mmcif_writel(host, MMCIF_CE_BLOCK_SET, mrq->data->blksz); 573 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
574 mrq->data->blksz);
601 } 575 }
602 opc = sh_mmcif_set_cmd(host, mrq, cmd, opc); 576 opc = sh_mmcif_set_cmd(host, mrq, cmd, opc);
603 577
604 sh_mmcif_writel(host, MMCIF_CE_INT, 0xD80430C0); 578 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
605 sh_mmcif_writel(host, MMCIF_CE_INT_MASK, mask); 579 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
606 /* set arg */ 580 /* set arg */
607 sh_mmcif_writel(host, MMCIF_CE_ARG, cmd->arg); 581 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
608 host->wait_int = 0; 582 host->wait_int = 0;
609 /* set cmd */ 583 /* set cmd */
610 sh_mmcif_writel(host, MMCIF_CE_CMD_SET, opc); 584 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
611 585
612 time = wait_event_interruptible_timeout(host->intr_wait, 586 time = wait_event_interruptible_timeout(host->intr_wait,
613 host->wait_int == 1 || host->sd_error == 1, host->timeout); 587 host->wait_int == 1 || host->sd_error == 1, host->timeout);
@@ -752,43 +726,44 @@ static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
752 u32 state = 0; 726 u32 state = 0;
753 int err = 0; 727 int err = 0;
754 728
755 state = sh_mmcif_readl(host, MMCIF_CE_INT); 729 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
756 730
757 if (state & INT_RBSYE) { 731 if (state & INT_RBSYE) {
758 sh_mmcif_writel(host, MMCIF_CE_INT, ~(INT_RBSYE | INT_CRSPE)); 732 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
733 ~(INT_RBSYE | INT_CRSPE));
759 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE); 734 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
760 } else if (state & INT_CRSPE) { 735 } else if (state & INT_CRSPE) {
761 sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_CRSPE); 736 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
762 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE); 737 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
763 } else if (state & INT_BUFREN) { 738 } else if (state & INT_BUFREN) {
764 sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFREN); 739 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
765 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 740 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
766 } else if (state & INT_BUFWEN) { 741 } else if (state & INT_BUFWEN) {
767 sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFWEN); 742 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
768 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 743 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
769 } else if (state & INT_CMD12DRE) { 744 } else if (state & INT_CMD12DRE) {
770 sh_mmcif_writel(host, MMCIF_CE_INT, 745 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
771 ~(INT_CMD12DRE | INT_CMD12RBE | 746 ~(INT_CMD12DRE | INT_CMD12RBE |
772 INT_CMD12CRE | INT_BUFRE)); 747 INT_CMD12CRE | INT_BUFRE));
773 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 748 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
774 } else if (state & INT_BUFRE) { 749 } else if (state & INT_BUFRE) {
775 sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFRE); 750 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
776 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 751 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
777 } else if (state & INT_DTRANE) { 752 } else if (state & INT_DTRANE) {
778 sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_DTRANE); 753 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
779 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 754 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
780 } else if (state & INT_CMD12RBE) { 755 } else if (state & INT_CMD12RBE) {
781 sh_mmcif_writel(host, MMCIF_CE_INT, 756 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
782 ~(INT_CMD12RBE | INT_CMD12CRE)); 757 ~(INT_CMD12RBE | INT_CMD12CRE));
783 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 758 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
784 } else if (state & INT_ERR_STS) { 759 } else if (state & INT_ERR_STS) {
785 /* err interrupts */ 760 /* err interrupts */
786 sh_mmcif_writel(host, MMCIF_CE_INT, ~state); 761 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
787 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 762 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
788 err = 1; 763 err = 1;
789 } else { 764 } else {
790 pr_debug("%s: Not support int\n", DRIVER_NAME); 765 pr_debug("%s: Not support int\n", DRIVER_NAME);
791 sh_mmcif_writel(host, MMCIF_CE_INT, ~state); 766 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
792 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 767 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
793 err = 1; 768 err = 1;
794 } 769 }
@@ -894,12 +869,12 @@ static int __devinit sh_mmcif_probe(struct platform_device *pdev)
894 goto clean_up2; 869 goto clean_up2;
895 } 870 }
896 871
897 sh_mmcif_writel(host, MMCIF_CE_INT_MASK, MASK_ALL); 872 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
898 sh_mmcif_detect(host->mmc); 873 sh_mmcif_detect(host->mmc);
899 874
900 pr_info("%s: driver version %s\n", DRIVER_NAME, DRIVER_VERSION); 875 pr_info("%s: driver version %s\n", DRIVER_NAME, DRIVER_VERSION);
901 pr_debug("%s: chip ver H'%04x\n", DRIVER_NAME, 876 pr_debug("%s: chip ver H'%04x\n", DRIVER_NAME,
902 sh_mmcif_readl(host, MMCIF_CE_VERSION) & 0x0000ffff); 877 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
903 return ret; 878 return ret;
904 879
905clean_up2: 880clean_up2:
@@ -917,7 +892,7 @@ static int __devexit sh_mmcif_remove(struct platform_device *pdev)
917 struct sh_mmcif_host *host = platform_get_drvdata(pdev); 892 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
918 int irq[2]; 893 int irq[2];
919 894
920 sh_mmcif_writel(host, MMCIF_CE_INT_MASK, MASK_ALL); 895 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
921 896
922 irq[0] = platform_get_irq(pdev, 0); 897 irq[0] = platform_get_irq(pdev, 0);
923 irq[1] = platform_get_irq(pdev, 1); 898 irq[1] = platform_get_irq(pdev, 1);
diff --git a/drivers/sh/intc.c b/drivers/sh/intc.c
index c585574b9aed..e91a23e5ffd8 100644
--- a/drivers/sh/intc.c
+++ b/drivers/sh/intc.c
@@ -16,6 +16,8 @@
16 * License. See the file "COPYING" in the main directory of this archive 16 * License. See the file "COPYING" in the main directory of this archive
17 * for more details. 17 * for more details.
18 */ 18 */
19#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
19#include <linux/init.h> 21#include <linux/init.h>
20#include <linux/irq.h> 22#include <linux/irq.h>
21#include <linux/module.h> 23#include <linux/module.h>
@@ -855,8 +857,8 @@ static void __init intc_register_irq(struct intc_desc *desc,
855 primary = 1; 857 primary = 1;
856 858
857 if (!data[0] && !data[1]) 859 if (!data[0] && !data[1])
858 pr_warning("intc: missing unique irq mask for " 860 pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n",
859 "irq %d (vect 0x%04x)\n", irq, irq2evt(irq)); 861 irq, irq2evt(irq));
860 862
861 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1); 863 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
862 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1); 864 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
@@ -952,7 +954,7 @@ int __init register_intc_controller(struct intc_desc *desc)
952 struct intc_desc_int *d; 954 struct intc_desc_int *d;
953 struct resource *res; 955 struct resource *res;
954 956
955 pr_info("intc: Registered controller '%s' with %u IRQs\n", 957 pr_info("Registered controller '%s' with %u IRQs\n",
956 desc->name, hw->nr_vectors); 958 desc->name, hw->nr_vectors);
957 959
958 d = kzalloc(sizeof(*d), GFP_NOWAIT); 960 d = kzalloc(sizeof(*d), GFP_NOWAIT);
@@ -1148,7 +1150,7 @@ int register_intc_userimask(unsigned long addr)
1148 if (unlikely(!uimask)) 1150 if (unlikely(!uimask))
1149 return -ENOMEM; 1151 return -ENOMEM;
1150 1152
1151 pr_info("intc: userimask support registered for levels 0 -> %d\n", 1153 pr_info("userimask support registered for levels 0 -> %d\n",
1152 default_prio_level - 1); 1154 default_prio_level - 1);
1153 1155
1154 return 0; 1156 return 0;
@@ -1286,7 +1288,7 @@ static int __init register_intc_sysdevs(void)
1286 } 1288 }
1287 1289
1288 if (error) 1290 if (error)
1289 pr_err("intc: sysdev registration error\n"); 1291 pr_err("sysdev registration error\n");
1290 1292
1291 return error; 1293 return error;
1292} 1294}
diff --git a/drivers/usb/gadget/m66592-udc.h b/drivers/usb/gadget/m66592-udc.h
index 8b960deed680..c3caf1ac73ce 100644
--- a/drivers/usb/gadget/m66592-udc.h
+++ b/drivers/usb/gadget/m66592-udc.h
@@ -537,35 +537,35 @@ struct m66592 {
537/*-------------------------------------------------------------------------*/ 537/*-------------------------------------------------------------------------*/
538static inline u16 m66592_read(struct m66592 *m66592, unsigned long offset) 538static inline u16 m66592_read(struct m66592 *m66592, unsigned long offset)
539{ 539{
540 return inw((unsigned long)m66592->reg + offset); 540 return ioread16(m66592->reg + offset);
541} 541}
542 542
543static inline void m66592_read_fifo(struct m66592 *m66592, 543static inline void m66592_read_fifo(struct m66592 *m66592,
544 unsigned long offset, 544 unsigned long offset,
545 void *buf, unsigned long len) 545 void *buf, unsigned long len)
546{ 546{
547 unsigned long fifoaddr = (unsigned long)m66592->reg + offset; 547 void __iomem *fifoaddr = m66592->reg + offset;
548 548
549 if (m66592->pdata->on_chip) { 549 if (m66592->pdata->on_chip) {
550 len = (len + 3) / 4; 550 len = (len + 3) / 4;
551 insl(fifoaddr, buf, len); 551 ioread32_rep(fifoaddr, buf, len);
552 } else { 552 } else {
553 len = (len + 1) / 2; 553 len = (len + 1) / 2;
554 insw(fifoaddr, buf, len); 554 ioread16_rep(fifoaddr, buf, len);
555 } 555 }
556} 556}
557 557
558static inline void m66592_write(struct m66592 *m66592, u16 val, 558static inline void m66592_write(struct m66592 *m66592, u16 val,
559 unsigned long offset) 559 unsigned long offset)
560{ 560{
561 outw(val, (unsigned long)m66592->reg + offset); 561 iowrite16(val, m66592->reg + offset);
562} 562}
563 563
564static inline void m66592_write_fifo(struct m66592 *m66592, 564static inline void m66592_write_fifo(struct m66592 *m66592,
565 unsigned long offset, 565 unsigned long offset,
566 void *buf, unsigned long len) 566 void *buf, unsigned long len)
567{ 567{
568 unsigned long fifoaddr = (unsigned long)m66592->reg + offset; 568 void __iomem *fifoaddr = m66592->reg + offset;
569 569
570 if (m66592->pdata->on_chip) { 570 if (m66592->pdata->on_chip) {
571 unsigned long count; 571 unsigned long count;
@@ -573,25 +573,25 @@ static inline void m66592_write_fifo(struct m66592 *m66592,
573 int i; 573 int i;
574 574
575 count = len / 4; 575 count = len / 4;
576 outsl(fifoaddr, buf, count); 576 iowrite32_rep(fifoaddr, buf, count);
577 577
578 if (len & 0x00000003) { 578 if (len & 0x00000003) {
579 pb = buf + count * 4; 579 pb = buf + count * 4;
580 for (i = 0; i < (len & 0x00000003); i++) { 580 for (i = 0; i < (len & 0x00000003); i++) {
581 if (m66592_read(m66592, M66592_CFBCFG)) /* le */ 581 if (m66592_read(m66592, M66592_CFBCFG)) /* le */
582 outb(pb[i], fifoaddr + (3 - i)); 582 iowrite8(pb[i], fifoaddr + (3 - i));
583 else 583 else
584 outb(pb[i], fifoaddr + i); 584 iowrite8(pb[i], fifoaddr + i);
585 } 585 }
586 } 586 }
587 } else { 587 } else {
588 unsigned long odd = len & 0x0001; 588 unsigned long odd = len & 0x0001;
589 589
590 len = len / 2; 590 len = len / 2;
591 outsw(fifoaddr, buf, len); 591 iowrite16_rep(fifoaddr, buf, len);
592 if (odd) { 592 if (odd) {
593 unsigned char *p = buf + len*2; 593 unsigned char *p = buf + len*2;
594 outb(*p, fifoaddr); 594 iowrite8(*p, fifoaddr);
595 } 595 }
596 } 596 }
597} 597}
diff --git a/drivers/usb/gadget/r8a66597-udc.c b/drivers/usb/gadget/r8a66597-udc.c
index 888d8f166c0b..70a817842755 100644
--- a/drivers/usb/gadget/r8a66597-udc.c
+++ b/drivers/usb/gadget/r8a66597-udc.c
@@ -1500,7 +1500,7 @@ static int __exit r8a66597_remove(struct platform_device *pdev)
1500 struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev); 1500 struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev);
1501 1501
1502 del_timer_sync(&r8a66597->timer); 1502 del_timer_sync(&r8a66597->timer);
1503 iounmap((void *)r8a66597->reg); 1503 iounmap(r8a66597->reg);
1504 free_irq(platform_get_irq(pdev, 0), r8a66597); 1504 free_irq(platform_get_irq(pdev, 0), r8a66597);
1505 r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req); 1505 r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
1506#ifdef CONFIG_HAVE_CLK 1506#ifdef CONFIG_HAVE_CLK
@@ -1578,7 +1578,7 @@ static int __init r8a66597_probe(struct platform_device *pdev)
1578 init_timer(&r8a66597->timer); 1578 init_timer(&r8a66597->timer);
1579 r8a66597->timer.function = r8a66597_timer; 1579 r8a66597->timer.function = r8a66597_timer;
1580 r8a66597->timer.data = (unsigned long)r8a66597; 1580 r8a66597->timer.data = (unsigned long)r8a66597;
1581 r8a66597->reg = (unsigned long)reg; 1581 r8a66597->reg = reg;
1582 1582
1583#ifdef CONFIG_HAVE_CLK 1583#ifdef CONFIG_HAVE_CLK
1584 if (r8a66597->pdata->on_chip) { 1584 if (r8a66597->pdata->on_chip) {
diff --git a/drivers/usb/gadget/r8a66597-udc.h b/drivers/usb/gadget/r8a66597-udc.h
index 9a537aa07968..f763b5190afa 100644
--- a/drivers/usb/gadget/r8a66597-udc.h
+++ b/drivers/usb/gadget/r8a66597-udc.h
@@ -91,7 +91,7 @@ struct r8a66597_ep {
91 91
92struct r8a66597 { 92struct r8a66597 {
93 spinlock_t lock; 93 spinlock_t lock;
94 unsigned long reg; 94 void __iomem *reg;
95 95
96#ifdef CONFIG_HAVE_CLK 96#ifdef CONFIG_HAVE_CLK
97 struct clk *clk; 97 struct clk *clk;
@@ -127,7 +127,7 @@ struct r8a66597 {
127 127
128static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset) 128static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
129{ 129{
130 return inw(r8a66597->reg + offset); 130 return ioread16(r8a66597->reg + offset);
131} 131}
132 132
133static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597, 133static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
@@ -135,7 +135,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
135 unsigned char *buf, 135 unsigned char *buf,
136 int len) 136 int len)
137{ 137{
138 unsigned long fifoaddr = r8a66597->reg + offset; 138 void __iomem *fifoaddr = r8a66597->reg + offset;
139 unsigned int data; 139 unsigned int data;
140 int i; 140 int i;
141 141
@@ -144,7 +144,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
144 144
145 /* aligned buf case */ 145 /* aligned buf case */
146 if (len >= 4 && !((unsigned long)buf & 0x03)) { 146 if (len >= 4 && !((unsigned long)buf & 0x03)) {
147 insl(fifoaddr, buf, len / 4); 147 ioread32_rep(fifoaddr, buf, len / 4);
148 buf += len & ~0x03; 148 buf += len & ~0x03;
149 len &= 0x03; 149 len &= 0x03;
150 } 150 }
@@ -152,7 +152,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
152 /* unaligned buf case */ 152 /* unaligned buf case */
153 for (i = 0; i < len; i++) { 153 for (i = 0; i < len; i++) {
154 if (!(i & 0x03)) 154 if (!(i & 0x03))
155 data = inl(fifoaddr); 155 data = ioread32(fifoaddr);
156 156
157 buf[i] = (data >> ((i & 0x03) * 8)) & 0xff; 157 buf[i] = (data >> ((i & 0x03) * 8)) & 0xff;
158 } 158 }
@@ -161,7 +161,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
161 161
162 /* aligned buf case */ 162 /* aligned buf case */
163 if (len >= 2 && !((unsigned long)buf & 0x01)) { 163 if (len >= 2 && !((unsigned long)buf & 0x01)) {
164 insw(fifoaddr, buf, len / 2); 164 ioread16_rep(fifoaddr, buf, len / 2);
165 buf += len & ~0x01; 165 buf += len & ~0x01;
166 len &= 0x01; 166 len &= 0x01;
167 } 167 }
@@ -169,7 +169,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
169 /* unaligned buf case */ 169 /* unaligned buf case */
170 for (i = 0; i < len; i++) { 170 for (i = 0; i < len; i++) {
171 if (!(i & 0x01)) 171 if (!(i & 0x01))
172 data = inw(fifoaddr); 172 data = ioread16(fifoaddr);
173 173
174 buf[i] = (data >> ((i & 0x01) * 8)) & 0xff; 174 buf[i] = (data >> ((i & 0x01) * 8)) & 0xff;
175 } 175 }
@@ -179,7 +179,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
179static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val, 179static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
180 unsigned long offset) 180 unsigned long offset)
181{ 181{
182 outw(val, r8a66597->reg + offset); 182 iowrite16(val, r8a66597->reg + offset);
183} 183}
184 184
185static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597, 185static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
@@ -187,21 +187,21 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
187 unsigned char *buf, 187 unsigned char *buf,
188 int len) 188 int len)
189{ 189{
190 unsigned long fifoaddr = r8a66597->reg + offset; 190 void __iomem *fifoaddr = r8a66597->reg + offset;
191 int adj = 0; 191 int adj = 0;
192 int i; 192 int i;
193 193
194 if (r8a66597->pdata->on_chip) { 194 if (r8a66597->pdata->on_chip) {
195 /* 32-bit access only if buf is 32-bit aligned */ 195 /* 32-bit access only if buf is 32-bit aligned */
196 if (len >= 4 && !((unsigned long)buf & 0x03)) { 196 if (len >= 4 && !((unsigned long)buf & 0x03)) {
197 outsl(fifoaddr, buf, len / 4); 197 iowrite32_rep(fifoaddr, buf, len / 4);
198 buf += len & ~0x03; 198 buf += len & ~0x03;
199 len &= 0x03; 199 len &= 0x03;
200 } 200 }
201 } else { 201 } else {
202 /* 16-bit access only if buf is 16-bit aligned */ 202 /* 16-bit access only if buf is 16-bit aligned */
203 if (len >= 2 && !((unsigned long)buf & 0x01)) { 203 if (len >= 2 && !((unsigned long)buf & 0x01)) {
204 outsw(fifoaddr, buf, len / 2); 204 iowrite16_rep(fifoaddr, buf, len / 2);
205 buf += len & ~0x01; 205 buf += len & ~0x01;
206 len &= 0x01; 206 len &= 0x01;
207 } 207 }
@@ -216,7 +216,7 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
216 } 216 }
217 217
218 for (i = 0; i < len; i++) 218 for (i = 0; i < len; i++)
219 outb(buf[i], fifoaddr + adj - (i & adj)); 219 iowrite8(buf[i], fifoaddr + adj - (i & adj));
220} 220}
221 221
222static inline void r8a66597_mdfy(struct r8a66597 *r8a66597, 222static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c
index 6db57ab6079d..1a2bb4ce638f 100644
--- a/drivers/usb/host/r8a66597-hcd.c
+++ b/drivers/usb/host/r8a66597-hcd.c
@@ -2404,7 +2404,7 @@ static int __init_or_module r8a66597_remove(struct platform_device *pdev)
2404 2404
2405 del_timer_sync(&r8a66597->rh_timer); 2405 del_timer_sync(&r8a66597->rh_timer);
2406 usb_remove_hcd(hcd); 2406 usb_remove_hcd(hcd);
2407 iounmap((void *)r8a66597->reg); 2407 iounmap(r8a66597->reg);
2408#ifdef CONFIG_HAVE_CLK 2408#ifdef CONFIG_HAVE_CLK
2409 if (r8a66597->pdata->on_chip) 2409 if (r8a66597->pdata->on_chip)
2410 clk_put(r8a66597->clk); 2410 clk_put(r8a66597->clk);
@@ -2496,7 +2496,7 @@ static int __devinit r8a66597_probe(struct platform_device *pdev)
2496 init_timer(&r8a66597->rh_timer); 2496 init_timer(&r8a66597->rh_timer);
2497 r8a66597->rh_timer.function = r8a66597_timer; 2497 r8a66597->rh_timer.function = r8a66597_timer;
2498 r8a66597->rh_timer.data = (unsigned long)r8a66597; 2498 r8a66597->rh_timer.data = (unsigned long)r8a66597;
2499 r8a66597->reg = (unsigned long)reg; 2499 r8a66597->reg = reg;
2500 2500
2501 /* make sure no interrupts are pending */ 2501 /* make sure no interrupts are pending */
2502 ret = r8a66597_clock_enable(r8a66597); 2502 ret = r8a66597_clock_enable(r8a66597);
diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h
index 228e3fb23854..95d0f5adfdcf 100644
--- a/drivers/usb/host/r8a66597.h
+++ b/drivers/usb/host/r8a66597.h
@@ -112,7 +112,7 @@ struct r8a66597_root_hub {
112 112
113struct r8a66597 { 113struct r8a66597 {
114 spinlock_t lock; 114 spinlock_t lock;
115 unsigned long reg; 115 void __iomem *reg;
116#ifdef CONFIG_HAVE_CLK 116#ifdef CONFIG_HAVE_CLK
117 struct clk *clk; 117 struct clk *clk;
118#endif 118#endif
@@ -170,67 +170,67 @@ static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
170 170
171static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset) 171static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
172{ 172{
173 return inw(r8a66597->reg + offset); 173 return ioread16(r8a66597->reg + offset);
174} 174}
175 175
176static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597, 176static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
177 unsigned long offset, u16 *buf, 177 unsigned long offset, u16 *buf,
178 int len) 178 int len)
179{ 179{
180 unsigned long fifoaddr = r8a66597->reg + offset; 180 void __iomem *fifoaddr = r8a66597->reg + offset;
181 unsigned long count; 181 unsigned long count;
182 182
183 if (r8a66597->pdata->on_chip) { 183 if (r8a66597->pdata->on_chip) {
184 count = len / 4; 184 count = len / 4;
185 insl(fifoaddr, buf, count); 185 ioread32_rep(fifoaddr, buf, count);
186 186
187 if (len & 0x00000003) { 187 if (len & 0x00000003) {
188 unsigned long tmp = inl(fifoaddr); 188 unsigned long tmp = ioread32(fifoaddr);
189 memcpy((unsigned char *)buf + count * 4, &tmp, 189 memcpy((unsigned char *)buf + count * 4, &tmp,
190 len & 0x03); 190 len & 0x03);
191 } 191 }
192 } else { 192 } else {
193 len = (len + 1) / 2; 193 len = (len + 1) / 2;
194 insw(fifoaddr, buf, len); 194 ioread16_rep(fifoaddr, buf, len);
195 } 195 }
196} 196}
197 197
198static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val, 198static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
199 unsigned long offset) 199 unsigned long offset)
200{ 200{
201 outw(val, r8a66597->reg + offset); 201 iowrite16(val, r8a66597->reg + offset);
202} 202}
203 203
204static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597, 204static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
205 unsigned long offset, u16 *buf, 205 unsigned long offset, u16 *buf,
206 int len) 206 int len)
207{ 207{
208 unsigned long fifoaddr = r8a66597->reg + offset; 208 void __iomem *fifoaddr = r8a66597->reg + offset;
209 unsigned long count; 209 unsigned long count;
210 unsigned char *pb; 210 unsigned char *pb;
211 int i; 211 int i;
212 212
213 if (r8a66597->pdata->on_chip) { 213 if (r8a66597->pdata->on_chip) {
214 count = len / 4; 214 count = len / 4;
215 outsl(fifoaddr, buf, count); 215 iowrite32_rep(fifoaddr, buf, count);
216 216
217 if (len & 0x00000003) { 217 if (len & 0x00000003) {
218 pb = (unsigned char *)buf + count * 4; 218 pb = (unsigned char *)buf + count * 4;
219 for (i = 0; i < (len & 0x00000003); i++) { 219 for (i = 0; i < (len & 0x00000003); i++) {
220 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND) 220 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
221 outb(pb[i], fifoaddr + i); 221 iowrite8(pb[i], fifoaddr + i);
222 else 222 else
223 outb(pb[i], fifoaddr + 3 - i); 223 iowrite8(pb[i], fifoaddr + 3 - i);
224 } 224 }
225 } 225 }
226 } else { 226 } else {
227 int odd = len & 0x0001; 227 int odd = len & 0x0001;
228 228
229 len = len / 2; 229 len = len / 2;
230 outsw(fifoaddr, buf, len); 230 ioread16_rep(fifoaddr, buf, len);
231 if (unlikely(odd)) { 231 if (unlikely(odd)) {
232 buf = &buf[len]; 232 buf = &buf[len];
233 outb((unsigned char)*buf, fifoaddr); 233 iowrite8((unsigned char)*buf, fifoaddr);
234 } 234 }
235 } 235 }
236} 236}
diff --git a/drivers/video/sh_mobile_lcdcfb.c b/drivers/video/sh_mobile_lcdcfb.c
index e8c769944812..12c451a711e9 100644
--- a/drivers/video/sh_mobile_lcdcfb.c
+++ b/drivers/video/sh_mobile_lcdcfb.c
@@ -991,13 +991,13 @@ static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
991 priv->ch[j].lcdc = priv; 991 priv->ch[j].lcdc = priv;
992 memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i])); 992 memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
993 993
994 error = sh_mobile_lcdc_check_interface(&priv->ch[i]); 994 error = sh_mobile_lcdc_check_interface(&priv->ch[j]);
995 if (error) { 995 if (error) {
996 dev_err(&pdev->dev, "unsupported interface type\n"); 996 dev_err(&pdev->dev, "unsupported interface type\n");
997 goto err1; 997 goto err1;
998 } 998 }
999 init_waitqueue_head(&priv->ch[i].frame_end_wait); 999 init_waitqueue_head(&priv->ch[j].frame_end_wait);
1000 init_completion(&priv->ch[i].vsync_completion); 1000 init_completion(&priv->ch[j].vsync_completion);
1001 priv->ch[j].pan_offset = 0; 1001 priv->ch[j].pan_offset = 0;
1002 1002
1003 switch (pdata->ch[i].chan) { 1003 switch (pdata->ch[i].chan) {