aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
Diffstat (limited to 'drivers')
-rw-r--r--drivers/ata/libata-core.c6
-rw-r--r--drivers/ata/libata-scsi.c7
-rw-r--r--drivers/ata/sata_nv.c53
-rw-r--r--drivers/ata/sata_promise.c20
-rw-r--r--drivers/ata/sata_via.c4
-rw-r--r--drivers/block/cciss.c28
-rw-r--r--drivers/block/cpqarray.c7
-rw-r--r--drivers/char/vt.c10
-rw-r--r--drivers/gpu/drm/i915/Makefile3
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c1
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h12
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c196
-rw-r--r--drivers/gpu/drm/radeon/radeon_cp.c15
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.h12
-rw-r--r--drivers/hwmon/applesmc.c36
-rw-r--r--drivers/mtd/chips/cfi_cmdset_0002.c13
-rw-r--r--drivers/mtd/chips/jedec_probe.c10
-rw-r--r--drivers/mtd/onenand/omap2.c1
-rw-r--r--drivers/net/Kconfig18
-rw-r--r--drivers/net/atl1e/atl1e.h1
-rw-r--r--drivers/net/bnx2x_init.h9
-rw-r--r--drivers/net/bnx2x_main.c10
-rw-r--r--drivers/net/fs_enet/fs_enet-main.c6
-rw-r--r--drivers/net/mv643xx_eth.c9
-rw-r--r--drivers/net/niu.c6
-rw-r--r--drivers/net/smc911x.c2
-rw-r--r--drivers/net/smc91x.c2
-rw-r--r--drivers/net/ucc_geth_ethtool.c1
-rw-r--r--drivers/pnp/interface.c1
-rw-r--r--drivers/ps3/ps3-lpm.c1
-rw-r--r--drivers/rtc/interface.c2
-rw-r--r--drivers/rtc/rtc-cmos.c2
-rw-r--r--drivers/sbus/char/jsflash.c1
-rw-r--r--drivers/serial/atmel_serial.c17
-rw-r--r--drivers/staging/echo/echo.c1
-rw-r--r--drivers/staging/me4000/me4000.c1
-rw-r--r--drivers/video/Kconfig32
-rw-r--r--drivers/video/Makefile1
-rw-r--r--drivers/video/fbmem.c63
-rw-r--r--drivers/video/mb862xx/Makefile5
-rw-r--r--drivers/video/mb862xx/mb862xx_reg.h138
-rw-r--r--drivers/video/mb862xx/mb862xxfb.c1061
-rw-r--r--drivers/video/mb862xx/mb862xxfb.h83
-rw-r--r--drivers/watchdog/at91sam9_wdt.c2
-rw-r--r--drivers/xen/balloon.c1
45 files changed, 1685 insertions, 225 deletions
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 82af7011f2dd..622350d9b2e3 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -4024,6 +4024,7 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
4024 4024
4025 /* Weird ATAPI devices */ 4025 /* Weird ATAPI devices */
4026 { "TORiSAN DVD-ROM DRD-N216", NULL, ATA_HORKAGE_MAX_SEC_128 }, 4026 { "TORiSAN DVD-ROM DRD-N216", NULL, ATA_HORKAGE_MAX_SEC_128 },
4027 { "QUANTUM DAT DAT72-000", NULL, ATA_HORKAGE_ATAPI_MOD16_DMA },
4027 4028
4028 /* Devices we expect to fail diagnostics */ 4029 /* Devices we expect to fail diagnostics */
4029 4030
@@ -4444,7 +4445,8 @@ int atapi_check_dma(struct ata_queued_cmd *qc)
4444 /* Don't allow DMA if it isn't multiple of 16 bytes. Quite a 4445 /* Don't allow DMA if it isn't multiple of 16 bytes. Quite a
4445 * few ATAPI devices choke on such DMA requests. 4446 * few ATAPI devices choke on such DMA requests.
4446 */ 4447 */
4447 if (unlikely(qc->nbytes & 15)) 4448 if (!(qc->dev->horkage & ATA_HORKAGE_ATAPI_MOD16_DMA) &&
4449 unlikely(qc->nbytes & 15))
4448 return 1; 4450 return 1;
4449 4451
4450 if (ap->ops->check_atapi_dma) 4452 if (ap->ops->check_atapi_dma)
@@ -5934,7 +5936,7 @@ static void ata_port_detach(struct ata_port *ap)
5934 * to us. Restore SControl and disable all existing devices. 5936 * to us. Restore SControl and disable all existing devices.
5935 */ 5937 */
5936 __ata_port_for_each_link(link, ap) { 5938 __ata_port_for_each_link(link, ap) {
5937 sata_scr_write(link, SCR_CONTROL, link->saved_scontrol); 5939 sata_scr_write(link, SCR_CONTROL, link->saved_scontrol & 0xff0);
5938 ata_link_for_each_dev(dev, link) 5940 ata_link_for_each_dev(dev, link)
5939 ata_dev_disable(dev); 5941 ata_dev_disable(dev);
5940 } 5942 }
diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c
index bbb30d882f05..3fa75eac135d 100644
--- a/drivers/ata/libata-scsi.c
+++ b/drivers/ata/libata-scsi.c
@@ -190,7 +190,7 @@ static ssize_t ata_scsi_park_show(struct device *device,
190 struct ata_port *ap; 190 struct ata_port *ap;
191 struct ata_link *link; 191 struct ata_link *link;
192 struct ata_device *dev; 192 struct ata_device *dev;
193 unsigned long flags; 193 unsigned long flags, now;
194 unsigned int uninitialized_var(msecs); 194 unsigned int uninitialized_var(msecs);
195 int rc = 0; 195 int rc = 0;
196 196
@@ -208,10 +208,11 @@ static ssize_t ata_scsi_park_show(struct device *device,
208 } 208 }
209 209
210 link = dev->link; 210 link = dev->link;
211 now = jiffies;
211 if (ap->pflags & ATA_PFLAG_EH_IN_PROGRESS && 212 if (ap->pflags & ATA_PFLAG_EH_IN_PROGRESS &&
212 link->eh_context.unloaded_mask & (1 << dev->devno) && 213 link->eh_context.unloaded_mask & (1 << dev->devno) &&
213 time_after(dev->unpark_deadline, jiffies)) 214 time_after(dev->unpark_deadline, now))
214 msecs = jiffies_to_msecs(dev->unpark_deadline - jiffies); 215 msecs = jiffies_to_msecs(dev->unpark_deadline - now);
215 else 216 else
216 msecs = 0; 217 msecs = 0;
217 218
diff --git a/drivers/ata/sata_nv.c b/drivers/ata/sata_nv.c
index fae3841de0d8..6f1460614325 100644
--- a/drivers/ata/sata_nv.c
+++ b/drivers/ata/sata_nv.c
@@ -307,10 +307,10 @@ static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
307 307
308static void nv_nf2_freeze(struct ata_port *ap); 308static void nv_nf2_freeze(struct ata_port *ap);
309static void nv_nf2_thaw(struct ata_port *ap); 309static void nv_nf2_thaw(struct ata_port *ap);
310static int nv_nf2_hardreset(struct ata_link *link, unsigned int *class,
311 unsigned long deadline);
310static void nv_ck804_freeze(struct ata_port *ap); 312static void nv_ck804_freeze(struct ata_port *ap);
311static void nv_ck804_thaw(struct ata_port *ap); 313static void nv_ck804_thaw(struct ata_port *ap);
312static int nv_hardreset(struct ata_link *link, unsigned int *class,
313 unsigned long deadline);
314static int nv_adma_slave_config(struct scsi_device *sdev); 314static int nv_adma_slave_config(struct scsi_device *sdev);
315static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc); 315static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc);
316static void nv_adma_qc_prep(struct ata_queued_cmd *qc); 316static void nv_adma_qc_prep(struct ata_queued_cmd *qc);
@@ -405,17 +405,8 @@ static struct scsi_host_template nv_swncq_sht = {
405 .slave_configure = nv_swncq_slave_config, 405 .slave_configure = nv_swncq_slave_config,
406}; 406};
407 407
408/* OSDL bz3352 reports that some nv controllers can't determine device
409 * signature reliably and nv_hardreset is implemented to work around
410 * the problem. This was reported on nf3 and it's unclear whether any
411 * other controllers are affected. However, the workaround has been
412 * applied to all variants and there isn't much to gain by trying to
413 * find out exactly which ones are affected at this point especially
414 * because NV has moved over to ahci for newer controllers.
415 */
416static struct ata_port_operations nv_common_ops = { 408static struct ata_port_operations nv_common_ops = {
417 .inherits = &ata_bmdma_port_ops, 409 .inherits = &ata_bmdma_port_ops,
418 .hardreset = nv_hardreset,
419 .scr_read = nv_scr_read, 410 .scr_read = nv_scr_read,
420 .scr_write = nv_scr_write, 411 .scr_write = nv_scr_write,
421}; 412};
@@ -429,12 +420,22 @@ static struct ata_port_operations nv_generic_ops = {
429 .hardreset = ATA_OP_NULL, 420 .hardreset = ATA_OP_NULL,
430}; 421};
431 422
423/* OSDL bz3352 reports that nf2/3 controllers can't determine device
424 * signature reliably. Also, the following thread reports detection
425 * failure on cold boot with the standard debouncing timing.
426 *
427 * http://thread.gmane.org/gmane.linux.ide/34098
428 *
429 * Debounce with hotplug timing and request follow-up SRST.
430 */
432static struct ata_port_operations nv_nf2_ops = { 431static struct ata_port_operations nv_nf2_ops = {
433 .inherits = &nv_common_ops, 432 .inherits = &nv_common_ops,
434 .freeze = nv_nf2_freeze, 433 .freeze = nv_nf2_freeze,
435 .thaw = nv_nf2_thaw, 434 .thaw = nv_nf2_thaw,
435 .hardreset = nv_nf2_hardreset,
436}; 436};
437 437
438/* CK804 finally gets hardreset right */
438static struct ata_port_operations nv_ck804_ops = { 439static struct ata_port_operations nv_ck804_ops = {
439 .inherits = &nv_common_ops, 440 .inherits = &nv_common_ops,
440 .freeze = nv_ck804_freeze, 441 .freeze = nv_ck804_freeze,
@@ -443,7 +444,7 @@ static struct ata_port_operations nv_ck804_ops = {
443}; 444};
444 445
445static struct ata_port_operations nv_adma_ops = { 446static struct ata_port_operations nv_adma_ops = {
446 .inherits = &nv_common_ops, 447 .inherits = &nv_ck804_ops,
447 448
448 .check_atapi_dma = nv_adma_check_atapi_dma, 449 .check_atapi_dma = nv_adma_check_atapi_dma,
449 .sff_tf_read = nv_adma_tf_read, 450 .sff_tf_read = nv_adma_tf_read,
@@ -467,7 +468,7 @@ static struct ata_port_operations nv_adma_ops = {
467}; 468};
468 469
469static struct ata_port_operations nv_swncq_ops = { 470static struct ata_port_operations nv_swncq_ops = {
470 .inherits = &nv_common_ops, 471 .inherits = &nv_generic_ops,
471 472
472 .qc_defer = ata_std_qc_defer, 473 .qc_defer = ata_std_qc_defer,
473 .qc_prep = nv_swncq_qc_prep, 474 .qc_prep = nv_swncq_qc_prep,
@@ -1553,6 +1554,17 @@ static void nv_nf2_thaw(struct ata_port *ap)
1553 iowrite8(mask, scr_addr + NV_INT_ENABLE); 1554 iowrite8(mask, scr_addr + NV_INT_ENABLE);
1554} 1555}
1555 1556
1557static int nv_nf2_hardreset(struct ata_link *link, unsigned int *class,
1558 unsigned long deadline)
1559{
1560 bool online;
1561 int rc;
1562
1563 rc = sata_link_hardreset(link, sata_deb_timing_hotplug, deadline,
1564 &online, NULL);
1565 return online ? -EAGAIN : rc;
1566}
1567
1556static void nv_ck804_freeze(struct ata_port *ap) 1568static void nv_ck804_freeze(struct ata_port *ap)
1557{ 1569{
1558 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR]; 1570 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
@@ -1605,21 +1617,6 @@ static void nv_mcp55_thaw(struct ata_port *ap)
1605 ata_sff_thaw(ap); 1617 ata_sff_thaw(ap);
1606} 1618}
1607 1619
1608static int nv_hardreset(struct ata_link *link, unsigned int *class,
1609 unsigned long deadline)
1610{
1611 int rc;
1612
1613 /* SATA hardreset fails to retrieve proper device signature on
1614 * some controllers. Request follow up SRST. For more info,
1615 * see http://bugzilla.kernel.org/show_bug.cgi?id=3352
1616 */
1617 rc = sata_sff_hardreset(link, class, deadline);
1618 if (rc)
1619 return rc;
1620 return -EAGAIN;
1621}
1622
1623static void nv_adma_error_handler(struct ata_port *ap) 1620static void nv_adma_error_handler(struct ata_port *ap)
1624{ 1621{
1625 struct nv_adma_port_priv *pp = ap->private_data; 1622 struct nv_adma_port_priv *pp = ap->private_data;
diff --git a/drivers/ata/sata_promise.c b/drivers/ata/sata_promise.c
index 750d8cdc00cd..ba9a2570a742 100644
--- a/drivers/ata/sata_promise.c
+++ b/drivers/ata/sata_promise.c
@@ -153,6 +153,10 @@ static void pdc_freeze(struct ata_port *ap);
153static void pdc_sata_freeze(struct ata_port *ap); 153static void pdc_sata_freeze(struct ata_port *ap);
154static void pdc_thaw(struct ata_port *ap); 154static void pdc_thaw(struct ata_port *ap);
155static void pdc_sata_thaw(struct ata_port *ap); 155static void pdc_sata_thaw(struct ata_port *ap);
156static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
157 unsigned long deadline);
158static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
159 unsigned long deadline);
156static void pdc_error_handler(struct ata_port *ap); 160static void pdc_error_handler(struct ata_port *ap);
157static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); 161static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
158static int pdc_pata_cable_detect(struct ata_port *ap); 162static int pdc_pata_cable_detect(struct ata_port *ap);
@@ -186,6 +190,7 @@ static struct ata_port_operations pdc_sata_ops = {
186 .scr_read = pdc_sata_scr_read, 190 .scr_read = pdc_sata_scr_read,
187 .scr_write = pdc_sata_scr_write, 191 .scr_write = pdc_sata_scr_write,
188 .port_start = pdc_sata_port_start, 192 .port_start = pdc_sata_port_start,
193 .hardreset = pdc_sata_hardreset,
189}; 194};
190 195
191/* First-generation chips need a more restrictive ->check_atapi_dma op */ 196/* First-generation chips need a more restrictive ->check_atapi_dma op */
@@ -200,6 +205,7 @@ static struct ata_port_operations pdc_pata_ops = {
200 .freeze = pdc_freeze, 205 .freeze = pdc_freeze,
201 .thaw = pdc_thaw, 206 .thaw = pdc_thaw,
202 .port_start = pdc_common_port_start, 207 .port_start = pdc_common_port_start,
208 .softreset = pdc_pata_softreset,
203}; 209};
204 210
205static const struct ata_port_info pdc_port_info[] = { 211static const struct ata_port_info pdc_port_info[] = {
@@ -693,6 +699,20 @@ static void pdc_sata_thaw(struct ata_port *ap)
693 readl(host_mmio + hotplug_offset); /* flush */ 699 readl(host_mmio + hotplug_offset); /* flush */
694} 700}
695 701
702static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
703 unsigned long deadline)
704{
705 pdc_reset_port(link->ap);
706 return ata_sff_softreset(link, class, deadline);
707}
708
709static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
710 unsigned long deadline)
711{
712 pdc_reset_port(link->ap);
713 return sata_sff_hardreset(link, class, deadline);
714}
715
696static void pdc_error_handler(struct ata_port *ap) 716static void pdc_error_handler(struct ata_port *ap)
697{ 717{
698 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 718 if (!(ap->pflags & ATA_PFLAG_FROZEN))
diff --git a/drivers/ata/sata_via.c b/drivers/ata/sata_via.c
index 62367fe4d5dc..c18935f0bda2 100644
--- a/drivers/ata/sata_via.c
+++ b/drivers/ata/sata_via.c
@@ -602,8 +602,10 @@ static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
602 rc = vt8251_prepare_host(pdev, &host); 602 rc = vt8251_prepare_host(pdev, &host);
603 break; 603 break;
604 default: 604 default:
605 return -EINVAL; 605 rc = -EINVAL;
606 } 606 }
607 if (rc)
608 return rc;
607 609
608 svia_configure(pdev); 610 svia_configure(pdev);
609 611
diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c
index 4023885353e0..12de1fdaa6c6 100644
--- a/drivers/block/cciss.c
+++ b/drivers/block/cciss.c
@@ -96,6 +96,8 @@ static const struct pci_device_id cciss_pci_device_id[] = {
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245}, 96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247}, 97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249}, 98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
99 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 101 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
100 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0}, 102 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
101 {0,} 103 {0,}
@@ -133,6 +135,8 @@ static struct board_type products[] = {
133 {0x3245103C, "Smart Array P410i", &SA5_access}, 135 {0x3245103C, "Smart Array P410i", &SA5_access},
134 {0x3247103C, "Smart Array P411", &SA5_access}, 136 {0x3247103C, "Smart Array P411", &SA5_access},
135 {0x3249103C, "Smart Array P812", &SA5_access}, 137 {0x3249103C, "Smart Array P812", &SA5_access},
138 {0x324A103C, "Smart Array P712m", &SA5_access},
139 {0x324B103C, "Smart Array P711m", &SA5_access},
136 {0xFFFF103C, "Unknown Smart Array", &SA5_access}, 140 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
137}; 141};
138 142
@@ -1366,6 +1370,7 @@ static void cciss_add_disk(ctlr_info_t *h, struct gendisk *disk,
1366 disk->first_minor = drv_index << NWD_SHIFT; 1370 disk->first_minor = drv_index << NWD_SHIFT;
1367 disk->fops = &cciss_fops; 1371 disk->fops = &cciss_fops;
1368 disk->private_data = &h->drv[drv_index]; 1372 disk->private_data = &h->drv[drv_index];
1373 disk->driverfs_dev = &h->pdev->dev;
1369 1374
1370 /* Set up queue information */ 1375 /* Set up queue information */
1371 blk_queue_bounce_limit(disk->queue, h->pdev->dma_mask); 1376 blk_queue_bounce_limit(disk->queue, h->pdev->dma_mask);
@@ -3404,7 +3409,8 @@ static int __devinit cciss_init_one(struct pci_dev *pdev,
3404 int i; 3409 int i;
3405 int j = 0; 3410 int j = 0;
3406 int rc; 3411 int rc;
3407 int dac; 3412 int dac, return_code;
3413 InquiryData_struct *inq_buff = NULL;
3408 3414
3409 i = alloc_cciss_hba(); 3415 i = alloc_cciss_hba();
3410 if (i < 0) 3416 if (i < 0)
@@ -3510,6 +3516,25 @@ static int __devinit cciss_init_one(struct pci_dev *pdev,
3510 /* Turn the interrupts on so we can service requests */ 3516 /* Turn the interrupts on so we can service requests */
3511 hba[i]->access.set_intr_mask(hba[i], CCISS_INTR_ON); 3517 hba[i]->access.set_intr_mask(hba[i], CCISS_INTR_ON);
3512 3518
3519 /* Get the firmware version */
3520 inq_buff = kzalloc(sizeof(InquiryData_struct), GFP_KERNEL);
3521 if (inq_buff == NULL) {
3522 printk(KERN_ERR "cciss: out of memory\n");
3523 goto clean4;
3524 }
3525
3526 return_code = sendcmd_withirq(CISS_INQUIRY, i, inq_buff,
3527 sizeof(InquiryData_struct), 0, 0 , 0, TYPE_CMD);
3528 if (return_code == IO_OK) {
3529 hba[i]->firm_ver[0] = inq_buff->data_byte[32];
3530 hba[i]->firm_ver[1] = inq_buff->data_byte[33];
3531 hba[i]->firm_ver[2] = inq_buff->data_byte[34];
3532 hba[i]->firm_ver[3] = inq_buff->data_byte[35];
3533 } else { /* send command failed */
3534 printk(KERN_WARNING "cciss: unable to determine firmware"
3535 " version of controller\n");
3536 }
3537
3513 cciss_procinit(i); 3538 cciss_procinit(i);
3514 3539
3515 hba[i]->cciss_max_sectors = 2048; 3540 hba[i]->cciss_max_sectors = 2048;
@@ -3520,6 +3545,7 @@ static int __devinit cciss_init_one(struct pci_dev *pdev,
3520 return 1; 3545 return 1;
3521 3546
3522clean4: 3547clean4:
3548 kfree(inq_buff);
3523#ifdef CONFIG_CISS_SCSI_TAPE 3549#ifdef CONFIG_CISS_SCSI_TAPE
3524 kfree(hba[i]->scsi_rejects.complete); 3550 kfree(hba[i]->scsi_rejects.complete);
3525#endif 3551#endif
diff --git a/drivers/block/cpqarray.c b/drivers/block/cpqarray.c
index 47d233c6d0b3..5d39df14ed90 100644
--- a/drivers/block/cpqarray.c
+++ b/drivers/block/cpqarray.c
@@ -567,7 +567,12 @@ static int __init cpqarray_init(void)
567 num_cntlrs_reg++; 567 num_cntlrs_reg++;
568 } 568 }
569 569
570 return(num_cntlrs_reg); 570 if (num_cntlrs_reg)
571 return 0;
572 else {
573 pci_unregister_driver(&cpqarray_pci_driver);
574 return -ENODEV;
575 }
571} 576}
572 577
573/* Function to find the first free pointer into our hba[] array */ 578/* Function to find the first free pointer into our hba[] array */
diff --git a/drivers/char/vt.c b/drivers/char/vt.c
index d8f83e26e4a4..a5af6072e2b3 100644
--- a/drivers/char/vt.c
+++ b/drivers/char/vt.c
@@ -1644,7 +1644,10 @@ static void reset_terminal(struct vc_data *vc, int do_clear)
1644 vc->vc_tab_stop[1] = 1644 vc->vc_tab_stop[1] =
1645 vc->vc_tab_stop[2] = 1645 vc->vc_tab_stop[2] =
1646 vc->vc_tab_stop[3] = 1646 vc->vc_tab_stop[3] =
1647 vc->vc_tab_stop[4] = 0x01010101; 1647 vc->vc_tab_stop[4] =
1648 vc->vc_tab_stop[5] =
1649 vc->vc_tab_stop[6] =
1650 vc->vc_tab_stop[7] = 0x01010101;
1648 1651
1649 vc->vc_bell_pitch = DEFAULT_BELL_PITCH; 1652 vc->vc_bell_pitch = DEFAULT_BELL_PITCH;
1650 vc->vc_bell_duration = DEFAULT_BELL_DURATION; 1653 vc->vc_bell_duration = DEFAULT_BELL_DURATION;
@@ -1935,7 +1938,10 @@ static void do_con_trol(struct tty_struct *tty, struct vc_data *vc, int c)
1935 vc->vc_tab_stop[1] = 1938 vc->vc_tab_stop[1] =
1936 vc->vc_tab_stop[2] = 1939 vc->vc_tab_stop[2] =
1937 vc->vc_tab_stop[3] = 1940 vc->vc_tab_stop[3] =
1938 vc->vc_tab_stop[4] = 0; 1941 vc->vc_tab_stop[4] =
1942 vc->vc_tab_stop[5] =
1943 vc->vc_tab_stop[6] =
1944 vc->vc_tab_stop[7] = 0;
1939 } 1945 }
1940 return; 1946 return;
1941 case 'm': 1947 case 'm':
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5ba78e4fd2b5..d8fb5d8ee7ea 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -3,13 +3,14 @@
3# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. 3# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
4 4
5ccflags-y := -Iinclude/drm 5ccflags-y := -Iinclude/drm
6i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o i915_opregion.o \ 6i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \
7 i915_suspend.o \ 7 i915_suspend.o \
8 i915_gem.o \ 8 i915_gem.o \
9 i915_gem_debug.o \ 9 i915_gem_debug.o \
10 i915_gem_proc.o \ 10 i915_gem_proc.o \
11 i915_gem_tiling.o 11 i915_gem_tiling.o
12 12
13i915-$(CONFIG_ACPI) += i915_opregion.o
13i915-$(CONFIG_COMPAT) += i915_ioc32.o 14i915-$(CONFIG_COMPAT) += i915_ioc32.o
14 15
15obj-$(CONFIG_DRM_I915) += i915.o 16obj-$(CONFIG_DRM_I915) += i915.o
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 01de536e0211..256e22963ae4 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -960,6 +960,7 @@ struct drm_ioctl_desc i915_ioctls[] = {
960 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0), 960 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
961 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0), 961 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
962 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0), 962 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
963 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),
963}; 964};
964 965
965int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); 966int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f20ffe17df71..572dcd0e3e0d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -31,6 +31,7 @@
31#define _I915_DRV_H_ 31#define _I915_DRV_H_
32 32
33#include "i915_reg.h" 33#include "i915_reg.h"
34#include <linux/io-mapping.h>
34 35
35/* General customization: 36/* General customization:
36 */ 37 */
@@ -246,6 +247,8 @@ typedef struct drm_i915_private {
246 struct { 247 struct {
247 struct drm_mm gtt_space; 248 struct drm_mm gtt_space;
248 249
250 struct io_mapping *gtt_mapping;
251
249 /** 252 /**
250 * List of objects currently involved in rendering from the 253 * List of objects currently involved in rendering from the
251 * ringbuffer. 254 * ringbuffer.
@@ -502,6 +505,8 @@ int i915_gem_set_tiling(struct drm_device *dev, void *data,
502 struct drm_file *file_priv); 505 struct drm_file *file_priv);
503int i915_gem_get_tiling(struct drm_device *dev, void *data, 506int i915_gem_get_tiling(struct drm_device *dev, void *data,
504 struct drm_file *file_priv); 507 struct drm_file *file_priv);
508int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
509 struct drm_file *file_priv);
505void i915_gem_load(struct drm_device *dev); 510void i915_gem_load(struct drm_device *dev);
506int i915_gem_proc_init(struct drm_minor *minor); 511int i915_gem_proc_init(struct drm_minor *minor);
507void i915_gem_proc_cleanup(struct drm_minor *minor); 512void i915_gem_proc_cleanup(struct drm_minor *minor);
@@ -539,11 +544,18 @@ extern int i915_restore_state(struct drm_device *dev);
539extern int i915_save_state(struct drm_device *dev); 544extern int i915_save_state(struct drm_device *dev);
540extern int i915_restore_state(struct drm_device *dev); 545extern int i915_restore_state(struct drm_device *dev);
541 546
547#ifdef CONFIG_ACPI
542/* i915_opregion.c */ 548/* i915_opregion.c */
543extern int intel_opregion_init(struct drm_device *dev); 549extern int intel_opregion_init(struct drm_device *dev);
544extern void intel_opregion_free(struct drm_device *dev); 550extern void intel_opregion_free(struct drm_device *dev);
545extern void opregion_asle_intr(struct drm_device *dev); 551extern void opregion_asle_intr(struct drm_device *dev);
546extern void opregion_enable_asle(struct drm_device *dev); 552extern void opregion_enable_asle(struct drm_device *dev);
553#else
554static inline int intel_opregion_init(struct drm_device *dev) { return 0; }
555static inline void intel_opregion_free(struct drm_device *dev) { return; }
556static inline void opregion_asle_intr(struct drm_device *dev) { return; }
557static inline void opregion_enable_asle(struct drm_device *dev) { return; }
558#endif
547 559
548/** 560/**
549 * Lock test for when it's just for synchronization of ring access. 561 * Lock test for when it's just for synchronization of ring access.
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 17ae330ff269..b0ec73fa6a93 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -79,6 +79,28 @@ i915_gem_init_ioctl(struct drm_device *dev, void *data,
79 return 0; 79 return 0;
80} 80}
81 81
82int
83i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
84 struct drm_file *file_priv)
85{
86 drm_i915_private_t *dev_priv = dev->dev_private;
87 struct drm_i915_gem_get_aperture *args = data;
88 struct drm_i915_gem_object *obj_priv;
89
90 if (!(dev->driver->driver_features & DRIVER_GEM))
91 return -ENODEV;
92
93 args->aper_size = dev->gtt_total;
94 args->aper_available_size = args->aper_size;
95
96 list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {
97 if (obj_priv->pin_count > 0)
98 args->aper_available_size -= obj_priv->obj->size;
99 }
100
101 return 0;
102}
103
82 104
83/** 105/**
84 * Creates a new mm object and returns a handle to it. 106 * Creates a new mm object and returns a handle to it.
@@ -171,35 +193,50 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
171 return 0; 193 return 0;
172} 194}
173 195
174/* 196/* This is the fast write path which cannot handle
175 * Try to write quickly with an atomic kmap. Return true on success. 197 * page faults in the source data
176 *
177 * If this fails (which includes a partial write), we'll redo the whole
178 * thing with the slow version.
179 *
180 * This is a workaround for the low performance of iounmap (approximate
181 * 10% cpu cost on normal 3D workloads). kmap_atomic on HIGHMEM kernels
182 * happens to let us map card memory without taking IPIs. When the vmap
183 * rework lands we should be able to dump this hack.
184 */ 198 */
185static inline int fast_user_write(unsigned long pfn, char __user *user_data, 199
186 int l, int o) 200static inline int
201fast_user_write(struct io_mapping *mapping,
202 loff_t page_base, int page_offset,
203 char __user *user_data,
204 int length)
187{ 205{
188#ifdef CONFIG_HIGHMEM
189 unsigned long unwritten;
190 char *vaddr_atomic; 206 char *vaddr_atomic;
207 unsigned long unwritten;
191 208
192 vaddr_atomic = kmap_atomic_pfn(pfn, KM_USER0); 209 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
193#if WATCH_PWRITE 210 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
194 DRM_INFO("pwrite i %d o %d l %d pfn %ld vaddr %p\n", 211 user_data, length);
195 i, o, l, pfn, vaddr_atomic); 212 io_mapping_unmap_atomic(vaddr_atomic);
196#endif 213 if (unwritten)
197 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + o, user_data, l); 214 return -EFAULT;
198 kunmap_atomic(vaddr_atomic, KM_USER0); 215 return 0;
199 return !unwritten; 216}
200#else 217
218/* Here's the write path which can sleep for
219 * page faults
220 */
221
222static inline int
223slow_user_write(struct io_mapping *mapping,
224 loff_t page_base, int page_offset,
225 char __user *user_data,
226 int length)
227{
228 char __iomem *vaddr;
229 unsigned long unwritten;
230
231 vaddr = io_mapping_map_wc(mapping, page_base);
232 if (vaddr == NULL)
233 return -EFAULT;
234 unwritten = __copy_from_user(vaddr + page_offset,
235 user_data, length);
236 io_mapping_unmap(vaddr);
237 if (unwritten)
238 return -EFAULT;
201 return 0; 239 return 0;
202#endif
203} 240}
204 241
205static int 242static int
@@ -208,10 +245,12 @@ i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
208 struct drm_file *file_priv) 245 struct drm_file *file_priv)
209{ 246{
210 struct drm_i915_gem_object *obj_priv = obj->driver_private; 247 struct drm_i915_gem_object *obj_priv = obj->driver_private;
248 drm_i915_private_t *dev_priv = dev->dev_private;
211 ssize_t remain; 249 ssize_t remain;
212 loff_t offset; 250 loff_t offset, page_base;
213 char __user *user_data; 251 char __user *user_data;
214 int ret = 0; 252 int page_offset, page_length;
253 int ret;
215 254
216 user_data = (char __user *) (uintptr_t) args->data_ptr; 255 user_data = (char __user *) (uintptr_t) args->data_ptr;
217 remain = args->size; 256 remain = args->size;
@@ -235,57 +274,37 @@ i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
235 obj_priv->dirty = 1; 274 obj_priv->dirty = 1;
236 275
237 while (remain > 0) { 276 while (remain > 0) {
238 unsigned long pfn;
239 int i, o, l;
240
241 /* Operation in this page 277 /* Operation in this page
242 * 278 *
243 * i = page number 279 * page_base = page offset within aperture
244 * o = offset within page 280 * page_offset = offset within page
245 * l = bytes to copy 281 * page_length = bytes to copy for this page
246 */ 282 */
247 i = offset >> PAGE_SHIFT; 283 page_base = (offset & ~(PAGE_SIZE-1));
248 o = offset & (PAGE_SIZE-1); 284 page_offset = offset & (PAGE_SIZE-1);
249 l = remain; 285 page_length = remain;
250 if ((o + l) > PAGE_SIZE) 286 if ((page_offset + remain) > PAGE_SIZE)
251 l = PAGE_SIZE - o; 287 page_length = PAGE_SIZE - page_offset;
252 288
253 pfn = (dev->agp->base >> PAGE_SHIFT) + i; 289 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
254 290 page_offset, user_data, page_length);
255 if (!fast_user_write(pfn, user_data, l, o)) { 291
256 unsigned long unwritten; 292 /* If we get a fault while copying data, then (presumably) our
257 char __iomem *vaddr; 293 * source page isn't available. In this case, use the
258 294 * non-atomic function
259 vaddr = ioremap_wc(pfn << PAGE_SHIFT, PAGE_SIZE); 295 */
260#if WATCH_PWRITE 296 if (ret) {
261 DRM_INFO("pwrite slow i %d o %d l %d " 297 ret = slow_user_write (dev_priv->mm.gtt_mapping,
262 "pfn %ld vaddr %p\n", 298 page_base, page_offset,
263 i, o, l, pfn, vaddr); 299 user_data, page_length);
264#endif 300 if (ret)
265 if (vaddr == NULL) {
266 ret = -EFAULT;
267 goto fail;
268 }
269 unwritten = __copy_from_user(vaddr + o, user_data, l);
270#if WATCH_PWRITE
271 DRM_INFO("unwritten %ld\n", unwritten);
272#endif
273 iounmap(vaddr);
274 if (unwritten) {
275 ret = -EFAULT;
276 goto fail; 301 goto fail;
277 }
278 } 302 }
279 303
280 remain -= l; 304 remain -= page_length;
281 user_data += l; 305 user_data += page_length;
282 offset += l; 306 offset += page_length;
283 } 307 }
284#if WATCH_PWRITE && 1
285 i915_gem_clflush_object(obj);
286 i915_gem_dump_object(obj, args->offset + args->size, __func__, ~0);
287 i915_gem_clflush_object(obj);
288#endif
289 308
290fail: 309fail:
291 i915_gem_object_unpin(obj); 310 i915_gem_object_unpin(obj);
@@ -1503,12 +1522,12 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
1503 struct drm_i915_gem_exec_object *entry) 1522 struct drm_i915_gem_exec_object *entry)
1504{ 1523{
1505 struct drm_device *dev = obj->dev; 1524 struct drm_device *dev = obj->dev;
1525 drm_i915_private_t *dev_priv = dev->dev_private;
1506 struct drm_i915_gem_relocation_entry reloc; 1526 struct drm_i915_gem_relocation_entry reloc;
1507 struct drm_i915_gem_relocation_entry __user *relocs; 1527 struct drm_i915_gem_relocation_entry __user *relocs;
1508 struct drm_i915_gem_object *obj_priv = obj->driver_private; 1528 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1509 int i, ret; 1529 int i, ret;
1510 uint32_t last_reloc_offset = -1; 1530 void __iomem *reloc_page;
1511 void __iomem *reloc_page = NULL;
1512 1531
1513 /* Choose the GTT offset for our buffer and put it there. */ 1532 /* Choose the GTT offset for our buffer and put it there. */
1514 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); 1533 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
@@ -1631,26 +1650,11 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
1631 * perform. 1650 * perform.
1632 */ 1651 */
1633 reloc_offset = obj_priv->gtt_offset + reloc.offset; 1652 reloc_offset = obj_priv->gtt_offset + reloc.offset;
1634 if (reloc_page == NULL || 1653 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
1635 (last_reloc_offset & ~(PAGE_SIZE - 1)) != 1654 (reloc_offset &
1636 (reloc_offset & ~(PAGE_SIZE - 1))) { 1655 ~(PAGE_SIZE - 1)));
1637 if (reloc_page != NULL)
1638 iounmap(reloc_page);
1639
1640 reloc_page = ioremap_wc(dev->agp->base +
1641 (reloc_offset &
1642 ~(PAGE_SIZE - 1)),
1643 PAGE_SIZE);
1644 last_reloc_offset = reloc_offset;
1645 if (reloc_page == NULL) {
1646 drm_gem_object_unreference(target_obj);
1647 i915_gem_object_unpin(obj);
1648 return -ENOMEM;
1649 }
1650 }
1651
1652 reloc_entry = (uint32_t __iomem *)(reloc_page + 1656 reloc_entry = (uint32_t __iomem *)(reloc_page +
1653 (reloc_offset & (PAGE_SIZE - 1))); 1657 (reloc_offset & (PAGE_SIZE - 1)));
1654 reloc_val = target_obj_priv->gtt_offset + reloc.delta; 1658 reloc_val = target_obj_priv->gtt_offset + reloc.delta;
1655 1659
1656#if WATCH_BUF 1660#if WATCH_BUF
@@ -1659,6 +1663,7 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
1659 readl(reloc_entry), reloc_val); 1663 readl(reloc_entry), reloc_val);
1660#endif 1664#endif
1661 writel(reloc_val, reloc_entry); 1665 writel(reloc_val, reloc_entry);
1666 io_mapping_unmap_atomic(reloc_page);
1662 1667
1663 /* Write the updated presumed offset for this entry back out 1668 /* Write the updated presumed offset for this entry back out
1664 * to the user. 1669 * to the user.
@@ -1674,9 +1679,6 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
1674 drm_gem_object_unreference(target_obj); 1679 drm_gem_object_unreference(target_obj);
1675 } 1680 }
1676 1681
1677 if (reloc_page != NULL)
1678 iounmap(reloc_page);
1679
1680#if WATCH_BUF 1682#if WATCH_BUF
1681 if (0) 1683 if (0)
1682 i915_gem_dump_object(obj, 128, __func__, ~0); 1684 i915_gem_dump_object(obj, 128, __func__, ~0);
@@ -2518,6 +2520,10 @@ i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2518 if (ret != 0) 2520 if (ret != 0)
2519 return ret; 2521 return ret;
2520 2522
2523 dev_priv->mm.gtt_mapping = io_mapping_create_wc(dev->agp->base,
2524 dev->agp->agp_info.aper_size
2525 * 1024 * 1024);
2526
2521 mutex_lock(&dev->struct_mutex); 2527 mutex_lock(&dev->struct_mutex);
2522 BUG_ON(!list_empty(&dev_priv->mm.active_list)); 2528 BUG_ON(!list_empty(&dev_priv->mm.active_list));
2523 BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); 2529 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
@@ -2535,11 +2541,13 @@ int
2535i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 2541i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2536 struct drm_file *file_priv) 2542 struct drm_file *file_priv)
2537{ 2543{
2544 drm_i915_private_t *dev_priv = dev->dev_private;
2538 int ret; 2545 int ret;
2539 2546
2540 ret = i915_gem_idle(dev); 2547 ret = i915_gem_idle(dev);
2541 drm_irq_uninstall(dev); 2548 drm_irq_uninstall(dev);
2542 2549
2550 io_mapping_free(dev_priv->mm.gtt_mapping);
2543 return ret; 2551 return ret;
2544} 2552}
2545 2553
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index 59a2132a8f57..073894824e6b 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -653,15 +653,16 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
653 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); 653 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
654 654
655 /* Turn on bus mastering */ 655 /* Turn on bus mastering */
656 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || 656 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
657 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
658 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { 657 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
659 /* rs400, rs690/rs740 */ 658 /* rs600/rs690/rs740 */
660 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS400_BUS_MASTER_DIS; 659 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
661 RADEON_WRITE(RADEON_BUS_CNTL, tmp); 660 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
662 } else if (!(((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || 661 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
663 ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R423))) { 662 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
664 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */ 663 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
664 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
665 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
665 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 666 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
666 RADEON_WRITE(RADEON_BUS_CNTL, tmp); 667 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
667 } /* PCIE cards appears to not need this */ 668 } /* PCIE cards appears to not need this */
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 4dbb813910c3..02f5575ba395 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -447,12 +447,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
447 * handling, not bus mastering itself. 447 * handling, not bus mastering itself.
448 */ 448 */
449#define RADEON_BUS_CNTL 0x0030 449#define RADEON_BUS_CNTL 0x0030
450/* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */ 450/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
451# define RADEON_BUS_MASTER_DIS (1 << 6) 451# define RADEON_BUS_MASTER_DIS (1 << 6)
452/* rs400, rs690/rs740 */ 452/* rs600/rs690/rs740 */
453# define RS400_BUS_MASTER_DIS (1 << 14) 453# define RS600_BUS_MASTER_DIS (1 << 14)
454# define RS400_MSI_REARM (1 << 20) 454# define RS600_MSI_REARM (1 << 20)
455/* see RS480_MSI_REARM in AIC_CNTL for rs480 */ 455/* see RS400_MSI_REARM in AIC_CNTL for rs480 */
456 456
457#define RADEON_BUS_CNTL1 0x0034 457#define RADEON_BUS_CNTL1 0x0034
458# define RADEON_PMI_BM_DIS (1 << 2) 458# define RADEON_PMI_BM_DIS (1 << 2)
@@ -937,7 +937,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
937 937
938#define RADEON_AIC_CNTL 0x01d0 938#define RADEON_AIC_CNTL 0x01d0
939# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 939# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
940# define RS480_MSI_REARM (1 << 3) 940# define RS400_MSI_REARM (1 << 3)
941#define RADEON_AIC_STAT 0x01d4 941#define RADEON_AIC_STAT 0x01d4
942#define RADEON_AIC_PT_BASE 0x01d8 942#define RADEON_AIC_PT_BASE 0x01d8
943#define RADEON_AIC_LO_ADDR 0x01dc 943#define RADEON_AIC_LO_ADDR 0x01dc
diff --git a/drivers/hwmon/applesmc.c b/drivers/hwmon/applesmc.c
index bc011da79e14..be3285912cb7 100644
--- a/drivers/hwmon/applesmc.c
+++ b/drivers/hwmon/applesmc.c
@@ -116,6 +116,18 @@ static const char* temperature_sensors_sets[][36] = {
116/* Set 9: Macbook Pro 3,1 (Santa Rosa) */ 116/* Set 9: Macbook Pro 3,1 (Santa Rosa) */
117 { "TALP", "TB0T", "TC0D", "TC0P", "TG0D", "TG0H", "TTF0", "TW0P", 117 { "TALP", "TB0T", "TC0D", "TC0P", "TG0D", "TG0H", "TTF0", "TW0P",
118 "Th0H", "Th1H", "Th2H", "Tm0P", "Ts0P", NULL }, 118 "Th0H", "Th1H", "Th2H", "Tm0P", "Ts0P", NULL },
119/* Set 10: iMac 5,1 */
120 { "TA0P", "TC0D", "TC0P", "TG0D", "TH0P", "TO0P", "Tm0P", NULL },
121/* Set 11: Macbook 5,1 */
122 { "TB0T", "TB1T", "TB2T", "TB3T", "TC0D", "TC0P", "TN0D", "TN0P",
123 "TTF0", "Th0H", "Th1H", "ThFH", "Ts0P", "Ts0S", NULL },
124/* Set 12: Macbook Pro 5,1 */
125 { "TB0T", "TB1T", "TB2T", "TB3T", "TC0D", "TC0F", "TC0P", "TG0D",
126 "TG0F", "TG0H", "TG0P", "TG0T", "TG1H", "TN0D", "TN0P", "TTF0",
127 "Th2H", "Tm0P", "Ts0P", "Ts0S", NULL },
128/* Set 13: iMac 8,1 */
129 { "TA0P", "TC0D", "TC0H", "TC0P", "TG0D", "TG0H", "TG0P", "TH0P",
130 "TL0P", "TO0P", "TW0P", "Tm0P", "Tp0P", NULL },
119}; 131};
120 132
121/* List of keys used to read/write fan speeds */ 133/* List of keys used to read/write fan speeds */
@@ -1276,6 +1288,14 @@ static __initdata struct dmi_match_data applesmc_dmi_data[] = {
1276 { .accelerometer = 1, .light = 1, .temperature_set = 8 }, 1288 { .accelerometer = 1, .light = 1, .temperature_set = 8 },
1277/* MacBook Pro 3: accelerometer, backlight and temperature set 9 */ 1289/* MacBook Pro 3: accelerometer, backlight and temperature set 9 */
1278 { .accelerometer = 1, .light = 1, .temperature_set = 9 }, 1290 { .accelerometer = 1, .light = 1, .temperature_set = 9 },
1291/* iMac 5: light sensor only, temperature set 10 */
1292 { .accelerometer = 0, .light = 0, .temperature_set = 10 },
1293/* MacBook 5: accelerometer, backlight and temperature set 11 */
1294 { .accelerometer = 1, .light = 1, .temperature_set = 11 },
1295/* MacBook Pro 5: accelerometer, backlight and temperature set 12 */
1296 { .accelerometer = 1, .light = 1, .temperature_set = 12 },
1297/* iMac 8: light sensor only, temperature set 13 */
1298 { .accelerometer = 0, .light = 0, .temperature_set = 13 },
1279}; 1299};
1280 1300
1281/* Note that DMI_MATCH(...,"MacBook") will match "MacBookPro1,1". 1301/* Note that DMI_MATCH(...,"MacBook") will match "MacBookPro1,1".
@@ -1285,6 +1305,10 @@ static __initdata struct dmi_system_id applesmc_whitelist[] = {
1285 DMI_MATCH(DMI_BOARD_VENDOR, "Apple"), 1305 DMI_MATCH(DMI_BOARD_VENDOR, "Apple"),
1286 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookAir") }, 1306 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookAir") },
1287 &applesmc_dmi_data[7]}, 1307 &applesmc_dmi_data[7]},
1308 { applesmc_dmi_match, "Apple MacBook Pro 5", {
1309 DMI_MATCH(DMI_BOARD_VENDOR, "Apple"),
1310 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro5") },
1311 &applesmc_dmi_data[12]},
1288 { applesmc_dmi_match, "Apple MacBook Pro 4", { 1312 { applesmc_dmi_match, "Apple MacBook Pro 4", {
1289 DMI_MATCH(DMI_BOARD_VENDOR, "Apple"), 1313 DMI_MATCH(DMI_BOARD_VENDOR, "Apple"),
1290 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro4") }, 1314 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro4") },
@@ -1305,6 +1329,10 @@ static __initdata struct dmi_system_id applesmc_whitelist[] = {
1305 DMI_MATCH(DMI_BOARD_VENDOR,"Apple"), 1329 DMI_MATCH(DMI_BOARD_VENDOR,"Apple"),
1306 DMI_MATCH(DMI_PRODUCT_NAME,"MacBook3") }, 1330 DMI_MATCH(DMI_PRODUCT_NAME,"MacBook3") },
1307 &applesmc_dmi_data[6]}, 1331 &applesmc_dmi_data[6]},
1332 { applesmc_dmi_match, "Apple MacBook 5", {
1333 DMI_MATCH(DMI_BOARD_VENDOR, "Apple"),
1334 DMI_MATCH(DMI_PRODUCT_NAME, "MacBook5") },
1335 &applesmc_dmi_data[11]},
1308 { applesmc_dmi_match, "Apple MacBook", { 1336 { applesmc_dmi_match, "Apple MacBook", {
1309 DMI_MATCH(DMI_BOARD_VENDOR,"Apple"), 1337 DMI_MATCH(DMI_BOARD_VENDOR,"Apple"),
1310 DMI_MATCH(DMI_PRODUCT_NAME,"MacBook") }, 1338 DMI_MATCH(DMI_PRODUCT_NAME,"MacBook") },
@@ -1317,6 +1345,14 @@ static __initdata struct dmi_system_id applesmc_whitelist[] = {
1317 DMI_MATCH(DMI_BOARD_VENDOR,"Apple"), 1345 DMI_MATCH(DMI_BOARD_VENDOR,"Apple"),
1318 DMI_MATCH(DMI_PRODUCT_NAME,"MacPro2") }, 1346 DMI_MATCH(DMI_PRODUCT_NAME,"MacPro2") },
1319 &applesmc_dmi_data[4]}, 1347 &applesmc_dmi_data[4]},
1348 { applesmc_dmi_match, "Apple iMac 8", {
1349 DMI_MATCH(DMI_BOARD_VENDOR, "Apple"),
1350 DMI_MATCH(DMI_PRODUCT_NAME, "iMac8") },
1351 &applesmc_dmi_data[13]},
1352 { applesmc_dmi_match, "Apple iMac 5", {
1353 DMI_MATCH(DMI_BOARD_VENDOR, "Apple"),
1354 DMI_MATCH(DMI_PRODUCT_NAME, "iMac5") },
1355 &applesmc_dmi_data[10]},
1320 { applesmc_dmi_match, "Apple iMac", { 1356 { applesmc_dmi_match, "Apple iMac", {
1321 DMI_MATCH(DMI_BOARD_VENDOR,"Apple"), 1357 DMI_MATCH(DMI_BOARD_VENDOR,"Apple"),
1322 DMI_MATCH(DMI_PRODUCT_NAME,"iMac") }, 1358 DMI_MATCH(DMI_PRODUCT_NAME,"iMac") },
diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c
index 3e6f5d8609e8..d74ec46aa032 100644
--- a/drivers/mtd/chips/cfi_cmdset_0002.c
+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
@@ -406,19 +406,6 @@ struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
406 /* Set the default CFI lock/unlock addresses */ 406 /* Set the default CFI lock/unlock addresses */
407 cfi->addr_unlock1 = 0x555; 407 cfi->addr_unlock1 = 0x555;
408 cfi->addr_unlock2 = 0x2aa; 408 cfi->addr_unlock2 = 0x2aa;
409 /* Modify the unlock address if we are in compatibility mode */
410 if ( /* x16 in x8 mode */
411 ((cfi->device_type == CFI_DEVICETYPE_X8) &&
412 (cfi->cfiq->InterfaceDesc ==
413 CFI_INTERFACE_X8_BY_X16_ASYNC)) ||
414 /* x32 in x16 mode */
415 ((cfi->device_type == CFI_DEVICETYPE_X16) &&
416 (cfi->cfiq->InterfaceDesc ==
417 CFI_INTERFACE_X16_BY_X32_ASYNC)))
418 {
419 cfi->addr_unlock1 = 0xaaa;
420 cfi->addr_unlock2 = 0x555;
421 }
422 409
423 } /* CFI mode */ 410 } /* CFI mode */
424 else if (cfi->cfi_mode == CFI_MODE_JEDEC) { 411 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
diff --git a/drivers/mtd/chips/jedec_probe.c b/drivers/mtd/chips/jedec_probe.c
index f84ab6182148..2f3f2f719ba4 100644
--- a/drivers/mtd/chips/jedec_probe.c
+++ b/drivers/mtd/chips/jedec_probe.c
@@ -1808,9 +1808,7 @@ static inline u32 jedec_read_mfr(struct map_info *map, uint32_t base,
1808 * several first banks can contain 0x7f instead of actual ID 1808 * several first banks can contain 0x7f instead of actual ID
1809 */ 1809 */
1810 do { 1810 do {
1811 uint32_t ofs = cfi_build_cmd_addr(0 + (bank << 8), 1811 uint32_t ofs = cfi_build_cmd_addr(0 + (bank << 8), map, cfi);
1812 cfi_interleave(cfi),
1813 cfi->device_type);
1814 mask = (1 << (cfi->device_type * 8)) - 1; 1812 mask = (1 << (cfi->device_type * 8)) - 1;
1815 result = map_read(map, base + ofs); 1813 result = map_read(map, base + ofs);
1816 bank++; 1814 bank++;
@@ -1824,7 +1822,7 @@ static inline u32 jedec_read_id(struct map_info *map, uint32_t base,
1824{ 1822{
1825 map_word result; 1823 map_word result;
1826 unsigned long mask; 1824 unsigned long mask;
1827 u32 ofs = cfi_build_cmd_addr(1, cfi_interleave(cfi), cfi->device_type); 1825 u32 ofs = cfi_build_cmd_addr(1, map, cfi);
1828 mask = (1 << (cfi->device_type * 8)) -1; 1826 mask = (1 << (cfi->device_type * 8)) -1;
1829 result = map_read(map, base + ofs); 1827 result = map_read(map, base + ofs);
1830 return result.x[0] & mask; 1828 return result.x[0] & mask;
@@ -2067,8 +2065,8 @@ static int jedec_probe_chip(struct map_info *map, __u32 base,
2067 2065
2068 } 2066 }
2069 /* Ensure the unlock addresses we try stay inside the map */ 2067 /* Ensure the unlock addresses we try stay inside the map */
2070 probe_offset1 = cfi_build_cmd_addr(cfi->addr_unlock1, cfi_interleave(cfi), cfi->device_type); 2068 probe_offset1 = cfi_build_cmd_addr(cfi->addr_unlock1, map, cfi);
2071 probe_offset2 = cfi_build_cmd_addr(cfi->addr_unlock2, cfi_interleave(cfi), cfi->device_type); 2069 probe_offset2 = cfi_build_cmd_addr(cfi->addr_unlock2, map, cfi);
2072 if ( ((base + probe_offset1 + map_bankwidth(map)) >= map->size) || 2070 if ( ((base + probe_offset1 + map_bankwidth(map)) >= map->size) ||
2073 ((base + probe_offset2 + map_bankwidth(map)) >= map->size)) 2071 ((base + probe_offset2 + map_bankwidth(map)) >= map->size))
2074 goto retry; 2072 goto retry;
diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index 8387e05daae2..e39b21d3e168 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -38,7 +38,6 @@
38#include <asm/arch/gpmc.h> 38#include <asm/arch/gpmc.h>
39#include <asm/arch/onenand.h> 39#include <asm/arch/onenand.h>
40#include <asm/arch/gpio.h> 40#include <asm/arch/gpio.h>
41#include <asm/arch/gpmc.h>
42#include <asm/arch/pm.h> 41#include <asm/arch/pm.h>
43 42
44#include <linux/dma-mapping.h> 43#include <linux/dma-mapping.h>
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index f749b40f954e..11f143f4adf6 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2010,9 +2010,13 @@ config IGB_LRO
2010 If in doubt, say N. 2010 If in doubt, say N.
2011 2011
2012config IGB_DCA 2012config IGB_DCA
2013 bool "Enable DCA" 2013 bool "Direct Cache Access (DCA) Support"
2014 default y 2014 default y
2015 depends on IGB && DCA && !(IGB=y && DCA=m) 2015 depends on IGB && DCA && !(IGB=y && DCA=m)
2016 ---help---
2017 Say Y here if you want to use Direct Cache Access (DCA) in the
2018 driver. DCA is a method for warming the CPU cache before data
2019 is used, with the intent of lessening the impact of cache misses.
2016 2020
2017source "drivers/net/ixp2000/Kconfig" 2021source "drivers/net/ixp2000/Kconfig"
2018 2022
@@ -2437,9 +2441,13 @@ config IXGBE
2437 will be called ixgbe. 2441 will be called ixgbe.
2438 2442
2439config IXGBE_DCA 2443config IXGBE_DCA
2440 bool 2444 bool "Direct Cache Access (DCA) Support"
2441 default y 2445 default y
2442 depends on IXGBE && DCA && !(IXGBE=y && DCA=m) 2446 depends on IXGBE && DCA && !(IXGBE=y && DCA=m)
2447 ---help---
2448 Say Y here if you want to use Direct Cache Access (DCA) in the
2449 driver. DCA is a method for warming the CPU cache before data
2450 is used, with the intent of lessening the impact of cache misses.
2443 2451
2444config IXGB 2452config IXGB
2445 tristate "Intel(R) PRO/10GbE support" 2453 tristate "Intel(R) PRO/10GbE support"
@@ -2489,9 +2497,13 @@ config MYRI10GE
2489 will be called myri10ge. 2497 will be called myri10ge.
2490 2498
2491config MYRI10GE_DCA 2499config MYRI10GE_DCA
2492 bool 2500 bool "Direct Cache Access (DCA) Support"
2493 default y 2501 default y
2494 depends on MYRI10GE && DCA && !(MYRI10GE=y && DCA=m) 2502 depends on MYRI10GE && DCA && !(MYRI10GE=y && DCA=m)
2503 ---help---
2504 Say Y here if you want to use Direct Cache Access (DCA) in the
2505 driver. DCA is a method for warming the CPU cache before data
2506 is used, with the intent of lessening the impact of cache misses.
2495 2507
2496config NETXEN_NIC 2508config NETXEN_NIC
2497 tristate "NetXen Multi port (1/10) Gigabit Ethernet NIC" 2509 tristate "NetXen Multi port (1/10) Gigabit Ethernet NIC"
diff --git a/drivers/net/atl1e/atl1e.h b/drivers/net/atl1e/atl1e.h
index b645fa0f3f64..c49550d507a0 100644
--- a/drivers/net/atl1e/atl1e.h
+++ b/drivers/net/atl1e/atl1e.h
@@ -46,7 +46,6 @@
46#include <linux/vmalloc.h> 46#include <linux/vmalloc.h>
47#include <linux/pagemap.h> 47#include <linux/pagemap.h>
48#include <linux/tcp.h> 48#include <linux/tcp.h>
49#include <linux/mii.h>
50#include <linux/ethtool.h> 49#include <linux/ethtool.h>
51#include <linux/if_vlan.h> 50#include <linux/if_vlan.h>
52#include <linux/workqueue.h> 51#include <linux/workqueue.h>
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
index 130927cfc75b..a6c0b3abba29 100644
--- a/drivers/net/bnx2x_init.h
+++ b/drivers/net/bnx2x_init.h
@@ -564,14 +564,15 @@ static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
564 564
565static void bnx2x_init_pxp(struct bnx2x *bp) 565static void bnx2x_init_pxp(struct bnx2x *bp)
566{ 566{
567 u16 devctl;
567 int r_order, w_order; 568 int r_order, w_order;
568 u32 val, i; 569 u32 val, i;
569 570
570 pci_read_config_word(bp->pdev, 571 pci_read_config_word(bp->pdev,
571 bp->pcie_cap + PCI_EXP_DEVCTL, (u16 *)&val); 572 bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
572 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", (u16)val); 573 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
573 w_order = ((val & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 574 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
574 r_order = ((val & PCI_EXP_DEVCTL_READRQ) >> 12); 575 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
575 576
576 if (r_order > MAX_RD_ORD) { 577 if (r_order > MAX_RD_ORD) {
577 DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n", 578 DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n",
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index fce745148ff9..600210d7eff9 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -59,8 +59,8 @@
59#include "bnx2x.h" 59#include "bnx2x.h"
60#include "bnx2x_init.h" 60#include "bnx2x_init.h"
61 61
62#define DRV_MODULE_VERSION "1.45.22" 62#define DRV_MODULE_VERSION "1.45.23"
63#define DRV_MODULE_RELDATE "2008/09/09" 63#define DRV_MODULE_RELDATE "2008/11/03"
64#define BNX2X_BC_VER 0x040200 64#define BNX2X_BC_VER 0x040200
65 65
66/* Time in jiffies before concluding the transmitter is hung */ 66/* Time in jiffies before concluding the transmitter is hung */
@@ -6481,6 +6481,7 @@ load_int_disable:
6481 bnx2x_free_irq(bp); 6481 bnx2x_free_irq(bp);
6482load_error: 6482load_error:
6483 bnx2x_free_mem(bp); 6483 bnx2x_free_mem(bp);
6484 bp->port.pmf = 0;
6484 6485
6485 /* TBD we really need to reset the chip 6486 /* TBD we really need to reset the chip
6486 if we want to recover from this */ 6487 if we want to recover from this */
@@ -6791,6 +6792,7 @@ unload_error:
6791 /* Report UNLOAD_DONE to MCP */ 6792 /* Report UNLOAD_DONE to MCP */
6792 if (!BP_NOMCP(bp)) 6793 if (!BP_NOMCP(bp))
6793 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE); 6794 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
6795 bp->port.pmf = 0;
6794 6796
6795 /* Free SKBs, SGEs, TPA pool and driver internals */ 6797 /* Free SKBs, SGEs, TPA pool and driver internals */
6796 bnx2x_free_skbs(bp); 6798 bnx2x_free_skbs(bp);
@@ -10204,8 +10206,6 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10204 return -ENOMEM; 10206 return -ENOMEM;
10205 } 10207 }
10206 10208
10207 netif_carrier_off(dev);
10208
10209 bp = netdev_priv(dev); 10209 bp = netdev_priv(dev);
10210 bp->msglevel = debug; 10210 bp->msglevel = debug;
10211 10211
@@ -10229,6 +10229,8 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10229 goto init_one_exit; 10229 goto init_one_exit;
10230 } 10230 }
10231 10231
10232 netif_carrier_off(dev);
10233
10232 bp->common.name = board_info[ent->driver_data].name; 10234 bp->common.name = board_info[ent->driver_data].name;
10233 printk(KERN_INFO "%s: %s (%c%d) PCI-E x%d %s found at mem %lx," 10235 printk(KERN_INFO "%s: %s (%c%d) PCI-E x%d %s found at mem %lx,"
10234 " IRQ %d, ", dev->name, bp->common.name, 10236 " IRQ %d, ", dev->name, bp->common.name,
diff --git a/drivers/net/fs_enet/fs_enet-main.c b/drivers/net/fs_enet/fs_enet-main.c
index cb51c1fb0338..a6f49d025787 100644
--- a/drivers/net/fs_enet/fs_enet-main.c
+++ b/drivers/net/fs_enet/fs_enet-main.c
@@ -1099,7 +1099,9 @@ static int __devinit fs_enet_probe(struct of_device *ofdev,
1099 ndev->stop = fs_enet_close; 1099 ndev->stop = fs_enet_close;
1100 ndev->get_stats = fs_enet_get_stats; 1100 ndev->get_stats = fs_enet_get_stats;
1101 ndev->set_multicast_list = fs_set_multicast_list; 1101 ndev->set_multicast_list = fs_set_multicast_list;
1102 1102#ifdef CONFIG_NET_POLL_CONTROLLER
1103 ndev->poll_controller = fs_enet_netpoll;
1104#endif
1103 if (fpi->use_napi) 1105 if (fpi->use_napi)
1104 netif_napi_add(ndev, &fep->napi, fs_enet_rx_napi, 1106 netif_napi_add(ndev, &fep->napi, fs_enet_rx_napi,
1105 fpi->napi_weight); 1107 fpi->napi_weight);
@@ -1209,7 +1211,7 @@ static void __exit fs_cleanup(void)
1209static void fs_enet_netpoll(struct net_device *dev) 1211static void fs_enet_netpoll(struct net_device *dev)
1210{ 1212{
1211 disable_irq(dev->irq); 1213 disable_irq(dev->irq);
1212 fs_enet_interrupt(dev->irq, dev, NULL); 1214 fs_enet_interrupt(dev->irq, dev);
1213 enable_irq(dev->irq); 1215 enable_irq(dev->irq);
1214} 1216}
1215#endif 1217#endif
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index a9c8c08044b1..b9dcdbd369f8 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -1066,9 +1066,12 @@ static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1066 return 0; 1066 return 0;
1067 } 1067 }
1068 1068
1069 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp), 1069 if (!smi_is_done(msp)) {
1070 msecs_to_jiffies(100))) 1070 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1071 return -ETIMEDOUT; 1071 msecs_to_jiffies(100));
1072 if (!smi_is_done(msp))
1073 return -ETIMEDOUT;
1074 }
1072 1075
1073 return 0; 1076 return 0;
1074} 1077}
diff --git a/drivers/net/niu.c b/drivers/net/niu.c
index ebc812702903..9acb5d70a3ae 100644
--- a/drivers/net/niu.c
+++ b/drivers/net/niu.c
@@ -8667,7 +8667,6 @@ static void __devinit niu_device_announce(struct niu *np)
8667static int __devinit niu_pci_init_one(struct pci_dev *pdev, 8667static int __devinit niu_pci_init_one(struct pci_dev *pdev,
8668 const struct pci_device_id *ent) 8668 const struct pci_device_id *ent)
8669{ 8669{
8670 unsigned long niureg_base, niureg_len;
8671 union niu_parent_id parent_id; 8670 union niu_parent_id parent_id;
8672 struct net_device *dev; 8671 struct net_device *dev;
8673 struct niu *np; 8672 struct niu *np;
@@ -8758,10 +8757,7 @@ static int __devinit niu_pci_init_one(struct pci_dev *pdev,
8758 8757
8759 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM); 8758 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
8760 8759
8761 niureg_base = pci_resource_start(pdev, 0); 8760 np->regs = pci_ioremap_bar(pdev, 0);
8762 niureg_len = pci_resource_len(pdev, 0);
8763
8764 np->regs = ioremap_nocache(niureg_base, niureg_len);
8765 if (!np->regs) { 8761 if (!np->regs) {
8766 dev_err(&pdev->dev, PFX "Cannot map device registers, " 8762 dev_err(&pdev->dev, PFX "Cannot map device registers, "
8767 "aborting.\n"); 8763 "aborting.\n");
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index f59c7772f344..5051554ff05b 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -499,7 +499,7 @@ static void smc911x_hardware_send_pkt(struct net_device *dev)
499#else 499#else
500 SMC_PUSH_DATA(lp, buf, len); 500 SMC_PUSH_DATA(lp, buf, len);
501 dev->trans_start = jiffies; 501 dev->trans_start = jiffies;
502 dev_kfree_skb(skb); 502 dev_kfree_skb_irq(skb);
503#endif 503#endif
504 if (!lp->tx_throttle) { 504 if (!lp->tx_throttle) {
505 netif_wake_queue(dev); 505 netif_wake_queue(dev);
diff --git a/drivers/net/smc91x.c b/drivers/net/smc91x.c
index 6f9895d4e5bd..fc80f250da31 100644
--- a/drivers/net/smc91x.c
+++ b/drivers/net/smc91x.c
@@ -2060,6 +2060,7 @@ static int smc_request_attrib(struct platform_device *pdev,
2060 struct net_device *ndev) 2060 struct net_device *ndev)
2061{ 2061{
2062 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); 2062 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2063 struct smc_local *lp __maybe_unused = netdev_priv(ndev);
2063 2064
2064 if (!res) 2065 if (!res)
2065 return 0; 2066 return 0;
@@ -2074,6 +2075,7 @@ static void smc_release_attrib(struct platform_device *pdev,
2074 struct net_device *ndev) 2075 struct net_device *ndev)
2075{ 2076{
2076 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); 2077 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2078 struct smc_local *lp __maybe_unused = netdev_priv(ndev);
2077 2079
2078 if (res) 2080 if (res)
2079 release_mem_region(res->start, ATTRIB_SIZE); 2081 release_mem_region(res->start, ATTRIB_SIZE);
diff --git a/drivers/net/ucc_geth_ethtool.c b/drivers/net/ucc_geth_ethtool.c
index cfbbfee55836..85f38a6b6a49 100644
--- a/drivers/net/ucc_geth_ethtool.c
+++ b/drivers/net/ucc_geth_ethtool.c
@@ -37,7 +37,6 @@
37#include <asm/irq.h> 37#include <asm/irq.h>
38#include <asm/uaccess.h> 38#include <asm/uaccess.h>
39#include <asm/types.h> 39#include <asm/types.h>
40#include <asm/uaccess.h>
41 40
42#include "ucc_geth.h" 41#include "ucc_geth.h"
43#include "ucc_geth_mii.h" 42#include "ucc_geth_mii.h"
diff --git a/drivers/pnp/interface.c b/drivers/pnp/interface.c
index 478a4a739c00..c3f1c8e9d254 100644
--- a/drivers/pnp/interface.c
+++ b/drivers/pnp/interface.c
@@ -12,7 +12,6 @@
12#include <linux/errno.h> 12#include <linux/errno.h>
13#include <linux/list.h> 13#include <linux/list.h>
14#include <linux/types.h> 14#include <linux/types.h>
15#include <linux/pnp.h>
16#include <linux/stat.h> 15#include <linux/stat.h>
17#include <linux/ctype.h> 16#include <linux/ctype.h>
18#include <linux/slab.h> 17#include <linux/slab.h>
diff --git a/drivers/ps3/ps3-lpm.c b/drivers/ps3/ps3-lpm.c
index 85edf945ab86..204158cf7a55 100644
--- a/drivers/ps3/ps3-lpm.c
+++ b/drivers/ps3/ps3-lpm.c
@@ -22,6 +22,7 @@
22#include <linux/module.h> 22#include <linux/module.h>
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/uaccess.h> 24#include <linux/uaccess.h>
25#include <asm/smp.h>
25#include <asm/time.h> 26#include <asm/time.h>
26#include <asm/ps3.h> 27#include <asm/ps3.h>
27#include <asm/lv1call.h> 28#include <asm/lv1call.h>
diff --git a/drivers/rtc/interface.c b/drivers/rtc/interface.c
index 7af60b98d8a4..a04c1b6b1575 100644
--- a/drivers/rtc/interface.c
+++ b/drivers/rtc/interface.c
@@ -271,7 +271,7 @@ int rtc_read_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm)
271 dev_dbg(&rtc->dev, "alarm rollover: %s\n", "year"); 271 dev_dbg(&rtc->dev, "alarm rollover: %s\n", "year");
272 do { 272 do {
273 alarm->time.tm_year++; 273 alarm->time.tm_year++;
274 } while (!rtc_valid_tm(&alarm->time)); 274 } while (rtc_valid_tm(&alarm->time) != 0);
275 break; 275 break;
276 276
277 default: 277 default:
diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c
index 5549231179a2..6cf8e282338f 100644
--- a/drivers/rtc/rtc-cmos.c
+++ b/drivers/rtc/rtc-cmos.c
@@ -794,7 +794,7 @@ cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq)
794 goto cleanup2; 794 goto cleanup2;
795 } 795 }
796 796
797 pr_info("%s: alarms up to one %s%s, %zd bytes nvram, %s irqs\n", 797 pr_info("%s: alarms up to one %s%s, %zd bytes nvram%s\n",
798 cmos_rtc.rtc->dev.bus_id, 798 cmos_rtc.rtc->dev.bus_id,
799 is_valid_irq(rtc_irq) 799 is_valid_irq(rtc_irq)
800 ? (cmos_rtc.mon_alrm 800 ? (cmos_rtc.mon_alrm
diff --git a/drivers/sbus/char/jsflash.c b/drivers/sbus/char/jsflash.c
index 2bec9ccc0293..a9a9893a5f95 100644
--- a/drivers/sbus/char/jsflash.c
+++ b/drivers/sbus/char/jsflash.c
@@ -36,7 +36,6 @@
36#include <linux/poll.h> 36#include <linux/poll.h>
37#include <linux/init.h> 37#include <linux/init.h>
38#include <linux/string.h> 38#include <linux/string.h>
39#include <linux/smp_lock.h>
40#include <linux/genhd.h> 39#include <linux/genhd.h>
41#include <linux/blkdev.h> 40#include <linux/blkdev.h>
42 41
diff --git a/drivers/serial/atmel_serial.c b/drivers/serial/atmel_serial.c
index 61fb8b6d19af..d5efd6c77904 100644
--- a/drivers/serial/atmel_serial.c
+++ b/drivers/serial/atmel_serial.c
@@ -1258,6 +1258,8 @@ static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
1258 atmel_port->clk = clk_get(&pdev->dev, "usart"); 1258 atmel_port->clk = clk_get(&pdev->dev, "usart");
1259 clk_enable(atmel_port->clk); 1259 clk_enable(atmel_port->clk);
1260 port->uartclk = clk_get_rate(atmel_port->clk); 1260 port->uartclk = clk_get_rate(atmel_port->clk);
1261 clk_disable(atmel_port->clk);
1262 /* only enable clock when USART is in use */
1261 } 1263 }
1262 1264
1263 atmel_port->use_dma_rx = data->use_dma_rx; 1265 atmel_port->use_dma_rx = data->use_dma_rx;
@@ -1379,6 +1381,8 @@ static int __init atmel_console_setup(struct console *co, char *options)
1379 return -ENODEV; 1381 return -ENODEV;
1380 } 1382 }
1381 1383
1384 clk_enable(atmel_ports[co->index].clk);
1385
1382 UART_PUT_IDR(port, -1); 1386 UART_PUT_IDR(port, -1);
1383 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 1387 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1384 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); 1388 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
@@ -1403,7 +1407,7 @@ static struct console atmel_console = {
1403 .data = &atmel_uart, 1407 .data = &atmel_uart,
1404}; 1408};
1405 1409
1406#define ATMEL_CONSOLE_DEVICE &atmel_console 1410#define ATMEL_CONSOLE_DEVICE (&atmel_console)
1407 1411
1408/* 1412/*
1409 * Early console initialization (before VM subsystem initialized). 1413 * Early console initialization (before VM subsystem initialized).
@@ -1534,6 +1538,15 @@ static int __devinit atmel_serial_probe(struct platform_device *pdev)
1534 if (ret) 1538 if (ret)
1535 goto err_add_port; 1539 goto err_add_port;
1536 1540
1541 if (atmel_is_console_port(&port->uart)
1542 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
1543 /*
1544 * The serial core enabled the clock for us, so undo
1545 * the clk_enable() in atmel_console_setup()
1546 */
1547 clk_disable(port->clk);
1548 }
1549
1537 device_init_wakeup(&pdev->dev, 1); 1550 device_init_wakeup(&pdev->dev, 1);
1538 platform_set_drvdata(pdev, port); 1551 platform_set_drvdata(pdev, port);
1539 1552
@@ -1544,7 +1557,6 @@ err_add_port:
1544 port->rx_ring.buf = NULL; 1557 port->rx_ring.buf = NULL;
1545err_alloc_ring: 1558err_alloc_ring:
1546 if (!atmel_is_console_port(&port->uart)) { 1559 if (!atmel_is_console_port(&port->uart)) {
1547 clk_disable(port->clk);
1548 clk_put(port->clk); 1560 clk_put(port->clk);
1549 port->clk = NULL; 1561 port->clk = NULL;
1550 } 1562 }
@@ -1568,7 +1580,6 @@ static int __devexit atmel_serial_remove(struct platform_device *pdev)
1568 1580
1569 /* "port" is allocated statically, so we shouldn't free it */ 1581 /* "port" is allocated statically, so we shouldn't free it */
1570 1582
1571 clk_disable(atmel_port->clk);
1572 clk_put(atmel_port->clk); 1583 clk_put(atmel_port->clk);
1573 1584
1574 return ret; 1585 return ret;
diff --git a/drivers/staging/echo/echo.c b/drivers/staging/echo/echo.c
index b8f2c5e9dee5..fd4007e329e7 100644
--- a/drivers/staging/echo/echo.c
+++ b/drivers/staging/echo/echo.c
@@ -106,7 +106,6 @@
106 106
107#include <linux/kernel.h> /* We're doing kernel work */ 107#include <linux/kernel.h> /* We're doing kernel work */
108#include <linux/module.h> 108#include <linux/module.h>
109#include <linux/kernel.h>
110#include <linux/slab.h> 109#include <linux/slab.h>
111 110
112#include "bit_operations.h" 111#include "bit_operations.h"
diff --git a/drivers/staging/me4000/me4000.c b/drivers/staging/me4000/me4000.c
index cf8b01bcac8d..0394e2709278 100644
--- a/drivers/staging/me4000/me4000.c
+++ b/drivers/staging/me4000/me4000.c
@@ -39,7 +39,6 @@
39#include <asm/uaccess.h> 39#include <asm/uaccess.h>
40#include <asm/io.h> 40#include <asm/io.h>
41#include <asm/system.h> 41#include <asm/system.h>
42#include <asm/uaccess.h>
43 42
44/* Include-File for the Meilhaus ME-4000 I/O board */ 43/* Include-File for the Meilhaus ME-4000 I/O board */
45#include "me4000.h" 44#include "me4000.h"
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 0f13448c6f79..3f3ce13fef43 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -2083,6 +2083,38 @@ config FB_METRONOME
2083 controller. The pre-release name for this device was 8track 2083 controller. The pre-release name for this device was 8track
2084 and could also have been called by some vendors as PVI-nnnn. 2084 and could also have been called by some vendors as PVI-nnnn.
2085 2085
2086config FB_MB862XX
2087 tristate "Fujitsu MB862xx GDC support"
2088 depends on FB
2089 select FB_CFB_FILLRECT
2090 select FB_CFB_COPYAREA
2091 select FB_CFB_IMAGEBLIT
2092 ---help---
2093 Frame buffer driver for Fujitsu Carmine/Coral-P(A)/Lime controllers.
2094
2095config FB_MB862XX_PCI_GDC
2096 bool "Carmine/Coral-P(A) GDC"
2097 depends on PCI && FB_MB862XX
2098 ---help---
2099 This enables framebuffer support for Fujitsu Carmine/Coral-P(A)
2100 PCI graphics controller devices.
2101
2102config FB_MB862XX_LIME
2103 bool "Lime GDC"
2104 depends on FB_MB862XX
2105 depends on OF && !FB_MB862XX_PCI_GDC
2106 select FB_FOREIGN_ENDIAN
2107 select FB_LITTLE_ENDIAN
2108 ---help---
2109 Framebuffer support for Fujitsu Lime GDC on host CPU bus.
2110
2111config FB_PRE_INIT_FB
2112 bool "Don't reinitialize, use bootloader's GDC/Display configuration"
2113 depends on FB_MB862XX_LIME
2114 ---help---
2115 Select this option if display contents should be inherited as set by
2116 the bootloader.
2117
2086source "drivers/video/omap/Kconfig" 2118source "drivers/video/omap/Kconfig"
2087 2119
2088source "drivers/video/backlight/Kconfig" 2120source "drivers/video/backlight/Kconfig"
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 248bddc8d0b0..e39e33e797da 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -122,6 +122,7 @@ obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o
122obj-$(CONFIG_FB_OMAP) += omap/ 122obj-$(CONFIG_FB_OMAP) += omap/
123obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o 123obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o
124obj-$(CONFIG_FB_CARMINE) += carminefb.o 124obj-$(CONFIG_FB_CARMINE) += carminefb.o
125obj-$(CONFIG_FB_MB862XX) += mb862xx/
125 126
126# Platform or fallback drivers go here 127# Platform or fallback drivers go here
127obj-$(CONFIG_FB_UVESA) += uvesafb.o 128obj-$(CONFIG_FB_UVESA) += uvesafb.o
diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c
index 6048b55f2878..1d5ae39cb271 100644
--- a/drivers/video/fbmem.c
+++ b/drivers/video/fbmem.c
@@ -1002,13 +1002,9 @@ fb_blank(struct fb_info *info, int blank)
1002 return ret; 1002 return ret;
1003} 1003}
1004 1004
1005static long 1005static long do_fb_ioctl(struct fb_info *info, unsigned int cmd,
1006fb_ioctl(struct file *file, unsigned int cmd, 1006 unsigned long arg)
1007 unsigned long arg)
1008{ 1007{
1009 struct inode *inode = file->f_path.dentry->d_inode;
1010 int fbidx = iminor(inode);
1011 struct fb_info *info;
1012 struct fb_ops *fb; 1008 struct fb_ops *fb;
1013 struct fb_var_screeninfo var; 1009 struct fb_var_screeninfo var;
1014 struct fb_fix_screeninfo fix; 1010 struct fb_fix_screeninfo fix;
@@ -1018,14 +1014,10 @@ fb_ioctl(struct file *file, unsigned int cmd,
1018 void __user *argp = (void __user *)arg; 1014 void __user *argp = (void __user *)arg;
1019 long ret = 0; 1015 long ret = 0;
1020 1016
1021 info = registered_fb[fbidx];
1022 mutex_lock(&info->lock);
1023 fb = info->fbops; 1017 fb = info->fbops;
1024 1018 if (!fb)
1025 if (!fb) {
1026 mutex_unlock(&info->lock);
1027 return -ENODEV; 1019 return -ENODEV;
1028 } 1020
1029 switch (cmd) { 1021 switch (cmd) {
1030 case FBIOGET_VSCREENINFO: 1022 case FBIOGET_VSCREENINFO:
1031 ret = copy_to_user(argp, &info->var, 1023 ret = copy_to_user(argp, &info->var,
@@ -1126,6 +1118,21 @@ fb_ioctl(struct file *file, unsigned int cmd,
1126 else 1118 else
1127 ret = fb->fb_ioctl(info, cmd, arg); 1119 ret = fb->fb_ioctl(info, cmd, arg);
1128 } 1120 }
1121 return ret;
1122}
1123
1124static long fb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1125__acquires(&info->lock)
1126__releases(&info->lock)
1127{
1128 struct inode *inode = file->f_path.dentry->d_inode;
1129 int fbidx = iminor(inode);
1130 struct fb_info *info;
1131 long ret;
1132
1133 info = registered_fb[fbidx];
1134 mutex_lock(&info->lock);
1135 ret = do_fb_ioctl(info, cmd, arg);
1129 mutex_unlock(&info->lock); 1136 mutex_unlock(&info->lock);
1130 return ret; 1137 return ret;
1131} 1138}
@@ -1157,8 +1164,8 @@ struct fb_cmap32 {
1157 compat_caddr_t transp; 1164 compat_caddr_t transp;
1158}; 1165};
1159 1166
1160static int fb_getput_cmap(struct inode *inode, struct file *file, 1167static int fb_getput_cmap(struct fb_info *info, unsigned int cmd,
1161 unsigned int cmd, unsigned long arg) 1168 unsigned long arg)
1162{ 1169{
1163 struct fb_cmap_user __user *cmap; 1170 struct fb_cmap_user __user *cmap;
1164 struct fb_cmap32 __user *cmap32; 1171 struct fb_cmap32 __user *cmap32;
@@ -1181,7 +1188,7 @@ static int fb_getput_cmap(struct inode *inode, struct file *file,
1181 put_user(compat_ptr(data), &cmap->transp)) 1188 put_user(compat_ptr(data), &cmap->transp))
1182 return -EFAULT; 1189 return -EFAULT;
1183 1190
1184 err = fb_ioctl(file, cmd, (unsigned long) cmap); 1191 err = do_fb_ioctl(info, cmd, (unsigned long) cmap);
1185 1192
1186 if (!err) { 1193 if (!err) {
1187 if (copy_in_user(&cmap32->start, 1194 if (copy_in_user(&cmap32->start,
@@ -1223,8 +1230,8 @@ static int do_fscreeninfo_to_user(struct fb_fix_screeninfo *fix,
1223 return err; 1230 return err;
1224} 1231}
1225 1232
1226static int fb_get_fscreeninfo(struct inode *inode, struct file *file, 1233static int fb_get_fscreeninfo(struct fb_info *info, unsigned int cmd,
1227 unsigned int cmd, unsigned long arg) 1234 unsigned long arg)
1228{ 1235{
1229 mm_segment_t old_fs; 1236 mm_segment_t old_fs;
1230 struct fb_fix_screeninfo fix; 1237 struct fb_fix_screeninfo fix;
@@ -1235,7 +1242,7 @@ static int fb_get_fscreeninfo(struct inode *inode, struct file *file,
1235 1242
1236 old_fs = get_fs(); 1243 old_fs = get_fs();
1237 set_fs(KERNEL_DS); 1244 set_fs(KERNEL_DS);
1238 err = fb_ioctl(file, cmd, (unsigned long) &fix); 1245 err = do_fb_ioctl(info, cmd, (unsigned long) &fix);
1239 set_fs(old_fs); 1246 set_fs(old_fs);
1240 1247
1241 if (!err) 1248 if (!err)
@@ -1244,8 +1251,10 @@ static int fb_get_fscreeninfo(struct inode *inode, struct file *file,
1244 return err; 1251 return err;
1245} 1252}
1246 1253
1247static long 1254static long fb_compat_ioctl(struct file *file, unsigned int cmd,
1248fb_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 1255 unsigned long arg)
1256__acquires(&info->lock)
1257__releases(&info->lock)
1249{ 1258{
1250 struct inode *inode = file->f_path.dentry->d_inode; 1259 struct inode *inode = file->f_path.dentry->d_inode;
1251 int fbidx = iminor(inode); 1260 int fbidx = iminor(inode);
@@ -1262,16 +1271,16 @@ fb_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1262 case FBIOPUT_CON2FBMAP: 1271 case FBIOPUT_CON2FBMAP:
1263 arg = (unsigned long) compat_ptr(arg); 1272 arg = (unsigned long) compat_ptr(arg);
1264 case FBIOBLANK: 1273 case FBIOBLANK:
1265 mutex_unlock(&info->lock); 1274 ret = do_fb_ioctl(info, cmd, arg);
1266 return fb_ioctl(file, cmd, arg); 1275 break;
1267 1276
1268 case FBIOGET_FSCREENINFO: 1277 case FBIOGET_FSCREENINFO:
1269 ret = fb_get_fscreeninfo(inode, file, cmd, arg); 1278 ret = fb_get_fscreeninfo(info, cmd, arg);
1270 break; 1279 break;
1271 1280
1272 case FBIOGETCMAP: 1281 case FBIOGETCMAP:
1273 case FBIOPUTCMAP: 1282 case FBIOPUTCMAP:
1274 ret = fb_getput_cmap(inode, file, cmd, arg); 1283 ret = fb_getput_cmap(info, cmd, arg);
1275 break; 1284 break;
1276 1285
1277 default: 1286 default:
@@ -1286,6 +1295,8 @@ fb_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
1286 1295
1287static int 1296static int
1288fb_mmap(struct file *file, struct vm_area_struct * vma) 1297fb_mmap(struct file *file, struct vm_area_struct * vma)
1298__acquires(&info->lock)
1299__releases(&info->lock)
1289{ 1300{
1290 int fbidx = iminor(file->f_path.dentry->d_inode); 1301 int fbidx = iminor(file->f_path.dentry->d_inode);
1291 struct fb_info *info = registered_fb[fbidx]; 1302 struct fb_info *info = registered_fb[fbidx];
@@ -1339,6 +1350,8 @@ fb_mmap(struct file *file, struct vm_area_struct * vma)
1339 1350
1340static int 1351static int
1341fb_open(struct inode *inode, struct file *file) 1352fb_open(struct inode *inode, struct file *file)
1353__acquires(&info->lock)
1354__releases(&info->lock)
1342{ 1355{
1343 int fbidx = iminor(inode); 1356 int fbidx = iminor(inode);
1344 struct fb_info *info; 1357 struct fb_info *info;
@@ -1374,6 +1387,8 @@ out:
1374 1387
1375static int 1388static int
1376fb_release(struct inode *inode, struct file *file) 1389fb_release(struct inode *inode, struct file *file)
1390__acquires(&info->lock)
1391__releases(&info->lock)
1377{ 1392{
1378 struct fb_info * const info = file->private_data; 1393 struct fb_info * const info = file->private_data;
1379 1394
diff --git a/drivers/video/mb862xx/Makefile b/drivers/video/mb862xx/Makefile
new file mode 100644
index 000000000000..07664814bb1d
--- /dev/null
+++ b/drivers/video/mb862xx/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the MB862xx framebuffer driver
3#
4
5obj-$(CONFIG_FB_MB862XX) := mb862xxfb.o
diff --git a/drivers/video/mb862xx/mb862xx_reg.h b/drivers/video/mb862xx/mb862xx_reg.h
new file mode 100644
index 000000000000..2ba65e118500
--- /dev/null
+++ b/drivers/video/mb862xx/mb862xx_reg.h
@@ -0,0 +1,138 @@
1/*
2 * Fujitsu MB862xx Graphics Controller Registers/Bits
3 */
4
5#ifndef _MB862XX_REG_H
6#define _MB862XX_REG_H
7
8#ifdef MB862XX_MMIO_BOTTOM
9#define MB862XX_MMIO_BASE 0x03fc0000
10#else
11#define MB862XX_MMIO_BASE 0x01fc0000
12#endif
13#define MB862XX_I2C_BASE 0x0000c000
14#define MB862XX_DISP_BASE 0x00010000
15#define MB862XX_CAP_BASE 0x00018000
16#define MB862XX_DRAW_BASE 0x00030000
17#define MB862XX_GEO_BASE 0x00038000
18#define MB862XX_PIO_BASE 0x00038000
19#define MB862XX_MMIO_SIZE 0x40000
20
21/* Host interface/pio registers */
22#define GC_IST 0x00000020
23#define GC_IMASK 0x00000024
24#define GC_SRST 0x0000002c
25#define GC_CCF 0x00000038
26#define GC_CID 0x000000f0
27#define GC_REVISION 0x00000084
28
29#define GC_CCF_CGE_100 0x00000000
30#define GC_CCF_CGE_133 0x00040000
31#define GC_CCF_CGE_166 0x00080000
32#define GC_CCF_COT_100 0x00000000
33#define GC_CCF_COT_133 0x00010000
34#define GC_CID_CNAME_MSK 0x0000ff00
35#define GC_CID_VERSION_MSK 0x000000ff
36
37/* define enabled interrupts hereby */
38#define GC_INT_EN 0x00000000
39
40/* Memory interface mode register */
41#define GC_MMR 0x0000fffc
42
43/* Display Controller registers */
44#define GC_DCM0 0x00000000
45#define GC_HTP 0x00000004
46#define GC_HDB_HDP 0x00000008
47#define GC_VSW_HSW_HSP 0x0000000c
48#define GC_VTR 0x00000010
49#define GC_VDP_VSP 0x00000014
50#define GC_WY_WX 0x00000018
51#define GC_WH_WW 0x0000001c
52#define GC_L0M 0x00000020
53#define GC_L0OA0 0x00000024
54#define GC_L0DA0 0x00000028
55#define GC_L0DY_L0DX 0x0000002c
56#define GC_DCM1 0x00000100
57#define GC_L0EM 0x00000110
58#define GC_L0WY_L0WX 0x00000114
59#define GC_L0WH_L0WW 0x00000118
60#define GC_DCM2 0x00000104
61#define GC_DCM3 0x00000108
62#define GC_CPM_CUTC 0x000000a0
63#define GC_CUOA0 0x000000a4
64#define GC_CUY0_CUX0 0x000000a8
65#define GC_CUOA1 0x000000ac
66#define GC_CUY1_CUX1 0x000000b0
67#define GC_L0PAL0 0x00000400
68
69#define GC_CPM_CEN0 0x00100000
70#define GC_CPM_CEN1 0x00200000
71
72#define GC_DCM01_ESY 0x00000004
73#define GC_DCM01_SC 0x00003f00
74#define GC_DCM01_RESV 0x00004000
75#define GC_DCM01_CKS 0x00008000
76#define GC_DCM01_L0E 0x00010000
77#define GC_DCM01_DEN 0x80000000
78#define GC_L0M_L0C_8 0x00000000
79#define GC_L0M_L0C_16 0x80000000
80#define GC_L0EM_L0EC_24 0x40000000
81#define GC_L0M_L0W_UNIT 64
82
83#define GC_DISP_REFCLK_400 400
84
85/* Carmine specific */
86#define MB86297_DRAW_BASE 0x00020000
87#define MB86297_DISP0_BASE 0x00100000
88#define MB86297_DISP1_BASE 0x00140000
89#define MB86297_WRBACK_BASE 0x00180000
90#define MB86297_CAP0_BASE 0x00200000
91#define MB86297_CAP1_BASE 0x00280000
92#define MB86297_DRAMCTRL_BASE 0x00300000
93#define MB86297_CTRL_BASE 0x00400000
94#define MB86297_I2C_BASE 0x00500000
95
96#define GC_CTRL_STATUS 0x00000000
97#define GC_CTRL_INT_MASK 0x00000004
98#define GC_CTRL_CLK_ENABLE 0x0000000c
99#define GC_CTRL_SOFT_RST 0x00000010
100
101#define GC_CTRL_CLK_EN_DRAM 0x00000001
102#define GC_CTRL_CLK_EN_2D3D 0x00000002
103#define GC_CTRL_CLK_EN_DISP0 0x00000020
104#define GC_CTRL_CLK_EN_DISP1 0x00000040
105
106#define GC_2D3D_REV 0x000004b4
107#define GC_RE_REVISION 0x24240200
108
109/* define enabled interrupts hereby */
110#define GC_CARMINE_INT_EN 0x00000004
111
112/* DRAM controller */
113#define GC_DCTL_MODE_ADD 0x00000000
114#define GC_DCTL_SETTIME1_EMODE 0x00000004
115#define GC_DCTL_REFRESH_SETTIME2 0x00000008
116#define GC_DCTL_RSV0_STATES 0x0000000C
117#define GC_DCTL_RSV2_RSV1 0x00000010
118#define GC_DCTL_DDRIF2_DDRIF1 0x00000014
119#define GC_DCTL_IOCONT1_IOCONT0 0x00000024
120
121#define GC_DCTL_STATES_MSK 0x0000000f
122#define GC_DCTL_INIT_WAIT_CNT 3000
123#define GC_DCTL_INIT_WAIT_INTERVAL 1
124
125/* DRAM ctrl values for Carmine PCI Eval. board */
126#define GC_EVB_DCTL_MODE_ADD 0x012105c3
127#define GC_EVB_DCTL_MODE_ADD_AFT_RST 0x002105c3
128#define GC_EVB_DCTL_SETTIME1_EMODE 0x47498000
129#define GC_EVB_DCTL_REFRESH_SETTIME2 0x00422a22
130#define GC_EVB_DCTL_RSV0_STATES 0x00200003
131#define GC_EVB_DCTL_RSV0_STATES_AFT_RST 0x00200002
132#define GC_EVB_DCTL_RSV2_RSV1 0x0000000f
133#define GC_EVB_DCTL_DDRIF2_DDRIF1 0x00556646
134#define GC_EVB_DCTL_IOCONT1_IOCONT0 0x05550555
135
136#define GC_DISP_REFCLK_533 533
137
138#endif
diff --git a/drivers/video/mb862xx/mb862xxfb.c b/drivers/video/mb862xx/mb862xxfb.c
new file mode 100644
index 000000000000..38718d95fbb9
--- /dev/null
+++ b/drivers/video/mb862xx/mb862xxfb.c
@@ -0,0 +1,1061 @@
1/*
2 * drivers/mb862xx/mb862xxfb.c
3 *
4 * Fujitsu Carmine/Coral-P(A)/Lime framebuffer driver
5 *
6 * (C) 2008 Anatolij Gustschin <agust@denx.de>
7 * DENX Software Engineering
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#undef DEBUG
16
17#include <linux/fb.h>
18#include <linux/delay.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/pci.h>
22#if defined(CONFIG_PPC_OF)
23#include <linux/of_platform.h>
24#endif
25#include "mb862xxfb.h"
26#include "mb862xx_reg.h"
27
28#define NR_PALETTE 256
29#define MB862XX_MEM_SIZE 0x1000000
30#define CORALP_MEM_SIZE 0x4000000
31#define CARMINE_MEM_SIZE 0x8000000
32#define DRV_NAME "mb862xxfb"
33
34#if defined(CONFIG_LWMON5)
35static struct mb862xx_gc_mode lwmon5_gc_mode = {
36 /* Mode for Sharp LQ104V1DG61 TFT LCD Panel */
37 { "640x480", 60, 640, 480, 40000, 48, 16, 32, 11, 96, 2, 0, 0, 0 },
38 /* 16 bits/pixel, 32MB, 100MHz, SDRAM memory mode value */
39 16, 0x2000000, GC_CCF_COT_100, 0x414fb7f2
40};
41#endif
42
43#if defined(CONFIG_SOCRATES)
44static struct mb862xx_gc_mode socrates_gc_mode = {
45 /* Mode for Prime View PM070WL4 TFT LCD Panel */
46 { "800x480", 45, 800, 480, 40000, 86, 42, 33, 10, 128, 2, 0, 0, 0 },
47 /* 16 bits/pixel, 16MB, 133MHz, SDRAM memory mode value */
48 16, 0x1000000, GC_CCF_COT_133, 0x4157ba63
49};
50#endif
51
52/* Helpers */
53static inline int h_total(struct fb_var_screeninfo *var)
54{
55 return var->xres + var->left_margin +
56 var->right_margin + var->hsync_len;
57}
58
59static inline int v_total(struct fb_var_screeninfo *var)
60{
61 return var->yres + var->upper_margin +
62 var->lower_margin + var->vsync_len;
63}
64
65static inline int hsp(struct fb_var_screeninfo *var)
66{
67 return var->xres + var->right_margin - 1;
68}
69
70static inline int vsp(struct fb_var_screeninfo *var)
71{
72 return var->yres + var->lower_margin - 1;
73}
74
75static inline int d_pitch(struct fb_var_screeninfo *var)
76{
77 return var->xres * var->bits_per_pixel / 8;
78}
79
80static inline unsigned int chan_to_field(unsigned int chan,
81 struct fb_bitfield *bf)
82{
83 chan &= 0xffff;
84 chan >>= 16 - bf->length;
85 return chan << bf->offset;
86}
87
88static int mb862xxfb_setcolreg(unsigned regno,
89 unsigned red, unsigned green, unsigned blue,
90 unsigned transp, struct fb_info *info)
91{
92 struct mb862xxfb_par *par = info->par;
93 unsigned int val;
94
95 switch (info->fix.visual) {
96 case FB_VISUAL_TRUECOLOR:
97 if (regno < 16) {
98 val = chan_to_field(red, &info->var.red);
99 val |= chan_to_field(green, &info->var.green);
100 val |= chan_to_field(blue, &info->var.blue);
101 par->pseudo_palette[regno] = val;
102 }
103 break;
104 case FB_VISUAL_PSEUDOCOLOR:
105 if (regno < 256) {
106 val = (red >> 8) << 16;
107 val |= (green >> 8) << 8;
108 val |= blue >> 8;
109 outreg(disp, GC_L0PAL0 + (regno * 4), val);
110 }
111 break;
112 default:
113 return 1; /* unsupported type */
114 }
115 return 0;
116}
117
118static int mb862xxfb_check_var(struct fb_var_screeninfo *var,
119 struct fb_info *fbi)
120{
121 unsigned long tmp;
122
123 if (fbi->dev)
124 dev_dbg(fbi->dev, "%s\n", __func__);
125
126 /* check if these values fit into the registers */
127 if (var->hsync_len > 255 || var->vsync_len > 255)
128 return -EINVAL;
129
130 if ((var->xres + var->right_margin) >= 4096)
131 return -EINVAL;
132
133 if ((var->yres + var->lower_margin) > 4096)
134 return -EINVAL;
135
136 if (h_total(var) > 4096 || v_total(var) > 4096)
137 return -EINVAL;
138
139 if (var->xres_virtual > 4096 || var->yres_virtual > 4096)
140 return -EINVAL;
141
142 if (var->bits_per_pixel <= 8)
143 var->bits_per_pixel = 8;
144 else if (var->bits_per_pixel <= 16)
145 var->bits_per_pixel = 16;
146 else if (var->bits_per_pixel <= 32)
147 var->bits_per_pixel = 32;
148
149 /*
150 * can cope with 8,16 or 24/32bpp if resulting
151 * pitch is divisible by 64 without remainder
152 */
153 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT) {
154 int r;
155
156 var->bits_per_pixel = 0;
157 do {
158 var->bits_per_pixel += 8;
159 r = d_pitch(&fbi->var) % GC_L0M_L0W_UNIT;
160 } while (r && var->bits_per_pixel <= 32);
161
162 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT)
163 return -EINVAL;
164 }
165
166 /* line length is going to be 128 bit aligned */
167 tmp = (var->xres * var->bits_per_pixel) / 8;
168 if ((tmp & 15) != 0)
169 return -EINVAL;
170
171 /* set r/g/b positions and validate bpp */
172 switch (var->bits_per_pixel) {
173 case 8:
174 var->red.length = var->bits_per_pixel;
175 var->green.length = var->bits_per_pixel;
176 var->blue.length = var->bits_per_pixel;
177 var->red.offset = 0;
178 var->green.offset = 0;
179 var->blue.offset = 0;
180 var->transp.length = 0;
181 break;
182 case 16:
183 var->red.length = 5;
184 var->green.length = 5;
185 var->blue.length = 5;
186 var->red.offset = 10;
187 var->green.offset = 5;
188 var->blue.offset = 0;
189 var->transp.length = 0;
190 break;
191 case 24:
192 case 32:
193 var->transp.length = 8;
194 var->red.length = 8;
195 var->green.length = 8;
196 var->blue.length = 8;
197 var->transp.offset = 24;
198 var->red.offset = 16;
199 var->green.offset = 8;
200 var->blue.offset = 0;
201 break;
202 default:
203 return -EINVAL;
204 }
205 return 0;
206}
207
208/*
209 * set display parameters
210 */
211static int mb862xxfb_set_par(struct fb_info *fbi)
212{
213 struct mb862xxfb_par *par = fbi->par;
214 unsigned long reg, sc;
215
216 dev_dbg(par->dev, "%s\n", __func__);
217
218 if (par->pre_init)
219 return 0;
220
221 /* disp off */
222 reg = inreg(disp, GC_DCM1);
223 reg &= ~GC_DCM01_DEN;
224 outreg(disp, GC_DCM1, reg);
225
226 /* set display reference clock div. */
227 sc = par->refclk / (1000000 / fbi->var.pixclock) - 1;
228 reg = inreg(disp, GC_DCM1);
229 reg &= ~(GC_DCM01_CKS | GC_DCM01_RESV | GC_DCM01_SC);
230 reg |= sc << 8;
231 outreg(disp, GC_DCM1, reg);
232 dev_dbg(par->dev, "SC 0x%lx\n", sc);
233
234 /* disp dimension, format */
235 reg = pack(d_pitch(&fbi->var) / GC_L0M_L0W_UNIT,
236 (fbi->var.yres - 1));
237 if (fbi->var.bits_per_pixel == 16)
238 reg |= GC_L0M_L0C_16;
239 outreg(disp, GC_L0M, reg);
240
241 if (fbi->var.bits_per_pixel == 32) {
242 reg = inreg(disp, GC_L0EM);
243 outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24);
244 }
245 outreg(disp, GC_WY_WX, 0);
246 reg = pack(fbi->var.yres - 1, fbi->var.xres);
247 outreg(disp, GC_WH_WW, reg);
248 outreg(disp, GC_L0OA0, 0);
249 outreg(disp, GC_L0DA0, 0);
250 outreg(disp, GC_L0DY_L0DX, 0);
251 outreg(disp, GC_L0WY_L0WX, 0);
252 outreg(disp, GC_L0WH_L0WW, reg);
253
254 /* both HW-cursors off */
255 reg = inreg(disp, GC_CPM_CUTC);
256 reg &= ~(GC_CPM_CEN0 | GC_CPM_CEN1);
257 outreg(disp, GC_CPM_CUTC, reg);
258
259 /* timings */
260 reg = pack(fbi->var.xres - 1, fbi->var.xres - 1);
261 outreg(disp, GC_HDB_HDP, reg);
262 reg = pack((fbi->var.yres - 1), vsp(&fbi->var));
263 outreg(disp, GC_VDP_VSP, reg);
264 reg = ((fbi->var.vsync_len - 1) << 24) |
265 pack((fbi->var.hsync_len - 1), hsp(&fbi->var));
266 outreg(disp, GC_VSW_HSW_HSP, reg);
267 outreg(disp, GC_HTP, pack(h_total(&fbi->var) - 1, 0));
268 outreg(disp, GC_VTR, pack(v_total(&fbi->var) - 1, 0));
269
270 /* display on */
271 reg = inreg(disp, GC_DCM1);
272 reg |= GC_DCM01_DEN | GC_DCM01_L0E;
273 reg &= ~GC_DCM01_ESY;
274 outreg(disp, GC_DCM1, reg);
275 return 0;
276}
277
278static int mb862xxfb_pan(struct fb_var_screeninfo *var,
279 struct fb_info *info)
280{
281 struct mb862xxfb_par *par = info->par;
282 unsigned long reg;
283
284 reg = pack(var->yoffset, var->xoffset);
285 outreg(disp, GC_L0WY_L0WX, reg);
286
287 reg = pack(var->yres_virtual, var->xres_virtual);
288 outreg(disp, GC_L0WH_L0WW, reg);
289 return 0;
290}
291
292static int mb862xxfb_blank(int mode, struct fb_info *fbi)
293{
294 struct mb862xxfb_par *par = fbi->par;
295 unsigned long reg;
296
297 dev_dbg(fbi->dev, "blank mode=%d\n", mode);
298
299 switch (mode) {
300 case FB_BLANK_POWERDOWN:
301 reg = inreg(disp, GC_DCM1);
302 reg &= ~GC_DCM01_DEN;
303 outreg(disp, GC_DCM1, reg);
304 break;
305 case FB_BLANK_UNBLANK:
306 reg = inreg(disp, GC_DCM1);
307 reg |= GC_DCM01_DEN;
308 outreg(disp, GC_DCM1, reg);
309 break;
310 case FB_BLANK_NORMAL:
311 case FB_BLANK_VSYNC_SUSPEND:
312 case FB_BLANK_HSYNC_SUSPEND:
313 default:
314 return 1;
315 }
316 return 0;
317}
318
319/* framebuffer ops */
320static struct fb_ops mb862xxfb_ops = {
321 .owner = THIS_MODULE,
322 .fb_check_var = mb862xxfb_check_var,
323 .fb_set_par = mb862xxfb_set_par,
324 .fb_setcolreg = mb862xxfb_setcolreg,
325 .fb_blank = mb862xxfb_blank,
326 .fb_pan_display = mb862xxfb_pan,
327 .fb_fillrect = cfb_fillrect,
328 .fb_copyarea = cfb_copyarea,
329 .fb_imageblit = cfb_imageblit,
330};
331
332/* initialize fb_info data */
333static int mb862xxfb_init_fbinfo(struct fb_info *fbi)
334{
335 struct mb862xxfb_par *par = fbi->par;
336 struct mb862xx_gc_mode *mode = par->gc_mode;
337 unsigned long reg;
338
339 fbi->fbops = &mb862xxfb_ops;
340 fbi->pseudo_palette = par->pseudo_palette;
341 fbi->screen_base = par->fb_base;
342 fbi->screen_size = par->mapped_vram;
343
344 strcpy(fbi->fix.id, DRV_NAME);
345 fbi->fix.smem_start = (unsigned long)par->fb_base_phys;
346 fbi->fix.smem_len = par->mapped_vram;
347 fbi->fix.mmio_start = (unsigned long)par->mmio_base_phys;
348 fbi->fix.mmio_len = par->mmio_len;
349 fbi->fix.accel = FB_ACCEL_NONE;
350 fbi->fix.type = FB_TYPE_PACKED_PIXELS;
351 fbi->fix.type_aux = 0;
352 fbi->fix.xpanstep = 1;
353 fbi->fix.ypanstep = 1;
354 fbi->fix.ywrapstep = 0;
355
356 reg = inreg(disp, GC_DCM1);
357 if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E) {
358 /* get the disp mode from active display cfg */
359 unsigned long sc = ((reg & GC_DCM01_SC) >> 8) + 1;
360 unsigned long hsp, vsp, ht, vt;
361
362 dev_dbg(par->dev, "using bootloader's disp. mode\n");
363 fbi->var.pixclock = (sc * 1000000) / par->refclk;
364 fbi->var.xres = (inreg(disp, GC_HDB_HDP) & 0x0fff) + 1;
365 reg = inreg(disp, GC_VDP_VSP);
366 fbi->var.yres = ((reg >> 16) & 0x0fff) + 1;
367 vsp = (reg & 0x0fff) + 1;
368 fbi->var.xres_virtual = fbi->var.xres;
369 fbi->var.yres_virtual = fbi->var.yres;
370 reg = inreg(disp, GC_L0EM);
371 if (reg & GC_L0EM_L0EC_24) {
372 fbi->var.bits_per_pixel = 32;
373 } else {
374 reg = inreg(disp, GC_L0M);
375 if (reg & GC_L0M_L0C_16)
376 fbi->var.bits_per_pixel = 16;
377 else
378 fbi->var.bits_per_pixel = 8;
379 }
380 reg = inreg(disp, GC_VSW_HSW_HSP);
381 fbi->var.hsync_len = ((reg & 0xff0000) >> 16) + 1;
382 fbi->var.vsync_len = ((reg & 0x3f000000) >> 24) + 1;
383 hsp = (reg & 0xffff) + 1;
384 ht = ((inreg(disp, GC_HTP) & 0xfff0000) >> 16) + 1;
385 fbi->var.right_margin = hsp - fbi->var.xres;
386 fbi->var.left_margin = ht - hsp - fbi->var.hsync_len;
387 vt = ((inreg(disp, GC_VTR) & 0xfff0000) >> 16) + 1;
388 fbi->var.lower_margin = vsp - fbi->var.yres;
389 fbi->var.upper_margin = vt - vsp - fbi->var.vsync_len;
390 } else if (mode) {
391 dev_dbg(par->dev, "using supplied mode\n");
392 fb_videomode_to_var(&fbi->var, (struct fb_videomode *)mode);
393 fbi->var.bits_per_pixel = mode->def_bpp ? mode->def_bpp : 8;
394 } else {
395 int ret;
396
397 ret = fb_find_mode(&fbi->var, fbi, "640x480-16@60",
398 NULL, 0, NULL, 16);
399 if (ret == 0 || ret == 4) {
400 dev_err(par->dev,
401 "failed to get initial mode\n");
402 return -EINVAL;
403 }
404 }
405
406 fbi->var.xoffset = 0;
407 fbi->var.yoffset = 0;
408 fbi->var.grayscale = 0;
409 fbi->var.nonstd = 0;
410 fbi->var.height = -1;
411 fbi->var.width = -1;
412 fbi->var.accel_flags = 0;
413 fbi->var.vmode = FB_VMODE_NONINTERLACED;
414 fbi->var.activate = FB_ACTIVATE_NOW;
415 fbi->flags = FBINFO_DEFAULT |
416#ifdef __BIG_ENDIAN
417 FBINFO_FOREIGN_ENDIAN |
418#endif
419 FBINFO_HWACCEL_XPAN |
420 FBINFO_HWACCEL_YPAN;
421
422 /* check and possibly fix bpp */
423 if ((fbi->fbops->fb_check_var)(&fbi->var, fbi))
424 dev_err(par->dev, "check_var() failed on initial setup?\n");
425
426 fbi->fix.visual = fbi->var.bits_per_pixel == 8 ?
427 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
428 fbi->fix.line_length = (fbi->var.xres_virtual *
429 fbi->var.bits_per_pixel) / 8;
430 return 0;
431}
432
433/*
434 * show some display controller and cursor registers
435 */
436static ssize_t mb862xxfb_show_dispregs(struct device *dev,
437 struct device_attribute *attr, char *buf)
438{
439 struct fb_info *fbi = dev_get_drvdata(dev);
440 struct mb862xxfb_par *par = fbi->par;
441 char *ptr = buf;
442 unsigned int reg;
443
444 for (reg = GC_DCM0; reg <= GC_L0DY_L0DX; reg += 4)
445 ptr += sprintf(ptr, "%08x = %08x\n",
446 reg, inreg(disp, reg));
447
448 for (reg = GC_CPM_CUTC; reg <= GC_CUY1_CUX1; reg += 4)
449 ptr += sprintf(ptr, "%08x = %08x\n",
450 reg, inreg(disp, reg));
451
452 for (reg = GC_DCM1; reg <= GC_L0WH_L0WW; reg += 4)
453 ptr += sprintf(ptr, "%08x = %08x\n",
454 reg, inreg(disp, reg));
455
456 return ptr - buf;
457}
458
459static DEVICE_ATTR(dispregs, 0444, mb862xxfb_show_dispregs, NULL);
460
461irqreturn_t mb862xx_intr(int irq, void *dev_id)
462{
463 struct mb862xxfb_par *par = (struct mb862xxfb_par *) dev_id;
464 unsigned long reg_ist, mask;
465
466 if (!par)
467 return IRQ_NONE;
468
469 if (par->type == BT_CARMINE) {
470 /* Get Interrupt Status */
471 reg_ist = inreg(ctrl, GC_CTRL_STATUS);
472 mask = inreg(ctrl, GC_CTRL_INT_MASK);
473 if (reg_ist == 0)
474 return IRQ_HANDLED;
475
476 reg_ist &= mask;
477 if (reg_ist == 0)
478 return IRQ_HANDLED;
479
480 /* Clear interrupt status */
481 outreg(ctrl, 0x0, reg_ist);
482 } else {
483 /* Get status */
484 reg_ist = inreg(host, GC_IST);
485 mask = inreg(host, GC_IMASK);
486
487 reg_ist &= mask;
488 if (reg_ist == 0)
489 return IRQ_HANDLED;
490
491 /* Clear status */
492 outreg(host, GC_IST, ~reg_ist);
493 }
494 return IRQ_HANDLED;
495}
496
497#if defined(CONFIG_FB_MB862XX_LIME)
498/*
499 * GDC (Lime, Coral(B/Q), Mint, ...) on host bus
500 */
501static int mb862xx_gdc_init(struct mb862xxfb_par *par)
502{
503 unsigned long ccf, mmr;
504 unsigned long ver, rev;
505
506 if (!par)
507 return -ENODEV;
508
509#if defined(CONFIG_FB_PRE_INIT_FB)
510 par->pre_init = 1;
511#endif
512 par->host = par->mmio_base;
513 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
514 par->disp = par->mmio_base + MB862XX_DISP_BASE;
515 par->cap = par->mmio_base + MB862XX_CAP_BASE;
516 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
517 par->geo = par->mmio_base + MB862XX_GEO_BASE;
518 par->pio = par->mmio_base + MB862XX_PIO_BASE;
519
520 par->refclk = GC_DISP_REFCLK_400;
521
522 ver = inreg(host, GC_CID);
523 rev = inreg(pio, GC_REVISION);
524 if ((ver == 0x303) && (rev & 0xffffff00) == 0x20050100) {
525 dev_info(par->dev, "Fujitsu Lime v1.%d found\n",
526 (int)rev & 0xff);
527 par->type = BT_LIME;
528 ccf = par->gc_mode ? par->gc_mode->ccf : GC_CCF_COT_100;
529 mmr = par->gc_mode ? par->gc_mode->mmr : 0x414fb7f2;
530 } else {
531 dev_info(par->dev, "? GDC, CID/Rev.: 0x%lx/0x%lx \n", ver, rev);
532 return -ENODEV;
533 }
534
535 if (!par->pre_init) {
536 outreg(host, GC_CCF, ccf);
537 udelay(200);
538 outreg(host, GC_MMR, mmr);
539 udelay(10);
540 }
541
542 /* interrupt status */
543 outreg(host, GC_IST, 0);
544 outreg(host, GC_IMASK, GC_INT_EN);
545 return 0;
546}
547
548static int __devinit of_platform_mb862xx_probe(struct of_device *ofdev,
549 const struct of_device_id *id)
550{
551 struct device_node *np = ofdev->node;
552 struct device *dev = &ofdev->dev;
553 struct mb862xxfb_par *par;
554 struct fb_info *info;
555 struct resource res;
556 resource_size_t res_size;
557 unsigned long ret = -ENODEV;
558
559 if (of_address_to_resource(np, 0, &res)) {
560 dev_err(dev, "Invalid address\n");
561 return -ENXIO;
562 }
563
564 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
565 if (info == NULL) {
566 dev_err(dev, "cannot allocate framebuffer\n");
567 return -ENOMEM;
568 }
569
570 par = info->par;
571 par->info = info;
572 par->dev = dev;
573
574 par->irq = irq_of_parse_and_map(np, 0);
575 if (par->irq == NO_IRQ) {
576 dev_err(dev, "failed to map irq\n");
577 ret = -ENODEV;
578 goto fbrel;
579 }
580
581 res_size = 1 + res.end - res.start;
582 par->res = request_mem_region(res.start, res_size, DRV_NAME);
583 if (par->res == NULL) {
584 dev_err(dev, "Cannot claim framebuffer/mmio\n");
585 ret = -ENXIO;
586 goto irqdisp;
587 }
588
589#if defined(CONFIG_LWMON5)
590 par->gc_mode = &lwmon5_gc_mode;
591#endif
592
593#if defined(CONFIG_SOCRATES)
594 par->gc_mode = &socrates_gc_mode;
595#endif
596
597 par->fb_base_phys = res.start;
598 par->mmio_base_phys = res.start + MB862XX_MMIO_BASE;
599 par->mmio_len = MB862XX_MMIO_SIZE;
600 if (par->gc_mode)
601 par->mapped_vram = par->gc_mode->max_vram;
602 else
603 par->mapped_vram = MB862XX_MEM_SIZE;
604
605 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
606 if (par->fb_base == NULL) {
607 dev_err(dev, "Cannot map framebuffer\n");
608 goto rel_reg;
609 }
610
611 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
612 if (par->mmio_base == NULL) {
613 dev_err(dev, "Cannot map registers\n");
614 goto fb_unmap;
615 }
616
617 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
618 (u64)par->fb_base_phys, (ulong)par->mapped_vram);
619 dev_dbg(dev, "mmio phys 0x%llx 0x%lx, (irq = %d)\n",
620 (u64)par->mmio_base_phys, (ulong)par->mmio_len, par->irq);
621
622 if (mb862xx_gdc_init(par))
623 goto io_unmap;
624
625 if (request_irq(par->irq, mb862xx_intr, IRQF_DISABLED,
626 DRV_NAME, (void *)par)) {
627 dev_err(dev, "Cannot request irq\n");
628 goto io_unmap;
629 }
630
631 mb862xxfb_init_fbinfo(info);
632
633 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
634 dev_err(dev, "Could not allocate cmap for fb_info.\n");
635 goto free_irq;
636 }
637
638 if ((info->fbops->fb_set_par)(info))
639 dev_err(dev, "set_var() failed on initial setup?\n");
640
641 if (register_framebuffer(info)) {
642 dev_err(dev, "failed to register framebuffer\n");
643 goto rel_cmap;
644 }
645
646 dev_set_drvdata(dev, info);
647
648 if (device_create_file(dev, &dev_attr_dispregs))
649 dev_err(dev, "Can't create sysfs regdump file\n");
650 return 0;
651
652rel_cmap:
653 fb_dealloc_cmap(&info->cmap);
654free_irq:
655 outreg(host, GC_IMASK, 0);
656 free_irq(par->irq, (void *)par);
657io_unmap:
658 iounmap(par->mmio_base);
659fb_unmap:
660 iounmap(par->fb_base);
661rel_reg:
662 release_mem_region(res.start, res_size);
663irqdisp:
664 irq_dispose_mapping(par->irq);
665fbrel:
666 dev_set_drvdata(dev, NULL);
667 framebuffer_release(info);
668 return ret;
669}
670
671static int __devexit of_platform_mb862xx_remove(struct of_device *ofdev)
672{
673 struct fb_info *fbi = dev_get_drvdata(&ofdev->dev);
674 struct mb862xxfb_par *par = fbi->par;
675 resource_size_t res_size = 1 + par->res->end - par->res->start;
676 unsigned long reg;
677
678 dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
679
680 /* display off */
681 reg = inreg(disp, GC_DCM1);
682 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
683 outreg(disp, GC_DCM1, reg);
684
685 /* disable interrupts */
686 outreg(host, GC_IMASK, 0);
687
688 free_irq(par->irq, (void *)par);
689 irq_dispose_mapping(par->irq);
690
691 device_remove_file(&ofdev->dev, &dev_attr_dispregs);
692
693 unregister_framebuffer(fbi);
694 fb_dealloc_cmap(&fbi->cmap);
695
696 iounmap(par->mmio_base);
697 iounmap(par->fb_base);
698
699 dev_set_drvdata(&ofdev->dev, NULL);
700 release_mem_region(par->res->start, res_size);
701 framebuffer_release(fbi);
702 return 0;
703}
704
705/*
706 * common types
707 */
708static struct of_device_id __devinitdata of_platform_mb862xx_tbl[] = {
709 { .compatible = "fujitsu,MB86276", },
710 { .compatible = "fujitsu,lime", },
711 { .compatible = "fujitsu,MB86277", },
712 { .compatible = "fujitsu,mint", },
713 { .compatible = "fujitsu,MB86293", },
714 { .compatible = "fujitsu,MB86294", },
715 { .compatible = "fujitsu,coral", },
716 { /* end */ }
717};
718
719static struct of_platform_driver of_platform_mb862xxfb_driver = {
720 .owner = THIS_MODULE,
721 .name = DRV_NAME,
722 .match_table = of_platform_mb862xx_tbl,
723 .probe = of_platform_mb862xx_probe,
724 .remove = __devexit_p(of_platform_mb862xx_remove),
725};
726#endif
727
728#if defined(CONFIG_FB_MB862XX_PCI_GDC)
729static int coralp_init(struct mb862xxfb_par *par)
730{
731 int cn, ver;
732
733 par->host = par->mmio_base;
734 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
735 par->disp = par->mmio_base + MB862XX_DISP_BASE;
736 par->cap = par->mmio_base + MB862XX_CAP_BASE;
737 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
738 par->geo = par->mmio_base + MB862XX_GEO_BASE;
739 par->pio = par->mmio_base + MB862XX_PIO_BASE;
740
741 par->refclk = GC_DISP_REFCLK_400;
742
743 ver = inreg(host, GC_CID);
744 cn = (ver & GC_CID_CNAME_MSK) >> 8;
745 ver = ver & GC_CID_VERSION_MSK;
746 if (cn == 3) {
747 dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\
748 (ver == 6) ? "P" : (ver == 8) ? "PA" : "?",
749 par->pdev->revision);
750 outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133);
751 udelay(200);
752 outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL);
753 udelay(10);
754 /* Clear interrupt status */
755 outreg(host, GC_IST, 0);
756 } else {
757 return -ENODEV;
758 }
759 return 0;
760}
761
762static int init_dram_ctrl(struct mb862xxfb_par *par)
763{
764 unsigned long i = 0;
765
766 /*
767 * Set io mode first! Spec. says IC may be destroyed
768 * if not set to SSTL2/LVCMOS before init.
769 */
770 outreg(dram_ctrl, GC_DCTL_IOCONT1_IOCONT0, GC_EVB_DCTL_IOCONT1_IOCONT0);
771
772 /* DRAM init */
773 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD);
774 outreg(dram_ctrl, GC_DCTL_SETTIME1_EMODE, GC_EVB_DCTL_SETTIME1_EMODE);
775 outreg(dram_ctrl, GC_DCTL_REFRESH_SETTIME2,
776 GC_EVB_DCTL_REFRESH_SETTIME2);
777 outreg(dram_ctrl, GC_DCTL_RSV2_RSV1, GC_EVB_DCTL_RSV2_RSV1);
778 outreg(dram_ctrl, GC_DCTL_DDRIF2_DDRIF1, GC_EVB_DCTL_DDRIF2_DDRIF1);
779 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES);
780
781 /* DLL reset done? */
782 while ((inreg(dram_ctrl, GC_DCTL_RSV0_STATES) & GC_DCTL_STATES_MSK)) {
783 udelay(GC_DCTL_INIT_WAIT_INTERVAL);
784 if (i++ > GC_DCTL_INIT_WAIT_CNT) {
785 dev_err(par->dev, "VRAM init failed.\n");
786 return -EINVAL;
787 }
788 }
789 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD_AFT_RST);
790 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES_AFT_RST);
791 return 0;
792}
793
794static int carmine_init(struct mb862xxfb_par *par)
795{
796 unsigned long reg;
797
798 par->ctrl = par->mmio_base + MB86297_CTRL_BASE;
799 par->i2c = par->mmio_base + MB86297_I2C_BASE;
800 par->disp = par->mmio_base + MB86297_DISP0_BASE;
801 par->disp1 = par->mmio_base + MB86297_DISP1_BASE;
802 par->cap = par->mmio_base + MB86297_CAP0_BASE;
803 par->cap1 = par->mmio_base + MB86297_CAP1_BASE;
804 par->draw = par->mmio_base + MB86297_DRAW_BASE;
805 par->dram_ctrl = par->mmio_base + MB86297_DRAMCTRL_BASE;
806 par->wrback = par->mmio_base + MB86297_WRBACK_BASE;
807
808 par->refclk = GC_DISP_REFCLK_533;
809
810 /* warm up */
811 reg = GC_CTRL_CLK_EN_DRAM | GC_CTRL_CLK_EN_2D3D | GC_CTRL_CLK_EN_DISP0;
812 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
813
814 /* check for engine module revision */
815 if (inreg(draw, GC_2D3D_REV) == GC_RE_REVISION)
816 dev_info(par->dev, "Fujitsu Carmine GDC Rev.%d found\n",
817 par->pdev->revision);
818 else
819 goto err_init;
820
821 reg &= ~GC_CTRL_CLK_EN_2D3D;
822 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
823
824 /* set up vram */
825 if (init_dram_ctrl(par) < 0)
826 goto err_init;
827
828 outreg(ctrl, GC_CTRL_INT_MASK, 0);
829 return 0;
830
831err_init:
832 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
833 return -EINVAL;
834}
835
836static inline int mb862xx_pci_gdc_init(struct mb862xxfb_par *par)
837{
838 switch (par->type) {
839 case BT_CORALP:
840 return coralp_init(par);
841 case BT_CARMINE:
842 return carmine_init(par);
843 default:
844 return -ENODEV;
845 }
846}
847
848#define CHIP_ID(id) \
849 { PCI_DEVICE(PCI_VENDOR_ID_FUJITSU_LIMITED, id) }
850
851static struct pci_device_id mb862xx_pci_tbl[] __devinitdata = {
852 /* MB86295/MB86296 */
853 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALP),
854 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALPA),
855 /* MB86297 */
856 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CARMINE),
857 { 0, }
858};
859
860MODULE_DEVICE_TABLE(pci, mb862xx_pci_tbl);
861
862static int __devinit mb862xx_pci_probe(struct pci_dev *pdev,
863 const struct pci_device_id *ent)
864{
865 struct mb862xxfb_par *par;
866 struct fb_info *info;
867 struct device *dev = &pdev->dev;
868 int ret;
869
870 ret = pci_enable_device(pdev);
871 if (ret < 0) {
872 dev_err(dev, "Cannot enable PCI device\n");
873 goto out;
874 }
875
876 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
877 if (!info) {
878 dev_err(dev, "framebuffer alloc failed\n");
879 ret = -ENOMEM;
880 goto dis_dev;
881 }
882
883 par = info->par;
884 par->info = info;
885 par->dev = dev;
886 par->pdev = pdev;
887 par->irq = pdev->irq;
888
889 ret = pci_request_regions(pdev, DRV_NAME);
890 if (ret < 0) {
891 dev_err(dev, "Cannot reserve region(s) for PCI device\n");
892 goto rel_fb;
893 }
894
895 switch (pdev->device) {
896 case PCI_DEVICE_ID_FUJITSU_CORALP:
897 case PCI_DEVICE_ID_FUJITSU_CORALPA:
898 par->fb_base_phys = pci_resource_start(par->pdev, 0);
899 par->mapped_vram = CORALP_MEM_SIZE;
900 par->mmio_base_phys = par->fb_base_phys + MB862XX_MMIO_BASE;
901 par->mmio_len = MB862XX_MMIO_SIZE;
902 par->type = BT_CORALP;
903 break;
904 case PCI_DEVICE_ID_FUJITSU_CARMINE:
905 par->fb_base_phys = pci_resource_start(par->pdev, 2);
906 par->mmio_base_phys = pci_resource_start(par->pdev, 3);
907 par->mmio_len = pci_resource_len(par->pdev, 3);
908 par->mapped_vram = CARMINE_MEM_SIZE;
909 par->type = BT_CARMINE;
910 break;
911 default:
912 /* should never occur */
913 goto rel_reg;
914 }
915
916 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
917 if (par->fb_base == NULL) {
918 dev_err(dev, "Cannot map framebuffer\n");
919 goto rel_reg;
920 }
921
922 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
923 if (par->mmio_base == NULL) {
924 dev_err(dev, "Cannot map registers\n");
925 ret = -EIO;
926 goto fb_unmap;
927 }
928
929 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
930 (u64)par->fb_base_phys, (ulong)par->mapped_vram);
931 dev_dbg(dev, "mmio phys 0x%llx 0x%lx\n",
932 (u64)par->mmio_base_phys, (ulong)par->mmio_len);
933
934 if (mb862xx_pci_gdc_init(par))
935 goto io_unmap;
936
937 if (request_irq(par->irq, mb862xx_intr, IRQF_DISABLED | IRQF_SHARED,
938 DRV_NAME, (void *)par)) {
939 dev_err(dev, "Cannot request irq\n");
940 goto io_unmap;
941 }
942
943 mb862xxfb_init_fbinfo(info);
944
945 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
946 dev_err(dev, "Could not allocate cmap for fb_info.\n");
947 ret = -ENOMEM;
948 goto free_irq;
949 }
950
951 if ((info->fbops->fb_set_par)(info))
952 dev_err(dev, "set_var() failed on initial setup?\n");
953
954 ret = register_framebuffer(info);
955 if (ret < 0) {
956 dev_err(dev, "failed to register framebuffer\n");
957 goto rel_cmap;
958 }
959
960 pci_set_drvdata(pdev, info);
961
962 if (device_create_file(dev, &dev_attr_dispregs))
963 dev_err(dev, "Can't create sysfs regdump file\n");
964
965 if (par->type == BT_CARMINE)
966 outreg(ctrl, GC_CTRL_INT_MASK, GC_CARMINE_INT_EN);
967 else
968 outreg(host, GC_IMASK, GC_INT_EN);
969
970 return 0;
971
972rel_cmap:
973 fb_dealloc_cmap(&info->cmap);
974free_irq:
975 free_irq(par->irq, (void *)par);
976io_unmap:
977 iounmap(par->mmio_base);
978fb_unmap:
979 iounmap(par->fb_base);
980rel_reg:
981 pci_release_regions(pdev);
982rel_fb:
983 framebuffer_release(info);
984dis_dev:
985 pci_disable_device(pdev);
986out:
987 return ret;
988}
989
990static void __devexit mb862xx_pci_remove(struct pci_dev *pdev)
991{
992 struct fb_info *fbi = pci_get_drvdata(pdev);
993 struct mb862xxfb_par *par = fbi->par;
994 unsigned long reg;
995
996 dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
997
998 /* display off */
999 reg = inreg(disp, GC_DCM1);
1000 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
1001 outreg(disp, GC_DCM1, reg);
1002
1003 if (par->type == BT_CARMINE) {
1004 outreg(ctrl, GC_CTRL_INT_MASK, 0);
1005 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
1006 } else {
1007 outreg(host, GC_IMASK, 0);
1008 }
1009
1010 device_remove_file(&pdev->dev, &dev_attr_dispregs);
1011
1012 pci_set_drvdata(pdev, NULL);
1013 unregister_framebuffer(fbi);
1014 fb_dealloc_cmap(&fbi->cmap);
1015
1016 free_irq(par->irq, (void *)par);
1017 iounmap(par->mmio_base);
1018 iounmap(par->fb_base);
1019
1020 pci_release_regions(pdev);
1021 framebuffer_release(fbi);
1022 pci_disable_device(pdev);
1023}
1024
1025static struct pci_driver mb862xxfb_pci_driver = {
1026 .name = DRV_NAME,
1027 .id_table = mb862xx_pci_tbl,
1028 .probe = mb862xx_pci_probe,
1029 .remove = __devexit_p(mb862xx_pci_remove),
1030};
1031#endif
1032
1033static int __devinit mb862xxfb_init(void)
1034{
1035 int ret = -ENODEV;
1036
1037#if defined(CONFIG_FB_MB862XX_LIME)
1038 ret = of_register_platform_driver(&of_platform_mb862xxfb_driver);
1039#endif
1040#if defined(CONFIG_FB_MB862XX_PCI_GDC)
1041 ret = pci_register_driver(&mb862xxfb_pci_driver);
1042#endif
1043 return ret;
1044}
1045
1046static void __exit mb862xxfb_exit(void)
1047{
1048#if defined(CONFIG_FB_MB862XX_LIME)
1049 of_unregister_platform_driver(&of_platform_mb862xxfb_driver);
1050#endif
1051#if defined(CONFIG_FB_MB862XX_PCI_GDC)
1052 pci_unregister_driver(&mb862xxfb_pci_driver);
1053#endif
1054}
1055
1056module_init(mb862xxfb_init);
1057module_exit(mb862xxfb_exit);
1058
1059MODULE_DESCRIPTION("Fujitsu MB862xx Framebuffer driver");
1060MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
1061MODULE_LICENSE("GPL v2");
diff --git a/drivers/video/mb862xx/mb862xxfb.h b/drivers/video/mb862xx/mb862xxfb.h
new file mode 100644
index 000000000000..c4c8f4dd2217
--- /dev/null
+++ b/drivers/video/mb862xx/mb862xxfb.h
@@ -0,0 +1,83 @@
1#ifndef __MB862XX_H__
2#define __MB862XX_H__
3
4#define PCI_VENDOR_ID_FUJITSU_LIMITED 0x10cf
5#define PCI_DEVICE_ID_FUJITSU_CORALP 0x2019
6#define PCI_DEVICE_ID_FUJITSU_CORALPA 0x201e
7#define PCI_DEVICE_ID_FUJITSU_CARMINE 0x202b
8
9#define GC_MMR_CORALP_EVB_VAL 0x11d7fa13
10
11enum gdctype {
12 BT_NONE,
13 BT_LIME,
14 BT_MINT,
15 BT_CORAL,
16 BT_CORALP,
17 BT_CARMINE,
18};
19
20struct mb862xx_gc_mode {
21 struct fb_videomode def_mode; /* mode of connected display */
22 unsigned int def_bpp; /* default depth */
23 unsigned long max_vram; /* connected SDRAM size */
24 unsigned long ccf; /* gdc clk */
25 unsigned long mmr; /* memory mode for SDRAM */
26};
27
28/* private data */
29struct mb862xxfb_par {
30 struct fb_info *info; /* fb info head */
31 struct device *dev;
32 struct pci_dev *pdev;
33 struct resource *res; /* framebuffer/mmio resource */
34
35 resource_size_t fb_base_phys; /* fb base, 36-bit PPC440EPx */
36 resource_size_t mmio_base_phys; /* io base addr */
37 void __iomem *fb_base; /* remapped framebuffer */
38 void __iomem *mmio_base; /* remapped registers */
39 size_t mapped_vram; /* length of remapped vram */
40 size_t mmio_len; /* length of register region */
41
42 void __iomem *host; /* relocatable reg. bases */
43 void __iomem *i2c;
44 void __iomem *disp;
45 void __iomem *disp1;
46 void __iomem *cap;
47 void __iomem *cap1;
48 void __iomem *draw;
49 void __iomem *geo;
50 void __iomem *pio;
51 void __iomem *ctrl;
52 void __iomem *dram_ctrl;
53 void __iomem *wrback;
54
55 unsigned int irq;
56 unsigned int type; /* GDC type */
57 unsigned int refclk; /* disp. reference clock */
58 struct mb862xx_gc_mode *gc_mode; /* GDC mode init data */
59 int pre_init; /* don't init display if 1 */
60
61 u32 pseudo_palette[16];
62};
63
64#if defined(CONFIG_FB_MB862XX_LIME) && defined(CONFIG_FB_MB862XX_PCI_GDC)
65#error "Select Lime GDC or CoralP/Carmine support, but not both together"
66#endif
67#if defined(CONFIG_FB_MB862XX_LIME)
68#define gdc_read __raw_readl
69#define gdc_write __raw_writel
70#else
71#define gdc_read readl
72#define gdc_write writel
73#endif
74
75#define inreg(type, off) \
76 gdc_read((par->type + (off)))
77
78#define outreg(type, off, val) \
79 gdc_write((val), (par->type + (off)))
80
81#define pack(a, b) (((a) << 16) | (b))
82
83#endif
diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c
index b4babfc31586..b1da287f90ec 100644
--- a/drivers/watchdog/at91sam9_wdt.c
+++ b/drivers/watchdog/at91sam9_wdt.c
@@ -30,7 +30,7 @@
30#include <linux/bitops.h> 30#include <linux/bitops.h>
31#include <linux/uaccess.h> 31#include <linux/uaccess.h>
32 32
33#include <asm/arch/at91_wdt.h> 33#include <mach/at91_wdt.h>
34 34
35#define DRV_NAME "AT91SAM9 Watchdog" 35#define DRV_NAME "AT91SAM9 Watchdog"
36 36
diff --git a/drivers/xen/balloon.c b/drivers/xen/balloon.c
index 8c83abc73400..a0fb5eac407c 100644
--- a/drivers/xen/balloon.c
+++ b/drivers/xen/balloon.c
@@ -41,7 +41,6 @@
41#include <linux/pagemap.h> 41#include <linux/pagemap.h>
42#include <linux/highmem.h> 42#include <linux/highmem.h>
43#include <linux/mutex.h> 43#include <linux/mutex.h>
44#include <linux/highmem.h>
45#include <linux/list.h> 44#include <linux/list.h>
46#include <linux/sysdev.h> 45#include <linux/sysdev.h>
47 46
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 16:24:59 -0500