aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/atlx/atl1.c1406
-rw-r--r--drivers/net/atlx/atl1.h10
2 files changed, 703 insertions, 713 deletions
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index 6f4a1d5376bc..240db847e129 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -108,6 +108,709 @@ module_param(debug, int, 0);
108MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)"); 108MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)");
109 109
110/* 110/*
111 * Reset the transmit and receive units; mask and clear all interrupts.
112 * hw - Struct containing variables accessed by shared code
113 * return : 0 or idle status (if error)
114 */
115static s32 atl1_reset_hw(struct atl1_hw *hw)
116{
117 struct pci_dev *pdev = hw->back->pdev;
118 struct atl1_adapter *adapter = hw->back;
119 u32 icr;
120 int i;
121
122 /*
123 * Clear Interrupt mask to stop board from generating
124 * interrupts & Clear any pending interrupt events
125 */
126 /*
127 * iowrite32(0, hw->hw_addr + REG_IMR);
128 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
129 */
130
131 /*
132 * Issue Soft Reset to the MAC. This will reset the chip's
133 * transmit, receive, DMA. It will not effect
134 * the current PCI configuration. The global reset bit is self-
135 * clearing, and should clear within a microsecond.
136 */
137 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
138 ioread32(hw->hw_addr + REG_MASTER_CTRL);
139
140 iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
141 ioread16(hw->hw_addr + REG_PHY_ENABLE);
142
143 /* delay about 1ms */
144 msleep(1);
145
146 /* Wait at least 10ms for All module to be Idle */
147 for (i = 0; i < 10; i++) {
148 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
149 if (!icr)
150 break;
151 /* delay 1 ms */
152 msleep(1);
153 /* FIXME: still the right way to do this? */
154 cpu_relax();
155 }
156
157 if (icr) {
158 if (netif_msg_hw(adapter))
159 dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
160 return icr;
161 }
162
163 return 0;
164}
165
166/* function about EEPROM
167 *
168 * check_eeprom_exist
169 * return 0 if eeprom exist
170 */
171static int atl1_check_eeprom_exist(struct atl1_hw *hw)
172{
173 u32 value;
174 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
175 if (value & SPI_FLASH_CTRL_EN_VPD) {
176 value &= ~SPI_FLASH_CTRL_EN_VPD;
177 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
178 }
179
180 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
181 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
182}
183
184static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
185{
186 int i;
187 u32 control;
188
189 if (offset & 3)
190 /* address do not align */
191 return false;
192
193 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
194 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
195 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
196 ioread32(hw->hw_addr + REG_VPD_CAP);
197
198 for (i = 0; i < 10; i++) {
199 msleep(2);
200 control = ioread32(hw->hw_addr + REG_VPD_CAP);
201 if (control & VPD_CAP_VPD_FLAG)
202 break;
203 }
204 if (control & VPD_CAP_VPD_FLAG) {
205 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
206 return true;
207 }
208 /* timeout */
209 return false;
210}
211
212/*
213 * Reads the value from a PHY register
214 * hw - Struct containing variables accessed by shared code
215 * reg_addr - address of the PHY register to read
216 */
217s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
218{
219 u32 val;
220 int i;
221
222 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
223 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
224 MDIO_CLK_SEL_SHIFT;
225 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
226 ioread32(hw->hw_addr + REG_MDIO_CTRL);
227
228 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
229 udelay(2);
230 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
231 if (!(val & (MDIO_START | MDIO_BUSY)))
232 break;
233 }
234 if (!(val & (MDIO_START | MDIO_BUSY))) {
235 *phy_data = (u16) val;
236 return 0;
237 }
238 return ATLX_ERR_PHY;
239}
240
241#define CUSTOM_SPI_CS_SETUP 2
242#define CUSTOM_SPI_CLK_HI 2
243#define CUSTOM_SPI_CLK_LO 2
244#define CUSTOM_SPI_CS_HOLD 2
245#define CUSTOM_SPI_CS_HI 3
246
247static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
248{
249 int i;
250 u32 value;
251
252 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
253 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
254
255 value = SPI_FLASH_CTRL_WAIT_READY |
256 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
257 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
258 SPI_FLASH_CTRL_CLK_HI_MASK) <<
259 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
260 SPI_FLASH_CTRL_CLK_LO_MASK) <<
261 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
262 SPI_FLASH_CTRL_CS_HOLD_MASK) <<
263 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
264 SPI_FLASH_CTRL_CS_HI_MASK) <<
265 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
266 SPI_FLASH_CTRL_INS_SHIFT;
267
268 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
269
270 value |= SPI_FLASH_CTRL_START;
271 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
272 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
273
274 for (i = 0; i < 10; i++) {
275 msleep(1);
276 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
277 if (!(value & SPI_FLASH_CTRL_START))
278 break;
279 }
280
281 if (value & SPI_FLASH_CTRL_START)
282 return false;
283
284 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
285
286 return true;
287}
288
289/*
290 * get_permanent_address
291 * return 0 if get valid mac address,
292 */
293static int atl1_get_permanent_address(struct atl1_hw *hw)
294{
295 u32 addr[2];
296 u32 i, control;
297 u16 reg;
298 u8 eth_addr[ETH_ALEN];
299 bool key_valid;
300
301 if (is_valid_ether_addr(hw->perm_mac_addr))
302 return 0;
303
304 /* init */
305 addr[0] = addr[1] = 0;
306
307 if (!atl1_check_eeprom_exist(hw)) {
308 reg = 0;
309 key_valid = false;
310 /* Read out all EEPROM content */
311 i = 0;
312 while (1) {
313 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
314 if (key_valid) {
315 if (reg == REG_MAC_STA_ADDR)
316 addr[0] = control;
317 else if (reg == (REG_MAC_STA_ADDR + 4))
318 addr[1] = control;
319 key_valid = false;
320 } else if ((control & 0xff) == 0x5A) {
321 key_valid = true;
322 reg = (u16) (control >> 16);
323 } else
324 break;
325 } else
326 /* read error */
327 break;
328 i += 4;
329 }
330
331 *(u32 *) &eth_addr[2] = swab32(addr[0]);
332 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
333 if (is_valid_ether_addr(eth_addr)) {
334 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
335 return 0;
336 }
337 return 1;
338 }
339
340 /* see if SPI FLAGS exist ? */
341 addr[0] = addr[1] = 0;
342 reg = 0;
343 key_valid = false;
344 i = 0;
345 while (1) {
346 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
347 if (key_valid) {
348 if (reg == REG_MAC_STA_ADDR)
349 addr[0] = control;
350 else if (reg == (REG_MAC_STA_ADDR + 4))
351 addr[1] = control;
352 key_valid = false;
353 } else if ((control & 0xff) == 0x5A) {
354 key_valid = true;
355 reg = (u16) (control >> 16);
356 } else
357 /* data end */
358 break;
359 } else
360 /* read error */
361 break;
362 i += 4;
363 }
364
365 *(u32 *) &eth_addr[2] = swab32(addr[0]);
366 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
367 if (is_valid_ether_addr(eth_addr)) {
368 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
369 return 0;
370 }
371
372 /*
373 * On some motherboards, the MAC address is written by the
374 * BIOS directly to the MAC register during POST, and is
375 * not stored in eeprom. If all else thus far has failed
376 * to fetch the permanent MAC address, try reading it directly.
377 */
378 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
379 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
380 *(u32 *) &eth_addr[2] = swab32(addr[0]);
381 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
382 if (is_valid_ether_addr(eth_addr)) {
383 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
384 return 0;
385 }
386
387 return 1;
388}
389
390/*
391 * Reads the adapter's MAC address from the EEPROM
392 * hw - Struct containing variables accessed by shared code
393 */
394s32 atl1_read_mac_addr(struct atl1_hw *hw)
395{
396 u16 i;
397
398 if (atl1_get_permanent_address(hw))
399 random_ether_addr(hw->perm_mac_addr);
400
401 for (i = 0; i < ETH_ALEN; i++)
402 hw->mac_addr[i] = hw->perm_mac_addr[i];
403 return 0;
404}
405
406/*
407 * Hashes an address to determine its location in the multicast table
408 * hw - Struct containing variables accessed by shared code
409 * mc_addr - the multicast address to hash
410 *
411 * atl1_hash_mc_addr
412 * purpose
413 * set hash value for a multicast address
414 * hash calcu processing :
415 * 1. calcu 32bit CRC for multicast address
416 * 2. reverse crc with MSB to LSB
417 */
418u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
419{
420 u32 crc32, value = 0;
421 int i;
422
423 crc32 = ether_crc_le(6, mc_addr);
424 for (i = 0; i < 32; i++)
425 value |= (((crc32 >> i) & 1) << (31 - i));
426
427 return value;
428}
429
430/*
431 * Sets the bit in the multicast table corresponding to the hash value.
432 * hw - Struct containing variables accessed by shared code
433 * hash_value - Multicast address hash value
434 */
435void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
436{
437 u32 hash_bit, hash_reg;
438 u32 mta;
439
440 /*
441 * The HASH Table is a register array of 2 32-bit registers.
442 * It is treated like an array of 64 bits. We want to set
443 * bit BitArray[hash_value]. So we figure out what register
444 * the bit is in, read it, OR in the new bit, then write
445 * back the new value. The register is determined by the
446 * upper 7 bits of the hash value and the bit within that
447 * register are determined by the lower 5 bits of the value.
448 */
449 hash_reg = (hash_value >> 31) & 0x1;
450 hash_bit = (hash_value >> 26) & 0x1F;
451 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
452 mta |= (1 << hash_bit);
453 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
454}
455
456/*
457 * Writes a value to a PHY register
458 * hw - Struct containing variables accessed by shared code
459 * reg_addr - address of the PHY register to write
460 * data - data to write to the PHY
461 */
462static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
463{
464 int i;
465 u32 val;
466
467 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
468 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
469 MDIO_SUP_PREAMBLE |
470 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
471 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
472 ioread32(hw->hw_addr + REG_MDIO_CTRL);
473
474 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
475 udelay(2);
476 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
477 if (!(val & (MDIO_START | MDIO_BUSY)))
478 break;
479 }
480
481 if (!(val & (MDIO_START | MDIO_BUSY)))
482 return 0;
483
484 return ATLX_ERR_PHY;
485}
486
487/*
488 * Make L001's PHY out of Power Saving State (bug)
489 * hw - Struct containing variables accessed by shared code
490 * when power on, L001's PHY always on Power saving State
491 * (Gigabit Link forbidden)
492 */
493static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
494{
495 s32 ret;
496 ret = atl1_write_phy_reg(hw, 29, 0x0029);
497 if (ret)
498 return ret;
499 return atl1_write_phy_reg(hw, 30, 0);
500}
501
502/*
503 *TODO: do something or get rid of this
504 */
505static s32 atl1_phy_enter_power_saving(struct atl1_hw *hw)
506{
507/* s32 ret_val;
508 * u16 phy_data;
509 */
510
511/*
512 ret_val = atl1_write_phy_reg(hw, ...);
513 ret_val = atl1_write_phy_reg(hw, ...);
514 ....
515*/
516 return 0;
517}
518
519/*
520 * Resets the PHY and make all config validate
521 * hw - Struct containing variables accessed by shared code
522 *
523 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
524 */
525static s32 atl1_phy_reset(struct atl1_hw *hw)
526{
527 struct pci_dev *pdev = hw->back->pdev;
528 struct atl1_adapter *adapter = hw->back;
529 s32 ret_val;
530 u16 phy_data;
531
532 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
533 hw->media_type == MEDIA_TYPE_1000M_FULL)
534 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
535 else {
536 switch (hw->media_type) {
537 case MEDIA_TYPE_100M_FULL:
538 phy_data =
539 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
540 MII_CR_RESET;
541 break;
542 case MEDIA_TYPE_100M_HALF:
543 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
544 break;
545 case MEDIA_TYPE_10M_FULL:
546 phy_data =
547 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
548 break;
549 default:
550 /* MEDIA_TYPE_10M_HALF: */
551 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
552 break;
553 }
554 }
555
556 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
557 if (ret_val) {
558 u32 val;
559 int i;
560 /* pcie serdes link may be down! */
561 if (netif_msg_hw(adapter))
562 dev_dbg(&pdev->dev, "pcie phy link down\n");
563
564 for (i = 0; i < 25; i++) {
565 msleep(1);
566 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
567 if (!(val & (MDIO_START | MDIO_BUSY)))
568 break;
569 }
570
571 if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
572 if (netif_msg_hw(adapter))
573 dev_warn(&pdev->dev,
574 "pcie link down at least 25ms\n");
575 return ret_val;
576 }
577 }
578 return 0;
579}
580
581/*
582 * Configures PHY autoneg and flow control advertisement settings
583 * hw - Struct containing variables accessed by shared code
584 */
585static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
586{
587 s32 ret_val;
588 s16 mii_autoneg_adv_reg;
589 s16 mii_1000t_ctrl_reg;
590
591 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
592 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
593
594 /* Read the MII 1000Base-T Control Register (Address 9). */
595 mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK;
596
597 /*
598 * First we clear all the 10/100 mb speed bits in the Auto-Neg
599 * Advertisement Register (Address 4) and the 1000 mb speed bits in
600 * the 1000Base-T Control Register (Address 9).
601 */
602 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
603 mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK;
604
605 /*
606 * Need to parse media_type and set up
607 * the appropriate PHY registers.
608 */
609 switch (hw->media_type) {
610 case MEDIA_TYPE_AUTO_SENSOR:
611 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
612 MII_AR_10T_FD_CAPS |
613 MII_AR_100TX_HD_CAPS |
614 MII_AR_100TX_FD_CAPS);
615 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
616 break;
617
618 case MEDIA_TYPE_1000M_FULL:
619 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
620 break;
621
622 case MEDIA_TYPE_100M_FULL:
623 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
624 break;
625
626 case MEDIA_TYPE_100M_HALF:
627 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
628 break;
629
630 case MEDIA_TYPE_10M_FULL:
631 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
632 break;
633
634 default:
635 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
636 break;
637 }
638
639 /* flow control fixed to enable all */
640 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
641
642 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
643 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
644
645 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
646 if (ret_val)
647 return ret_val;
648
649 ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg);
650 if (ret_val)
651 return ret_val;
652
653 return 0;
654}
655
656/*
657 * Configures link settings.
658 * hw - Struct containing variables accessed by shared code
659 * Assumes the hardware has previously been reset and the
660 * transmitter and receiver are not enabled.
661 */
662static s32 atl1_setup_link(struct atl1_hw *hw)
663{
664 struct pci_dev *pdev = hw->back->pdev;
665 struct atl1_adapter *adapter = hw->back;
666 s32 ret_val;
667
668 /*
669 * Options:
670 * PHY will advertise value(s) parsed from
671 * autoneg_advertised and fc
672 * no matter what autoneg is , We will not wait link result.
673 */
674 ret_val = atl1_phy_setup_autoneg_adv(hw);
675 if (ret_val) {
676 if (netif_msg_link(adapter))
677 dev_dbg(&pdev->dev,
678 "error setting up autonegotiation\n");
679 return ret_val;
680 }
681 /* SW.Reset , En-Auto-Neg if needed */
682 ret_val = atl1_phy_reset(hw);
683 if (ret_val) {
684 if (netif_msg_link(adapter))
685 dev_dbg(&pdev->dev, "error resetting phy\n");
686 return ret_val;
687 }
688 hw->phy_configured = true;
689 return ret_val;
690}
691
692static void atl1_init_flash_opcode(struct atl1_hw *hw)
693{
694 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
695 /* Atmel */
696 hw->flash_vendor = 0;
697
698 /* Init OP table */
699 iowrite8(flash_table[hw->flash_vendor].cmd_program,
700 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
701 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
702 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
703 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
704 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
705 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
706 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
707 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
708 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
709 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
710 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
711 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
712 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
713 iowrite8(flash_table[hw->flash_vendor].cmd_read,
714 hw->hw_addr + REG_SPI_FLASH_OP_READ);
715}
716
717/*
718 * Performs basic configuration of the adapter.
719 * hw - Struct containing variables accessed by shared code
720 * Assumes that the controller has previously been reset and is in a
721 * post-reset uninitialized state. Initializes multicast table,
722 * and Calls routines to setup link
723 * Leaves the transmit and receive units disabled and uninitialized.
724 */
725static s32 atl1_init_hw(struct atl1_hw *hw)
726{
727 u32 ret_val = 0;
728
729 /* Zero out the Multicast HASH table */
730 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
731 /* clear the old settings from the multicast hash table */
732 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
733
734 atl1_init_flash_opcode(hw);
735
736 if (!hw->phy_configured) {
737 /* enable GPHY LinkChange Interrrupt */
738 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
739 if (ret_val)
740 return ret_val;
741 /* make PHY out of power-saving state */
742 ret_val = atl1_phy_leave_power_saving(hw);
743 if (ret_val)
744 return ret_val;
745 /* Call a subroutine to configure the link */
746 ret_val = atl1_setup_link(hw);
747 }
748 return ret_val;
749}
750
751/*
752 * Detects the current speed and duplex settings of the hardware.
753 * hw - Struct containing variables accessed by shared code
754 * speed - Speed of the connection
755 * duplex - Duplex setting of the connection
756 */
757static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
758{
759 struct pci_dev *pdev = hw->back->pdev;
760 struct atl1_adapter *adapter = hw->back;
761 s32 ret_val;
762 u16 phy_data;
763
764 /* ; --- Read PHY Specific Status Register (17) */
765 ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
766 if (ret_val)
767 return ret_val;
768
769 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
770 return ATLX_ERR_PHY_RES;
771
772 switch (phy_data & MII_ATLX_PSSR_SPEED) {
773 case MII_ATLX_PSSR_1000MBS:
774 *speed = SPEED_1000;
775 break;
776 case MII_ATLX_PSSR_100MBS:
777 *speed = SPEED_100;
778 break;
779 case MII_ATLX_PSSR_10MBS:
780 *speed = SPEED_10;
781 break;
782 default:
783 if (netif_msg_hw(adapter))
784 dev_dbg(&pdev->dev, "error getting speed\n");
785 return ATLX_ERR_PHY_SPEED;
786 break;
787 }
788 if (phy_data & MII_ATLX_PSSR_DPLX)
789 *duplex = FULL_DUPLEX;
790 else
791 *duplex = HALF_DUPLEX;
792
793 return 0;
794}
795
796void atl1_set_mac_addr(struct atl1_hw *hw)
797{
798 u32 value;
799 /*
800 * 00-0B-6A-F6-00-DC
801 * 0: 6AF600DC 1: 000B
802 * low dword
803 */
804 value = (((u32) hw->mac_addr[2]) << 24) |
805 (((u32) hw->mac_addr[3]) << 16) |
806 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
807 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
808 /* high dword */
809 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
810 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
811}
812
813/*
111 * atl1_sw_init - Initialize general software structures (struct atl1_adapter) 814 * atl1_sw_init - Initialize general software structures (struct atl1_adapter)
112 * @adapter: board private structure to initialize 815 * @adapter: board private structure to initialize
113 * 816 *
@@ -2860,706 +3563,3 @@ const struct ethtool_ops atl1_ethtool_ops = {
2860 .get_sset_count = atl1_get_sset_count, 3563 .get_sset_count = atl1_get_sset_count,
2861 .set_tso = ethtool_op_set_tso, 3564 .set_tso = ethtool_op_set_tso,
2862}; 3565};
2863
2864/*
2865 * Reset the transmit and receive units; mask and clear all interrupts.
2866 * hw - Struct containing variables accessed by shared code
2867 * return : 0 or idle status (if error)
2868 */
2869s32 atl1_reset_hw(struct atl1_hw *hw)
2870{
2871 struct pci_dev *pdev = hw->back->pdev;
2872 struct atl1_adapter *adapter = hw->back;
2873 u32 icr;
2874 int i;
2875
2876 /*
2877 * Clear Interrupt mask to stop board from generating
2878 * interrupts & Clear any pending interrupt events
2879 */
2880 /*
2881 * iowrite32(0, hw->hw_addr + REG_IMR);
2882 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
2883 */
2884
2885 /*
2886 * Issue Soft Reset to the MAC. This will reset the chip's
2887 * transmit, receive, DMA. It will not effect
2888 * the current PCI configuration. The global reset bit is self-
2889 * clearing, and should clear within a microsecond.
2890 */
2891 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
2892 ioread32(hw->hw_addr + REG_MASTER_CTRL);
2893
2894 iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
2895 ioread16(hw->hw_addr + REG_PHY_ENABLE);
2896
2897 /* delay about 1ms */
2898 msleep(1);
2899
2900 /* Wait at least 10ms for All module to be Idle */
2901 for (i = 0; i < 10; i++) {
2902 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
2903 if (!icr)
2904 break;
2905 /* delay 1 ms */
2906 msleep(1);
2907 /* FIXME: still the right way to do this? */
2908 cpu_relax();
2909 }
2910
2911 if (icr) {
2912 if (netif_msg_hw(adapter))
2913 dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
2914 return icr;
2915 }
2916
2917 return 0;
2918}
2919
2920/* function about EEPROM
2921 *
2922 * check_eeprom_exist
2923 * return 0 if eeprom exist
2924 */
2925static int atl1_check_eeprom_exist(struct atl1_hw *hw)
2926{
2927 u32 value;
2928 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
2929 if (value & SPI_FLASH_CTRL_EN_VPD) {
2930 value &= ~SPI_FLASH_CTRL_EN_VPD;
2931 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
2932 }
2933
2934 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
2935 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
2936}
2937
2938static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
2939{
2940 int i;
2941 u32 control;
2942
2943 if (offset & 3)
2944 /* address do not align */
2945 return false;
2946
2947 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
2948 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
2949 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
2950 ioread32(hw->hw_addr + REG_VPD_CAP);
2951
2952 for (i = 0; i < 10; i++) {
2953 msleep(2);
2954 control = ioread32(hw->hw_addr + REG_VPD_CAP);
2955 if (control & VPD_CAP_VPD_FLAG)
2956 break;
2957 }
2958 if (control & VPD_CAP_VPD_FLAG) {
2959 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
2960 return true;
2961 }
2962 /* timeout */
2963 return false;
2964}
2965
2966/*
2967 * Reads the value from a PHY register
2968 * hw - Struct containing variables accessed by shared code
2969 * reg_addr - address of the PHY register to read
2970 */
2971s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
2972{
2973 u32 val;
2974 int i;
2975
2976 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
2977 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
2978 MDIO_CLK_SEL_SHIFT;
2979 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
2980 ioread32(hw->hw_addr + REG_MDIO_CTRL);
2981
2982 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2983 udelay(2);
2984 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
2985 if (!(val & (MDIO_START | MDIO_BUSY)))
2986 break;
2987 }
2988 if (!(val & (MDIO_START | MDIO_BUSY))) {
2989 *phy_data = (u16) val;
2990 return 0;
2991 }
2992 return ATLX_ERR_PHY;
2993}
2994
2995#define CUSTOM_SPI_CS_SETUP 2
2996#define CUSTOM_SPI_CLK_HI 2
2997#define CUSTOM_SPI_CLK_LO 2
2998#define CUSTOM_SPI_CS_HOLD 2
2999#define CUSTOM_SPI_CS_HI 3
3000
3001static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
3002{
3003 int i;
3004 u32 value;
3005
3006 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
3007 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
3008
3009 value = SPI_FLASH_CTRL_WAIT_READY |
3010 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
3011 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
3012 SPI_FLASH_CTRL_CLK_HI_MASK) <<
3013 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
3014 SPI_FLASH_CTRL_CLK_LO_MASK) <<
3015 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
3016 SPI_FLASH_CTRL_CS_HOLD_MASK) <<
3017 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
3018 SPI_FLASH_CTRL_CS_HI_MASK) <<
3019 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
3020 SPI_FLASH_CTRL_INS_SHIFT;
3021
3022 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
3023
3024 value |= SPI_FLASH_CTRL_START;
3025 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
3026 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
3027
3028 for (i = 0; i < 10; i++) {
3029 msleep(1);
3030 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
3031 if (!(value & SPI_FLASH_CTRL_START))
3032 break;
3033 }
3034
3035 if (value & SPI_FLASH_CTRL_START)
3036 return false;
3037
3038 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
3039
3040 return true;
3041}
3042
3043/*
3044 * get_permanent_address
3045 * return 0 if get valid mac address,
3046 */
3047static int atl1_get_permanent_address(struct atl1_hw *hw)
3048{
3049 u32 addr[2];
3050 u32 i, control;
3051 u16 reg;
3052 u8 eth_addr[ETH_ALEN];
3053 bool key_valid;
3054
3055 if (is_valid_ether_addr(hw->perm_mac_addr))
3056 return 0;
3057
3058 /* init */
3059 addr[0] = addr[1] = 0;
3060
3061 if (!atl1_check_eeprom_exist(hw)) {
3062 reg = 0;
3063 key_valid = false;
3064 /* Read out all EEPROM content */
3065 i = 0;
3066 while (1) {
3067 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
3068 if (key_valid) {
3069 if (reg == REG_MAC_STA_ADDR)
3070 addr[0] = control;
3071 else if (reg == (REG_MAC_STA_ADDR + 4))
3072 addr[1] = control;
3073 key_valid = false;
3074 } else if ((control & 0xff) == 0x5A) {
3075 key_valid = true;
3076 reg = (u16) (control >> 16);
3077 } else
3078 break;
3079 } else
3080 /* read error */
3081 break;
3082 i += 4;
3083 }
3084
3085 *(u32 *) &eth_addr[2] = swab32(addr[0]);
3086 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
3087 if (is_valid_ether_addr(eth_addr)) {
3088 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
3089 return 0;
3090 }
3091 return 1;
3092 }
3093
3094 /* see if SPI FLAGS exist ? */
3095 addr[0] = addr[1] = 0;
3096 reg = 0;
3097 key_valid = false;
3098 i = 0;
3099 while (1) {
3100 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
3101 if (key_valid) {
3102 if (reg == REG_MAC_STA_ADDR)
3103 addr[0] = control;
3104 else if (reg == (REG_MAC_STA_ADDR + 4))
3105 addr[1] = control;
3106 key_valid = false;
3107 } else if ((control & 0xff) == 0x5A) {
3108 key_valid = true;
3109 reg = (u16) (control >> 16);
3110 } else
3111 /* data end */
3112 break;
3113 } else
3114 /* read error */
3115 break;
3116 i += 4;
3117 }
3118
3119 *(u32 *) &eth_addr[2] = swab32(addr[0]);
3120 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
3121 if (is_valid_ether_addr(eth_addr)) {
3122 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
3123 return 0;
3124 }
3125
3126 /*
3127 * On some motherboards, the MAC address is written by the
3128 * BIOS directly to the MAC register during POST, and is
3129 * not stored in eeprom. If all else thus far has failed
3130 * to fetch the permanent MAC address, try reading it directly.
3131 */
3132 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
3133 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
3134 *(u32 *) &eth_addr[2] = swab32(addr[0]);
3135 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
3136 if (is_valid_ether_addr(eth_addr)) {
3137 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
3138 return 0;
3139 }
3140
3141 return 1;
3142}
3143
3144/*
3145 * Reads the adapter's MAC address from the EEPROM
3146 * hw - Struct containing variables accessed by shared code
3147 */
3148s32 atl1_read_mac_addr(struct atl1_hw *hw)
3149{
3150 u16 i;
3151
3152 if (atl1_get_permanent_address(hw))
3153 random_ether_addr(hw->perm_mac_addr);
3154
3155 for (i = 0; i < ETH_ALEN; i++)
3156 hw->mac_addr[i] = hw->perm_mac_addr[i];
3157 return 0;
3158}
3159
3160/*
3161 * Hashes an address to determine its location in the multicast table
3162 * hw - Struct containing variables accessed by shared code
3163 * mc_addr - the multicast address to hash
3164 *
3165 * atl1_hash_mc_addr
3166 * purpose
3167 * set hash value for a multicast address
3168 * hash calcu processing :
3169 * 1. calcu 32bit CRC for multicast address
3170 * 2. reverse crc with MSB to LSB
3171 */
3172u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
3173{
3174 u32 crc32, value = 0;
3175 int i;
3176
3177 crc32 = ether_crc_le(6, mc_addr);
3178 for (i = 0; i < 32; i++)
3179 value |= (((crc32 >> i) & 1) << (31 - i));
3180
3181 return value;
3182}
3183
3184/*
3185 * Sets the bit in the multicast table corresponding to the hash value.
3186 * hw - Struct containing variables accessed by shared code
3187 * hash_value - Multicast address hash value
3188 */
3189void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
3190{
3191 u32 hash_bit, hash_reg;
3192 u32 mta;
3193
3194 /*
3195 * The HASH Table is a register array of 2 32-bit registers.
3196 * It is treated like an array of 64 bits. We want to set
3197 * bit BitArray[hash_value]. So we figure out what register
3198 * the bit is in, read it, OR in the new bit, then write
3199 * back the new value. The register is determined by the
3200 * upper 7 bits of the hash value and the bit within that
3201 * register are determined by the lower 5 bits of the value.
3202 */
3203 hash_reg = (hash_value >> 31) & 0x1;
3204 hash_bit = (hash_value >> 26) & 0x1F;
3205 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
3206 mta |= (1 << hash_bit);
3207 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
3208}
3209
3210/*
3211 * Writes a value to a PHY register
3212 * hw - Struct containing variables accessed by shared code
3213 * reg_addr - address of the PHY register to write
3214 * data - data to write to the PHY
3215 */
3216s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
3217{
3218 int i;
3219 u32 val;
3220
3221 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
3222 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
3223 MDIO_SUP_PREAMBLE |
3224 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
3225 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
3226 ioread32(hw->hw_addr + REG_MDIO_CTRL);
3227
3228 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
3229 udelay(2);
3230 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
3231 if (!(val & (MDIO_START | MDIO_BUSY)))
3232 break;
3233 }
3234
3235 if (!(val & (MDIO_START | MDIO_BUSY)))
3236 return 0;
3237
3238 return ATLX_ERR_PHY;
3239}
3240
3241/*
3242 * Make L001's PHY out of Power Saving State (bug)
3243 * hw - Struct containing variables accessed by shared code
3244 * when power on, L001's PHY always on Power saving State
3245 * (Gigabit Link forbidden)
3246 */
3247static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
3248{
3249 s32 ret;
3250 ret = atl1_write_phy_reg(hw, 29, 0x0029);
3251 if (ret)
3252 return ret;
3253 return atl1_write_phy_reg(hw, 30, 0);
3254}
3255
3256/*
3257 *TODO: do something or get rid of this
3258 */
3259s32 atl1_phy_enter_power_saving(struct atl1_hw *hw)
3260{
3261/* s32 ret_val;
3262 * u16 phy_data;
3263 */
3264
3265/*
3266 ret_val = atl1_write_phy_reg(hw, ...);
3267 ret_val = atl1_write_phy_reg(hw, ...);
3268 ....
3269*/
3270 return 0;
3271}
3272
3273/*
3274 * Resets the PHY and make all config validate
3275 * hw - Struct containing variables accessed by shared code
3276 *
3277 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
3278 */
3279static s32 atl1_phy_reset(struct atl1_hw *hw)
3280{
3281 struct pci_dev *pdev = hw->back->pdev;
3282 struct atl1_adapter *adapter = hw->back;
3283 s32 ret_val;
3284 u16 phy_data;
3285
3286 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3287 hw->media_type == MEDIA_TYPE_1000M_FULL)
3288 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3289 else {
3290 switch (hw->media_type) {
3291 case MEDIA_TYPE_100M_FULL:
3292 phy_data =
3293 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
3294 MII_CR_RESET;
3295 break;
3296 case MEDIA_TYPE_100M_HALF:
3297 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3298 break;
3299 case MEDIA_TYPE_10M_FULL:
3300 phy_data =
3301 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
3302 break;
3303 default:
3304 /* MEDIA_TYPE_10M_HALF: */
3305 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3306 break;
3307 }
3308 }
3309
3310 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3311 if (ret_val) {
3312 u32 val;
3313 int i;
3314 /* pcie serdes link may be down! */
3315 if (netif_msg_hw(adapter))
3316 dev_dbg(&pdev->dev, "pcie phy link down\n");
3317
3318 for (i = 0; i < 25; i++) {
3319 msleep(1);
3320 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
3321 if (!(val & (MDIO_START | MDIO_BUSY)))
3322 break;
3323 }
3324
3325 if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
3326 if (netif_msg_hw(adapter))
3327 dev_warn(&pdev->dev,
3328 "pcie link down at least 25ms\n");
3329 return ret_val;
3330 }
3331 }
3332 return 0;
3333}
3334
3335/*
3336 * Configures PHY autoneg and flow control advertisement settings
3337 * hw - Struct containing variables accessed by shared code
3338 */
3339s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
3340{
3341 s32 ret_val;
3342 s16 mii_autoneg_adv_reg;
3343 s16 mii_1000t_ctrl_reg;
3344
3345 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3346 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
3347
3348 /* Read the MII 1000Base-T Control Register (Address 9). */
3349 mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK;
3350
3351 /*
3352 * First we clear all the 10/100 mb speed bits in the Auto-Neg
3353 * Advertisement Register (Address 4) and the 1000 mb speed bits in
3354 * the 1000Base-T Control Register (Address 9).
3355 */
3356 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
3357 mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK;
3358
3359 /*
3360 * Need to parse media_type and set up
3361 * the appropriate PHY registers.
3362 */
3363 switch (hw->media_type) {
3364 case MEDIA_TYPE_AUTO_SENSOR:
3365 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
3366 MII_AR_10T_FD_CAPS |
3367 MII_AR_100TX_HD_CAPS |
3368 MII_AR_100TX_FD_CAPS);
3369 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
3370 break;
3371
3372 case MEDIA_TYPE_1000M_FULL:
3373 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
3374 break;
3375
3376 case MEDIA_TYPE_100M_FULL:
3377 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
3378 break;
3379
3380 case MEDIA_TYPE_100M_HALF:
3381 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
3382 break;
3383
3384 case MEDIA_TYPE_10M_FULL:
3385 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
3386 break;
3387
3388 default:
3389 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
3390 break;
3391 }
3392
3393 /* flow control fixed to enable all */
3394 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
3395
3396 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
3397 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
3398
3399 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
3400 if (ret_val)
3401 return ret_val;
3402
3403 ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg);
3404 if (ret_val)
3405 return ret_val;
3406
3407 return 0;
3408}
3409
3410/*
3411 * Configures link settings.
3412 * hw - Struct containing variables accessed by shared code
3413 * Assumes the hardware has previously been reset and the
3414 * transmitter and receiver are not enabled.
3415 */
3416static s32 atl1_setup_link(struct atl1_hw *hw)
3417{
3418 struct pci_dev *pdev = hw->back->pdev;
3419 struct atl1_adapter *adapter = hw->back;
3420 s32 ret_val;
3421
3422 /*
3423 * Options:
3424 * PHY will advertise value(s) parsed from
3425 * autoneg_advertised and fc
3426 * no matter what autoneg is , We will not wait link result.
3427 */
3428 ret_val = atl1_phy_setup_autoneg_adv(hw);
3429 if (ret_val) {
3430 if (netif_msg_link(adapter))
3431 dev_dbg(&pdev->dev,
3432 "error setting up autonegotiation\n");
3433 return ret_val;
3434 }
3435 /* SW.Reset , En-Auto-Neg if needed */
3436 ret_val = atl1_phy_reset(hw);
3437 if (ret_val) {
3438 if (netif_msg_link(adapter))
3439 dev_dbg(&pdev->dev, "error resetting phy\n");
3440 return ret_val;
3441 }
3442 hw->phy_configured = true;
3443 return ret_val;
3444}
3445
3446static void atl1_init_flash_opcode(struct atl1_hw *hw)
3447{
3448 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
3449 /* Atmel */
3450 hw->flash_vendor = 0;
3451
3452 /* Init OP table */
3453 iowrite8(flash_table[hw->flash_vendor].cmd_program,
3454 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
3455 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
3456 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
3457 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
3458 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
3459 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
3460 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
3461 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
3462 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
3463 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
3464 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
3465 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
3466 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
3467 iowrite8(flash_table[hw->flash_vendor].cmd_read,
3468 hw->hw_addr + REG_SPI_FLASH_OP_READ);
3469}
3470
3471/*
3472 * Performs basic configuration of the adapter.
3473 * hw - Struct containing variables accessed by shared code
3474 * Assumes that the controller has previously been reset and is in a
3475 * post-reset uninitialized state. Initializes multicast table,
3476 * and Calls routines to setup link
3477 * Leaves the transmit and receive units disabled and uninitialized.
3478 */
3479s32 atl1_init_hw(struct atl1_hw *hw)
3480{
3481 u32 ret_val = 0;
3482
3483 /* Zero out the Multicast HASH table */
3484 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
3485 /* clear the old settings from the multicast hash table */
3486 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
3487
3488 atl1_init_flash_opcode(hw);
3489
3490 if (!hw->phy_configured) {
3491 /* enable GPHY LinkChange Interrrupt */
3492 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
3493 if (ret_val)
3494 return ret_val;
3495 /* make PHY out of power-saving state */
3496 ret_val = atl1_phy_leave_power_saving(hw);
3497 if (ret_val)
3498 return ret_val;
3499 /* Call a subroutine to configure the link */
3500 ret_val = atl1_setup_link(hw);
3501 }
3502 return ret_val;
3503}
3504
3505/*
3506 * Detects the current speed and duplex settings of the hardware.
3507 * hw - Struct containing variables accessed by shared code
3508 * speed - Speed of the connection
3509 * duplex - Duplex setting of the connection
3510 */
3511s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
3512{
3513 struct pci_dev *pdev = hw->back->pdev;
3514 struct atl1_adapter *adapter = hw->back;
3515 s32 ret_val;
3516 u16 phy_data;
3517
3518 /* ; --- Read PHY Specific Status Register (17) */
3519 ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
3520 if (ret_val)
3521 return ret_val;
3522
3523 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
3524 return ATLX_ERR_PHY_RES;
3525
3526 switch (phy_data & MII_ATLX_PSSR_SPEED) {
3527 case MII_ATLX_PSSR_1000MBS:
3528 *speed = SPEED_1000;
3529 break;
3530 case MII_ATLX_PSSR_100MBS:
3531 *speed = SPEED_100;
3532 break;
3533 case MII_ATLX_PSSR_10MBS:
3534 *speed = SPEED_10;
3535 break;
3536 default:
3537 if (netif_msg_hw(adapter))
3538 dev_dbg(&pdev->dev, "error getting speed\n");
3539 return ATLX_ERR_PHY_SPEED;
3540 break;
3541 }
3542 if (phy_data & MII_ATLX_PSSR_DPLX)
3543 *duplex = FULL_DUPLEX;
3544 else
3545 *duplex = HALF_DUPLEX;
3546
3547 return 0;
3548}
3549
3550void atl1_set_mac_addr(struct atl1_hw *hw)
3551{
3552 u32 value;
3553 /*
3554 * 00-0B-6A-F6-00-DC
3555 * 0: 6AF600DC 1: 000B
3556 * low dword
3557 */
3558 value = (((u32) hw->mac_addr[2]) << 24) |
3559 (((u32) hw->mac_addr[3]) << 16) |
3560 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
3561 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
3562 /* high dword */
3563 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
3564 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
3565}
diff --git a/drivers/net/atlx/atl1.h b/drivers/net/atlx/atl1.h
index 6220298908ba..51893d66eae1 100644
--- a/drivers/net/atlx/atl1.h
+++ b/drivers/net/atlx/atl1.h
@@ -56,20 +56,10 @@ struct atl1_adapter;
56struct atl1_hw; 56struct atl1_hw;
57 57
58/* function prototypes needed by multiple files */ 58/* function prototypes needed by multiple files */
59s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw);
60s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data);
61s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
62s32 atl1_read_mac_addr(struct atl1_hw *hw);
63s32 atl1_init_hw(struct atl1_hw *hw);
64s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
65s32 atl1_set_speed_and_duplex(struct atl1_hw *hw, u16 speed, u16 duplex);
66u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr); 59u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
67void atl1_hash_set(struct atl1_hw *hw, u32 hash_value); 60void atl1_hash_set(struct atl1_hw *hw, u32 hash_value);
68s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data); 61s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data);
69void atl1_set_mac_addr(struct atl1_hw *hw); 62void atl1_set_mac_addr(struct atl1_hw *hw);
70s32 atl1_phy_enter_power_saving(struct atl1_hw *hw);
71s32 atl1_reset_hw(struct atl1_hw *hw);
72void atl1_check_options(struct atl1_adapter *adapter);
73static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, 63static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
74 int cmd); 64 int cmd);
75static u32 atl1_check_link(struct atl1_adapter *adapter); 65static u32 atl1_check_link(struct atl1_adapter *adapter);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 18:26:57 -0500