2 files changed, 37 insertions, 39 deletions

diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index d4ac6e9ef6db..4f9fbe268ec9 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -4865,9 +4865,15 @@ static void tg3_restore_pci_state(struct tg3 *tp)
         pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd);
 
         /* Make sure PCI-X relaxed ordering bit is clear. */
-        pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
-        val &= ~PCIX_CAPS_RELAXED_ORDERING;
-        pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
+        if (tp->pcix_cap) {
+                u16 pcix_cmd;
+
+                pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
+                                     &pcix_cmd);
+                pcix_cmd &= ~PCI_X_CMD_ERO;
+                pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
+                                      pcix_cmd);
+        }
 
         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
 
@@ -6574,16 +6580,20 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
         tw32_f(WDMAC_MODE, val);
         udelay(40);
 
-        if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
-                val = tr32(TG3PCI_X_CAPS);
+        if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
+                u16 pcix_cmd;
+
+                pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
+                                     &pcix_cmd);
                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
-                        val &= ~PCIX_CAPS_BURST_MASK;
-                        val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
+                        pcix_cmd &= ~PCI_X_CMD_MAX_READ;
+                        pcix_cmd |= PCI_X_CMD_READ_2K;
                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
-                        val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
-                        val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
+                        pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
+                        pcix_cmd |= PCI_X_CMD_READ_2K;
                 }
-                tw32(TG3PCI_X_CAPS, val);
+                pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
+                                      pcix_cmd);
         }
 
         tw32_f(RDMAC_MODE, rdmac_mode);
@@ -10712,10 +10722,20 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                                        cacheline_sz_reg);
         }
 
+        if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
+            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
+                tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
+                if (!tp->pcix_cap) {
+                        printk(KERN_ERR PFX "Cannot find PCI-X "
+                                            "capability, aborting.\n");
+                        return -EIO;
+                }
+        }
+
         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
                               &pci_state_reg);
 
-        if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
+        if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
 
                 /* If this is a 5700 BX chipset, and we are in PCI-X
@@ -10733,11 +10753,13 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                          * space registers clobbered due to this bug.
                          * So explicitly force the chip into D0 here.
                          */
-                        pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
+                        pci_read_config_dword(tp->pdev,
+                                              tp->pm_cap + PCI_PM_CTRL,
                                               &pm_reg);
                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
-                        pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
+                        pci_write_config_dword(tp->pdev,
+                                               tp->pm_cap + PCI_PM_CTRL,
                                                pm_reg);
 
                         /* Also, force SERR#/PERR# in PCI command. */
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index a6a23bbcdfee..c4f845dd1e8b 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -57,32 +57,7 @@
 #define TG3PCI_IRQ_PIN                  0x0000003d
 #define TG3PCI_MIN_GNT                  0x0000003e
 #define TG3PCI_MAX_LAT                  0x0000003f
-#define TG3PCI_X_CAPS                   0x00000040
-#define  PCIX_CAPS_RELAXED_ORDERING      0x00020000
-#define  PCIX_CAPS_SPLIT_MASK            0x00700000
-#define  PCIX_CAPS_SPLIT_SHIFT           20
-#define  PCIX_CAPS_BURST_MASK            0x000c0000
-#define  PCIX_CAPS_BURST_SHIFT           18
-#define  PCIX_CAPS_MAX_BURST_CPIOB       2
-#define TG3PCI_PM_CAP_PTR               0x00000041
-#define TG3PCI_X_COMMAND                0x00000042
-#define TG3PCI_X_STATUS                 0x00000044
-#define TG3PCI_PM_CAP_ID                0x00000048
-#define TG3PCI_VPD_CAP_PTR              0x00000049
-#define TG3PCI_PM_CAPS                  0x0000004a
-#define TG3PCI_PM_CTRL_STAT             0x0000004c
-#define TG3PCI_BR_SUPP_EXT              0x0000004e
-#define TG3PCI_PM_DATA                  0x0000004f
-#define TG3PCI_VPD_CAP_ID               0x00000050
-#define TG3PCI_MSI_CAP_PTR              0x00000051
-#define TG3PCI_VPD_ADDR_FLAG            0x00000052
-#define  VPD_ADDR_FLAG_WRITE            0x00008000
-#define TG3PCI_VPD_DATA                 0x00000054
-#define TG3PCI_MSI_CAP_ID               0x00000058
-#define TG3PCI_NXT_CAP_PTR              0x00000059
-#define TG3PCI_MSI_CTRL                 0x0000005a
-#define TG3PCI_MSI_ADDR_LOW             0x0000005c
-#define TG3PCI_MSI_ADDR_HIGH            0x00000060
+/* 0x40 --> 0x64 unused */
 #define TG3PCI_MSI_DATA                 0x00000064
 /* 0x66 --> 0x68 unused */
 #define TG3PCI_MISC_HOST_CTRL           0x00000068
@@ -2318,6 +2293,7 @@ struct tg3 {
 
         int                             pm_cap;
         int                             msi_cap;
+        int                             pcix_cap;
 
         /* PHY info */
         u32                             phy_id;