2 files changed, 44 insertions, 20 deletions

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b46442d7d66e..d8d0cda2641d 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -100,18 +100,21 @@ config GPIO_VR41XX
           Say yes here to support the NEC VR4100 series General-purpose I/O Uint
 
 config GPIO_SCH
-        tristate "Intel SCH GPIO"
+        tristate "Intel SCH/TunnelCreek GPIO"
         depends on GPIOLIB && PCI && X86
         select MFD_CORE
         select LPC_SCH
         help
-          Say yes here to support GPIO interface on Intel Poulsbo SCH.
+          Say yes here to support GPIO interface on Intel Poulsbo SCH
+          or Intel Tunnel Creek processor.
           The Intel SCH contains a total of 14 GPIO pins. Ten GPIOs are
           powered by the core power rail and are turned off during sleep
           modes (S3 and higher). The remaining four GPIOs are powered by
           the Intel SCH suspend power supply. These GPIOs remain
           active during S3. The suspend powered GPIOs can be used to wake the
           system from the Suspend-to-RAM state.
+          The Intel Tunnel Creek processor has 5 GPIOs powered by the
+          core power rail and 9 from suspend power supply.
 
           This driver can also be built as a module. If so, the module
           will be called sch-gpio.
diff --git a/drivers/gpio/sch_gpio.c b/drivers/gpio/sch_gpio.c
index 583521352c16..56060421cdff 100644
--- a/drivers/gpio/sch_gpio.c
+++ b/drivers/gpio/sch_gpio.c
@@ -25,6 +25,7 @@
 #include <linux/errno.h>
 #include <linux/acpi.h>
 #include <linux/platform_device.h>
+#include <linux/pci_ids.h>
 
 #include <linux/gpio.h>
 
@@ -187,7 +188,11 @@ static struct gpio_chip sch_gpio_resume = {
 static int __devinit sch_gpio_probe(struct platform_device *pdev)
 {
         struct resource *res;
-        int err;
+        int err, id;
+
+        id = pdev->id;
+        if (!id)
+                return -ENODEV;
 
         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
         if (!res)
@@ -198,12 +203,40 @@ static int __devinit sch_gpio_probe(struct platform_device *pdev)
 
         gpio_ba = res->start;
 
-        sch_gpio_core.base = 0;
-        sch_gpio_core.ngpio = 10;
-        sch_gpio_core.dev = &pdev->dev;
+        switch (id) {
+                case PCI_DEVICE_ID_INTEL_SCH_LPC:
+                        sch_gpio_core.base = 0;
+                        sch_gpio_core.ngpio = 10;
+
+                        sch_gpio_resume.base = 10;
+                        sch_gpio_resume.ngpio = 4;
+
+                        /*
+                         * GPIO[6:0] enabled by default
+                         * GPIO7 is configured by the CMC as SLPIOVR
+                         * Enable GPIO[9:8] core powered gpios explicitly
+                         */
+                        outb(0x3, gpio_ba + CGEN + 1);
+                        /*
+                         * SUS_GPIO[2:0] enabled by default
+                         * Enable SUS_GPIO3 resume powered gpio explicitly
+                         */
+                        outb(0x8, gpio_ba + RGEN);
+                        break;
+
+                case PCI_DEVICE_ID_INTEL_ITC_LPC:
+                        sch_gpio_core.base = 0;
+                        sch_gpio_core.ngpio = 5;
+
+                        sch_gpio_resume.base = 5;
+                        sch_gpio_resume.ngpio = 9;
+                        break;
+
+                default:
+                        return -ENODEV;
+        }
 
-        sch_gpio_resume.base = 10;
-        sch_gpio_resume.ngpio = 4;
+        sch_gpio_core.dev = &pdev->dev;
         sch_gpio_resume.dev = &pdev->dev;
 
         err = gpiochip_add(&sch_gpio_core);
@@ -214,18 +247,6 @@ static int __devinit sch_gpio_probe(struct platform_device *pdev)
         if (err < 0)
                 goto err_sch_gpio_resume;
 
-        /*
-         * GPIO[6:0] enabled by default
-         * GPIO7 is configured by the CMC as SLPIOVR
-         * Enable GPIO[9:8] core powered gpios explicitly
-         */
-        outb(0x3, gpio_ba + CGEN + 1);
-        /*
-         * SUS_GPIO[2:0] enabled by default
-         * Enable SUS_GPIO3 resume powered gpio explicitly
-         */
-        outb(0x8, gpio_ba + RGEN);
-
         return 0;
 
 err_sch_gpio_resume: