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-rw-r--r--drivers/char/hw_random/omap-rng.c2
-rw-r--r--drivers/devfreq/exynos4_bus.c230
-rw-r--r--drivers/gpio/gpio-ep93xx.c7
-rw-r--r--drivers/gpio/gpio-omap.c1106
-rw-r--r--drivers/input/touchscreen/Kconfig2
-rw-r--r--drivers/leds/Kconfig2
-rw-r--r--drivers/mmc/host/Kconfig2
-rw-r--r--drivers/mmc/host/at91_mci.c1
-rw-r--r--drivers/mtd/nand/Kconfig2
-rw-r--r--drivers/rtc/Kconfig2
-rw-r--r--drivers/rtc/rtc-sa1100.c81
-rw-r--r--drivers/spi/Kconfig2
-rw-r--r--drivers/spi/spi-s3c24xx.c2
-rw-r--r--drivers/usb/Kconfig2
-rw-r--r--drivers/usb/gadget/Kconfig8
-rw-r--r--drivers/usb/host/ohci-hcd.c2
-rw-r--r--drivers/video/Kconfig2
-rw-r--r--drivers/video/backlight/ep93xx_bl.c25
-rw-r--r--drivers/video/ep93xx-fb.c18
-rw-r--r--drivers/video/omap2/dss/dispc.c5
-rw-r--r--drivers/video/omap2/dss/dss.c3
-rw-r--r--drivers/watchdog/Kconfig2
-rw-r--r--drivers/watchdog/ep93xx_wdt.c51
23 files changed, 667 insertions, 892 deletions
diff --git a/drivers/char/hw_random/omap-rng.c b/drivers/char/hw_random/omap-rng.c
index b757fac3cd1f..a07a5caa599c 100644
--- a/drivers/char/hw_random/omap-rng.c
+++ b/drivers/char/hw_random/omap-rng.c
@@ -26,6 +26,8 @@
26 26
27#include <asm/io.h> 27#include <asm/io.h>
28 28
29#include <plat/cpu.h>
30
29#define RNG_OUT_REG 0x00 /* Output register */ 31#define RNG_OUT_REG 0x00 /* Output register */
30#define RNG_STAT_REG 0x04 /* Status register 32#define RNG_STAT_REG 0x04 /* Status register
31 [0] = STAT_BUSY */ 33 [0] = STAT_BUSY */
diff --git a/drivers/devfreq/exynos4_bus.c b/drivers/devfreq/exynos4_bus.c
index 1a361e99965a..88ddc77a9bb1 100644
--- a/drivers/devfreq/exynos4_bus.c
+++ b/drivers/devfreq/exynos4_bus.c
@@ -311,51 +311,51 @@ static int exynos4210_set_busclk(struct busfreq_data *data, struct opp *opp)
311 /* Change Divider - DMC0 */ 311 /* Change Divider - DMC0 */
312 tmp = data->dmc_divtable[index]; 312 tmp = data->dmc_divtable[index];
313 313
314 __raw_writel(tmp, S5P_CLKDIV_DMC0); 314 __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
315 315
316 do { 316 do {
317 tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0); 317 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
318 } while (tmp & 0x11111111); 318 } while (tmp & 0x11111111);
319 319
320 /* Change Divider - TOP */ 320 /* Change Divider - TOP */
321 tmp = data->top_divtable[index]; 321 tmp = data->top_divtable[index];
322 322
323 __raw_writel(tmp, S5P_CLKDIV_TOP); 323 __raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
324 324
325 do { 325 do {
326 tmp = __raw_readl(S5P_CLKDIV_STAT_TOP); 326 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
327 } while (tmp & 0x11111); 327 } while (tmp & 0x11111);
328 328
329 /* Change Divider - LEFTBUS */ 329 /* Change Divider - LEFTBUS */
330 tmp = __raw_readl(S5P_CLKDIV_LEFTBUS); 330 tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
331 331
332 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK); 332 tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
333 333
334 tmp |= ((exynos4210_clkdiv_lr_bus[index][0] << 334 tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
335 S5P_CLKDIV_BUS_GDLR_SHIFT) | 335 EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
336 (exynos4210_clkdiv_lr_bus[index][1] << 336 (exynos4210_clkdiv_lr_bus[index][1] <<
337 S5P_CLKDIV_BUS_GPLR_SHIFT)); 337 EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
338 338
339 __raw_writel(tmp, S5P_CLKDIV_LEFTBUS); 339 __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
340 340
341 do { 341 do {
342 tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS); 342 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
343 } while (tmp & 0x11); 343 } while (tmp & 0x11);
344 344
345 /* Change Divider - RIGHTBUS */ 345 /* Change Divider - RIGHTBUS */
346 tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS); 346 tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
347 347
348 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK); 348 tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
349 349
350 tmp |= ((exynos4210_clkdiv_lr_bus[index][0] << 350 tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
351 S5P_CLKDIV_BUS_GDLR_SHIFT) | 351 EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
352 (exynos4210_clkdiv_lr_bus[index][1] << 352 (exynos4210_clkdiv_lr_bus[index][1] <<
353 S5P_CLKDIV_BUS_GPLR_SHIFT)); 353 EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
354 354
355 __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS); 355 __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
356 356
357 do { 357 do {
358 tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS); 358 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
359 } while (tmp & 0x11); 359 } while (tmp & 0x11);
360 360
361 return 0; 361 return 0;
@@ -376,137 +376,137 @@ static int exynos4x12_set_busclk(struct busfreq_data *data, struct opp *opp)
376 /* Change Divider - DMC0 */ 376 /* Change Divider - DMC0 */
377 tmp = data->dmc_divtable[index]; 377 tmp = data->dmc_divtable[index];
378 378
379 __raw_writel(tmp, S5P_CLKDIV_DMC0); 379 __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
380 380
381 do { 381 do {
382 tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0); 382 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
383 } while (tmp & 0x11111111); 383 } while (tmp & 0x11111111);
384 384
385 /* Change Divider - DMC1 */ 385 /* Change Divider - DMC1 */
386 tmp = __raw_readl(S5P_CLKDIV_DMC1); 386 tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1);
387 387
388 tmp &= ~(S5P_CLKDIV_DMC1_G2D_ACP_MASK | 388 tmp &= ~(EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK |
389 S5P_CLKDIV_DMC1_C2C_MASK | 389 EXYNOS4_CLKDIV_DMC1_C2C_MASK |
390 S5P_CLKDIV_DMC1_C2CACLK_MASK); 390 EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK);
391 391
392 tmp |= ((exynos4x12_clkdiv_dmc1[index][0] << 392 tmp |= ((exynos4x12_clkdiv_dmc1[index][0] <<
393 S5P_CLKDIV_DMC1_G2D_ACP_SHIFT) | 393 EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) |
394 (exynos4x12_clkdiv_dmc1[index][1] << 394 (exynos4x12_clkdiv_dmc1[index][1] <<
395 S5P_CLKDIV_DMC1_C2C_SHIFT) | 395 EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) |
396 (exynos4x12_clkdiv_dmc1[index][2] << 396 (exynos4x12_clkdiv_dmc1[index][2] <<
397 S5P_CLKDIV_DMC1_C2CACLK_SHIFT)); 397 EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT));
398 398
399 __raw_writel(tmp, S5P_CLKDIV_DMC1); 399 __raw_writel(tmp, EXYNOS4_CLKDIV_DMC1);
400 400
401 do { 401 do {
402 tmp = __raw_readl(S5P_CLKDIV_STAT_DMC1); 402 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC1);
403 } while (tmp & 0x111111); 403 } while (tmp & 0x111111);
404 404
405 /* Change Divider - TOP */ 405 /* Change Divider - TOP */
406 tmp = __raw_readl(S5P_CLKDIV_TOP); 406 tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
407 407
408 tmp &= ~(S5P_CLKDIV_TOP_ACLK266_GPS_MASK | 408 tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK |
409 S5P_CLKDIV_TOP_ACLK100_MASK | 409 EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
410 S5P_CLKDIV_TOP_ACLK160_MASK | 410 EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
411 S5P_CLKDIV_TOP_ACLK133_MASK | 411 EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
412 S5P_CLKDIV_TOP_ONENAND_MASK); 412 EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
413 413
414 tmp |= ((exynos4x12_clkdiv_top[index][0] << 414 tmp |= ((exynos4x12_clkdiv_top[index][0] <<
415 S5P_CLKDIV_TOP_ACLK266_GPS_SHIFT) | 415 EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) |
416 (exynos4x12_clkdiv_top[index][1] << 416 (exynos4x12_clkdiv_top[index][1] <<
417 S5P_CLKDIV_TOP_ACLK100_SHIFT) | 417 EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
418 (exynos4x12_clkdiv_top[index][2] << 418 (exynos4x12_clkdiv_top[index][2] <<
419 S5P_CLKDIV_TOP_ACLK160_SHIFT) | 419 EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
420 (exynos4x12_clkdiv_top[index][3] << 420 (exynos4x12_clkdiv_top[index][3] <<
421 S5P_CLKDIV_TOP_ACLK133_SHIFT) | 421 EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
422 (exynos4x12_clkdiv_top[index][4] << 422 (exynos4x12_clkdiv_top[index][4] <<
423 S5P_CLKDIV_TOP_ONENAND_SHIFT)); 423 EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
424 424
425 __raw_writel(tmp, S5P_CLKDIV_TOP); 425 __raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
426 426
427 do { 427 do {
428 tmp = __raw_readl(S5P_CLKDIV_STAT_TOP); 428 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
429 } while (tmp & 0x11111); 429 } while (tmp & 0x11111);
430 430
431 /* Change Divider - LEFTBUS */ 431 /* Change Divider - LEFTBUS */
432 tmp = __raw_readl(S5P_CLKDIV_LEFTBUS); 432 tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
433 433
434 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK); 434 tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
435 435
436 tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] << 436 tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
437 S5P_CLKDIV_BUS_GDLR_SHIFT) | 437 EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
438 (exynos4x12_clkdiv_lr_bus[index][1] << 438 (exynos4x12_clkdiv_lr_bus[index][1] <<
439 S5P_CLKDIV_BUS_GPLR_SHIFT)); 439 EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
440 440
441 __raw_writel(tmp, S5P_CLKDIV_LEFTBUS); 441 __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
442 442
443 do { 443 do {
444 tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS); 444 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
445 } while (tmp & 0x11); 445 } while (tmp & 0x11);
446 446
447 /* Change Divider - RIGHTBUS */ 447 /* Change Divider - RIGHTBUS */
448 tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS); 448 tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
449 449
450 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK); 450 tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
451 451
452 tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] << 452 tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
453 S5P_CLKDIV_BUS_GDLR_SHIFT) | 453 EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
454 (exynos4x12_clkdiv_lr_bus[index][1] << 454 (exynos4x12_clkdiv_lr_bus[index][1] <<
455 S5P_CLKDIV_BUS_GPLR_SHIFT)); 455 EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
456 456
457 __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS); 457 __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
458 458
459 do { 459 do {
460 tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS); 460 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
461 } while (tmp & 0x11); 461 } while (tmp & 0x11);
462 462
463 /* Change Divider - MFC */ 463 /* Change Divider - MFC */
464 tmp = __raw_readl(S5P_CLKDIV_MFC); 464 tmp = __raw_readl(EXYNOS4_CLKDIV_MFC);
465 465
466 tmp &= ~(S5P_CLKDIV_MFC_MASK); 466 tmp &= ~(EXYNOS4_CLKDIV_MFC_MASK);
467 467
468 tmp |= ((exynos4x12_clkdiv_sclkip[index][0] << 468 tmp |= ((exynos4x12_clkdiv_sclkip[index][0] <<
469 S5P_CLKDIV_MFC_SHIFT)); 469 EXYNOS4_CLKDIV_MFC_SHIFT));
470 470
471 __raw_writel(tmp, S5P_CLKDIV_MFC); 471 __raw_writel(tmp, EXYNOS4_CLKDIV_MFC);
472 472
473 do { 473 do {
474 tmp = __raw_readl(S5P_CLKDIV_STAT_MFC); 474 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_MFC);
475 } while (tmp & 0x1); 475 } while (tmp & 0x1);
476 476
477 /* Change Divider - JPEG */ 477 /* Change Divider - JPEG */
478 tmp = __raw_readl(S5P_CLKDIV_CAM1); 478 tmp = __raw_readl(EXYNOS4_CLKDIV_CAM1);
479 479
480 tmp &= ~(S5P_CLKDIV_CAM1_JPEG_MASK); 480 tmp &= ~(EXYNOS4_CLKDIV_CAM1_JPEG_MASK);
481 481
482 tmp |= ((exynos4x12_clkdiv_sclkip[index][1] << 482 tmp |= ((exynos4x12_clkdiv_sclkip[index][1] <<
483 S5P_CLKDIV_CAM1_JPEG_SHIFT)); 483 EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT));
484 484
485 __raw_writel(tmp, S5P_CLKDIV_CAM1); 485 __raw_writel(tmp, EXYNOS4_CLKDIV_CAM1);
486 486
487 do { 487 do {
488 tmp = __raw_readl(S5P_CLKDIV_STAT_CAM1); 488 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1);
489 } while (tmp & 0x1); 489 } while (tmp & 0x1);
490 490
491 /* Change Divider - FIMC0~3 */ 491 /* Change Divider - FIMC0~3 */
492 tmp = __raw_readl(S5P_CLKDIV_CAM); 492 tmp = __raw_readl(EXYNOS4_CLKDIV_CAM);
493 493
494 tmp &= ~(S5P_CLKDIV_CAM_FIMC0_MASK | S5P_CLKDIV_CAM_FIMC1_MASK | 494 tmp &= ~(EXYNOS4_CLKDIV_CAM_FIMC0_MASK | EXYNOS4_CLKDIV_CAM_FIMC1_MASK |
495 S5P_CLKDIV_CAM_FIMC2_MASK | S5P_CLKDIV_CAM_FIMC3_MASK); 495 EXYNOS4_CLKDIV_CAM_FIMC2_MASK | EXYNOS4_CLKDIV_CAM_FIMC3_MASK);
496 496
497 tmp |= ((exynos4x12_clkdiv_sclkip[index][2] << 497 tmp |= ((exynos4x12_clkdiv_sclkip[index][2] <<
498 S5P_CLKDIV_CAM_FIMC0_SHIFT) | 498 EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) |
499 (exynos4x12_clkdiv_sclkip[index][2] << 499 (exynos4x12_clkdiv_sclkip[index][2] <<
500 S5P_CLKDIV_CAM_FIMC1_SHIFT) | 500 EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) |
501 (exynos4x12_clkdiv_sclkip[index][2] << 501 (exynos4x12_clkdiv_sclkip[index][2] <<
502 S5P_CLKDIV_CAM_FIMC2_SHIFT) | 502 EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) |
503 (exynos4x12_clkdiv_sclkip[index][2] << 503 (exynos4x12_clkdiv_sclkip[index][2] <<
504 S5P_CLKDIV_CAM_FIMC3_SHIFT)); 504 EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT));
505 505
506 __raw_writel(tmp, S5P_CLKDIV_CAM); 506 __raw_writel(tmp, EXYNOS4_CLKDIV_CAM);
507 507
508 do { 508 do {
509 tmp = __raw_readl(S5P_CLKDIV_STAT_CAM1); 509 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1);
510 } while (tmp & 0x1111); 510 } while (tmp & 0x1111);
511 511
512 return 0; 512 return 0;
@@ -760,55 +760,55 @@ static int exynos4210_init_tables(struct busfreq_data *data)
760 int mgrp; 760 int mgrp;
761 int i, err = 0; 761 int i, err = 0;
762 762
763 tmp = __raw_readl(S5P_CLKDIV_DMC0); 763 tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
764 for (i = LV_0; i < EX4210_LV_NUM; i++) { 764 for (i = LV_0; i < EX4210_LV_NUM; i++) {
765 tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | 765 tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
766 S5P_CLKDIV_DMC0_ACPPCLK_MASK | 766 EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
767 S5P_CLKDIV_DMC0_DPHY_MASK | 767 EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
768 S5P_CLKDIV_DMC0_DMC_MASK | 768 EXYNOS4_CLKDIV_DMC0_DMC_MASK |
769 S5P_CLKDIV_DMC0_DMCD_MASK | 769 EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
770 S5P_CLKDIV_DMC0_DMCP_MASK | 770 EXYNOS4_CLKDIV_DMC0_DMCP_MASK |
771 S5P_CLKDIV_DMC0_COPY2_MASK | 771 EXYNOS4_CLKDIV_DMC0_COPY2_MASK |
772 S5P_CLKDIV_DMC0_CORETI_MASK); 772 EXYNOS4_CLKDIV_DMC0_CORETI_MASK);
773 773
774 tmp |= ((exynos4210_clkdiv_dmc0[i][0] << 774 tmp |= ((exynos4210_clkdiv_dmc0[i][0] <<
775 S5P_CLKDIV_DMC0_ACP_SHIFT) | 775 EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
776 (exynos4210_clkdiv_dmc0[i][1] << 776 (exynos4210_clkdiv_dmc0[i][1] <<
777 S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) | 777 EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
778 (exynos4210_clkdiv_dmc0[i][2] << 778 (exynos4210_clkdiv_dmc0[i][2] <<
779 S5P_CLKDIV_DMC0_DPHY_SHIFT) | 779 EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
780 (exynos4210_clkdiv_dmc0[i][3] << 780 (exynos4210_clkdiv_dmc0[i][3] <<
781 S5P_CLKDIV_DMC0_DMC_SHIFT) | 781 EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
782 (exynos4210_clkdiv_dmc0[i][4] << 782 (exynos4210_clkdiv_dmc0[i][4] <<
783 S5P_CLKDIV_DMC0_DMCD_SHIFT) | 783 EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
784 (exynos4210_clkdiv_dmc0[i][5] << 784 (exynos4210_clkdiv_dmc0[i][5] <<
785 S5P_CLKDIV_DMC0_DMCP_SHIFT) | 785 EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) |
786 (exynos4210_clkdiv_dmc0[i][6] << 786 (exynos4210_clkdiv_dmc0[i][6] <<
787 S5P_CLKDIV_DMC0_COPY2_SHIFT) | 787 EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) |
788 (exynos4210_clkdiv_dmc0[i][7] << 788 (exynos4210_clkdiv_dmc0[i][7] <<
789 S5P_CLKDIV_DMC0_CORETI_SHIFT)); 789 EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT));
790 790
791 data->dmc_divtable[i] = tmp; 791 data->dmc_divtable[i] = tmp;
792 } 792 }
793 793
794 tmp = __raw_readl(S5P_CLKDIV_TOP); 794 tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
795 for (i = LV_0; i < EX4210_LV_NUM; i++) { 795 for (i = LV_0; i < EX4210_LV_NUM; i++) {
796 tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK | 796 tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK200_MASK |
797 S5P_CLKDIV_TOP_ACLK100_MASK | 797 EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
798 S5P_CLKDIV_TOP_ACLK160_MASK | 798 EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
799 S5P_CLKDIV_TOP_ACLK133_MASK | 799 EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
800 S5P_CLKDIV_TOP_ONENAND_MASK); 800 EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
801 801
802 tmp |= ((exynos4210_clkdiv_top[i][0] << 802 tmp |= ((exynos4210_clkdiv_top[i][0] <<
803 S5P_CLKDIV_TOP_ACLK200_SHIFT) | 803 EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) |
804 (exynos4210_clkdiv_top[i][1] << 804 (exynos4210_clkdiv_top[i][1] <<
805 S5P_CLKDIV_TOP_ACLK100_SHIFT) | 805 EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
806 (exynos4210_clkdiv_top[i][2] << 806 (exynos4210_clkdiv_top[i][2] <<
807 S5P_CLKDIV_TOP_ACLK160_SHIFT) | 807 EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
808 (exynos4210_clkdiv_top[i][3] << 808 (exynos4210_clkdiv_top[i][3] <<
809 S5P_CLKDIV_TOP_ACLK133_SHIFT) | 809 EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
810 (exynos4210_clkdiv_top[i][4] << 810 (exynos4210_clkdiv_top[i][4] <<
811 S5P_CLKDIV_TOP_ONENAND_SHIFT)); 811 EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
812 812
813 data->top_divtable[i] = tmp; 813 data->top_divtable[i] = tmp;
814 } 814 }
@@ -868,32 +868,32 @@ static int exynos4x12_init_tables(struct busfreq_data *data)
868 int ret; 868 int ret;
869 869
870 /* Enable pause function for DREX2 DVFS */ 870 /* Enable pause function for DREX2 DVFS */
871 tmp = __raw_readl(S5P_DMC_PAUSE_CTRL); 871 tmp = __raw_readl(EXYNOS4_DMC_PAUSE_CTRL);
872 tmp |= DMC_PAUSE_ENABLE; 872 tmp |= EXYNOS4_DMC_PAUSE_ENABLE;
873 __raw_writel(tmp, S5P_DMC_PAUSE_CTRL); 873 __raw_writel(tmp, EXYNOS4_DMC_PAUSE_CTRL);
874 874
875 tmp = __raw_readl(S5P_CLKDIV_DMC0); 875 tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
876 876
877 for (i = 0; i < EX4x12_LV_NUM; i++) { 877 for (i = 0; i < EX4x12_LV_NUM; i++) {
878 tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | 878 tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
879 S5P_CLKDIV_DMC0_ACPPCLK_MASK | 879 EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
880 S5P_CLKDIV_DMC0_DPHY_MASK | 880 EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
881 S5P_CLKDIV_DMC0_DMC_MASK | 881 EXYNOS4_CLKDIV_DMC0_DMC_MASK |
882 S5P_CLKDIV_DMC0_DMCD_MASK | 882 EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
883 S5P_CLKDIV_DMC0_DMCP_MASK); 883 EXYNOS4_CLKDIV_DMC0_DMCP_MASK);
884 884
885 tmp |= ((exynos4x12_clkdiv_dmc0[i][0] << 885 tmp |= ((exynos4x12_clkdiv_dmc0[i][0] <<
886 S5P_CLKDIV_DMC0_ACP_SHIFT) | 886 EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
887 (exynos4x12_clkdiv_dmc0[i][1] << 887 (exynos4x12_clkdiv_dmc0[i][1] <<
888 S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) | 888 EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
889 (exynos4x12_clkdiv_dmc0[i][2] << 889 (exynos4x12_clkdiv_dmc0[i][2] <<
890 S5P_CLKDIV_DMC0_DPHY_SHIFT) | 890 EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
891 (exynos4x12_clkdiv_dmc0[i][3] << 891 (exynos4x12_clkdiv_dmc0[i][3] <<
892 S5P_CLKDIV_DMC0_DMC_SHIFT) | 892 EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
893 (exynos4x12_clkdiv_dmc0[i][4] << 893 (exynos4x12_clkdiv_dmc0[i][4] <<
894 S5P_CLKDIV_DMC0_DMCD_SHIFT) | 894 EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
895 (exynos4x12_clkdiv_dmc0[i][5] << 895 (exynos4x12_clkdiv_dmc0[i][5] <<
896 S5P_CLKDIV_DMC0_DMCP_SHIFT)); 896 EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT));
897 897
898 data->dmc_divtable[i] = tmp; 898 data->dmc_divtable[i] = tmp;
899 } 899 }
diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c
index 1c0fc3756cb1..4ca5642e9776 100644
--- a/drivers/gpio/gpio-ep93xx.c
+++ b/drivers/gpio/gpio-ep93xx.c
@@ -378,13 +378,6 @@ static int __devinit ep93xx_gpio_probe(struct platform_device *pdev)
378 } 378 }
379 ep93xx_gpio->mmio_base = mmio; 379 ep93xx_gpio->mmio_base = mmio;
380 380
381 /* Default all ports to GPIO */
382 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
383 EP93XX_SYSCON_DEVCFG_GONK |
384 EP93XX_SYSCON_DEVCFG_EONIDE |
385 EP93XX_SYSCON_DEVCFG_GONIDE |
386 EP93XX_SYSCON_DEVCFG_HONIDE);
387
388 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) { 381 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
389 struct bgpio_chip *bgc = &ep93xx_gpio->bgc[i]; 382 struct bgpio_chip *bgc = &ep93xx_gpio->bgc[i];
390 struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i]; 383 struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 0b0562979171..f49bd6f47a50 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -21,6 +21,7 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/slab.h> 22#include <linux/slab.h>
23#include <linux/pm_runtime.h> 23#include <linux/pm_runtime.h>
24#include <linux/pm.h>
24 25
25#include <mach/hardware.h> 26#include <mach/hardware.h>
26#include <asm/irq.h> 27#include <asm/irq.h>
@@ -28,19 +29,36 @@
28#include <asm/gpio.h> 29#include <asm/gpio.h>
29#include <asm/mach/irq.h> 30#include <asm/mach/irq.h>
30 31
32#define OFF_MODE 1
33
34static LIST_HEAD(omap_gpio_list);
35
36struct gpio_regs {
37 u32 irqenable1;
38 u32 irqenable2;
39 u32 wake_en;
40 u32 ctrl;
41 u32 oe;
42 u32 leveldetect0;
43 u32 leveldetect1;
44 u32 risingdetect;
45 u32 fallingdetect;
46 u32 dataout;
47 u32 debounce;
48 u32 debounce_en;
49};
50
31struct gpio_bank { 51struct gpio_bank {
52 struct list_head node;
32 unsigned long pbase; 53 unsigned long pbase;
33 void __iomem *base; 54 void __iomem *base;
34 u16 irq; 55 u16 irq;
35 u16 virtual_irq_start; 56 u16 virtual_irq_start;
36 int method;
37 u32 suspend_wakeup; 57 u32 suspend_wakeup;
38#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
39 u32 saved_wakeup; 58 u32 saved_wakeup;
40#endif
41 u32 non_wakeup_gpios; 59 u32 non_wakeup_gpios;
42 u32 enabled_non_wakeup_gpios; 60 u32 enabled_non_wakeup_gpios;
43 61 struct gpio_regs context;
44 u32 saved_datain; 62 u32 saved_datain;
45 u32 saved_fallingdetect; 63 u32 saved_fallingdetect;
46 u32 saved_risingdetect; 64 u32 saved_risingdetect;
@@ -51,44 +69,27 @@ struct gpio_bank {
51 struct clk *dbck; 69 struct clk *dbck;
52 u32 mod_usage; 70 u32 mod_usage;
53 u32 dbck_enable_mask; 71 u32 dbck_enable_mask;
72 bool dbck_enabled;
54 struct device *dev; 73 struct device *dev;
74 bool is_mpuio;
55 bool dbck_flag; 75 bool dbck_flag;
76 bool loses_context;
56 int stride; 77 int stride;
57 u32 width; 78 u32 width;
79 int context_loss_count;
80 u16 id;
81 int power_mode;
82 bool workaround_enabled;
58 83
59 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable); 84 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
85 int (*get_context_loss_count)(struct device *dev);
60 86
61 struct omap_gpio_reg_offs *regs; 87 struct omap_gpio_reg_offs *regs;
62}; 88};
63 89
64#ifdef CONFIG_ARCH_OMAP3
65struct omap3_gpio_regs {
66 u32 irqenable1;
67 u32 irqenable2;
68 u32 wake_en;
69 u32 ctrl;
70 u32 oe;
71 u32 leveldetect0;
72 u32 leveldetect1;
73 u32 risingdetect;
74 u32 fallingdetect;
75 u32 dataout;
76};
77
78static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
79#endif
80
81/*
82 * TODO: Cleanup gpio_bank usage as it is having information
83 * related to all instances of the device
84 */
85static struct gpio_bank *gpio_bank;
86
87/* TODO: Analyze removing gpio_bank_count usage from driver code */
88int gpio_bank_count;
89
90#define GPIO_INDEX(bank, gpio) (gpio % bank->width) 90#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
91#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) 91#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
92#define GPIO_MOD_CTRL_BIT BIT(0)
92 93
93static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) 94static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
94{ 95{
@@ -102,6 +103,7 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
102 else 103 else
103 l &= ~(1 << gpio); 104 l &= ~(1 << gpio);
104 __raw_writel(l, reg); 105 __raw_writel(l, reg);
106 bank->context.oe = l;
105} 107}
106 108
107 109
@@ -132,6 +134,7 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
132 else 134 else
133 l &= ~gpio_bit; 135 l &= ~gpio_bit;
134 __raw_writel(l, reg); 136 __raw_writel(l, reg);
137 bank->context.dataout = l;
135} 138}
136 139
137static int _get_gpio_datain(struct gpio_bank *bank, int gpio) 140static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
@@ -160,6 +163,22 @@ static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
160 __raw_writel(l, base + reg); 163 __raw_writel(l, base + reg);
161} 164}
162 165
166static inline void _gpio_dbck_enable(struct gpio_bank *bank)
167{
168 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
169 clk_enable(bank->dbck);
170 bank->dbck_enabled = true;
171 }
172}
173
174static inline void _gpio_dbck_disable(struct gpio_bank *bank)
175{
176 if (bank->dbck_enable_mask && bank->dbck_enabled) {
177 clk_disable(bank->dbck);
178 bank->dbck_enabled = false;
179 }
180}
181
163/** 182/**
164 * _set_gpio_debounce - low level gpio debounce time 183 * _set_gpio_debounce - low level gpio debounce time
165 * @bank: the gpio bank we're acting upon 184 * @bank: the gpio bank we're acting upon
@@ -188,70 +207,74 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
188 207
189 l = GPIO_BIT(bank, gpio); 208 l = GPIO_BIT(bank, gpio);
190 209
210 clk_enable(bank->dbck);
191 reg = bank->base + bank->regs->debounce; 211 reg = bank->base + bank->regs->debounce;
192 __raw_writel(debounce, reg); 212 __raw_writel(debounce, reg);
193 213
194 reg = bank->base + bank->regs->debounce_en; 214 reg = bank->base + bank->regs->debounce_en;
195 val = __raw_readl(reg); 215 val = __raw_readl(reg);
196 216
197 if (debounce) { 217 if (debounce)
198 val |= l; 218 val |= l;
199 clk_enable(bank->dbck); 219 else
200 } else {
201 val &= ~l; 220 val &= ~l;
202 clk_disable(bank->dbck);
203 }
204 bank->dbck_enable_mask = val; 221 bank->dbck_enable_mask = val;
205 222
206 __raw_writel(val, reg); 223 __raw_writel(val, reg);
224 clk_disable(bank->dbck);
225 /*
226 * Enable debounce clock per module.
227 * This call is mandatory because in omap_gpio_request() when
228 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
229 * runtime callbck fails to turn on dbck because dbck_enable_mask
230 * used within _gpio_dbck_enable() is still not initialized at
231 * that point. Therefore we have to enable dbck here.
232 */
233 _gpio_dbck_enable(bank);
234 if (bank->dbck_enable_mask) {
235 bank->context.debounce = debounce;
236 bank->context.debounce_en = val;
237 }
207} 238}
208 239
209#ifdef CONFIG_ARCH_OMAP2PLUS 240static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
210static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
211 int trigger) 241 int trigger)
212{ 242{
213 void __iomem *base = bank->base; 243 void __iomem *base = bank->base;
214 u32 gpio_bit = 1 << gpio; 244 u32 gpio_bit = 1 << gpio;
215 245
216 if (cpu_is_omap44xx()) { 246 _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
217 _gpio_rmw(base, OMAP4_GPIO_LEVELDETECT0, gpio_bit, 247 trigger & IRQ_TYPE_LEVEL_LOW);
218 trigger & IRQ_TYPE_LEVEL_LOW); 248 _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
219 _gpio_rmw(base, OMAP4_GPIO_LEVELDETECT1, gpio_bit, 249 trigger & IRQ_TYPE_LEVEL_HIGH);
220 trigger & IRQ_TYPE_LEVEL_HIGH); 250 _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
221 _gpio_rmw(base, OMAP4_GPIO_RISINGDETECT, gpio_bit, 251 trigger & IRQ_TYPE_EDGE_RISING);
222 trigger & IRQ_TYPE_EDGE_RISING); 252 _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
223 _gpio_rmw(base, OMAP4_GPIO_FALLINGDETECT, gpio_bit, 253 trigger & IRQ_TYPE_EDGE_FALLING);
224 trigger & IRQ_TYPE_EDGE_FALLING); 254
225 } else { 255 bank->context.leveldetect0 =
226 _gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, 256 __raw_readl(bank->base + bank->regs->leveldetect0);
227 trigger & IRQ_TYPE_LEVEL_LOW); 257 bank->context.leveldetect1 =
228 _gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, 258 __raw_readl(bank->base + bank->regs->leveldetect1);
229 trigger & IRQ_TYPE_LEVEL_HIGH); 259 bank->context.risingdetect =
230 _gpio_rmw(base, OMAP24XX_GPIO_RISINGDETECT, gpio_bit, 260 __raw_readl(bank->base + bank->regs->risingdetect);
231 trigger & IRQ_TYPE_EDGE_RISING); 261 bank->context.fallingdetect =
232 _gpio_rmw(base, OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, 262 __raw_readl(bank->base + bank->regs->fallingdetect);
233 trigger & IRQ_TYPE_EDGE_FALLING); 263
234 }
235 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { 264 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
236 if (cpu_is_omap44xx()) { 265 _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
237 _gpio_rmw(base, OMAP4_GPIO_IRQWAKEN0, gpio_bit, 266 bank->context.wake_en =
238 trigger != 0); 267 __raw_readl(bank->base + bank->regs->wkup_en);
239 } else {
240 /*
241 * GPIO wakeup request can only be generated on edge
242 * transitions
243 */
244 if (trigger & IRQ_TYPE_EDGE_BOTH)
245 __raw_writel(1 << gpio, bank->base
246 + OMAP24XX_GPIO_SETWKUENA);
247 else
248 __raw_writel(1 << gpio, bank->base
249 + OMAP24XX_GPIO_CLEARWKUENA);
250 }
251 } 268 }
269
252 /* This part needs to be executed always for OMAP{34xx, 44xx} */ 270 /* This part needs to be executed always for OMAP{34xx, 44xx} */
253 if (cpu_is_omap34xx() || cpu_is_omap44xx() || 271 if (!bank->regs->irqctrl) {
254 (bank->non_wakeup_gpios & gpio_bit)) { 272 /* On omap24xx proceed only when valid GPIO bit is set */
273 if (bank->non_wakeup_gpios) {
274 if (!(bank->non_wakeup_gpios & gpio_bit))
275 goto exit;
276 }
277
255 /* 278 /*
256 * Log the edge gpio and manually trigger the IRQ 279 * Log the edge gpio and manually trigger the IRQ
257 * after resume if the input level changes 280 * after resume if the input level changes
@@ -264,17 +287,11 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
264 bank->enabled_non_wakeup_gpios &= ~gpio_bit; 287 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
265 } 288 }
266 289
267 if (cpu_is_omap44xx()) { 290exit:
268 bank->level_mask = 291 bank->level_mask =
269 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) | 292 __raw_readl(bank->base + bank->regs->leveldetect0) |
270 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1); 293 __raw_readl(bank->base + bank->regs->leveldetect1);
271 } else {
272 bank->level_mask =
273 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
274 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
275 }
276} 294}
277#endif
278 295
279#ifdef CONFIG_ARCH_OMAP1 296#ifdef CONFIG_ARCH_OMAP1
280/* 297/*
@@ -286,23 +303,10 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
286 void __iomem *reg = bank->base; 303 void __iomem *reg = bank->base;
287 u32 l = 0; 304 u32 l = 0;
288 305
289 switch (bank->method) { 306 if (!bank->regs->irqctrl)
290 case METHOD_MPUIO:
291 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
292 break;
293#ifdef CONFIG_ARCH_OMAP15XX
294 case METHOD_GPIO_1510:
295 reg += OMAP1510_GPIO_INT_CONTROL;
296 break;
297#endif
298#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
299 case METHOD_GPIO_7XX:
300 reg += OMAP7XX_GPIO_INT_CONTROL;
301 break;
302#endif
303 default:
304 return; 307 return;
305 } 308
309 reg += bank->regs->irqctrl;
306 310
307 l = __raw_readl(reg); 311 l = __raw_readl(reg);
308 if ((l >> gpio) & 1) 312 if ((l >> gpio) & 1)
@@ -312,31 +316,21 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
312 316
313 __raw_writel(l, reg); 317 __raw_writel(l, reg);
314} 318}
319#else
320static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
315#endif 321#endif
316 322
317static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) 323static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
318{ 324{
319 void __iomem *reg = bank->base; 325 void __iomem *reg = bank->base;
326 void __iomem *base = bank->base;
320 u32 l = 0; 327 u32 l = 0;
321 328
322 switch (bank->method) { 329 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
323#ifdef CONFIG_ARCH_OMAP1 330 set_gpio_trigger(bank, gpio, trigger);
324 case METHOD_MPUIO: 331 } else if (bank->regs->irqctrl) {
325 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride; 332 reg += bank->regs->irqctrl;
326 l = __raw_readl(reg); 333
327 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
328 bank->toggle_mask |= 1 << gpio;
329 if (trigger & IRQ_TYPE_EDGE_RISING)
330 l |= 1 << gpio;
331 else if (trigger & IRQ_TYPE_EDGE_FALLING)
332 l &= ~(1 << gpio);
333 else
334 goto bad;
335 break;
336#endif
337#ifdef CONFIG_ARCH_OMAP15XX
338 case METHOD_GPIO_1510:
339 reg += OMAP1510_GPIO_INT_CONTROL;
340 l = __raw_readl(reg); 334 l = __raw_readl(reg);
341 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 335 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
342 bank->toggle_mask |= 1 << gpio; 336 bank->toggle_mask |= 1 << gpio;
@@ -345,15 +339,15 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
345 else if (trigger & IRQ_TYPE_EDGE_FALLING) 339 else if (trigger & IRQ_TYPE_EDGE_FALLING)
346 l &= ~(1 << gpio); 340 l &= ~(1 << gpio);
347 else 341 else
348 goto bad; 342 return -EINVAL;
349 break; 343
350#endif 344 __raw_writel(l, reg);
351#ifdef CONFIG_ARCH_OMAP16XX 345 } else if (bank->regs->edgectrl1) {
352 case METHOD_GPIO_1610:
353 if (gpio & 0x08) 346 if (gpio & 0x08)
354 reg += OMAP1610_GPIO_EDGE_CTRL2; 347 reg += bank->regs->edgectrl2;
355 else 348 else
356 reg += OMAP1610_GPIO_EDGE_CTRL1; 349 reg += bank->regs->edgectrl1;
350
357 gpio &= 0x07; 351 gpio &= 0x07;
358 l = __raw_readl(reg); 352 l = __raw_readl(reg);
359 l &= ~(3 << (gpio << 1)); 353 l &= ~(3 << (gpio << 1));
@@ -361,40 +355,14 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
361 l |= 2 << (gpio << 1); 355 l |= 2 << (gpio << 1);
362 if (trigger & IRQ_TYPE_EDGE_FALLING) 356 if (trigger & IRQ_TYPE_EDGE_FALLING)
363 l |= 1 << (gpio << 1); 357 l |= 1 << (gpio << 1);
364 if (trigger) 358
365 /* Enable wake-up during idle for dynamic tick */ 359 /* Enable wake-up during idle for dynamic tick */
366 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); 360 _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
367 else 361 bank->context.wake_en =
368 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); 362 __raw_readl(bank->base + bank->regs->wkup_en);
369 break; 363 __raw_writel(l, reg);
370#endif
371#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
372 case METHOD_GPIO_7XX:
373 reg += OMAP7XX_GPIO_INT_CONTROL;
374 l = __raw_readl(reg);
375 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
376 bank->toggle_mask |= 1 << gpio;
377 if (trigger & IRQ_TYPE_EDGE_RISING)
378 l |= 1 << gpio;
379 else if (trigger & IRQ_TYPE_EDGE_FALLING)
380 l &= ~(1 << gpio);
381 else
382 goto bad;
383 break;
384#endif
385#ifdef CONFIG_ARCH_OMAP2PLUS
386 case METHOD_GPIO_24XX:
387 case METHOD_GPIO_44XX:
388 set_24xx_gpio_triggering(bank, gpio, trigger);
389 return 0;
390#endif
391 default:
392 goto bad;
393 } 364 }
394 __raw_writel(l, reg);
395 return 0; 365 return 0;
396bad:
397 return -EINVAL;
398} 366}
399 367
400static int gpio_irq_type(struct irq_data *d, unsigned type) 368static int gpio_irq_type(struct irq_data *d, unsigned type)
@@ -412,12 +380,12 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
412 if (type & ~IRQ_TYPE_SENSE_MASK) 380 if (type & ~IRQ_TYPE_SENSE_MASK)
413 return -EINVAL; 381 return -EINVAL;
414 382
415 /* OMAP1 allows only only edge triggering */ 383 bank = irq_data_get_irq_chip_data(d);
416 if (!cpu_class_is_omap2() 384
417 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) 385 if (!bank->regs->leveldetect0 &&
386 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
418 return -EINVAL; 387 return -EINVAL;
419 388
420 bank = irq_data_get_irq_chip_data(d);
421 spin_lock_irqsave(&bank->lock, flags); 389 spin_lock_irqsave(&bank->lock, flags);
422 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type); 390 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
423 spin_unlock_irqrestore(&bank->lock, flags); 391 spin_unlock_irqrestore(&bank->lock, flags);
@@ -484,6 +452,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
484 } 452 }
485 453
486 __raw_writel(l, reg); 454 __raw_writel(l, reg);
455 bank->context.irqenable1 = l;
487} 456}
488 457
489static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) 458static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
@@ -504,6 +473,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
504 } 473 }
505 474
506 __raw_writel(l, reg); 475 __raw_writel(l, reg);
476 bank->context.irqenable1 = l;
507} 477}
508 478
509static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) 479static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
@@ -567,38 +537,39 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
567 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); 537 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
568 unsigned long flags; 538 unsigned long flags;
569 539
570 spin_lock_irqsave(&bank->lock, flags); 540 /*
541 * If this is the first gpio_request for the bank,
542 * enable the bank module.
543 */
544 if (!bank->mod_usage)
545 pm_runtime_get_sync(bank->dev);
571 546
547 spin_lock_irqsave(&bank->lock, flags);
572 /* Set trigger to none. You need to enable the desired trigger with 548 /* Set trigger to none. You need to enable the desired trigger with
573 * request_irq() or set_irq_type(). 549 * request_irq() or set_irq_type().
574 */ 550 */
575 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); 551 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
576 552
577#ifdef CONFIG_ARCH_OMAP15XX 553 if (bank->regs->pinctrl) {
578 if (bank->method == METHOD_GPIO_1510) { 554 void __iomem *reg = bank->base + bank->regs->pinctrl;
579 void __iomem *reg;
580 555
581 /* Claim the pin for MPU */ 556 /* Claim the pin for MPU */
582 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
583 __raw_writel(__raw_readl(reg) | (1 << offset), reg); 557 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
584 } 558 }
585#endif 559
586 if (!cpu_class_is_omap1()) { 560 if (bank->regs->ctrl && !bank->mod_usage) {
587 if (!bank->mod_usage) { 561 void __iomem *reg = bank->base + bank->regs->ctrl;
588 void __iomem *reg = bank->base; 562 u32 ctrl;
589 u32 ctrl; 563
590 564 ctrl = __raw_readl(reg);
591 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 565 /* Module is enabled, clocks are not gated */
592 reg += OMAP24XX_GPIO_CTRL; 566 ctrl &= ~GPIO_MOD_CTRL_BIT;
593 else if (cpu_is_omap44xx()) 567 __raw_writel(ctrl, reg);
594 reg += OMAP4_GPIO_CTRL; 568 bank->context.ctrl = ctrl;
595 ctrl = __raw_readl(reg);
596 /* Module is enabled, clocks are not gated */
597 ctrl &= 0xFFFFFFFE;
598 __raw_writel(ctrl, reg);
599 }
600 bank->mod_usage |= 1 << offset;
601 } 569 }
570
571 bank->mod_usage |= 1 << offset;
572
602 spin_unlock_irqrestore(&bank->lock, flags); 573 spin_unlock_irqrestore(&bank->lock, flags);
603 574
604 return 0; 575 return 0;
@@ -607,48 +578,40 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
607static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) 578static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
608{ 579{
609 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); 580 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
581 void __iomem *base = bank->base;
610 unsigned long flags; 582 unsigned long flags;
611 583
612 spin_lock_irqsave(&bank->lock, flags); 584 spin_lock_irqsave(&bank->lock, flags);
613#ifdef CONFIG_ARCH_OMAP16XX 585
614 if (bank->method == METHOD_GPIO_1610) { 586 if (bank->regs->wkup_en) {
615 /* Disable wake-up during idle for dynamic tick */
616 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
617 __raw_writel(1 << offset, reg);
618 }
619#endif
620#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
621 if (bank->method == METHOD_GPIO_24XX) {
622 /* Disable wake-up during idle for dynamic tick */
623 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
624 __raw_writel(1 << offset, reg);
625 }
626#endif
627#ifdef CONFIG_ARCH_OMAP4
628 if (bank->method == METHOD_GPIO_44XX) {
629 /* Disable wake-up during idle for dynamic tick */ 587 /* Disable wake-up during idle for dynamic tick */
630 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0; 588 _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
631 __raw_writel(1 << offset, reg); 589 bank->context.wake_en =
590 __raw_readl(bank->base + bank->regs->wkup_en);
632 } 591 }
633#endif 592
634 if (!cpu_class_is_omap1()) { 593 bank->mod_usage &= ~(1 << offset);
635 bank->mod_usage &= ~(1 << offset); 594
636 if (!bank->mod_usage) { 595 if (bank->regs->ctrl && !bank->mod_usage) {
637 void __iomem *reg = bank->base; 596 void __iomem *reg = bank->base + bank->regs->ctrl;
638 u32 ctrl; 597 u32 ctrl;
639 598
640 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 599 ctrl = __raw_readl(reg);
641 reg += OMAP24XX_GPIO_CTRL; 600 /* Module is disabled, clocks are gated */
642 else if (cpu_is_omap44xx()) 601 ctrl |= GPIO_MOD_CTRL_BIT;
643 reg += OMAP4_GPIO_CTRL; 602 __raw_writel(ctrl, reg);
644 ctrl = __raw_readl(reg); 603 bank->context.ctrl = ctrl;
645 /* Module is disabled, clocks are gated */
646 ctrl |= 1;
647 __raw_writel(ctrl, reg);
648 }
649 } 604 }
605
650 _reset_gpio(bank, bank->chip.base + offset); 606 _reset_gpio(bank, bank->chip.base + offset);
651 spin_unlock_irqrestore(&bank->lock, flags); 607 spin_unlock_irqrestore(&bank->lock, flags);
608
609 /*
610 * If this is the last gpio to be freed in the bank,
611 * disable the bank module.
612 */
613 if (!bank->mod_usage)
614 pm_runtime_put(bank->dev);
652} 615}
653 616
654/* 617/*
@@ -674,6 +637,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
674 637
675 bank = irq_get_handler_data(irq); 638 bank = irq_get_handler_data(irq);
676 isr_reg = bank->base + bank->regs->irqstatus; 639 isr_reg = bank->base + bank->regs->irqstatus;
640 pm_runtime_get_sync(bank->dev);
677 641
678 if (WARN_ON(!isr_reg)) 642 if (WARN_ON(!isr_reg))
679 goto exit; 643 goto exit;
@@ -685,12 +649,8 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
685 enabled = _get_gpio_irqbank_mask(bank); 649 enabled = _get_gpio_irqbank_mask(bank);
686 isr_saved = isr = __raw_readl(isr_reg) & enabled; 650 isr_saved = isr = __raw_readl(isr_reg) & enabled;
687 651
688 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) 652 if (bank->level_mask)
689 isr &= 0x0000ffff;
690
691 if (cpu_class_is_omap2()) {
692 level_mask = bank->level_mask & enabled; 653 level_mask = bank->level_mask & enabled;
693 }
694 654
695 /* clear edge sensitive interrupts before handler(s) are 655 /* clear edge sensitive interrupts before handler(s) are
696 called so that we don't miss any interrupt occurred while 656 called so that we don't miss any interrupt occurred while
@@ -718,7 +678,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
718 if (!(isr & 1)) 678 if (!(isr & 1))
719 continue; 679 continue;
720 680
721#ifdef CONFIG_ARCH_OMAP1
722 /* 681 /*
723 * Some chips can't respond to both rising and falling 682 * Some chips can't respond to both rising and falling
724 * at the same time. If this irq was requested with 683 * at the same time. If this irq was requested with
@@ -728,7 +687,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
728 */ 687 */
729 if (bank->toggle_mask & (1 << gpio_index)) 688 if (bank->toggle_mask & (1 << gpio_index))
730 _toggle_gpio_edge_triggering(bank, gpio_index); 689 _toggle_gpio_edge_triggering(bank, gpio_index);
731#endif
732 690
733 generic_handle_irq(gpio_irq); 691 generic_handle_irq(gpio_irq);
734 } 692 }
@@ -740,6 +698,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
740exit: 698exit:
741 if (!unmasked) 699 if (!unmasked)
742 chained_irq_exit(chip, desc); 700 chained_irq_exit(chip, desc);
701 pm_runtime_put(bank->dev);
743} 702}
744 703
745static void gpio_irq_shutdown(struct irq_data *d) 704static void gpio_irq_shutdown(struct irq_data *d)
@@ -808,14 +767,6 @@ static struct irq_chip gpio_irq_chip = {
808 767
809/*---------------------------------------------------------------------*/ 768/*---------------------------------------------------------------------*/
810 769
811#ifdef CONFIG_ARCH_OMAP1
812
813#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
814
815#ifdef CONFIG_ARCH_OMAP16XX
816
817#include <linux/platform_device.h>
818
819static int omap_mpuio_suspend_noirq(struct device *dev) 770static int omap_mpuio_suspend_noirq(struct device *dev)
820{ 771{
821 struct platform_device *pdev = to_platform_device(dev); 772 struct platform_device *pdev = to_platform_device(dev);
@@ -869,32 +820,16 @@ static struct platform_device omap_mpuio_device = {
869 /* could list the /proc/iomem resources */ 820 /* could list the /proc/iomem resources */
870}; 821};
871 822
872static inline void mpuio_init(void) 823static inline void mpuio_init(struct gpio_bank *bank)
873{ 824{
874 struct gpio_bank *bank = &gpio_bank[0];
875 platform_set_drvdata(&omap_mpuio_device, bank); 825 platform_set_drvdata(&omap_mpuio_device, bank);
876 826
877 if (platform_driver_register(&omap_mpuio_driver) == 0) 827 if (platform_driver_register(&omap_mpuio_driver) == 0)
878 (void) platform_device_register(&omap_mpuio_device); 828 (void) platform_device_register(&omap_mpuio_device);
879} 829}
880 830
881#else
882static inline void mpuio_init(void) {}
883#endif /* 16xx */
884
885#else
886
887#define bank_is_mpuio(bank) 0
888static inline void mpuio_init(void) {}
889
890#endif
891
892/*---------------------------------------------------------------------*/ 831/*---------------------------------------------------------------------*/
893 832
894/* REVISIT these are stupid implementations! replace by ones that
895 * don't switch on METHOD_* and which mostly avoid spinlocks
896 */
897
898static int gpio_input(struct gpio_chip *chip, unsigned offset) 833static int gpio_input(struct gpio_chip *chip, unsigned offset)
899{ 834{
900 struct gpio_bank *bank; 835 struct gpio_bank *bank;
@@ -1007,78 +942,32 @@ static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1007 */ 942 */
1008static struct lock_class_key gpio_lock_class; 943static struct lock_class_key gpio_lock_class;
1009 944
1010static inline int init_gpio_info(struct platform_device *pdev) 945static void omap_gpio_mod_init(struct gpio_bank *bank)
1011{ 946{
1012 /* TODO: Analyze removing gpio_bank_count usage from driver code */ 947 void __iomem *base = bank->base;
1013 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank), 948 u32 l = 0xffffffff;
1014 GFP_KERNEL);
1015 if (!gpio_bank) {
1016 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1017 return -ENOMEM;
1018 }
1019 return 0;
1020}
1021 949
1022/* TODO: Cleanup cpu_is_* checks */ 950 if (bank->width == 16)
1023static void omap_gpio_mod_init(struct gpio_bank *bank, int id) 951 l = 0xffff;
1024{
1025 if (cpu_class_is_omap2()) {
1026 if (cpu_is_omap44xx()) {
1027 __raw_writel(0xffffffff, bank->base +
1028 OMAP4_GPIO_IRQSTATUSCLR0);
1029 __raw_writel(0x00000000, bank->base +
1030 OMAP4_GPIO_DEBOUNCENABLE);
1031 /* Initialize interface clk ungated, module enabled */
1032 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1033 } else if (cpu_is_omap34xx()) {
1034 __raw_writel(0x00000000, bank->base +
1035 OMAP24XX_GPIO_IRQENABLE1);
1036 __raw_writel(0xffffffff, bank->base +
1037 OMAP24XX_GPIO_IRQSTATUS1);
1038 __raw_writel(0x00000000, bank->base +
1039 OMAP24XX_GPIO_DEBOUNCE_EN);
1040
1041 /* Initialize interface clk ungated, module enabled */
1042 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1043 } else if (cpu_is_omap24xx()) {
1044 static const u32 non_wakeup_gpios[] = {
1045 0xe203ffc0, 0x08700040
1046 };
1047 if (id < ARRAY_SIZE(non_wakeup_gpios))
1048 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1049 }
1050 } else if (cpu_class_is_omap1()) {
1051 if (bank_is_mpuio(bank))
1052 __raw_writew(0xffff, bank->base +
1053 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1054 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1055 __raw_writew(0xffff, bank->base
1056 + OMAP1510_GPIO_INT_MASK);
1057 __raw_writew(0x0000, bank->base
1058 + OMAP1510_GPIO_INT_STATUS);
1059 }
1060 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1061 __raw_writew(0x0000, bank->base
1062 + OMAP1610_GPIO_IRQENABLE1);
1063 __raw_writew(0xffff, bank->base
1064 + OMAP1610_GPIO_IRQSTATUS1);
1065 __raw_writew(0x0014, bank->base
1066 + OMAP1610_GPIO_SYSCONFIG);
1067 952
1068 /* 953 if (bank->is_mpuio) {
1069 * Enable system clock for GPIO module. 954 __raw_writel(l, bank->base + bank->regs->irqenable);
1070 * The CAM_CLK_CTRL *is* really the right place. 955 return;
1071 */
1072 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1073 ULPD_CAM_CLK_CTRL);
1074 }
1075 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1076 __raw_writel(0xffffffff, bank->base
1077 + OMAP7XX_GPIO_INT_MASK);
1078 __raw_writel(0x00000000, bank->base
1079 + OMAP7XX_GPIO_INT_STATUS);
1080 }
1081 } 956 }
957
958 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
959 _gpio_rmw(base, bank->regs->irqstatus, l,
960 bank->regs->irqenable_inv == false);
961 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->debounce_en != 0);
962 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->ctrl != 0);
963 if (bank->regs->debounce_en)
964 _gpio_rmw(base, bank->regs->debounce_en, 0, 1);
965
966 /* Save OE default value (0xffffffff) in the context */
967 bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
968 /* Initialize interface clk ungated, module enabled */
969 if (bank->regs->ctrl)
970 _gpio_rmw(base, bank->regs->ctrl, 0, 1);
1082} 971}
1083 972
1084static __init void 973static __init void
@@ -1101,8 +990,8 @@ omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1101 ct->chip.irq_mask = irq_gc_mask_set_bit; 990 ct->chip.irq_mask = irq_gc_mask_set_bit;
1102 ct->chip.irq_unmask = irq_gc_mask_clr_bit; 991 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1103 ct->chip.irq_set_type = gpio_irq_type; 992 ct->chip.irq_set_type = gpio_irq_type;
1104 /* REVISIT: assuming only 16xx supports MPUIO wake events */ 993
1105 if (cpu_is_omap16xx()) 994 if (bank->regs->wkup_en)
1106 ct->chip.irq_set_wake = gpio_wake_enable, 995 ct->chip.irq_set_wake = gpio_wake_enable,
1107 996
1108 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; 997 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
@@ -1115,7 +1004,6 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1115 int j; 1004 int j;
1116 static int gpio; 1005 static int gpio;
1117 1006
1118 bank->mod_usage = 0;
1119 /* 1007 /*
1120 * REVISIT eventually switch from OMAP-specific gpio structs 1008 * REVISIT eventually switch from OMAP-specific gpio structs
1121 * over to the generic ones 1009 * over to the generic ones
@@ -1128,11 +1016,10 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1128 bank->chip.set_debounce = gpio_debounce; 1016 bank->chip.set_debounce = gpio_debounce;
1129 bank->chip.set = gpio_set; 1017 bank->chip.set = gpio_set;
1130 bank->chip.to_irq = gpio_2irq; 1018 bank->chip.to_irq = gpio_2irq;
1131 if (bank_is_mpuio(bank)) { 1019 if (bank->is_mpuio) {
1132 bank->chip.label = "mpuio"; 1020 bank->chip.label = "mpuio";
1133#ifdef CONFIG_ARCH_OMAP16XX 1021 if (bank->regs->wkup_en)
1134 bank->chip.dev = &omap_mpuio_device.dev; 1022 bank->chip.dev = &omap_mpuio_device.dev;
1135#endif
1136 bank->chip.base = OMAP_MPUIO(0); 1023 bank->chip.base = OMAP_MPUIO(0);
1137 } else { 1024 } else {
1138 bank->chip.label = "gpio"; 1025 bank->chip.label = "gpio";
@@ -1147,7 +1034,7 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1147 j < bank->virtual_irq_start + bank->width; j++) { 1034 j < bank->virtual_irq_start + bank->width; j++) {
1148 irq_set_lockdep_class(j, &gpio_lock_class); 1035 irq_set_lockdep_class(j, &gpio_lock_class);
1149 irq_set_chip_data(j, bank); 1036 irq_set_chip_data(j, bank);
1150 if (bank_is_mpuio(bank)) { 1037 if (bank->is_mpuio) {
1151 omap_mpuio_alloc_gc(bank, j, bank->width); 1038 omap_mpuio_alloc_gc(bank, j, bank->width);
1152 } else { 1039 } else {
1153 irq_set_chip(j, &gpio_irq_chip); 1040 irq_set_chip(j, &gpio_irq_chip);
@@ -1161,42 +1048,44 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1161 1048
1162static int __devinit omap_gpio_probe(struct platform_device *pdev) 1049static int __devinit omap_gpio_probe(struct platform_device *pdev)
1163{ 1050{
1164 static int gpio_init_done;
1165 struct omap_gpio_platform_data *pdata; 1051 struct omap_gpio_platform_data *pdata;
1166 struct resource *res; 1052 struct resource *res;
1167 int id;
1168 struct gpio_bank *bank; 1053 struct gpio_bank *bank;
1054 int ret = 0;
1169 1055
1170 if (!pdev->dev.platform_data) 1056 if (!pdev->dev.platform_data) {
1171 return -EINVAL; 1057 ret = -EINVAL;
1172 1058 goto err_exit;
1173 pdata = pdev->dev.platform_data;
1174
1175 if (!gpio_init_done) {
1176 int ret;
1177
1178 ret = init_gpio_info(pdev);
1179 if (ret)
1180 return ret;
1181 } 1059 }
1182 1060
1183 id = pdev->id; 1061 bank = kzalloc(sizeof(struct gpio_bank), GFP_KERNEL);
1184 bank = &gpio_bank[id]; 1062 if (!bank) {
1063 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1064 ret = -ENOMEM;
1065 goto err_exit;
1066 }
1185 1067
1186 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1068 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1187 if (unlikely(!res)) { 1069 if (unlikely(!res)) {
1188 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id); 1070 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n",
1189 return -ENODEV; 1071 pdev->id);
1072 ret = -ENODEV;
1073 goto err_free;
1190 } 1074 }
1191 1075
1192 bank->irq = res->start; 1076 bank->irq = res->start;
1077 bank->id = pdev->id;
1078
1079 pdata = pdev->dev.platform_data;
1193 bank->virtual_irq_start = pdata->virtual_irq_start; 1080 bank->virtual_irq_start = pdata->virtual_irq_start;
1194 bank->method = pdata->bank_type;
1195 bank->dev = &pdev->dev; 1081 bank->dev = &pdev->dev;
1196 bank->dbck_flag = pdata->dbck_flag; 1082 bank->dbck_flag = pdata->dbck_flag;
1197 bank->stride = pdata->bank_stride; 1083 bank->stride = pdata->bank_stride;
1198 bank->width = pdata->bank_width; 1084 bank->width = pdata->bank_width;
1199 1085 bank->is_mpuio = pdata->is_mpuio;
1086 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1087 bank->loses_context = pdata->loses_context;
1088 bank->get_context_loss_count = pdata->get_context_loss_count;
1200 bank->regs = pdata->regs; 1089 bank->regs = pdata->regs;
1201 1090
1202 if (bank->regs->set_dataout && bank->regs->clr_dataout) 1091 if (bank->regs->set_dataout && bank->regs->clr_dataout)
@@ -1209,369 +1098,310 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
1209 /* Static mapping, never released */ 1098 /* Static mapping, never released */
1210 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1099 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1211 if (unlikely(!res)) { 1100 if (unlikely(!res)) {
1212 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id); 1101 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n",
1213 return -ENODEV; 1102 pdev->id);
1103 ret = -ENODEV;
1104 goto err_free;
1214 } 1105 }
1215 1106
1216 bank->base = ioremap(res->start, resource_size(res)); 1107 bank->base = ioremap(res->start, resource_size(res));
1217 if (!bank->base) { 1108 if (!bank->base) {
1218 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id); 1109 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n",
1219 return -ENOMEM; 1110 pdev->id);
1111 ret = -ENOMEM;
1112 goto err_free;
1220 } 1113 }
1221 1114
1115 platform_set_drvdata(pdev, bank);
1116
1222 pm_runtime_enable(bank->dev); 1117 pm_runtime_enable(bank->dev);
1118 pm_runtime_irq_safe(bank->dev);
1223 pm_runtime_get_sync(bank->dev); 1119 pm_runtime_get_sync(bank->dev);
1224 1120
1225 omap_gpio_mod_init(bank, id); 1121 if (bank->is_mpuio)
1122 mpuio_init(bank);
1123
1124 omap_gpio_mod_init(bank);
1226 omap_gpio_chip_init(bank); 1125 omap_gpio_chip_init(bank);
1227 omap_gpio_show_rev(bank); 1126 omap_gpio_show_rev(bank);
1228 1127
1229 if (!gpio_init_done) 1128 pm_runtime_put(bank->dev);
1230 gpio_init_done = 1;
1231 1129
1232 return 0; 1130 list_add_tail(&bank->node, &omap_gpio_list);
1131
1132 return ret;
1133
1134err_free:
1135 kfree(bank);
1136err_exit:
1137 return ret;
1233} 1138}
1234 1139
1235#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) 1140#ifdef CONFIG_ARCH_OMAP2PLUS
1236static int omap_gpio_suspend(void) 1141
1142#if defined(CONFIG_PM_SLEEP)
1143static int omap_gpio_suspend(struct device *dev)
1237{ 1144{
1238 int i; 1145 struct platform_device *pdev = to_platform_device(dev);
1146 struct gpio_bank *bank = platform_get_drvdata(pdev);
1147 void __iomem *base = bank->base;
1148 void __iomem *wakeup_enable;
1149 unsigned long flags;
1239 1150
1240 if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) 1151 if (!bank->mod_usage || !bank->loses_context)
1241 return 0; 1152 return 0;
1242 1153
1243 for (i = 0; i < gpio_bank_count; i++) { 1154 if (!bank->regs->wkup_en || !bank->suspend_wakeup)
1244 struct gpio_bank *bank = &gpio_bank[i]; 1155 return 0;
1245 void __iomem *wake_status;
1246 void __iomem *wake_clear;
1247 void __iomem *wake_set;
1248 unsigned long flags;
1249
1250 switch (bank->method) {
1251#ifdef CONFIG_ARCH_OMAP16XX
1252 case METHOD_GPIO_1610:
1253 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1254 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1255 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1256 break;
1257#endif
1258#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1259 case METHOD_GPIO_24XX:
1260 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1261 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1262 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1263 break;
1264#endif
1265#ifdef CONFIG_ARCH_OMAP4
1266 case METHOD_GPIO_44XX:
1267 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1268 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1269 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1270 break;
1271#endif
1272 default:
1273 continue;
1274 }
1275 1156
1276 spin_lock_irqsave(&bank->lock, flags); 1157 wakeup_enable = bank->base + bank->regs->wkup_en;
1277 bank->saved_wakeup = __raw_readl(wake_status); 1158
1278 __raw_writel(0xffffffff, wake_clear); 1159 spin_lock_irqsave(&bank->lock, flags);
1279 __raw_writel(bank->suspend_wakeup, wake_set); 1160 bank->saved_wakeup = __raw_readl(wakeup_enable);
1280 spin_unlock_irqrestore(&bank->lock, flags); 1161 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1281 } 1162 _gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1);
1163 spin_unlock_irqrestore(&bank->lock, flags);
1282 1164
1283 return 0; 1165 return 0;
1284} 1166}
1285 1167
1286static void omap_gpio_resume(void) 1168static int omap_gpio_resume(struct device *dev)
1287{ 1169{
1288 int i; 1170 struct platform_device *pdev = to_platform_device(dev);
1171 struct gpio_bank *bank = platform_get_drvdata(pdev);
1172 void __iomem *base = bank->base;
1173 unsigned long flags;
1289 1174
1290 if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) 1175 if (!bank->mod_usage || !bank->loses_context)
1291 return; 1176 return 0;
1292 1177
1293 for (i = 0; i < gpio_bank_count; i++) { 1178 if (!bank->regs->wkup_en || !bank->saved_wakeup)
1294 struct gpio_bank *bank = &gpio_bank[i]; 1179 return 0;
1295 void __iomem *wake_clear;
1296 void __iomem *wake_set;
1297 unsigned long flags;
1298
1299 switch (bank->method) {
1300#ifdef CONFIG_ARCH_OMAP16XX
1301 case METHOD_GPIO_1610:
1302 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1303 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1304 break;
1305#endif
1306#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1307 case METHOD_GPIO_24XX:
1308 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1309 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1310 break;
1311#endif
1312#ifdef CONFIG_ARCH_OMAP4
1313 case METHOD_GPIO_44XX:
1314 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1315 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1316 break;
1317#endif
1318 default:
1319 continue;
1320 }
1321 1180
1322 spin_lock_irqsave(&bank->lock, flags); 1181 spin_lock_irqsave(&bank->lock, flags);
1323 __raw_writel(0xffffffff, wake_clear); 1182 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1324 __raw_writel(bank->saved_wakeup, wake_set); 1183 _gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1);
1325 spin_unlock_irqrestore(&bank->lock, flags); 1184 spin_unlock_irqrestore(&bank->lock, flags);
1326 }
1327}
1328 1185
1329static struct syscore_ops omap_gpio_syscore_ops = { 1186 return 0;
1330 .suspend = omap_gpio_suspend, 1187}
1331 .resume = omap_gpio_resume, 1188#endif /* CONFIG_PM_SLEEP */
1332};
1333 1189
1334#endif 1190#if defined(CONFIG_PM_RUNTIME)
1191static void omap_gpio_restore_context(struct gpio_bank *bank);
1335 1192
1336#ifdef CONFIG_ARCH_OMAP2PLUS 1193static int omap_gpio_runtime_suspend(struct device *dev)
1194{
1195 struct platform_device *pdev = to_platform_device(dev);
1196 struct gpio_bank *bank = platform_get_drvdata(pdev);
1197 u32 l1 = 0, l2 = 0;
1198 unsigned long flags;
1337 1199
1338static int workaround_enabled; 1200 spin_lock_irqsave(&bank->lock, flags);
1201 if (bank->power_mode != OFF_MODE) {
1202 bank->power_mode = 0;
1203 goto update_gpio_context_count;
1204 }
1205 /*
1206 * If going to OFF, remove triggering for all
1207 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1208 * generated. See OMAP2420 Errata item 1.101.
1209 */
1210 if (!(bank->enabled_non_wakeup_gpios))
1211 goto update_gpio_context_count;
1339 1212
1340void omap2_gpio_prepare_for_idle(int off_mode) 1213 bank->saved_datain = __raw_readl(bank->base +
1341{ 1214 bank->regs->datain);
1342 int i, c = 0; 1215 l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
1343 int min = 0; 1216 l2 = __raw_readl(bank->base + bank->regs->risingdetect);
1344 1217
1345 if (cpu_is_omap34xx()) 1218 bank->saved_fallingdetect = l1;
1346 min = 1; 1219 bank->saved_risingdetect = l2;
1220 l1 &= ~bank->enabled_non_wakeup_gpios;
1221 l2 &= ~bank->enabled_non_wakeup_gpios;
1347 1222
1348 for (i = min; i < gpio_bank_count; i++) { 1223 __raw_writel(l1, bank->base + bank->regs->fallingdetect);
1349 struct gpio_bank *bank = &gpio_bank[i]; 1224 __raw_writel(l2, bank->base + bank->regs->risingdetect);
1350 u32 l1 = 0, l2 = 0;
1351 int j;
1352 1225
1353 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) 1226 bank->workaround_enabled = true;
1354 clk_disable(bank->dbck);
1355 1227
1356 if (!off_mode) 1228update_gpio_context_count:
1357 continue; 1229 if (bank->get_context_loss_count)
1230 bank->context_loss_count =
1231 bank->get_context_loss_count(bank->dev);
1358 1232
1359 /* If going to OFF, remove triggering for all 1233 _gpio_dbck_disable(bank);
1360 * non-wakeup GPIOs. Otherwise spurious IRQs will be 1234 spin_unlock_irqrestore(&bank->lock, flags);
1361 * generated. See OMAP2420 Errata item 1.101. */
1362 if (!(bank->enabled_non_wakeup_gpios))
1363 continue;
1364 1235
1365 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 1236 return 0;
1366 bank->saved_datain = __raw_readl(bank->base + 1237}
1367 OMAP24XX_GPIO_DATAIN);
1368 l1 = __raw_readl(bank->base +
1369 OMAP24XX_GPIO_FALLINGDETECT);
1370 l2 = __raw_readl(bank->base +
1371 OMAP24XX_GPIO_RISINGDETECT);
1372 }
1373 1238
1374 if (cpu_is_omap44xx()) { 1239static int omap_gpio_runtime_resume(struct device *dev)
1375 bank->saved_datain = __raw_readl(bank->base + 1240{
1376 OMAP4_GPIO_DATAIN); 1241 struct platform_device *pdev = to_platform_device(dev);
1377 l1 = __raw_readl(bank->base + 1242 struct gpio_bank *bank = platform_get_drvdata(pdev);
1378 OMAP4_GPIO_FALLINGDETECT); 1243 int context_lost_cnt_after;
1379 l2 = __raw_readl(bank->base + 1244 u32 l = 0, gen, gen0, gen1;
1380 OMAP4_GPIO_RISINGDETECT); 1245 unsigned long flags;
1381 }
1382 1246
1383 bank->saved_fallingdetect = l1; 1247 spin_lock_irqsave(&bank->lock, flags);
1384 bank->saved_risingdetect = l2; 1248 _gpio_dbck_enable(bank);
1385 l1 &= ~bank->enabled_non_wakeup_gpios; 1249 if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) {
1386 l2 &= ~bank->enabled_non_wakeup_gpios; 1250 spin_unlock_irqrestore(&bank->lock, flags);
1251 return 0;
1252 }
1387 1253
1388 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 1254 if (bank->get_context_loss_count) {
1389 __raw_writel(l1, bank->base + 1255 context_lost_cnt_after =
1390 OMAP24XX_GPIO_FALLINGDETECT); 1256 bank->get_context_loss_count(bank->dev);
1391 __raw_writel(l2, bank->base + 1257 if (context_lost_cnt_after != bank->context_loss_count ||
1392 OMAP24XX_GPIO_RISINGDETECT); 1258 !context_lost_cnt_after) {
1259 omap_gpio_restore_context(bank);
1260 } else {
1261 spin_unlock_irqrestore(&bank->lock, flags);
1262 return 0;
1393 } 1263 }
1264 }
1394 1265
1395 if (cpu_is_omap44xx()) { 1266 __raw_writel(bank->saved_fallingdetect,
1396 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); 1267 bank->base + bank->regs->fallingdetect);
1397 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); 1268 __raw_writel(bank->saved_risingdetect,
1398 } 1269 bank->base + bank->regs->risingdetect);
1270 l = __raw_readl(bank->base + bank->regs->datain);
1399 1271
1400 c++; 1272 /*
1401 } 1273 * Check if any of the non-wakeup interrupt GPIOs have changed
1402 if (!c) { 1274 * state. If so, generate an IRQ by software. This is
1403 workaround_enabled = 0; 1275 * horribly racy, but it's the best we can do to work around
1404 return; 1276 * this silicon bug.
1405 } 1277 */
1406 workaround_enabled = 1; 1278 l ^= bank->saved_datain;
1407} 1279 l &= bank->enabled_non_wakeup_gpios;
1408 1280
1409void omap2_gpio_resume_after_idle(void) 1281 /*
1410{ 1282 * No need to generate IRQs for the rising edge for gpio IRQs
1411 int i; 1283 * configured with falling edge only; and vice versa.
1412 int min = 0; 1284 */
1285 gen0 = l & bank->saved_fallingdetect;
1286 gen0 &= bank->saved_datain;
1413 1287
1414 if (cpu_is_omap34xx()) 1288 gen1 = l & bank->saved_risingdetect;
1415 min = 1; 1289 gen1 &= ~(bank->saved_datain);
1416 for (i = min; i < gpio_bank_count; i++) {
1417 struct gpio_bank *bank = &gpio_bank[i];
1418 u32 l = 0, gen, gen0, gen1;
1419 int j;
1420 1290
1421 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) 1291 /* FIXME: Consider GPIO IRQs with level detections properly! */
1422 clk_enable(bank->dbck); 1292 gen = l & (~(bank->saved_fallingdetect) & ~(bank->saved_risingdetect));
1293 /* Consider all GPIO IRQs needed to be updated */
1294 gen |= gen0 | gen1;
1423 1295
1424 if (!workaround_enabled) 1296 if (gen) {
1425 continue; 1297 u32 old0, old1;
1426 1298
1427 if (!(bank->enabled_non_wakeup_gpios)) 1299 old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
1428 continue; 1300 old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
1429 1301
1430 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 1302 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1431 __raw_writel(bank->saved_fallingdetect, 1303 __raw_writel(old0 | gen, bank->base +
1432 bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1304 bank->regs->leveldetect0);
1433 __raw_writel(bank->saved_risingdetect, 1305 __raw_writel(old1 | gen, bank->base +
1434 bank->base + OMAP24XX_GPIO_RISINGDETECT); 1306 bank->regs->leveldetect1);
1435 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1436 } 1307 }
1437 1308
1438 if (cpu_is_omap44xx()) { 1309 if (cpu_is_omap44xx()) {
1439 __raw_writel(bank->saved_fallingdetect, 1310 __raw_writel(old0 | l, bank->base +
1440 bank->base + OMAP4_GPIO_FALLINGDETECT); 1311 bank->regs->leveldetect0);
1441 __raw_writel(bank->saved_risingdetect, 1312 __raw_writel(old1 | l, bank->base +
1442 bank->base + OMAP4_GPIO_RISINGDETECT); 1313 bank->regs->leveldetect1);
1443 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1444 }
1445
1446 /* Check if any of the non-wakeup interrupt GPIOs have changed
1447 * state. If so, generate an IRQ by software. This is
1448 * horribly racy, but it's the best we can do to work around
1449 * this silicon bug. */
1450 l ^= bank->saved_datain;
1451 l &= bank->enabled_non_wakeup_gpios;
1452
1453 /*
1454 * No need to generate IRQs for the rising edge for gpio IRQs
1455 * configured with falling edge only; and vice versa.
1456 */
1457 gen0 = l & bank->saved_fallingdetect;
1458 gen0 &= bank->saved_datain;
1459
1460 gen1 = l & bank->saved_risingdetect;
1461 gen1 &= ~(bank->saved_datain);
1462
1463 /* FIXME: Consider GPIO IRQs with level detections properly! */
1464 gen = l & (~(bank->saved_fallingdetect) &
1465 ~(bank->saved_risingdetect));
1466 /* Consider all GPIO IRQs needed to be updated */
1467 gen |= gen0 | gen1;
1468
1469 if (gen) {
1470 u32 old0, old1;
1471
1472 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1473 old0 = __raw_readl(bank->base +
1474 OMAP24XX_GPIO_LEVELDETECT0);
1475 old1 = __raw_readl(bank->base +
1476 OMAP24XX_GPIO_LEVELDETECT1);
1477 __raw_writel(old0 | gen, bank->base +
1478 OMAP24XX_GPIO_LEVELDETECT0);
1479 __raw_writel(old1 | gen, bank->base +
1480 OMAP24XX_GPIO_LEVELDETECT1);
1481 __raw_writel(old0, bank->base +
1482 OMAP24XX_GPIO_LEVELDETECT0);
1483 __raw_writel(old1, bank->base +
1484 OMAP24XX_GPIO_LEVELDETECT1);
1485 }
1486
1487 if (cpu_is_omap44xx()) {
1488 old0 = __raw_readl(bank->base +
1489 OMAP4_GPIO_LEVELDETECT0);
1490 old1 = __raw_readl(bank->base +
1491 OMAP4_GPIO_LEVELDETECT1);
1492 __raw_writel(old0 | l, bank->base +
1493 OMAP4_GPIO_LEVELDETECT0);
1494 __raw_writel(old1 | l, bank->base +
1495 OMAP4_GPIO_LEVELDETECT1);
1496 __raw_writel(old0, bank->base +
1497 OMAP4_GPIO_LEVELDETECT0);
1498 __raw_writel(old1, bank->base +
1499 OMAP4_GPIO_LEVELDETECT1);
1500 }
1501 } 1314 }
1315 __raw_writel(old0, bank->base + bank->regs->leveldetect0);
1316 __raw_writel(old1, bank->base + bank->regs->leveldetect1);
1502 } 1317 }
1503 1318
1319 bank->workaround_enabled = false;
1320 spin_unlock_irqrestore(&bank->lock, flags);
1321
1322 return 0;
1504} 1323}
1324#endif /* CONFIG_PM_RUNTIME */
1505 1325
1506#endif 1326void omap2_gpio_prepare_for_idle(int pwr_mode)
1327{
1328 struct gpio_bank *bank;
1329
1330 list_for_each_entry(bank, &omap_gpio_list, node) {
1331 if (!bank->mod_usage || !bank->loses_context)
1332 continue;
1333
1334 bank->power_mode = pwr_mode;
1335
1336 pm_runtime_put_sync_suspend(bank->dev);
1337 }
1338}
1507 1339
1508#ifdef CONFIG_ARCH_OMAP3 1340void omap2_gpio_resume_after_idle(void)
1509/* save the registers of bank 2-6 */
1510void omap_gpio_save_context(void)
1511{ 1341{
1512 int i; 1342 struct gpio_bank *bank;
1513 1343
1514 /* saving banks from 2-6 only since GPIO1 is in WKUP */ 1344 list_for_each_entry(bank, &omap_gpio_list, node) {
1515 for (i = 1; i < gpio_bank_count; i++) { 1345 if (!bank->mod_usage || !bank->loses_context)
1516 struct gpio_bank *bank = &gpio_bank[i]; 1346 continue;
1517 gpio_context[i].irqenable1 = 1347
1518 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); 1348 pm_runtime_get_sync(bank->dev);
1519 gpio_context[i].irqenable2 =
1520 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1521 gpio_context[i].wake_en =
1522 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1523 gpio_context[i].ctrl =
1524 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1525 gpio_context[i].oe =
1526 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1527 gpio_context[i].leveldetect0 =
1528 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1529 gpio_context[i].leveldetect1 =
1530 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1531 gpio_context[i].risingdetect =
1532 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1533 gpio_context[i].fallingdetect =
1534 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1535 gpio_context[i].dataout =
1536 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
1537 } 1349 }
1538} 1350}
1539 1351
1540/* restore the required registers of bank 2-6 */ 1352#if defined(CONFIG_PM_RUNTIME)
1541void omap_gpio_restore_context(void) 1353static void omap_gpio_restore_context(struct gpio_bank *bank)
1542{ 1354{
1543 int i; 1355 __raw_writel(bank->context.wake_en,
1544 1356 bank->base + bank->regs->wkup_en);
1545 for (i = 1; i < gpio_bank_count; i++) { 1357 __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
1546 struct gpio_bank *bank = &gpio_bank[i]; 1358 __raw_writel(bank->context.leveldetect0,
1547 __raw_writel(gpio_context[i].irqenable1, 1359 bank->base + bank->regs->leveldetect0);
1548 bank->base + OMAP24XX_GPIO_IRQENABLE1); 1360 __raw_writel(bank->context.leveldetect1,
1549 __raw_writel(gpio_context[i].irqenable2, 1361 bank->base + bank->regs->leveldetect1);
1550 bank->base + OMAP24XX_GPIO_IRQENABLE2); 1362 __raw_writel(bank->context.risingdetect,
1551 __raw_writel(gpio_context[i].wake_en, 1363 bank->base + bank->regs->risingdetect);
1552 bank->base + OMAP24XX_GPIO_WAKE_EN); 1364 __raw_writel(bank->context.fallingdetect,
1553 __raw_writel(gpio_context[i].ctrl, 1365 bank->base + bank->regs->fallingdetect);
1554 bank->base + OMAP24XX_GPIO_CTRL); 1366 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1555 __raw_writel(gpio_context[i].oe, 1367 __raw_writel(bank->context.dataout,
1556 bank->base + OMAP24XX_GPIO_OE); 1368 bank->base + bank->regs->set_dataout);
1557 __raw_writel(gpio_context[i].leveldetect0, 1369 else
1558 bank->base + OMAP24XX_GPIO_LEVELDETECT0); 1370 __raw_writel(bank->context.dataout,
1559 __raw_writel(gpio_context[i].leveldetect1, 1371 bank->base + bank->regs->dataout);
1560 bank->base + OMAP24XX_GPIO_LEVELDETECT1); 1372 __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
1561 __raw_writel(gpio_context[i].risingdetect, 1373
1562 bank->base + OMAP24XX_GPIO_RISINGDETECT); 1374 if (bank->dbck_enable_mask) {
1563 __raw_writel(gpio_context[i].fallingdetect, 1375 __raw_writel(bank->context.debounce, bank->base +
1564 bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1376 bank->regs->debounce);
1565 __raw_writel(gpio_context[i].dataout, 1377 __raw_writel(bank->context.debounce_en,
1566 bank->base + OMAP24XX_GPIO_DATAOUT); 1378 bank->base + bank->regs->debounce_en);
1567 } 1379 }
1380
1381 __raw_writel(bank->context.irqenable1,
1382 bank->base + bank->regs->irqenable);
1383 __raw_writel(bank->context.irqenable2,
1384 bank->base + bank->regs->irqenable2);
1568} 1385}
1386#endif /* CONFIG_PM_RUNTIME */
1387#else
1388#define omap_gpio_suspend NULL
1389#define omap_gpio_resume NULL
1390#define omap_gpio_runtime_suspend NULL
1391#define omap_gpio_runtime_resume NULL
1569#endif 1392#endif
1570 1393
1394static const struct dev_pm_ops gpio_pm_ops = {
1395 SET_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
1396 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1397 NULL)
1398};
1399
1571static struct platform_driver omap_gpio_driver = { 1400static struct platform_driver omap_gpio_driver = {
1572 .probe = omap_gpio_probe, 1401 .probe = omap_gpio_probe,
1573 .driver = { 1402 .driver = {
1574 .name = "omap_gpio", 1403 .name = "omap_gpio",
1404 .pm = &gpio_pm_ops,
1575 }, 1405 },
1576}; 1406};
1577 1407
@@ -1585,17 +1415,3 @@ static int __init omap_gpio_drv_reg(void)
1585 return platform_driver_register(&omap_gpio_driver); 1415 return platform_driver_register(&omap_gpio_driver);
1586} 1416}
1587postcore_initcall(omap_gpio_drv_reg); 1417postcore_initcall(omap_gpio_drv_reg);
1588
1589static int __init omap_gpio_sysinit(void)
1590{
1591 mpuio_init();
1592
1593#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1594 if (cpu_is_omap16xx() || cpu_class_is_omap2())
1595 register_syscore_ops(&omap_gpio_syscore_ops);
1596#endif
1597
1598 return 0;
1599}
1600
1601arch_initcall(omap_gpio_sysinit);
diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
index 97b31a0e0525..2a2141915aa0 100644
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -260,7 +260,7 @@ config TOUCHSCREEN_ILI210X
260 260
261config TOUCHSCREEN_S3C2410 261config TOUCHSCREEN_S3C2410
262 tristate "Samsung S3C2410/generic touchscreen input driver" 262 tristate "Samsung S3C2410/generic touchscreen input driver"
263 depends on ARCH_S3C2410 || SAMSUNG_DEV_TS 263 depends on ARCH_S3C24XX || SAMSUNG_DEV_TS
264 select S3C_ADC 264 select S3C_ADC
265 help 265 help
266 Say Y here if you have the s3c2410 touchscreen. 266 Say Y here if you have the s3c2410 touchscreen.
diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index 589ba02d65a2..2cdcf8c2ed49 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -69,7 +69,7 @@ config LEDS_MIKROTIK_RB532
69config LEDS_S3C24XX 69config LEDS_S3C24XX
70 tristate "LED Support for Samsung S3C24XX GPIO LEDs" 70 tristate "LED Support for Samsung S3C24XX GPIO LEDs"
71 depends on LEDS_CLASS 71 depends on LEDS_CLASS
72 depends on ARCH_S3C2410 72 depends on ARCH_S3C24XX
73 help 73 help
74 This option enables support for LEDs connected to GPIO lines 74 This option enables support for LEDs connected to GPIO lines
75 on Samsung S3C24XX series CPUs, such as the S3C2410 and S3C2440. 75 on Samsung S3C24XX series CPUs, such as the S3C2410 and S3C2440.
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 00fcbed1afd2..ecbee9bf87b2 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -395,7 +395,7 @@ config MMC_SPI
395 395
396config MMC_S3C 396config MMC_S3C
397 tristate "Samsung S3C SD/MMC Card Interface support" 397 tristate "Samsung S3C SD/MMC Card Interface support"
398 depends on ARCH_S3C2410 398 depends on ARCH_S3C24XX
399 help 399 help
400 This selects a driver for the MCI interface found in 400 This selects a driver for the MCI interface found in
401 Samsung's S3C2410, S3C2412, S3C2440, S3C2442 CPUs. 401 Samsung's S3C2410, S3C2412, S3C2440, S3C2442 CPUs.
diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c
index 947faa5d2ce4..efdb81d21c44 100644
--- a/drivers/mmc/host/at91_mci.c
+++ b/drivers/mmc/host/at91_mci.c
@@ -86,7 +86,6 @@ static inline int at91mci_is_mci1rev2xx(void)
86{ 86{
87 return ( cpu_is_at91sam9260() 87 return ( cpu_is_at91sam9260()
88 || cpu_is_at91sam9263() 88 || cpu_is_at91sam9263()
89 || cpu_is_at91cap9()
90 || cpu_is_at91sam9rl() 89 || cpu_is_at91sam9rl()
91 || cpu_is_at91sam9g10() 90 || cpu_is_at91sam9g10()
92 || cpu_is_at91sam9g20() 91 || cpu_is_at91sam9g20()
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 3b1d6da874e0..3d8d2d83995f 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -187,7 +187,7 @@ config MTD_NAND_PPCHAMELEONEVB
187 187
188config MTD_NAND_S3C2410 188config MTD_NAND_S3C2410
189 tristate "NAND Flash support for Samsung S3C SoCs" 189 tristate "NAND Flash support for Samsung S3C SoCs"
190 depends on ARCH_S3C2410 || ARCH_S3C64XX 190 depends on ARCH_S3C24XX || ARCH_S3C64XX
191 help 191 help
192 This enables the NAND flash controller on the S3C24xx and S3C64xx 192 This enables the NAND flash controller on the S3C24xx and S3C64xx
193 SoCs 193 SoCs
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 4f9fb25f945b..4768a9d28375 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -755,7 +755,7 @@ config HAVE_S3C_RTC
755 755
756config RTC_DRV_S3C 756config RTC_DRV_S3C
757 tristate "Samsung S3C series SoC RTC" 757 tristate "Samsung S3C series SoC RTC"
758 depends on ARCH_S3C2410 || ARCH_S3C64XX || HAVE_S3C_RTC 758 depends on ARCH_S3C64XX || HAVE_S3C_RTC
759 help 759 help
760 RTC (Realtime Clock) driver for the clock inbuilt into the 760 RTC (Realtime Clock) driver for the clock inbuilt into the
761 Samsung S3C24XX series of SoCs. This can provide periodic 761 Samsung S3C24XX series of SoCs. This can provide periodic
diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c
index fb758db9d0f4..44cd81c72ea1 100644
--- a/drivers/rtc/rtc-sa1100.c
+++ b/drivers/rtc/rtc-sa1100.c
@@ -42,67 +42,8 @@
42#define RTC_DEF_TRIM 0 42#define RTC_DEF_TRIM 0
43 43
44static const unsigned long RTC_FREQ = 1024; 44static const unsigned long RTC_FREQ = 1024;
45static struct rtc_time rtc_alarm;
46static DEFINE_SPINLOCK(sa1100_rtc_lock); 45static DEFINE_SPINLOCK(sa1100_rtc_lock);
47 46
48static inline int rtc_periodic_alarm(struct rtc_time *tm)
49{
50 return (tm->tm_year == -1) ||
51 ((unsigned)tm->tm_mon >= 12) ||
52 ((unsigned)(tm->tm_mday - 1) >= 31) ||
53 ((unsigned)tm->tm_hour > 23) ||
54 ((unsigned)tm->tm_min > 59) ||
55 ((unsigned)tm->tm_sec > 59);
56}
57
58/*
59 * Calculate the next alarm time given the requested alarm time mask
60 * and the current time.
61 */
62static void rtc_next_alarm_time(struct rtc_time *next, struct rtc_time *now,
63 struct rtc_time *alrm)
64{
65 unsigned long next_time;
66 unsigned long now_time;
67
68 next->tm_year = now->tm_year;
69 next->tm_mon = now->tm_mon;
70 next->tm_mday = now->tm_mday;
71 next->tm_hour = alrm->tm_hour;
72 next->tm_min = alrm->tm_min;
73 next->tm_sec = alrm->tm_sec;
74
75 rtc_tm_to_time(now, &now_time);
76 rtc_tm_to_time(next, &next_time);
77
78 if (next_time < now_time) {
79 /* Advance one day */
80 next_time += 60 * 60 * 24;
81 rtc_time_to_tm(next_time, next);
82 }
83}
84
85static int rtc_update_alarm(struct rtc_time *alrm)
86{
87 struct rtc_time alarm_tm, now_tm;
88 unsigned long now, time;
89 int ret;
90
91 do {
92 now = RCNR;
93 rtc_time_to_tm(now, &now_tm);
94 rtc_next_alarm_time(&alarm_tm, &now_tm, alrm);
95 ret = rtc_tm_to_time(&alarm_tm, &time);
96 if (ret != 0)
97 break;
98
99 RTSR = RTSR & (RTSR_HZE|RTSR_ALE|RTSR_AL);
100 RTAR = time;
101 } while (now != RCNR);
102
103 return ret;
104}
105
106static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id) 47static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id)
107{ 48{
108 struct platform_device *pdev = to_platform_device(dev_id); 49 struct platform_device *pdev = to_platform_device(dev_id);
@@ -146,9 +87,6 @@ static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id)
146 87
147 rtc_update_irq(rtc, 1, events); 88 rtc_update_irq(rtc, 1, events);
148 89
149 if (rtsr & RTSR_AL && rtc_periodic_alarm(&rtc_alarm))
150 rtc_update_alarm(&rtc_alarm);
151
152 spin_unlock(&sa1100_rtc_lock); 90 spin_unlock(&sa1100_rtc_lock);
153 91
154 return IRQ_HANDLED; 92 return IRQ_HANDLED;
@@ -224,7 +162,6 @@ static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
224{ 162{
225 u32 rtsr; 163 u32 rtsr;
226 164
227 memcpy(&alrm->time, &rtc_alarm, sizeof(struct rtc_time));
228 rtsr = RTSR; 165 rtsr = RTSR;
229 alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0; 166 alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0;
230 alrm->pending = (rtsr & RTSR_AL) ? 1 : 0; 167 alrm->pending = (rtsr & RTSR_AL) ? 1 : 0;
@@ -233,16 +170,20 @@ static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
233 170
234static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 171static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
235{ 172{
173 unsigned long time;
236 int ret; 174 int ret;
237 175
238 spin_lock_irq(&sa1100_rtc_lock); 176 spin_lock_irq(&sa1100_rtc_lock);
239 ret = rtc_update_alarm(&alrm->time); 177 ret = rtc_tm_to_time(&alrm->time, &time);
240 if (ret == 0) { 178 if (ret != 0)
241 if (alrm->enabled) 179 goto out;
242 RTSR |= RTSR_ALE; 180 RTSR = RTSR & (RTSR_HZE|RTSR_ALE|RTSR_AL);
243 else 181 RTAR = time;
244 RTSR &= ~RTSR_ALE; 182 if (alrm->enabled)
245 } 183 RTSR |= RTSR_ALE;
184 else
185 RTSR &= ~RTSR_ALE;
186out:
246 spin_unlock_irq(&sa1100_rtc_lock); 187 spin_unlock_irq(&sa1100_rtc_lock);
247 188
248 return ret; 189 return ret;
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 0b06e360628a..3ed748355b98 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -293,7 +293,7 @@ config SPI_RSPI
293 293
294config SPI_S3C24XX 294config SPI_S3C24XX
295 tristate "Samsung S3C24XX series SPI" 295 tristate "Samsung S3C24XX series SPI"
296 depends on ARCH_S3C2410 && EXPERIMENTAL 296 depends on ARCH_S3C24XX && EXPERIMENTAL
297 select SPI_BITBANG 297 select SPI_BITBANG
298 help 298 help
299 SPI driver for Samsung S3C24XX series ARM SoCs 299 SPI driver for Samsung S3C24XX series ARM SoCs
diff --git a/drivers/spi/spi-s3c24xx.c b/drivers/spi/spi-s3c24xx.c
index fc064535f4fc..8ee7d790ce49 100644
--- a/drivers/spi/spi-s3c24xx.c
+++ b/drivers/spi/spi-s3c24xx.c
@@ -24,10 +24,10 @@
24 24
25#include <linux/spi/spi.h> 25#include <linux/spi/spi.h>
26#include <linux/spi/spi_bitbang.h> 26#include <linux/spi/spi_bitbang.h>
27#include <linux/spi/s3c24xx.h>
27#include <linux/module.h> 28#include <linux/module.h>
28 29
29#include <plat/regs-spi.h> 30#include <plat/regs-spi.h>
30#include <mach/spi.h>
31 31
32#include <plat/fiq.h> 32#include <plat/fiq.h>
33#include <asm/fiq.h> 33#include <asm/fiq.h>
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index e4405e088589..48ac6e781ba2 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -16,7 +16,7 @@ config USB_ARCH_HAS_OHCI
16 # ARM: 16 # ARM:
17 default y if SA1111 17 default y if SA1111
18 default y if ARCH_OMAP 18 default y if ARCH_OMAP
19 default y if ARCH_S3C2410 19 default y if ARCH_S3C24XX
20 default y if PXA27x 20 default y if PXA27x
21 default y if PXA3xx 21 default y if PXA3xx
22 default y if ARCH_EP93XX 22 default y if ARCH_EP93XX
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index c14a3972953a..26c0b75f152e 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -137,7 +137,7 @@ choice
137 137
138config USB_AT91 138config USB_AT91
139 tristate "Atmel AT91 USB Device Port" 139 tristate "Atmel AT91 USB Device Port"
140 depends on ARCH_AT91 && !ARCH_AT91SAM9RL && !ARCH_AT91CAP9 && !ARCH_AT91SAM9G45 140 depends on ARCH_AT91 && !ARCH_AT91SAM9RL && !ARCH_AT91SAM9G45
141 help 141 help
142 Many Atmel AT91 processors (such as the AT91RM2000) have a 142 Many Atmel AT91 processors (such as the AT91RM2000) have a
143 full speed USB Device Port with support for five configurable 143 full speed USB Device Port with support for five configurable
@@ -150,7 +150,7 @@ config USB_AT91
150config USB_ATMEL_USBA 150config USB_ATMEL_USBA
151 tristate "Atmel USBA" 151 tristate "Atmel USBA"
152 select USB_GADGET_DUALSPEED 152 select USB_GADGET_DUALSPEED
153 depends on AVR32 || ARCH_AT91CAP9 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 153 depends on AVR32 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45
154 help 154 help
155 USBA is the integrated high-speed USB Device controller on 155 USBA is the integrated high-speed USB Device controller on
156 the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel. 156 the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel.
@@ -284,7 +284,7 @@ config USB_IMX
284 284
285config USB_S3C2410 285config USB_S3C2410
286 tristate "S3C2410 USB Device Controller" 286 tristate "S3C2410 USB Device Controller"
287 depends on ARCH_S3C2410 287 depends on ARCH_S3C24XX
288 help 288 help
289 Samsung's S3C2410 is an ARM-4 processor with an integrated 289 Samsung's S3C2410 is an ARM-4 processor with an integrated
290 full speed USB 1.1 device controller. It has 4 configurable 290 full speed USB 1.1 device controller. It has 4 configurable
@@ -299,7 +299,7 @@ config USB_S3C2410_DEBUG
299 299
300config USB_S3C_HSUDC 300config USB_S3C_HSUDC
301 tristate "S3C2416, S3C2443 and S3C2450 USB Device Controller" 301 tristate "S3C2416, S3C2443 and S3C2450 USB Device Controller"
302 depends on ARCH_S3C2410 302 depends on ARCH_S3C24XX
303 select USB_GADGET_DUALSPEED 303 select USB_GADGET_DUALSPEED
304 help 304 help
305 Samsung's S3C2416, S3C2443 and S3C2450 is an ARM9 based SoC 305 Samsung's S3C2416, S3C2443 and S3C2450 is an ARM9 based SoC
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index cd5e382db89c..543e90e336b8 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1000,7 +1000,7 @@ MODULE_LICENSE ("GPL");
1000#define SA1111_DRIVER ohci_hcd_sa1111_driver 1000#define SA1111_DRIVER ohci_hcd_sa1111_driver
1001#endif 1001#endif
1002 1002
1003#if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX) 1003#if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S3C64XX)
1004#include "ohci-s3c2410.c" 1004#include "ohci-s3c2410.c"
1005#define PLATFORM_DRIVER ohci_hcd_s3c2410_driver 1005#define PLATFORM_DRIVER ohci_hcd_s3c2410_driver
1006#endif 1006#endif
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index a8a897ac5446..a290be51a1f4 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -2061,7 +2061,7 @@ config FB_S3C_DEBUG_REGWRITE
2061 2061
2062config FB_S3C2410 2062config FB_S3C2410
2063 tristate "S3C2410 LCD framebuffer support" 2063 tristate "S3C2410 LCD framebuffer support"
2064 depends on FB && ARCH_S3C2410 2064 depends on FB && ARCH_S3C24XX
2065 select FB_CFB_FILLRECT 2065 select FB_CFB_FILLRECT
2066 select FB_CFB_COPYAREA 2066 select FB_CFB_COPYAREA
2067 select FB_CFB_IMAGEBLIT 2067 select FB_CFB_IMAGEBLIT
diff --git a/drivers/video/backlight/ep93xx_bl.c b/drivers/video/backlight/ep93xx_bl.c
index b62b8b9063b5..08214e1f0958 100644
--- a/drivers/video/backlight/ep93xx_bl.c
+++ b/drivers/video/backlight/ep93xx_bl.c
@@ -17,11 +17,6 @@
17#include <linux/fb.h> 17#include <linux/fb.h>
18#include <linux/backlight.h> 18#include <linux/backlight.h>
19 19
20#include <mach/hardware.h>
21
22#define EP93XX_RASTER_REG(x) (EP93XX_RASTER_BASE + (x))
23#define EP93XX_RASTER_BRIGHTNESS EP93XX_RASTER_REG(0x20)
24
25#define EP93XX_MAX_COUNT 255 20#define EP93XX_MAX_COUNT 255
26#define EP93XX_MAX_BRIGHT 255 21#define EP93XX_MAX_BRIGHT 255
27#define EP93XX_DEF_BRIGHT 128 22#define EP93XX_DEF_BRIGHT 128
@@ -35,7 +30,7 @@ static int ep93xxbl_set(struct backlight_device *bl, int brightness)
35{ 30{
36 struct ep93xxbl *ep93xxbl = bl_get_data(bl); 31 struct ep93xxbl *ep93xxbl = bl_get_data(bl);
37 32
38 __raw_writel((brightness << 8) | EP93XX_MAX_COUNT, ep93xxbl->mmio); 33 writel((brightness << 8) | EP93XX_MAX_COUNT, ep93xxbl->mmio);
39 34
40 ep93xxbl->brightness = brightness; 35 ep93xxbl->brightness = brightness;
41 36
@@ -70,21 +65,29 @@ static int __init ep93xxbl_probe(struct platform_device *dev)
70 struct ep93xxbl *ep93xxbl; 65 struct ep93xxbl *ep93xxbl;
71 struct backlight_device *bl; 66 struct backlight_device *bl;
72 struct backlight_properties props; 67 struct backlight_properties props;
68 struct resource *res;
73 69
74 ep93xxbl = devm_kzalloc(&dev->dev, sizeof(*ep93xxbl), GFP_KERNEL); 70 ep93xxbl = devm_kzalloc(&dev->dev, sizeof(*ep93xxbl), GFP_KERNEL);
75 if (!ep93xxbl) 71 if (!ep93xxbl)
76 return -ENOMEM; 72 return -ENOMEM;
77 73
74 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
75 if (!res)
76 return -ENXIO;
77
78 /* 78 /*
79 * This register is located in the range already ioremap'ed by 79 * FIXME - We don't do a request_mem_region here because we are
80 * the framebuffer driver. A MFD driver seems a bit of overkill 80 * sharing the register space with the framebuffer driver (see
81 * to handle this so use the static I/O mapping; this address 81 * drivers/video/ep93xx-fb.c) and doing so will cause the second
82 * is already virtual. 82 * loaded driver to return -EBUSY.
83 * 83 *
84 * NOTE: No locking is required; the framebuffer does not touch 84 * NOTE: No locking is required; the framebuffer does not touch
85 * this register. 85 * this register.
86 */ 86 */
87 ep93xxbl->mmio = EP93XX_RASTER_BRIGHTNESS; 87 ep93xxbl->mmio = devm_ioremap(&dev->dev, res->start,
88 resource_size(res));
89 if (!ep93xxbl->mmio)
90 return -ENXIO;
88 91
89 memset(&props, 0, sizeof(struct backlight_properties)); 92 memset(&props, 0, sizeof(struct backlight_properties));
90 props.type = BACKLIGHT_RAW; 93 props.type = BACKLIGHT_RAW;
diff --git a/drivers/video/ep93xx-fb.c b/drivers/video/ep93xx-fb.c
index 2e830ec52a5a..f8babbeee275 100644
--- a/drivers/video/ep93xx-fb.c
+++ b/drivers/video/ep93xx-fb.c
@@ -519,12 +519,15 @@ static int __devinit ep93xxfb_probe(struct platform_device *pdev)
519 goto failed; 519 goto failed;
520 } 520 }
521 521
522 res = request_mem_region(res->start, resource_size(res), pdev->name); 522 /*
523 if (!res) { 523 * FIXME - We don't do a request_mem_region here because we are
524 err = -EBUSY; 524 * sharing the register space with the backlight driver (see
525 goto failed; 525 * drivers/video/backlight/ep93xx_bl.c) and doing so will cause
526 } 526 * the second loaded driver to return -EBUSY.
527 527 *
528 * NOTE: No locking is required; the backlight does not touch
529 * any of the framebuffer registers.
530 */
528 fbi->res = res; 531 fbi->res = res;
529 fbi->mmio_base = ioremap(res->start, resource_size(res)); 532 fbi->mmio_base = ioremap(res->start, resource_size(res));
530 if (!fbi->mmio_base) { 533 if (!fbi->mmio_base) {
@@ -586,8 +589,6 @@ failed:
586 clk_put(fbi->clk); 589 clk_put(fbi->clk);
587 if (fbi->mmio_base) 590 if (fbi->mmio_base)
588 iounmap(fbi->mmio_base); 591 iounmap(fbi->mmio_base);
589 if (fbi->res)
590 release_mem_region(fbi->res->start, resource_size(fbi->res));
591 ep93xxfb_dealloc_videomem(info); 592 ep93xxfb_dealloc_videomem(info);
592 if (&info->cmap) 593 if (&info->cmap)
593 fb_dealloc_cmap(&info->cmap); 594 fb_dealloc_cmap(&info->cmap);
@@ -608,7 +609,6 @@ static int __devexit ep93xxfb_remove(struct platform_device *pdev)
608 clk_disable(fbi->clk); 609 clk_disable(fbi->clk);
609 clk_put(fbi->clk); 610 clk_put(fbi->clk);
610 iounmap(fbi->mmio_base); 611 iounmap(fbi->mmio_base);
611 release_mem_region(fbi->res->start, resource_size(fbi->res));
612 ep93xxfb_dealloc_videomem(info); 612 ep93xxfb_dealloc_videomem(info);
613 fb_dealloc_cmap(&info->cmap); 613 fb_dealloc_cmap(&info->cmap);
614 614
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index bddd64b435b9..ee30937482e1 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -3318,11 +3318,6 @@ static void _omap_dispc_initial_config(void)
3318 if (dss_has_feature(FEAT_FUNCGATED)) 3318 if (dss_has_feature(FEAT_FUNCGATED))
3319 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); 3319 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3320 3320
3321 /* L3 firewall setting: enable access to OCM RAM */
3322 /* XXX this should be somewhere in plat-omap */
3323 if (cpu_is_omap24xx())
3324 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3325
3326 _dispc_setup_color_conv_coef(); 3321 _dispc_setup_color_conv_coef();
3327 3322
3328 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY); 3323 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 4a6b5eeef6a7..bd2d5e159463 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -33,7 +33,10 @@
33#include <linux/pm_runtime.h> 33#include <linux/pm_runtime.h>
34 34
35#include <video/omapdss.h> 35#include <video/omapdss.h>
36
37#include <plat/cpu.h>
36#include <plat/clock.h> 38#include <plat/clock.h>
39
37#include "dss.h" 40#include "dss.h"
38#include "dss_features.h" 41#include "dss_features.h"
39 42
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 7e9e8f4d8f0c..0e7366dfc901 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -170,7 +170,7 @@ config HAVE_S3C2410_WATCHDOG
170 170
171config S3C2410_WATCHDOG 171config S3C2410_WATCHDOG
172 tristate "S3C2410 Watchdog" 172 tristate "S3C2410 Watchdog"
173 depends on ARCH_S3C2410 || HAVE_S3C2410_WATCHDOG 173 depends on HAVE_S3C2410_WATCHDOG
174 select WATCHDOG_CORE 174 select WATCHDOG_CORE
175 help 175 help
176 Watchdog timer block in the Samsung SoCs. This will reboot 176 Watchdog timer block in the Samsung SoCs. This will reboot
diff --git a/drivers/watchdog/ep93xx_wdt.c b/drivers/watchdog/ep93xx_wdt.c
index 726b7df61fd0..09cd888db619 100644
--- a/drivers/watchdog/ep93xx_wdt.c
+++ b/drivers/watchdog/ep93xx_wdt.c
@@ -23,6 +23,7 @@
23 * - Add a few missing ioctls 23 * - Add a few missing ioctls
24 */ 24 */
25 25
26#include <linux/platform_device.h>
26#include <linux/module.h> 27#include <linux/module.h>
27#include <linux/fs.h> 28#include <linux/fs.h>
28#include <linux/miscdevice.h> 29#include <linux/miscdevice.h>
@@ -30,7 +31,6 @@
30#include <linux/timer.h> 31#include <linux/timer.h>
31#include <linux/uaccess.h> 32#include <linux/uaccess.h>
32#include <linux/io.h> 33#include <linux/io.h>
33#include <mach/hardware.h>
34 34
35#define WDT_VERSION "0.3" 35#define WDT_VERSION "0.3"
36#define PFX "ep93xx_wdt: " 36#define PFX "ep93xx_wdt: "
@@ -41,6 +41,7 @@
41static int nowayout = WATCHDOG_NOWAYOUT; 41static int nowayout = WATCHDOG_NOWAYOUT;
42static int timeout = WDT_TIMEOUT; 42static int timeout = WDT_TIMEOUT;
43 43
44static void __iomem *mmio_base;
44static struct timer_list timer; 45static struct timer_list timer;
45static unsigned long next_heartbeat; 46static unsigned long next_heartbeat;
46static unsigned long wdt_status; 47static unsigned long wdt_status;
@@ -49,26 +50,25 @@ static unsigned long boot_status;
49#define WDT_IN_USE 0 50#define WDT_IN_USE 0
50#define WDT_OK_TO_CLOSE 1 51#define WDT_OK_TO_CLOSE 1
51 52
52#define EP93XX_WDT_REG(x) (EP93XX_WATCHDOG_BASE + (x)) 53#define EP93XX_WATCHDOG 0x00
53#define EP93XX_WDT_WATCHDOG EP93XX_WDT_REG(0x00) 54#define EP93XX_WDSTATUS 0x04
54#define EP93XX_WDT_WDSTATUS EP93XX_WDT_REG(0x04)
55 55
56/* reset the wdt every ~200ms */ 56/* reset the wdt every ~200ms */
57#define WDT_INTERVAL (HZ/5) 57#define WDT_INTERVAL (HZ/5)
58 58
59static void wdt_enable(void) 59static void wdt_enable(void)
60{ 60{
61 __raw_writew(0xaaaa, EP93XX_WDT_WATCHDOG); 61 writel(0xaaaa, mmio_base + EP93XX_WATCHDOG);
62} 62}
63 63
64static void wdt_disable(void) 64static void wdt_disable(void)
65{ 65{
66 __raw_writew(0xaa55, EP93XX_WDT_WATCHDOG); 66 writel(0xaa55, mmio_base + EP93XX_WATCHDOG);
67} 67}
68 68
69static inline void wdt_ping(void) 69static inline void wdt_ping(void)
70{ 70{
71 __raw_writew(0x5555, EP93XX_WDT_WATCHDOG); 71 writel(0x5555, mmio_base + EP93XX_WATCHDOG);
72} 72}
73 73
74static void wdt_startup(void) 74static void wdt_startup(void)
@@ -206,18 +206,32 @@ static void ep93xx_timer_ping(unsigned long data)
206 mod_timer(&timer, jiffies + WDT_INTERVAL); 206 mod_timer(&timer, jiffies + WDT_INTERVAL);
207} 207}
208 208
209static int __init ep93xx_wdt_init(void) 209static int __devinit ep93xx_wdt_probe(struct platform_device *pdev)
210{ 210{
211 struct resource *res;
212 unsigned long val;
211 int err; 213 int err;
212 214
215 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
216 if (!res)
217 return -ENXIO;
218
219 if (!devm_request_mem_region(&pdev->dev, res->start,
220 resource_size(res), pdev->name))
221 return -EBUSY;
222
223 mmio_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
224 if (!mmio_base)
225 return -ENXIO;
226
213 err = misc_register(&ep93xx_wdt_miscdev); 227 err = misc_register(&ep93xx_wdt_miscdev);
214 228
215 boot_status = __raw_readl(EP93XX_WDT_WATCHDOG) & 0x01 ? 1 : 0; 229 val = readl(mmio_base + EP93XX_WATCHDOG);
230 boot_status = val & 0x01 ? 1 : 0;
216 231
217 printk(KERN_INFO PFX "EP93XX watchdog, driver version " 232 printk(KERN_INFO PFX "EP93XX watchdog, driver version "
218 WDT_VERSION "%s\n", 233 WDT_VERSION "%s\n",
219 (__raw_readl(EP93XX_WDT_WATCHDOG) & 0x08) 234 (val & 0x08) ? " (nCS1 disable detected)" : "");
220 ? " (nCS1 disable detected)" : "");
221 235
222 if (timeout < 1 || timeout > 3600) { 236 if (timeout < 1 || timeout > 3600) {
223 timeout = WDT_TIMEOUT; 237 timeout = WDT_TIMEOUT;
@@ -230,14 +244,23 @@ static int __init ep93xx_wdt_init(void)
230 return err; 244 return err;
231} 245}
232 246
233static void __exit ep93xx_wdt_exit(void) 247static int __devexit ep93xx_wdt_remove(struct platform_device *pdev)
234{ 248{
235 wdt_shutdown(); 249 wdt_shutdown();
236 misc_deregister(&ep93xx_wdt_miscdev); 250 misc_deregister(&ep93xx_wdt_miscdev);
251 return 0;
237} 252}
238 253
239module_init(ep93xx_wdt_init); 254static struct platform_driver ep93xx_wdt_driver = {
240module_exit(ep93xx_wdt_exit); 255 .driver = {
256 .owner = THIS_MODULE,
257 .name = "ep93xx-wdt",
258 },
259 .probe = ep93xx_wdt_probe,
260 .remove = __devexit_p(ep93xx_wdt_remove),
261};
262
263module_platform_driver(ep93xx_wdt_driver);
241 264
242module_param(nowayout, int, 0); 265module_param(nowayout, int, 0);
243MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"); 266MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 12:59:05 -0500