75 files changed, 3475 insertions, 1889 deletions

diff --git a/drivers/acpi/ac.c b/drivers/acpi/ac.c
index 5b73f6a2cd86..831883b7d6c9 100644
--- a/drivers/acpi/ac.c
+++ b/drivers/acpi/ac.c
@@ -233,6 +233,9 @@ static void acpi_ac_notify(acpi_handle handle, u32 event, void *data)
 
         device = ac->device;
         switch (event) {
+        default:
+                ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+                                  "Unsupported event [0x%x]\n", event));
         case ACPI_AC_NOTIFY_STATUS:
         case ACPI_NOTIFY_BUS_CHECK:
         case ACPI_NOTIFY_DEVICE_CHECK:
@@ -244,11 +247,6 @@ static void acpi_ac_notify(acpi_handle handle, u32 event, void *data)
 #ifdef CONFIG_ACPI_SYSFS_POWER
                 kobject_uevent(&ac->charger.dev->kobj, KOBJ_CHANGE);
 #endif
-                break;
-        default:
-                ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-                                  "Unsupported event [0x%x]\n", event));
-                break;
         }
 
         return;
diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c
index 5e5dda3a3027..d089c4519d45 100644
--- a/drivers/acpi/video.c
+++ b/drivers/acpi/video.c
@@ -1713,7 +1713,8 @@ acpi_video_bus_get_devices(struct acpi_video_bus *video,
 
                 status = acpi_video_bus_get_one_device(dev, video);
                 if (ACPI_FAILURE(status)) {
-                        ACPI_EXCEPTION((AE_INFO, status, "Cant attach device"));
+                        ACPI_DEBUG_PRINT((ACPI_DB_WARN,
+                                        "Cant attach device"));
                         continue;
                 }
         }
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 9bf2986a2788..ae8494944c45 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -651,9 +651,17 @@ config PATA_WINBOND_VLB
           Support for the Winbond W83759A controller on Vesa Local Bus
           systems.
 
+config HAVE_PATA_PLATFORM
+        bool
+        help
+          This is an internal configuration node for any machine that
+          uses pata-platform driver to enable the relevant driver in the
+          configuration structure without having to submit endless patches
+          to update the PATA_PLATFORM entry.
+
 config PATA_PLATFORM
         tristate "Generic platform device PATA support"
-        depends on EMBEDDED || ARCH_RPC || PPC
+        depends on EMBEDDED || ARCH_RPC || PPC || HAVE_PATA_PLATFORM
         help
           This option enables support for generic directly connected ATA
           devices commonly found on embedded systems.
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 966ab401e523..6a4a2a25d97a 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -90,6 +90,7 @@ enum {
         board_ahci_mv           = 4,
         board_ahci_sb700        = 5,
         board_ahci_mcp65        = 6,
+        board_ahci_nopmp        = 7,
 
         /* global controller registers */
         HOST_CAP                = 0x00, /* host capabilities */
@@ -401,6 +402,14 @@ static const struct ata_port_info ahci_port_info[] = {
                 .udma_mask      = ATA_UDMA6,
                 .port_ops       = &ahci_ops,
         },
+        /* board_ahci_nopmp */
+        {
+                AHCI_HFLAGS     (AHCI_HFLAG_NO_PMP),
+                .flags          = AHCI_FLAG_COMMON,
+                .pio_mask       = 0x1f, /* pio0-4 */
+                .udma_mask      = ATA_UDMA6,
+                .port_ops       = &ahci_ops,
+        },
 };
 
 static const struct pci_device_id ahci_pci_tbl[] = {
@@ -525,9 +534,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
         { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci },            /* MCP7B */
 
         /* SiS */
-        { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
-        { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
-        { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
+        { PCI_VDEVICE(SI, 0x1184), board_ahci_nopmp },          /* SiS 966 */
+        { PCI_VDEVICE(SI, 0x1185), board_ahci_nopmp },          /* SiS 968 */
+        { PCI_VDEVICE(SI, 0x0186), board_ahci_nopmp },          /* SiS 968 */
 
         /* Marvell */
         { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },        /* 6145 */
@@ -653,6 +662,14 @@ static void ahci_save_initial_config(struct pci_dev *pdev,
                 cap &= ~HOST_CAP_PMP;
         }
 
+        if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
+            port_map != 1) {
+                dev_printk(KERN_INFO, &pdev->dev,
+                           "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
+                           port_map, 1);
+                port_map = 1;
+        }
+
         /*
          * Temporary Marvell 6145 hack: PATA port presence
          * is asserted through the standard AHCI port
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
index 81b7ae376951..a90ae03f56b2 100644
--- a/drivers/ata/ata_piix.c
+++ b/drivers/ata/ata_piix.c
@@ -1043,6 +1043,13 @@ static int piix_broken_suspend(void)
                         },
                 },
                 {
+                        .ident = "TECRA M4",
+                        .matches = {
+                                DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+                                DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
+                        },
+                },
+                {
                         .ident = "TECRA M5",
                         .matches = {
                                 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index cc816ca623d3..303fc0d2b978 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -4297,7 +4297,7 @@ void ata_sg_clean(struct ata_queued_cmd *qc)
 }
 
 /**
- *      ata_check_atapi_dma - Check whether ATAPI DMA can be supported
+ *      atapi_check_dma - Check whether ATAPI DMA can be supported
  *      @qc: Metadata associated with taskfile to check
  *
  *      Allow low-level driver to filter ATA PACKET commands, returning
@@ -4310,7 +4310,7 @@ void ata_sg_clean(struct ata_queued_cmd *qc)
  *      RETURNS: 0 when ATAPI DMA can be used
  *               nonzero otherwise
  */
-int ata_check_atapi_dma(struct ata_queued_cmd *qc)
+int atapi_check_dma(struct ata_queued_cmd *qc)
 {
         struct ata_port *ap = qc->ap;
 
diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c
index 2e6e1622dc6d..57a43649a461 100644
--- a/drivers/ata/libata-scsi.c
+++ b/drivers/ata/libata-scsi.c
@@ -2343,8 +2343,8 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc)
 {
         struct scsi_cmnd *scmd = qc->scsicmd;
         struct ata_device *dev = qc->dev;
-        int using_pio = (dev->flags & ATA_DFLAG_PIO);
         int nodata = (scmd->sc_data_direction == DMA_NONE);
+        int using_pio = !nodata && (dev->flags & ATA_DFLAG_PIO);
         unsigned int nbytes;
 
         memset(qc->cdb, 0, dev->cdb_len);
@@ -2362,7 +2362,7 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc)
         ata_qc_set_pc_nbytes(qc);
 
         /* check whether ATAPI DMA is safe */
-        if (!using_pio && ata_check_atapi_dma(qc))
+        if (!nodata && !using_pio && atapi_check_dma(qc))
                 using_pio = 1;
 
         /* Some controller variants snoop this value for Packet
@@ -2402,13 +2402,11 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc)
         qc->tf.lbam = (nbytes & 0xFF);
         qc->tf.lbah = (nbytes >> 8);
 
-        if (using_pio || nodata) {
-                /* no data, or PIO data xfer */
-                if (nodata)
-                        qc->tf.protocol = ATAPI_PROT_NODATA;
-                else
-                        qc->tf.protocol = ATAPI_PROT_PIO;
-        } else {
+        if (nodata)
+                qc->tf.protocol = ATAPI_PROT_NODATA;
+        else if (using_pio)
+                qc->tf.protocol = ATAPI_PROT_PIO;
+        else {
                 /* DMA data xfer */
                 qc->tf.protocol = ATAPI_PROT_DMA;
                 qc->tf.feature |= ATAPI_PKT_DMA;
diff --git a/drivers/ata/libata.h b/drivers/ata/libata.h
index 4514283937ea..1cf803adbc95 100644
--- a/drivers/ata/libata.h
+++ b/drivers/ata/libata.h
@@ -106,7 +106,7 @@ extern void ata_sg_clean(struct ata_queued_cmd *qc);
 extern void ata_qc_free(struct ata_queued_cmd *qc);
 extern void ata_qc_issue(struct ata_queued_cmd *qc);
 extern void __ata_qc_complete(struct ata_queued_cmd *qc);
-extern int ata_check_atapi_dma(struct ata_queued_cmd *qc);
+extern int atapi_check_dma(struct ata_queued_cmd *qc);
 extern void swap_buf_le16(u16 *buf, unsigned int buf_words);
 extern void ata_dev_init(struct ata_device *dev);
 extern void ata_link_init(struct ata_port *ap, struct ata_link *link, int pmp);
diff --git a/drivers/ata/pata_pcmcia.c b/drivers/ata/pata_pcmcia.c
index 3d39f9dfec5a..41b4361bbf6e 100644
--- a/drivers/ata/pata_pcmcia.c
+++ b/drivers/ata/pata_pcmcia.c
@@ -414,6 +414,7 @@ static struct pcmcia_device_id pcmcia_devices[] = {
         PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDE", 0x547e66dc, 0x5c5ab149),
         PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDEII", 0x547e66dc, 0xb3662674),
         PCMCIA_DEVICE_PROD_ID12("LOOKMEET", "CBIDE2      ", 0xe37be2b5, 0x8671043b),
+        PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF300", 0x7ed2ad87, 0x7e9e78ee),
         PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF500", 0x7ed2ad87, 0x7a13045c),
         PCMCIA_DEVICE_PROD_ID2("NinjaATA-", 0xebe0bd79),
         PCMCIA_DEVICE_PROD_ID12("PCMCIA", "CD-ROM", 0x281f1c5d, 0x66536591),
@@ -424,6 +425,7 @@ static struct pcmcia_device_id pcmcia_devices[] = {
         PCMCIA_DEVICE_PROD_ID12("SMI VENDOR", "SMI PRODUCT", 0x30896c92, 0x703cc5f6),
         PCMCIA_DEVICE_PROD_ID12("TOSHIBA", "MK2001MPL", 0xb4585a1a, 0x3489e003),
         PCMCIA_DEVICE_PROD_ID1("TRANSCEND    512M   ", 0xd0909443),
+        PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF45", 0x709b1bf1, 0xf68b6f32),
         PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF80", 0x709b1bf1, 0x2a54d4b1),
         PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS2GCF120", 0x709b1bf1, 0x969aa4f2),
         PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS4GCF120", 0x709b1bf1, 0xf54a91c8),
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index 60391e9a84db..28092bc50146 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -1322,6 +1322,9 @@ static int mv_port_start(struct ata_port *ap)
                 goto out_port_free_dma_mem;
         memset(pp->crpb, 0, MV_CRPB_Q_SZ);
 
+        /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
+        if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
+                ap->flags |= ATA_FLAG_AN;
         /*
          * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
          * For later hardware, we need one unique sg_tbl per NCQ tag.
@@ -1592,6 +1595,24 @@ static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
 
         if ((qc->tf.protocol != ATA_PROT_DMA) &&
             (qc->tf.protocol != ATA_PROT_NCQ)) {
+                static int limit_warnings = 10;
+                /*
+                 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
+                 *
+                 * Someday, we might implement special polling workarounds
+                 * for these, but it all seems rather unnecessary since we
+                 * normally use only DMA for commands which transfer more
+                 * than a single block of data.
+                 *
+                 * Much of the time, this could just work regardless.
+                 * So for now, just log the incident, and allow the attempt.
+                 */
+                if (limit_warnings && (qc->nbytes / qc->sect_size) > 1) {
+                        --limit_warnings;
+                        ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
+                                        ": attempting PIO w/multiple DRQ: "
+                                        "this may fail due to h/w errata\n");
+                }
                 /*
                  * We're about to send a non-EDMA capable command to the
                  * port.  Turn off EDMA so there won't be problems accessing
diff --git a/drivers/char/agp/agp.h b/drivers/char/agp/agp.h
index 99e6a406efb4..81e14bea54bd 100644
--- a/drivers/char/agp/agp.h
+++ b/drivers/char/agp/agp.h
@@ -99,8 +99,8 @@ struct agp_bridge_driver {
         const void *aperture_sizes;
         int num_aperture_sizes;
         enum aper_size_type size_type;
-        int cant_use_aperture;
-        int needs_scratch_page;
+        bool cant_use_aperture;
+        bool needs_scratch_page;
         const struct gatt_mask *masks;
         int (*fetch_size)(void);
         int (*configure)(void);
@@ -278,7 +278,7 @@ void agp_generic_destroy_page(void *addr, int flags);
 void agp_free_key(int key);
 int agp_num_entries(void);
 u32 agp_collect_device_status(struct agp_bridge_data *bridge, u32 mode, u32 command);
-void agp_device_command(u32 command, int agp_v3);
+void agp_device_command(u32 command, bool agp_v3);
 int agp_3_5_enable(struct agp_bridge_data *bridge);
 void global_cache_flush(void);
 void get_agp_version(struct agp_bridge_data *bridge);
diff --git a/drivers/char/agp/alpha-agp.c b/drivers/char/agp/alpha-agp.c
index e77c17838c8a..5da89f6c6c25 100644
--- a/drivers/char/agp/alpha-agp.c
+++ b/drivers/char/agp/alpha-agp.c
@@ -80,7 +80,7 @@ static void alpha_core_agp_enable(struct agp_bridge_data *bridge, u32 mode)
         agp->mode.bits.enable = 1;
         agp->ops->configure(agp);
 
-        agp_device_command(agp->mode.lw, 0);
+        agp_device_command(agp->mode.lw, false);
 }
 
 static int alpha_core_agp_insert_memory(struct agp_memory *mem, off_t pg_start,
@@ -126,7 +126,7 @@ struct agp_bridge_driver alpha_core_agp_driver = {
         .aperture_sizes         = alpha_core_agp_sizes,
         .num_aperture_sizes     = 1,
         .size_type              = FIXED_APER_SIZE,
-        .cant_use_aperture      = 1,
+        .cant_use_aperture      = true,
         .masks                  = NULL,
 
         .fetch_size             = alpha_core_agp_fetch_size,
diff --git a/drivers/char/agp/amd-k7-agp.c b/drivers/char/agp/amd-k7-agp.c
index 96bdb9296b07..39a0718bc616 100644
--- a/drivers/char/agp/amd-k7-agp.c
+++ b/drivers/char/agp/amd-k7-agp.c
@@ -314,9 +314,9 @@ static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
                 j++;
         }
 
-        if (mem->is_flushed == FALSE) {
+        if (!mem->is_flushed) {
                 global_cache_flush();
-                mem->is_flushed = TRUE;
+                mem->is_flushed = true;
         }
 
         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c
index d8200ac8f8cb..13665db363d6 100644
--- a/drivers/char/agp/amd64-agp.c
+++ b/drivers/char/agp/amd64-agp.c
@@ -90,9 +90,9 @@ static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
                 j++;
         }
 
-        if (mem->is_flushed == FALSE) {
+        if (!mem->is_flushed) {
                 global_cache_flush();
-                mem->is_flushed = TRUE;
+                mem->is_flushed = true;
         }
 
         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
diff --git a/drivers/char/agp/ati-agp.c b/drivers/char/agp/ati-agp.c
index 07b4d8ff56e5..3a4566c0d84f 100644
--- a/drivers/char/agp/ati-agp.c
+++ b/drivers/char/agp/ati-agp.c
@@ -287,10 +287,10 @@ static int ati_insert_memory(struct agp_memory * mem,
                 j++;
         }
 
-        if (mem->is_flushed == FALSE) {
+        if (!mem->is_flushed) {
                 /*CACHE_FLUSH(); */
                 global_cache_flush();
-                mem->is_flushed = TRUE;
+                mem->is_flushed = true;
         }
 
         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
diff --git a/drivers/char/agp/backend.c b/drivers/char/agp/backend.c
index b1bdd015165c..1ec87104e68c 100644
--- a/drivers/char/agp/backend.c
+++ b/drivers/char/agp/backend.c
@@ -188,10 +188,10 @@ static int agp_backend_initialize(struct agp_bridge_data *bridge)
 
 err_out:
         if (bridge->driver->needs_scratch_page) {
-                bridge->driver->agp_destroy_page(gart_to_virt(bridge->scratch_page_real),
-                                                 AGP_PAGE_DESTROY_UNMAP);
-                bridge->driver->agp_destroy_page(gart_to_virt(bridge->scratch_page_real),
-                                                 AGP_PAGE_DESTROY_FREE);
+                void *va = gart_to_virt(bridge->scratch_page_real);
+
+                bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_UNMAP);
+                bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_FREE);
         }
         if (got_gatt)
                 bridge->driver->free_gatt_table(bridge);
@@ -215,10 +215,10 @@ static void agp_backend_cleanup(struct agp_bridge_data *bridge)
 
         if (bridge->driver->agp_destroy_page &&
             bridge->driver->needs_scratch_page) {
-                bridge->driver->agp_destroy_page(gart_to_virt(bridge->scratch_page_real),
-                                                 AGP_PAGE_DESTROY_UNMAP);
-                bridge->driver->agp_destroy_page(gart_to_virt(bridge->scratch_page_real),
-                                                 AGP_PAGE_DESTROY_FREE);
+                void *va = gart_to_virt(bridge->scratch_page_real);
+
+                bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_UNMAP);
+                bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_FREE);
         }
 }
 
diff --git a/drivers/char/agp/compat_ioctl.c b/drivers/char/agp/compat_ioctl.c
index 39275794fe63..58c57cb2518c 100644
--- a/drivers/char/agp/compat_ioctl.c
+++ b/drivers/char/agp/compat_ioctl.c
@@ -214,7 +214,7 @@ long compat_agp_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
                 ret_val = -EINVAL;
                 goto ioctl_out;
         }
-        if ((agp_fe.backend_acquired != TRUE) &&
+        if ((agp_fe.backend_acquired != true) &&
             (cmd != AGPIOC_ACQUIRE32)) {
                 ret_val = -EBUSY;
                 goto ioctl_out;
diff --git a/drivers/char/agp/efficeon-agp.c b/drivers/char/agp/efficeon-agp.c
index cac0009cebc1..8ca6f262ef85 100644
--- a/drivers/char/agp/efficeon-agp.c
+++ b/drivers/char/agp/efficeon-agp.c
@@ -249,9 +249,9 @@ static int efficeon_insert_memory(struct agp_memory * mem, off_t pg_start, int t
         if (type != 0 || mem->type != 0)
                 return -EINVAL;
 
-        if (mem->is_flushed == FALSE) {
+        if (!mem->is_flushed) {
                 global_cache_flush();
-                mem->is_flushed = TRUE;
+                mem->is_flushed = true;
         }
 
         last_page = NULL;
@@ -329,7 +329,7 @@ static const struct agp_bridge_driver efficeon_driver = {
         .free_gatt_table        = efficeon_free_gatt_table,
         .insert_memory          = efficeon_insert_memory,
         .remove_memory          = efficeon_remove_memory,
-        .cant_use_aperture      = 0,    // 1 might be faster?
+        .cant_use_aperture      = false,        // true might be faster?
 
         // Generic
         .alloc_by_type          = agp_generic_alloc_by_type,
diff --git a/drivers/char/agp/frontend.c b/drivers/char/agp/frontend.c
index 857b26227d87..e6cb1ab03e06 100644
--- a/drivers/char/agp/frontend.c
+++ b/drivers/char/agp/frontend.c
@@ -395,7 +395,7 @@ static int agp_remove_controller(struct agp_controller *controller)
 
         if (agp_fe.current_controller == controller) {
                 agp_fe.current_controller = NULL;
-                agp_fe.backend_acquired = FALSE;
+                agp_fe.backend_acquired = false;
                 agp_backend_release(agp_bridge);
         }
         kfree(controller);
@@ -443,7 +443,7 @@ static void agp_controller_release_current(struct agp_controller *controller,
         }
 
         agp_fe.current_controller = NULL;
-        agp_fe.used_by_controller = FALSE;
+        agp_fe.used_by_controller = false;
         agp_backend_release(agp_bridge);
 }
 
@@ -573,7 +573,7 @@ static int agp_mmap(struct file *file, struct vm_area_struct *vma)
 
         mutex_lock(&(agp_fe.agp_mutex));
 
-        if (agp_fe.backend_acquired != TRUE)
+        if (agp_fe.backend_acquired != true)
                 goto out_eperm;
 
         if (!(test_bit(AGP_FF_IS_VALID, &priv->access_flags)))
@@ -768,7 +768,7 @@ int agpioc_acquire_wrap(struct agp_file_private *priv)
 
         atomic_inc(&agp_bridge->agp_in_use);
 
-        agp_fe.backend_acquired = TRUE;
+        agp_fe.backend_acquired = true;
 
         controller = agp_find_controller_by_pid(priv->my_pid);
 
@@ -778,7 +778,7 @@ int agpioc_acquire_wrap(struct agp_file_private *priv)
                 controller = agp_create_controller(priv->my_pid);
 
                 if (controller == NULL) {
-                        agp_fe.backend_acquired = FALSE;
+                        agp_fe.backend_acquired = false;
                         agp_backend_release(agp_bridge);
                         return -ENOMEM;
                 }
@@ -981,7 +981,7 @@ static long agp_ioctl(struct file *file,
                 ret_val = -EINVAL;
                 goto ioctl_out;
         }
-        if ((agp_fe.backend_acquired != TRUE) &&
+        if ((agp_fe.backend_acquired != true) &&
             (cmd != AGPIOC_ACQUIRE)) {
                 ret_val = -EBUSY;
                 goto ioctl_out;
diff --git a/drivers/char/agp/generic.c b/drivers/char/agp/generic.c
index 7fc0c99a3a58..564daaa6c7d0 100644
--- a/drivers/char/agp/generic.c
+++ b/drivers/char/agp/generic.c
@@ -96,13 +96,13 @@ EXPORT_SYMBOL(agp_flush_chipset);
 void agp_alloc_page_array(size_t size, struct agp_memory *mem)
 {
         mem->memory = NULL;
-        mem->vmalloc_flag = 0;
+        mem->vmalloc_flag = false;
 
         if (size <= 2*PAGE_SIZE)
                 mem->memory = kmalloc(size, GFP_KERNEL | __GFP_NORETRY);
         if (mem->memory == NULL) {
                 mem->memory = vmalloc(size);
-                mem->vmalloc_flag = 1;
+                mem->vmalloc_flag = true;
         }
 }
 EXPORT_SYMBOL(agp_alloc_page_array);
@@ -188,7 +188,7 @@ void agp_free_memory(struct agp_memory *curr)
         if (curr == NULL)
                 return;
 
-        if (curr->is_bound == TRUE)
+        if (curr->is_bound)
                 agp_unbind_memory(curr);
 
         if (curr->type >= AGP_USER_TYPES) {
@@ -202,10 +202,13 @@ void agp_free_memory(struct agp_memory *curr)
         }
         if (curr->page_count != 0) {
                 for (i = 0; i < curr->page_count; i++) {
-                        curr->bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[i]), AGP_PAGE_DESTROY_UNMAP);
+                        curr->memory[i] = (unsigned long)gart_to_virt(curr->memory[i]);
+                        curr->bridge->driver->agp_destroy_page((void *)curr->memory[i],
+                                                               AGP_PAGE_DESTROY_UNMAP);
                 }
                 for (i = 0; i < curr->page_count; i++) {
-                        curr->bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[i]), AGP_PAGE_DESTROY_FREE);
+                        curr->bridge->driver->agp_destroy_page((void *)curr->memory[i],
+                                                               AGP_PAGE_DESTROY_FREE);
                 }
         }
         agp_free_key(curr->key);
@@ -411,20 +414,20 @@ int agp_bind_memory(struct agp_memory *curr, off_t pg_start)
         if (curr == NULL)
                 return -EINVAL;
 
-        if (curr->is_bound == TRUE) {
+        if (curr->is_bound) {
                 printk(KERN_INFO PFX "memory %p is already bound!\n", curr);
                 return -EINVAL;
         }
-        if (curr->is_flushed == FALSE) {
+        if (!curr->is_flushed) {
                 curr->bridge->driver->cache_flush();
-                curr->is_flushed = TRUE;
+                curr->is_flushed = true;
         }
         ret_val = curr->bridge->driver->insert_memory(curr, pg_start, curr->type);
 
         if (ret_val != 0)
                 return ret_val;
 
-        curr->is_bound = TRUE;
+        curr->is_bound = true;
         curr->pg_start = pg_start;
         return 0;
 }
@@ -446,7 +449,7 @@ int agp_unbind_memory(struct agp_memory *curr)
         if (curr == NULL)
                 return -EINVAL;
 
-        if (curr->is_bound != TRUE) {
+        if (!curr->is_bound) {
                 printk(KERN_INFO PFX "memory %p was not bound!\n", curr);
                 return -EINVAL;
         }
@@ -456,7 +459,7 @@ int agp_unbind_memory(struct agp_memory *curr)
         if (ret_val != 0)
                 return ret_val;
 
-        curr->is_bound = FALSE;
+        curr->is_bound = false;
         curr->pg_start = 0;
         return 0;
 }
@@ -754,7 +757,7 @@ u32 agp_collect_device_status(struct agp_bridge_data *bridge, u32 requested_mode
 EXPORT_SYMBOL(agp_collect_device_status);
 
 
-void agp_device_command(u32 bridge_agpstat, int agp_v3)
+void agp_device_command(u32 bridge_agpstat, bool agp_v3)
 {
         struct pci_dev *device = NULL;
         int mode;
@@ -818,7 +821,7 @@ void agp_generic_enable(struct agp_bridge_data *bridge, u32 requested_mode)
                         /* If we have 3.5, we can do the isoch stuff. */
                         if (bridge->minor_version >= 5)
                                 agp_3_5_enable(bridge);
-                        agp_device_command(bridge_agpstat, TRUE);
+                        agp_device_command(bridge_agpstat, true);
                         return;
                 } else {
                     /* Disable calibration cycle in RX91<1> when not in AGP3.0 mode of operation.*/
@@ -835,7 +838,7 @@ void agp_generic_enable(struct agp_bridge_data *bridge, u32 requested_mode)
         }
 
         /* AGP v<3 */
-        agp_device_command(bridge_agpstat, FALSE);
+        agp_device_command(bridge_agpstat, false);
 }
 EXPORT_SYMBOL(agp_generic_enable);
 
@@ -1083,9 +1086,9 @@ int agp_generic_insert_memory(struct agp_memory * mem, off_t pg_start, int type)
                 j++;
         }
 
-        if (mem->is_flushed == FALSE) {
+        if (!mem->is_flushed) {
                 bridge->driver->cache_flush();
-                mem->is_flushed = TRUE;
+                mem->is_flushed = true;
         }
 
         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
diff --git a/drivers/char/agp/hp-agp.c b/drivers/char/agp/hp-agp.c
index cbb0444467ba..80d7317f85c9 100644
--- a/drivers/char/agp/hp-agp.c
+++ b/drivers/char/agp/hp-agp.c
@@ -353,9 +353,9 @@ hp_zx1_insert_memory (struct agp_memory *mem, off_t pg_start, int type)
                 j++;
         }
 
-        if (mem->is_flushed == FALSE) {
+        if (!mem->is_flushed) {
                 global_cache_flush();
-                mem->is_flushed = TRUE;
+                mem->is_flushed = true;
         }
 
         for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
@@ -437,7 +437,7 @@ const struct agp_bridge_driver hp_zx1_driver = {
         .agp_alloc_page         = agp_generic_alloc_page,
         .agp_destroy_page       = agp_generic_destroy_page,
         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
-        .cant_use_aperture      = 1,
+        .cant_use_aperture      = true,
 };
 
 static int __init
diff --git a/drivers/char/agp/i460-agp.c b/drivers/char/agp/i460-agp.c
index 76f581c85a7d..e587eebebc67 100644
--- a/drivers/char/agp/i460-agp.c
+++ b/drivers/char/agp/i460-agp.c
@@ -580,7 +580,7 @@ const struct agp_bridge_driver intel_i460_driver = {
         .alloc_by_type          = agp_generic_alloc_by_type,
         .free_by_type           = agp_generic_free_by_type,
         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
-        .cant_use_aperture      = 1,
+        .cant_use_aperture      = true,
 };
 
 static int __devinit agp_intel_i460_probe(struct pci_dev *pdev,
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index eeea50a1d22a..df702642ab8f 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -34,6 +34,12 @@
 #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
 #define PCI_DEVICE_ID_INTEL_IGD_HB          0x2A40
 #define PCI_DEVICE_ID_INTEL_IGD_IG          0x2A42
+#define PCI_DEVICE_ID_INTEL_IGD_E_HB        0x2E00
+#define PCI_DEVICE_ID_INTEL_IGD_E_IG        0x2E02
+#define PCI_DEVICE_ID_INTEL_Q45_HB          0x2E10
+#define PCI_DEVICE_ID_INTEL_Q45_IG          0x2E12
+#define PCI_DEVICE_ID_INTEL_G45_HB          0x2E20
+#define PCI_DEVICE_ID_INTEL_G45_IG          0x2E22
 
 /* cover 915 and 945 variants */
 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
@@ -55,6 +61,10 @@
                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
 
+#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
+                agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
+                agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB)
+
 extern int agp_memory_reserved;
 
 
@@ -80,8 +90,13 @@ extern int agp_memory_reserved;
 #define I915_PTEADDR    0x1C
 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
-#define G33_GMCH_GMS_STOLEN_128M       (0x8 << 4)
-#define G33_GMCH_GMS_STOLEN_256M       (0x9 << 4)
+#define G33_GMCH_GMS_STOLEN_128M        (0x8 << 4)
+#define G33_GMCH_GMS_STOLEN_256M        (0x9 << 4)
+#define INTEL_GMCH_GMS_STOLEN_96M       (0xa << 4)
+#define INTEL_GMCH_GMS_STOLEN_160M      (0xb << 4)
+#define INTEL_GMCH_GMS_STOLEN_224M      (0xc << 4)
+#define INTEL_GMCH_GMS_STOLEN_352M      (0xd << 4)
+
 #define I915_IFPADDR    0x60
 
 /* Intel 965G registers */
@@ -325,7 +340,7 @@ static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 out:
         ret = 0;
 out_err:
-        mem->is_flushed = 1;
+        mem->is_flushed = true;
         return ret;
 }
 
@@ -418,9 +433,11 @@ static void intel_i810_free_by_type(struct agp_memory *curr)
                 if (curr->page_count == 4)
                         i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
                 else {
-                        agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
+                        void *va = gart_to_virt(curr->memory[0]);
+
+                        agp_bridge->driver->agp_destroy_page(va,
                                                              AGP_PAGE_DESTROY_UNMAP);
-                        agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
+                        agp_bridge->driver->agp_destroy_page(va,
                                                              AGP_PAGE_DESTROY_FREE);
                 }
                 agp_free_page_array(curr);
@@ -504,6 +521,10 @@ static void intel_i830_init_gtt_entries(void)
                         size = 512;
                 }
                 size += 4;
+        } else if (IS_G4X) {
+                /* On 4 series hardware, GTT stolen is separate from graphics
+                 * stolen, ignore it in stolen gtt entries counting */
+                size = 0;
         } else {
                 /* On previous hardware, the GTT size was just what was
                  * required to map the aperture.
@@ -552,30 +573,54 @@ static void intel_i830_init_gtt_entries(void)
                         break;
                 case I915_GMCH_GMS_STOLEN_48M:
                         /* Check it's really I915G */
-                        if (IS_I915 || IS_I965 || IS_G33)
+                        if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
                                 gtt_entries = MB(48) - KB(size);
                         else
                                 gtt_entries = 0;
                         break;
                 case I915_GMCH_GMS_STOLEN_64M:
                         /* Check it's really I915G */
-                        if (IS_I915 || IS_I965 || IS_G33)
+                        if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
                                 gtt_entries = MB(64) - KB(size);
                         else
                                 gtt_entries = 0;
                         break;
                 case G33_GMCH_GMS_STOLEN_128M:
-                        if (IS_G33)
+                        if (IS_G33 || IS_I965 || IS_G4X)
                                 gtt_entries = MB(128) - KB(size);
                         else
                                 gtt_entries = 0;
                         break;
                 case G33_GMCH_GMS_STOLEN_256M:
-                        if (IS_G33)
+                        if (IS_G33 || IS_I965 || IS_G4X)
                                 gtt_entries = MB(256) - KB(size);
                         else
                                 gtt_entries = 0;
                         break;
+                case INTEL_GMCH_GMS_STOLEN_96M:
+                        if (IS_I965 || IS_G4X)
+                                gtt_entries = MB(96) - KB(size);
+                        else
+                                gtt_entries = 0;
+                        break;
+                case INTEL_GMCH_GMS_STOLEN_160M:
+                        if (IS_I965 || IS_G4X)
+                                gtt_entries = MB(160) - KB(size);
+                        else
+                                gtt_entries = 0;
+                        break;
+                case INTEL_GMCH_GMS_STOLEN_224M:
+                        if (IS_I965 || IS_G4X)
+                                gtt_entries = MB(224) - KB(size);
+                        else
+                                gtt_entries = 0;
+                        break;
+                case INTEL_GMCH_GMS_STOLEN_352M:
+                        if (IS_I965 || IS_G4X)
+                                gtt_entries = MB(352) - KB(size);
+                        else
+                                gtt_entries = 0;
+                        break;
                 default:
                         gtt_entries = 0;
                         break;
@@ -793,7 +838,7 @@ static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
 out:
         ret = 0;
 out_err:
-        mem->is_flushed = 1;
+        mem->is_flushed = true;
         return ret;
 }
 
@@ -903,7 +948,7 @@ static void intel_i9xx_setup_flush(void)
         intel_private.ifp_resource.flags = IORESOURCE_MEM;
 
         /* Setup chipset flush for 915 */
-        if (IS_I965 || IS_G33) {
+        if (IS_I965 || IS_G33 || IS_G4X) {
                 intel_i965_g33_setup_chipset_flush();
         } else {
                 intel_i915_setup_chipset_flush();
@@ -1020,7 +1065,7 @@ static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
  out:
         ret = 0;
  out_err:
-        mem->is_flushed = 1;
+        mem->is_flushed = true;
         return ret;
 }
 
@@ -1134,53 +1179,64 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
         return addr | bridge->driver->masks[type].mask;
 }
 
+static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
+{
+        switch (agp_bridge->dev->device) {
+        case PCI_DEVICE_ID_INTEL_IGD_HB:
+        case PCI_DEVICE_ID_INTEL_IGD_E_HB:
+        case PCI_DEVICE_ID_INTEL_Q45_HB:
+        case PCI_DEVICE_ID_INTEL_G45_HB:
+                *gtt_offset = *gtt_size = MB(2);
+                break;
+        default:
+                *gtt_offset = *gtt_size = KB(512);
+        }
+}
+
 /* The intel i965 automatically initializes the agp aperture during POST.
  * Use the memory already set aside for in the GTT.
  */
 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
 {
-       int page_order;
-       struct aper_size_info_fixed *size;
-       int num_entries;
-       u32 temp;
-       int gtt_offset, gtt_size;
+        int page_order;
+        struct aper_size_info_fixed *size;
+        int num_entries;
+        u32 temp;
+        int gtt_offset, gtt_size;
 
-       size = agp_bridge->current_size;
-       page_order = size->page_order;
-       num_entries = size->num_entries;
-       agp_bridge->gatt_table_real = NULL;
+        size = agp_bridge->current_size;
+        page_order = size->page_order;
+        num_entries = size->num_entries;
+        agp_bridge->gatt_table_real = NULL;
 
-       pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
+        pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
 
-       temp &= 0xfff00000;
+        temp &= 0xfff00000;
 
-       if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB)
-               gtt_offset = gtt_size = MB(2);
-       else
-               gtt_offset = gtt_size = KB(512);
+        intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
 
-       intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
+        intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
 
-       if (!intel_private.gtt)
-               return -ENOMEM;
+        if (!intel_private.gtt)
+                return -ENOMEM;
 
-       intel_private.registers = ioremap(temp, 128 * 4096);
-       if (!intel_private.registers) {
+        intel_private.registers = ioremap(temp, 128 * 4096);
+        if (!intel_private.registers) {
                 iounmap(intel_private.gtt);
                 return -ENOMEM;
         }
 
-       temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
-       global_cache_flush();   /* FIXME: ? */
+        temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
+        global_cache_flush();   /* FIXME: ? */
 
-       /* we have to call this as early as possible after the MMIO base address is known */
-       intel_i830_init_gtt_entries();
+        /* we have to call this as early as possible after the MMIO base address is known */
+        intel_i830_init_gtt_entries();
 
-       agp_bridge->gatt_table = NULL;
+        agp_bridge->gatt_table = NULL;
 
-       agp_bridge->gatt_bus_addr = temp;
+        agp_bridge->gatt_bus_addr = temp;
 
-       return 0;
+        return 0;
 }
 
 
@@ -1656,7 +1712,7 @@ static const struct agp_bridge_driver intel_810_driver = {
         .aperture_sizes         = intel_i810_sizes,
         .size_type              = FIXED_APER_SIZE,
         .num_aperture_sizes     = 2,
-        .needs_scratch_page     = TRUE,
+        .needs_scratch_page     = true,
         .configure              = intel_i810_configure,
         .fetch_size             = intel_i810_fetch_size,
         .cleanup                = intel_i810_cleanup,
@@ -1697,7 +1753,7 @@ static const struct agp_bridge_driver intel_815_driver = {
         .free_by_type           = agp_generic_free_by_type,
         .agp_alloc_page         = agp_generic_alloc_page,
         .agp_destroy_page       = agp_generic_destroy_page,
-        .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
+        .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
 };
 
 static const struct agp_bridge_driver intel_830_driver = {
@@ -1705,7 +1761,7 @@ static const struct agp_bridge_driver intel_830_driver = {
         .aperture_sizes         = intel_i830_sizes,
         .size_type              = FIXED_APER_SIZE,
         .num_aperture_sizes     = 4,
-        .needs_scratch_page     = TRUE,
+        .needs_scratch_page     = true,
         .configure              = intel_i830_configure,
         .fetch_size             = intel_i830_fetch_size,
         .cleanup                = intel_i830_cleanup,
@@ -1876,7 +1932,7 @@ static const struct agp_bridge_driver intel_915_driver = {
         .aperture_sizes         = intel_i830_sizes,
         .size_type              = FIXED_APER_SIZE,
         .num_aperture_sizes     = 4,
-        .needs_scratch_page     = TRUE,
+        .needs_scratch_page     = true,
         .configure              = intel_i915_configure,
         .fetch_size             = intel_i9xx_fetch_size,
         .cleanup                = intel_i915_cleanup,
@@ -1898,28 +1954,28 @@ static const struct agp_bridge_driver intel_915_driver = {
 };
 
 static const struct agp_bridge_driver intel_i965_driver = {
-       .owner                  = THIS_MODULE,
-       .aperture_sizes         = intel_i830_sizes,
-       .size_type              = FIXED_APER_SIZE,
-       .num_aperture_sizes     = 4,
-       .needs_scratch_page     = TRUE,
-       .configure              = intel_i915_configure,
-       .fetch_size             = intel_i9xx_fetch_size,
-       .cleanup                = intel_i915_cleanup,
-       .tlb_flush              = intel_i810_tlbflush,
-       .mask_memory            = intel_i965_mask_memory,
-       .masks                  = intel_i810_masks,
-       .agp_enable             = intel_i810_agp_enable,
-       .cache_flush            = global_cache_flush,
-       .create_gatt_table      = intel_i965_create_gatt_table,
-       .free_gatt_table        = intel_i830_free_gatt_table,
-       .insert_memory          = intel_i915_insert_entries,
-       .remove_memory          = intel_i915_remove_entries,
-       .alloc_by_type          = intel_i830_alloc_by_type,
-       .free_by_type           = intel_i810_free_by_type,
-       .agp_alloc_page         = agp_generic_alloc_page,
-       .agp_destroy_page       = agp_generic_destroy_page,
-       .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
+        .owner                  = THIS_MODULE,
+        .aperture_sizes         = intel_i830_sizes,
+        .size_type              = FIXED_APER_SIZE,
+        .num_aperture_sizes     = 4,
+        .needs_scratch_page     = true,
+        .configure              = intel_i915_configure,
+        .fetch_size             = intel_i9xx_fetch_size,
+        .cleanup                = intel_i915_cleanup,
+        .tlb_flush              = intel_i810_tlbflush,
+        .mask_memory            = intel_i965_mask_memory,
+        .masks                  = intel_i810_masks,
+        .agp_enable             = intel_i810_agp_enable,
+        .cache_flush            = global_cache_flush,
+        .create_gatt_table      = intel_i965_create_gatt_table,
+        .free_gatt_table        = intel_i830_free_gatt_table,
+        .insert_memory          = intel_i915_insert_entries,
+        .remove_memory          = intel_i915_remove_entries,
+        .alloc_by_type          = intel_i830_alloc_by_type,
+        .free_by_type           = intel_i810_free_by_type,
+        .agp_alloc_page         = agp_generic_alloc_page,
+        .agp_destroy_page       = agp_generic_destroy_page,
+        .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
         .chipset_flush          = intel_i915_chipset_flush,
 };
 
@@ -1948,28 +2004,28 @@ static const struct agp_bridge_driver intel_7505_driver = {
 };
 
 static const struct agp_bridge_driver intel_g33_driver = {
-        .owner                  = THIS_MODULE,
-        .aperture_sizes         = intel_i830_sizes,
-        .size_type              = FIXED_APER_SIZE,
-        .num_aperture_sizes     = 4,
-        .needs_scratch_page     = TRUE,
-        .configure              = intel_i915_configure,
-        .fetch_size             = intel_i9xx_fetch_size,
-        .cleanup                = intel_i915_cleanup,
-        .tlb_flush              = intel_i810_tlbflush,
-        .mask_memory            = intel_i965_mask_memory,
-        .masks                  = intel_i810_masks,
-        .agp_enable             = intel_i810_agp_enable,
-        .cache_flush            = global_cache_flush,
-        .create_gatt_table      = intel_i915_create_gatt_table,
-        .free_gatt_table        = intel_i830_free_gatt_table,
-        .insert_memory          = intel_i915_insert_entries,
-        .remove_memory          = intel_i915_remove_entries,
-        .alloc_by_type          = intel_i830_alloc_by_type,
-        .free_by_type           = intel_i810_free_by_type,
-        .agp_alloc_page         = agp_generic_alloc_page,
-        .agp_destroy_page       = agp_generic_destroy_page,
-        .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
+        .owner                  = THIS_MODULE,
+        .aperture_sizes         = intel_i830_sizes,
+        .size_type              = FIXED_APER_SIZE,
+        .num_aperture_sizes     = 4,
+        .needs_scratch_page     = true,
+        .configure              = intel_i915_configure,
+        .fetch_size             = intel_i9xx_fetch_size,
+        .cleanup                = intel_i915_cleanup,
+        .tlb_flush              = intel_i810_tlbflush,
+        .mask_memory            = intel_i965_mask_memory,
+        .masks                  = intel_i810_masks,
+        .agp_enable             = intel_i810_agp_enable,
+        .cache_flush            = global_cache_flush,
+        .create_gatt_table      = intel_i915_create_gatt_table,
+        .free_gatt_table        = intel_i830_free_gatt_table,
+        .insert_memory          = intel_i915_insert_entries,
+        .remove_memory          = intel_i915_remove_entries,
+        .alloc_by_type          = intel_i830_alloc_by_type,
+        .free_by_type           = intel_i810_free_by_type,
+        .agp_alloc_page         = agp_generic_alloc_page,
+        .agp_destroy_page       = agp_generic_destroy_page,
+        .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
         .chipset_flush          = intel_i915_chipset_flush,
 };
 
@@ -2063,6 +2119,12 @@ static const struct intel_driver_description {
                 NULL, &intel_g33_driver },
         { PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0,
             "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
+        { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
+            "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
+        { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
+            "Q45/Q43", NULL, &intel_i965_driver },
+        { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
+            "G45/G43", NULL, &intel_i965_driver },
         { 0, 0, 0, NULL, NULL, NULL }
 };
 
@@ -2254,6 +2316,9 @@ static struct pci_device_id agp_intel_pci_table[] = {
         ID(PCI_DEVICE_ID_INTEL_Q35_HB),
         ID(PCI_DEVICE_ID_INTEL_Q33_HB),
         ID(PCI_DEVICE_ID_INTEL_IGD_HB),
+        ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
+        ID(PCI_DEVICE_ID_INTEL_Q45_HB),
+        ID(PCI_DEVICE_ID_INTEL_G45_HB),
         { }
 };
 
diff --git a/drivers/char/agp/nvidia-agp.c b/drivers/char/agp/nvidia-agp.c
index 225ed2a53d45..eaceb61ba2dc 100644
--- a/drivers/char/agp/nvidia-agp.c
+++ b/drivers/char/agp/nvidia-agp.c
@@ -214,9 +214,9 @@ static int nvidia_insert_memory(struct agp_memory *mem, off_t pg_start, int type
                         return -EBUSY;
         }
 
-        if (mem->is_flushed == FALSE) {
+        if (!mem->is_flushed) {
                 global_cache_flush();
-                mem->is_flushed = TRUE;
+                mem->is_flushed = true;
         }
         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
                 writel(agp_bridge->driver->mask_memory(agp_bridge,
diff --git a/drivers/char/agp/parisc-agp.c b/drivers/char/agp/parisc-agp.c
index 2939e3570f9d..8c42dcc5958c 100644
--- a/drivers/char/agp/parisc-agp.c
+++ b/drivers/char/agp/parisc-agp.c
@@ -141,9 +141,9 @@ parisc_agp_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
                 j++;
         }
 
-        if (mem->is_flushed == FALSE) {
+        if (!mem->is_flushed) {
                 global_cache_flush();
-                mem->is_flushed = TRUE;
+                mem->is_flushed = true;
         }
 
         for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
@@ -226,7 +226,7 @@ static const struct agp_bridge_driver parisc_agp_driver = {
         .agp_alloc_page         = agp_generic_alloc_page,
         .agp_destroy_page       = agp_generic_destroy_page,
         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
-        .cant_use_aperture      = 1,
+        .cant_use_aperture      = true,
 };
 
 static int __init
diff --git a/drivers/char/agp/sgi-agp.c b/drivers/char/agp/sgi-agp.c
index 98cf8abb3e57..b972d83bb1b2 100644
--- a/drivers/char/agp/sgi-agp.c
+++ b/drivers/char/agp/sgi-agp.c
@@ -182,9 +182,9 @@ static int sgi_tioca_insert_memory(struct agp_memory *mem, off_t pg_start,
                 j++;
         }
 
-        if (mem->is_flushed == FALSE) {
+        if (!mem->is_flushed) {
                 bridge->driver->cache_flush();
-                mem->is_flushed = TRUE;
+                mem->is_flushed = true;
         }
 
         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
@@ -264,8 +264,8 @@ const struct agp_bridge_driver sgi_tioca_driver = {
         .agp_alloc_page = sgi_tioca_alloc_page,
         .agp_destroy_page = agp_generic_destroy_page,
         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
-        .cant_use_aperture = 1,
-        .needs_scratch_page = 0,
+        .cant_use_aperture = true,
+        .needs_scratch_page = false,
         .num_aperture_sizes = 1,
 };
 
diff --git a/drivers/char/agp/sworks-agp.c b/drivers/char/agp/sworks-agp.c
index e08934e58f32..0e054c134490 100644
--- a/drivers/char/agp/sworks-agp.c
+++ b/drivers/char/agp/sworks-agp.c
@@ -339,9 +339,9 @@ static int serverworks_insert_memory(struct agp_memory *mem,
                 j++;
         }
 
-        if (mem->is_flushed == FALSE) {
+        if (!mem->is_flushed) {
                 global_cache_flush();
-                mem->is_flushed = TRUE;
+                mem->is_flushed = true;
         }
 
         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
@@ -412,7 +412,7 @@ static void serverworks_agp_enable(struct agp_bridge_data *bridge, u32 mode)
                                bridge->capndx + PCI_AGP_COMMAND,
                                command);
 
-        agp_device_command(command, 0);
+        agp_device_command(command, false);
 }
 
 static const struct agp_bridge_driver sworks_driver = {
diff --git a/drivers/char/agp/uninorth-agp.c b/drivers/char/agp/uninorth-agp.c
index 42c0a600b1ac..d2fa3cfca02a 100644
--- a/drivers/char/agp/uninorth-agp.c
+++ b/drivers/char/agp/uninorth-agp.c
@@ -281,10 +281,10 @@ static void uninorth_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 
         if (uninorth_rev >= 0x30) {
                 /* This is an AGP V3 */
-                agp_device_command(command, (status & AGPSTAT_MODE_3_0));
+                agp_device_command(command, (status & AGPSTAT_MODE_3_0) != 0);
         } else {
                 /* AGP V2 */
-                agp_device_command(command, 0);
+                agp_device_command(command, false);
         }
 
         uninorth_tlbflush(NULL);
@@ -511,7 +511,7 @@ const struct agp_bridge_driver uninorth_agp_driver = {
         .agp_alloc_page         = agp_generic_alloc_page,
         .agp_destroy_page       = agp_generic_destroy_page,
         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
-        .cant_use_aperture      = 1,
+        .cant_use_aperture      = true,
 };
 
 const struct agp_bridge_driver u3_agp_driver = {
@@ -536,8 +536,8 @@ const struct agp_bridge_driver u3_agp_driver = {
         .agp_alloc_page         = agp_generic_alloc_page,
         .agp_destroy_page       = agp_generic_destroy_page,
         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
-        .cant_use_aperture      = 1,
-        .needs_scratch_page     = 1,
+        .cant_use_aperture      = true,
+        .needs_scratch_page     = true,
 };
 
 static struct agp_device_ids uninorth_agp_device_ids[] __devinitdata = {
diff --git a/drivers/char/agp/via-agp.c b/drivers/char/agp/via-agp.c
index 0ecc54d327bc..7b36476dff41 100644
--- a/drivers/char/agp/via-agp.c
+++ b/drivers/char/agp/via-agp.c
@@ -389,11 +389,20 @@ static struct agp_device_ids via_agp_device_ids[] __devinitdata =
                 .device_id  = PCI_DEVICE_ID_VIA_VT3324,
                 .chipset_name   = "CX700",
         },
-        /* VT3336 */
+        /* VT3336 - this is a chipset for AMD Athlon/K8 CPU. Due to K8's unique
+         * architecture, the AGP resource and behavior are different from
+         * the traditional AGP which resides only in chipset. AGP is used
+         * by 3D driver which wasn't available for the VT3336 and VT3364
+         * generation until now.  Unfortunately, by testing, VT3364 works
+         * but VT3336 doesn't. - explaination from via, just leave this as
+         * as a placeholder to avoid future patches adding it back in.
+         */
+#if 0
         {
                 .device_id  = PCI_DEVICE_ID_VIA_VT3336,
                 .chipset_name   = "VT3336",
         },
+#endif
         /* P4M890 */
         {
                 .device_id  = PCI_DEVICE_ID_VIA_P4M890,
@@ -546,8 +555,8 @@ static const struct pci_device_id agp_via_pci_table[] = {
         ID(PCI_DEVICE_ID_VIA_3296_0),
         ID(PCI_DEVICE_ID_VIA_P4M800CE),
         ID(PCI_DEVICE_ID_VIA_VT3324),
-        ID(PCI_DEVICE_ID_VIA_VT3336),
         ID(PCI_DEVICE_ID_VIA_P4M890),
+        ID(PCI_DEVICE_ID_VIA_VT3364),
         { }
 };
 
diff --git a/drivers/char/drm/ati_pcigart.c b/drivers/char/drm/ati_pcigart.c
index b710426bab3e..c533d0c9ec61 100644
--- a/drivers/char/drm/ati_pcigart.c
+++ b/drivers/char/drm/ati_pcigart.c
@@ -76,7 +76,7 @@ int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info
                 for (i = 0; i < pages; i++) {
                         if (!entry->busaddr[i])
                                 break;
-                        pci_unmap_single(dev->pdev, entry->busaddr[i],
+                        pci_unmap_page(dev->pdev, entry->busaddr[i],
                                          PAGE_SIZE, PCI_DMA_TODEVICE);
                 }
 
@@ -137,10 +137,8 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga
 
         for (i = 0; i < pages; i++) {
                 /* we need to support large memory configurations */
-                entry->busaddr[i] = pci_map_single(dev->pdev,
-                                                   page_address(entry->
-                                                                pagelist[i]),
-                                                   PAGE_SIZE, PCI_DMA_TODEVICE);
+                entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i],
+                                                 0, PAGE_SIZE, PCI_DMA_TODEVICE);
                 if (entry->busaddr[i] == 0) {
                         DRM_ERROR("unable to map PCIGART pages!\n");
                         drm_ati_pcigart_cleanup(dev, gart_info);
diff --git a/drivers/char/drm/drm.h b/drivers/char/drm/drm.h
index 3a05c6d5ebe1..38d3c6b8276a 100644
--- a/drivers/char/drm/drm.h
+++ b/drivers/char/drm/drm.h
@@ -628,7 +628,7 @@ struct drm_set_version {
 #define DRM_IOCTL_AGP_BIND              DRM_IOW( 0x36, struct drm_agp_binding)
 #define DRM_IOCTL_AGP_UNBIND            DRM_IOW( 0x37, struct drm_agp_binding)
 
-#define DRM_IOCTL_SG_ALLOC              DRM_IOW( 0x38, struct drm_scatter_gather)
+#define DRM_IOCTL_SG_ALLOC              DRM_IOWR(0x38, struct drm_scatter_gather)
 #define DRM_IOCTL_SG_FREE               DRM_IOW( 0x39, struct drm_scatter_gather)
 
 #define DRM_IOCTL_WAIT_VBLANK           DRM_IOWR(0x3a, union drm_wait_vblank)
diff --git a/drivers/char/drm/drm_drv.c b/drivers/char/drm/drm_drv.c
index fc54140551a7..564138714bb5 100644
--- a/drivers/char/drm/drm_drv.c
+++ b/drivers/char/drm/drm_drv.c
@@ -470,17 +470,18 @@ int drm_ioctl(struct inode *inode, struct file *filp,
         if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) &&
             (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls))
                 ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE];
-        else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE))
+        else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) {
                 ioctl = &drm_ioctls[nr];
-        else
+                cmd = ioctl->cmd;
+        } else
                 goto err_i1;
 
+        /* Do not trust userspace, use our own definition */
         func = ioctl->func;
         /* is there a local override? */
         if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl)
                 func = dev->driver->dma_ioctl;
 
-
         if (!func) {
                 DRM_DEBUG("no function\n");
                 retcode = -EINVAL;
diff --git a/drivers/char/drm/drm_pciids.h b/drivers/char/drm/drm_pciids.h
index a6a499f97e22..135bd19499fc 100644
--- a/drivers/char/drm/drm_pciids.h
+++ b/drivers/char/drm/drm_pciids.h
@@ -103,20 +103,18 @@
         {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
         {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \
         {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
-        {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
-        {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
-        {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
-        {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+        {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+        {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+        {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+        {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
         {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
         {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
         {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
         {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
         {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
         {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
-        {0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
-        {0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
-        {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
-        {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+        {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+        {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
         {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
         {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
         {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
@@ -411,4 +409,7 @@
         {0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
         {0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
         {0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
+        {0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
         {0, 0, 0}
diff --git a/drivers/char/drm/i915_drv.h b/drivers/char/drm/i915_drv.h
index 1b20f7c0639c..d7326d92a237 100644
--- a/drivers/char/drm/i915_drv.h
+++ b/drivers/char/drm/i915_drv.h
@@ -1112,12 +1112,19 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
                        (dev)->pci_device == 0x29A2 || \
                        (dev)->pci_device == 0x2A02 || \
                        (dev)->pci_device == 0x2A12 || \
-                       (dev)->pci_device == 0x2A42)
+                       (dev)->pci_device == 0x2A42 || \
+                       (dev)->pci_device == 0x2E02 || \
+                       (dev)->pci_device == 0x2E12 || \
+                       (dev)->pci_device == 0x2E22)
 
 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
 
 #define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42)
 
+#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
+                     (dev)->pci_device == 0x2E12 || \
+                     (dev)->pci_device == 0x2E22)
+
 #define IS_G33(dev)    ((dev)->pci_device == 0x29C2 ||  \
                         (dev)->pci_device == 0x29B2 ||  \
                         (dev)->pci_device == 0x29D2)
@@ -1128,7 +1135,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
                         IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev))
 
-#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev))
+#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev) || IS_G4X(dev))
 
 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
 
diff --git a/drivers/char/drm/r300_cmdbuf.c b/drivers/char/drm/r300_cmdbuf.c
index f535812e4057..702df45320f7 100644
--- a/drivers/char/drm/r300_cmdbuf.c
+++ b/drivers/char/drm/r300_cmdbuf.c
@@ -189,18 +189,12 @@ void r300_init_reg_flags(struct drm_device *dev)
         ADD_RANGE(R300_RE_CULL_CNTL, 1);
         ADD_RANGE(0x42C0, 2);
         ADD_RANGE(R300_RS_CNTL_0, 2);
-        ADD_RANGE(R300_RS_INTERP_0, 8);
-        ADD_RANGE(R300_RS_ROUTE_0, 8);
-        ADD_RANGE(0x43A4, 2);
+
+        ADD_RANGE(R300_SC_HYPERZ, 2);
         ADD_RANGE(0x43E8, 1);
-        ADD_RANGE(R300_PFS_CNTL_0, 3);
-        ADD_RANGE(R300_PFS_NODE_0, 4);
-        ADD_RANGE(R300_PFS_TEXI_0, 64);
+
         ADD_RANGE(0x46A4, 5);
-        ADD_RANGE(R300_PFS_INSTR0_0, 64);
-        ADD_RANGE(R300_PFS_INSTR1_0, 64);
-        ADD_RANGE(R300_PFS_INSTR2_0, 64);
-        ADD_RANGE(R300_PFS_INSTR3_0, 64);
+
         ADD_RANGE(R300_RE_FOG_STATE, 1);
         ADD_RANGE(R300_FOG_COLOR_R, 3);
         ADD_RANGE(R300_PP_ALPHA_TEST, 2);
@@ -215,14 +209,12 @@ void r300_init_reg_flags(struct drm_device *dev)
         ADD_RANGE(0x4E50, 9);
         ADD_RANGE(0x4E88, 1);
         ADD_RANGE(0x4EA0, 2);
-        ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3);
-        ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4);
-        ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET);    /* check offset */
-        ADD_RANGE(R300_RB3D_DEPTHPITCH, 1);
-        ADD_RANGE(0x4F28, 1);
-        ADD_RANGE(0x4F30, 2);
-        ADD_RANGE(0x4F44, 1);
-        ADD_RANGE(0x4F54, 1);
+        ADD_RANGE(R300_ZB_CNTL, 3);
+        ADD_RANGE(R300_ZB_FORMAT, 4);
+        ADD_RANGE_MARK(R300_ZB_DEPTHOFFSET, 1, MARK_CHECK_OFFSET);      /* check offset */
+        ADD_RANGE(R300_ZB_DEPTHPITCH, 1);
+        ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1);
+        ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13);
 
         ADD_RANGE(R300_TX_FILTER_0, 16);
         ADD_RANGE(R300_TX_FILTER1_0, 16);
@@ -235,13 +227,32 @@ void r300_init_reg_flags(struct drm_device *dev)
         ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
 
         /* Sporadic registers used as primitives are emitted */
-        ADD_RANGE(R300_RB3D_ZCACHE_CTLSTAT, 1);
+        ADD_RANGE(R300_ZB_ZCACHE_CTLSTAT, 1);
         ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
         ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
         ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
 
         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
-                ADD_RANGE(0x4074, 16);
+                ADD_RANGE(R500_VAP_INDEX_OFFSET, 1);
+                ADD_RANGE(R500_US_CONFIG, 2);
+                ADD_RANGE(R500_US_CODE_ADDR, 3);
+                ADD_RANGE(R500_US_FC_CTRL, 1);
+                ADD_RANGE(R500_RS_IP_0, 16);
+                ADD_RANGE(R500_RS_INST_0, 16);
+                ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2);
+                ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2);
+                ADD_RANGE(R500_ZB_FIFO_SIZE, 2);
+        } else {
+                ADD_RANGE(R300_PFS_CNTL_0, 3);
+                ADD_RANGE(R300_PFS_NODE_0, 4);
+                ADD_RANGE(R300_PFS_TEXI_0, 64);
+                ADD_RANGE(R300_PFS_INSTR0_0, 64);
+                ADD_RANGE(R300_PFS_INSTR1_0, 64);
+                ADD_RANGE(R300_PFS_INSTR2_0, 64);
+                ADD_RANGE(R300_PFS_INSTR3_0, 64);
+                ADD_RANGE(R300_RS_INTERP_0, 8);
+                ADD_RANGE(R300_RS_ROUTE_0, 8);
+
         }
 }
 
@@ -707,8 +718,9 @@ static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
         BEGIN_RING(6);
         OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
         OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A);
-        OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
-        OUT_RING(R300_RB3D_ZCACHE_UNKNOWN_03);
+        OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));
+        OUT_RING(R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE|
+                 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
         OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
         OUT_RING(0x0);
         ADVANCE_RING();
@@ -829,6 +841,54 @@ static int r300_scratch(drm_radeon_private_t *dev_priv,
 }
 
 /**
+ * Uploads user-supplied vertex program instructions or parameters onto
+ * the graphics card.
+ * Called by r300_do_cp_cmdbuf.
+ */
+static inline int r300_emit_r500fp(drm_radeon_private_t *dev_priv,
+                                       drm_radeon_kcmd_buffer_t *cmdbuf,
+                                       drm_r300_cmd_header_t header)
+{
+        int sz;
+        int addr;
+        int type;
+        int clamp;
+        int stride;
+        RING_LOCALS;
+
+        sz = header.r500fp.count;
+        /* address is 9 bits 0 - 8, bit 1 of flags is part of address */
+        addr = ((header.r500fp.adrhi_flags & 1) << 8) | header.r500fp.adrlo;
+
+        type = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
+        clamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
+
+        addr |= (type << 16);
+        addr |= (clamp << 17);
+
+        stride = type ? 4 : 6;
+
+        DRM_DEBUG("r500fp %d %d type: %d\n", sz, addr, type);
+        if (!sz)
+                return 0;
+        if (sz * stride * 4 > cmdbuf->bufsz)
+                return -EINVAL;
+
+        BEGIN_RING(3 + sz * stride);
+        OUT_RING_REG(R500_GA_US_VECTOR_INDEX, addr);
+        OUT_RING(CP_PACKET0_TABLE(R500_GA_US_VECTOR_DATA, sz * stride - 1));
+        OUT_RING_TABLE((int *)cmdbuf->buf, sz * stride);
+
+        ADVANCE_RING();
+
+        cmdbuf->buf += sz * stride * 4;
+        cmdbuf->bufsz -= sz * stride * 4;
+
+        return 0;
+}
+
+
+/**
  * Parses and validates a user-supplied command buffer and emits appropriate
  * commands on the DMA ring buffer.
  * Called by the ioctl handler function radeon_cp_cmdbuf.
@@ -963,6 +1023,19 @@ int r300_do_cp_cmdbuf(struct drm_device *dev,
                         }
                         break;
 
+                case R300_CMD_R500FP:
+                        if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
+                                DRM_ERROR("Calling r500 command on r300 card\n");
+                                ret = -EINVAL;
+                                goto cleanup;
+                        }
+                        DRM_DEBUG("R300_CMD_R500FP\n");
+                        ret = r300_emit_r500fp(dev_priv, cmdbuf, header);
+                        if (ret) {
+                                DRM_ERROR("r300_emit_r500fp failed\n");
+                                goto cleanup;
+                        }
+                        break;
                 default:
                         DRM_ERROR("bad cmd_type %i at %p\n",
                                   header.header.cmd_type,
diff --git a/drivers/char/drm/r300_reg.h b/drivers/char/drm/r300_reg.h
index 8f664af9c4a4..a6802f26afc4 100644
--- a/drivers/char/drm/r300_reg.h
+++ b/drivers/char/drm/r300_reg.h
@@ -702,6 +702,27 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #               define R300_RS_ROUTE_1_UNKNOWN11         (1 << 11)
 /* END: Rasterization / Interpolators - many guesses */
 
+/* Hierarchical Z Enable */
+#define R300_SC_HYPERZ                   0x43a4
+#       define R300_SC_HYPERZ_DISABLE     (0 << 0)
+#       define R300_SC_HYPERZ_ENABLE      (1 << 0)
+#       define R300_SC_HYPERZ_MIN         (0 << 1)
+#       define R300_SC_HYPERZ_MAX         (1 << 1)
+#       define R300_SC_HYPERZ_ADJ_256     (0 << 2)
+#       define R300_SC_HYPERZ_ADJ_128     (1 << 2)
+#       define R300_SC_HYPERZ_ADJ_64      (2 << 2)
+#       define R300_SC_HYPERZ_ADJ_32      (3 << 2)
+#       define R300_SC_HYPERZ_ADJ_16      (4 << 2)
+#       define R300_SC_HYPERZ_ADJ_8       (5 << 2)
+#       define R300_SC_HYPERZ_ADJ_4       (6 << 2)
+#       define R300_SC_HYPERZ_ADJ_2       (7 << 2)
+#       define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5)
+#       define R300_SC_HYPERZ_HZ_Z0MIN    (1 << 5)
+#       define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6)
+#       define R300_SC_HYPERZ_HZ_Z0MAX    (1 << 6)
+
+#define R300_SC_EDGERULE                 0x43a8
+
 /* BEGIN: Scissors and cliprects */
 
 /* There are four clipping rectangles. Their corner coordinates are inclusive.
@@ -1346,7 +1367,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 /* Guess by Vladimir.
  * Set to 0A before 3D operations, set to 02 afterwards.
  */
-#define R300_RB3D_DSTCACHE_CTLSTAT          0x4E4C
+/*#define R300_RB3D_DSTCACHE_CTLSTAT          0x4E4C*/
 #       define R300_RB3D_DSTCACHE_UNKNOWN_02             0x00000002
 #       define R300_RB3D_DSTCACHE_UNKNOWN_0A             0x0000000A
 
@@ -1355,19 +1376,14 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  * for this.
  * Bit (1<<8) is the "test" bit. so plain write is 6  - vd
  */
-#define R300_RB3D_ZSTENCIL_CNTL_0                   0x4F00
-#       define R300_RB3D_Z_DISABLED_1            0x00000010
-#       define R300_RB3D_Z_DISABLED_2            0x00000014
-#       define R300_RB3D_Z_TEST                  0x00000012
-#       define R300_RB3D_Z_TEST_AND_WRITE        0x00000016
-#       define R300_RB3D_Z_WRITE_ONLY            0x00000006
-
-#       define R300_RB3D_Z_TEST                  0x00000012
-#       define R300_RB3D_Z_TEST_AND_WRITE        0x00000016
-#       define R300_RB3D_Z_WRITE_ONLY            0x00000006
-#       define R300_RB3D_STENCIL_ENABLE          0x00000001
-
-#define R300_RB3D_ZSTENCIL_CNTL_1                   0x4F04
+#define R300_ZB_CNTL                             0x4F00
+#       define R300_STENCIL_ENABLE               (1 << 0)
+#       define R300_Z_ENABLE                     (1 << 1)
+#       define R300_Z_WRITE_ENABLE               (1 << 2)
+#       define R300_Z_SIGNED_COMPARE             (1 << 3)
+#       define R300_STENCIL_FRONT_BACK           (1 << 4)
+
+#define R300_ZB_ZSTENCILCNTL                   0x4f04
         /* functions */
 #       define R300_ZS_NEVER                    0
 #       define R300_ZS_LESS                     1
@@ -1387,52 +1403,166 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #       define R300_ZS_INVERT                   5
 #       define R300_ZS_INCR_WRAP                6
 #       define R300_ZS_DECR_WRAP                7
+#       define R300_Z_FUNC_SHIFT                0
         /* front and back refer to operations done for front
            and back faces, i.e. separate stencil function support */
-#       define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT           0
-#       define R300_RB3D_ZS1_FRONT_FUNC_SHIFT           3
-#       define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT        6
-#       define R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT       9
-#       define R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT      12
-#       define R300_RB3D_ZS1_BACK_FUNC_SHIFT           15
-#       define R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT        18
-#       define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT       21
-#       define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT       24
-
-#define R300_RB3D_ZSTENCIL_CNTL_2                   0x4F08
-#       define R300_RB3D_ZS2_STENCIL_REF_SHIFT          0
-#       define R300_RB3D_ZS2_STENCIL_MASK               0xFF
-#       define R300_RB3D_ZS2_STENCIL_MASK_SHIFT         8
-#       define R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT   16
+#       define R300_S_FRONT_FUNC_SHIFT          3
+#       define R300_S_FRONT_SFAIL_OP_SHIFT      6
+#       define R300_S_FRONT_ZPASS_OP_SHIFT      9
+#       define R300_S_FRONT_ZFAIL_OP_SHIFT      12
+#       define R300_S_BACK_FUNC_SHIFT           15
+#       define R300_S_BACK_SFAIL_OP_SHIFT       18
+#       define R300_S_BACK_ZPASS_OP_SHIFT       21
+#       define R300_S_BACK_ZFAIL_OP_SHIFT       24
+
+#define R300_ZB_STENCILREFMASK                        0x4f08
+#       define R300_STENCILREF_SHIFT       0
+#       define R300_STENCILREF_MASK        0x000000ff
+#       define R300_STENCILMASK_SHIFT      8
+#       define R300_STENCILMASK_MASK       0x0000ff00
+#       define R300_STENCILWRITEMASK_SHIFT 16
+#       define R300_STENCILWRITEMASK_MASK  0x00ff0000
 
 /* gap */
 
-#define R300_RB3D_ZSTENCIL_FORMAT                   0x4F10
-#       define R300_DEPTH_FORMAT_16BIT_INT_Z     (0 << 0)
-#       define R300_DEPTH_FORMAT_24BIT_INT_Z     (2 << 0)
-        /* 16 bit format or some aditional bit ? */
-#       define R300_DEPTH_FORMAT_UNK32          (32 << 0)
+#define R300_ZB_FORMAT                             0x4f10
+#       define R300_DEPTHFORMAT_16BIT_INT_Z   (0 << 0)
+#       define R300_DEPTHFORMAT_16BIT_13E3    (1 << 0)
+#       define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL   (2 << 0)
+/* reserved up to (15 << 0) */
+#       define R300_INVERT_13E3_LEADING_ONES  (0 << 4)
+#       define R300_INVERT_13E3_LEADING_ZEROS (1 << 4)
 
-#define R300_RB3D_EARLY_Z                           0x4F14
-#       define R300_EARLY_Z_DISABLE              (0 << 0)
-#       define R300_EARLY_Z_ENABLE               (1 << 0)
+#define R300_ZB_ZTOP                             0x4F14
+#       define R300_ZTOP_DISABLE                 (0 << 0)
+#       define R300_ZTOP_ENABLE                  (1 << 0)
 
 /* gap */
 
-#define R300_RB3D_ZCACHE_CTLSTAT            0x4F18 /* GUESS */
-#       define R300_RB3D_ZCACHE_UNKNOWN_01  0x1
-#       define R300_RB3D_ZCACHE_UNKNOWN_03  0x3
+#define R300_ZB_ZCACHE_CTLSTAT            0x4f18
+#       define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT      (0 << 0)
+#       define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
+#       define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT       (0 << 1)
+#       define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE            (1 << 1)
+#       define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE            (0 << 31)
+#       define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY            (1 << 31)
+
+#define R300_ZB_BW_CNTL                     0x4f1c
+#       define R300_HIZ_DISABLE                              (0 << 0)
+#       define R300_HIZ_ENABLE                               (1 << 0)
+#       define R300_HIZ_MIN                                  (0 << 1)
+#       define R300_HIZ_MAX                                  (1 << 1)
+#       define R300_FAST_FILL_DISABLE                        (0 << 2)
+#       define R300_FAST_FILL_ENABLE                         (1 << 2)
+#       define R300_RD_COMP_DISABLE                          (0 << 3)
+#       define R300_RD_COMP_ENABLE                           (1 << 3)
+#       define R300_WR_COMP_DISABLE                          (0 << 4)
+#       define R300_WR_COMP_ENABLE                           (1 << 4)
+#       define R300_ZB_CB_CLEAR_RMW                          (0 << 5)
+#       define R300_ZB_CB_CLEAR_CACHE_LINEAR                 (1 << 5)
+#       define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE   (0 << 6)
+#       define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE    (1 << 6)
+
+#       define R500_ZEQUAL_OPTIMIZE_ENABLE                   (0 << 7)
+#       define R500_ZEQUAL_OPTIMIZE_DISABLE                  (1 << 7)
+#       define R500_SEQUAL_OPTIMIZE_ENABLE                   (0 << 8)
+#       define R500_SEQUAL_OPTIMIZE_DISABLE                  (1 << 8)
+
+#       define R500_BMASK_ENABLE                             (0 << 10)
+#       define R500_BMASK_DISABLE                            (1 << 10)
+#       define R500_HIZ_EQUAL_REJECT_DISABLE                 (0 << 11)
+#       define R500_HIZ_EQUAL_REJECT_ENABLE                  (1 << 11)
+#       define R500_HIZ_FP_EXP_BITS_DISABLE                  (0 << 12)
+#       define R500_HIZ_FP_EXP_BITS_1                        (1 << 12)
+#       define R500_HIZ_FP_EXP_BITS_2                        (2 << 12)
+#       define R500_HIZ_FP_EXP_BITS_3                        (3 << 12)
+#       define R500_HIZ_FP_EXP_BITS_4                        (4 << 12)
+#       define R500_HIZ_FP_EXP_BITS_5                        (5 << 12)
+#       define R500_HIZ_FP_INVERT_LEADING_ONES               (0 << 15)
+#       define R500_HIZ_FP_INVERT_LEADING_ZEROS              (1 << 15)
+#       define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE      (0 << 16)
+#       define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE     (1 << 16)
+#       define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE           (0 << 17)
+#       define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE          (1 << 17)
+#       define R500_PEQ_PACKING_DISABLE                      (0 << 18)
+#       define R500_PEQ_PACKING_ENABLE                       (1 << 18)
+#       define R500_COVERED_PTR_MASKING_DISABLE              (0 << 18)
+#       define R500_COVERED_PTR_MASKING_ENABLE               (1 << 18)
+
 
 /* gap */
 
-#define R300_RB3D_DEPTHOFFSET               0x4F20
-#define R300_RB3D_DEPTHPITCH                0x4F24
-#       define R300_DEPTHPITCH_MASK              0x00001FF8 /* GUESS */
-#       define R300_DEPTH_TILE_ENABLE            (1 << 16) /* GUESS */
-#       define R300_DEPTH_MICROTILE_ENABLE       (1 << 17) /* GUESS */
-#       define R300_DEPTH_ENDIAN_NO_SWAP         (0 << 18) /* GUESS */
-#       define R300_DEPTH_ENDIAN_WORD_SWAP       (1 << 18) /* GUESS */
-#       define R300_DEPTH_ENDIAN_DWORD_SWAP      (2 << 18) /* GUESS */
+/* Z Buffer Address Offset.
+ * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
+ */
+#define R300_ZB_DEPTHOFFSET               0x4f20
+
+/* Z Buffer Pitch and Endian Control */
+#define R300_ZB_DEPTHPITCH                0x4f24
+#       define R300_DEPTHPITCH_MASK              0x00003FFC
+#       define R300_DEPTHMACROTILE_DISABLE      (0 << 16)
+#       define R300_DEPTHMACROTILE_ENABLE       (1 << 16)
+#       define R300_DEPTHMICROTILE_LINEAR       (0 << 17)
+#       define R300_DEPTHMICROTILE_TILED        (1 << 17)
+#       define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
+#       define R300_DEPTHENDIAN_NO_SWAP         (0 << 18)
+#       define R300_DEPTHENDIAN_WORD_SWAP       (1 << 18)
+#       define R300_DEPTHENDIAN_DWORD_SWAP      (2 << 18)
+#       define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
+
+/* Z Buffer Clear Value */
+#define R300_ZB_DEPTHCLEARVALUE                  0x4f28
+
+#define R300_ZB_ZMASK_OFFSET                     0x4f30
+#define R300_ZB_ZMASK_PITCH                      0x4f34
+#define R300_ZB_ZMASK_WRINDEX                    0x4f38
+#define R300_ZB_ZMASK_DWORD                      0x4f3c
+#define R300_ZB_ZMASK_RDINDEX                    0x4f40
+
+/* Hierarchical Z Memory Offset */
+#define R300_ZB_HIZ_OFFSET                       0x4f44
+
+/* Hierarchical Z Write Index */
+#define R300_ZB_HIZ_WRINDEX                      0x4f48
+
+/* Hierarchical Z Data */
+#define R300_ZB_HIZ_DWORD                        0x4f4c
+
+/* Hierarchical Z Read Index */
+#define R300_ZB_HIZ_RDINDEX                      0x4f50
+
+/* Hierarchical Z Pitch */
+#define R300_ZB_HIZ_PITCH                        0x4f54
+
+/* Z Buffer Z Pass Counter Data */
+#define R300_ZB_ZPASS_DATA                       0x4f58
+
+/* Z Buffer Z Pass Counter Address */
+#define R300_ZB_ZPASS_ADDR                       0x4f5c
+
+/* Depth buffer X and Y coordinate offset */
+#define R300_ZB_DEPTHXY_OFFSET                   0x4f60
+#       define R300_DEPTHX_OFFSET_SHIFT  1
+#       define R300_DEPTHX_OFFSET_MASK   0x000007FE
+#       define R300_DEPTHY_OFFSET_SHIFT  17
+#       define R300_DEPTHY_OFFSET_MASK   0x07FE0000
+
+/* Sets the fifo sizes */
+#define R500_ZB_FIFO_SIZE                        0x4fd0
+#       define R500_OP_FIFO_SIZE_FULL   (0 << 0)
+#       define R500_OP_FIFO_SIZE_HALF   (1 << 0)
+#       define R500_OP_FIFO_SIZE_QUATER (2 << 0)
+#       define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)
+
+/* Stencil Reference Value and Mask for backfacing quads */
+/* R300_ZB_STENCILREFMASK handles front face */
+#define R500_ZB_STENCILREFMASK_BF                0x4fd4
+#       define R500_STENCILREF_SHIFT       0
+#       define R500_STENCILREF_MASK        0x000000ff
+#       define R500_STENCILMASK_SHIFT      8
+#       define R500_STENCILMASK_MASK       0x0000ff00
+#       define R500_STENCILWRITEMASK_SHIFT 16
+#       define R500_STENCILWRITEMASK_MASK  0x00ff0000
 
 /* BEGIN: Vertex program instruction set */
 
@@ -1623,4 +1753,20 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 #define R300_CP_CMD_BITBLT_MULTI        0xC0009B00
 
+#define R500_VAP_INDEX_OFFSET           0x208c
+
+#define R500_GA_US_VECTOR_INDEX         0x4250
+#define R500_GA_US_VECTOR_DATA          0x4254
+
+#define R500_RS_IP_0                    0x4074
+#define R500_RS_INST_0                  0x4320
+
+#define R500_US_CONFIG                  0x4600
+
+#define R500_US_FC_CTRL                 0x4624
+#define R500_US_CODE_ADDR               0x4630
+
+#define R500_RB3D_COLOR_CLEAR_VALUE_AR  0x46c0
+#define R500_RB3D_CONSTANT_COLOR_AR     0x4ef8
+
 #endif /* _R300_REG_H */
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index f6f6c92bf771..e53158f0ecb5 100644
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -2,6 +2,7 @@
 /*
  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
+ * Copyright 2007 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -34,789 +35,13 @@
 #include "radeon_drv.h"
 #include "r300_reg.h"
 
+#include "radeon_microcode.h"
+
 #define RADEON_FIFO_DEBUG       0
 
 static int radeon_do_cleanup_cp(struct drm_device * dev);
 
-/* CP microcode (from ATI) */
-static const u32 R200_cp_microcode[][2] = {
-        {0x21007000, 0000000000},
-        {0x20007000, 0000000000},
-        {0x000000ab, 0x00000004},
-        {0x000000af, 0x00000004},
-        {0x66544a49, 0000000000},
-        {0x49494174, 0000000000},
-        {0x54517d83, 0000000000},
-        {0x498d8b64, 0000000000},
-        {0x49494949, 0000000000},
-        {0x49da493c, 0000000000},
-        {0x49989898, 0000000000},
-        {0xd34949d5, 0000000000},
-        {0x9dc90e11, 0000000000},
-        {0xce9b9b9b, 0000000000},
-        {0x000f0000, 0x00000016},
-        {0x352e232c, 0000000000},
-        {0x00000013, 0x00000004},
-        {0x000f0000, 0x00000016},
-        {0x352e272c, 0000000000},
-        {0x000f0001, 0x00000016},
-        {0x3239362f, 0000000000},
-        {0x000077ef, 0x00000002},
-        {0x00061000, 0x00000002},
-        {0x00000020, 0x0000001a},
-        {0x00004000, 0x0000001e},
-        {0x00061000, 0x00000002},
-        {0x00000020, 0x0000001a},
-        {0x00004000, 0x0000001e},
-        {0x00061000, 0x00000002},
-        {0x00000020, 0x0000001a},
-        {0x00004000, 0x0000001e},
-        {0x00000016, 0x00000004},
-        {0x0003802a, 0x00000002},
-        {0x040067e0, 0x00000002},
-        {0x00000016, 0x00000004},
-        {0x000077e0, 0x00000002},
-        {0x00065000, 0x00000002},
-        {0x000037e1, 0x00000002},
-        {0x040067e1, 0x00000006},
-        {0x000077e0, 0x00000002},
-        {0x000077e1, 0x00000002},
-        {0x000077e1, 0x00000006},
-        {0xffffffff, 0000000000},
-        {0x10000000, 0000000000},
-        {0x0003802a, 0x00000002},
-        {0x040067e0, 0x00000006},
-        {0x00007675, 0x00000002},
-        {0x00007676, 0x00000002},
-        {0x00007677, 0x00000002},
-        {0x00007678, 0x00000006},
-        {0x0003802b, 0x00000002},
-        {0x04002676, 0x00000002},
-        {0x00007677, 0x00000002},
-        {0x00007678, 0x00000006},
-        {0x0000002e, 0x00000018},
-        {0x0000002e, 0x00000018},
-        {0000000000, 0x00000006},
-        {0x0000002f, 0x00000018},
-        {0x0000002f, 0x00000018},
-        {0000000000, 0x00000006},
-        {0x01605000, 0x00000002},
-        {0x00065000, 0x00000002},
-        {0x00098000, 0x00000002},
-        {0x00061000, 0x00000002},
-        {0x64c0603d, 0x00000004},
-        {0x00080000, 0x00000016},
-        {0000000000, 0000000000},
-        {0x0400251d, 0x00000002},
-        {0x00007580, 0x00000002},
-        {0x00067581, 0x00000002},
-        {0x04002580, 0x00000002},
-        {0x00067581, 0x00000002},
-        {0x00000046, 0x00000004},
-        {0x00005000, 0000000000},
-        {0x00061000, 0x00000002},
-        {0x0000750e, 0x00000002},
-        {0x00019000, 0x00000002},
-        {0x00011055, 0x00000014},
-        {0x00000055, 0x00000012},
-        {0x0400250f, 0x00000002},
-        {0x0000504a, 0x00000004},
-        {0x00007565, 0x00000002},
-        {0x00007566, 0x00000002},
-        {0x00000051, 0x00000004},
-        {0x01e655b4, 0x00000002},
-        {0x4401b0dc, 0x00000002},
-        {0x01c110dc, 0x00000002},
-        {0x2666705d, 0x00000018},
-        {0x040c2565, 0x00000002},
-        {0x0000005d, 0x00000018},
-        {0x04002564, 0x00000002},
-        {0x00007566, 0x00000002},
-        {0x00000054, 0x00000004},
-        {0x00401060, 0x00000008},
-        {0x00101000, 0x00000002},
-        {0x000d80ff, 0x00000002},
-        {0x00800063, 0x00000008},
-        {0x000f9000, 0x00000002},
-        {0x000e00ff, 0x00000002},
-        {0000000000, 0x00000006},
-        {0x00000080, 0x00000018},
-        {0x00000054, 0x00000004},
-        {0x00007576, 0x00000002},
-        {0x00065000, 0x00000002},
-        {0x00009000, 0x00000002},
-        {0x00041000, 0x00000002},
-        {0x0c00350e, 0x00000002},
-        {0x00049000, 0x00000002},
-        {0x00051000, 0x00000002},
-        {0x01e785f8, 0x00000002},
-        {0x00200000, 0x00000002},
-        {0x00600073, 0x0000000c},
-        {0x00007563, 0x00000002},
-        {0x006075f0, 0x00000021},
-        {0x20007068, 0x00000004},
-        {0x00005068, 0x00000004},
-        {0x00007576, 0x00000002},
-        {0x00007577, 0x00000002},
-        {0x0000750e, 0x00000002},
-        {0x0000750f, 0x00000002},
-        {0x00a05000, 0x00000002},
-        {0x00600076, 0x0000000c},
-        {0x006075f0, 0x00000021},
-        {0x000075f8, 0x00000002},
-        {0x00000076, 0x00000004},
-        {0x000a750e, 0x00000002},
-        {0x0020750f, 0x00000002},
-        {0x00600079, 0x00000004},
-        {0x00007570, 0x00000002},
-        {0x00007571, 0x00000002},
-        {0x00007572, 0x00000006},
-        {0x00005000, 0x00000002},
-        {0x00a05000, 0x00000002},
-        {0x00007568, 0x00000002},
-        {0x00061000, 0x00000002},
-        {0x00000084, 0x0000000c},
-        {0x00058000, 0x00000002},
-        {0x0c607562, 0x00000002},
-        {0x00000086, 0x00000004},
-        {0x00600085, 0x00000004},
-        {0x400070dd, 0000000000},
-        {0x000380dd, 0x00000002},
-        {0x00000093, 0x0000001c},
-        {0x00065095, 0x00000018},
-        {0x040025bb, 0x00000002},
-        {0x00061096, 0x00000018},
-        {0x040075bc, 0000000000},
-        {0x000075bb, 0x00000002},
-        {0x000075bc, 0000000000},
-        {0x00090000, 0x00000006},
-        {0x00090000, 0x00000002},
-        {0x000d8002, 0x00000006},
-        {0x00005000, 0x00000002},
-        {0x00007821, 0x00000002},
-        {0x00007800, 0000000000},
-        {0x00007821, 0x00000002},
-        {0x00007800, 0000000000},
-        {0x01665000, 0x00000002},
-        {0x000a0000, 0x00000002},
-        {0x000671cc, 0x00000002},
-        {0x0286f1cd, 0x00000002},
-        {0x000000a3, 0x00000010},
-        {0x21007000, 0000000000},
-        {0x000000aa, 0x0000001c},
-        {0x00065000, 0x00000002},
-        {0x000a0000, 0x00000002},
-        {0x00061000, 0x00000002},
-        {0x000b0000, 0x00000002},
-        {0x38067000, 0x00000002},
-        {0x000a00a6, 0x00000004},
-        {0x20007000, 0000000000},
-        {0x01200000, 0x00000002},
-        {0x20077000, 0x00000002},
-        {0x01200000, 0x00000002},
-        {0x20007000, 0000000000},
-        {0x00061000, 0x00000002},
-        {0x0120751b, 0x00000002},
-        {0x8040750a, 0x00000002},
-        {0x8040750b, 0x00000002},
-        {0x00110000, 0x00000002},
-        {0x000380dd, 0x00000002},
-        {0x000000bd, 0x0000001c},
-        {0x00061096, 0x00000018},
-        {0x844075bd, 0x00000002},
-        {0x00061095, 0x00000018},
-        {0x840075bb, 0x00000002},
-        {0x00061096, 0x00000018},
-        {0x844075bc, 0x00000002},
-        {0x000000c0, 0x00000004},
-        {0x804075bd, 0x00000002},
-        {0x800075bb, 0x00000002},
-        {0x804075bc, 0x00000002},
-        {0x00108000, 0x00000002},
-        {0x01400000, 0x00000002},
-        {0x006000c4, 0x0000000c},
-        {0x20c07000, 0x00000020},
-        {0x000000c6, 0x00000012},
-        {0x00800000, 0x00000006},
-        {0x0080751d, 0x00000006},
-        {0x000025bb, 0x00000002},
-        {0x000040c0, 0x00000004},
-        {0x0000775c, 0x00000002},
-        {0x00a05000, 0x00000002},
-        {0x00661000, 0x00000002},
-        {0x0460275d, 0x00000020},
-        {0x00004000, 0000000000},
-        {0x00007999, 0x00000002},
-        {0x00a05000, 0x00000002},
-        {0x00661000, 0x00000002},
-        {0x0460299b, 0x00000020},
-        {0x00004000, 0000000000},
-        {0x01e00830, 0x00000002},
-        {0x21007000, 0000000000},
-        {0x00005000, 0x00000002},
-        {0x00038042, 0x00000002},
-        {0x040025e0, 0x00000002},
-        {0x000075e1, 0000000000},
-        {0x00000001, 0000000000},
-        {0x000380d9, 0x00000002},
-        {0x04007394, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-};
-
-static const u32 radeon_cp_microcode[][2] = {
-        {0x21007000, 0000000000},
-        {0x20007000, 0000000000},
-        {0x000000b4, 0x00000004},
-        {0x000000b8, 0x00000004},
-        {0x6f5b4d4c, 0000000000},
-        {0x4c4c427f, 0000000000},
-        {0x5b568a92, 0000000000},
-        {0x4ca09c6d, 0000000000},
-        {0xad4c4c4c, 0000000000},
-        {0x4ce1af3d, 0000000000},
-        {0xd8afafaf, 0000000000},
-        {0xd64c4cdc, 0000000000},
-        {0x4cd10d10, 0000000000},
-        {0x000f0000, 0x00000016},
-        {0x362f242d, 0000000000},
-        {0x00000012, 0x00000004},
-        {0x000f0000, 0x00000016},
-        {0x362f282d, 0000000000},
-        {0x000380e7, 0x00000002},
-        {0x04002c97, 0x00000002},
-        {0x000f0001, 0x00000016},
-        {0x333a3730, 0000000000},
-        {0x000077ef, 0x00000002},
-        {0x00061000, 0x00000002},
-        {0x00000021, 0x0000001a},
-        {0x00004000, 0x0000001e},
-        {0x00061000, 0x00000002},
-        {0x00000021, 0x0000001a},
-        {0x00004000, 0x0000001e},
-        {0x00061000, 0x00000002},
-        {0x00000021, 0x0000001a},
-        {0x00004000, 0x0000001e},
-        {0x00000017, 0x00000004},
-        {0x0003802b, 0x00000002},
-        {0x040067e0, 0x00000002},
-        {0x00000017, 0x00000004},
-        {0x000077e0, 0x00000002},
-        {0x00065000, 0x00000002},
-        {0x000037e1, 0x00000002},
-        {0x040067e1, 0x00000006},
-        {0x000077e0, 0x00000002},
-        {0x000077e1, 0x00000002},
-        {0x000077e1, 0x00000006},
-        {0xffffffff, 0000000000},
-        {0x10000000, 0000000000},
-        {0x0003802b, 0x00000002},
-        {0x040067e0, 0x00000006},
-        {0x00007675, 0x00000002},
-        {0x00007676, 0x00000002},
-        {0x00007677, 0x00000002},
-        {0x00007678, 0x00000006},
-        {0x0003802c, 0x00000002},
-        {0x04002676, 0x00000002},
-        {0x00007677, 0x00000002},
-        {0x00007678, 0x00000006},
-        {0x0000002f, 0x00000018},
-        {0x0000002f, 0x00000018},
-        {0000000000, 0x00000006},
-        {0x00000030, 0x00000018},
-        {0x00000030, 0x00000018},
-        {0000000000, 0x00000006},
-        {0x01605000, 0x00000002},
-        {0x00065000, 0x00000002},
-        {0x00098000, 0x00000002},
-        {0x00061000, 0x00000002},
-        {0x64c0603e, 0x00000004},
-        {0x000380e6, 0x00000002},
-        {0x040025c5, 0x00000002},
-        {0x00080000, 0x00000016},
-        {0000000000, 0000000000},
-        {0x0400251d, 0x00000002},
-        {0x00007580, 0x00000002},
-        {0x00067581, 0x00000002},
-        {0x04002580, 0x00000002},
-        {0x00067581, 0x00000002},
-        {0x00000049, 0x00000004},
-        {0x00005000, 0000000000},
-        {0x000380e6, 0x00000002},
-        {0x040025c5, 0x00000002},
-        {0x00061000, 0x00000002},
-        {0x0000750e, 0x00000002},
-        {0x00019000, 0x00000002},
-        {0x00011055, 0x00000014},
-        {0x00000055, 0x00000012},
-        {0x0400250f, 0x00000002},
-        {0x0000504f, 0x00000004},
-        {0x000380e6, 0x00000002},
-        {0x040025c5, 0x00000002},
-        {0x00007565, 0x00000002},
-        {0x00007566, 0x00000002},
-        {0x00000058, 0x00000004},
-        {0x000380e6, 0x00000002},
-        {0x040025c5, 0x00000002},
-        {0x01e655b4, 0x00000002},
-        {0x4401b0e4, 0x00000002},
-        {0x01c110e4, 0x00000002},
-        {0x26667066, 0x00000018},
-        {0x040c2565, 0x00000002},
-        {0x00000066, 0x00000018},
-        {0x04002564, 0x00000002},
-        {0x00007566, 0x00000002},
-        {0x0000005d, 0x00000004},
-        {0x00401069, 0x00000008},
-        {0x00101000, 0x00000002},
-        {0x000d80ff, 0x00000002},
-        {0x0080006c, 0x00000008},
-        {0x000f9000, 0x00000002},
-        {0x000e00ff, 0x00000002},
-        {0000000000, 0x00000006},
-        {0x0000008f, 0x00000018},
-        {0x0000005b, 0x00000004},
-        {0x000380e6, 0x00000002},
-        {0x040025c5, 0x00000002},
-        {0x00007576, 0x00000002},
-        {0x00065000, 0x00000002},
-        {0x00009000, 0x00000002},
-        {0x00041000, 0x00000002},
-        {0x0c00350e, 0x00000002},
-        {0x00049000, 0x00000002},
-        {0x00051000, 0x00000002},
-        {0x01e785f8, 0x00000002},
-        {0x00200000, 0x00000002},
-        {0x0060007e, 0x0000000c},
-        {0x00007563, 0x00000002},
-        {0x006075f0, 0x00000021},
-        {0x20007073, 0x00000004},
-        {0x00005073, 0x00000004},
-        {0x000380e6, 0x00000002},
-        {0x040025c5, 0x00000002},
-        {0x00007576, 0x00000002},
-        {0x00007577, 0x00000002},
-        {0x0000750e, 0x00000002},
-        {0x0000750f, 0x00000002},
-        {0x00a05000, 0x00000002},
-        {0x00600083, 0x0000000c},
-        {0x006075f0, 0x00000021},
-        {0x000075f8, 0x00000002},
-        {0x00000083, 0x00000004},
-        {0x000a750e, 0x00000002},
-        {0x000380e6, 0x00000002},
-        {0x040025c5, 0x00000002},
-        {0x0020750f, 0x00000002},
-        {0x00600086, 0x00000004},
-        {0x00007570, 0x00000002},
-        {0x00007571, 0x00000002},
-        {0x00007572, 0x00000006},
-        {0x000380e6, 0x00000002},
-        {0x040025c5, 0x00000002},
-        {0x00005000, 0x00000002},
-        {0x00a05000, 0x00000002},
-        {0x00007568, 0x00000002},
-        {0x00061000, 0x00000002},
-        {0x00000095, 0x0000000c},
-        {0x00058000, 0x00000002},
-        {0x0c607562, 0x00000002},
-        {0x00000097, 0x00000004},
-        {0x000380e6, 0x00000002},
-        {0x040025c5, 0x00000002},
-        {0x00600096, 0x00000004},
-        {0x400070e5, 0000000000},
-        {0x000380e6, 0x00000002},
-        {0x040025c5, 0x00000002},
-        {0x000380e5, 0x00000002},
-        {0x000000a8, 0x0000001c},
-        {0x000650aa, 0x00000018},
-        {0x040025bb, 0x00000002},
-        {0x000610ab, 0x00000018},
-        {0x040075bc, 0000000000},
-        {0x000075bb, 0x00000002},
-        {0x000075bc, 0000000000},
-        {0x00090000, 0x00000006},
-        {0x00090000, 0x00000002},
-        {0x000d8002, 0x00000006},
-        {0x00007832, 0x00000002},
-        {0x00005000, 0x00000002},
-        {0x000380e7, 0x00000002},
-        {0x04002c97, 0x00000002},
-        {0x00007820, 0x00000002},
-        {0x00007821, 0x00000002},
-        {0x00007800, 0000000000},
-        {0x01200000, 0x00000002},
-        {0x20077000, 0x00000002},
-        {0x01200000, 0x00000002},
-        {0x20007000, 0x00000002},
-        {0x00061000, 0x00000002},
-        {0x0120751b, 0x00000002},
-        {0x8040750a, 0x00000002},
-        {0x8040750b, 0x00000002},
-        {0x00110000, 0x00000002},
-        {0x000380e5, 0x00000002},
-        {0x000000c6, 0x0000001c},
-        {0x000610ab, 0x00000018},
-        {0x844075bd, 0x00000002},
-        {0x000610aa, 0x00000018},
-        {0x840075bb, 0x00000002},
-        {0x000610ab, 0x00000018},
-        {0x844075bc, 0x00000002},
-        {0x000000c9, 0x00000004},
-        {0x804075bd, 0x00000002},
-        {0x800075bb, 0x00000002},
-        {0x804075bc, 0x00000002},
-        {0x00108000, 0x00000002},
-        {0x01400000, 0x00000002},
-        {0x006000cd, 0x0000000c},
-        {0x20c07000, 0x00000020},
-        {0x000000cf, 0x00000012},
-        {0x00800000, 0x00000006},
-        {0x0080751d, 0x00000006},
-        {0000000000, 0000000000},
-        {0x0000775c, 0x00000002},
-        {0x00a05000, 0x00000002},
-        {0x00661000, 0x00000002},
-        {0x0460275d, 0x00000020},
-        {0x00004000, 0000000000},
-        {0x01e00830, 0x00000002},
-        {0x21007000, 0000000000},
-        {0x6464614d, 0000000000},
-        {0x69687420, 0000000000},
-        {0x00000073, 0000000000},
-        {0000000000, 0000000000},
-        {0x00005000, 0x00000002},
-        {0x000380d0, 0x00000002},
-        {0x040025e0, 0x00000002},
-        {0x000075e1, 0000000000},
-        {0x00000001, 0000000000},
-        {0x000380e0, 0x00000002},
-        {0x04002394, 0x00000002},
-        {0x00005000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0x00000008, 0000000000},
-        {0x00000004, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-};
-
-static const u32 R300_cp_microcode[][2] = {
-        {0x4200e000, 0000000000},
-        {0x4000e000, 0000000000},
-        {0x000000af, 0x00000008},
-        {0x000000b3, 0x00000008},
-        {0x6c5a504f, 0000000000},
-        {0x4f4f497a, 0000000000},
-        {0x5a578288, 0000000000},
-        {0x4f91906a, 0000000000},
-        {0x4f4f4f4f, 0000000000},
-        {0x4fe24f44, 0000000000},
-        {0x4f9c9c9c, 0000000000},
-        {0xdc4f4fde, 0000000000},
-        {0xa1cd4f4f, 0000000000},
-        {0xd29d9d9d, 0000000000},
-        {0x4f0f9fd7, 0000000000},
-        {0x000ca000, 0x00000004},
-        {0x000d0012, 0x00000038},
-        {0x0000e8b4, 0x00000004},
-        {0x000d0014, 0x00000038},
-        {0x0000e8b6, 0x00000004},
-        {0x000d0016, 0x00000038},
-        {0x0000e854, 0x00000004},
-        {0x000d0018, 0x00000038},
-        {0x0000e855, 0x00000004},
-        {0x000d001a, 0x00000038},
-        {0x0000e856, 0x00000004},
-        {0x000d001c, 0x00000038},
-        {0x0000e857, 0x00000004},
-        {0x000d001e, 0x00000038},
-        {0x0000e824, 0x00000004},
-        {0x000d0020, 0x00000038},
-        {0x0000e825, 0x00000004},
-        {0x000d0022, 0x00000038},
-        {0x0000e830, 0x00000004},
-        {0x000d0024, 0x00000038},
-        {0x0000f0c0, 0x00000004},
-        {0x000d0026, 0x00000038},
-        {0x0000f0c1, 0x00000004},
-        {0x000d0028, 0x00000038},
-        {0x0000f041, 0x00000004},
-        {0x000d002a, 0x00000038},
-        {0x0000f184, 0x00000004},
-        {0x000d002c, 0x00000038},
-        {0x0000f185, 0x00000004},
-        {0x000d002e, 0x00000038},
-        {0x0000f186, 0x00000004},
-        {0x000d0030, 0x00000038},
-        {0x0000f187, 0x00000004},
-        {0x000d0032, 0x00000038},
-        {0x0000f180, 0x00000004},
-        {0x000d0034, 0x00000038},
-        {0x0000f393, 0x00000004},
-        {0x000d0036, 0x00000038},
-        {0x0000f38a, 0x00000004},
-        {0x000d0038, 0x00000038},
-        {0x0000f38e, 0x00000004},
-        {0x0000e821, 0x00000004},
-        {0x0140a000, 0x00000004},
-        {0x00000043, 0x00000018},
-        {0x00cce800, 0x00000004},
-        {0x001b0001, 0x00000004},
-        {0x08004800, 0x00000004},
-        {0x001b0001, 0x00000004},
-        {0x08004800, 0x00000004},
-        {0x001b0001, 0x00000004},
-        {0x08004800, 0x00000004},
-        {0x0000003a, 0x00000008},
-        {0x0000a000, 0000000000},
-        {0x02c0a000, 0x00000004},
-        {0x000ca000, 0x00000004},
-        {0x00130000, 0x00000004},
-        {0x000c2000, 0x00000004},
-        {0xc980c045, 0x00000008},
-        {0x2000451d, 0x00000004},
-        {0x0000e580, 0x00000004},
-        {0x000ce581, 0x00000004},
-        {0x08004580, 0x00000004},
-        {0x000ce581, 0x00000004},
-        {0x0000004c, 0x00000008},
-        {0x0000a000, 0000000000},
-        {0x000c2000, 0x00000004},
-        {0x0000e50e, 0x00000004},
-        {0x00032000, 0x00000004},
-        {0x00022056, 0x00000028},
-        {0x00000056, 0x00000024},
-        {0x0800450f, 0x00000004},
-        {0x0000a050, 0x00000008},
-        {0x0000e565, 0x00000004},
-        {0x0000e566, 0x00000004},
-        {0x00000057, 0x00000008},
-        {0x03cca5b4, 0x00000004},
-        {0x05432000, 0x00000004},
-        {0x00022000, 0x00000004},
-        {0x4ccce063, 0x00000030},
-        {0x08274565, 0x00000004},
-        {0x00000063, 0x00000030},
-        {0x08004564, 0x00000004},
-        {0x0000e566, 0x00000004},
-        {0x0000005a, 0x00000008},
-        {0x00802066, 0x00000010},
-        {0x00202000, 0x00000004},
-        {0x001b00ff, 0x00000004},
-        {0x01000069, 0x00000010},
-        {0x001f2000, 0x00000004},
-        {0x001c00ff, 0x00000004},
-        {0000000000, 0x0000000c},
-        {0x00000085, 0x00000030},
-        {0x0000005a, 0x00000008},
-        {0x0000e576, 0x00000004},
-        {0x000ca000, 0x00000004},
-        {0x00012000, 0x00000004},
-        {0x00082000, 0x00000004},
-        {0x1800650e, 0x00000004},
-        {0x00092000, 0x00000004},
-        {0x000a2000, 0x00000004},
-        {0x000f0000, 0x00000004},
-        {0x00400000, 0x00000004},
-        {0x00000079, 0x00000018},
-        {0x0000e563, 0x00000004},
-        {0x00c0e5f9, 0x000000c2},
-        {0x0000006e, 0x00000008},
-        {0x0000a06e, 0x00000008},
-        {0x0000e576, 0x00000004},
-        {0x0000e577, 0x00000004},
-        {0x0000e50e, 0x00000004},
-        {0x0000e50f, 0x00000004},
-        {0x0140a000, 0x00000004},
-        {0x0000007c, 0x00000018},
-        {0x00c0e5f9, 0x000000c2},
-        {0x0000007c, 0x00000008},
-        {0x0014e50e, 0x00000004},
-        {0x0040e50f, 0x00000004},
-        {0x00c0007f, 0x00000008},
-        {0x0000e570, 0x00000004},
-        {0x0000e571, 0x00000004},
-        {0x0000e572, 0x0000000c},
-        {0x0000a000, 0x00000004},
-        {0x0140a000, 0x00000004},
-        {0x0000e568, 0x00000004},
-        {0x000c2000, 0x00000004},
-        {0x00000089, 0x00000018},
-        {0x000b0000, 0x00000004},
-        {0x18c0e562, 0x00000004},
-        {0x0000008b, 0x00000008},
-        {0x00c0008a, 0x00000008},
-        {0x000700e4, 0x00000004},
-        {0x00000097, 0x00000038},
-        {0x000ca099, 0x00000030},
-        {0x080045bb, 0x00000004},
-        {0x000c209a, 0x00000030},
-        {0x0800e5bc, 0000000000},
-        {0x0000e5bb, 0x00000004},
-        {0x0000e5bc, 0000000000},
-        {0x00120000, 0x0000000c},
-        {0x00120000, 0x00000004},
-        {0x001b0002, 0x0000000c},
-        {0x0000a000, 0x00000004},
-        {0x0000e821, 0x00000004},
-        {0x0000e800, 0000000000},
-        {0x0000e821, 0x00000004},
-        {0x0000e82e, 0000000000},
-        {0x02cca000, 0x00000004},
-        {0x00140000, 0x00000004},
-        {0x000ce1cc, 0x00000004},
-        {0x050de1cd, 0x00000004},
-        {0x000000a7, 0x00000020},
-        {0x4200e000, 0000000000},
-        {0x000000ae, 0x00000038},
-        {0x000ca000, 0x00000004},
-        {0x00140000, 0x00000004},
-        {0x000c2000, 0x00000004},
-        {0x00160000, 0x00000004},
-        {0x700ce000, 0x00000004},
-        {0x001400aa, 0x00000008},
-        {0x4000e000, 0000000000},
-        {0x02400000, 0x00000004},
-        {0x400ee000, 0x00000004},
-        {0x02400000, 0x00000004},
-        {0x4000e000, 0000000000},
-        {0x000c2000, 0x00000004},
-        {0x0240e51b, 0x00000004},
-        {0x0080e50a, 0x00000005},
-        {0x0080e50b, 0x00000005},
-        {0x00220000, 0x00000004},
-        {0x000700e4, 0x00000004},
-        {0x000000c1, 0x00000038},
-        {0x000c209a, 0x00000030},
-        {0x0880e5bd, 0x00000005},
-        {0x000c2099, 0x00000030},
-        {0x0800e5bb, 0x00000005},
-        {0x000c209a, 0x00000030},
-        {0x0880e5bc, 0x00000005},
-        {0x000000c4, 0x00000008},
-        {0x0080e5bd, 0x00000005},
-        {0x0000e5bb, 0x00000005},
-        {0x0080e5bc, 0x00000005},
-        {0x00210000, 0x00000004},
-        {0x02800000, 0x00000004},
-        {0x00c000c8, 0x00000018},
-        {0x4180e000, 0x00000040},
-        {0x000000ca, 0x00000024},
-        {0x01000000, 0x0000000c},
-        {0x0100e51d, 0x0000000c},
-        {0x000045bb, 0x00000004},
-        {0x000080c4, 0x00000008},
-        {0x0000f3ce, 0x00000004},
-        {0x0140a000, 0x00000004},
-        {0x00cc2000, 0x00000004},
-        {0x08c053cf, 0x00000040},
-        {0x00008000, 0000000000},
-        {0x0000f3d2, 0x00000004},
-        {0x0140a000, 0x00000004},
-        {0x00cc2000, 0x00000004},
-        {0x08c053d3, 0x00000040},
-        {0x00008000, 0000000000},
-        {0x0000f39d, 0x00000004},
-        {0x0140a000, 0x00000004},
-        {0x00cc2000, 0x00000004},
-        {0x08c0539e, 0x00000040},
-        {0x00008000, 0000000000},
-        {0x03c00830, 0x00000004},
-        {0x4200e000, 0000000000},
-        {0x0000a000, 0x00000004},
-        {0x200045e0, 0x00000004},
-        {0x0000e5e1, 0000000000},
-        {0x00000001, 0000000000},
-        {0x000700e1, 0x00000004},
-        {0x0800e394, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-        {0000000000, 0000000000},
-};
-
-static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
+static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 {
         u32 ret;
         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
@@ -825,21 +50,41 @@ static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
         return ret;
 }
 
+static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
+{
+        u32 ret;
+        RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
+        ret = RADEON_READ(RS480_NB_MC_DATA);
+        RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
+        return ret;
+}
+
 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 {
+        u32 ret;
         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
-        return RADEON_READ(RS690_MC_DATA);
+        ret = RADEON_READ(RS690_MC_DATA);
+        RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
+        return ret;
+}
+
+static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
+{
+        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
+                return RS690_READ_MCIND(dev_priv, addr);
+        else
+                return RS480_READ_MCIND(dev_priv, addr);
 }
 
 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 {
 
         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
-                return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
+                return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
-                return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
+                return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
         else
                 return RADEON_READ(RADEON_MC_FB_LOCATION);
 }
@@ -847,11 +92,11 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 {
         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
-                RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
+                R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
-                RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
+                R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
         else
                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 }
@@ -859,15 +104,39 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 {
         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
-                RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
+                R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
-                RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
+                R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
         else
                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 }
 
+static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
+{
+        u32 agp_base_hi = upper_32_bits(agp_base);
+        u32 agp_base_lo = agp_base & 0xffffffff;
+
+        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
+                R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
+                R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
+        } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
+                RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
+                RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
+        } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
+                R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
+                R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
+        } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) {
+                RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
+                RADEON_WRITE(RS480_AGP_BASE_2, 0);
+        } else {
+                RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
+                if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
+                        RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
+        }
+}
+
 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 {
         drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -882,15 +151,6 @@ static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
         return RADEON_READ(RADEON_PCIE_DATA);
 }
 
-static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
-{
-        u32 ret;
-        RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
-        ret = RADEON_READ(RADEON_IGPGART_DATA);
-        RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
-        return ret;
-}
-
 #if RADEON_FIFO_DEBUG
 static void radeon_status(drm_radeon_private_t * dev_priv)
 {
@@ -925,16 +185,36 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 
         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 
-        tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
-        tmp |= RADEON_RB3D_DC_FLUSH_ALL;
-        RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
+        if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
+                tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
+                tmp |= RADEON_RB3D_DC_FLUSH_ALL;
+                RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 
-        for (i = 0; i < dev_priv->usec_timeout; i++) {
-                if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
-                      & RADEON_RB3D_DC_BUSY)) {
-                        return 0;
+                for (i = 0; i < dev_priv->usec_timeout; i++) {
+                        if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
+                              & RADEON_RB3D_DC_BUSY)) {
+                                return 0;
+                        }
+                        DRM_UDELAY(1);
+                }
+        } else {
+                /* 3D */
+                tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT);
+                tmp |= RADEON_RB3D_DC_FLUSH_ALL;
+                RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp);
+
+                /* 2D */
+                tmp = RADEON_READ(R300_DSTCACHE_CTLSTAT);
+                tmp |= RADEON_RB3D_DC_FLUSH_ALL;
+                RADEON_WRITE(R300_DSTCACHE_CTLSTAT, tmp);
+
+                for (i = 0; i < dev_priv->usec_timeout; i++) {
+                        if (!(RADEON_READ(R300_DSTCACHE_CTLSTAT)
+                          & RADEON_RB3D_DC_BUSY)) {
+                                return 0;
+                        }
+                        DRM_UDELAY(1);
                 }
-                DRM_UDELAY(1);
         }
 
 #if RADEON_FIFO_DEBUG
@@ -991,6 +271,50 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
         return -EBUSY;
 }
 
+static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
+{
+        uint32_t gb_tile_config, gb_pipe_sel = 0;
+
+        /* RS4xx/RS6xx/R4xx/R5xx */
+        if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
+                gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
+                dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
+        } else {
+                /* R3xx */
+                if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
+                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
+                        dev_priv->num_gb_pipes = 2;
+                } else {
+                        /* R3Vxx */
+                        dev_priv->num_gb_pipes = 1;
+                }
+        }
+        DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
+
+        gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
+
+        switch (dev_priv->num_gb_pipes) {
+        case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
+        case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
+        case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
+        default:
+        case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
+        }
+
+        if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
+                RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
+                RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
+        }
+        RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
+        radeon_do_wait_for_idle(dev_priv);
+        RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
+        RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
+                                               R300_DC_AUTOFLUSH_ENABLE |
+                                               R300_DC_DC_DISABLE_IGNORE_PE));
+
+
+}
+
 /* ================================================================
  * CP control, initialization
  */
@@ -1004,8 +328,22 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
         radeon_do_wait_for_idle(dev_priv);
 
         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
-
-        if (dev_priv->microcode_version == UCODE_R200) {
+        if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
+            ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
+            ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
+            ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
+            ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
+                DRM_INFO("Loading R100 Microcode\n");
+                for (i = 0; i < 256; i++) {
+                        RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
+                                     R100_cp_microcode[i][1]);
+                        RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
+                                     R100_cp_microcode[i][0]);
+                }
+        } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
+                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
+                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
+                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
                 DRM_INFO("Loading R200 Microcode\n");
                 for (i = 0; i < 256; i++) {
                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
@@ -1013,7 +351,11 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
                                      R200_cp_microcode[i][0]);
                 }
-        } else if (dev_priv->microcode_version == UCODE_R300) {
+        } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
+                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
+                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
+                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
+                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
                 DRM_INFO("Loading R300 Microcode\n");
                 for (i = 0; i < 256; i++) {
                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
@@ -1021,12 +363,35 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
                                      R300_cp_microcode[i][0]);
                 }
-        } else {
+        } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
+                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
+                DRM_INFO("Loading R400 Microcode\n");
                 for (i = 0; i < 256; i++) {
                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
-                                     radeon_cp_microcode[i][1]);
+                                     R420_cp_microcode[i][1]);
                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
-                                     radeon_cp_microcode[i][0]);
+                                     R420_cp_microcode[i][0]);
+                }
+        } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
+                DRM_INFO("Loading RS690 Microcode\n");
+                for (i = 0; i < 256; i++) {
+                        RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
+                                     RS690_cp_microcode[i][1]);
+                        RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
+                                     RS690_cp_microcode[i][0]);
+                }
+        } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
+                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
+                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
+                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
+                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
+                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
+                DRM_INFO("Loading R500 Microcode\n");
+                for (i = 0; i < 256; i++) {
+                        RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
+                                     R520_cp_microcode[i][1]);
+                        RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
+                                     R520_cp_microcode[i][0]);
                 }
         }
 }
@@ -1121,12 +486,13 @@ static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 static int radeon_do_engine_reset(struct drm_device * dev)
 {
         drm_radeon_private_t *dev_priv = dev->dev_private;
-        u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
+        u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
         DRM_DEBUG("\n");
 
         radeon_do_pixcache_flush(dev_priv);
 
-        if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
+        if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
+                /* may need something similar for newer chips */
                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 
@@ -1137,33 +503,39 @@ static int radeon_do_engine_reset(struct drm_device * dev)
                                                     RADEON_FORCEON_YCLKB |
                                                     RADEON_FORCEON_MC |
                                                     RADEON_FORCEON_AIC));
+        }
 
-                rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
-
-                RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
-                                                      RADEON_SOFT_RESET_CP |
-                                                      RADEON_SOFT_RESET_HI |
-                                                      RADEON_SOFT_RESET_SE |
-                                                      RADEON_SOFT_RESET_RE |
-                                                      RADEON_SOFT_RESET_PP |
-                                                      RADEON_SOFT_RESET_E2 |
-                                                      RADEON_SOFT_RESET_RB));
-                RADEON_READ(RADEON_RBBM_SOFT_RESET);
-                RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
-                                                      ~(RADEON_SOFT_RESET_CP |
-                                                        RADEON_SOFT_RESET_HI |
-                                                        RADEON_SOFT_RESET_SE |
-                                                        RADEON_SOFT_RESET_RE |
-                                                        RADEON_SOFT_RESET_PP |
-                                                        RADEON_SOFT_RESET_E2 |
-                                                        RADEON_SOFT_RESET_RB)));
-                RADEON_READ(RADEON_RBBM_SOFT_RESET);
-
+        rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
+
+        RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
+                                              RADEON_SOFT_RESET_CP |
+                                              RADEON_SOFT_RESET_HI |
+                                              RADEON_SOFT_RESET_SE |
+                                              RADEON_SOFT_RESET_RE |
+                                              RADEON_SOFT_RESET_PP |
+                                              RADEON_SOFT_RESET_E2 |
+                                              RADEON_SOFT_RESET_RB));
+        RADEON_READ(RADEON_RBBM_SOFT_RESET);
+        RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
+                                              ~(RADEON_SOFT_RESET_CP |
+                                                RADEON_SOFT_RESET_HI |
+                                                RADEON_SOFT_RESET_SE |
+                                                RADEON_SOFT_RESET_RE |
+                                                RADEON_SOFT_RESET_PP |
+                                                RADEON_SOFT_RESET_E2 |
+                                                RADEON_SOFT_RESET_RB)));
+        RADEON_READ(RADEON_RBBM_SOFT_RESET);
+
+        if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
         }
 
+        /* setup the raster pipes */
+        if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
+            radeon_init_pipes(dev_priv);
+
         /* Reset the CP ring */
         radeon_do_cp_reset(dev_priv);
 
@@ -1194,7 +566,8 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 
 #if __OS_HAS_AGP
         if (dev_priv->flags & RADEON_IS_AGP) {
-                RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
+                radeon_write_agp_base(dev_priv, dev->agp->base);
+
                 radeon_write_agp_location(dev_priv,
                              (((dev_priv->gart_vm_start - 1 +
                                 dev_priv->gart_size) & 0xffff0000) |
@@ -1339,102 +712,70 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 /* Enable or disable IGP GART on the chip */
 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 {
-        u32 temp, tmp;
-
-        tmp = RADEON_READ(RADEON_AIC_CNTL);
-        if (on) {
-                DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
-                         dev_priv->gart_vm_start,
-                         (long)dev_priv->gart_info.bus_addr,
-                         dev_priv->gart_size);
-
-                RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
-                RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
-                RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
-                RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
-                                     dev_priv->gart_info.bus_addr);
-
-                temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
-                RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);
-
-                RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
-                dev_priv->gart_size = 32*1024*1024;
-                radeon_write_agp_location(dev_priv,
-                             (((dev_priv->gart_vm_start - 1 +
-                               dev_priv->gart_size) & 0xffff0000) |
-                             (dev_priv->gart_vm_start >> 16)));
-
-                temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
-                RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
-
-                RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
-                RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
-                RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
-                RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
-       }
-}
-
-/* Enable or disable RS690 GART on the chip */
-static void radeon_set_rs690gart(drm_radeon_private_t *dev_priv, int on)
-{
         u32 temp;
 
         if (on) {
-                DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n",
+                DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
                           dev_priv->gart_vm_start,
                           (long)dev_priv->gart_info.bus_addr,
                           dev_priv->gart_size);
 
-                temp = RS690_READ_MCIND(dev_priv, RS690_MC_MISC_CNTL);
-                RS690_WRITE_MCIND(RS690_MC_MISC_CNTL, 0x5000);
+                temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
+                if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
+                        IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
+                                                             RS690_BLOCK_GFX_D3_EN));
+                else
+                        IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 
-                RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
-                                  RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
+                IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
+                                                               RS480_VA_SIZE_32MB));
 
-                temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID);
-                RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800);
+                temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
+                IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
+                                                        RS480_TLB_ENABLE |
+                                                        RS480_GTW_LAC_EN |
+                                                        RS480_1LEVEL_GART));
 
-                RS690_WRITE_MCIND(RS690_MC_GART_BASE,
-                                  dev_priv->gart_info.bus_addr);
+                temp = dev_priv->gart_info.bus_addr & 0xfffff000;
+                temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
+                IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 
-                temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL);
-                RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000);
+                temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
+                IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
+                                                      RS480_REQ_TYPE_SNOOP_DIS));
 
-                RS690_WRITE_MCIND(RS690_MC_AGP_BASE,
-                                  (unsigned int)dev_priv->gart_vm_start);
+                radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 
                 dev_priv->gart_size = 32*1024*1024;
                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
 
-                RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp);
+                radeon_write_agp_location(dev_priv, temp);
 
-                temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_SIZE);
-                RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
-                                  RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
+                temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
+                IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
+                                                               RS480_VA_SIZE_32MB));
 
                 do {
-                        temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL);
-                        if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
-                            RS690_MC_GART_CLEAR_DONE)
+                        temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
+                        if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
                                 break;
                         DRM_UDELAY(1);
                 } while (1);
 
-                RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL,
-                                  RS690_MC_GART_CC_CLEAR);
+                IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
+                                RS480_GART_CACHE_INVALIDATE);
+
                 do {
-                        temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL);
-                        if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
-                                   RS690_MC_GART_CLEAR_DONE)
+                        temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
+                        if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
                                 break;
                         DRM_UDELAY(1);
                 } while (1);
 
-                RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL,
-                                  RS690_MC_GART_CC_NO_CHANGE);
+                IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
         } else {
-                RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, RS690_MC_GART_DIS);
+                IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
         }
 }
 
@@ -1472,12 +813,8 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 {
         u32 tmp;
 
-        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
-                radeon_set_rs690gart(dev_priv, on);
-                return;
-        }
-
-        if (dev_priv->flags & RADEON_IS_IGPGART) {
+        if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+            (dev_priv->flags & RADEON_IS_IGPGART)) {
                 radeon_set_igpgart(dev_priv, on);
                 return;
         }
@@ -1951,6 +1288,7 @@ static int radeon_do_resume_cp(struct drm_device * dev)
         radeon_cp_init_ring_buffer(dev, dev_priv);
 
         radeon_do_engine_reset(dev);
+        radeon_enable_interrupt(dev);
 
         DRM_DEBUG("radeon_do_resume_cp() complete\n");
 
diff --git a/drivers/char/drm/radeon_drm.h b/drivers/char/drm/radeon_drm.h
index aab82e121e07..73ff51f12311 100644
--- a/drivers/char/drm/radeon_drm.h
+++ b/drivers/char/drm/radeon_drm.h
@@ -240,6 +240,7 @@ typedef union {
 #       define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN    0x8
 
 #define R300_CMD_SCRATCH                8
+#define R300_CMD_R500FP                 9
 
 typedef union {
         unsigned int u;
@@ -268,6 +269,9 @@ typedef union {
         struct {
                 unsigned char cmd_type, reg, n_bufs, flags;
         } scratch;
+        struct {
+                unsigned char cmd_type, count, adrlo, adrhi_flags;
+        } r500fp;
 } drm_r300_cmd_header_t;
 
 #define RADEON_FRONT                    0x1
@@ -278,6 +282,9 @@ typedef union {
 #define RADEON_USE_HIERZ                0x40000000
 #define RADEON_USE_COMP_ZBUF            0x20000000
 
+#define R500FP_CONSTANT_TYPE  (1 << 1)
+#define R500FP_CONSTANT_CLAMP (1 << 2)
+
 /* Primitive types
  */
 #define RADEON_POINTS                   0x1
@@ -669,6 +676,7 @@ typedef struct drm_radeon_indirect {
 #define RADEON_PARAM_CARD_TYPE             12
 #define RADEON_PARAM_VBLANK_CRTC           13   /* VBLANK CRTC */
 #define RADEON_PARAM_FB_LOCATION           14   /* FB location */
+#define RADEON_PARAM_NUM_GB_PIPES          15   /* num GB pipes */
 
 typedef struct drm_radeon_getparam {
         int param;
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index 173ae620223a..3f0eca957aa7 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -38,7 +38,7 @@
 
 #define DRIVER_NAME             "radeon"
 #define DRIVER_DESC             "ATI Radeon"
-#define DRIVER_DATE             "20060524"
+#define DRIVER_DATE             "20080528"
 
 /* Interface history:
  *
@@ -98,9 +98,10 @@
  * 1.26- Add support for variable size PCI(E) gart aperture
  * 1.27- Add support for IGP GART
  * 1.28- Add support for VBL on CRTC2
+ * 1.29- R500 3D cmd buffer support
  */
 #define DRIVER_MAJOR            1
-#define DRIVER_MINOR            28
+#define DRIVER_MINOR            29
 #define DRIVER_PATCHLEVEL       0
 
 /*
@@ -122,7 +123,7 @@ enum radeon_family {
         CHIP_RV380,
         CHIP_R420,
         CHIP_RV410,
-        CHIP_RS400,
+        CHIP_RS480,
         CHIP_RS690,
         CHIP_RV515,
         CHIP_R520,
@@ -294,6 +295,7 @@ typedef struct drm_radeon_private {
         int vblank_crtc;
         uint32_t irq_enable_reg;
         int irq_enabled;
+        uint32_t r500_disp_irq_reg;
 
         struct radeon_surface surfaces[RADEON_MAX_SURFACES];
         struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
@@ -307,6 +309,8 @@ typedef struct drm_radeon_private {
         /* starting from here on, data is preserved accross an open */
         uint32_t flags;         /* see radeon_chip_flags */
         unsigned long fb_aper_offset;
+
+        int num_gb_pipes;
 } drm_radeon_private_t;
 
 typedef struct drm_radeon_buf_priv {
@@ -382,6 +386,7 @@ extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
 extern void radeon_driver_irq_preinstall(struct drm_device * dev);
 extern void radeon_driver_irq_postinstall(struct drm_device * dev);
 extern void radeon_driver_irq_uninstall(struct drm_device * dev);
+extern void radeon_enable_interrupt(struct drm_device *dev);
 extern int radeon_vblank_crtc_get(struct drm_device *dev);
 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
 
@@ -444,13 +449,13 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
 #define RADEON_PCIE_DATA                0x0034
 #define RADEON_PCIE_TX_GART_CNTL        0x10
 #       define RADEON_PCIE_TX_GART_EN           (1 << 0)
-#       define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
-#       define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO  (1<<1)
-#       define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD   (3<<1)
-#       define RADEON_PCIE_TX_GART_MODE_32_128_CACHE    (0<<3)
-#       define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE   (1<<3)
-#       define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN      (1<<5)
-#       define RADEON_PCIE_TX_GART_INVALIDATE_TLB       (1<<8)
+#       define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
+#       define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO  (1 << 1)
+#       define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD   (3 << 1)
+#       define RADEON_PCIE_TX_GART_MODE_32_128_CACHE    (0 << 3)
+#       define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE   (1 << 3)
+#       define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN      (1 << 5)
+#       define RADEON_PCIE_TX_GART_INVALIDATE_TLB       (1 << 8)
 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
 #define RADEON_PCIE_TX_GART_BASE        0x13
@@ -459,14 +464,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
 #define RADEON_PCIE_TX_GART_END_LO      0x16
 #define RADEON_PCIE_TX_GART_END_HI      0x17
 
-#define RADEON_IGPGART_INDEX            0x168
-#define RADEON_IGPGART_DATA             0x16c
-#define RADEON_IGPGART_UNK_18           0x18
-#define RADEON_IGPGART_CTRL             0x2b
-#define RADEON_IGPGART_BASE_ADDR        0x2c
-#define RADEON_IGPGART_FLUSH            0x2e
-#define RADEON_IGPGART_ENABLE           0x38
-#define RADEON_IGPGART_UNK_39           0x39
+#define RS480_NB_MC_INDEX               0x168
+#       define RS480_NB_MC_IND_WR_EN    (1 << 8)
+#define RS480_NB_MC_DATA                0x16c
 
 #define RS690_MC_INDEX                  0x78
 #   define RS690_MC_INDEX_MASK          0x1ff
@@ -474,45 +474,91 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
 #   define RS690_MC_INDEX_WR_ACK        0x7f
 #define RS690_MC_DATA                   0x7c
 
-#define RS690_MC_MISC_CNTL              0x18
-#define RS690_MC_GART_FEATURE_ID        0x2b
-#define RS690_MC_GART_BASE              0x2c
-#define RS690_MC_GART_CACHE_CNTL        0x2e
-#   define RS690_MC_GART_CC_NO_CHANGE   0x0
-#   define RS690_MC_GART_CC_CLEAR       0x1
-#   define RS690_MC_GART_CLEAR_STATUS   (1 << 1)
-#       define RS690_MC_GART_CLEAR_DONE     (0 << 1)
-#       define RS690_MC_GART_CLEAR_PENDING  (1 << 1)
-#define RS690_MC_AGP_SIZE               0x38
-#   define RS690_MC_GART_DIS            0x0
-#   define RS690_MC_GART_EN             0x1
-#   define RS690_MC_AGP_SIZE_32MB       (0 << 1)
-#   define RS690_MC_AGP_SIZE_64MB       (1 << 1)
-#   define RS690_MC_AGP_SIZE_128MB      (2 << 1)
-#   define RS690_MC_AGP_SIZE_256MB      (3 << 1)
-#   define RS690_MC_AGP_SIZE_512MB      (4 << 1)
-#   define RS690_MC_AGP_SIZE_1GB        (5 << 1)
-#   define RS690_MC_AGP_SIZE_2GB        (6 << 1)
-#define RS690_MC_AGP_MODE_CONTROL       0x39
+/* MC indirect registers */
+#define RS480_MC_MISC_CNTL              0x18
+#       define RS480_DISABLE_GTW        (1 << 1)
+/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
+#       define RS480_GART_INDEX_REG_EN  (1 << 12)
+#       define RS690_BLOCK_GFX_D3_EN    (1 << 14)
+#define RS480_K8_FB_LOCATION            0x1e
+#define RS480_GART_FEATURE_ID           0x2b
+#       define RS480_HANG_EN            (1 << 11)
+#       define RS480_TLB_ENABLE         (1 << 18)
+#       define RS480_P2P_ENABLE         (1 << 19)
+#       define RS480_GTW_LAC_EN         (1 << 25)
+#       define RS480_2LEVEL_GART        (0 << 30)
+#       define RS480_1LEVEL_GART        (1 << 30)
+#       define RS480_PDC_EN             (1 << 31)
+#define RS480_GART_BASE                 0x2c
+#define RS480_GART_CACHE_CNTRL          0x2e
+#       define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
+#define RS480_AGP_ADDRESS_SPACE_SIZE    0x38
+#       define RS480_GART_EN            (1 << 0)
+#       define RS480_VA_SIZE_32MB       (0 << 1)
+#       define RS480_VA_SIZE_64MB       (1 << 1)
+#       define RS480_VA_SIZE_128MB      (2 << 1)
+#       define RS480_VA_SIZE_256MB      (3 << 1)
+#       define RS480_VA_SIZE_512MB      (4 << 1)
+#       define RS480_VA_SIZE_1GB        (5 << 1)
+#       define RS480_VA_SIZE_2GB        (6 << 1)
+#define RS480_AGP_MODE_CNTL             0x39
+#       define RS480_POST_GART_Q_SIZE   (1 << 18)
+#       define RS480_NONGART_SNOOP      (1 << 19)
+#       define RS480_AGP_RD_BUF_SIZE    (1 << 20)
+#       define RS480_REQ_TYPE_SNOOP_SHIFT 22
+#       define RS480_REQ_TYPE_SNOOP_MASK  0x3
+#       define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
+#define RS480_MC_MISC_UMA_CNTL          0x5f
+#define RS480_MC_MCLK_CNTL              0x7a
+#define RS480_MC_UMA_DUALCH_CNTL        0x86
+
 #define RS690_MC_FB_LOCATION            0x100
 #define RS690_MC_AGP_LOCATION           0x101
 #define RS690_MC_AGP_BASE               0x102
+#define RS690_MC_AGP_BASE_2             0x103
 
 #define R520_MC_IND_INDEX 0x70
-#define R520_MC_IND_WR_EN (1<<24)
+#define R520_MC_IND_WR_EN (1 << 24)
 #define R520_MC_IND_DATA  0x74
 
 #define RV515_MC_FB_LOCATION 0x01
 #define RV515_MC_AGP_LOCATION 0x02
+#define RV515_MC_AGP_BASE     0x03
+#define RV515_MC_AGP_BASE_2   0x04
 
 #define R520_MC_FB_LOCATION 0x04
 #define R520_MC_AGP_LOCATION 0x05
+#define R520_MC_AGP_BASE     0x06
+#define R520_MC_AGP_BASE_2   0x07
 
 #define RADEON_MPP_TB_CONFIG            0x01c0
 #define RADEON_MEM_CNTL                 0x0140
 #define RADEON_MEM_SDRAM_MODE_REG       0x0158
+#define RADEON_AGP_BASE_2               0x015c /* r200+ only */
+#define RS480_AGP_BASE_2                0x0164
 #define RADEON_AGP_BASE                 0x0170
 
+/* pipe config regs */
+#define R400_GB_PIPE_SELECT             0x402c
+#define R500_DYN_SCLK_PWMEM_PIPE        0x000d /* PLL */
+#define R500_SU_REG_DEST                0x42c8
+#define R300_GB_TILE_CONFIG             0x4018
+#       define R300_ENABLE_TILING       (1 << 0)
+#       define R300_PIPE_COUNT_RV350    (0 << 1)
+#       define R300_PIPE_COUNT_R300     (3 << 1)
+#       define R300_PIPE_COUNT_R420_3P  (6 << 1)
+#       define R300_PIPE_COUNT_R420     (7 << 1)
+#       define R300_TILE_SIZE_8         (0 << 4)
+#       define R300_TILE_SIZE_16        (1 << 4)
+#       define R300_TILE_SIZE_32        (2 << 4)
+#       define R300_SUBPIXEL_1_12       (0 << 16)
+#       define R300_SUBPIXEL_1_16       (1 << 16)
+#define R300_DST_PIPE_CONFIG            0x170c
+#       define R300_PIPE_AUTO_CONFIG    (1 << 31)
+#define R300_RB2D_DSTCACHE_MODE         0x3428
+#       define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
+#       define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
+
 #define RADEON_RB3D_COLOROFFSET         0x1c40
 #define RADEON_RB3D_COLORPITCH          0x1c48
 
@@ -616,11 +662,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
 #define RADEON_PP_TXFILTER_1            0x1c6c
 #define RADEON_PP_TXFILTER_2            0x1c84
 
-#define RADEON_RB2D_DSTCACHE_CTLSTAT    0x342c
-#       define RADEON_RB2D_DC_FLUSH             (3 << 0)
-#       define RADEON_RB2D_DC_FREE              (3 << 2)
-#       define RADEON_RB2D_DC_FLUSH_ALL         0xf
-#       define RADEON_RB2D_DC_BUSY              (1 << 31)
+#define R300_RB2D_DSTCACHE_CTLSTAT      0x342c /* use R300_DSTCACHE_CTLSTAT */
+#define R300_DSTCACHE_CTLSTAT           0x1714
+#       define R300_RB2D_DC_FLUSH               (3 << 0)
+#       define R300_RB2D_DC_FREE                (3 << 2)
+#       define R300_RB2D_DC_FLUSH_ALL           0xf
+#       define R300_RB2D_DC_BUSY                (1 << 31)
 #define RADEON_RB3D_CNTL                0x1c3c
 #       define RADEON_ALPHA_BLEND_ENABLE        (1 << 0)
 #       define RADEON_PLANE_MASK_ENABLE         (1 << 1)
@@ -643,11 +690,18 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
 #       define RADEON_RB3D_ZC_FREE              (1 << 2)
 #       define RADEON_RB3D_ZC_FLUSH_ALL         0x5
 #       define RADEON_RB3D_ZC_BUSY              (1 << 31)
+#define R300_ZB_ZCACHE_CTLSTAT                  0x4f18
+#       define R300_ZC_FLUSH                    (1 << 0)
+#       define R300_ZC_FREE                     (1 << 1)
+#       define R300_ZC_FLUSH_ALL                0x3
+#       define R300_ZC_BUSY                     (1 << 31)
 #define RADEON_RB3D_DSTCACHE_CTLSTAT    0x325c
 #       define RADEON_RB3D_DC_FLUSH             (3 << 0)
 #       define RADEON_RB3D_DC_FREE              (3 << 2)
 #       define RADEON_RB3D_DC_FLUSH_ALL         0xf
 #       define RADEON_RB3D_DC_BUSY              (1 << 31)
+#define R300_RB3D_DSTCACHE_CTLSTAT              0x4e4c
+#       define R300_RB3D_DC_FINISH              (1 << 4)
 #define RADEON_RB3D_ZSTENCILCNTL        0x1c2c
 #       define RADEON_Z_TEST_MASK               (7 << 4)
 #       define RADEON_Z_TEST_ALWAYS             (7 << 4)
@@ -1057,6 +1111,31 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
 
 #define R200_VAP_PVS_CNTL_1               0x22D0
 
+#define R500_D1CRTC_STATUS 0x609c
+#define R500_D2CRTC_STATUS 0x689c
+#define R500_CRTC_V_BLANK (1<<0)
+
+#define R500_D1CRTC_FRAME_COUNT 0x60a4
+#define R500_D2CRTC_FRAME_COUNT 0x68a4
+
+#define R500_D1MODE_V_COUNTER 0x6530
+#define R500_D2MODE_V_COUNTER 0x6d30
+
+#define R500_D1MODE_VBLANK_STATUS 0x6534
+#define R500_D2MODE_VBLANK_STATUS 0x6d34
+#define R500_VBLANK_OCCURED (1<<0)
+#define R500_VBLANK_ACK     (1<<4)
+#define R500_VBLANK_STAT    (1<<12)
+#define R500_VBLANK_INT     (1<<16)
+
+#define R500_DxMODE_INT_MASK 0x6540
+#define R500_D1MODE_INT_MASK (1<<0)
+#define R500_D2MODE_INT_MASK (1<<8)
+
+#define R500_DISP_INTERRUPT_STATUS 0x7edc
+#define R500_D1_VBLANK_INTERRUPT (1 << 4)
+#define R500_D2_VBLANK_INTERRUPT (1 << 5)
+
 /* Constants */
 #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
 
@@ -1078,42 +1157,50 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
 #define RADEON_READ8(reg)       DRM_READ8(  dev_priv->mmio, (reg) )
 #define RADEON_WRITE8(reg,val)  DRM_WRITE8( dev_priv->mmio, (reg), (val) )
 
-#define RADEON_WRITE_PLL( addr, val )                                   \
+#define RADEON_WRITE_PLL(addr, val)                                     \
 do {                                                                    \
-        RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX,                         \
+        RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX,                          \
                        ((addr) & 0x1f) | RADEON_PLL_WR_EN );            \
-        RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) );                  \
+        RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val));                    \
 } while (0)
 
-#define RADEON_WRITE_IGPGART( addr, val )                               \
+#define RADEON_WRITE_PCIE(addr, val)                                    \
 do {                                                                    \
-        RADEON_WRITE( RADEON_IGPGART_INDEX,                             \
-                        ((addr) & 0x7f) | (1 << 8));                    \
-        RADEON_WRITE( RADEON_IGPGART_DATA, (val) );                     \
-        RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f );                     \
+        RADEON_WRITE8(RADEON_PCIE_INDEX,                                \
+                        ((addr) & 0xff));                               \
+        RADEON_WRITE(RADEON_PCIE_DATA, (val));                  \
 } while (0)
 
-#define RADEON_WRITE_PCIE( addr, val )                                  \
-do {                                                                    \
-        RADEON_WRITE8( RADEON_PCIE_INDEX,                               \
-                        ((addr) & 0xff));                               \
-        RADEON_WRITE( RADEON_PCIE_DATA, (val) );                        \
+#define R500_WRITE_MCIND(addr, val)                                     \
+do {                                                            \
+        RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff));    \
+        RADEON_WRITE(R520_MC_IND_DATA, (val));                  \
+        RADEON_WRITE(R520_MC_IND_INDEX, 0);     \
 } while (0)
 
-#define RADEON_WRITE_MCIND( addr, val )                                 \
-        do {                                                            \
-                RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff));    \
-                RADEON_WRITE(R520_MC_IND_DATA, (val));                  \
-                RADEON_WRITE(R520_MC_IND_INDEX, 0);     \
-        } while (0)
+#define RS480_WRITE_MCIND(addr, val)                            \
+do {                                                                    \
+        RADEON_WRITE(RS480_NB_MC_INDEX,                         \
+                        ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN);       \
+        RADEON_WRITE(RS480_NB_MC_DATA, (val));                  \
+        RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);                  \
+} while (0)
 
-#define RS690_WRITE_MCIND( addr, val )                                  \
+#define RS690_WRITE_MCIND(addr, val)                                    \
 do {                                                            \
         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK));    \
         RADEON_WRITE(RS690_MC_DATA, val);                       \
         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);    \
 } while (0)
 
+#define IGP_WRITE_MCIND(addr, val)                              \
+do {                                                                    \
+        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)       \
+                RS690_WRITE_MCIND(addr, val);                           \
+        else                                                            \
+                RS480_WRITE_MCIND(addr, val);                           \
+} while (0)
+
 #define CP_PACKET0( reg, n )                                            \
         (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
 #define CP_PACKET0_TABLE( reg, n )                                      \
@@ -1154,23 +1241,43 @@ do {								\
 } while (0)
 
 #define RADEON_FLUSH_CACHE() do {                                       \
-        OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) );      \
-        OUT_RING( RADEON_RB3D_DC_FLUSH );                               \
+        if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {     \
+                OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));  \
+                OUT_RING(RADEON_RB3D_DC_FLUSH);                         \
+        } else {                                                        \
+                OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));    \
+                OUT_RING(RADEON_RB3D_DC_FLUSH);                         \
+        }                                                               \
 } while (0)
 
 #define RADEON_PURGE_CACHE() do {                                       \
-        OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) );      \
-        OUT_RING( RADEON_RB3D_DC_FLUSH_ALL );                           \
+        if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {     \
+                OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));  \
+                OUT_RING(RADEON_RB3D_DC_FLUSH_ALL);                     \
+        } else {                                                        \
+                OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));    \
+                OUT_RING(RADEON_RB3D_DC_FLUSH_ALL);                     \
+        }                                                               \
 } while (0)
 
 #define RADEON_FLUSH_ZCACHE() do {                                      \
-        OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) );        \
-        OUT_RING( RADEON_RB3D_ZC_FLUSH );                               \
+        if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {     \
+                OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));    \
+                OUT_RING(RADEON_RB3D_ZC_FLUSH);                         \
+        } else {                                                        \
+                OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));        \
+                OUT_RING(R300_ZC_FLUSH);                                \
+        }                                                               \
 } while (0)
 
 #define RADEON_PURGE_ZCACHE() do {                                      \
-        OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) );        \
-        OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL );                           \
+        if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {     \
+                OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));    \
+                OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL);                     \
+        } else {                                                        \
+                OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));    \
+                OUT_RING(R300_ZC_FLUSH_ALL);                            \
+        }                                                               \
 } while (0)
 
 /* ================================================================
diff --git a/drivers/char/drm/radeon_irq.c b/drivers/char/drm/radeon_irq.c
index 009af3814b6f..ee40d197deb7 100644
--- a/drivers/char/drm/radeon_irq.c
+++ b/drivers/char/drm/radeon_irq.c
@@ -234,7 +234,7 @@ int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_pr
         return radeon_wait_irq(dev, irqwait->irq_seq);
 }
 
-static void radeon_enable_interrupt(struct drm_device *dev)
+void radeon_enable_interrupt(struct drm_device *dev)
 {
         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 
diff --git a/drivers/char/drm/radeon_microcode.h b/drivers/char/drm/radeon_microcode.h
new file mode 100644
index 000000000000..a348c9e7db1c
--- /dev/null
+++ b/drivers/char/drm/radeon_microcode.h
@@ -0,0 +1,1844 @@
+/*
+ * Copyright 2007 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef RADEON_MICROCODE_H
+#define RADEON_MICROCODE_H
+
+/* production radeon ucode r1xx-r6xx */
+static const u32 R100_cp_microcode[][2] = {
+    { 0x21007000, 0000000000 },
+    { 0x20007000, 0000000000 },
+    { 0x000000b4, 0x00000004 },
+    { 0x000000b8, 0x00000004 },
+    { 0x6f5b4d4c, 0000000000 },
+    { 0x4c4c427f, 0000000000 },
+    { 0x5b568a92, 0000000000 },
+    { 0x4ca09c6d, 0000000000 },
+    { 0xad4c4c4c, 0000000000 },
+    { 0x4ce1af3d, 0000000000 },
+    { 0xd8afafaf, 0000000000 },
+    { 0xd64c4cdc, 0000000000 },
+    { 0x4cd10d10, 0000000000 },
+    { 0x000f0000, 0x00000016 },
+    { 0x362f242d, 0000000000 },
+    { 0x00000012, 0x00000004 },
+    { 0x000f0000, 0x00000016 },
+    { 0x362f282d, 0000000000 },
+    { 0x000380e7, 0x00000002 },
+    { 0x04002c97, 0x00000002 },
+    { 0x000f0001, 0x00000016 },
+    { 0x333a3730, 0000000000 },
+    { 0x000077ef, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x00000021, 0x0000001a },
+    { 0x00004000, 0x0000001e },
+    { 0x00061000, 0x00000002 },
+    { 0x00000021, 0x0000001a },
+    { 0x00004000, 0x0000001e },
+    { 0x00061000, 0x00000002 },
+    { 0x00000021, 0x0000001a },
+    { 0x00004000, 0x0000001e },
+    { 0x00000017, 0x00000004 },
+    { 0x0003802b, 0x00000002 },
+    { 0x040067e0, 0x00000002 },
+    { 0x00000017, 0x00000004 },
+    { 0x000077e0, 0x00000002 },
+    { 0x00065000, 0x00000002 },
+    { 0x000037e1, 0x00000002 },
+    { 0x040067e1, 0x00000006 },
+    { 0x000077e0, 0x00000002 },
+    { 0x000077e1, 0x00000002 },
+    { 0x000077e1, 0x00000006 },
+    { 0xffffffff, 0000000000 },
+    { 0x10000000, 0000000000 },
+    { 0x0003802b, 0x00000002 },
+    { 0x040067e0, 0x00000006 },
+    { 0x00007675, 0x00000002 },
+    { 0x00007676, 0x00000002 },
+    { 0x00007677, 0x00000002 },
+    { 0x00007678, 0x00000006 },
+    { 0x0003802c, 0x00000002 },
+    { 0x04002676, 0x00000002 },
+    { 0x00007677, 0x00000002 },
+    { 0x00007678, 0x00000006 },
+    { 0x0000002f, 0x00000018 },
+    { 0x0000002f, 0x00000018 },
+    { 0000000000, 0x00000006 },
+    { 0x00000030, 0x00000018 },
+    { 0x00000030, 0x00000018 },
+    { 0000000000, 0x00000006 },
+    { 0x01605000, 0x00000002 },
+    { 0x00065000, 0x00000002 },
+    { 0x00098000, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x64c0603e, 0x00000004 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00080000, 0x00000016 },
+    { 0000000000, 0000000000 },
+    { 0x0400251d, 0x00000002 },
+    { 0x00007580, 0x00000002 },
+    { 0x00067581, 0x00000002 },
+    { 0x04002580, 0x00000002 },
+    { 0x00067581, 0x00000002 },
+    { 0x00000049, 0x00000004 },
+    { 0x00005000, 0000000000 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x0000750e, 0x00000002 },
+    { 0x00019000, 0x00000002 },
+    { 0x00011055, 0x00000014 },
+    { 0x00000055, 0x00000012 },
+    { 0x0400250f, 0x00000002 },
+    { 0x0000504f, 0x00000004 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00007565, 0x00000002 },
+    { 0x00007566, 0x00000002 },
+    { 0x00000058, 0x00000004 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x01e655b4, 0x00000002 },
+    { 0x4401b0e4, 0x00000002 },
+    { 0x01c110e4, 0x00000002 },
+    { 0x26667066, 0x00000018 },
+    { 0x040c2565, 0x00000002 },
+    { 0x00000066, 0x00000018 },
+    { 0x04002564, 0x00000002 },
+    { 0x00007566, 0x00000002 },
+    { 0x0000005d, 0x00000004 },
+    { 0x00401069, 0x00000008 },
+    { 0x00101000, 0x00000002 },
+    { 0x000d80ff, 0x00000002 },
+    { 0x0080006c, 0x00000008 },
+    { 0x000f9000, 0x00000002 },
+    { 0x000e00ff, 0x00000002 },
+    { 0000000000, 0x00000006 },
+    { 0x0000008f, 0x00000018 },
+    { 0x0000005b, 0x00000004 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00007576, 0x00000002 },
+    { 0x00065000, 0x00000002 },
+    { 0x00009000, 0x00000002 },
+    { 0x00041000, 0x00000002 },
+    { 0x0c00350e, 0x00000002 },
+    { 0x00049000, 0x00000002 },
+    { 0x00051000, 0x00000002 },
+    { 0x01e785f8, 0x00000002 },
+    { 0x00200000, 0x00000002 },
+    { 0x0060007e, 0x0000000c },
+    { 0x00007563, 0x00000002 },
+    { 0x006075f0, 0x00000021 },
+    { 0x20007073, 0x00000004 },
+    { 0x00005073, 0x00000004 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00007576, 0x00000002 },
+    { 0x00007577, 0x00000002 },
+    { 0x0000750e, 0x00000002 },
+    { 0x0000750f, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x00600083, 0x0000000c },
+    { 0x006075f0, 0x00000021 },
+    { 0x000075f8, 0x00000002 },
+    { 0x00000083, 0x00000004 },
+    { 0x000a750e, 0x00000002 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x0020750f, 0x00000002 },
+    { 0x00600086, 0x00000004 },
+    { 0x00007570, 0x00000002 },
+    { 0x00007571, 0x00000002 },
+    { 0x00007572, 0x00000006 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00005000, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x00007568, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x00000095, 0x0000000c },
+    { 0x00058000, 0x00000002 },
+    { 0x0c607562, 0x00000002 },
+    { 0x00000097, 0x00000004 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00600096, 0x00000004 },
+    { 0x400070e5, 0000000000 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x000380e5, 0x00000002 },
+    { 0x000000a8, 0x0000001c },
+    { 0x000650aa, 0x00000018 },
+    { 0x040025bb, 0x00000002 },
+    { 0x000610ab, 0x00000018 },
+    { 0x040075bc, 0000000000 },
+    { 0x000075bb, 0x00000002 },
+    { 0x000075bc, 0000000000 },
+    { 0x00090000, 0x00000006 },
+    { 0x00090000, 0x00000002 },
+    { 0x000d8002, 0x00000006 },
+    { 0x00007832, 0x00000002 },
+    { 0x00005000, 0x00000002 },
+    { 0x000380e7, 0x00000002 },
+    { 0x04002c97, 0x00000002 },
+    { 0x00007820, 0x00000002 },
+    { 0x00007821, 0x00000002 },
+    { 0x00007800, 0000000000 },
+    { 0x01200000, 0x00000002 },
+    { 0x20077000, 0x00000002 },
+    { 0x01200000, 0x00000002 },
+    { 0x20007000, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x0120751b, 0x00000002 },
+    { 0x8040750a, 0x00000002 },
+    { 0x8040750b, 0x00000002 },
+    { 0x00110000, 0x00000002 },
+    { 0x000380e5, 0x00000002 },
+    { 0x000000c6, 0x0000001c },
+    { 0x000610ab, 0x00000018 },
+    { 0x844075bd, 0x00000002 },
+    { 0x000610aa, 0x00000018 },
+    { 0x840075bb, 0x00000002 },
+    { 0x000610ab, 0x00000018 },
+    { 0x844075bc, 0x00000002 },
+    { 0x000000c9, 0x00000004 },
+    { 0x804075bd, 0x00000002 },
+    { 0x800075bb, 0x00000002 },
+    { 0x804075bc, 0x00000002 },
+    { 0x00108000, 0x00000002 },
+    { 0x01400000, 0x00000002 },
+    { 0x006000cd, 0x0000000c },
+    { 0x20c07000, 0x00000020 },
+    { 0x000000cf, 0x00000012 },
+    { 0x00800000, 0x00000006 },
+    { 0x0080751d, 0x00000006 },
+    { 0000000000, 0000000000 },
+    { 0x0000775c, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x00661000, 0x00000002 },
+    { 0x0460275d, 0x00000020 },
+    { 0x00004000, 0000000000 },
+    { 0x01e00830, 0x00000002 },
+    { 0x21007000, 0000000000 },
+    { 0x6464614d, 0000000000 },
+    { 0x69687420, 0000000000 },
+    { 0x00000073, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x00005000, 0x00000002 },
+    { 0x000380d0, 0x00000002 },
+    { 0x040025e0, 0x00000002 },
+    { 0x000075e1, 0000000000 },
+    { 0x00000001, 0000000000 },
+    { 0x000380e0, 0x00000002 },
+    { 0x04002394, 0x00000002 },
+    { 0x00005000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x00000008, 0000000000 },
+    { 0x00000004, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+};
+
+static const u32 R200_cp_microcode[][2] = {
+    { 0x21007000, 0000000000 },
+    { 0x20007000, 0000000000 },
+    { 0x000000bf, 0x00000004 },
+    { 0x000000c3, 0x00000004 },
+    { 0x7a685e5d, 0000000000 },
+    { 0x5d5d5588, 0000000000 },
+    { 0x68659197, 0000000000 },
+    { 0x5da19f78, 0000000000 },
+    { 0x5d5d5d5d, 0000000000 },
+    { 0x5dee5d50, 0000000000 },
+    { 0xf2acacac, 0000000000 },
+    { 0xe75df9e9, 0000000000 },
+    { 0xb1dd0e11, 0000000000 },
+    { 0xe2afafaf, 0000000000 },
+    { 0x000f0000, 0x00000016 },
+    { 0x452f232d, 0000000000 },
+    { 0x00000013, 0x00000004 },
+    { 0x000f0000, 0x00000016 },
+    { 0x452f272d, 0000000000 },
+    { 0x000f0001, 0x00000016 },
+    { 0x3e4d4a37, 0000000000 },
+    { 0x000077ef, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x00000020, 0x0000001a },
+    { 0x00004000, 0x0000001e },
+    { 0x00061000, 0x00000002 },
+    { 0x00000020, 0x0000001a },
+    { 0x00004000, 0x0000001e },
+    { 0x00061000, 0x00000002 },
+    { 0x00000020, 0x0000001a },
+    { 0x00004000, 0x0000001e },
+    { 0x00000016, 0x00000004 },
+    { 0x0003802a, 0x00000002 },
+    { 0x040067e0, 0x00000002 },
+    { 0x00000016, 0x00000004 },
+    { 0x000077e0, 0x00000002 },
+    { 0x00065000, 0x00000002 },
+    { 0x000037e1, 0x00000002 },
+    { 0x040067e1, 0x00000006 },
+    { 0x000077e0, 0x00000002 },
+    { 0x000077e1, 0x00000002 },
+    { 0x000077e1, 0x00000006 },
+    { 0xffffffff, 0000000000 },
+    { 0x10000000, 0000000000 },
+    { 0x07f007f0, 0000000000 },
+    { 0x0003802a, 0x00000002 },
+    { 0x040067e0, 0x00000006 },
+    { 0x0003802c, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002743, 0x00000002 },
+    { 0x00007675, 0x00000002 },
+    { 0x00007676, 0x00000002 },
+    { 0x00007677, 0x00000002 },
+    { 0x00007678, 0x00000006 },
+    { 0x0003802c, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002743, 0x00000002 },
+    { 0x00007676, 0x00000002 },
+    { 0x00007677, 0x00000002 },
+    { 0x00007678, 0x00000006 },
+    { 0x0003802b, 0x00000002 },
+    { 0x04002676, 0x00000002 },
+    { 0x00007677, 0x00000002 },
+    { 0x0003802c, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002743, 0x00000002 },
+    { 0x00007678, 0x00000006 },
+    { 0x0003802c, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002743, 0x00000002 },
+    { 0x00007678, 0x00000006 },
+    { 0x0000002f, 0x00000018 },
+    { 0x0000002f, 0x00000018 },
+    { 0000000000, 0x00000006 },
+    { 0x00000037, 0x00000018 },
+    { 0x00000037, 0x00000018 },
+    { 0000000000, 0x00000006 },
+    { 0x01605000, 0x00000002 },
+    { 0x00065000, 0x00000002 },
+    { 0x00098000, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x64c06051, 0x00000004 },
+    { 0x00080000, 0x00000016 },
+    { 0000000000, 0000000000 },
+    { 0x0400251d, 0x00000002 },
+    { 0x00007580, 0x00000002 },
+    { 0x00067581, 0x00000002 },
+    { 0x04002580, 0x00000002 },
+    { 0x00067581, 0x00000002 },
+    { 0x0000005a, 0x00000004 },
+    { 0x00005000, 0000000000 },
+    { 0x00061000, 0x00000002 },
+    { 0x0000750e, 0x00000002 },
+    { 0x00019000, 0x00000002 },
+    { 0x00011064, 0x00000014 },
+    { 0x00000064, 0x00000012 },
+    { 0x0400250f, 0x00000002 },
+    { 0x0000505e, 0x00000004 },
+    { 0x00007565, 0x00000002 },
+    { 0x00007566, 0x00000002 },
+    { 0x00000065, 0x00000004 },
+    { 0x01e655b4, 0x00000002 },
+    { 0x4401b0f0, 0x00000002 },
+    { 0x01c110f0, 0x00000002 },
+    { 0x26667071, 0x00000018 },
+    { 0x040c2565, 0x00000002 },
+    { 0x00000071, 0x00000018 },
+    { 0x04002564, 0x00000002 },
+    { 0x00007566, 0x00000002 },
+    { 0x00000068, 0x00000004 },
+    { 0x00401074, 0x00000008 },
+    { 0x00101000, 0x00000002 },
+    { 0x000d80ff, 0x00000002 },
+    { 0x00800077, 0x00000008 },
+    { 0x000f9000, 0x00000002 },
+    { 0x000e00ff, 0x00000002 },
+    { 0000000000, 0x00000006 },
+    { 0x00000094, 0x00000018 },
+    { 0x00000068, 0x00000004 },
+    { 0x00007576, 0x00000002 },
+    { 0x00065000, 0x00000002 },
+    { 0x00009000, 0x00000002 },
+    { 0x00041000, 0x00000002 },
+    { 0x0c00350e, 0x00000002 },
+    { 0x00049000, 0x00000002 },
+    { 0x00051000, 0x00000002 },
+    { 0x01e785f8, 0x00000002 },
+    { 0x00200000, 0x00000002 },
+    { 0x00600087, 0x0000000c },
+    { 0x00007563, 0x00000002 },
+    { 0x006075f0, 0x00000021 },
+    { 0x2000707c, 0x00000004 },
+    { 0x0000507c, 0x00000004 },
+    { 0x00007576, 0x00000002 },
+    { 0x00007577, 0x00000002 },
+    { 0x0000750e, 0x00000002 },
+    { 0x0000750f, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x0060008a, 0x0000000c },
+    { 0x006075f0, 0x00000021 },
+    { 0x000075f8, 0x00000002 },
+    { 0x0000008a, 0x00000004 },
+    { 0x000a750e, 0x00000002 },
+    { 0x0020750f, 0x00000002 },
+    { 0x0060008d, 0x00000004 },
+    { 0x00007570, 0x00000002 },
+    { 0x00007571, 0x00000002 },
+    { 0x00007572, 0x00000006 },
+    { 0x00005000, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x00007568, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x00000098, 0x0000000c },
+    { 0x00058000, 0x00000002 },
+    { 0x0c607562, 0x00000002 },
+    { 0x0000009a, 0x00000004 },
+    { 0x00600099, 0x00000004 },
+    { 0x400070f1, 0000000000 },
+    { 0x000380f1, 0x00000002 },
+    { 0x000000a7, 0x0000001c },
+    { 0x000650a9, 0x00000018 },
+    { 0x040025bb, 0x00000002 },
+    { 0x000610aa, 0x00000018 },
+    { 0x040075bc, 0000000000 },
+    { 0x000075bb, 0x00000002 },
+    { 0x000075bc, 0000000000 },
+    { 0x00090000, 0x00000006 },
+    { 0x00090000, 0x00000002 },
+    { 0x000d8002, 0x00000006 },
+    { 0x00005000, 0x00000002 },
+    { 0x00007821, 0x00000002 },
+    { 0x00007800, 0000000000 },
+    { 0x00007821, 0x00000002 },
+    { 0x00007800, 0000000000 },
+    { 0x01665000, 0x00000002 },
+    { 0x000a0000, 0x00000002 },
+    { 0x000671cc, 0x00000002 },
+    { 0x0286f1cd, 0x00000002 },
+    { 0x000000b7, 0x00000010 },
+    { 0x21007000, 0000000000 },
+    { 0x000000be, 0x0000001c },
+    { 0x00065000, 0x00000002 },
+    { 0x000a0000, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x000b0000, 0x00000002 },
+    { 0x38067000, 0x00000002 },
+    { 0x000a00ba, 0x00000004 },
+    { 0x20007000, 0000000000 },
+    { 0x01200000, 0x00000002 },
+    { 0x20077000, 0x00000002 },
+    { 0x01200000, 0x00000002 },
+    { 0x20007000, 0000000000 },
+    { 0x00061000, 0x00000002 },
+    { 0x0120751b, 0x00000002 },
+    { 0x8040750a, 0x00000002 },
+    { 0x8040750b, 0x00000002 },
+    { 0x00110000, 0x00000002 },
+    { 0x000380f1, 0x00000002 },
+    { 0x000000d1, 0x0000001c },
+    { 0x000610aa, 0x00000018 },
+    { 0x844075bd, 0x00000002 },
+    { 0x000610a9, 0x00000018 },
+    { 0x840075bb, 0x00000002 },
+    { 0x000610aa, 0x00000018 },
+    { 0x844075bc, 0x00000002 },
+    { 0x000000d4, 0x00000004 },
+    { 0x804075bd, 0x00000002 },
+    { 0x800075bb, 0x00000002 },
+    { 0x804075bc, 0x00000002 },
+    { 0x00108000, 0x00000002 },
+    { 0x01400000, 0x00000002 },
+    { 0x006000d8, 0x0000000c },
+    { 0x20c07000, 0x00000020 },
+    { 0x000000da, 0x00000012 },
+    { 0x00800000, 0x00000006 },
+    { 0x0080751d, 0x00000006 },
+    { 0x000025bb, 0x00000002 },
+    { 0x000040d4, 0x00000004 },
+    { 0x0000775c, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x00661000, 0x00000002 },
+    { 0x0460275d, 0x00000020 },
+    { 0x00004000, 0000000000 },
+    { 0x00007999, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x00661000, 0x00000002 },
+    { 0x0460299b, 0x00000020 },
+    { 0x00004000, 0000000000 },
+    { 0x01e00830, 0x00000002 },
+    { 0x21007000, 0000000000 },
+    { 0x00005000, 0x00000002 },
+    { 0x00038056, 0x00000002 },
+    { 0x040025e0, 0x00000002 },
+    { 0x000075e1, 0000000000 },
+    { 0x00000001, 0000000000 },
+    { 0x000380ed, 0x00000002 },
+    { 0x04007394, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x000078c4, 0x00000002 },
+    { 0x000078c5, 0x00000002 },
+    { 0x000078c6, 0x00000002 },
+    { 0x00007924, 0x00000002 },
+    { 0x00007925, 0x00000002 },
+    { 0x00007926, 0x00000002 },
+    { 0x000000f2, 0x00000004 },
+    { 0x00007924, 0x00000002 },
+    { 0x00007925, 0x00000002 },
+    { 0x00007926, 0x00000002 },
+    { 0x000000f9, 0x00000004 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+};
+
+static const u32 R300_cp_microcode[][2] = {
+    { 0x4200e000, 0000000000 },
+    { 0x4000e000, 0000000000 },
+    { 0x000000ae, 0x00000008 },
+    { 0x000000b2, 0x00000008 },
+    { 0x67554b4a, 0000000000 },
+    { 0x4a4a4475, 0000000000 },
+    { 0x55527d83, 0000000000 },
+    { 0x4a8c8b65, 0000000000 },
+    { 0x4aef4af6, 0000000000 },
+    { 0x4ae14a4a, 0000000000 },
+    { 0xe4979797, 0000000000 },
+    { 0xdb4aebdd, 0000000000 },
+    { 0x9ccc4a4a, 0000000000 },
+    { 0xd1989898, 0000000000 },
+    { 0x4a0f9ad6, 0000000000 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000d0012, 0x00000038 },
+    { 0x0000e8b4, 0x00000004 },
+    { 0x000d0014, 0x00000038 },
+    { 0x0000e8b6, 0x00000004 },
+    { 0x000d0016, 0x00000038 },
+    { 0x0000e854, 0x00000004 },
+    { 0x000d0018, 0x00000038 },
+    { 0x0000e855, 0x00000004 },
+    { 0x000d001a, 0x00000038 },
+    { 0x0000e856, 0x00000004 },
+    { 0x000d001c, 0x00000038 },
+    { 0x0000e857, 0x00000004 },
+    { 0x000d001e, 0x00000038 },
+    { 0x0000e824, 0x00000004 },
+    { 0x000d0020, 0x00000038 },
+    { 0x0000e825, 0x00000004 },
+    { 0x000d0022, 0x00000038 },
+    { 0x0000e830, 0x00000004 },
+    { 0x000d0024, 0x00000038 },
+    { 0x0000f0c0, 0x00000004 },
+    { 0x000d0026, 0x00000038 },
+    { 0x0000f0c1, 0x00000004 },
+    { 0x000d0028, 0x00000038 },
+    { 0x0000f041, 0x00000004 },
+    { 0x000d002a, 0x00000038 },
+    { 0x0000f184, 0x00000004 },
+    { 0x000d002c, 0x00000038 },
+    { 0x0000f185, 0x00000004 },
+    { 0x000d002e, 0x00000038 },
+    { 0x0000f186, 0x00000004 },
+    { 0x000d0030, 0x00000038 },
+    { 0x0000f187, 0x00000004 },
+    { 0x000d0032, 0x00000038 },
+    { 0x0000f180, 0x00000004 },
+    { 0x000d0034, 0x00000038 },
+    { 0x0000f393, 0x00000004 },
+    { 0x000d0036, 0x00000038 },
+    { 0x0000f38a, 0x00000004 },
+    { 0x000d0038, 0x00000038 },
+    { 0x0000f38e, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000043, 0x00000018 },
+    { 0x00cce800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x0000003a, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x2000451d, 0x00000004 },
+    { 0x0000e580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x08004580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x00000047, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x00032000, 0x00000004 },
+    { 0x00022051, 0x00000028 },
+    { 0x00000051, 0x00000024 },
+    { 0x0800450f, 0x00000004 },
+    { 0x0000a04b, 0x00000008 },
+    { 0x0000e565, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000052, 0x00000008 },
+    { 0x03cca5b4, 0x00000004 },
+    { 0x05432000, 0x00000004 },
+    { 0x00022000, 0x00000004 },
+    { 0x4ccce05e, 0x00000030 },
+    { 0x08274565, 0x00000004 },
+    { 0x0000005e, 0x00000030 },
+    { 0x08004564, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000055, 0x00000008 },
+    { 0x00802061, 0x00000010 },
+    { 0x00202000, 0x00000004 },
+    { 0x001b00ff, 0x00000004 },
+    { 0x01000064, 0x00000010 },
+    { 0x001f2000, 0x00000004 },
+    { 0x001c00ff, 0x00000004 },
+    { 0000000000, 0x0000000c },
+    { 0x00000080, 0x00000030 },
+    { 0x00000055, 0x00000008 },
+    { 0x0000e576, 0x00000004 },
+    { 0x000ca000, 0x00000004 },
+    { 0x00012000, 0x00000004 },
+    { 0x00082000, 0x00000004 },
+    { 0x1800650e, 0x00000004 },
+    { 0x00092000, 0x00000004 },
+    { 0x000a2000, 0x00000004 },
+    { 0x000f0000, 0x00000004 },
+    { 0x00400000, 0x00000004 },
+    { 0x00000074, 0x00000018 },
+    { 0x0000e563, 0x00000004 },
+    { 0x00c0e5f9, 0x000000c2 },
+    { 0x00000069, 0x00000008 },
+    { 0x0000a069, 0x00000008 },
+    { 0x0000e576, 0x00000004 },
+    { 0x0000e577, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x0000e50f, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000077, 0x00000018 },
+    { 0x00c0e5f9, 0x000000c2 },
+    { 0x00000077, 0x00000008 },
+    { 0x0014e50e, 0x00000004 },
+    { 0x0040e50f, 0x00000004 },
+    { 0x00c0007a, 0x00000008 },
+    { 0x0000e570, 0x00000004 },
+    { 0x0000e571, 0x00000004 },
+    { 0x0000e572, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x0000e568, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00000084, 0x00000018 },
+    { 0x000b0000, 0x00000004 },
+    { 0x18c0e562, 0x00000004 },
+    { 0x00000086, 0x00000008 },
+    { 0x00c00085, 0x00000008 },
+    { 0x000700e3, 0x00000004 },
+    { 0x00000092, 0x00000038 },
+    { 0x000ca094, 0x00000030 },
+    { 0x080045bb, 0x00000004 },
+    { 0x000c2095, 0x00000030 },
+    { 0x0800e5bc, 0000000000 },
+    { 0x0000e5bb, 0x00000004 },
+    { 0x0000e5bc, 0000000000 },
+    { 0x00120000, 0x0000000c },
+    { 0x00120000, 0x00000004 },
+    { 0x001b0002, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e800, 0000000000 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e82e, 0000000000 },
+    { 0x02cca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000ce1cc, 0x00000004 },
+    { 0x050de1cd, 0x00000004 },
+    { 0x00400000, 0x00000004 },
+    { 0x000000a4, 0x00000018 },
+    { 0x00c0a000, 0x00000004 },
+    { 0x000000a1, 0x00000008 },
+    { 0x000000a6, 0x00000020 },
+    { 0x4200e000, 0000000000 },
+    { 0x000000ad, 0x00000038 },
+    { 0x000ca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00160000, 0x00000004 },
+    { 0x700ce000, 0x00000004 },
+    { 0x001400a9, 0x00000008 },
+    { 0x4000e000, 0000000000 },
+    { 0x02400000, 0x00000004 },
+    { 0x400ee000, 0x00000004 },
+    { 0x02400000, 0x00000004 },
+    { 0x4000e000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0240e51b, 0x00000004 },
+    { 0x0080e50a, 0x00000005 },
+    { 0x0080e50b, 0x00000005 },
+    { 0x00220000, 0x00000004 },
+    { 0x000700e3, 0x00000004 },
+    { 0x000000c0, 0x00000038 },
+    { 0x000c2095, 0x00000030 },
+    { 0x0880e5bd, 0x00000005 },
+    { 0x000c2094, 0x00000030 },
+    { 0x0800e5bb, 0x00000005 },
+    { 0x000c2095, 0x00000030 },
+    { 0x0880e5bc, 0x00000005 },
+    { 0x000000c3, 0x00000008 },
+    { 0x0080e5bd, 0x00000005 },
+    { 0x0000e5bb, 0x00000005 },
+    { 0x0080e5bc, 0x00000005 },
+    { 0x00210000, 0x00000004 },
+    { 0x02800000, 0x00000004 },
+    { 0x00c000c7, 0x00000018 },
+    { 0x4180e000, 0x00000040 },
+    { 0x000000c9, 0x00000024 },
+    { 0x01000000, 0x0000000c },
+    { 0x0100e51d, 0x0000000c },
+    { 0x000045bb, 0x00000004 },
+    { 0x000080c3, 0x00000008 },
+    { 0x0000f3ce, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053cf, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f3d2, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053d3, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f39d, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c0539e, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x03c00830, 0x00000004 },
+    { 0x4200e000, 0000000000 },
+    { 0x0000a000, 0x00000004 },
+    { 0x200045e0, 0x00000004 },
+    { 0x0000e5e1, 0000000000 },
+    { 0x00000001, 0000000000 },
+    { 0x000700e0, 0x00000004 },
+    { 0x0800e394, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x0000e8c4, 0x00000004 },
+    { 0x0000e8c5, 0x00000004 },
+    { 0x0000e8c6, 0x00000004 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000e4, 0x00000008 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000eb, 0x00000008 },
+    { 0x02c02000, 0x00000004 },
+    { 0x00060000, 0x00000004 },
+    { 0x000000f3, 0x00000034 },
+    { 0x000000f0, 0x00000008 },
+    { 0x00008000, 0x00000004 },
+    { 0xc000e000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x001d0018, 0x00000004 },
+    { 0x001a0001, 0x00000004 },
+    { 0x000000fb, 0x00000034 },
+    { 0x0000004a, 0x00000008 },
+    { 0x0500a04a, 0x00000008 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+};
+
+static const u32 R420_cp_microcode[][2] = {
+    { 0x4200e000, 0000000000 },
+    { 0x4000e000, 0000000000 },
+    { 0x00000099, 0x00000008 },
+    { 0x0000009d, 0x00000008 },
+    { 0x4a554b4a, 0000000000 },
+    { 0x4a4a4467, 0000000000 },
+    { 0x55526f75, 0000000000 },
+    { 0x4a7e7d65, 0000000000 },
+    { 0xd9d3dff6, 0000000000 },
+    { 0x4ac54a4a, 0000000000 },
+    { 0xc8828282, 0000000000 },
+    { 0xbf4acfc1, 0000000000 },
+    { 0x87b04a4a, 0000000000 },
+    { 0xb5838383, 0000000000 },
+    { 0x4a0f85ba, 0000000000 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000d0012, 0x00000038 },
+    { 0x0000e8b4, 0x00000004 },
+    { 0x000d0014, 0x00000038 },
+    { 0x0000e8b6, 0x00000004 },
+    { 0x000d0016, 0x00000038 },
+    { 0x0000e854, 0x00000004 },
+    { 0x000d0018, 0x00000038 },
+    { 0x0000e855, 0x00000004 },
+    { 0x000d001a, 0x00000038 },
+    { 0x0000e856, 0x00000004 },
+    { 0x000d001c, 0x00000038 },
+    { 0x0000e857, 0x00000004 },
+    { 0x000d001e, 0x00000038 },
+    { 0x0000e824, 0x00000004 },
+    { 0x000d0020, 0x00000038 },
+    { 0x0000e825, 0x00000004 },
+    { 0x000d0022, 0x00000038 },
+    { 0x0000e830, 0x00000004 },
+    { 0x000d0024, 0x00000038 },
+    { 0x0000f0c0, 0x00000004 },
+    { 0x000d0026, 0x00000038 },
+    { 0x0000f0c1, 0x00000004 },
+    { 0x000d0028, 0x00000038 },
+    { 0x0000f041, 0x00000004 },
+    { 0x000d002a, 0x00000038 },
+    { 0x0000f184, 0x00000004 },
+    { 0x000d002c, 0x00000038 },
+    { 0x0000f185, 0x00000004 },
+    { 0x000d002e, 0x00000038 },
+    { 0x0000f186, 0x00000004 },
+    { 0x000d0030, 0x00000038 },
+    { 0x0000f187, 0x00000004 },
+    { 0x000d0032, 0x00000038 },
+    { 0x0000f180, 0x00000004 },
+    { 0x000d0034, 0x00000038 },
+    { 0x0000f393, 0x00000004 },
+    { 0x000d0036, 0x00000038 },
+    { 0x0000f38a, 0x00000004 },
+    { 0x000d0038, 0x00000038 },
+    { 0x0000f38e, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000043, 0x00000018 },
+    { 0x00cce800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x0000003a, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x2000451d, 0x00000004 },
+    { 0x0000e580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x08004580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x00000047, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x00032000, 0x00000004 },
+    { 0x00022051, 0x00000028 },
+    { 0x00000051, 0x00000024 },
+    { 0x0800450f, 0x00000004 },
+    { 0x0000a04b, 0x00000008 },
+    { 0x0000e565, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000052, 0x00000008 },
+    { 0x03cca5b4, 0x00000004 },
+    { 0x05432000, 0x00000004 },
+    { 0x00022000, 0x00000004 },
+    { 0x4ccce05e, 0x00000030 },
+    { 0x08274565, 0x00000004 },
+    { 0x0000005e, 0x00000030 },
+    { 0x08004564, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000055, 0x00000008 },
+    { 0x00802061, 0x00000010 },
+    { 0x00202000, 0x00000004 },
+    { 0x001b00ff, 0x00000004 },
+    { 0x01000064, 0x00000010 },
+    { 0x001f2000, 0x00000004 },
+    { 0x001c00ff, 0x00000004 },
+    { 0000000000, 0x0000000c },
+    { 0x00000072, 0x00000030 },
+    { 0x00000055, 0x00000008 },
+    { 0x0000e576, 0x00000004 },
+    { 0x0000e577, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x0000e50f, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000069, 0x00000018 },
+    { 0x00c0e5f9, 0x000000c2 },
+    { 0x00000069, 0x00000008 },
+    { 0x0014e50e, 0x00000004 },
+    { 0x0040e50f, 0x00000004 },
+    { 0x00c0006c, 0x00000008 },
+    { 0x0000e570, 0x00000004 },
+    { 0x0000e571, 0x00000004 },
+    { 0x0000e572, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x0000e568, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00000076, 0x00000018 },
+    { 0x000b0000, 0x00000004 },
+    { 0x18c0e562, 0x00000004 },
+    { 0x00000078, 0x00000008 },
+    { 0x00c00077, 0x00000008 },
+    { 0x000700c7, 0x00000004 },
+    { 0x00000080, 0x00000038 },
+    { 0x0000e5bb, 0x00000004 },
+    { 0x0000e5bc, 0000000000 },
+    { 0x0000a000, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e800, 0000000000 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e82e, 0000000000 },
+    { 0x02cca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000ce1cc, 0x00000004 },
+    { 0x050de1cd, 0x00000004 },
+    { 0x00400000, 0x00000004 },
+    { 0x0000008f, 0x00000018 },
+    { 0x00c0a000, 0x00000004 },
+    { 0x0000008c, 0x00000008 },
+    { 0x00000091, 0x00000020 },
+    { 0x4200e000, 0000000000 },
+    { 0x00000098, 0x00000038 },
+    { 0x000ca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00160000, 0x00000004 },
+    { 0x700ce000, 0x00000004 },
+    { 0x00140094, 0x00000008 },
+    { 0x4000e000, 0000000000 },
+    { 0x02400000, 0x00000004 },
+    { 0x400ee000, 0x00000004 },
+    { 0x02400000, 0x00000004 },
+    { 0x4000e000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0240e51b, 0x00000004 },
+    { 0x0080e50a, 0x00000005 },
+    { 0x0080e50b, 0x00000005 },
+    { 0x00220000, 0x00000004 },
+    { 0x000700c7, 0x00000004 },
+    { 0x000000a4, 0x00000038 },
+    { 0x0080e5bd, 0x00000005 },
+    { 0x0000e5bb, 0x00000005 },
+    { 0x0080e5bc, 0x00000005 },
+    { 0x00210000, 0x00000004 },
+    { 0x02800000, 0x00000004 },
+    { 0x00c000ab, 0x00000018 },
+    { 0x4180e000, 0x00000040 },
+    { 0x000000ad, 0x00000024 },
+    { 0x01000000, 0x0000000c },
+    { 0x0100e51d, 0x0000000c },
+    { 0x000045bb, 0x00000004 },
+    { 0x000080a7, 0x00000008 },
+    { 0x0000f3ce, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053cf, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f3d2, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053d3, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f39d, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c0539e, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x03c00830, 0x00000004 },
+    { 0x4200e000, 0000000000 },
+    { 0x0000a000, 0x00000004 },
+    { 0x200045e0, 0x00000004 },
+    { 0x0000e5e1, 0000000000 },
+    { 0x00000001, 0000000000 },
+    { 0x000700c4, 0x00000004 },
+    { 0x0800e394, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x0000e8c4, 0x00000004 },
+    { 0x0000e8c5, 0x00000004 },
+    { 0x0000e8c6, 0x00000004 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000c8, 0x00000008 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000cf, 0x00000008 },
+    { 0x02c02000, 0x00000004 },
+    { 0x00060000, 0x00000004 },
+    { 0x000000d7, 0x00000034 },
+    { 0x000000d4, 0x00000008 },
+    { 0x00008000, 0x00000004 },
+    { 0xc000e000, 0000000000 },
+    { 0x0000e1cc, 0x00000004 },
+    { 0x0500e1cd, 0x00000004 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000000de, 0x00000034 },
+    { 0x000000da, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x0019e1cc, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x0500a000, 0x00000004 },
+    { 0x080041cd, 0x00000004 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000000fb, 0x00000034 },
+    { 0x0000004a, 0x00000008 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x001d0018, 0x00000004 },
+    { 0x001a0001, 0x00000004 },
+    { 0x000000fb, 0x00000034 },
+    { 0x0000004a, 0x00000008 },
+    { 0x0500a04a, 0x00000008 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+};
+
+static const u32 RS600_cp_microcode[][2] = {
+    { 0x4200e000, 0000000000 },
+    { 0x4000e000, 0000000000 },
+    { 0x000000a0, 0x00000008 },
+    { 0x000000a4, 0x00000008 },
+    { 0x4a554b4a, 0000000000 },
+    { 0x4a4a4467, 0000000000 },
+    { 0x55526f75, 0000000000 },
+    { 0x4a7e7d65, 0000000000 },
+    { 0x4ae74af6, 0000000000 },
+    { 0x4ad34a4a, 0000000000 },
+    { 0xd6898989, 0000000000 },
+    { 0xcd4addcf, 0000000000 },
+    { 0x8ebe4ae2, 0000000000 },
+    { 0xc38a8a8a, 0000000000 },
+    { 0x4a0f8cc8, 0000000000 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000d0012, 0x00000038 },
+    { 0x0000e8b4, 0x00000004 },
+    { 0x000d0014, 0x00000038 },
+    { 0x0000e8b6, 0x00000004 },
+    { 0x000d0016, 0x00000038 },
+    { 0x0000e854, 0x00000004 },
+    { 0x000d0018, 0x00000038 },
+    { 0x0000e855, 0x00000004 },
+    { 0x000d001a, 0x00000038 },
+    { 0x0000e856, 0x00000004 },
+    { 0x000d001c, 0x00000038 },
+    { 0x0000e857, 0x00000004 },
+    { 0x000d001e, 0x00000038 },
+    { 0x0000e824, 0x00000004 },
+    { 0x000d0020, 0x00000038 },
+    { 0x0000e825, 0x00000004 },
+    { 0x000d0022, 0x00000038 },
+    { 0x0000e830, 0x00000004 },
+    { 0x000d0024, 0x00000038 },
+    { 0x0000f0c0, 0x00000004 },
+    { 0x000d0026, 0x00000038 },
+    { 0x0000f0c1, 0x00000004 },
+    { 0x000d0028, 0x00000038 },
+    { 0x0000f041, 0x00000004 },
+    { 0x000d002a, 0x00000038 },
+    { 0x0000f184, 0x00000004 },
+    { 0x000d002c, 0x00000038 },
+    { 0x0000f185, 0x00000004 },
+    { 0x000d002e, 0x00000038 },
+    { 0x0000f186, 0x00000004 },
+    { 0x000d0030, 0x00000038 },
+    { 0x0000f187, 0x00000004 },
+    { 0x000d0032, 0x00000038 },
+    { 0x0000f180, 0x00000004 },
+    { 0x000d0034, 0x00000038 },
+    { 0x0000f393, 0x00000004 },
+    { 0x000d0036, 0x00000038 },
+    { 0x0000f38a, 0x00000004 },
+    { 0x000d0038, 0x00000038 },
+    { 0x0000f38e, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000043, 0x00000018 },
+    { 0x00cce800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x0000003a, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x2000451d, 0x00000004 },
+    { 0x0000e580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x08004580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x00000047, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x00032000, 0x00000004 },
+    { 0x00022051, 0x00000028 },
+    { 0x00000051, 0x00000024 },
+    { 0x0800450f, 0x00000004 },
+    { 0x0000a04b, 0x00000008 },
+    { 0x0000e565, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000052, 0x00000008 },
+    { 0x03cca5b4, 0x00000004 },
+    { 0x05432000, 0x00000004 },
+    { 0x00022000, 0x00000004 },
+    { 0x4ccce05e, 0x00000030 },
+    { 0x08274565, 0x00000004 },
+    { 0x0000005e, 0x00000030 },
+    { 0x08004564, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000055, 0x00000008 },
+    { 0x00802061, 0x00000010 },
+    { 0x00202000, 0x00000004 },
+    { 0x001b00ff, 0x00000004 },
+    { 0x01000064, 0x00000010 },
+    { 0x001f2000, 0x00000004 },
+    { 0x001c00ff, 0x00000004 },
+    { 0000000000, 0x0000000c },
+    { 0x00000072, 0x00000030 },
+    { 0x00000055, 0x00000008 },
+    { 0x0000e576, 0x00000004 },
+    { 0x0000e577, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x0000e50f, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000069, 0x00000018 },
+    { 0x00c0e5f9, 0x000000c2 },
+    { 0x00000069, 0x00000008 },
+    { 0x0014e50e, 0x00000004 },
+    { 0x0040e50f, 0x00000004 },
+    { 0x00c0006c, 0x00000008 },
+    { 0x0000e570, 0x00000004 },
+    { 0x0000e571, 0x00000004 },
+    { 0x0000e572, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x0000e568, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00000076, 0x00000018 },
+    { 0x000b0000, 0x00000004 },
+    { 0x18c0e562, 0x00000004 },
+    { 0x00000078, 0x00000008 },
+    { 0x00c00077, 0x00000008 },
+    { 0x000700d5, 0x00000004 },
+    { 0x00000084, 0x00000038 },
+    { 0x000ca086, 0x00000030 },
+    { 0x080045bb, 0x00000004 },
+    { 0x000c2087, 0x00000030 },
+    { 0x0800e5bc, 0000000000 },
+    { 0x0000e5bb, 0x00000004 },
+    { 0x0000e5bc, 0000000000 },
+    { 0x00120000, 0x0000000c },
+    { 0x00120000, 0x00000004 },
+    { 0x001b0002, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e800, 0000000000 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e82e, 0000000000 },
+    { 0x02cca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000ce1cc, 0x00000004 },
+    { 0x050de1cd, 0x00000004 },
+    { 0x00400000, 0x00000004 },
+    { 0x00000096, 0x00000018 },
+    { 0x00c0a000, 0x00000004 },
+    { 0x00000093, 0x00000008 },
+    { 0x00000098, 0x00000020 },
+    { 0x4200e000, 0000000000 },
+    { 0x0000009f, 0x00000038 },
+    { 0x000ca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00160000, 0x00000004 },
+    { 0x700ce000, 0x00000004 },
+    { 0x0014009b, 0x00000008 },
+    { 0x4000e000, 0000000000 },
+    { 0x02400000, 0x00000004 },
+    { 0x400ee000, 0x00000004 },
+    { 0x02400000, 0x00000004 },
+    { 0x4000e000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0240e51b, 0x00000004 },
+    { 0x0080e50a, 0x00000005 },
+    { 0x0080e50b, 0x00000005 },
+    { 0x00220000, 0x00000004 },
+    { 0x000700d5, 0x00000004 },
+    { 0x000000b2, 0x00000038 },
+    { 0x000c2087, 0x00000030 },
+    { 0x0880e5bd, 0x00000005 },
+    { 0x000c2086, 0x00000030 },
+    { 0x0800e5bb, 0x00000005 },
+    { 0x000c2087, 0x00000030 },
+    { 0x0880e5bc, 0x00000005 },
+    { 0x000000b5, 0x00000008 },
+    { 0x0080e5bd, 0x00000005 },
+    { 0x0000e5bb, 0x00000005 },
+    { 0x0080e5bc, 0x00000005 },
+    { 0x00210000, 0x00000004 },
+    { 0x02800000, 0x00000004 },
+    { 0x00c000b9, 0x00000018 },
+    { 0x4180e000, 0x00000040 },
+    { 0x000000bb, 0x00000024 },
+    { 0x01000000, 0x0000000c },
+    { 0x0100e51d, 0x0000000c },
+    { 0x000045bb, 0x00000004 },
+    { 0x000080b5, 0x00000008 },
+    { 0x0000f3ce, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053cf, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f3d2, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053d3, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f39d, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c0539e, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x03c00830, 0x00000004 },
+    { 0x4200e000, 0000000000 },
+    { 0x0000a000, 0x00000004 },
+    { 0x200045e0, 0x00000004 },
+    { 0x0000e5e1, 0000000000 },
+    { 0x00000001, 0000000000 },
+    { 0x000700d2, 0x00000004 },
+    { 0x0800e394, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x0000e8c4, 0x00000004 },
+    { 0x0000e8c5, 0x00000004 },
+    { 0x0000e8c6, 0x00000004 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000d6, 0x00000008 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000dd, 0x00000008 },
+    { 0x00e00116, 0000000000 },
+    { 0x000700e1, 0x00000004 },
+    { 0x0800401c, 0x00000004 },
+    { 0x200050e7, 0x00000004 },
+    { 0x0000e01d, 0x00000004 },
+    { 0x000000e4, 0x00000008 },
+    { 0x02c02000, 0x00000004 },
+    { 0x00060000, 0x00000004 },
+    { 0x000000eb, 0x00000034 },
+    { 0x000000e8, 0x00000008 },
+    { 0x00008000, 0x00000004 },
+    { 0xc000e000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x001d0018, 0x00000004 },
+    { 0x001a0001, 0x00000004 },
+    { 0x000000fb, 0x00000034 },
+    { 0x0000004a, 0x00000008 },
+    { 0x0500a04a, 0x00000008 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+};
+
+static const u32 RS690_cp_microcode[][2] = {
+    { 0x000000dd, 0x00000008 },
+    { 0x000000df, 0x00000008 },
+    { 0x000000a0, 0x00000008 },
+    { 0x000000a4, 0x00000008 },
+    { 0x4a554b4a, 0000000000 },
+    { 0x4a4a4467, 0000000000 },
+    { 0x55526f75, 0000000000 },
+    { 0x4a7e7d65, 0000000000 },
+    { 0x4ad74af6, 0000000000 },
+    { 0x4ac94a4a, 0000000000 },
+    { 0xcc898989, 0000000000 },
+    { 0xc34ad3c5, 0000000000 },
+    { 0x8e4a4a4a, 0000000000 },
+    { 0x4a8a8a8a, 0000000000 },
+    { 0x4a0f8c4a, 0000000000 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000d0012, 0x00000038 },
+    { 0x0000e8b4, 0x00000004 },
+    { 0x000d0014, 0x00000038 },
+    { 0x0000e8b6, 0x00000004 },
+    { 0x000d0016, 0x00000038 },
+    { 0x0000e854, 0x00000004 },
+    { 0x000d0018, 0x00000038 },
+    { 0x0000e855, 0x00000004 },
+    { 0x000d001a, 0x00000038 },
+    { 0x0000e856, 0x00000004 },
+    { 0x000d001c, 0x00000038 },
+    { 0x0000e857, 0x00000004 },
+    { 0x000d001e, 0x00000038 },
+    { 0x0000e824, 0x00000004 },
+    { 0x000d0020, 0x00000038 },
+    { 0x0000e825, 0x00000004 },
+    { 0x000d0022, 0x00000038 },
+    { 0x0000e830, 0x00000004 },
+    { 0x000d0024, 0x00000038 },
+    { 0x0000f0c0, 0x00000004 },
+    { 0x000d0026, 0x00000038 },
+    { 0x0000f0c1, 0x00000004 },
+    { 0x000d0028, 0x00000038 },
+    { 0x0000f041, 0x00000004 },
+    { 0x000d002a, 0x00000038 },
+    { 0x0000f184, 0x00000004 },
+    { 0x000d002c, 0x00000038 },
+    { 0x0000f185, 0x00000004 },
+    { 0x000d002e, 0x00000038 },
+    { 0x0000f186, 0x00000004 },
+    { 0x000d0030, 0x00000038 },
+    { 0x0000f187, 0x00000004 },
+    { 0x000d0032, 0x00000038 },
+    { 0x0000f180, 0x00000004 },
+    { 0x000d0034, 0x00000038 },
+    { 0x0000f393, 0x00000004 },
+    { 0x000d0036, 0x00000038 },
+    { 0x0000f38a, 0x00000004 },
+    { 0x000d0038, 0x00000038 },
+    { 0x0000f38e, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000043, 0x00000018 },
+    { 0x00cce800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x0000003a, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x2000451d, 0x00000004 },
+    { 0x0000e580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x08004580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x00000047, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x00032000, 0x00000004 },
+    { 0x00022051, 0x00000028 },
+    { 0x00000051, 0x00000024 },
+    { 0x0800450f, 0x00000004 },
+    { 0x0000a04b, 0x00000008 },
+    { 0x0000e565, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000052, 0x00000008 },
+    { 0x03cca5b4, 0x00000004 },
+    { 0x05432000, 0x00000004 },
+    { 0x00022000, 0x00000004 },
+    { 0x4ccce05e, 0x00000030 },
+    { 0x08274565, 0x00000004 },
+    { 0x0000005e, 0x00000030 },
+    { 0x08004564, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000055, 0x00000008 },
+    { 0x00802061, 0x00000010 },
+    { 0x00202000, 0x00000004 },
+    { 0x001b00ff, 0x00000004 },
+    { 0x01000064, 0x00000010 },
+    { 0x001f2000, 0x00000004 },
+    { 0x001c00ff, 0x00000004 },
+    { 0000000000, 0x0000000c },
+    { 0x00000072, 0x00000030 },
+    { 0x00000055, 0x00000008 },
+    { 0x0000e576, 0x00000004 },
+    { 0x0000e577, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x0000e50f, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000069, 0x00000018 },
+    { 0x00c0e5f9, 0x000000c2 },
+    { 0x00000069, 0x00000008 },
+    { 0x0014e50e, 0x00000004 },
+    { 0x0040e50f, 0x00000004 },
+    { 0x00c0006c, 0x00000008 },
+    { 0x0000e570, 0x00000004 },
+    { 0x0000e571, 0x00000004 },
+    { 0x0000e572, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x0000e568, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00000076, 0x00000018 },
+    { 0x000b0000, 0x00000004 },
+    { 0x18c0e562, 0x00000004 },
+    { 0x00000078, 0x00000008 },
+    { 0x00c00077, 0x00000008 },
+    { 0x000700cb, 0x00000004 },
+    { 0x00000084, 0x00000038 },
+    { 0x000ca086, 0x00000030 },
+    { 0x080045bb, 0x00000004 },
+    { 0x000c2087, 0x00000030 },
+    { 0x0800e5bc, 0000000000 },
+    { 0x0000e5bb, 0x00000004 },
+    { 0x0000e5bc, 0000000000 },
+    { 0x00120000, 0x0000000c },
+    { 0x00120000, 0x00000004 },
+    { 0x001b0002, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e800, 0000000000 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e82e, 0000000000 },
+    { 0x02cca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000ce1cc, 0x00000004 },
+    { 0x050de1cd, 0x00000004 },
+    { 0x00400000, 0x00000004 },
+    { 0x00000096, 0x00000018 },
+    { 0x00c0a000, 0x00000004 },
+    { 0x00000093, 0x00000008 },
+    { 0x00000098, 0x00000020 },
+    { 0x4200e000, 0000000000 },
+    { 0x0000009f, 0x00000038 },
+    { 0x000ca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00160000, 0x00000004 },
+    { 0x700ce000, 0x00000004 },
+    { 0x0014009b, 0x00000008 },
+    { 0x4000e000, 0000000000 },
+    { 0x02400000, 0x00000004 },
+    { 0x400ee000, 0x00000004 },
+    { 0x02400000, 0x00000004 },
+    { 0x4000e000, 0000000000 },
+    { 0x00100000, 0x0000002c },
+    { 0x00004000, 0000000000 },
+    { 0x080045c8, 0x00000004 },
+    { 0x00240005, 0x00000004 },
+    { 0x08004d0b, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0240e51b, 0x00000004 },
+    { 0x0080e50a, 0x00000005 },
+    { 0x0080e50b, 0x00000005 },
+    { 0x00220000, 0x00000004 },
+    { 0x000700cb, 0x00000004 },
+    { 0x000000b7, 0x00000038 },
+    { 0x000c2087, 0x00000030 },
+    { 0x0880e5bd, 0x00000005 },
+    { 0x000c2086, 0x00000030 },
+    { 0x0800e5bb, 0x00000005 },
+    { 0x000c2087, 0x00000030 },
+    { 0x0880e5bc, 0x00000005 },
+    { 0x000000ba, 0x00000008 },
+    { 0x0080e5bd, 0x00000005 },
+    { 0x0000e5bb, 0x00000005 },
+    { 0x0080e5bc, 0x00000005 },
+    { 0x00210000, 0x00000004 },
+    { 0x02800000, 0x00000004 },
+    { 0x00c000be, 0x00000018 },
+    { 0x4180e000, 0x00000040 },
+    { 0x000000c0, 0x00000024 },
+    { 0x01000000, 0x0000000c },
+    { 0x0100e51d, 0x0000000c },
+    { 0x000045bb, 0x00000004 },
+    { 0x000080ba, 0x00000008 },
+    { 0x03c00830, 0x00000004 },
+    { 0x4200e000, 0000000000 },
+    { 0x0000a000, 0x00000004 },
+    { 0x200045e0, 0x00000004 },
+    { 0x0000e5e1, 0000000000 },
+    { 0x00000001, 0000000000 },
+    { 0x000700c8, 0x00000004 },
+    { 0x0800e394, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x0000e8c4, 0x00000004 },
+    { 0x0000e8c5, 0x00000004 },
+    { 0x0000e8c6, 0x00000004 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000cc, 0x00000008 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000d3, 0x00000008 },
+    { 0x02c02000, 0x00000004 },
+    { 0x00060000, 0x00000004 },
+    { 0x000000db, 0x00000034 },
+    { 0x000000d8, 0x00000008 },
+    { 0x00008000, 0x00000004 },
+    { 0xc000e000, 0000000000 },
+    { 0x000000e1, 0x00000030 },
+    { 0x4200e000, 0000000000 },
+    { 0x000000e1, 0x00000030 },
+    { 0x4000e000, 0000000000 },
+    { 0x0025001b, 0x00000004 },
+    { 0x00230000, 0x00000004 },
+    { 0x00250005, 0x00000004 },
+    { 0x000000e6, 0x00000034 },
+    { 0000000000, 0x0000000c },
+    { 0x00244000, 0x00000004 },
+    { 0x080045c8, 0x00000004 },
+    { 0x00240005, 0x00000004 },
+    { 0x08004d0b, 0x0000000c },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x001d0018, 0x00000004 },
+    { 0x001a0001, 0x00000004 },
+    { 0x000000fb, 0x00000034 },
+    { 0x0000004a, 0x00000008 },
+    { 0x0500a04a, 0x00000008 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+};
+
+static const u32 R520_cp_microcode[][2] = {
+    { 0x4200e000, 0000000000 },
+    { 0x4000e000, 0000000000 },
+    { 0x00000099, 0x00000008 },
+    { 0x0000009d, 0x00000008 },
+    { 0x4a554b4a, 0000000000 },
+    { 0x4a4a4467, 0000000000 },
+    { 0x55526f75, 0000000000 },
+    { 0x4a7e7d65, 0000000000 },
+    { 0xe0dae6f6, 0000000000 },
+    { 0x4ac54a4a, 0000000000 },
+    { 0xc8828282, 0000000000 },
+    { 0xbf4acfc1, 0000000000 },
+    { 0x87b04ad5, 0000000000 },
+    { 0xb5838383, 0000000000 },
+    { 0x4a0f85ba, 0000000000 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000d0012, 0x00000038 },
+    { 0x0000e8b4, 0x00000004 },
+    { 0x000d0014, 0x00000038 },
+    { 0x0000e8b6, 0x00000004 },
+    { 0x000d0016, 0x00000038 },
+    { 0x0000e854, 0x00000004 },
+    { 0x000d0018, 0x00000038 },
+    { 0x0000e855, 0x00000004 },
+    { 0x000d001a, 0x00000038 },
+    { 0x0000e856, 0x00000004 },
+    { 0x000d001c, 0x00000038 },
+    { 0x0000e857, 0x00000004 },
+    { 0x000d001e, 0x00000038 },
+    { 0x0000e824, 0x00000004 },
+    { 0x000d0020, 0x00000038 },
+    { 0x0000e825, 0x00000004 },
+    { 0x000d0022, 0x00000038 },
+    { 0x0000e830, 0x00000004 },
+    { 0x000d0024, 0x00000038 },
+    { 0x0000f0c0, 0x00000004 },
+    { 0x000d0026, 0x00000038 },
+    { 0x0000f0c1, 0x00000004 },
+    { 0x000d0028, 0x00000038 },
+    { 0x0000e000, 0x00000004 },
+    { 0x000d002a, 0x00000038 },
+    { 0x0000e000, 0x00000004 },
+    { 0x000d002c, 0x00000038 },
+    { 0x0000e000, 0x00000004 },
+    { 0x000d002e, 0x00000038 },
+    { 0x0000e000, 0x00000004 },
+    { 0x000d0030, 0x00000038 },
+    { 0x0000e000, 0x00000004 },
+    { 0x000d0032, 0x00000038 },
+    { 0x0000f180, 0x00000004 },
+    { 0x000d0034, 0x00000038 },
+    { 0x0000f393, 0x00000004 },
+    { 0x000d0036, 0x00000038 },
+    { 0x0000f38a, 0x00000004 },
+    { 0x000d0038, 0x00000038 },
+    { 0x0000f38e, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000043, 0x00000018 },
+    { 0x00cce800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x0000003a, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x2000451d, 0x00000004 },
+    { 0x0000e580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x08004580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x00000047, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x00032000, 0x00000004 },
+    { 0x00022051, 0x00000028 },
+    { 0x00000051, 0x00000024 },
+    { 0x0800450f, 0x00000004 },
+    { 0x0000a04b, 0x00000008 },
+    { 0x0000e565, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000052, 0x00000008 },
+    { 0x03cca5b4, 0x00000004 },
+    { 0x05432000, 0x00000004 },
+    { 0x00022000, 0x00000004 },
+    { 0x4ccce05e, 0x00000030 },
+    { 0x08274565, 0x00000004 },
+    { 0x0000005e, 0x00000030 },
+    { 0x08004564, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000055, 0x00000008 },
+    { 0x00802061, 0x00000010 },
+    { 0x00202000, 0x00000004 },
+    { 0x001b00ff, 0x00000004 },
+    { 0x01000064, 0x00000010 },
+    { 0x001f2000, 0x00000004 },
+    { 0x001c00ff, 0x00000004 },
+    { 0000000000, 0x0000000c },
+    { 0x00000072, 0x00000030 },
+    { 0x00000055, 0x00000008 },
+    { 0x0000e576, 0x00000004 },
+    { 0x0000e577, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x0000e50f, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000069, 0x00000018 },
+    { 0x00c0e5f9, 0x000000c2 },
+    { 0x00000069, 0x00000008 },
+    { 0x0014e50e, 0x00000004 },
+    { 0x0040e50f, 0x00000004 },
+    { 0x00c0006c, 0x00000008 },
+    { 0x0000e570, 0x00000004 },
+    { 0x0000e571, 0x00000004 },
+    { 0x0000e572, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x0000e568, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00000076, 0x00000018 },
+    { 0x000b0000, 0x00000004 },
+    { 0x18c0e562, 0x00000004 },
+    { 0x00000078, 0x00000008 },
+    { 0x00c00077, 0x00000008 },
+    { 0x000700c7, 0x00000004 },
+    { 0x00000080, 0x00000038 },
+    { 0x0000e5bb, 0x00000004 },
+    { 0x0000e5bc, 0000000000 },
+    { 0x0000a000, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e800, 0000000000 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e82e, 0000000000 },
+    { 0x02cca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000ce1cc, 0x00000004 },
+    { 0x050de1cd, 0x00000004 },
+    { 0x00400000, 0x00000004 },
+    { 0x0000008f, 0x00000018 },
+    { 0x00c0a000, 0x00000004 },
+    { 0x0000008c, 0x00000008 },
+    { 0x00000091, 0x00000020 },
+    { 0x4200e000, 0000000000 },
+    { 0x00000098, 0x00000038 },
+    { 0x000ca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00160000, 0x00000004 },
+    { 0x700ce000, 0x00000004 },
+    { 0x00140094, 0x00000008 },
+    { 0x4000e000, 0000000000 },
+    { 0x02400000, 0x00000004 },
+    { 0x400ee000, 0x00000004 },
+    { 0x02400000, 0x00000004 },
+    { 0x4000e000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0240e51b, 0x00000004 },
+    { 0x0080e50a, 0x00000005 },
+    { 0x0080e50b, 0x00000005 },
+    { 0x00220000, 0x00000004 },
+    { 0x000700c7, 0x00000004 },
+    { 0x000000a4, 0x00000038 },
+    { 0x0080e5bd, 0x00000005 },
+    { 0x0000e5bb, 0x00000005 },
+    { 0x0080e5bc, 0x00000005 },
+    { 0x00210000, 0x00000004 },
+    { 0x02800000, 0x00000004 },
+    { 0x00c000ab, 0x00000018 },
+    { 0x4180e000, 0x00000040 },
+    { 0x000000ad, 0x00000024 },
+    { 0x01000000, 0x0000000c },
+    { 0x0100e51d, 0x0000000c },
+    { 0x000045bb, 0x00000004 },
+    { 0x000080a7, 0x00000008 },
+    { 0x0000f3ce, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053cf, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f3d2, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053d3, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f39d, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c0539e, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x03c00830, 0x00000004 },
+    { 0x4200e000, 0000000000 },
+    { 0x0000a000, 0x00000004 },
+    { 0x200045e0, 0x00000004 },
+    { 0x0000e5e1, 0000000000 },
+    { 0x00000001, 0000000000 },
+    { 0x000700c4, 0x00000004 },
+    { 0x0800e394, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x0000e8c4, 0x00000004 },
+    { 0x0000e8c5, 0x00000004 },
+    { 0x0000e8c6, 0x00000004 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000c8, 0x00000008 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000cf, 0x00000008 },
+    { 0xdeadbeef, 0000000000 },
+    { 0x00000116, 0000000000 },
+    { 0x000700d3, 0x00000004 },
+    { 0x080050e7, 0x00000004 },
+    { 0x000700d4, 0x00000004 },
+    { 0x0800401c, 0x00000004 },
+    { 0x0000e01d, 0000000000 },
+    { 0x02c02000, 0x00000004 },
+    { 0x00060000, 0x00000004 },
+    { 0x000000de, 0x00000034 },
+    { 0x000000db, 0x00000008 },
+    { 0x00008000, 0x00000004 },
+    { 0xc000e000, 0000000000 },
+    { 0x0000e1cc, 0x00000004 },
+    { 0x0500e1cd, 0x00000004 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000000e5, 0x00000034 },
+    { 0x000000e1, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x0019e1cc, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x0500a000, 0x00000004 },
+    { 0x080041cd, 0x00000004 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000000fb, 0x00000034 },
+    { 0x0000004a, 0x00000008 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x001d0018, 0x00000004 },
+    { 0x001a0001, 0x00000004 },
+    { 0x000000fb, 0x00000034 },
+    { 0x0000004a, 0x00000008 },
+    { 0x0500a04a, 0x00000008 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+};
+
+
+#endif
diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c
index 6f75512f591e..11c146b49211 100644
--- a/drivers/char/drm/radeon_state.c
+++ b/drivers/char/drm/radeon_state.c
@@ -1662,7 +1662,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
         u32 height;
         int i;
         u32 texpitch, microtile;
-        u32 offset;
+        u32 offset, byte_offset;
         RING_LOCALS;
 
         if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) {
@@ -1727,6 +1727,13 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
         } else
                 microtile = 0;
 
+        /* this might fail for zero-sized uploads - are those illegal? */
+        if (!radeon_check_offset(dev_priv, tex->offset + image->height *
+                                blit_width - 1)) {
+                DRM_ERROR("Invalid final destination offset\n");
+                return -EINVAL;
+        }
+
         DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
 
         do {
@@ -1840,6 +1847,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
                 }
 
 #undef RADEON_COPY_MT
+                byte_offset = (image->y & ~2047) * blit_width;
                 buf->file_priv = file_priv;
                 buf->used = size;
                 offset = dev_priv->gart_buffers_offset + buf->offset;
@@ -1854,9 +1862,9 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
                          RADEON_DP_SRC_SOURCE_MEMORY |
                          RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
                 OUT_RING((spitch << 22) | (offset >> 10));
-                OUT_RING((texpitch << 22) | (tex->offset >> 10));
+                OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10)));
                 OUT_RING(0);
-                OUT_RING((image->x << 16) | image->y);
+                OUT_RING((image->x << 16) | (image->y % 2048));
                 OUT_RING((image->width << 16) | height);
                 RADEON_WAIT_UNTIL_2D_IDLE();
                 ADVANCE_RING();
@@ -3037,6 +3045,9 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
         case RADEON_PARAM_FB_LOCATION:
                 value = radeon_read_fb_location(dev_priv);
                 break;
+        case RADEON_PARAM_NUM_GB_PIPES:
+                value = dev_priv->num_gb_pipes;
+                break;
         default:
                 DRM_DEBUG("Invalid parameter %d\n", param->param);
                 return -EINVAL;
diff --git a/drivers/firewire/Kconfig b/drivers/firewire/Kconfig
index fb4d391810b6..76f26710fc16 100644
--- a/drivers/firewire/Kconfig
+++ b/drivers/firewire/Kconfig
@@ -1,28 +1,26 @@
-comment "An alternative FireWire stack is available with EXPERIMENTAL=y"
+comment "A new alternative FireWire stack is available with EXPERIMENTAL=y"
         depends on EXPERIMENTAL=n
 
+comment "Enable only one of the two stacks, unless you know what you are doing"
+        depends on EXPERIMENTAL
+
 config FIREWIRE
-        tristate "IEEE 1394 (FireWire) support - alternative stack, EXPERIMENTAL"
+        tristate "New FireWire stack, EXPERIMENTAL"
         depends on EXPERIMENTAL
         select CRC_ITU_T
         help
           This is the "Juju" FireWire stack, a new alternative implementation
           designed for robustness and simplicity.  You can build either this
-          stack, or the classic stack (the ieee1394 driver, ohci1394 etc.)
-          or both.  Please read http://wiki.linux1394.org/JujuMigration before
-          you enable the new stack.
+          stack, or the old stack (the ieee1394 driver, ohci1394 etc.) or both.
+          Please read http://wiki.linux1394.org/JujuMigration before you
+          enable the new stack.
 
           To compile this driver as a module, say M here: the module will be
           called firewire-core.  It functionally replaces ieee1394, raw1394,
           and video1394.
 
-          NOTE:
-
-          You should only build ONE of the stacks, unless you REALLY know what
-          you are doing.
-
 config FIREWIRE_OHCI
-        tristate "Support for OHCI FireWire host controllers"
+        tristate "OHCI-1394 controllers"
         depends on PCI && FIREWIRE
         help
           Enable this driver if you have a FireWire controller based
@@ -33,12 +31,12 @@ config FIREWIRE_OHCI
           called firewire-ohci.  It replaces ohci1394 of the classic IEEE 1394
           stack.
 
-          NOTE:
+          NOTE:
 
-          You should only build ohci1394 or firewire-ohci, but not both.
-          If you nevertheless want to install both, you should configure them
-          only as modules and blacklist the driver(s) which you don't want to
-          have auto-loaded.  Add either
+          You should only build either firewire-ohci or the old ohci1394 driver,
+          but not both.  If you nevertheless want to install both, you should
+          configure them only as modules and blacklist the driver(s) which you
+          don't want to have auto-loaded.  Add either
 
               blacklist firewire-ohci
           or
@@ -60,7 +58,7 @@ config FIREWIRE_OHCI_DEBUG
         default y
 
 config FIREWIRE_SBP2
-        tristate "Support for storage devices (SBP-2 protocol driver)"
+        tristate "Storage devices (SBP-2 protocol)"
         depends on FIREWIRE && SCSI
         help
           This option enables you to use SBP-2 devices connected to a
diff --git a/drivers/firewire/fw-cdev.c b/drivers/firewire/fw-cdev.c
index dda14015e873..c639915fc3cb 100644
--- a/drivers/firewire/fw-cdev.c
+++ b/drivers/firewire/fw-cdev.c
@@ -205,6 +205,7 @@ fw_device_op_read(struct file *file,
         return dequeue_event(client, buffer, count);
 }
 
+/* caller must hold card->lock so that node pointers can be dereferenced here */
 static void
 fill_bus_reset_event(struct fw_cdev_event_bus_reset *event,
                      struct client *client)
@@ -214,7 +215,6 @@ fill_bus_reset_event(struct fw_cdev_event_bus_reset *event,
         event->closure       = client->bus_reset_closure;
         event->type          = FW_CDEV_EVENT_BUS_RESET;
         event->generation    = client->device->generation;
-        smp_rmb();           /* node_id must not be older than generation */
         event->node_id       = client->device->node_id;
         event->local_node_id = card->local_node->node_id;
         event->bm_node_id    = 0; /* FIXME: We don't track the BM. */
@@ -274,6 +274,7 @@ static int ioctl_get_info(struct client *client, void *buffer)
 {
         struct fw_cdev_get_info *get_info = buffer;
         struct fw_cdev_event_bus_reset bus_reset;
+        struct fw_card *card = client->device->card;
         unsigned long ret = 0;
 
         client->version = get_info->version;
@@ -299,13 +300,17 @@ static int ioctl_get_info(struct client *client, void *buffer)
         client->bus_reset_closure = get_info->bus_reset_closure;
         if (get_info->bus_reset != 0) {
                 void __user *uptr = u64_to_uptr(get_info->bus_reset);
+                unsigned long flags;
 
+                spin_lock_irqsave(&card->lock, flags);
                 fill_bus_reset_event(&bus_reset, client);
+                spin_unlock_irqrestore(&card->lock, flags);
+
                 if (copy_to_user(uptr, &bus_reset, sizeof(bus_reset)))
                         return -EFAULT;
         }
 
-        get_info->card = client->device->card->index;
+        get_info->card = card->index;
 
         return 0;
 }
diff --git a/drivers/firewire/fw-ohci.c b/drivers/firewire/fw-ohci.c
index 4f02c55f13e1..0b66306af479 100644
--- a/drivers/firewire/fw-ohci.c
+++ b/drivers/firewire/fw-ohci.c
@@ -265,27 +265,25 @@ static void log_irqs(u32 evt)
             !(evt & OHCI1394_busReset))
                 return;
 
-        printk(KERN_DEBUG KBUILD_MODNAME ": IRQ "
-               "%08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
-               evt,
-               evt & OHCI1394_selfIDComplete    ? " selfID"             : "",
-               evt & OHCI1394_RQPkt             ? " AR_req"             : "",
-               evt & OHCI1394_RSPkt             ? " AR_resp"            : "",
-               evt & OHCI1394_reqTxComplete     ? " AT_req"             : "",
-               evt & OHCI1394_respTxComplete    ? " AT_resp"            : "",
-               evt & OHCI1394_isochRx           ? " IR"                 : "",
-               evt & OHCI1394_isochTx           ? " IT"                 : "",
-               evt & OHCI1394_postedWriteErr    ? " postedWriteErr"     : "",
-               evt & OHCI1394_cycleTooLong      ? " cycleTooLong"       : "",
-               evt & OHCI1394_cycle64Seconds    ? " cycle64Seconds"     : "",
-               evt & OHCI1394_regAccessFail     ? " regAccessFail"      : "",
-               evt & OHCI1394_busReset          ? " busReset"           : "",
-               evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
-                       OHCI1394_RSPkt | OHCI1394_reqTxComplete |
-                       OHCI1394_respTxComplete | OHCI1394_isochRx |
-                       OHCI1394_isochTx | OHCI1394_postedWriteErr |
-                       OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
-                       OHCI1394_regAccessFail | OHCI1394_busReset)
+        fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
+            evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
+            evt & OHCI1394_RQPkt                ? " AR_req"             : "",
+            evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
+            evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
+            evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
+            evt & OHCI1394_isochRx              ? " IR"                 : "",
+            evt & OHCI1394_isochTx              ? " IT"                 : "",
+            evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
+            evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
+            evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
+            evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
+            evt & OHCI1394_busReset             ? " busReset"           : "",
+            evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
+                    OHCI1394_RSPkt | OHCI1394_reqTxComplete |
+                    OHCI1394_respTxComplete | OHCI1394_isochRx |
+                    OHCI1394_isochTx | OHCI1394_postedWriteErr |
+                    OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
+                    OHCI1394_regAccessFail | OHCI1394_busReset)
                                                 ? " ?"                  : "");
 }
 
@@ -308,23 +306,22 @@ static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
                 return;
 
-        printk(KERN_DEBUG KBUILD_MODNAME ": %d selfIDs, generation %d, "
-               "local node ID %04x\n", self_id_count, generation, node_id);
+        fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
+                  self_id_count, generation, node_id);
 
         for (; self_id_count--; ++s)
                 if ((*s & 1 << 23) == 0)
-                        printk(KERN_DEBUG "selfID 0: %08x, phy %d [%c%c%c] "
-                               "%s gc=%d %s %s%s%s\n",
-                               *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
-                               speed[*s >> 14 & 3], *s >> 16 & 63,
-                               power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
-                               *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
+                        fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
+                            "%s gc=%d %s %s%s%s\n",
+                            *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
+                            speed[*s >> 14 & 3], *s >> 16 & 63,
+                            power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
+                            *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
                 else
-                        printk(KERN_DEBUG "selfID n: %08x, phy %d "
-                               "[%c%c%c%c%c%c%c%c]\n",
-                               *s, *s >> 24 & 63,
-                               _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
-                               _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
+                        fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
+                            *s, *s >> 24 & 63,
+                            _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
+                            _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 }
 
 static const char *evts[] = {
@@ -373,15 +370,14 @@ static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
                         evt = 0x1f;
 
         if (evt == OHCI1394_evt_bus_reset) {
-                printk(KERN_DEBUG "A%c evt_bus_reset, generation %d\n",
-                       dir, (header[2] >> 16) & 0xff);
+                fw_notify("A%c evt_bus_reset, generation %d\n",
+                    dir, (header[2] >> 16) & 0xff);
                 return;
         }
 
         if (header[0] == ~header[1]) {
-                printk(KERN_DEBUG "A%c %s, %s, %08x\n",
-                       dir, evts[evt], phys[header[0] >> 30 & 0x3],
-                       header[0]);
+                fw_notify("A%c %s, %s, %08x\n",
+                    dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
                 return;
         }
 
@@ -400,24 +396,23 @@ static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
 
         switch (tcode) {
         case 0xe: case 0xa:
-                printk(KERN_DEBUG "A%c %s, %s\n",
-                       dir, evts[evt], tcodes[tcode]);
+                fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
                 break;
         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
-                printk(KERN_DEBUG "A%c spd %x tl %02x, "
-                       "%04x -> %04x, %s, "
-                       "%s, %04x%08x%s\n",
-                       dir, speed, header[0] >> 10 & 0x3f,
-                       header[1] >> 16, header[0] >> 16, evts[evt],
-                       tcodes[tcode], header[1] & 0xffff, header[2], specific);
+                fw_notify("A%c spd %x tl %02x, "
+                    "%04x -> %04x, %s, "
+                    "%s, %04x%08x%s\n",
+                    dir, speed, header[0] >> 10 & 0x3f,
+                    header[1] >> 16, header[0] >> 16, evts[evt],
+                    tcodes[tcode], header[1] & 0xffff, header[2], specific);
                 break;
         default:
-                printk(KERN_DEBUG "A%c spd %x tl %02x, "
-                       "%04x -> %04x, %s, "
-                       "%s%s\n",
-                       dir, speed, header[0] >> 10 & 0x3f,
-                       header[1] >> 16, header[0] >> 16, evts[evt],
-                       tcodes[tcode], specific);
+                fw_notify("A%c spd %x tl %02x, "
+                    "%04x -> %04x, %s, "
+                    "%s%s\n",
+                    dir, speed, header[0] >> 10 & 0x3f,
+                    header[1] >> 16, header[0] >> 16, evts[evt],
+                    tcodes[tcode], specific);
         }
 }
 
@@ -548,6 +543,11 @@ static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
                 p.header_length = 12;
                 p.payload_length = 0;
                 break;
+
+        default:
+                /* FIXME: Stop context, discard everything, and restart? */
+                p.header_length = 0;
+                p.payload_length = 0;
         }
 
         p.payload = (void *) buffer + p.header_length;
@@ -1468,6 +1468,9 @@ static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
         reg_write(ohci, OHCI1394_HCControlClear,
                   OHCI1394_HCControl_noByteSwapData);
 
+        reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
+        reg_write(ohci, OHCI1394_LinkControlClear,
+                  OHCI1394_LinkControl_rcvPhyPkt);
         reg_write(ohci, OHCI1394_LinkControlSet,
                   OHCI1394_LinkControl_rcvSelfID |
                   OHCI1394_LinkControl_cycleTimerEnable |
@@ -1481,7 +1484,6 @@ static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
         ar_context_run(&ohci->ar_request_ctx);
         ar_context_run(&ohci->ar_response_ctx);
 
-        reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
         reg_write(ohci, OHCI1394_IntEventClear, ~0);
         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
diff --git a/drivers/firewire/fw-transaction.c b/drivers/firewire/fw-transaction.c
index ccf0e4cf108f..03ae8a77c479 100644
--- a/drivers/firewire/fw-transaction.c
+++ b/drivers/firewire/fw-transaction.c
@@ -20,6 +20,7 @@
 
 #include <linux/completion.h>
 #include <linux/kernel.h>
+#include <linux/kref.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
@@ -297,37 +298,55 @@ EXPORT_SYMBOL(fw_send_request);
 struct fw_phy_packet {
         struct fw_packet packet;
         struct completion done;
+        struct kref kref;
 };
 
-static void
-transmit_phy_packet_callback(struct fw_packet *packet,
-                             struct fw_card *card, int status)
+static void phy_packet_release(struct kref *kref)
+{
+        struct fw_phy_packet *p =
+                        container_of(kref, struct fw_phy_packet, kref);
+        kfree(p);
+}
+
+static void transmit_phy_packet_callback(struct fw_packet *packet,
+                                         struct fw_card *card, int status)
 {
         struct fw_phy_packet *p =
                         container_of(packet, struct fw_phy_packet, packet);
 
         complete(&p->done);
+        kref_put(&p->kref, phy_packet_release);
 }
 
 void fw_send_phy_config(struct fw_card *card,
                         int node_id, int generation, int gap_count)
 {
-        struct fw_phy_packet p;
+        struct fw_phy_packet *p;
+        long timeout = DIV_ROUND_UP(HZ, 10);
         u32 data = PHY_IDENTIFIER(PHY_PACKET_CONFIG) |
                    PHY_CONFIG_ROOT_ID(node_id) |
                    PHY_CONFIG_GAP_COUNT(gap_count);
 
-        p.packet.header[0] = data;
-        p.packet.header[1] = ~data;
-        p.packet.header_length = 8;
-        p.packet.payload_length = 0;
-        p.packet.speed = SCODE_100;
-        p.packet.generation = generation;
-        p.packet.callback = transmit_phy_packet_callback;
-        init_completion(&p.done);
-
-        card->driver->send_request(card, &p.packet);
-        wait_for_completion(&p.done);
+        p = kmalloc(sizeof(*p), GFP_KERNEL);
+        if (p == NULL)
+                return;
+
+        p->packet.header[0] = data;
+        p->packet.header[1] = ~data;
+        p->packet.header_length = 8;
+        p->packet.payload_length = 0;
+        p->packet.speed = SCODE_100;
+        p->packet.generation = generation;
+        p->packet.callback = transmit_phy_packet_callback;
+        init_completion(&p->done);
+        kref_set(&p->kref, 2);
+
+        card->driver->send_request(card, &p->packet);
+        timeout = wait_for_completion_timeout(&p->done, timeout);
+        kref_put(&p->kref, phy_packet_release);
+
+        /* will leak p if the callback is never executed */
+        WARN_ON(timeout == 0);
 }
 
 void fw_flush_transactions(struct fw_card *card)
@@ -572,7 +591,8 @@ allocate_request(struct fw_packet *p)
                 break;
 
         default:
-                BUG();
+                fw_error("ERROR - corrupt request received - %08x %08x %08x\n",
+                         p->header[0], p->header[1], p->header[2]);
                 return NULL;
         }
 
diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig
index 1607536ff5fb..8e07de23d220 100644
--- a/drivers/ide/Kconfig
+++ b/drivers/ide/Kconfig
@@ -823,13 +823,6 @@ config BLK_DEV_IDE_RAPIDE
           Say Y here if you want to support the Yellowstone RapIDE controller
           manufactured for use with Acorn computers.
 
-config BLK_DEV_IDE_BAST
-        tristate "Simtec BAST / Thorcom VR1000 IDE support"
-        depends on ARM && (ARCH_BAST || MACH_VR1000)
-        help
-          Say Y here if you want to support the onboard IDE channels on the
-          Simtec BAST or the Thorcom VR1000
-
 config IDE_H8300
         tristate "H8300 IDE support"
         depends on H8300
diff --git a/drivers/ide/arm/Makefile b/drivers/ide/arm/Makefile
index 936e7b0237f5..5bc26053afa6 100644
--- a/drivers/ide/arm/Makefile
+++ b/drivers/ide/arm/Makefile
@@ -1,7 +1,6 @@
 
 obj-$(CONFIG_BLK_DEV_IDE_ICSIDE)        += icside.o
 obj-$(CONFIG_BLK_DEV_IDE_RAPIDE)        += rapide.o
-obj-$(CONFIG_BLK_DEV_IDE_BAST)          += bast-ide.o
 obj-$(CONFIG_BLK_DEV_PALMCHIP_BK3710)   += palm_bk3710.o
 
 ifeq ($(CONFIG_IDE_ARM), m)
diff --git a/drivers/ide/arm/bast-ide.c b/drivers/ide/arm/bast-ide.c
deleted file mode 100644
index 8e8c28104b45..000000000000
--- a/drivers/ide/arm/bast-ide.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright (c) 2003-2004 Simtec Electronics
- *  Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/ide.h>
-#include <linux/init.h>
-
-#include <asm/mach-types.h>
-
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/arch/map.h>
-#include <asm/arch/bast-map.h>
-#include <asm/arch/bast-irq.h>
-
-#define DRV_NAME "bast-ide"
-
-static int __init bastide_register(unsigned int base, unsigned int aux, int irq)
-{
-        ide_hwif_t *hwif;
-        hw_regs_t hw;
-        int i;
-        u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
-
-        memset(&hw, 0, sizeof(hw));
-
-        base += BAST_IDE_CS;
-        aux  += BAST_IDE_CS;
-
-        for (i = 0; i <= 7; i++) {
-                hw.io_ports_array[i] = (unsigned long)base;
-                base += 0x20;
-        }
-
-        hw.io_ports.ctl_addr = aux + (6 * 0x20);
-        hw.irq = irq;
-        hw.chipset = ide_generic;
-
-        hwif = ide_find_port();
-        if (hwif == NULL)
-                goto out;
-
-        i = hwif->index;
-
-        ide_init_port_data(hwif, i);
-        ide_init_port_hw(hwif, &hw);
-        hwif->port_ops = NULL;
-
-        idx[0] = i;
-
-        ide_device_add(idx, NULL);
-out:
-        return 0;
-}
-
-static int __init bastide_init(void)
-{
-        unsigned long base = BAST_VA_IDEPRI + BAST_IDE_CS;
-
-        /* we can treat the VR1000 and the BAST the same */
-
-        if (!(machine_is_bast() || machine_is_vr1000()))
-                return 0;
-
-        printk("BAST: IDE driver, (c) 2003-2004 Simtec Electronics\n");
-
-        if (!request_mem_region(base, 0x400000, DRV_NAME)) {
-                printk(KERN_ERR "%s: resources busy\n", DRV_NAME);
-                return -EBUSY;
-        }
-
-        bastide_register(BAST_VA_IDEPRI, BAST_VA_IDEPRIAUX, IRQ_IDE0);
-        bastide_register(BAST_VA_IDESEC, BAST_VA_IDESECAUX, IRQ_IDE1);
-
-        return 0;
-}
-
-module_init(bastide_init);
-
-MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("Simtec BAST / Thorcom VR1000 IDE driver");
diff --git a/drivers/ide/arm/palm_bk3710.c b/drivers/ide/arm/palm_bk3710.c
index d024ac8fad14..cc24803fadff 100644
--- a/drivers/ide/arm/palm_bk3710.c
+++ b/drivers/ide/arm/palm_bk3710.c
@@ -353,8 +353,8 @@ static int __devinit palm_bk3710_probe(struct platform_device *pdev)
         struct clk *clkp;
         struct resource *mem, *irq;
         ide_hwif_t *hwif;
-        void __iomem *base;
-        int pribase, i;
+        unsigned long base;
+        int i;
         hw_regs_t hw;
         u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
 
@@ -374,22 +374,27 @@ static int __devinit palm_bk3710_probe(struct platform_device *pdev)
                 printk(KERN_ERR "failed to get memory region resource\n");
                 return -ENODEV;
         }
+
         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
         if (irq == NULL) {
                 printk(KERN_ERR "failed to get IRQ resource\n");
                 return -ENODEV;
         }
 
-        base = (void *)mem->start;
+        if (request_mem_region(mem->start, mem->end - mem->start + 1,
+                               "palm_bk3710") == NULL) {
+                printk(KERN_ERR "failed to request memory region\n");
+                return -EBUSY;
+        }
+
+        base = IO_ADDRESS(mem->start);
 
         /* Configure the Palm Chip controller */
-        palm_bk3710_chipinit(base);
+        palm_bk3710_chipinit((void __iomem *)base);
 
-        pribase = mem->start + IDE_PALM_ATA_PRI_REG_OFFSET;
         for (i = 0; i < IDE_NR_PORTS - 2; i++)
-                hw.io_ports_array[i] = pribase + i;
-        hw.io_ports.ctl_addr = mem->start +
-                        IDE_PALM_ATA_PRI_CTL_OFFSET;
+                hw.io_ports_array[i] = base + IDE_PALM_ATA_PRI_REG_OFFSET + i;
+        hw.io_ports.ctl_addr = base + IDE_PALM_ATA_PRI_CTL_OFFSET;
         hw.irq = irq->start;
         hw.chipset = ide_palm3710;
 
@@ -434,4 +439,3 @@ static int __init palm_bk3710_init(void)
 
 module_init(palm_bk3710_init);
 MODULE_LICENSE("GPL");
-
diff --git a/drivers/ide/ide-generic.c b/drivers/ide/ide-generic.c
index 9134488ac043..2d92214096ab 100644
--- a/drivers/ide/ide-generic.c
+++ b/drivers/ide/ide-generic.c
@@ -22,6 +22,10 @@
 
 #define DRV_NAME        "ide_generic"
 
+static int probe_mask = 0x03;
+module_param(probe_mask, int, 0);
+MODULE_PARM_DESC(probe_mask, "probe mask for legacy ISA IDE ports");
+
 static ssize_t store_add(struct class *cls, const char *buf, size_t n)
 {
         ide_hwif_t *hwif;
@@ -89,6 +93,9 @@ static int __init ide_generic_init(void)
         u8 idx[MAX_HWIFS];
         int i;
 
+        printk(KERN_INFO DRV_NAME ": please use \"probe_mask=0x3f\" module "
+                         "parameter for probing all legacy ISA IDE ports\n");
+
         for (i = 0; i < MAX_HWIFS; i++) {
                 ide_hwif_t *hwif;
                 unsigned long io_addr = ide_default_io_base(i);
@@ -96,7 +103,7 @@ static int __init ide_generic_init(void)
 
                 idx[i] = 0xff;
 
-                if (io_addr) {
+                if ((probe_mask & (1 << i)) && io_addr) {
                         if (!request_region(io_addr, 8, DRV_NAME)) {
                                 printk(KERN_ERR "%s: I/O resource 0x%lX-0x%lX "
                                                 "not free.\n",
diff --git a/drivers/ide/ide-taskfile.c b/drivers/ide/ide-taskfile.c
index 0c908ca3ff79..ab545ffa1549 100644
--- a/drivers/ide/ide-taskfile.c
+++ b/drivers/ide/ide-taskfile.c
@@ -225,10 +225,10 @@ static u8 wait_drive_not_busy(ide_drive_t *drive)
         u8 stat;
 
         /*
-         * Last sector was transfered, wait until drive is ready.
-         * This can take up to 10 usec, but we will wait max 1 ms.
+         * Last sector was transfered, wait until device is ready.  This can
+         * take up to 6 ms on some ATAPI devices, so we will wait max 10 ms.
          */
-        for (retries = 0; retries < 100; retries++) {
+        for (retries = 0; retries < 1000; retries++) {
                 stat = ide_read_status(drive);
 
                 if (stat & BUSY_STAT)
diff --git a/drivers/ide/legacy/ide-cs.c b/drivers/ide/legacy/ide-cs.c
index aa2ea3deac85..3381424d70a1 100644
--- a/drivers/ide/legacy/ide-cs.c
+++ b/drivers/ide/legacy/ide-cs.c
@@ -135,13 +135,17 @@ static void ide_detach(struct pcmcia_device *link)
 {
     ide_info_t *info = link->priv;
     ide_hwif_t *hwif = info->hwif;
+    unsigned long data_addr, ctl_addr;
 
     DEBUG(0, "ide_detach(0x%p)\n", link);
 
+    data_addr = hwif->io_ports.data_addr;
+    ctl_addr  = hwif->io_ports.ctl_addr;
+
     ide_release(link);
 
-    release_region(hwif->io_ports.ctl_addr, 1);
-    release_region(hwif->io_ports.data_addr, 8);
+    release_region(ctl_addr, 1);
+    release_region(data_addr, 8);
 
     kfree(info);
 } /* ide_detach */
@@ -194,6 +198,16 @@ static ide_hwif_t *idecs_register(unsigned long io, unsigned long ctl,
     if (hwif->present)
         return hwif;
 
+    /* retry registration in case device is still spinning up */
+    for (i = 0; i < 10; i++) {
+        msleep(100);
+        ide_port_scan(hwif);
+        if (hwif->present)
+            return hwif;
+    }
+
+    return hwif;
+
 out_release:
     release_region(ctl, 1);
     release_region(io, 8);
@@ -222,7 +236,7 @@ static int ide_config(struct pcmcia_device *link)
         cistpl_cftable_entry_t dflt;
     } *stk = NULL;
     cistpl_cftable_entry_t *cfg;
-    int i, pass, last_ret = 0, last_fn = 0, is_kme = 0;
+    int pass, last_ret = 0, last_fn = 0, is_kme = 0;
     unsigned long io_base, ctl_base;
     ide_hwif_t *hwif;
 
@@ -319,30 +333,15 @@ static int ide_config(struct pcmcia_device *link)
     if (is_kme)
         outb(0x81, ctl_base+1);
 
-    /* retry registration in case device is still spinning up */
-    for (i = 0; i < 10; i++) {
-        hwif = idecs_register(io_base, ctl_base, link->irq.AssignedIRQ, link);
-        if (hwif)
-            break;
-        if (link->io.NumPorts1 == 0x20) {
+     hwif = idecs_register(io_base, ctl_base, link->irq.AssignedIRQ, link);
+     if (hwif == NULL && link->io.NumPorts1 == 0x20) {
             outb(0x02, ctl_base + 0x10);
             hwif = idecs_register(io_base + 0x10, ctl_base + 0x10,
                                   link->irq.AssignedIRQ, link);
-            if (hwif) {
-                io_base += 0x10;
-                ctl_base += 0x10;
-                break;
-            }
-        }
-        msleep(100);
     }
 
-    if (hwif == NULL) {
-        printk(KERN_NOTICE "ide-cs: ide_register() at 0x%3lx & 0x%3lx"
-               ", irq %u failed\n", io_base, ctl_base,
-               link->irq.AssignedIRQ);
+    if (hwif == NULL)
         goto failed;
-    }
 
     info->ndev = 1;
     sprintf(info->node.dev_name, "hd%c", 'a' + hwif->index * 2);
@@ -411,6 +410,7 @@ static struct pcmcia_device_id ide_ids[] = {
         PCMCIA_DEVICE_MANF_CARD(0x001c, 0x0001),        /* Mitsubishi CFA */
         PCMCIA_DEVICE_MANF_CARD(0x0032, 0x0704),
         PCMCIA_DEVICE_MANF_CARD(0x0045, 0x0401),        /* SanDisk CFA */
+        PCMCIA_DEVICE_MANF_CARD(0x004f, 0x0000),        /* Kingston */
         PCMCIA_DEVICE_MANF_CARD(0x0098, 0x0000),        /* Toshiba */
         PCMCIA_DEVICE_MANF_CARD(0x00a4, 0x002d),
         PCMCIA_DEVICE_MANF_CARD(0x00ce, 0x0000),        /* Samsung */
@@ -440,6 +440,7 @@ static struct pcmcia_device_id ide_ids[] = {
         PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDE", 0x547e66dc, 0x5c5ab149),
         PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDEII", 0x547e66dc, 0xb3662674),
         PCMCIA_DEVICE_PROD_ID12("LOOKMEET", "CBIDE2      ", 0xe37be2b5, 0x8671043b),
+        PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF300", 0x7ed2ad87, 0x7e9e78ee),
         PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF500", 0x7ed2ad87, 0x7a13045c),
         PCMCIA_DEVICE_PROD_ID2("NinjaATA-", 0xebe0bd79),
         PCMCIA_DEVICE_PROD_ID12("PCMCIA", "CD-ROM", 0x281f1c5d, 0x66536591),
@@ -450,6 +451,7 @@ static struct pcmcia_device_id ide_ids[] = {
         PCMCIA_DEVICE_PROD_ID12("SMI VENDOR", "SMI PRODUCT", 0x30896c92, 0x703cc5f6),
         PCMCIA_DEVICE_PROD_ID12("TOSHIBA", "MK2001MPL", 0xb4585a1a, 0x3489e003),
         PCMCIA_DEVICE_PROD_ID1("TRANSCEND    512M   ", 0xd0909443),
+        PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF45", 0x709b1bf1, 0xf68b6f32),
         PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF80", 0x709b1bf1, 0x2a54d4b1),
         PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS2GCF120", 0x709b1bf1, 0x969aa4f2),
         PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS4GCF120", 0x709b1bf1, 0xf54a91c8),
diff --git a/drivers/ide/pci/opti621.c b/drivers/ide/pci/opti621.c
index 6e99080497bf..725c80508d90 100644
--- a/drivers/ide/pci/opti621.c
+++ b/drivers/ide/pci/opti621.c
@@ -81,8 +81,6 @@
  * 0.5 doesn't work.
  */
 
-#define OPTI621_DEBUG           /* define for debug messages */
-
 #include <linux/types.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
@@ -92,28 +90,6 @@
 
 #include <asm/io.h>
 
-//#define OPTI621_MAX_PIO 3
-/* In fact, I do not have any PIO 4 drive
- * (address: 25 ns, data: 70 ns, recovery: 35 ns),
- * but OPTi 82C621 is programmable and it can do (minimal values):
- * on 40MHz PCI bus (pulse 25 ns):
- *  address: 25 ns, data: 25 ns, recovery: 50 ns;
- * on 20MHz PCI bus (pulse 50 ns):
- *  address: 50 ns, data: 50 ns, recovery: 100 ns.
- */
-
-/* #define READ_PREFETCH 0 */
-/* Uncomment for disable read prefetch.
- * There is some readprefetch capatibility in hdparm,
- * but when I type hdparm -P 1 /dev/hda, I got errors
- * and till reset drive is inaccessible.
- * This (hw) read prefetch is safe on my drive.
- */
-
-#ifndef READ_PREFETCH
-#define READ_PREFETCH 0x40 /* read prefetch is enabled */
-#endif /* else read prefetch is disabled */
-
 #define READ_REG 0      /* index of Read cycle timing register */
 #define WRITE_REG 1     /* index of Write cycle timing register */
 #define CNTRL_REG 3     /* index of Control register */
@@ -122,51 +98,8 @@
 
 static int reg_base;
 
-#define PIO_NOT_EXIST 254
-#define PIO_DONT_KNOW 255
-
 static DEFINE_SPINLOCK(opti621_lock);
 
-/* there are stored pio numbers from other calls of opti621_set_pio_mode */
-static void compute_pios(ide_drive_t *drive, const u8 pio)
-/* Store values into drive->drive_data
- *      second_contr - 0 for primary controller, 1 for secondary
- *      slave_drive - 0 -> pio is for master, 1 -> pio is for slave
- *      pio - PIO mode for selected drive (for other we don't know)
- */
-{
-        int d;
-        ide_hwif_t *hwif = HWIF(drive);
-
-        drive->drive_data = pio;
-
-        for (d = 0; d < 2; ++d) {
-                drive = &hwif->drives[d];
-                if (drive->present) {
-                        if (drive->drive_data == PIO_DONT_KNOW)
-                                drive->drive_data = ide_get_best_pio_mode(drive, 255, 3);
-#ifdef OPTI621_DEBUG
-                        printk("%s: Selected PIO mode %d\n",
-                                drive->name, drive->drive_data);
-#endif
-                } else {
-                        drive->drive_data = PIO_NOT_EXIST;
-                }
-        }
-}
-
-static int cmpt_clk(int time, int bus_speed)
-/* Returns (rounded up) time in clocks for time in ns,
- * with bus_speed in MHz.
- * Example: bus_speed = 40 MHz, time = 80 ns
- * 1000/40 = 25 ns (clk value),
- * 80/25 = 3.2, rounded up to 4 (I hope ;-)).
- * Use idebus=xx to select right frequency.
- */
-{
-        return ((time*bus_speed+999)/1000);
-}
-
 /* Write value to register reg, base of register
  * is at reg_base (0x1f0 primary, 0x170 secondary,
  * if not changed by PCI configuration).
@@ -199,83 +132,29 @@ static u8 read_reg(int reg)
         return ret;
 }
 
-typedef struct pio_clocks_s {
-        int     address_time;   /* Address setup (clocks) */
-        int     data_time;      /* Active/data pulse (clocks) */
-        int     recovery_time;  /* Recovery time (clocks) */
-} pio_clocks_t;
-
-static void compute_clocks(int pio, pio_clocks_t *clks)
-{
-        if (pio != PIO_NOT_EXIST) {
-                int adr_setup, data_pls;
-                int bus_speed = ide_pci_clk ? ide_pci_clk : system_bus_clock();
-
-                adr_setup = ide_pio_timings[pio].setup_time;
-                data_pls = ide_pio_timings[pio].active_time;
-                clks->address_time = cmpt_clk(adr_setup, bus_speed);
-                clks->data_time = cmpt_clk(data_pls, bus_speed);
-                clks->recovery_time = cmpt_clk(ide_pio_timings[pio].cycle_time
-                        - adr_setup-data_pls, bus_speed);
-                if (clks->address_time < 1)
-                        clks->address_time = 1;
-                if (clks->address_time > 4)
-                        clks->address_time = 4;
-                if (clks->data_time < 1)
-                        clks->data_time = 1;
-                if (clks->data_time > 16)
-                        clks->data_time = 16;
-                if (clks->recovery_time < 2)
-                        clks->recovery_time = 2;
-                if (clks->recovery_time > 17)
-                        clks->recovery_time = 17;
-        } else {
-                clks->address_time = 1;
-                clks->data_time = 1;
-                clks->recovery_time = 2;
-                /* minimal values */
-        }
-}
-
 static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
 {
-        /* primary and secondary drives share some registers,
-         * so we have to program both drives
-         */
+        ide_hwif_t *hwif = drive->hwif;
+        ide_drive_t *pair = ide_get_paired_drive(drive);
         unsigned long flags;
-        u8 pio1 = 0, pio2 = 0;
-        pio_clocks_t first, second;
-        int ax, drdy;
-        u8 cycle1, cycle2, misc;
-        ide_hwif_t *hwif = HWIF(drive);
-
-        /* sets drive->drive_data for both drives */
-        compute_pios(drive, pio);
-        pio1 = hwif->drives[0].drive_data;
-        pio2 = hwif->drives[1].drive_data;
-
-        compute_clocks(pio1, &first);
-        compute_clocks(pio2, &second);
-
-        /* ax = max(a1,a2) */
-        ax = (first.address_time < second.address_time) ? second.address_time : first.address_time;
-
-        drdy = 2; /* DRDY is default 2 (by OPTi Databook) */
-
-        cycle1 = ((first.data_time-1)<<4)  | (first.recovery_time-2);
-        cycle2 = ((second.data_time-1)<<4) | (second.recovery_time-2);
-        misc = READ_PREFETCH | ((ax-1)<<4) | ((drdy-2)<<1);
-
-#ifdef OPTI621_DEBUG
-        printk("%s: master: address: %d, data: %d, "
-                "recovery: %d, drdy: %d [clk]\n",
-                hwif->name, ax, first.data_time,
-                first.recovery_time, drdy);
-        printk("%s: slave:  address: %d, data: %d, "
-                "recovery: %d, drdy: %d [clk]\n",
-                hwif->name, ax, second.data_time,
-                second.recovery_time, drdy);
-#endif
+        u8 tim, misc, addr_pio = pio, clk;
+
+        /* DRDY is default 2 (by OPTi Databook) */
+        static const u8 addr_timings[2][5] = {
+                { 0x20, 0x10, 0x00, 0x00, 0x00 },       /* 33 MHz */
+                { 0x10, 0x10, 0x00, 0x00, 0x00 },       /* 25 MHz */
+        };
+        static const u8 data_rec_timings[2][5] = {
+                { 0x5b, 0x45, 0x32, 0x21, 0x20 },       /* 33 MHz */
+                { 0x48, 0x34, 0x21, 0x10, 0x10 }        /* 25 MHz */
+        };
+
+        drive->drive_data = XFER_PIO_0 + pio;
+
+        if (pair->present) {
+                if (pair->drive_data && pair->drive_data < drive->drive_data)
+                        addr_pio = pair->drive_data - XFER_PIO_0;
+        }
 
         spin_lock_irqsave(&opti621_lock, flags);
 
@@ -289,24 +168,21 @@ static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
         (void)inb(reg_base + CNTRL_REG);
         /* if reads 0xc0, no interface exist? */
         read_reg(CNTRL_REG);
-        /* read version, probably 0 */
-        read_reg(STRAP_REG);
 
-        /* program primary drive */
-        /* select Index-0 for Register-A */
-        write_reg(0, MISC_REG);
-        /* set read cycle timings */
-        write_reg(cycle1, READ_REG);
-        /* set write cycle timings */
-        write_reg(cycle1, WRITE_REG);
+        /* check CLK speed */
+        clk = read_reg(STRAP_REG) & 1;
+
+        printk(KERN_INFO "%s: CLK = %d MHz\n", hwif->name, clk ? 25 : 33);
 
-        /* program secondary drive */
-        /* select Index-1 for Register-B */
-        write_reg(1, MISC_REG);
+        tim  = data_rec_timings[clk][pio];
+        misc = addr_timings[clk][addr_pio];
+
+        /* select Index-0/1 for Register-A/B */
+        write_reg(drive->select.b.unit, MISC_REG);
         /* set read cycle timings */
-        write_reg(cycle2, READ_REG);
+        write_reg(tim, READ_REG);
         /* set write cycle timings */
-        write_reg(cycle2, WRITE_REG);
+        write_reg(tim, WRITE_REG);
 
         /* use Register-A for drive 0 */
         /* use Register-B for drive 1 */
@@ -319,45 +195,26 @@ static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
         spin_unlock_irqrestore(&opti621_lock, flags);
 }
 
-static void __devinit opti621_port_init_devs(ide_hwif_t *hwif)
-{
-        hwif->drives[0].drive_data = PIO_DONT_KNOW;
-        hwif->drives[1].drive_data = PIO_DONT_KNOW;
-}
-
 static const struct ide_port_ops opti621_port_ops = {
-        .port_init_devs         = opti621_port_init_devs,
         .set_pio_mode           = opti621_set_pio_mode,
 };
 
-static const struct ide_port_info opti621_chipsets[] __devinitdata = {
-        {       /* 0 */
-                .name           = "OPTI621",
-                .enablebits     = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
-                .port_ops       = &opti621_port_ops,
-                .host_flags     = IDE_HFLAG_TRUST_BIOS_FOR_DMA,
-                .pio_mask       = ATA_PIO3,
-                .swdma_mask     = ATA_SWDMA2,
-                .mwdma_mask     = ATA_MWDMA2,
-        }, {    /* 1 */
-                .name           = "OPTI621X",
-                .enablebits     = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
-                .port_ops       = &opti621_port_ops,
-                .host_flags     = IDE_HFLAG_TRUST_BIOS_FOR_DMA,
-                .pio_mask       = ATA_PIO3,
-                .swdma_mask     = ATA_SWDMA2,
-                .mwdma_mask     = ATA_MWDMA2,
-        }
+static const struct ide_port_info opti621_chipset __devinitdata = {
+        .name           = "OPTI621/X",
+        .enablebits     = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
+        .port_ops       = &opti621_port_ops,
+        .host_flags     = IDE_HFLAG_NO_DMA,
+        .pio_mask       = ATA_PIO4,
 };
 
 static int __devinit opti621_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 {
-        return ide_setup_pci_device(dev, &opti621_chipsets[id->driver_data]);
+        return ide_setup_pci_device(dev, &opti621_chipset);
 }
 
 static const struct pci_device_id opti621_pci_tbl[] = {
         { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 },
-        { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 1 },
+        { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 0 },
         { 0, },
 };
 MODULE_DEVICE_TABLE(pci, opti621_pci_tbl);
diff --git a/drivers/ide/ppc/pmac.c b/drivers/ide/ppc/pmac.c
index 48aa019127bc..ba2d58727964 100644
--- a/drivers/ide/ppc/pmac.c
+++ b/drivers/ide/ppc/pmac.c
@@ -59,7 +59,6 @@ typedef struct pmac_ide_hwif {
         int                             irq;
         int                             kind;
         int                             aapl_bus_id;
-        unsigned                        cable_80 : 1;
         unsigned                        mediabay : 1;
         unsigned                        broken_dma : 1;
         unsigned                        broken_dma_warn : 1;
@@ -918,10 +917,40 @@ pmac_ide_do_resume(ide_hwif_t *hwif)
         return 0;
 }
 
+static u8 pmac_ide_cable_detect(ide_hwif_t *hwif)
+{
+        pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)ide_get_hwifdata(hwif);
+        struct device_node *np = pmif->node;
+        const char *cable = of_get_property(np, "cable-type", NULL);
+
+        /* Get cable type from device-tree. */
+        if (cable && !strncmp(cable, "80-", 3))
+                return ATA_CBL_PATA80;
+
+        /*
+         * G5's seem to have incorrect cable type in device-tree.
+         * Let's assume they have a 80 conductor cable, this seem
+         * to be always the case unless the user mucked around.
+         */
+        if (of_device_is_compatible(np, "K2-UATA") ||
+            of_device_is_compatible(np, "shasta-ata"))
+                return ATA_CBL_PATA80;
+
+        return ATA_CBL_PATA40;
+}
+
 static const struct ide_port_ops pmac_ide_ata6_port_ops = {
         .set_pio_mode           = pmac_ide_set_pio_mode,
         .set_dma_mode           = pmac_ide_set_dma_mode,
         .selectproc             = pmac_ide_kauai_selectproc,
+        .cable_detect           = pmac_ide_cable_detect,
+};
+
+static const struct ide_port_ops pmac_ide_ata4_port_ops = {
+        .set_pio_mode           = pmac_ide_set_pio_mode,
+        .set_dma_mode           = pmac_ide_set_dma_mode,
+        .selectproc             = pmac_ide_selectproc,
+        .cable_detect           = pmac_ide_cable_detect,
 };
 
 static const struct ide_port_ops pmac_ide_port_ops = {
@@ -949,10 +978,7 @@ static const struct ide_port_info pmac_port_info = {
 
 /*
  * Setup, register & probe an IDE channel driven by this driver, this is
- * called by one of the 2 probe functions (macio or PCI). Note that a channel
- * that ends up beeing free of any device is not kept around by this driver
- * (it is kept in 2.4). This introduce an interface numbering change on some
- * rare machines unfortunately, but it's better this way.
+ * called by one of the 2 probe functions (macio or PCI).
  */
 static int __devinit
 pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw)
@@ -962,7 +988,6 @@ pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw)
         u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
         struct ide_port_info d = pmac_port_info;
 
-        pmif->cable_80 = 0;
         pmif->broken_dma = pmif->broken_dma_warn = 0;
         if (of_device_is_compatible(np, "shasta-ata")) {
                 pmif->kind = controller_sh_ata6;
@@ -979,6 +1004,7 @@ pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw)
         } else if (of_device_is_compatible(np, "keylargo-ata")) {
                 if (strcmp(np->name, "ata-4") == 0) {
                         pmif->kind = controller_kl_ata4;
+                        d.port_ops = &pmac_ide_ata4_port_ops;
                         d.udma_mask = ATA_UDMA4;
                 } else
                         pmif->kind = controller_kl_ata3;
@@ -992,22 +1018,6 @@ pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw)
         bidp = of_get_property(np, "AAPL,bus-id", NULL);
         pmif->aapl_bus_id =  bidp ? *bidp : 0;
 
-        /* Get cable type from device-tree */
-        if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
-            || pmif->kind == controller_k2_ata6
-            || pmif->kind == controller_sh_ata6) {
-                const char* cable = of_get_property(np, "cable-type", NULL);
-                if (cable && !strncmp(cable, "80-", 3))
-                        pmif->cable_80 = 1;
-        }
-        /* G5's seem to have incorrect cable type in device-tree. Let's assume
-         * they have a 80 conductor cable, this seem to be always the case unless
-         * the user mucked around
-         */
-        if (of_device_is_compatible(np, "K2-UATA") ||
-            of_device_is_compatible(np, "shasta-ata"))
-                pmif->cable_80 = 1;
-
         /* On Kauai-type controllers, we make sure the FCR is correct */
         if (pmif->kauai_fcr)
                 writel(KAUAI_FCR_UATA_MAGIC |
@@ -1053,7 +1063,6 @@ pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw)
 
         hwif->hwif_data = pmif;
         ide_init_port_hw(hwif, hw);
-        hwif->cbl = pmif->cable_80 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 
         printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
                hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
@@ -1070,11 +1079,6 @@ pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw)
                 }
         }
 
-#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
-        if (pmif->cable_80 == 0)
-                d.udma_mask &= ATA_UDMA2;
-#endif
-
         idx[0] = hwif->index;
 
         ide_device_add(idx, &d);
diff --git a/drivers/ieee1394/Kconfig b/drivers/ieee1394/Kconfig
index 545663ef820b..95f45f9b8e5e 100644
--- a/drivers/ieee1394/Kconfig
+++ b/drivers/ieee1394/Kconfig
@@ -4,7 +4,7 @@ menu "IEEE 1394 (FireWire) support"
 source "drivers/firewire/Kconfig"
 
 config IEEE1394
-        tristate "IEEE 1394 (FireWire) support"
+        tristate "Stable FireWire stack"
         depends on PCI || BROKEN
         help
           IEEE 1394 describes a high performance serial bus, which is also
@@ -19,30 +19,45 @@ config IEEE1394
           To compile this driver as a module, say M here: the
           module will be called ieee1394.
 
-comment "Subsystem Options"
-        depends on IEEE1394
-
-config IEEE1394_VERBOSEDEBUG
-        bool "Excessive debugging output"
-        depends on IEEE1394
+config IEEE1394_OHCI1394
+        tristate "OHCI-1394 controllers"
+        depends on PCI && IEEE1394
         help
-          If you say Y here, you will get very verbose debugging logs from
-          the subsystem which includes a dump of the header of every sent
-          and received packet.  This can amount to a high amount of data
-          collected in a very short time which is usually also saved to
-          disk by the system logging daemons.
+          Enable this driver if you have an IEEE 1394 controller based on the
+          OHCI-1394 specification. The current driver is only tested with OHCI
+          chipsets made by Texas Instruments and NEC. Most third-party vendors
+          use one of these chipsets.  It should work with any OHCI-1394
+          compliant card, however.
 
-          Say Y if you really want or need the debugging output, everyone
-          else says N.
+          To compile this driver as a module, say M here: the
+          module will be called ohci1394.
 
-comment "Controllers"
-        depends on IEEE1394
+          NOTE:
 
-comment "Texas Instruments PCILynx requires I2C"
+          You should only build either ohci1394 or the new firewire-ohci driver,
+          but not both.  If you nevertheless want to install both, you should
+          configure them only as modules and blacklist the driver(s) which you
+          don't want to have auto-loaded.  Add either
+
+              blacklist firewire-ohci
+          or
+              blacklist ohci1394
+              blacklist video1394
+              blacklist dv1394
+
+          to /etc/modprobe.conf or /etc/modprobe.d/* and update modprobe.conf
+          depending on your distribution.  The latter two modules should be
+          blacklisted together with ohci1394 because they depend on ohci1394.
+
+          If you have an old modprobe which doesn't implement the blacklist
+          directive, use "install modulename /bin/true" for the modules to be
+          blacklisted.
+
+comment "PCILynx controller requires I2C"
         depends on IEEE1394 && I2C=n
 
 config IEEE1394_PCILYNX
-        tristate "Texas Instruments PCILynx support"
+        tristate "PCILynx controller"
         depends on PCI && IEEE1394 && I2C
         select I2C_ALGOBIT
         help
@@ -57,35 +72,11 @@ config IEEE1394_PCILYNX
           PowerMacs G3 B&W contain the PCILynx controller.  Therefore
           almost everybody can say N here.
 
-config IEEE1394_OHCI1394
-        tristate "OHCI-1394 support"
-        depends on PCI && IEEE1394
-        help
-          Enable this driver if you have an IEEE 1394 controller based on the
-          OHCI-1394 specification. The current driver is only tested with OHCI
-          chipsets made by Texas Instruments and NEC. Most third-party vendors
-          use one of these chipsets.  It should work with any OHCI-1394
-          compliant card, however.
-
-          To compile this driver as a module, say M here: the
-          module will be called ohci1394.
-
-comment "Protocols"
-        depends on IEEE1394
-
-config IEEE1394_VIDEO1394
-        tristate "OHCI-1394 Video support"
-        depends on IEEE1394 && IEEE1394_OHCI1394
-        help
-          This option enables video device usage for OHCI-1394 cards.  Enable
-          this option only if you have an IEEE 1394 video device connected to
-          an OHCI-1394 card.
-
 comment "SBP-2 support (for storage devices) requires SCSI"
         depends on IEEE1394 && SCSI=n
 
 config IEEE1394_SBP2
-        tristate "SBP-2 support (Harddisks etc.)"
+        tristate "Storage devices (SBP-2 protocol)"
         depends on IEEE1394 && SCSI
         help
           This option enables you to use SBP-2 devices connected to an IEEE
@@ -127,24 +118,47 @@ config IEEE1394_ETH1394
 
           The module is called eth1394 although it does not emulate Ethernet.
 
+config IEEE1394_RAWIO
+        tristate "raw1394 userspace interface"
+        depends on IEEE1394
+        help
+          This option adds support for the raw1394 device file which enables
+          direct communication of user programs with IEEE 1394 devices
+          (isochronous and asynchronous).  Almost all application programs
+          which access FireWire require this option.
+
+          To compile this driver as a module, say M here: the module will be
+          called raw1394.
+
+config IEEE1394_VIDEO1394
+        tristate "video1394 userspace interface"
+        depends on IEEE1394 && IEEE1394_OHCI1394
+        help
+          This option adds support for the video1394 device files which enable
+          isochronous communication of user programs with IEEE 1394 devices,
+          especially video capture or export.  This interface is used by all
+          libdc1394 based programs and by several other programs, in addition to
+          the raw1394 interface.  It is generally not required for DV capture.
+
+          To compile this driver as a module, say M here: the module will be
+          called video1394.
+
 config IEEE1394_DV1394
-        tristate "OHCI-DV I/O support (deprecated)"
+        tristate "dv1394 userspace interface (deprecated)"
         depends on IEEE1394 && IEEE1394_OHCI1394
         help
           The dv1394 driver is unsupported and may be removed from Linux in a
           future release.  Its functionality is now provided by raw1394 together
           with libraries such as libiec61883.
 
-config IEEE1394_RAWIO
-        tristate "Raw IEEE1394 I/O support"
+config IEEE1394_VERBOSEDEBUG
+        bool "Excessive debugging output"
         depends on IEEE1394
         help
-          This option adds support for the raw1394 device file which enables
-          direct communication of user programs with the IEEE 1394 bus and thus
-          with the attached peripherals.  Almost all application programs which
-          access FireWire require this option.
+          If you say Y here, you will get very verbose debugging logs from the
+          ieee1394 drivers, including sent and received packet headers.  This
+          will quickly result in large amounts of data sent to the system log.
 
-          To compile this driver as a module, say M here: the module will be
-          called raw1394.
+          Say Y if you really need the debugging output.  Everyone else says N.
 
 endmenu
diff --git a/drivers/infiniband/core/uverbs_main.c b/drivers/infiniband/core/uverbs_main.c
index f806da184b51..caed42bf7ef5 100644
--- a/drivers/infiniband/core/uverbs_main.c
+++ b/drivers/infiniband/core/uverbs_main.c
@@ -423,7 +423,7 @@ static void ib_uverbs_async_handler(struct ib_uverbs_file *file,
         unsigned long flags;
 
         spin_lock_irqsave(&file->async_file->lock, flags);
-        if (!file->async_file->is_closed) {
+        if (file->async_file->is_closed) {
                 spin_unlock_irqrestore(&file->async_file->lock, flags);
                 return;
         }
diff --git a/drivers/infiniband/hw/nes/nes_verbs.c b/drivers/infiniband/hw/nes/nes_verbs.c
index 99b3c4ae86eb..d617da9bd351 100644
--- a/drivers/infiniband/hw/nes/nes_verbs.c
+++ b/drivers/infiniband/hw/nes/nes_verbs.c
@@ -2456,10 +2456,8 @@ static struct ib_mr *nes_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
                                                 if ((page_count!=0)&&(page_count<<12)-(region->offset&(4096-1))>=region->length)
                                                         goto enough_pages;
                                                 if ((page_count&0x01FF) == 0) {
-                                                        if (page_count>(1024*512)) {
+                                                        if (page_count >= 1024 * 512) {
                                                                 ib_umem_release(region);
-                                                                pci_free_consistent(nesdev->pcidev, 4096, vpbl.pbl_vbase,
-                                                                                vpbl.pbl_pbase);
                                                                 nes_free_resource(nesadapter,
                                                                                 nesadapter->allocated_mrs, stag_index);
                                                                 kfree(nesmr);
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 3ad8bd9f7543..432699d61c58 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -15,7 +15,6 @@ if INPUT_MISC
 config INPUT_PCSPKR
         tristate "PC Speaker support"
         depends on PCSPKR_PLATFORM
-        depends on SND_PCSP=n
         help
           Say Y here if you want the standard PC Speaker to be used for
           bells and whistles.
diff --git a/drivers/input/mouse/appletouch.c b/drivers/input/mouse/appletouch.c
index 8dd3942f3022..ce6fdec19e14 100644
--- a/drivers/input/mouse/appletouch.c
+++ b/drivers/input/mouse/appletouch.c
@@ -589,6 +589,21 @@ static void atp_close(struct input_dev *input)
         dev->open = 0;
 }
 
+static int atp_handle_geyser(struct atp *dev)
+{
+        struct usb_device *udev = dev->udev;
+
+        if (!atp_is_fountain(dev)) {
+                /* switch to raw sensor mode */
+                if (atp_geyser_init(udev))
+                        return -EIO;
+
+                printk(KERN_INFO "appletouch: Geyser mode initialized.\n");
+        }
+
+        return 0;
+}
+
 static int atp_probe(struct usb_interface *iface, const struct usb_device_id *id)
 {
         struct atp *dev;
@@ -633,14 +648,6 @@ static int atp_probe(struct usb_interface *iface, const struct usb_device_id *id
         else
                 dev->datalen = 81;
 
-        if (!atp_is_fountain(dev)) {
-                /* switch to raw sensor mode */
-                if (atp_geyser_init(udev))
-                        goto err_free_devs;
-
-                printk(KERN_INFO "appletouch: Geyser mode initialized.\n");
-        }
-
         dev->urb = usb_alloc_urb(0, GFP_KERNEL);
         if (!dev->urb)
                 goto err_free_devs;
@@ -654,6 +661,10 @@ static int atp_probe(struct usb_interface *iface, const struct usb_device_id *id
                          usb_rcvintpipe(udev, int_in_endpointAddr),
                          dev->data, dev->datalen, atp_complete, dev, 1);
 
+        error = atp_handle_geyser(dev);
+        if (error)
+                goto err_free_buffer;
+
         usb_make_path(udev, dev->phys, sizeof(dev->phys));
         strlcat(dev->phys, "/input0", sizeof(dev->phys));
 
@@ -744,6 +755,20 @@ static void atp_disconnect(struct usb_interface *iface)
         printk(KERN_INFO "input: appletouch disconnected\n");
 }
 
+static int atp_recover(struct atp *dev)
+{
+        int error;
+
+        error = atp_handle_geyser(dev);
+        if (error)
+                return error;
+
+        if (dev->open && usb_submit_urb(dev->urb, GFP_ATOMIC))
+                return -EIO;
+
+        return 0;
+}
+
 static int atp_suspend(struct usb_interface *iface, pm_message_t message)
 {
         struct atp *dev = usb_get_intfdata(iface);
@@ -764,12 +789,20 @@ static int atp_resume(struct usb_interface *iface)
         return 0;
 }
 
+static int atp_reset_resume(struct usb_interface *iface)
+{
+        struct atp *dev = usb_get_intfdata(iface);
+
+        return atp_recover(dev);
+}
+
 static struct usb_driver atp_driver = {
         .name           = "appletouch",
         .probe          = atp_probe,
         .disconnect     = atp_disconnect,
         .suspend        = atp_suspend,
         .resume         = atp_resume,
+        .reset_resume   = atp_reset_resume,
         .id_table       = atp_table,
 };
 
diff --git a/drivers/input/serio/i8042-x86ia64io.h b/drivers/input/serio/i8042-x86ia64io.h
index 9aafa96cb746..78eb7841174c 100644
--- a/drivers/input/serio/i8042-x86ia64io.h
+++ b/drivers/input/serio/i8042-x86ia64io.h
@@ -193,6 +193,13 @@ static struct dmi_system_id __initdata i8042_dmi_nomux_table[] = {
                 },
         },
         {
+                .ident = "Fujitsu-Siemens Amilo Pro 2030",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU SIEMENS"),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "AMILO PRO V2030"),
+                },
+        },
+        {
                 /*
                  * No data is coming from the touchscreen unless KBC
                  * is in legacy mode.
diff --git a/drivers/input/serio/i8042.c b/drivers/input/serio/i8042.c
index 592ff55b62d0..170f71ee5772 100644
--- a/drivers/input/serio/i8042.c
+++ b/drivers/input/serio/i8042.c
@@ -952,8 +952,12 @@ static int i8042_resume(struct platform_device *dev)
         i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS;
         i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT);
         if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
-                printk(KERN_ERR "i8042: Can't write CTR to resume\n");
-                return -EIO;
+                printk(KERN_WARNING "i8042: Can't write CTR to resume, retrying...\n");
+                msleep(50);
+                if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
+                        printk(KERN_ERR "i8042: CTR write retry failed\n");
+                        return -EIO;
+                }
         }
 
 
diff --git a/drivers/macintosh/mediabay.c b/drivers/macintosh/mediabay.c
index 82add26cc665..818aba368541 100644
--- a/drivers/macintosh/mediabay.c
+++ b/drivers/macintosh/mediabay.c
@@ -84,7 +84,7 @@ struct media_bay_info {
         int                             cd_irq;
         int                             cd_retry;
 #endif
-#if defined(CONFIG_BLK_DEV_IDE_PMAC) || defined(CONFIG_MAC_FLOPPY)
+#if defined(CONFIG_BLK_DEV_IDE_PMAC)
         int                             cd_index;
 #endif
 };
@@ -417,6 +417,7 @@ static void poll_media_bay(struct media_bay_info* bay)
         }
 }
 
+#ifdef CONFIG_BLK_DEV_IDE_PMAC
 int check_media_bay(struct device_node *which_bay, int what)
 {
         int     i;
@@ -432,7 +433,6 @@ int check_media_bay(struct device_node *which_bay, int what)
 }
 EXPORT_SYMBOL(check_media_bay);
 
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
 int check_media_bay_by_base(unsigned long base, int what)
 {
         int     i;
@@ -556,7 +556,8 @@ static void media_bay_step(int i)
                                 printk("mediabay %d, registering IDE...\n", i);
                                 pmu_suspend();
                                 ide_port_scan(bay->cd_port);
-                                bay->cd_index = bay->cd_port->index;
+                                if (bay->cd_port->present)
+                                        bay->cd_index = bay->cd_port->index;
                                 pmu_resume();
                         }
                         if (bay->cd_index == -1) {
diff --git a/drivers/macintosh/smu.c b/drivers/macintosh/smu.c
index 77ad192962c5..d86d57af282a 100644
--- a/drivers/macintosh/smu.c
+++ b/drivers/macintosh/smu.c
@@ -483,12 +483,15 @@ int __init smu_init (void)
 
         if (smu_cmdbuf_abs == 0) {
                 printk(KERN_ERR "SMU: Command buffer not allocated !\n");
+                of_node_put(np);
                 return -EINVAL;
         }
 
         smu = alloc_bootmem(sizeof(struct smu_device));
-        if (smu == NULL)
+        if (smu == NULL) {
+                of_node_put(np);
                 return -ENOMEM;
+        }
         memset(smu, 0, sizeof(*smu));
 
         spin_lock_init(&smu->lock);
diff --git a/drivers/macintosh/therm_adt746x.c b/drivers/macintosh/therm_adt746x.c
index 54f4942a2968..5366dc93fb38 100644
--- a/drivers/macintosh/therm_adt746x.c
+++ b/drivers/macintosh/therm_adt746x.c
@@ -562,18 +562,24 @@ thermostat_init(void)
                 therm_type = ADT7460;
         else if (of_device_is_compatible(np, "adt7467"))
                 therm_type = ADT7467;
-        else
+        else {
+                of_node_put(np);
                 return -ENODEV;
+        }
 
         prop = of_get_property(np, "hwsensor-params-version", NULL);
         printk(KERN_INFO "adt746x: version %d (%ssupported)\n", *prop,
                          (*prop == 1)?"":"un");
-        if (*prop != 1)
+        if (*prop != 1) {
+                of_node_put(np);
                 return -ENODEV;
+        }
 
         prop = of_get_property(np, "reg", NULL);
-        if (!prop)
+        if (!prop) {
+                of_node_put(np);
                 return -ENODEV;
+        }
 
         /* look for bus either by path or using "reg" */
         if (strstr(np->full_name, "/i2c-bus@") != NULL) {
@@ -610,6 +616,7 @@ thermostat_init(void)
         
         if (of_dev == NULL) {
                 printk(KERN_ERR "Can't register temperatures device !\n");
+                of_node_put(np);
                 return -ENODEV;
         }
         
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index 72cf61ed8f96..e1637bd82b8e 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -181,7 +181,7 @@ static int pci_call_probe(struct pci_driver *drv, struct pci_dev *dev,
            any need to change it. */
         struct mempolicy *oldpol;
         cpumask_t oldmask = current->cpus_allowed;
-        int node = pcibus_to_node(dev->bus);
+        int node = dev_to_node(&dev->dev);
 
         if (node >= 0) {
                 node_to_cpumask_ptr(nodecpumask, node);
diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
index 271d41cc05ab..6f3c7446c329 100644
--- a/drivers/pci/pci-sysfs.c
+++ b/drivers/pci/pci-sysfs.c
@@ -489,13 +489,13 @@ pci_mmap_legacy_mem(struct kobject *kobj, struct bin_attribute *attr,
  * @kobj: kobject for mapping
  * @attr: struct bin_attribute for the file being mapped
  * @vma: struct vm_area_struct passed into the mmap
+ * @write_combine: 1 for write_combine mapping
  *
  * Use the regular PCI mapping routines to map a PCI resource into userspace.
- * FIXME: write combining?  maybe automatic for prefetchable regions?
  */
 static int
 pci_mmap_resource(struct kobject *kobj, struct bin_attribute *attr,
-                  struct vm_area_struct *vma)
+                  struct vm_area_struct *vma, int write_combine)
 {
         struct pci_dev *pdev = to_pci_dev(container_of(kobj,
                                                        struct device, kobj));
@@ -518,7 +518,21 @@ pci_mmap_resource(struct kobject *kobj, struct bin_attribute *attr,
         vma->vm_pgoff += start >> PAGE_SHIFT;
         mmap_type = res->flags & IORESOURCE_MEM ? pci_mmap_mem : pci_mmap_io;
 
-        return pci_mmap_page_range(pdev, vma, mmap_type, 0);
+        return pci_mmap_page_range(pdev, vma, mmap_type, write_combine);
+}
+
+static int
+pci_mmap_resource_uc(struct kobject *kobj, struct bin_attribute *attr,
+                     struct vm_area_struct *vma)
+{
+        return pci_mmap_resource(kobj, attr, vma, 0);
+}
+
+static int
+pci_mmap_resource_wc(struct kobject *kobj, struct bin_attribute *attr,
+                     struct vm_area_struct *vma)
+{
+        return pci_mmap_resource(kobj, attr, vma, 1);
 }
 
 /**
@@ -541,9 +555,46 @@ pci_remove_resource_files(struct pci_dev *pdev)
                         sysfs_remove_bin_file(&pdev->dev.kobj, res_attr);
                         kfree(res_attr);
                 }
+
+                res_attr = pdev->res_attr_wc[i];
+                if (res_attr) {
+                        sysfs_remove_bin_file(&pdev->dev.kobj, res_attr);
+                        kfree(res_attr);
+                }
         }
 }
 
+static int pci_create_attr(struct pci_dev *pdev, int num, int write_combine)
+{
+        /* allocate attribute structure, piggyback attribute name */
+        int name_len = write_combine ? 13 : 10;
+        struct bin_attribute *res_attr;
+        int retval;
+
+        res_attr = kzalloc(sizeof(*res_attr) + name_len, GFP_ATOMIC);
+        if (res_attr) {
+                char *res_attr_name = (char *)(res_attr + 1);
+
+                if (write_combine) {
+                        pdev->res_attr_wc[num] = res_attr;
+                        sprintf(res_attr_name, "resource%d_wc", num);
+                        res_attr->mmap = pci_mmap_resource_wc;
+                } else {
+                        pdev->res_attr[num] = res_attr;
+                        sprintf(res_attr_name, "resource%d", num);
+                        res_attr->mmap = pci_mmap_resource_uc;
+                }
+                res_attr->attr.name = res_attr_name;
+                res_attr->attr.mode = S_IRUSR | S_IWUSR;
+                res_attr->size = pci_resource_len(pdev, num);
+                res_attr->private = &pdev->resource[num];
+                retval = sysfs_create_bin_file(&pdev->dev.kobj, res_attr);
+        } else
+                retval = -ENOMEM;
+
+        return retval;
+}
+
 /**
  * pci_create_resource_files - create resource files in sysfs for @dev
  * @dev: dev in question
@@ -557,31 +608,19 @@ static int pci_create_resource_files(struct pci_dev *pdev)
 
         /* Expose the PCI resources from this device as files */
         for (i = 0; i < PCI_ROM_RESOURCE; i++) {
-                struct bin_attribute *res_attr;
 
                 /* skip empty resources */
                 if (!pci_resource_len(pdev, i))
                         continue;
 
-                /* allocate attribute structure, piggyback attribute name */
-                res_attr = kzalloc(sizeof(*res_attr) + 10, GFP_ATOMIC);
-                if (res_attr) {
-                        char *res_attr_name = (char *)(res_attr + 1);
-
-                        pdev->res_attr[i] = res_attr;
-                        sprintf(res_attr_name, "resource%d", i);
-                        res_attr->attr.name = res_attr_name;
-                        res_attr->attr.mode = S_IRUSR | S_IWUSR;
-                        res_attr->size = pci_resource_len(pdev, i);
-                        res_attr->mmap = pci_mmap_resource;
-                        res_attr->private = &pdev->resource[i];
-                        retval = sysfs_create_bin_file(&pdev->dev.kobj, res_attr);
-                        if (retval) {
-                                pci_remove_resource_files(pdev);
-                                return retval;
-                        }
-                } else {
-                        return -ENOMEM;
+                retval = pci_create_attr(pdev, i, 0);
+                /* for prefetchable resources, create a WC mappable file */
+                if (!retval && pdev->resource[i].flags & IORESOURCE_PREFETCH)
+                        retval = pci_create_attr(pdev, i, 1);
+
+                if (retval) {
+                        pci_remove_resource_files(pdev);
+                        return retval;
                 }
         }
         return 0;
diff --git a/drivers/scsi/dpt/dptsig.h b/drivers/scsi/dpt/dptsig.h
index 72c8992fdf21..a6644b332b53 100644
--- a/drivers/scsi/dpt/dptsig.h
+++ b/drivers/scsi/dpt/dptsig.h
@@ -85,7 +85,7 @@ typedef unsigned int sigINT;
 /* ------------------------------------------------------------------ */
 /* What type of processor the file is meant to run on. */
 /* This will let us know whether to read sigWORDs as high/low or low/high. */
-#define PROC_INTEL      0x00    /* Intel 80x86 */
+#define PROC_INTEL      0x00    /* Intel 80x86/ia64 */
 #define PROC_MOTOROLA   0x01    /* Motorola 68K */
 #define PROC_MIPS4000   0x02    /* MIPS RISC 4000 */
 #define PROC_ALPHA      0x03    /* DEC Alpha */
@@ -104,6 +104,7 @@ typedef unsigned int sigINT;
 #define PROC_486        0x08    /* Intel 80486 */
 #define PROC_PENTIUM    0x10    /* Intel 586 aka P5 aka Pentium */
 #define PROC_SEXIUM     0x20    /* Intel 686 aka P6 aka Pentium Pro or MMX */
+#define PROC_IA64       0x40    /* Intel IA64 processor */
 
 /* PROC_i960: */
 #define PROC_960RX      0x01    /* Intel 80960RC/RD */
diff --git a/drivers/scsi/hosts.c b/drivers/scsi/hosts.c
index 3690360d7a79..c6457bfc8a49 100644
--- a/drivers/scsi/hosts.c
+++ b/drivers/scsi/hosts.c
@@ -456,6 +456,10 @@ static int __scsi_host_match(struct device *dev, void *data)
  *
  * Return value:
  *      A pointer to located Scsi_Host or NULL.
+ *
+ *      The caller must do a scsi_host_put() to drop the reference
+ *      that scsi_host_get() took. The put_device() below dropped
+ *      the reference from class_find_device().
  **/
 struct Scsi_Host *scsi_host_lookup(unsigned short hostnum)
 {
@@ -463,9 +467,10 @@ struct Scsi_Host *scsi_host_lookup(unsigned short hostnum)
         struct Scsi_Host *shost = ERR_PTR(-ENXIO);
 
         cdev = class_find_device(&shost_class, &hostnum, __scsi_host_match);
-        if (cdev)
+        if (cdev) {
                 shost = scsi_host_get(class_to_shost(cdev));
-
+                put_device(cdev);
+        }
         return shost;
 }
 EXPORT_SYMBOL(scsi_host_lookup);
diff --git a/drivers/scsi/sr.c b/drivers/scsi/sr.c
index 7ee86d4a7618..c82df8bd4d89 100644
--- a/drivers/scsi/sr.c
+++ b/drivers/scsi/sr.c
@@ -178,6 +178,9 @@ int sr_test_unit_ready(struct scsi_device *sdev, struct scsi_sense_hdr *sshdr)
                 the_result = scsi_execute_req(sdev, cmd, DMA_NONE, NULL,
                                               0, sshdr, SR_TIMEOUT,
                                               retries--);
+                if (scsi_sense_valid(sshdr) &&
+                    sshdr->sense_key == UNIT_ATTENTION)
+                        sdev->changed = 1;
 
         } while (retries > 0 &&
                  (!scsi_status_is_good(the_result) ||
diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c
index f20952c43cb8..fd9bb777df28 100644
--- a/drivers/serial/bfin_5xx.c
+++ b/drivers/serial/bfin_5xx.c
@@ -49,6 +49,7 @@
 #define DMA_RX_YCOUNT           (PAGE_SIZE / DMA_RX_XCOUNT)
 
 #define DMA_RX_FLUSH_JIFFIES    (HZ / 50)
+#define CTS_CHECK_JIFFIES       (HZ / 50)
 
 #ifdef CONFIG_SERIAL_BFIN_DMA
 static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
@@ -290,11 +291,6 @@ static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
 {
         struct circ_buf *xmit = &uart->port.info->xmit;
 
-        if (uart->port.x_char) {
-                UART_PUT_CHAR(uart, uart->port.x_char);
-                uart->port.icount.tx++;
-                uart->port.x_char = 0;
-        }
         /*
          * Check the modem control lines before
          * transmitting anything.
@@ -306,6 +302,12 @@ static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
                 return;
         }
 
+        if (uart->port.x_char) {
+                UART_PUT_CHAR(uart, uart->port.x_char);
+                uart->port.icount.tx++;
+                uart->port.x_char = 0;
+        }
+
         while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
                 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
@@ -345,15 +347,6 @@ static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
 }
 #endif
 
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-static void bfin_serial_do_work(struct work_struct *work)
-{
-        struct bfin_serial_port *uart = container_of(work, struct bfin_serial_port, cts_workqueue);
-
-        bfin_serial_mctrl_check(uart);
-}
-#endif
-
 #ifdef CONFIG_SERIAL_BFIN_DMA
 static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
 {
@@ -361,6 +354,12 @@ static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
 
         uart->tx_done = 0;
 
+        /*
+         * Check the modem control lines before
+         * transmitting anything.
+         */
+        bfin_serial_mctrl_check(uart);
+
         if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
                 uart->tx_count = 0;
                 uart->tx_done = 1;
@@ -373,12 +372,6 @@ static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
                 uart->port.x_char = 0;
         }
 
-        /*
-         * Check the modem control lines before
-         * transmitting anything.
-         */
-        bfin_serial_mctrl_check(uart);
-
         uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
         if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
                 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
@@ -565,7 +558,10 @@ static void bfin_serial_mctrl_check(struct bfin_serial_port *uart)
         uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
         if (!(status & TIOCM_CTS)) {
                 tty->hw_stopped = 1;
-                schedule_work(&uart->cts_workqueue);
+                uart->cts_timer.data = (unsigned long)(uart);
+                uart->cts_timer.function = (void *)bfin_serial_mctrl_check;
+                uart->cts_timer.expires = jiffies + CTS_CHECK_JIFFIES;
+                add_timer(&(uart->cts_timer));
         } else {
                 tty->hw_stopped = 0;
         }
@@ -885,7 +881,7 @@ static void __init bfin_serial_init_ports(void)
                 init_timer(&(bfin_serial_ports[i].rx_dma_timer));
 #endif
 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
-                INIT_WORK(&bfin_serial_ports[i].cts_workqueue, bfin_serial_do_work);
+                init_timer(&(bfin_serial_ports[i].cts_timer));
                 bfin_serial_ports[i].cts_pin        =
                         bfin_serial_resource[i].uart_cts_pin;
                 bfin_serial_ports[i].rts_pin        =
diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c
index 3da1ab4b389d..c070b34b669d 100644
--- a/drivers/usb/core/quirks.c
+++ b/drivers/usb/core/quirks.c
@@ -47,6 +47,9 @@ static const struct usb_device_id usb_quirk_list[] = {
         /* Edirol SD-20 */
         { USB_DEVICE(0x0582, 0x0027), .driver_info = USB_QUIRK_RESET_RESUME },
 
+        /* appletouch */
+        { USB_DEVICE(0x05ac, 0x021a), .driver_info = USB_QUIRK_RESET_RESUME },
+
         /* Avision AV600U */
         { USB_DEVICE(0x0638, 0x0a13), .driver_info =
           USB_QUIRK_STRING_FETCH_255 },
diff --git a/drivers/virtio/virtio.c b/drivers/virtio/virtio.c
index 0f3c2bb7bf35..7084e7e146c0 100644
--- a/drivers/virtio/virtio.c
+++ b/drivers/virtio/virtio.c
@@ -124,9 +124,9 @@ static int virtio_dev_probe(struct device *_d)
         if (err)
                 add_status(dev, VIRTIO_CONFIG_S_FAILED);
         else {
-                add_status(dev, VIRTIO_CONFIG_S_DRIVER_OK);
                 /* They should never have set feature bits beyond 32 */
                 dev->config->set_features(dev, dev->features[0]);
+                add_status(dev, VIRTIO_CONFIG_S_DRIVER_OK);
         }
         return err;
 }
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 25b352b664d9..8662a6b7a30b 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -68,6 +68,7 @@ obj-$(CONFIG_WAFER_WDT) += wafer5823wdt.o
 obj-$(CONFIG_I6300ESB_WDT) += i6300esb.o
 obj-$(CONFIG_ITCO_WDT) += iTCO_wdt.o iTCO_vendor_support.o
 obj-$(CONFIG_IT8712F_WDT) += it8712f_wdt.o
+CFLAGS_hpwdt.o += -O
 obj-$(CONFIG_HP_WATCHDOG) += hpwdt.o
 obj-$(CONFIG_SC1200_WDT) += sc1200wdt.o
 obj-$(CONFIG_SCx200_WDT) += scx200_wdt.o
diff --git a/drivers/watchdog/hpwdt.c b/drivers/watchdog/hpwdt.c
index 6a63535fc04d..eaa3f2a79ff5 100644
--- a/drivers/watchdog/hpwdt.c
+++ b/drivers/watchdog/hpwdt.c
@@ -140,49 +140,53 @@ static struct pci_device_id hpwdt_devices[] = {
 };
 MODULE_DEVICE_TABLE(pci, hpwdt_devices);
 
+extern asmlinkage void asminline_call(struct cmn_registers *pi86Regs, unsigned long *pRomEntry);
+
 #ifndef CONFIG_X86_64
 /* --32 Bit Bios------------------------------------------------------------ */
 
 #define HPWDT_ARCH      32
 
-static void asminline_call(struct cmn_registers *pi86Regs,
-                           unsigned long *pRomEntry)
-{
-        asm("pushl       %ebp               \n\t"
-            "movl        %esp, %ebp         \n\t"
-            "pusha                          \n\t"
-            "pushf                          \n\t"
-            "push        %es                \n\t"
-            "push        %ds                \n\t"
-            "pop         %es                \n\t"
-            "movl        8(%ebp),%eax       \n\t"
-            "movl        4(%eax),%ebx       \n\t"
-            "movl        8(%eax),%ecx       \n\t"
-            "movl        12(%eax),%edx      \n\t"
-            "movl        16(%eax),%esi      \n\t"
-            "movl        20(%eax),%edi      \n\t"
-            "movl        (%eax),%eax        \n\t"
-            "push        %cs                \n\t"
-            "call        *12(%ebp)          \n\t"
-            "pushf                          \n\t"
-            "pushl       %eax               \n\t"
-            "movl        8(%ebp),%eax       \n\t"
-            "movl        %ebx,4(%eax)       \n\t"
-            "movl        %ecx,8(%eax)       \n\t"
-            "movl        %edx,12(%eax)      \n\t"
-            "movl        %esi,16(%eax)      \n\t"
-            "movl        %edi,20(%eax)      \n\t"
-            "movw        %ds,24(%eax)       \n\t"
-            "movw        %es,26(%eax)       \n\t"
-            "popl        %ebx               \n\t"
-            "movl        %ebx,(%eax)        \n\t"
-            "popl        %ebx               \n\t"
-            "movl        %ebx,28(%eax)      \n\t"
-            "pop         %es                \n\t"
-            "popf                           \n\t"
-            "popa                           \n\t"
-            "leave                          \n\t" "ret");
-}
+asm(".text                          \n\t"
+    ".align 4                       \n"
+    "asminline_call:                \n\t"
+    "pushl       %ebp               \n\t"
+    "movl        %esp, %ebp         \n\t"
+    "pusha                          \n\t"
+    "pushf                          \n\t"
+    "push        %es                \n\t"
+    "push        %ds                \n\t"
+    "pop         %es                \n\t"
+    "movl        8(%ebp),%eax       \n\t"
+    "movl        4(%eax),%ebx       \n\t"
+    "movl        8(%eax),%ecx       \n\t"
+    "movl        12(%eax),%edx      \n\t"
+    "movl        16(%eax),%esi      \n\t"
+    "movl        20(%eax),%edi      \n\t"
+    "movl        (%eax),%eax        \n\t"
+    "push        %cs                \n\t"
+    "call        *12(%ebp)          \n\t"
+    "pushf                          \n\t"
+    "pushl       %eax               \n\t"
+    "movl        8(%ebp),%eax       \n\t"
+    "movl        %ebx,4(%eax)       \n\t"
+    "movl        %ecx,8(%eax)       \n\t"
+    "movl        %edx,12(%eax)      \n\t"
+    "movl        %esi,16(%eax)      \n\t"
+    "movl        %edi,20(%eax)      \n\t"
+    "movw        %ds,24(%eax)       \n\t"
+    "movw        %es,26(%eax)       \n\t"
+    "popl        %ebx               \n\t"
+    "movl        %ebx,(%eax)        \n\t"
+    "popl        %ebx               \n\t"
+    "movl        %ebx,28(%eax)      \n\t"
+    "pop         %es                \n\t"
+    "popf                           \n\t"
+    "popa                           \n\t"
+    "leave                          \n\t"
+    "ret                            \n\t"
+    ".previous");
+
 
 /*
  *      cru_detect
@@ -333,43 +337,44 @@ static int __devinit detect_cru_service(void)
 
 #define HPWDT_ARCH      64
 
-static void asminline_call(struct cmn_registers *pi86Regs,
-                           unsigned long *pRomEntry)
-{
-        asm("pushq      %rbp            \n\t"
-            "movq       %rsp, %rbp      \n\t"
-            "pushq      %rax            \n\t"
-            "pushq      %rbx            \n\t"
-            "pushq      %rdx            \n\t"
-            "pushq      %r12            \n\t"
-            "pushq      %r9             \n\t"
-            "movq       %rsi, %r12      \n\t"
-            "movq       %rdi, %r9       \n\t"
-            "movl       4(%r9),%ebx     \n\t"
-            "movl       8(%r9),%ecx     \n\t"
-            "movl       12(%r9),%edx    \n\t"
-            "movl       16(%r9),%esi    \n\t"
-            "movl       20(%r9),%edi    \n\t"
-            "movl       (%r9),%eax      \n\t"
-            "call       *%r12           \n\t"
-            "pushfq                     \n\t"
-            "popq        %r12           \n\t"
-            "popfq                      \n\t"
-            "movl       %eax, (%r9)     \n\t"
-            "movl       %ebx, 4(%r9)    \n\t"
-            "movl       %ecx, 8(%r9)    \n\t"
-            "movl       %edx, 12(%r9)   \n\t"
-            "movl       %esi, 16(%r9)   \n\t"
-            "movl       %edi, 20(%r9)   \n\t"
-            "movq       %r12, %rax      \n\t"
-            "movl       %eax, 28(%r9)   \n\t"
-            "popq       %r9             \n\t"
-            "popq       %r12            \n\t"
-            "popq       %rdx            \n\t"
-            "popq       %rbx            \n\t"
-            "popq       %rax            \n\t"
-            "leave                      \n\t" "ret");
-}
+asm(".text                      \n\t"
+    ".align 4                   \n"
+    "asminline_call:            \n\t"
+    "pushq      %rbp            \n\t"
+    "movq       %rsp, %rbp      \n\t"
+    "pushq      %rax            \n\t"
+    "pushq      %rbx            \n\t"
+    "pushq      %rdx            \n\t"
+    "pushq      %r12            \n\t"
+    "pushq      %r9             \n\t"
+    "movq       %rsi, %r12      \n\t"
+    "movq       %rdi, %r9       \n\t"
+    "movl       4(%r9),%ebx     \n\t"
+    "movl       8(%r9),%ecx     \n\t"
+    "movl       12(%r9),%edx    \n\t"
+    "movl       16(%r9),%esi    \n\t"
+    "movl       20(%r9),%edi    \n\t"
+    "movl       (%r9),%eax      \n\t"
+    "call       *%r12           \n\t"
+    "pushfq                     \n\t"
+    "popq        %r12           \n\t"
+    "popfq                      \n\t"
+    "movl       %eax, (%r9)     \n\t"
+    "movl       %ebx, 4(%r9)    \n\t"
+    "movl       %ecx, 8(%r9)    \n\t"
+    "movl       %edx, 12(%r9)   \n\t"
+    "movl       %esi, 16(%r9)   \n\t"
+    "movl       %edi, 20(%r9)   \n\t"
+    "movq       %r12, %rax      \n\t"
+    "movl       %eax, 28(%r9)   \n\t"
+    "popq       %r9             \n\t"
+    "popq       %r12            \n\t"
+    "popq       %rdx            \n\t"
+    "popq       %rbx            \n\t"
+    "popq       %rax            \n\t"
+    "leave                      \n\t"
+    "ret                        \n\t"
+    ".previous");
 
 /*
  *      dmi_find_cru
@@ -418,20 +423,23 @@ static int hpwdt_pretimeout(struct notifier_block *nb, unsigned long ulReason,
         static unsigned long rom_pl;
         static int die_nmi_called;
 
-        if (ulReason == DIE_NMI || ulReason == DIE_NMI_IPI) {
-                spin_lock_irqsave(&rom_lock, rom_pl);
-                if (!die_nmi_called)
-                        asminline_call(&cmn_regs, cru_rom_addr);
-                die_nmi_called = 1;
-                spin_unlock_irqrestore(&rom_lock, rom_pl);
-                if (cmn_regs.u1.ral != 0) {
-                        panic("An NMI occurred, please see the Integrated "
-                              "Management Log for details.\n");
-                }
+        if (ulReason != DIE_NMI && ulReason != DIE_NMI_IPI)
+                return NOTIFY_OK;
+
+        spin_lock_irqsave(&rom_lock, rom_pl);
+        if (!die_nmi_called)
+                asminline_call(&cmn_regs, cru_rom_addr);
+        die_nmi_called = 1;
+        spin_unlock_irqrestore(&rom_lock, rom_pl);
+        if (cmn_regs.u1.ral == 0) {
+                printk(KERN_WARNING "hpwdt: An NMI occurred, "
+                       "but unable to determine source.\n");
+        } else {
+                panic("An NMI occurred, please see the Integrated "
+                        "Management Log for details.\n");
         }
 
-        die_nmi_called = 0;
-        return NOTIFY_DONE;
+        return NOTIFY_STOP;
 }
 
 /*