diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/hw.c | 162 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/hw.h | 2 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/main.c | 8 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/reg.h | 3 |
4 files changed, 103 insertions, 72 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c index b6c6cca07812..82a24408528b 100644 --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c | |||
@@ -965,7 +965,7 @@ int ath9k_hw_init(struct ath_hw *ah) | |||
965 | ath9k_hw_init_mode_regs(ah); | 965 | ath9k_hw_init_mode_regs(ah); |
966 | 966 | ||
967 | if (ah->is_pciexpress) | 967 | if (ah->is_pciexpress) |
968 | ath9k_hw_configpcipowersave(ah, 0); | 968 | ath9k_hw_configpcipowersave(ah, 0, 0); |
969 | else | 969 | else |
970 | ath9k_hw_disablepcie(ah); | 970 | ath9k_hw_disablepcie(ah); |
971 | 971 | ||
@@ -3005,9 +3005,10 @@ void ath9k_ps_restore(struct ath_softc *sc) | |||
3005 | * Programming the SerDes must go through the same 288 bit serial shift | 3005 | * Programming the SerDes must go through the same 288 bit serial shift |
3006 | * register as the other analog registers. Hence the 9 writes. | 3006 | * register as the other analog registers. Hence the 9 writes. |
3007 | */ | 3007 | */ |
3008 | void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) | 3008 | void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off) |
3009 | { | 3009 | { |
3010 | u8 i; | 3010 | u8 i; |
3011 | u32 val; | ||
3011 | 3012 | ||
3012 | if (ah->is_pciexpress != true) | 3013 | if (ah->is_pciexpress != true) |
3013 | return; | 3014 | return; |
@@ -3017,84 +3018,113 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) | |||
3017 | return; | 3018 | return; |
3018 | 3019 | ||
3019 | /* Nothing to do on restore for 11N */ | 3020 | /* Nothing to do on restore for 11N */ |
3020 | if (restore) | 3021 | if (!restore) { |
3021 | return; | 3022 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
3022 | 3023 | /* | |
3023 | if (AR_SREV_9280_20_OR_LATER(ah)) { | 3024 | * AR9280 2.0 or later chips use SerDes values from the |
3024 | /* | 3025 | * initvals.h initialized depending on chipset during |
3025 | * AR9280 2.0 or later chips use SerDes values from the | 3026 | * ath9k_hw_init() |
3026 | * initvals.h initialized depending on chipset during | 3027 | */ |
3027 | * ath9k_hw_init() | 3028 | for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { |
3028 | */ | 3029 | REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), |
3029 | for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { | 3030 | INI_RA(&ah->iniPcieSerdes, i, 1)); |
3030 | REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), | 3031 | } |
3031 | INI_RA(&ah->iniPcieSerdes, i, 1)); | 3032 | } else if (AR_SREV_9280(ah) && |
3032 | } | 3033 | (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) { |
3033 | } else if (AR_SREV_9280(ah) && | 3034 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00); |
3034 | (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) { | 3035 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); |
3035 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00); | 3036 | |
3036 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | 3037 | /* RX shut off when elecidle is asserted */ |
3038 | REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019); | ||
3039 | REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); | ||
3040 | REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); | ||
3041 | |||
3042 | /* Shut off CLKREQ active in L1 */ | ||
3043 | if (ah->config.pcie_clock_req) | ||
3044 | REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); | ||
3045 | else | ||
3046 | REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd); | ||
3037 | 3047 | ||
3038 | /* RX shut off when elecidle is asserted */ | 3048 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); |
3039 | REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019); | 3049 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); |
3040 | REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); | 3050 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007); |
3041 | REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); | ||
3042 | 3051 | ||
3043 | /* Shut off CLKREQ active in L1 */ | 3052 | /* Load the new settings */ |
3044 | if (ah->config.pcie_clock_req) | 3053 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
3045 | REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); | ||
3046 | else | ||
3047 | REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd); | ||
3048 | 3054 | ||
3049 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); | 3055 | } else { |
3050 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | 3056 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); |
3051 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007); | 3057 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); |
3052 | 3058 | ||
3053 | /* Load the new settings */ | 3059 | /* RX shut off when elecidle is asserted */ |
3054 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); | 3060 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); |
3061 | REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); | ||
3062 | REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); | ||
3055 | 3063 | ||
3056 | } else { | 3064 | /* |
3057 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); | 3065 | * Ignore ah->ah_config.pcie_clock_req setting for |
3058 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | 3066 | * pre-AR9280 11n |
3067 | */ | ||
3068 | REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); | ||
3059 | 3069 | ||
3060 | /* RX shut off when elecidle is asserted */ | 3070 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); |
3061 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); | 3071 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); |
3062 | REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); | 3072 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); |
3063 | REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); | ||
3064 | 3073 | ||
3065 | /* | 3074 | /* Load the new settings */ |
3066 | * Ignore ah->ah_config.pcie_clock_req setting for | 3075 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
3067 | * pre-AR9280 11n | 3076 | } |
3068 | */ | ||
3069 | REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); | ||
3070 | 3077 | ||
3071 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); | 3078 | udelay(1000); |
3072 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | ||
3073 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); | ||
3074 | 3079 | ||
3075 | /* Load the new settings */ | 3080 | /* set bit 19 to allow forcing of pcie core into L1 state */ |
3076 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); | 3081 | REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); |
3077 | } | ||
3078 | 3082 | ||
3079 | udelay(1000); | 3083 | /* Several PCIe massages to ensure proper behaviour */ |
3084 | if (ah->config.pcie_waen) { | ||
3085 | val = ah->config.pcie_waen; | ||
3086 | if (!power_off) | ||
3087 | val &= (~AR_WA_D3_L1_DISABLE); | ||
3088 | } else { | ||
3089 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || | ||
3090 | AR_SREV_9287(ah)) { | ||
3091 | val = AR9285_WA_DEFAULT; | ||
3092 | if (!power_off) | ||
3093 | val &= (~AR_WA_D3_L1_DISABLE); | ||
3094 | } else if (AR_SREV_9280(ah)) { | ||
3095 | /* | ||
3096 | * On AR9280 chips bit 22 of 0x4004 needs to be | ||
3097 | * set otherwise card may disappear. | ||
3098 | */ | ||
3099 | val = AR9280_WA_DEFAULT; | ||
3100 | if (!power_off) | ||
3101 | val &= (~AR_WA_D3_L1_DISABLE); | ||
3102 | } else | ||
3103 | val = AR_WA_DEFAULT; | ||
3104 | } | ||
3080 | 3105 | ||
3081 | /* set bit 19 to allow forcing of pcie core into L1 state */ | 3106 | REG_WRITE(ah, AR_WA, val); |
3082 | REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); | 3107 | } |
3083 | 3108 | ||
3084 | /* Several PCIe massages to ensure proper behaviour */ | 3109 | if (power_off) { |
3085 | if (ah->config.pcie_waen) { | ||
3086 | REG_WRITE(ah, AR_WA, ah->config.pcie_waen); | ||
3087 | } else { | ||
3088 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah)) | ||
3089 | REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT); | ||
3090 | /* | 3110 | /* |
3091 | * On AR9280 chips bit 22 of 0x4004 needs to be set to | 3111 | * Set PCIe workaround bits |
3092 | * otherwise card may disappear. | 3112 | * bit 14 in WA register (disable L1) should only |
3113 | * be set when device enters D3 and be cleared | ||
3114 | * when device comes back to D0. | ||
3093 | */ | 3115 | */ |
3094 | else if (AR_SREV_9280(ah)) | 3116 | if (ah->config.pcie_waen) { |
3095 | REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); | 3117 | if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE) |
3096 | else | 3118 | REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE); |
3097 | REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); | 3119 | } else { |
3120 | if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) || | ||
3121 | AR_SREV_9287(ah)) && | ||
3122 | (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) || | ||
3123 | (AR_SREV_9280(ah) && | ||
3124 | (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) { | ||
3125 | REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE); | ||
3126 | } | ||
3127 | } | ||
3098 | } | 3128 | } |
3099 | } | 3129 | } |
3100 | 3130 | ||
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h index 9106a0b537dd..75c3041aadcb 100644 --- a/drivers/net/wireless/ath/ath9k/hw.h +++ b/drivers/net/wireless/ath/ath9k/hw.h | |||
@@ -650,7 +650,7 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, | |||
650 | const struct ath9k_beacon_state *bs); | 650 | const struct ath9k_beacon_state *bs); |
651 | bool ath9k_hw_setpower(struct ath_hw *ah, | 651 | bool ath9k_hw_setpower(struct ath_hw *ah, |
652 | enum ath9k_power_mode mode); | 652 | enum ath9k_power_mode mode); |
653 | void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore); | 653 | void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off); |
654 | 654 | ||
655 | /* Interrupt Handling */ | 655 | /* Interrupt Handling */ |
656 | bool ath9k_hw_intrpend(struct ath_hw *ah); | 656 | bool ath9k_hw_intrpend(struct ath_hw *ah); |
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c index 3dc7b5a13e64..5055f1842b89 100644 --- a/drivers/net/wireless/ath/ath9k/main.c +++ b/drivers/net/wireless/ath/ath9k/main.c | |||
@@ -1131,7 +1131,7 @@ void ath_radio_enable(struct ath_softc *sc) | |||
1131 | int r; | 1131 | int r; |
1132 | 1132 | ||
1133 | ath9k_ps_wakeup(sc); | 1133 | ath9k_ps_wakeup(sc); |
1134 | ath9k_hw_configpcipowersave(ah, 0); | 1134 | ath9k_hw_configpcipowersave(ah, 0, 0); |
1135 | 1135 | ||
1136 | if (!ah->curchan) | 1136 | if (!ah->curchan) |
1137 | ah->curchan = ath_get_curchannel(sc, sc->hw); | 1137 | ah->curchan = ath_get_curchannel(sc, sc->hw); |
@@ -1202,7 +1202,7 @@ void ath_radio_disable(struct ath_softc *sc) | |||
1202 | spin_unlock_bh(&sc->sc_resetlock); | 1202 | spin_unlock_bh(&sc->sc_resetlock); |
1203 | 1203 | ||
1204 | ath9k_hw_phy_disable(ah); | 1204 | ath9k_hw_phy_disable(ah); |
1205 | ath9k_hw_configpcipowersave(ah, 1); | 1205 | ath9k_hw_configpcipowersave(ah, 1, 1); |
1206 | ath9k_ps_restore(sc); | 1206 | ath9k_ps_restore(sc); |
1207 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); | 1207 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); |
1208 | } | 1208 | } |
@@ -1942,7 +1942,7 @@ static int ath9k_start(struct ieee80211_hw *hw) | |||
1942 | init_channel = ath_get_curchannel(sc, hw); | 1942 | init_channel = ath_get_curchannel(sc, hw); |
1943 | 1943 | ||
1944 | /* Reset SERDES registers */ | 1944 | /* Reset SERDES registers */ |
1945 | ath9k_hw_configpcipowersave(sc->sc_ah, 0); | 1945 | ath9k_hw_configpcipowersave(sc->sc_ah, 0, 0); |
1946 | 1946 | ||
1947 | /* | 1947 | /* |
1948 | * The basic interface to setting the hardware in a good | 1948 | * The basic interface to setting the hardware in a good |
@@ -2170,7 +2170,7 @@ static void ath9k_stop(struct ieee80211_hw *hw) | |||
2170 | 2170 | ||
2171 | /* disable HAL and put h/w to sleep */ | 2171 | /* disable HAL and put h/w to sleep */ |
2172 | ath9k_hw_disable(sc->sc_ah); | 2172 | ath9k_hw_disable(sc->sc_ah); |
2173 | ath9k_hw_configpcipowersave(sc->sc_ah, 1); | 2173 | ath9k_hw_configpcipowersave(sc->sc_ah, 1, 1); |
2174 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); | 2174 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); |
2175 | 2175 | ||
2176 | sc->sc_flags |= SC_OP_INVALID; | 2176 | sc->sc_flags |= SC_OP_INVALID; |
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h index e5c29eb86e80..d83b77f821e9 100644 --- a/drivers/net/wireless/ath/ath9k/reg.h +++ b/drivers/net/wireless/ath/ath9k/reg.h | |||
@@ -676,8 +676,9 @@ | |||
676 | #define AR_RC_HOSTIF 0x00000100 | 676 | #define AR_RC_HOSTIF 0x00000100 |
677 | 677 | ||
678 | #define AR_WA 0x4004 | 678 | #define AR_WA 0x4004 |
679 | #define AR_WA_D3_L1_DISABLE (1 << 14) | ||
679 | #define AR9285_WA_DEFAULT 0x004a05cb | 680 | #define AR9285_WA_DEFAULT 0x004a05cb |
680 | #define AR9280_WA_DEFAULT 0x0040073f | 681 | #define AR9280_WA_DEFAULT 0x0040073b |
681 | #define AR_WA_DEFAULT 0x0000073f | 682 | #define AR_WA_DEFAULT 0x0000073f |
682 | 683 | ||
683 | 684 | ||