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-rw-r--r--drivers/spi/Kconfig7
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/spi_imx.c1770
3 files changed, 0 insertions, 1778 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2c733c27db2f..86056d1409b1 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -116,13 +116,6 @@ config SPI_GPIO
116 GPIO operations, you should be able to leverage that for better 116 GPIO operations, you should be able to leverage that for better
117 speed with a custom version of this driver; see the source code. 117 speed with a custom version of this driver; see the source code.
118 118
119config SPI_IMX
120 tristate "Freescale iMX SPI controller"
121 depends on ARCH_MX1 && EXPERIMENTAL
122 help
123 This enables using the Freescale iMX SPI controller in master
124 mode.
125
126config SPI_LM70_LLP 119config SPI_LM70_LLP
127 tristate "Parallel port adapter for LM70 eval board (DEVELOPMENT)" 120 tristate "Parallel port adapter for LM70 eval board (DEVELOPMENT)"
128 depends on PARPORT && EXPERIMENTAL 121 depends on PARPORT && EXPERIMENTAL
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3de408d294ba..0f20a70b2fa9 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -17,7 +17,6 @@ obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o
17obj-$(CONFIG_SPI_AU1550) += au1550_spi.o 17obj-$(CONFIG_SPI_AU1550) += au1550_spi.o
18obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o 18obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
19obj-$(CONFIG_SPI_GPIO) += spi_gpio.o 19obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
20obj-$(CONFIG_SPI_IMX) += spi_imx.o
21obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o 20obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
22obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o 21obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o
23obj-$(CONFIG_SPI_OMAP_UWIRE) += omap_uwire.o 22obj-$(CONFIG_SPI_OMAP_UWIRE) += omap_uwire.o
diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
deleted file mode 100644
index c195e45f7f35..000000000000
--- a/drivers/spi/spi_imx.c
+++ /dev/null
@@ -1,1770 +0,0 @@
1/*
2 * drivers/spi/spi_imx.c
3 *
4 * Copyright (C) 2006 SWAPP
5 * Andrea Paterniani <a.paterniani@swapp-eng.it>
6 *
7 * Initial version inspired by:
8 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21#include <linux/init.h>
22#include <linux/module.h>
23#include <linux/device.h>
24#include <linux/ioport.h>
25#include <linux/errno.h>
26#include <linux/interrupt.h>
27#include <linux/platform_device.h>
28#include <linux/dma-mapping.h>
29#include <linux/spi/spi.h>
30#include <linux/workqueue.h>
31#include <linux/delay.h>
32#include <linux/clk.h>
33
34#include <asm/io.h>
35#include <asm/irq.h>
36#include <asm/delay.h>
37
38#include <mach/hardware.h>
39#include <mach/imx-dma.h>
40#include <mach/spi_imx.h>
41
42/*-------------------------------------------------------------------------*/
43/* SPI Registers offsets from peripheral base address */
44#define SPI_RXDATA (0x00)
45#define SPI_TXDATA (0x04)
46#define SPI_CONTROL (0x08)
47#define SPI_INT_STATUS (0x0C)
48#define SPI_TEST (0x10)
49#define SPI_PERIOD (0x14)
50#define SPI_DMA (0x18)
51#define SPI_RESET (0x1C)
52
53/* SPI Control Register Bit Fields & Masks */
54#define SPI_CONTROL_BITCOUNT_MASK (0xF) /* Bit Count Mask */
55#define SPI_CONTROL_BITCOUNT(n) (((n) - 1) & SPI_CONTROL_BITCOUNT_MASK)
56#define SPI_CONTROL_POL (0x1 << 4) /* Clock Polarity Mask */
57#define SPI_CONTROL_POL_ACT_HIGH (0x0 << 4) /* Active high pol. (0=idle) */
58#define SPI_CONTROL_POL_ACT_LOW (0x1 << 4) /* Active low pol. (1=idle) */
59#define SPI_CONTROL_PHA (0x1 << 5) /* Clock Phase Mask */
60#define SPI_CONTROL_PHA_0 (0x0 << 5) /* Clock Phase 0 */
61#define SPI_CONTROL_PHA_1 (0x1 << 5) /* Clock Phase 1 */
62#define SPI_CONTROL_SSCTL (0x1 << 6) /* /SS Waveform Select Mask */
63#define SPI_CONTROL_SSCTL_0 (0x0 << 6) /* Master: /SS stays low between SPI burst
64 Slave: RXFIFO advanced by BIT_COUNT */
65#define SPI_CONTROL_SSCTL_1 (0x1 << 6) /* Master: /SS insert pulse between SPI burst
66 Slave: RXFIFO advanced by /SS rising edge */
67#define SPI_CONTROL_SSPOL (0x1 << 7) /* /SS Polarity Select Mask */
68#define SPI_CONTROL_SSPOL_ACT_LOW (0x0 << 7) /* /SS Active low */
69#define SPI_CONTROL_SSPOL_ACT_HIGH (0x1 << 7) /* /SS Active high */
70#define SPI_CONTROL_XCH (0x1 << 8) /* Exchange */
71#define SPI_CONTROL_SPIEN (0x1 << 9) /* SPI Module Enable */
72#define SPI_CONTROL_MODE (0x1 << 10) /* SPI Mode Select Mask */
73#define SPI_CONTROL_MODE_SLAVE (0x0 << 10) /* SPI Mode Slave */
74#define SPI_CONTROL_MODE_MASTER (0x1 << 10) /* SPI Mode Master */
75#define SPI_CONTROL_DRCTL (0x3 << 11) /* /SPI_RDY Control Mask */
76#define SPI_CONTROL_DRCTL_0 (0x0 << 11) /* Ignore /SPI_RDY */
77#define SPI_CONTROL_DRCTL_1 (0x1 << 11) /* /SPI_RDY falling edge triggers input */
78#define SPI_CONTROL_DRCTL_2 (0x2 << 11) /* /SPI_RDY active low level triggers input */
79#define SPI_CONTROL_DATARATE (0x7 << 13) /* Data Rate Mask */
80#define SPI_PERCLK2_DIV_MIN (0) /* PERCLK2:4 */
81#define SPI_PERCLK2_DIV_MAX (7) /* PERCLK2:512 */
82#define SPI_CONTROL_DATARATE_MIN (SPI_PERCLK2_DIV_MAX << 13)
83#define SPI_CONTROL_DATARATE_MAX (SPI_PERCLK2_DIV_MIN << 13)
84#define SPI_CONTROL_DATARATE_BAD (SPI_CONTROL_DATARATE_MIN + 1)
85
86/* SPI Interrupt/Status Register Bit Fields & Masks */
87#define SPI_STATUS_TE (0x1 << 0) /* TXFIFO Empty Status */
88#define SPI_STATUS_TH (0x1 << 1) /* TXFIFO Half Status */
89#define SPI_STATUS_TF (0x1 << 2) /* TXFIFO Full Status */
90#define SPI_STATUS_RR (0x1 << 3) /* RXFIFO Data Ready Status */
91#define SPI_STATUS_RH (0x1 << 4) /* RXFIFO Half Status */
92#define SPI_STATUS_RF (0x1 << 5) /* RXFIFO Full Status */
93#define SPI_STATUS_RO (0x1 << 6) /* RXFIFO Overflow */
94#define SPI_STATUS_BO (0x1 << 7) /* Bit Count Overflow */
95#define SPI_STATUS (0xFF) /* SPI Status Mask */
96#define SPI_INTEN_TE (0x1 << 8) /* TXFIFO Empty Interrupt Enable */
97#define SPI_INTEN_TH (0x1 << 9) /* TXFIFO Half Interrupt Enable */
98#define SPI_INTEN_TF (0x1 << 10) /* TXFIFO Full Interrupt Enable */
99#define SPI_INTEN_RE (0x1 << 11) /* RXFIFO Data Ready Interrupt Enable */
100#define SPI_INTEN_RH (0x1 << 12) /* RXFIFO Half Interrupt Enable */
101#define SPI_INTEN_RF (0x1 << 13) /* RXFIFO Full Interrupt Enable */
102#define SPI_INTEN_RO (0x1 << 14) /* RXFIFO Overflow Interrupt Enable */
103#define SPI_INTEN_BO (0x1 << 15) /* Bit Count Overflow Interrupt Enable */
104#define SPI_INTEN (0xFF << 8) /* SPI Interrupt Enable Mask */
105
106/* SPI Test Register Bit Fields & Masks */
107#define SPI_TEST_TXCNT (0xF << 0) /* TXFIFO Counter */
108#define SPI_TEST_RXCNT_LSB (4) /* RXFIFO Counter LSB */
109#define SPI_TEST_RXCNT (0xF << 4) /* RXFIFO Counter */
110#define SPI_TEST_SSTATUS (0xF << 8) /* State Machine Status */
111#define SPI_TEST_LBC (0x1 << 14) /* Loop Back Control */
112
113/* SPI Period Register Bit Fields & Masks */
114#define SPI_PERIOD_WAIT (0x7FFF << 0) /* Wait Between Transactions */
115#define SPI_PERIOD_MAX_WAIT (0x7FFF) /* Max Wait Between
116 Transactions */
117#define SPI_PERIOD_CSRC (0x1 << 15) /* Period Clock Source Mask */
118#define SPI_PERIOD_CSRC_BCLK (0x0 << 15) /* Period Clock Source is
119 Bit Clock */
120#define SPI_PERIOD_CSRC_32768 (0x1 << 15) /* Period Clock Source is
121 32.768 KHz Clock */
122
123/* SPI DMA Register Bit Fields & Masks */
124#define SPI_DMA_RHDMA (0x1 << 4) /* RXFIFO Half Status */
125#define SPI_DMA_RFDMA (0x1 << 5) /* RXFIFO Full Status */
126#define SPI_DMA_TEDMA (0x1 << 6) /* TXFIFO Empty Status */
127#define SPI_DMA_THDMA (0x1 << 7) /* TXFIFO Half Status */
128#define SPI_DMA_RHDEN (0x1 << 12) /* RXFIFO Half DMA Request Enable */
129#define SPI_DMA_RFDEN (0x1 << 13) /* RXFIFO Full DMA Request Enable */
130#define SPI_DMA_TEDEN (0x1 << 14) /* TXFIFO Empty DMA Request Enable */
131#define SPI_DMA_THDEN (0x1 << 15) /* TXFIFO Half DMA Request Enable */
132
133/* SPI Soft Reset Register Bit Fields & Masks */
134#define SPI_RESET_START (0x1) /* Start */
135
136/* Default SPI configuration values */
137#define SPI_DEFAULT_CONTROL \
138( \
139 SPI_CONTROL_BITCOUNT(16) | \
140 SPI_CONTROL_POL_ACT_HIGH | \
141 SPI_CONTROL_PHA_0 | \
142 SPI_CONTROL_SPIEN | \
143 SPI_CONTROL_SSCTL_1 | \
144 SPI_CONTROL_MODE_MASTER | \
145 SPI_CONTROL_DRCTL_0 | \
146 SPI_CONTROL_DATARATE_MIN \
147)
148#define SPI_DEFAULT_ENABLE_LOOPBACK (0)
149#define SPI_DEFAULT_ENABLE_DMA (0)
150#define SPI_DEFAULT_PERIOD_WAIT (8)
151/*-------------------------------------------------------------------------*/
152
153
154/*-------------------------------------------------------------------------*/
155/* TX/RX SPI FIFO size */
156#define SPI_FIFO_DEPTH (8)
157#define SPI_FIFO_BYTE_WIDTH (2)
158#define SPI_FIFO_OVERFLOW_MARGIN (2)
159
160/* DMA burst length for half full/empty request trigger */
161#define SPI_DMA_BLR (SPI_FIFO_DEPTH * SPI_FIFO_BYTE_WIDTH / 2)
162
163/* Dummy char output to achieve reads.
164 Choosing something different from all zeroes may help pattern recogition
165 for oscilloscope analysis, but may break some drivers. */
166#define SPI_DUMMY_u8 0
167#define SPI_DUMMY_u16 ((SPI_DUMMY_u8 << 8) | SPI_DUMMY_u8)
168#define SPI_DUMMY_u32 ((SPI_DUMMY_u16 << 16) | SPI_DUMMY_u16)
169
170/**
171 * Macro to change a u32 field:
172 * @r : register to edit
173 * @m : bit mask
174 * @v : new value for the field correctly bit-alligned
175*/
176#define u32_EDIT(r, m, v) r = (r & ~(m)) | (v)
177
178/* Message state */
179#define START_STATE ((void*)0)
180#define RUNNING_STATE ((void*)1)
181#define DONE_STATE ((void*)2)
182#define ERROR_STATE ((void*)-1)
183
184/* Queue state */
185#define QUEUE_RUNNING (0)
186#define QUEUE_STOPPED (1)
187
188#define IS_DMA_ALIGNED(x) (((u32)(x) & 0x03) == 0)
189#define DMA_ALIGNMENT 4
190/*-------------------------------------------------------------------------*/
191
192
193/*-------------------------------------------------------------------------*/
194/* Driver data structs */
195
196/* Context */
197struct driver_data {
198 /* Driver model hookup */
199 struct platform_device *pdev;
200
201 /* SPI framework hookup */
202 struct spi_master *master;
203
204 /* IMX hookup */
205 struct spi_imx_master *master_info;
206
207 /* Memory resources and SPI regs virtual address */
208 struct resource *ioarea;
209 void __iomem *regs;
210
211 /* SPI RX_DATA physical address */
212 dma_addr_t rd_data_phys;
213
214 /* Driver message queue */
215 struct workqueue_struct *workqueue;
216 struct work_struct work;
217 spinlock_t lock;
218 struct list_head queue;
219 int busy;
220 int run;
221
222 /* Message Transfer pump */
223 struct tasklet_struct pump_transfers;
224
225 /* Current message, transfer and state */
226 struct spi_message *cur_msg;
227 struct spi_transfer *cur_transfer;
228 struct chip_data *cur_chip;
229
230 /* Rd / Wr buffers pointers */
231 size_t len;
232 void *tx;
233 void *tx_end;
234 void *rx;
235 void *rx_end;
236
237 u8 rd_only;
238 u8 n_bytes;
239 int cs_change;
240
241 /* Function pointers */
242 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
243 void (*cs_control)(u32 command);
244
245 /* DMA setup */
246 int rx_channel;
247 int tx_channel;
248 dma_addr_t rx_dma;
249 dma_addr_t tx_dma;
250 int rx_dma_needs_unmap;
251 int tx_dma_needs_unmap;
252 size_t tx_map_len;
253 u32 dummy_dma_buf ____cacheline_aligned;
254
255 struct clk *clk;
256};
257
258/* Runtime state */
259struct chip_data {
260 u32 control;
261 u32 period;
262 u32 test;
263
264 u8 enable_dma:1;
265 u8 bits_per_word;
266 u8 n_bytes;
267 u32 max_speed_hz;
268
269 void (*cs_control)(u32 command);
270};
271/*-------------------------------------------------------------------------*/
272
273
274static void pump_messages(struct work_struct *work);
275
276static void flush(struct driver_data *drv_data)
277{
278 void __iomem *regs = drv_data->regs;
279 u32 control;
280
281 dev_dbg(&drv_data->pdev->dev, "flush\n");
282
283 /* Wait for end of transaction */
284 do {
285 control = readl(regs + SPI_CONTROL);
286 } while (control & SPI_CONTROL_XCH);
287
288 /* Release chip select if requested, transfer delays are
289 handled in pump_transfers */
290 if (drv_data->cs_change)
291 drv_data->cs_control(SPI_CS_DEASSERT);
292
293 /* Disable SPI to flush FIFOs */
294 writel(control & ~SPI_CONTROL_SPIEN, regs + SPI_CONTROL);
295 writel(control, regs + SPI_CONTROL);
296}
297
298static void restore_state(struct driver_data *drv_data)
299{
300 void __iomem *regs = drv_data->regs;
301 struct chip_data *chip = drv_data->cur_chip;
302
303 /* Load chip registers */
304 dev_dbg(&drv_data->pdev->dev,
305 "restore_state\n"
306 " test = 0x%08X\n"
307 " control = 0x%08X\n",
308 chip->test,
309 chip->control);
310 writel(chip->test, regs + SPI_TEST);
311 writel(chip->period, regs + SPI_PERIOD);
312 writel(0, regs + SPI_INT_STATUS);
313 writel(chip->control, regs + SPI_CONTROL);
314}
315
316static void null_cs_control(u32 command)
317{
318}
319
320static inline u32 data_to_write(struct driver_data *drv_data)
321{
322 return ((u32)(drv_data->tx_end - drv_data->tx)) / drv_data->n_bytes;
323}
324
325static inline u32 data_to_read(struct driver_data *drv_data)
326{
327 return ((u32)(drv_data->rx_end - drv_data->rx)) / drv_data->n_bytes;
328}
329
330static int write(struct driver_data *drv_data)
331{
332 void __iomem *regs = drv_data->regs;
333 void *tx = drv_data->tx;
334 void *tx_end = drv_data->tx_end;
335 u8 n_bytes = drv_data->n_bytes;
336 u32 remaining_writes;
337 u32 fifo_avail_space;
338 u32 n;
339 u16 d;
340
341 /* Compute how many fifo writes to do */
342 remaining_writes = (u32)(tx_end - tx) / n_bytes;
343 fifo_avail_space = SPI_FIFO_DEPTH -
344 (readl(regs + SPI_TEST) & SPI_TEST_TXCNT);
345 if (drv_data->rx && (fifo_avail_space > SPI_FIFO_OVERFLOW_MARGIN))
346 /* Fix misunderstood receive overflow */
347 fifo_avail_space -= SPI_FIFO_OVERFLOW_MARGIN;
348 n = min(remaining_writes, fifo_avail_space);
349
350 dev_dbg(&drv_data->pdev->dev,
351 "write type %s\n"
352 " remaining writes = %d\n"
353 " fifo avail space = %d\n"
354 " fifo writes = %d\n",
355 (n_bytes == 1) ? "u8" : "u16",
356 remaining_writes,
357 fifo_avail_space,
358 n);
359
360 if (n > 0) {
361 /* Fill SPI TXFIFO */
362 if (drv_data->rd_only) {
363 tx += n * n_bytes;
364 while (n--)
365 writel(SPI_DUMMY_u16, regs + SPI_TXDATA);
366 } else {
367 if (n_bytes == 1) {
368 while (n--) {
369 d = *(u8*)tx;
370 writel(d, regs + SPI_TXDATA);
371 tx += 1;
372 }
373 } else {
374 while (n--) {
375 d = *(u16*)tx;
376 writel(d, regs + SPI_TXDATA);
377 tx += 2;
378 }
379 }
380 }
381
382 /* Trigger transfer */
383 writel(readl(regs + SPI_CONTROL) | SPI_CONTROL_XCH,
384 regs + SPI_CONTROL);
385
386 /* Update tx pointer */
387 drv_data->tx = tx;
388 }
389
390 return (tx >= tx_end);
391}
392
393static int read(struct driver_data *drv_data)
394{
395 void __iomem *regs = drv_data->regs;
396 void *rx = drv_data->rx;
397 void *rx_end = drv_data->rx_end;
398 u8 n_bytes = drv_data->n_bytes;
399 u32 remaining_reads;
400 u32 fifo_rxcnt;
401 u32 n;
402 u16 d;
403
404 /* Compute how many fifo reads to do */
405 remaining_reads = (u32)(rx_end - rx) / n_bytes;
406 fifo_rxcnt = (readl(regs + SPI_TEST) & SPI_TEST_RXCNT) >>
407 SPI_TEST_RXCNT_LSB;
408 n = min(remaining_reads, fifo_rxcnt);
409
410 dev_dbg(&drv_data->pdev->dev,
411 "read type %s\n"
412 " remaining reads = %d\n"
413 " fifo rx count = %d\n"
414 " fifo reads = %d\n",
415 (n_bytes == 1) ? "u8" : "u16",
416 remaining_reads,
417 fifo_rxcnt,
418 n);
419
420 if (n > 0) {
421 /* Read SPI RXFIFO */
422 if (n_bytes == 1) {
423 while (n--) {
424 d = readl(regs + SPI_RXDATA);
425 *((u8*)rx) = d;
426 rx += 1;
427 }
428 } else {
429 while (n--) {
430 d = readl(regs + SPI_RXDATA);
431 *((u16*)rx) = d;
432 rx += 2;
433 }
434 }
435
436 /* Update rx pointer */
437 drv_data->rx = rx;
438 }
439
440 return (rx >= rx_end);
441}
442
443static void *next_transfer(struct driver_data *drv_data)
444{
445 struct spi_message *msg = drv_data->cur_msg;
446 struct spi_transfer *trans = drv_data->cur_transfer;
447
448 /* Move to next transfer */
449 if (trans->transfer_list.next != &msg->transfers) {
450 drv_data->cur_transfer =
451 list_entry(trans->transfer_list.next,
452 struct spi_transfer,
453 transfer_list);
454 return RUNNING_STATE;
455 }
456
457 return DONE_STATE;
458}
459
460static int map_dma_buffers(struct driver_data *drv_data)
461{
462 struct spi_message *msg;
463 struct device *dev;
464 void *buf;
465
466 drv_data->rx_dma_needs_unmap = 0;
467 drv_data->tx_dma_needs_unmap = 0;
468
469 if (!drv_data->master_info->enable_dma ||
470 !drv_data->cur_chip->enable_dma)
471 return -1;
472
473 msg = drv_data->cur_msg;
474 dev = &msg->spi->dev;
475 if (msg->is_dma_mapped) {
476 if (drv_data->tx_dma)
477 /* The caller provided at least dma and cpu virtual
478 address for write; pump_transfers() will consider the
479 transfer as write only if cpu rx virtual address is
480 NULL */
481 return 0;
482
483 if (drv_data->rx_dma) {
484 /* The caller provided dma and cpu virtual address to
485 performe read only transfer -->
486 use drv_data->dummy_dma_buf for dummy writes to
487 achive reads */
488 buf = &drv_data->dummy_dma_buf;
489 drv_data->tx_map_len = sizeof(drv_data->dummy_dma_buf);
490 drv_data->tx_dma = dma_map_single(dev,
491 buf,
492 drv_data->tx_map_len,
493 DMA_TO_DEVICE);
494 if (dma_mapping_error(dev, drv_data->tx_dma))
495 return -1;
496
497 drv_data->tx_dma_needs_unmap = 1;
498
499 /* Flags transfer as rd_only for pump_transfers() DMA
500 regs programming (should be redundant) */
501 drv_data->tx = NULL;
502
503 return 0;
504 }
505 }
506
507 if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
508 return -1;
509
510 if (drv_data->tx == NULL) {
511 /* Read only message --> use drv_data->dummy_dma_buf for dummy
512 writes to achive reads */
513 buf = &drv_data->dummy_dma_buf;
514 drv_data->tx_map_len = sizeof(drv_data->dummy_dma_buf);
515 } else {
516 buf = drv_data->tx;
517 drv_data->tx_map_len = drv_data->len;
518 }
519 drv_data->tx_dma = dma_map_single(dev,
520 buf,
521 drv_data->tx_map_len,
522 DMA_TO_DEVICE);
523 if (dma_mapping_error(dev, drv_data->tx_dma))
524 return -1;
525 drv_data->tx_dma_needs_unmap = 1;
526
527 /* NULL rx means write-only transfer and no map needed
528 * since rx DMA will not be used */
529 if (drv_data->rx) {
530 buf = drv_data->rx;
531 drv_data->rx_dma = dma_map_single(dev,
532 buf,
533 drv_data->len,
534 DMA_FROM_DEVICE);
535 if (dma_mapping_error(dev, drv_data->rx_dma)) {
536 if (drv_data->tx_dma) {
537 dma_unmap_single(dev,
538 drv_data->tx_dma,
539 drv_data->tx_map_len,
540 DMA_TO_DEVICE);
541 drv_data->tx_dma_needs_unmap = 0;
542 }
543 return -1;
544 }
545 drv_data->rx_dma_needs_unmap = 1;
546 }
547
548 return 0;
549}
550
551static void unmap_dma_buffers(struct driver_data *drv_data)
552{
553 struct spi_message *msg = drv_data->cur_msg;
554 struct device *dev = &msg->spi->dev;
555
556 if (drv_data->rx_dma_needs_unmap) {
557 dma_unmap_single(dev,
558 drv_data->rx_dma,
559 drv_data->len,
560 DMA_FROM_DEVICE);
561 drv_data->rx_dma_needs_unmap = 0;
562 }
563 if (drv_data->tx_dma_needs_unmap) {
564 dma_unmap_single(dev,
565 drv_data->tx_dma,
566 drv_data->tx_map_len,
567 DMA_TO_DEVICE);
568 drv_data->tx_dma_needs_unmap = 0;
569 }
570}
571
572/* Caller already set message->status (dma is already blocked) */
573static void giveback(struct spi_message *message, struct driver_data *drv_data)
574{
575 void __iomem *regs = drv_data->regs;
576
577 /* Bring SPI to sleep; restore_state() and pump_transfer()
578 will do new setup */
579 writel(0, regs + SPI_INT_STATUS);
580 writel(0, regs + SPI_DMA);
581
582 /* Unconditioned deselct */
583 drv_data->cs_control(SPI_CS_DEASSERT);
584
585 message->state = NULL;
586 if (message->complete)
587 message->complete(message->context);
588
589 drv_data->cur_msg = NULL;
590 drv_data->cur_transfer = NULL;
591 drv_data->cur_chip = NULL;
592 queue_work(drv_data->workqueue, &drv_data->work);
593}
594
595static void dma_err_handler(int channel, void *data, int errcode)
596{
597 struct driver_data *drv_data = data;
598 struct spi_message *msg = drv_data->cur_msg;
599
600 dev_dbg(&drv_data->pdev->dev, "dma_err_handler\n");
601
602 /* Disable both rx and tx dma channels */
603 imx_dma_disable(drv_data->rx_channel);
604 imx_dma_disable(drv_data->tx_channel);
605 unmap_dma_buffers(drv_data);
606
607 flush(drv_data);
608
609 msg->state = ERROR_STATE;
610 tasklet_schedule(&drv_data->pump_transfers);
611}
612
613static void dma_tx_handler(int channel, void *data)
614{
615 struct driver_data *drv_data = data;
616
617 dev_dbg(&drv_data->pdev->dev, "dma_tx_handler\n");
618
619 imx_dma_disable(channel);
620
621 /* Now waits for TX FIFO empty */
622 writel(SPI_INTEN_TE, drv_data->regs + SPI_INT_STATUS);
623}
624
625static irqreturn_t dma_transfer(struct driver_data *drv_data)
626{
627 u32 status;
628 struct spi_message *msg = drv_data->cur_msg;
629 void __iomem *regs = drv_data->regs;
630
631 status = readl(regs + SPI_INT_STATUS);
632
633 if ((status & (SPI_INTEN_RO | SPI_STATUS_RO))
634 == (SPI_INTEN_RO | SPI_STATUS_RO)) {
635 writel(status & ~SPI_INTEN, regs + SPI_INT_STATUS);
636
637 imx_dma_disable(drv_data->tx_channel);
638 imx_dma_disable(drv_data->rx_channel);
639 unmap_dma_buffers(drv_data);
640
641 flush(drv_data);
642
643 dev_warn(&drv_data->pdev->dev,
644 "dma_transfer - fifo overun\n");
645
646 msg->state = ERROR_STATE;
647 tasklet_schedule(&drv_data->pump_transfers);
648
649 return IRQ_HANDLED;
650 }
651
652 if (status & SPI_STATUS_TE) {
653 writel(status & ~SPI_INTEN_TE, regs + SPI_INT_STATUS);
654
655 if (drv_data->rx) {
656 /* Wait end of transfer before read trailing data */
657 while (readl(regs + SPI_CONTROL) & SPI_CONTROL_XCH)
658 cpu_relax();
659
660 imx_dma_disable(drv_data->rx_channel);
661 unmap_dma_buffers(drv_data);
662
663 /* Release chip select if requested, transfer delays are
664 handled in pump_transfers() */
665 if (drv_data->cs_change)
666 drv_data->cs_control(SPI_CS_DEASSERT);
667
668 /* Calculate number of trailing data and read them */
669 dev_dbg(&drv_data->pdev->dev,
670 "dma_transfer - test = 0x%08X\n",
671 readl(regs + SPI_TEST));
672 drv_data->rx = drv_data->rx_end -
673 ((readl(regs + SPI_TEST) &
674 SPI_TEST_RXCNT) >>
675 SPI_TEST_RXCNT_LSB)*drv_data->n_bytes;
676 read(drv_data);
677 } else {
678 /* Write only transfer */
679 unmap_dma_buffers(drv_data);
680
681 flush(drv_data);
682 }
683
684 /* End of transfer, update total byte transfered */
685 msg->actual_length += drv_data->len;
686
687 /* Move to next transfer */
688 msg->state = next_transfer(drv_data);
689
690 /* Schedule transfer tasklet */
691 tasklet_schedule(&drv_data->pump_transfers);
692
693 return IRQ_HANDLED;
694 }
695
696 /* Opps problem detected */
697 return IRQ_NONE;
698}
699
700static irqreturn_t interrupt_wronly_transfer(struct driver_data *drv_data)
701{
702 struct spi_message *msg = drv_data->cur_msg;
703 void __iomem *regs = drv_data->regs;
704 u32 status;
705 irqreturn_t handled = IRQ_NONE;
706
707 status = readl(regs + SPI_INT_STATUS);
708
709 if (status & SPI_INTEN_TE) {
710 /* TXFIFO Empty Interrupt on the last transfered word */
711 writel(status & ~SPI_INTEN, regs + SPI_INT_STATUS);
712 dev_dbg(&drv_data->pdev->dev,
713 "interrupt_wronly_transfer - end of tx\n");
714
715 flush(drv_data);
716
717 /* Update total byte transfered */
718 msg->actual_length += drv_data->len;
719
720 /* Move to next transfer */
721 msg->state = next_transfer(drv_data);
722
723 /* Schedule transfer tasklet */
724 tasklet_schedule(&drv_data->pump_transfers);
725
726 return IRQ_HANDLED;
727 } else {
728 while (status & SPI_STATUS_TH) {
729 dev_dbg(&drv_data->pdev->dev,
730 "interrupt_wronly_transfer - status = 0x%08X\n",
731 status);
732
733 /* Pump data */
734 if (write(drv_data)) {
735 /* End of TXFIFO writes,
736 now wait until TXFIFO is empty */
737 writel(SPI_INTEN_TE, regs + SPI_INT_STATUS);
738 return IRQ_HANDLED;
739 }
740
741 status = readl(regs + SPI_INT_STATUS);
742
743 /* We did something */
744 handled = IRQ_HANDLED;
745 }
746 }
747
748 return handled;
749}
750
751static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
752{
753 struct spi_message *msg = drv_data->cur_msg;
754 void __iomem *regs = drv_data->regs;
755 u32 status, control;
756 irqreturn_t handled = IRQ_NONE;
757 unsigned long limit;
758
759 status = readl(regs + SPI_INT_STATUS);
760
761 if (status & SPI_INTEN_TE) {
762 /* TXFIFO Empty Interrupt on the last transfered word */
763 writel(status & ~SPI_INTEN, regs + SPI_INT_STATUS);
764 dev_dbg(&drv_data->pdev->dev,
765 "interrupt_transfer - end of tx\n");
766
767 if (msg->state == ERROR_STATE) {
768 /* RXFIFO overrun was detected and message aborted */
769 flush(drv_data);
770 } else {
771 /* Wait for end of transaction */
772 do {
773 control = readl(regs + SPI_CONTROL);
774 } while (control & SPI_CONTROL_XCH);
775
776 /* Release chip select if requested, transfer delays are
777 handled in pump_transfers */
778 if (drv_data->cs_change)
779 drv_data->cs_control(SPI_CS_DEASSERT);
780
781 /* Read trailing bytes */
782 limit = loops_per_jiffy << 1;
783 while ((read(drv_data) == 0) && --limit)
784 cpu_relax();
785
786 if (limit == 0)
787 dev_err(&drv_data->pdev->dev,
788 "interrupt_transfer - "
789 "trailing byte read failed\n");
790 else
791 dev_dbg(&drv_data->pdev->dev,
792 "interrupt_transfer - end of rx\n");
793
794 /* Update total byte transfered */
795 msg->actual_length += drv_data->len;
796
797 /* Move to next transfer */
798 msg->state = next_transfer(drv_data);
799 }
800
801 /* Schedule transfer tasklet */
802 tasklet_schedule(&drv_data->pump_transfers);
803
804 return IRQ_HANDLED;
805 } else {
806 while (status & (SPI_STATUS_TH | SPI_STATUS_RO)) {
807 dev_dbg(&drv_data->pdev->dev,
808 "interrupt_transfer - status = 0x%08X\n",
809 status);
810
811 if (status & SPI_STATUS_RO) {
812 /* RXFIFO overrun, abort message end wait
813 until TXFIFO is empty */
814 writel(SPI_INTEN_TE, regs + SPI_INT_STATUS);
815
816 dev_warn(&drv_data->pdev->dev,
817 "interrupt_transfer - fifo overun\n"
818 " data not yet written = %d\n"
819 " data not yet read = %d\n",
820 data_to_write(drv_data),
821 data_to_read(drv_data));
822
823 msg->state = ERROR_STATE;
824
825 return IRQ_HANDLED;
826 }
827
828 /* Pump data */
829 read(drv_data);
830 if (write(drv_data)) {
831 /* End of TXFIFO writes,
832 now wait until TXFIFO is empty */
833 writel(SPI_INTEN_TE, regs + SPI_INT_STATUS);
834 return IRQ_HANDLED;
835 }
836
837 status = readl(regs + SPI_INT_STATUS);
838
839 /* We did something */
840 handled = IRQ_HANDLED;
841 }
842 }
843
844 return handled;
845}
846
847static irqreturn_t spi_int(int irq, void *dev_id)
848{
849 struct driver_data *drv_data = (struct driver_data *)dev_id;
850
851 if (!drv_data->cur_msg) {
852 dev_err(&drv_data->pdev->dev,
853 "spi_int - bad message state\n");
854 /* Never fail */
855 return IRQ_HANDLED;
856 }
857
858 return drv_data->transfer_handler(drv_data);
859}
860
861static inline u32 spi_speed_hz(struct driver_data *drv_data, u32 data_rate)
862{
863 return clk_get_rate(drv_data->clk) / (4 << ((data_rate) >> 13));
864}
865
866static u32 spi_data_rate(struct driver_data *drv_data, u32 speed_hz)
867{
868 u32 div;
869 u32 quantized_hz = clk_get_rate(drv_data->clk) >> 2;
870
871 for (div = SPI_PERCLK2_DIV_MIN;
872 div <= SPI_PERCLK2_DIV_MAX;
873 div++, quantized_hz >>= 1) {
874 if (quantized_hz <= speed_hz)
875 /* Max available speed LEQ required speed */
876 return div << 13;
877 }
878 return SPI_CONTROL_DATARATE_BAD;
879}
880
881static void pump_transfers(unsigned long data)
882{
883 struct driver_data *drv_data = (struct driver_data *)data;
884 struct spi_message *message;
885 struct spi_transfer *transfer, *previous;
886 struct chip_data *chip;
887 void __iomem *regs;
888 u32 tmp, control;
889
890 dev_dbg(&drv_data->pdev->dev, "pump_transfer\n");
891
892 message = drv_data->cur_msg;
893
894 /* Handle for abort */
895 if (message->state == ERROR_STATE) {
896 message->status = -EIO;
897 giveback(message, drv_data);
898 return;
899 }
900
901 /* Handle end of message */
902 if (message->state == DONE_STATE) {
903 message->status = 0;
904 giveback(message, drv_data);
905 return;
906 }
907
908 chip = drv_data->cur_chip;
909
910 /* Delay if requested at end of transfer*/
911 transfer = drv_data->cur_transfer;
912 if (message->state == RUNNING_STATE) {
913 previous = list_entry(transfer->transfer_list.prev,
914 struct spi_transfer,
915 transfer_list);
916 if (previous->delay_usecs)
917 udelay(previous->delay_usecs);
918 } else {
919 /* START_STATE */
920 message->state = RUNNING_STATE;
921 drv_data->cs_control = chip->cs_control;
922 }
923
924 transfer = drv_data->cur_transfer;
925 drv_data->tx = (void *)transfer->tx_buf;
926 drv_data->tx_end = drv_data->tx + transfer->len;
927 drv_data->rx = transfer->rx_buf;
928 drv_data->rx_end = drv_data->rx + transfer->len;
929 drv_data->rx_dma = transfer->rx_dma;
930 drv_data->tx_dma = transfer->tx_dma;
931 drv_data->len = transfer->len;
932 drv_data->cs_change = transfer->cs_change;
933 drv_data->rd_only = (drv_data->tx == NULL);
934
935 regs = drv_data->regs;
936 control = readl(regs + SPI_CONTROL);
937
938 /* Bits per word setup */
939 tmp = transfer->bits_per_word;
940 if (tmp == 0) {
941 /* Use device setup */
942 tmp = chip->bits_per_word;
943 drv_data->n_bytes = chip->n_bytes;
944 } else
945 /* Use per-transfer setup */
946 drv_data->n_bytes = (tmp <= 8) ? 1 : 2;
947 u32_EDIT(control, SPI_CONTROL_BITCOUNT_MASK, tmp - 1);
948
949 /* Speed setup (surely valid because already checked) */
950 tmp = transfer->speed_hz;
951 if (tmp == 0)
952 tmp = chip->max_speed_hz;
953 tmp = spi_data_rate(drv_data, tmp);
954 u32_EDIT(control, SPI_CONTROL_DATARATE, tmp);
955
956 writel(control, regs + SPI_CONTROL);
957
958 /* Assert device chip-select */
959 drv_data->cs_control(SPI_CS_ASSERT);
960
961 /* DMA cannot read/write SPI FIFOs other than 16 bits at a time; hence
962 if bits_per_word is less or equal 8 PIO transfers are performed.
963 Moreover DMA is convinient for transfer length bigger than FIFOs
964 byte size. */
965 if ((drv_data->n_bytes == 2) &&
966 (drv_data->len > SPI_FIFO_DEPTH*SPI_FIFO_BYTE_WIDTH) &&
967 (map_dma_buffers(drv_data) == 0)) {
968 dev_dbg(&drv_data->pdev->dev,
969 "pump dma transfer\n"
970 " tx = %p\n"
971 " tx_dma = %08X\n"
972 " rx = %p\n"
973 " rx_dma = %08X\n"
974 " len = %d\n",
975 drv_data->tx,
976 (unsigned int)drv_data->tx_dma,
977 drv_data->rx,
978 (unsigned int)drv_data->rx_dma,
979 drv_data->len);
980
981 /* Ensure we have the correct interrupt handler */
982 drv_data->transfer_handler = dma_transfer;
983
984 /* Trigger transfer */
985 writel(readl(regs + SPI_CONTROL) | SPI_CONTROL_XCH,
986 regs + SPI_CONTROL);
987
988 /* Setup tx DMA */
989 if (drv_data->tx)
990 /* Linear source address */
991 CCR(drv_data->tx_channel) =
992 CCR_DMOD_FIFO |
993 CCR_SMOD_LINEAR |
994 CCR_SSIZ_32 | CCR_DSIZ_16 |
995 CCR_REN;
996 else
997 /* Read only transfer -> fixed source address for
998 dummy write to achive read */
999 CCR(drv_data->tx_channel) =
1000 CCR_DMOD_FIFO |
1001 CCR_SMOD_FIFO |
1002 CCR_SSIZ_32 | CCR_DSIZ_16 |
1003 CCR_REN;
1004
1005 imx_dma_setup_single(
1006 drv_data->tx_channel,
1007 drv_data->tx_dma,
1008 drv_data->len,
1009 drv_data->rd_data_phys + 4,
1010 DMA_MODE_WRITE);
1011
1012 if (drv_data->rx) {
1013 /* Setup rx DMA for linear destination address */
1014 CCR(drv_data->rx_channel) =
1015 CCR_DMOD_LINEAR |
1016 CCR_SMOD_FIFO |
1017 CCR_DSIZ_32 | CCR_SSIZ_16 |
1018 CCR_REN;
1019 imx_dma_setup_single(
1020 drv_data->rx_channel,
1021 drv_data->rx_dma,
1022 drv_data->len,
1023 drv_data->rd_data_phys,
1024 DMA_MODE_READ);
1025 imx_dma_enable(drv_data->rx_channel);
1026
1027 /* Enable SPI interrupt */
1028 writel(SPI_INTEN_RO, regs + SPI_INT_STATUS);
1029
1030 /* Set SPI to request DMA service on both
1031 Rx and Tx half fifo watermark */
1032 writel(SPI_DMA_RHDEN | SPI_DMA_THDEN, regs + SPI_DMA);
1033 } else
1034 /* Write only access -> set SPI to request DMA
1035 service on Tx half fifo watermark */
1036 writel(SPI_DMA_THDEN, regs + SPI_DMA);
1037
1038 imx_dma_enable(drv_data->tx_channel);
1039 } else {
1040 dev_dbg(&drv_data->pdev->dev,
1041 "pump pio transfer\n"
1042 " tx = %p\n"
1043 " rx = %p\n"
1044 " len = %d\n",
1045 drv_data->tx,
1046 drv_data->rx,
1047 drv_data->len);
1048
1049 /* Ensure we have the correct interrupt handler */
1050 if (drv_data->rx)
1051 drv_data->transfer_handler = interrupt_transfer;
1052 else
1053 drv_data->transfer_handler = interrupt_wronly_transfer;
1054
1055 /* Enable SPI interrupt */
1056 if (drv_data->rx)
1057 writel(SPI_INTEN_TH | SPI_INTEN_RO,
1058 regs + SPI_INT_STATUS);
1059 else
1060 writel(SPI_INTEN_TH, regs + SPI_INT_STATUS);
1061 }
1062}
1063
1064static void pump_messages(struct work_struct *work)
1065{
1066 struct driver_data *drv_data =
1067 container_of(work, struct driver_data, work);
1068 unsigned long flags;
1069
1070 /* Lock queue and check for queue work */
1071 spin_lock_irqsave(&drv_data->lock, flags);
1072 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1073 drv_data->busy = 0;
1074 spin_unlock_irqrestore(&drv_data->lock, flags);
1075 return;
1076 }
1077
1078 /* Make sure we are not already running a message */
1079 if (drv_data->cur_msg) {
1080 spin_unlock_irqrestore(&drv_data->lock, flags);
1081 return;
1082 }
1083
1084 /* Extract head of queue */
1085 drv_data->cur_msg = list_entry(drv_data->queue.next,
1086 struct spi_message, queue);
1087 list_del_init(&drv_data->cur_msg->queue);
1088 drv_data->busy = 1;
1089 spin_unlock_irqrestore(&drv_data->lock, flags);
1090
1091 /* Initial message state */
1092 drv_data->cur_msg->state = START_STATE;
1093 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1094 struct spi_transfer,
1095 transfer_list);
1096
1097 /* Setup the SPI using the per chip configuration */
1098 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1099 restore_state(drv_data);
1100
1101 /* Mark as busy and launch transfers */
1102 tasklet_schedule(&drv_data->pump_transfers);
1103}
1104
1105static int transfer(struct spi_device *spi, struct spi_message *msg)
1106{
1107 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1108 u32 min_speed_hz, max_speed_hz, tmp;
1109 struct spi_transfer *trans;
1110 unsigned long flags;
1111
1112 msg->actual_length = 0;
1113
1114 /* Per transfer setup check */
1115 min_speed_hz = spi_speed_hz(drv_data, SPI_CONTROL_DATARATE_MIN);
1116 max_speed_hz = spi->max_speed_hz;
1117 list_for_each_entry(trans, &msg->transfers, transfer_list) {
1118 tmp = trans->bits_per_word;
1119 if (tmp > 16) {
1120 dev_err(&drv_data->pdev->dev,
1121 "message rejected : "
1122 "invalid transfer bits_per_word (%d bits)\n",
1123 tmp);
1124 goto msg_rejected;
1125 }
1126 tmp = trans->speed_hz;
1127 if (tmp) {
1128 if (tmp < min_speed_hz) {
1129 dev_err(&drv_data->pdev->dev,
1130 "message rejected : "
1131 "device min speed (%d Hz) exceeds "
1132 "required transfer speed (%d Hz)\n",
1133 min_speed_hz,
1134 tmp);
1135 goto msg_rejected;
1136 } else if (tmp > max_speed_hz) {
1137 dev_err(&drv_data->pdev->dev,
1138 "message rejected : "
1139 "transfer speed (%d Hz) exceeds "
1140 "device max speed (%d Hz)\n",
1141 tmp,
1142 max_speed_hz);
1143 goto msg_rejected;
1144 }
1145 }
1146 }
1147
1148 /* Message accepted */
1149 msg->status = -EINPROGRESS;
1150 msg->state = START_STATE;
1151
1152 spin_lock_irqsave(&drv_data->lock, flags);
1153 if (drv_data->run == QUEUE_STOPPED) {
1154 spin_unlock_irqrestore(&drv_data->lock, flags);
1155 return -ESHUTDOWN;
1156 }
1157
1158 list_add_tail(&msg->queue, &drv_data->queue);
1159 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1160 queue_work(drv_data->workqueue, &drv_data->work);
1161
1162 spin_unlock_irqrestore(&drv_data->lock, flags);
1163 return 0;
1164
1165msg_rejected:
1166 /* Message rejected and not queued */
1167 msg->status = -EINVAL;
1168 msg->state = ERROR_STATE;
1169 if (msg->complete)
1170 msg->complete(msg->context);
1171 return -EINVAL;
1172}
1173
1174/* On first setup bad values must free chip_data memory since will cause
1175 spi_new_device to fail. Bad value setup from protocol driver are simply not
1176 applied and notified to the calling driver. */
1177static int setup(struct spi_device *spi)
1178{
1179 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1180 struct spi_imx_chip *chip_info;
1181 struct chip_data *chip;
1182 int first_setup = 0;
1183 u32 tmp;
1184 int status = 0;
1185
1186 /* Get controller data */
1187 chip_info = spi->controller_data;
1188
1189 /* Get controller_state */
1190 chip = spi_get_ctldata(spi);
1191 if (chip == NULL) {
1192 first_setup = 1;
1193
1194 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1195 if (!chip) {
1196 dev_err(&spi->dev,
1197 "setup - cannot allocate controller state\n");
1198 return -ENOMEM;
1199 }
1200 chip->control = SPI_DEFAULT_CONTROL;
1201
1202 if (chip_info == NULL) {
1203 /* spi_board_info.controller_data not is supplied */
1204 chip_info = kzalloc(sizeof(struct spi_imx_chip),
1205 GFP_KERNEL);
1206 if (!chip_info) {
1207 dev_err(&spi->dev,
1208 "setup - "
1209 "cannot allocate controller data\n");
1210 status = -ENOMEM;
1211 goto err_first_setup;
1212 }
1213 /* Set controller data default value */
1214 chip_info->enable_loopback =
1215 SPI_DEFAULT_ENABLE_LOOPBACK;
1216 chip_info->enable_dma = SPI_DEFAULT_ENABLE_DMA;
1217 chip_info->ins_ss_pulse = 1;
1218 chip_info->bclk_wait = SPI_DEFAULT_PERIOD_WAIT;
1219 chip_info->cs_control = null_cs_control;
1220 }
1221 }
1222
1223 /* Now set controller state based on controller data */
1224
1225 if (first_setup) {
1226 /* SPI loopback */
1227 if (chip_info->enable_loopback)
1228 chip->test = SPI_TEST_LBC;
1229 else
1230 chip->test = 0;
1231
1232 /* SPI dma driven */
1233 chip->enable_dma = chip_info->enable_dma;
1234
1235 /* SPI /SS pulse between spi burst */
1236 if (chip_info->ins_ss_pulse)
1237 u32_EDIT(chip->control,
1238 SPI_CONTROL_SSCTL, SPI_CONTROL_SSCTL_1);
1239 else
1240 u32_EDIT(chip->control,
1241 SPI_CONTROL_SSCTL, SPI_CONTROL_SSCTL_0);
1242
1243 /* SPI bclk waits between each bits_per_word spi burst */
1244 if (chip_info->bclk_wait > SPI_PERIOD_MAX_WAIT) {
1245 dev_err(&spi->dev,
1246 "setup - "
1247 "bclk_wait exceeds max allowed (%d)\n",
1248 SPI_PERIOD_MAX_WAIT);
1249 goto err_first_setup;
1250 }
1251 chip->period = SPI_PERIOD_CSRC_BCLK |
1252 (chip_info->bclk_wait & SPI_PERIOD_WAIT);
1253 }
1254
1255 /* SPI mode */
1256 tmp = spi->mode;
1257 if (tmp & SPI_CS_HIGH) {
1258 u32_EDIT(chip->control,
1259 SPI_CONTROL_SSPOL, SPI_CONTROL_SSPOL_ACT_HIGH);
1260 }
1261 switch (tmp & SPI_MODE_3) {
1262 case SPI_MODE_0:
1263 tmp = 0;
1264 break;
1265 case SPI_MODE_1:
1266 tmp = SPI_CONTROL_PHA_1;
1267 break;
1268 case SPI_MODE_2:
1269 tmp = SPI_CONTROL_POL_ACT_LOW;
1270 break;
1271 default:
1272 /* SPI_MODE_3 */
1273 tmp = SPI_CONTROL_PHA_1 | SPI_CONTROL_POL_ACT_LOW;
1274 break;
1275 }
1276 u32_EDIT(chip->control, SPI_CONTROL_POL | SPI_CONTROL_PHA, tmp);
1277
1278 /* SPI word width */
1279 tmp = spi->bits_per_word;
1280 if (tmp > 16) {
1281 status = -EINVAL;
1282 dev_err(&spi->dev,
1283 "setup - "
1284 "invalid bits_per_word (%d)\n",
1285 tmp);
1286 if (first_setup)
1287 goto err_first_setup;
1288 else {
1289 /* Undo setup using chip as backup copy */
1290 tmp = chip->bits_per_word;
1291 spi->bits_per_word = tmp;
1292 }
1293 }
1294 chip->bits_per_word = tmp;
1295 u32_EDIT(chip->control, SPI_CONTROL_BITCOUNT_MASK, tmp - 1);
1296 chip->n_bytes = (tmp <= 8) ? 1 : 2;
1297
1298 /* SPI datarate */
1299 tmp = spi_data_rate(drv_data, spi->max_speed_hz);
1300 if (tmp == SPI_CONTROL_DATARATE_BAD) {
1301 status = -EINVAL;
1302 dev_err(&spi->dev,
1303 "setup - "
1304 "HW min speed (%d Hz) exceeds required "
1305 "max speed (%d Hz)\n",
1306 spi_speed_hz(drv_data, SPI_CONTROL_DATARATE_MIN),
1307 spi->max_speed_hz);
1308 if (first_setup)
1309 goto err_first_setup;
1310 else
1311 /* Undo setup using chip as backup copy */
1312 spi->max_speed_hz = chip->max_speed_hz;
1313 } else {
1314 u32_EDIT(chip->control, SPI_CONTROL_DATARATE, tmp);
1315 /* Actual rounded max_speed_hz */
1316 tmp = spi_speed_hz(drv_data, tmp);
1317 spi->max_speed_hz = tmp;
1318 chip->max_speed_hz = tmp;
1319 }
1320
1321 /* SPI chip-select management */
1322 if (chip_info->cs_control)
1323 chip->cs_control = chip_info->cs_control;
1324 else
1325 chip->cs_control = null_cs_control;
1326
1327 /* Save controller_state */
1328 spi_set_ctldata(spi, chip);
1329
1330 /* Summary */
1331 dev_dbg(&spi->dev,
1332 "setup succeded\n"
1333 " loopback enable = %s\n"
1334 " dma enable = %s\n"
1335 " insert /ss pulse = %s\n"
1336 " period wait = %d\n"
1337 " mode = %d\n"
1338 " bits per word = %d\n"
1339 " min speed = %d Hz\n"
1340 " rounded max speed = %d Hz\n",
1341 chip->test & SPI_TEST_LBC ? "Yes" : "No",
1342 chip->enable_dma ? "Yes" : "No",
1343 chip->control & SPI_CONTROL_SSCTL ? "Yes" : "No",
1344 chip->period & SPI_PERIOD_WAIT,
1345 spi->mode,
1346 spi->bits_per_word,
1347 spi_speed_hz(drv_data, SPI_CONTROL_DATARATE_MIN),
1348 spi->max_speed_hz);
1349 return status;
1350
1351err_first_setup:
1352 kfree(chip);
1353 return status;
1354}
1355
1356static void cleanup(struct spi_device *spi)
1357{
1358 kfree(spi_get_ctldata(spi));
1359}
1360
1361static int __init init_queue(struct driver_data *drv_data)
1362{
1363 INIT_LIST_HEAD(&drv_data->queue);
1364 spin_lock_init(&drv_data->lock);
1365
1366 drv_data->run = QUEUE_STOPPED;
1367 drv_data->busy = 0;
1368
1369 tasklet_init(&drv_data->pump_transfers,
1370 pump_transfers, (unsigned long)drv_data);
1371
1372 INIT_WORK(&drv_data->work, pump_messages);
1373 drv_data->workqueue = create_singlethread_workqueue(
1374 dev_name(drv_data->master->dev.parent));
1375 if (drv_data->workqueue == NULL)
1376 return -EBUSY;
1377
1378 return 0;
1379}
1380
1381static int start_queue(struct driver_data *drv_data)
1382{
1383 unsigned long flags;
1384
1385 spin_lock_irqsave(&drv_data->lock, flags);
1386
1387 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1388 spin_unlock_irqrestore(&drv_data->lock, flags);
1389 return -EBUSY;
1390 }
1391
1392 drv_data->run = QUEUE_RUNNING;
1393 drv_data->cur_msg = NULL;
1394 drv_data->cur_transfer = NULL;
1395 drv_data->cur_chip = NULL;
1396 spin_unlock_irqrestore(&drv_data->lock, flags);
1397
1398 queue_work(drv_data->workqueue, &drv_data->work);
1399
1400 return 0;
1401}
1402
1403static int stop_queue(struct driver_data *drv_data)
1404{
1405 unsigned long flags;
1406 unsigned limit = 500;
1407 int status = 0;
1408
1409 spin_lock_irqsave(&drv_data->lock, flags);
1410
1411 /* This is a bit lame, but is optimized for the common execution path.
1412 * A wait_queue on the drv_data->busy could be used, but then the common
1413 * execution path (pump_messages) would be required to call wake_up or
1414 * friends on every SPI message. Do this instead */
1415 drv_data->run = QUEUE_STOPPED;
1416 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1417 spin_unlock_irqrestore(&drv_data->lock, flags);
1418 msleep(10);
1419 spin_lock_irqsave(&drv_data->lock, flags);
1420 }
1421
1422 if (!list_empty(&drv_data->queue) || drv_data->busy)
1423 status = -EBUSY;
1424
1425 spin_unlock_irqrestore(&drv_data->lock, flags);
1426
1427 return status;
1428}
1429
1430static int destroy_queue(struct driver_data *drv_data)
1431{
1432 int status;
1433
1434 status = stop_queue(drv_data);
1435 if (status != 0)
1436 return status;
1437
1438 if (drv_data->workqueue)
1439 destroy_workqueue(drv_data->workqueue);
1440
1441 return 0;
1442}
1443
1444static int __init spi_imx_probe(struct platform_device *pdev)
1445{
1446 struct device *dev = &pdev->dev;
1447 struct spi_imx_master *platform_info;
1448 struct spi_master *master;
1449 struct driver_data *drv_data;
1450 struct resource *res;
1451 int irq, status = 0;
1452
1453 platform_info = dev->platform_data;
1454 if (platform_info == NULL) {
1455 dev_err(&pdev->dev, "probe - no platform data supplied\n");
1456 status = -ENODEV;
1457 goto err_no_pdata;
1458 }
1459
1460 /* Allocate master with space for drv_data */
1461 master = spi_alloc_master(dev, sizeof(struct driver_data));
1462 if (!master) {
1463 dev_err(&pdev->dev, "probe - cannot alloc spi_master\n");
1464 status = -ENOMEM;
1465 goto err_no_mem;
1466 }
1467 drv_data = spi_master_get_devdata(master);
1468 drv_data->master = master;
1469 drv_data->master_info = platform_info;
1470 drv_data->pdev = pdev;
1471
1472 /* the spi->mode bits understood by this driver: */
1473 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1474
1475 master->bus_num = pdev->id;
1476 master->num_chipselect = platform_info->num_chipselect;
1477 master->dma_alignment = DMA_ALIGNMENT;
1478 master->cleanup = cleanup;
1479 master->setup = setup;
1480 master->transfer = transfer;
1481
1482 drv_data->dummy_dma_buf = SPI_DUMMY_u32;
1483
1484 drv_data->clk = clk_get(&pdev->dev, "perclk2");
1485 if (IS_ERR(drv_data->clk)) {
1486 dev_err(&pdev->dev, "probe - cannot get clock\n");
1487 status = PTR_ERR(drv_data->clk);
1488 goto err_no_clk;
1489 }
1490 clk_enable(drv_data->clk);
1491
1492 /* Find and map resources */
1493 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1494 if (!res) {
1495 dev_err(&pdev->dev, "probe - MEM resources not defined\n");
1496 status = -ENODEV;
1497 goto err_no_iores;
1498 }
1499 drv_data->ioarea = request_mem_region(res->start,
1500 res->end - res->start + 1,
1501 pdev->name);
1502 if (drv_data->ioarea == NULL) {
1503 dev_err(&pdev->dev, "probe - cannot reserve region\n");
1504 status = -ENXIO;
1505 goto err_no_iores;
1506 }
1507 drv_data->regs = ioremap(res->start, res->end - res->start + 1);
1508 if (drv_data->regs == NULL) {
1509 dev_err(&pdev->dev, "probe - cannot map IO\n");
1510 status = -ENXIO;
1511 goto err_no_iomap;
1512 }
1513 drv_data->rd_data_phys = (dma_addr_t)res->start;
1514
1515 /* Attach to IRQ */
1516 irq = platform_get_irq(pdev, 0);
1517 if (irq < 0) {
1518 dev_err(&pdev->dev, "probe - IRQ resource not defined\n");
1519 status = -ENODEV;
1520 goto err_no_irqres;
1521 }
1522 status = request_irq(irq, spi_int, IRQF_DISABLED,
1523 dev_name(dev), drv_data);
1524 if (status < 0) {
1525 dev_err(&pdev->dev, "probe - cannot get IRQ (%d)\n", status);
1526 goto err_no_irqres;
1527 }
1528
1529 /* Setup DMA if requested */
1530 drv_data->tx_channel = -1;
1531 drv_data->rx_channel = -1;
1532 if (platform_info->enable_dma) {
1533 /* Get rx DMA channel */
1534 drv_data->rx_channel = imx_dma_request_by_prio("spi_imx_rx",
1535 DMA_PRIO_HIGH);
1536 if (drv_data->rx_channel < 0) {
1537 dev_err(dev,
1538 "probe - problem (%d) requesting rx channel\n",
1539 drv_data->rx_channel);
1540 goto err_no_rxdma;
1541 } else
1542 imx_dma_setup_handlers(drv_data->rx_channel, NULL,
1543 dma_err_handler, drv_data);
1544
1545 /* Get tx DMA channel */
1546 drv_data->tx_channel = imx_dma_request_by_prio("spi_imx_tx",
1547 DMA_PRIO_MEDIUM);
1548 if (drv_data->tx_channel < 0) {
1549 dev_err(dev,
1550 "probe - problem (%d) requesting tx channel\n",
1551 drv_data->tx_channel);
1552 imx_dma_free(drv_data->rx_channel);
1553 goto err_no_txdma;
1554 } else
1555 imx_dma_setup_handlers(drv_data->tx_channel,
1556 dma_tx_handler, dma_err_handler,
1557 drv_data);
1558
1559 /* Set request source and burst length for allocated channels */
1560 switch (drv_data->pdev->id) {
1561 case 1:
1562 /* Using SPI1 */
1563 RSSR(drv_data->rx_channel) = DMA_REQ_SPI1_R;
1564 RSSR(drv_data->tx_channel) = DMA_REQ_SPI1_T;
1565 break;
1566 case 2:
1567 /* Using SPI2 */
1568 RSSR(drv_data->rx_channel) = DMA_REQ_SPI2_R;
1569 RSSR(drv_data->tx_channel) = DMA_REQ_SPI2_T;
1570 break;
1571 default:
1572 dev_err(dev, "probe - bad SPI Id\n");
1573 imx_dma_free(drv_data->rx_channel);
1574 imx_dma_free(drv_data->tx_channel);
1575 status = -ENODEV;
1576 goto err_no_devid;
1577 }
1578 BLR(drv_data->rx_channel) = SPI_DMA_BLR;
1579 BLR(drv_data->tx_channel) = SPI_DMA_BLR;
1580 }
1581
1582 /* Load default SPI configuration */
1583 writel(SPI_RESET_START, drv_data->regs + SPI_RESET);
1584 writel(0, drv_data->regs + SPI_RESET);
1585 writel(SPI_DEFAULT_CONTROL, drv_data->regs + SPI_CONTROL);
1586
1587 /* Initial and start queue */
1588 status = init_queue(drv_data);
1589 if (status != 0) {
1590 dev_err(&pdev->dev, "probe - problem initializing queue\n");
1591 goto err_init_queue;
1592 }
1593 status = start_queue(drv_data);
1594 if (status != 0) {
1595 dev_err(&pdev->dev, "probe - problem starting queue\n");
1596 goto err_start_queue;
1597 }
1598
1599 /* Register with the SPI framework */
1600 platform_set_drvdata(pdev, drv_data);
1601 status = spi_register_master(master);
1602 if (status != 0) {
1603 dev_err(&pdev->dev, "probe - problem registering spi master\n");
1604 goto err_spi_register;
1605 }
1606
1607 dev_dbg(dev, "probe succeded\n");
1608 return 0;
1609
1610err_init_queue:
1611err_start_queue:
1612err_spi_register:
1613 destroy_queue(drv_data);
1614
1615err_no_rxdma:
1616err_no_txdma:
1617err_no_devid:
1618 free_irq(irq, drv_data);
1619
1620err_no_irqres:
1621 iounmap(drv_data->regs);
1622
1623err_no_iomap:
1624 release_resource(drv_data->ioarea);
1625 kfree(drv_data->ioarea);
1626
1627err_no_iores:
1628 clk_disable(drv_data->clk);
1629 clk_put(drv_data->clk);
1630
1631err_no_clk:
1632 spi_master_put(master);
1633
1634err_no_pdata:
1635err_no_mem:
1636 return status;
1637}
1638
1639static int __exit spi_imx_remove(struct platform_device *pdev)
1640{
1641 struct driver_data *drv_data = platform_get_drvdata(pdev);
1642 int irq;
1643 int status = 0;
1644
1645 if (!drv_data)
1646 return 0;
1647
1648 tasklet_kill(&drv_data->pump_transfers);
1649
1650 /* Remove the queue */
1651 status = destroy_queue(drv_data);
1652 if (status != 0) {
1653 dev_err(&pdev->dev, "queue remove failed (%d)\n", status);
1654 return status;
1655 }
1656
1657 /* Reset SPI */
1658 writel(SPI_RESET_START, drv_data->regs + SPI_RESET);
1659 writel(0, drv_data->regs + SPI_RESET);
1660
1661 /* Release DMA */
1662 if (drv_data->master_info->enable_dma) {
1663 RSSR(drv_data->rx_channel) = 0;
1664 RSSR(drv_data->tx_channel) = 0;
1665 imx_dma_free(drv_data->tx_channel);
1666 imx_dma_free(drv_data->rx_channel);
1667 }
1668
1669 /* Release IRQ */
1670 irq = platform_get_irq(pdev, 0);
1671 if (irq >= 0)
1672 free_irq(irq, drv_data);
1673
1674 clk_disable(drv_data->clk);
1675 clk_put(drv_data->clk);
1676
1677 /* Release map resources */
1678 iounmap(drv_data->regs);
1679 release_resource(drv_data->ioarea);
1680 kfree(drv_data->ioarea);
1681
1682 /* Disconnect from the SPI framework */
1683 spi_unregister_master(drv_data->master);
1684 spi_master_put(drv_data->master);
1685
1686 /* Prevent double remove */
1687 platform_set_drvdata(pdev, NULL);
1688
1689 dev_dbg(&pdev->dev, "remove succeded\n");
1690
1691 return 0;
1692}
1693
1694static void spi_imx_shutdown(struct platform_device *pdev)
1695{
1696 struct driver_data *drv_data = platform_get_drvdata(pdev);
1697
1698 /* Reset SPI */
1699 writel(SPI_RESET_START, drv_data->regs + SPI_RESET);
1700 writel(0, drv_data->regs + SPI_RESET);
1701
1702 dev_dbg(&pdev->dev, "shutdown succeded\n");
1703}
1704
1705#ifdef CONFIG_PM
1706
1707static int spi_imx_suspend(struct platform_device *pdev, pm_message_t state)
1708{
1709 struct driver_data *drv_data = platform_get_drvdata(pdev);
1710 int status = 0;
1711
1712 status = stop_queue(drv_data);
1713 if (status != 0) {
1714 dev_warn(&pdev->dev, "suspend cannot stop queue\n");
1715 return status;
1716 }
1717
1718 dev_dbg(&pdev->dev, "suspended\n");
1719
1720 return 0;
1721}
1722
1723static int spi_imx_resume(struct platform_device *pdev)
1724{
1725 struct driver_data *drv_data = platform_get_drvdata(pdev);
1726 int status = 0;
1727
1728 /* Start the queue running */
1729 status = start_queue(drv_data);
1730 if (status != 0)
1731 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1732 else
1733 dev_dbg(&pdev->dev, "resumed\n");
1734
1735 return status;
1736}
1737#else
1738#define spi_imx_suspend NULL
1739#define spi_imx_resume NULL
1740#endif /* CONFIG_PM */
1741
1742/* work with hotplug and coldplug */
1743MODULE_ALIAS("platform:spi_imx");
1744
1745static struct platform_driver driver = {
1746 .driver = {
1747 .name = "spi_imx",
1748 .owner = THIS_MODULE,
1749 },
1750 .remove = __exit_p(spi_imx_remove),
1751 .shutdown = spi_imx_shutdown,
1752 .suspend = spi_imx_suspend,
1753 .resume = spi_imx_resume,
1754};
1755
1756static int __init spi_imx_init(void)
1757{
1758 return platform_driver_probe(&driver, spi_imx_probe);
1759}
1760module_init(spi_imx_init);
1761
1762static void __exit spi_imx_exit(void)
1763{
1764 platform_driver_unregister(&driver);
1765}
1766module_exit(spi_imx_exit);
1767
1768MODULE_AUTHOR("Andrea Paterniani, <a.paterniani@swapp-eng.it>");
1769MODULE_DESCRIPTION("iMX SPI Controller Driver");
1770MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 19:53:28 -0500