aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
Diffstat (limited to 'drivers')
-rw-r--r--drivers/char/pty.c2
-rw-r--r--drivers/gpu/drm/drm_irq.c2
-rw-r--r--drivers/gpu/drm/drm_modes.c2
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c15
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h4
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c4
-rw-r--r--drivers/gpu/drm/i915/i915_gem_debugfs.c2
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c239
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h45
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c2
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c40
-rw-r--r--drivers/gpu/drm/i915/intel_bios.h45
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c12
-rw-r--r--drivers/gpu/drm/i915/intel_display.c759
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c216
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h3
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c64
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c12
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c254
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c22
-rw-r--r--drivers/gpu/drm/radeon/r600_cp.c22
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c2
-rw-r--r--drivers/input/keyboard/matrix_keypad.c18
-rw-r--r--drivers/input/misc/wistron_btns.c16
-rw-r--r--drivers/input/serio/i8042-x86ia64io.h8
-rw-r--r--drivers/mmc/host/sdhci-of.c2
-rw-r--r--drivers/mtd/maps/Kconfig7
-rw-r--r--drivers/mtd/maps/Makefile1
-rw-r--r--drivers/mtd/maps/sbc8240.c250
-rw-r--r--drivers/mtd/mtd_blkdevs.c6
-rw-r--r--drivers/mtd/mtdblock.c16
-rw-r--r--drivers/mtd/mtdcore.c7
-rw-r--r--drivers/mtd/onenand/omap2.c3
-rw-r--r--drivers/mtd/ubi/eba.c1
-rw-r--r--drivers/mtd/ubi/scan.c13
-rw-r--r--drivers/pci/hotplug/sgi_hotplug.c7
-rw-r--r--drivers/pci/intel-iommu.c25
-rw-r--r--drivers/serial/s3c2400.c8
-rw-r--r--drivers/serial/s3c2410.c8
-rw-r--r--drivers/serial/s3c2412.c8
-rw-r--r--drivers/serial/s3c2440.c8
-rw-r--r--drivers/serial/s3c24a0.c8
-rw-r--r--drivers/serial/s3c6400.c8
-rw-r--r--drivers/serial/serial_ks8695.c2
-rw-r--r--drivers/staging/b3dfg/Kconfig1
-rw-r--r--drivers/staging/heci/Kconfig1
-rw-r--r--drivers/staging/rspiusb/rspiusb.c2
-rw-r--r--drivers/staging/rt2860/rt_linux.h13
-rw-r--r--drivers/staging/rt2870/2870_main_dev.c67
-rw-r--r--drivers/staging/rt2870/common/2870_rtmp_init.c33
-rw-r--r--drivers/staging/rt2870/common/rtusb_io.c3
-rw-r--r--drivers/staging/rt2870/rt2870.h9
-rw-r--r--drivers/staging/rtl8192su/ieee80211.h2
-rw-r--r--drivers/staging/rtl8192su/ieee80211/ieee80211.h2
-rw-r--r--drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c3
-rw-r--r--drivers/staging/rtl8192su/r8192U_core.c2
-rw-r--r--drivers/usb/class/cdc-acm.c10
-rw-r--r--drivers/usb/class/cdc-acm.h2
-rw-r--r--drivers/usb/core/devio.c10
-rw-r--r--drivers/usb/host/ehci-hcd.c3
-rw-r--r--drivers/usb/host/ehci-q.c15
-rw-r--r--drivers/usb/host/ehci-sched.c1
-rw-r--r--drivers/usb/musb/Kconfig1
-rw-r--r--drivers/usb/serial/ftdi_sio.c3
-rw-r--r--drivers/usb/serial/ftdi_sio.h14
-rw-r--r--drivers/usb/serial/pl2303.c1
-rw-r--r--drivers/usb/serial/pl2303.h4
-rw-r--r--drivers/usb/storage/unusual_devs.h7
-rw-r--r--drivers/video/console/fbcon.c6
-rw-r--r--drivers/video/console/fbcon_rotate.h2
-rw-r--r--drivers/video/mx3fb.c86
-rw-r--r--drivers/video/via/hw.c4
-rw-r--r--drivers/video/via/lcd.c15
-rw-r--r--drivers/video/via/viafbdev.c101
-rw-r--r--drivers/video/via/viafbdev.h3
-rw-r--r--drivers/w1/masters/omap_hdq.c1
-rw-r--r--drivers/watchdog/ks8695_wdt.c4
79 files changed, 1609 insertions, 1025 deletions
diff --git a/drivers/char/pty.c b/drivers/char/pty.c
index 6e6942c45f5b..d083c73d784a 100644
--- a/drivers/char/pty.c
+++ b/drivers/char/pty.c
@@ -144,6 +144,8 @@ static int pty_write(struct tty_struct *tty, const unsigned char *buf,
144 144
145static int pty_write_room(struct tty_struct *tty) 145static int pty_write_room(struct tty_struct *tty)
146{ 146{
147 if (tty->stopped)
148 return 0;
147 return pty_space(tty->link); 149 return pty_space(tty->link);
148} 150}
149 151
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index b4a3dbcebe9b..f85aaf21e783 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -566,7 +566,7 @@ int drm_wait_vblank(struct drm_device *dev, void *data,
566 566
567 ret = drm_vblank_get(dev, crtc); 567 ret = drm_vblank_get(dev, crtc);
568 if (ret) { 568 if (ret) {
569 DRM_ERROR("failed to acquire vblank counter, %d\n", ret); 569 DRM_DEBUG("failed to acquire vblank counter, %d\n", ret);
570 return ret; 570 return ret;
571 } 571 }
572 seq = drm_vblank_count(dev, crtc); 572 seq = drm_vblank_count(dev, crtc);
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 54f492a488a9..7914097b09c6 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -566,6 +566,8 @@ void drm_mode_connector_list_update(struct drm_connector *connector)
566 found_it = 1; 566 found_it = 1;
567 /* if equal delete the probed mode */ 567 /* if equal delete the probed mode */
568 mode->status = pmode->status; 568 mode->status = pmode->status;
569 /* Merge type bits together */
570 mode->type |= pmode->type;
569 list_del(&pmode->head); 571 list_del(&pmode->head);
570 drm_mode_destroy(connector->dev, pmode); 572 drm_mode_destroy(connector->dev, pmode);
571 break; 573 break;
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 8c4783180bf6..50d1f782768c 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1186,6 +1186,13 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1186 if (ret) 1186 if (ret)
1187 goto out_iomapfree; 1187 goto out_iomapfree;
1188 1188
1189 dev_priv->wq = create_workqueue("i915");
1190 if (dev_priv->wq == NULL) {
1191 DRM_ERROR("Failed to create our workqueue.\n");
1192 ret = -ENOMEM;
1193 goto out_iomapfree;
1194 }
1195
1189 /* enable GEM by default */ 1196 /* enable GEM by default */
1190 dev_priv->has_gem = 1; 1197 dev_priv->has_gem = 1;
1191 1198
@@ -1211,7 +1218,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1211 if (!I915_NEED_GFX_HWS(dev)) { 1218 if (!I915_NEED_GFX_HWS(dev)) {
1212 ret = i915_init_phys_hws(dev); 1219 ret = i915_init_phys_hws(dev);
1213 if (ret != 0) 1220 if (ret != 0)
1214 goto out_iomapfree; 1221 goto out_workqueue_free;
1215 } 1222 }
1216 1223
1217 i915_get_mem_freq(dev); 1224 i915_get_mem_freq(dev);
@@ -1245,7 +1252,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1245 ret = i915_load_modeset_init(dev, prealloc_size, agp_size); 1252 ret = i915_load_modeset_init(dev, prealloc_size, agp_size);
1246 if (ret < 0) { 1253 if (ret < 0) {
1247 DRM_ERROR("failed to init modeset\n"); 1254 DRM_ERROR("failed to init modeset\n");
1248 goto out_rmmap; 1255 goto out_workqueue_free;
1249 } 1256 }
1250 } 1257 }
1251 1258
@@ -1256,6 +1263,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1256 1263
1257 return 0; 1264 return 0;
1258 1265
1266out_workqueue_free:
1267 destroy_workqueue(dev_priv->wq);
1259out_iomapfree: 1268out_iomapfree:
1260 io_mapping_free(dev_priv->mm.gtt_mapping); 1269 io_mapping_free(dev_priv->mm.gtt_mapping);
1261out_rmmap: 1270out_rmmap:
@@ -1269,6 +1278,8 @@ int i915_driver_unload(struct drm_device *dev)
1269{ 1278{
1270 struct drm_i915_private *dev_priv = dev->dev_private; 1279 struct drm_i915_private *dev_priv = dev->dev_private;
1271 1280
1281 destroy_workqueue(dev_priv->wq);
1282
1272 io_mapping_free(dev_priv->mm.gtt_mapping); 1283 io_mapping_free(dev_priv->mm.gtt_mapping);
1273 if (dev_priv->mm.gtt_mtrr >= 0) { 1284 if (dev_priv->mm.gtt_mtrr >= 0) {
1274 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base, 1285 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d08752875885..7537f57d8a87 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -219,6 +219,7 @@ typedef struct drm_i915_private {
219 unsigned int lvds_vbt:1; 219 unsigned int lvds_vbt:1;
220 unsigned int int_crt_support:1; 220 unsigned int int_crt_support:1;
221 unsigned int lvds_use_ssc:1; 221 unsigned int lvds_use_ssc:1;
222 unsigned int edp_support:1;
222 int lvds_ssc_freq; 223 int lvds_ssc_freq;
223 224
224 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ 225 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
@@ -229,6 +230,8 @@ typedef struct drm_i915_private {
229 230
230 spinlock_t error_lock; 231 spinlock_t error_lock;
231 struct drm_i915_error_state *first_error; 232 struct drm_i915_error_state *first_error;
233 struct work_struct error_work;
234 struct workqueue_struct *wq;
232 235
233 /* Register state */ 236 /* Register state */
234 u8 saveLBB; 237 u8 saveLBB;
@@ -888,6 +891,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
888 IS_I915GM(dev))) 891 IS_I915GM(dev)))
889#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev)) 892#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
890#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev)) 893#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev))
894#define SUPPORTS_EDP(dev) (IS_IGDNG_M(dev))
891#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev)) 895#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev))
892/* dsparb controlled by hw only */ 896/* dsparb controlled by hw only */
893#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev)) 897#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5bf420378b6d..140bee142fc2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1570,7 +1570,7 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1570 } 1570 }
1571 1571
1572 if (was_empty && !dev_priv->mm.suspended) 1572 if (was_empty && !dev_priv->mm.suspended)
1573 schedule_delayed_work(&dev_priv->mm.retire_work, HZ); 1573 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1574 return seqno; 1574 return seqno;
1575} 1575}
1576 1576
@@ -1719,7 +1719,7 @@ i915_gem_retire_work_handler(struct work_struct *work)
1719 i915_gem_retire_requests(dev); 1719 i915_gem_retire_requests(dev);
1720 if (!dev_priv->mm.suspended && 1720 if (!dev_priv->mm.suspended &&
1721 !list_empty(&dev_priv->mm.request_list)) 1721 !list_empty(&dev_priv->mm.request_list))
1722 schedule_delayed_work(&dev_priv->mm.retire_work, HZ); 1722 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1723 mutex_unlock(&dev->struct_mutex); 1723 mutex_unlock(&dev->struct_mutex);
1724} 1724}
1725 1725
diff --git a/drivers/gpu/drm/i915/i915_gem_debugfs.c b/drivers/gpu/drm/i915/i915_gem_debugfs.c
index 9a44bfcb8139..cb3b97405fbf 100644
--- a/drivers/gpu/drm/i915/i915_gem_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_gem_debugfs.c
@@ -343,6 +343,8 @@ static int i915_error_state(struct seq_file *m, void *unused)
343 343
344 error = dev_priv->first_error; 344 error = dev_priv->first_error;
345 345
346 seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
347 error->time.tv_usec);
346 seq_printf(m, "EIR: 0x%08x\n", error->eir); 348 seq_printf(m, "EIR: 0x%08x\n", error->eir);
347 seq_printf(m, " PGTBL_ER: 0x%08x\n", error->pgtbl_er); 349 seq_printf(m, " PGTBL_ER: 0x%08x\n", error->pgtbl_er);
348 seq_printf(m, " INSTPM: 0x%08x\n", error->instpm); 350 seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7ba23a69a0c0..7ebc84c2881e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -190,7 +190,7 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
190 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; 190 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
191 191
192 if (!i915_pipe_enabled(dev, pipe)) { 192 if (!i915_pipe_enabled(dev, pipe)) {
193 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe); 193 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe);
194 return 0; 194 return 0;
195 } 195 }
196 196
@@ -219,7 +219,7 @@ u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
219 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; 219 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
220 220
221 if (!i915_pipe_enabled(dev, pipe)) { 221 if (!i915_pipe_enabled(dev, pipe)) {
222 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe); 222 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe);
223 return 0; 223 return 0;
224 } 224 }
225 225
@@ -290,6 +290,35 @@ irqreturn_t igdng_irq_handler(struct drm_device *dev)
290 return ret; 290 return ret;
291} 291}
292 292
293/**
294 * i915_error_work_func - do process context error handling work
295 * @work: work struct
296 *
297 * Fire an error uevent so userspace can see that a hang or error
298 * was detected.
299 */
300static void i915_error_work_func(struct work_struct *work)
301{
302 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
303 error_work);
304 struct drm_device *dev = dev_priv->dev;
305 char *event_string = "ERROR=1";
306 char *envp[] = { event_string, NULL };
307
308 DRM_DEBUG("generating error event\n");
309
310 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, envp);
311}
312
313/**
314 * i915_capture_error_state - capture an error record for later analysis
315 * @dev: drm device
316 *
317 * Should be called when an error is detected (either a hang or an error
318 * interrupt) to capture error state from the time of the error. Fills
319 * out a structure which becomes available in debugfs for user level tools
320 * to pick up.
321 */
293static void i915_capture_error_state(struct drm_device *dev) 322static void i915_capture_error_state(struct drm_device *dev)
294{ 323{
295 struct drm_i915_private *dev_priv = dev->dev_private; 324 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -325,12 +354,137 @@ static void i915_capture_error_state(struct drm_device *dev)
325 error->acthd = I915_READ(ACTHD_I965); 354 error->acthd = I915_READ(ACTHD_I965);
326 } 355 }
327 356
357 do_gettimeofday(&error->time);
358
328 dev_priv->first_error = error; 359 dev_priv->first_error = error;
329 360
330out: 361out:
331 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 362 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
332} 363}
333 364
365/**
366 * i915_handle_error - handle an error interrupt
367 * @dev: drm device
368 *
369 * Do some basic checking of regsiter state at error interrupt time and
370 * dump it to the syslog. Also call i915_capture_error_state() to make
371 * sure we get a record and make it available in debugfs. Fire a uevent
372 * so userspace knows something bad happened (should trigger collection
373 * of a ring dump etc.).
374 */
375static void i915_handle_error(struct drm_device *dev)
376{
377 struct drm_i915_private *dev_priv = dev->dev_private;
378 u32 eir = I915_READ(EIR);
379 u32 pipea_stats = I915_READ(PIPEASTAT);
380 u32 pipeb_stats = I915_READ(PIPEBSTAT);
381
382 i915_capture_error_state(dev);
383
384 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
385 eir);
386
387 if (IS_G4X(dev)) {
388 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
389 u32 ipeir = I915_READ(IPEIR_I965);
390
391 printk(KERN_ERR " IPEIR: 0x%08x\n",
392 I915_READ(IPEIR_I965));
393 printk(KERN_ERR " IPEHR: 0x%08x\n",
394 I915_READ(IPEHR_I965));
395 printk(KERN_ERR " INSTDONE: 0x%08x\n",
396 I915_READ(INSTDONE_I965));
397 printk(KERN_ERR " INSTPS: 0x%08x\n",
398 I915_READ(INSTPS));
399 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
400 I915_READ(INSTDONE1));
401 printk(KERN_ERR " ACTHD: 0x%08x\n",
402 I915_READ(ACTHD_I965));
403 I915_WRITE(IPEIR_I965, ipeir);
404 (void)I915_READ(IPEIR_I965);
405 }
406 if (eir & GM45_ERROR_PAGE_TABLE) {
407 u32 pgtbl_err = I915_READ(PGTBL_ER);
408 printk(KERN_ERR "page table error\n");
409 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
410 pgtbl_err);
411 I915_WRITE(PGTBL_ER, pgtbl_err);
412 (void)I915_READ(PGTBL_ER);
413 }
414 }
415
416 if (IS_I9XX(dev)) {
417 if (eir & I915_ERROR_PAGE_TABLE) {
418 u32 pgtbl_err = I915_READ(PGTBL_ER);
419 printk(KERN_ERR "page table error\n");
420 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
421 pgtbl_err);
422 I915_WRITE(PGTBL_ER, pgtbl_err);
423 (void)I915_READ(PGTBL_ER);
424 }
425 }
426
427 if (eir & I915_ERROR_MEMORY_REFRESH) {
428 printk(KERN_ERR "memory refresh error\n");
429 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
430 pipea_stats);
431 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
432 pipeb_stats);
433 /* pipestat has already been acked */
434 }
435 if (eir & I915_ERROR_INSTRUCTION) {
436 printk(KERN_ERR "instruction error\n");
437 printk(KERN_ERR " INSTPM: 0x%08x\n",
438 I915_READ(INSTPM));
439 if (!IS_I965G(dev)) {
440 u32 ipeir = I915_READ(IPEIR);
441
442 printk(KERN_ERR " IPEIR: 0x%08x\n",
443 I915_READ(IPEIR));
444 printk(KERN_ERR " IPEHR: 0x%08x\n",
445 I915_READ(IPEHR));
446 printk(KERN_ERR " INSTDONE: 0x%08x\n",
447 I915_READ(INSTDONE));
448 printk(KERN_ERR " ACTHD: 0x%08x\n",
449 I915_READ(ACTHD));
450 I915_WRITE(IPEIR, ipeir);
451 (void)I915_READ(IPEIR);
452 } else {
453 u32 ipeir = I915_READ(IPEIR_I965);
454
455 printk(KERN_ERR " IPEIR: 0x%08x\n",
456 I915_READ(IPEIR_I965));
457 printk(KERN_ERR " IPEHR: 0x%08x\n",
458 I915_READ(IPEHR_I965));
459 printk(KERN_ERR " INSTDONE: 0x%08x\n",
460 I915_READ(INSTDONE_I965));
461 printk(KERN_ERR " INSTPS: 0x%08x\n",
462 I915_READ(INSTPS));
463 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
464 I915_READ(INSTDONE1));
465 printk(KERN_ERR " ACTHD: 0x%08x\n",
466 I915_READ(ACTHD_I965));
467 I915_WRITE(IPEIR_I965, ipeir);
468 (void)I915_READ(IPEIR_I965);
469 }
470 }
471
472 I915_WRITE(EIR, eir);
473 (void)I915_READ(EIR);
474 eir = I915_READ(EIR);
475 if (eir) {
476 /*
477 * some errors might have become stuck,
478 * mask them.
479 */
480 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
481 I915_WRITE(EMR, I915_READ(EMR) | eir);
482 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
483 }
484
485 queue_work(dev_priv->wq, &dev_priv->error_work);
486}
487
334irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) 488irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
335{ 489{
336 struct drm_device *dev = (struct drm_device *) arg; 490 struct drm_device *dev = (struct drm_device *) arg;
@@ -372,6 +526,9 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
372 pipea_stats = I915_READ(PIPEASTAT); 526 pipea_stats = I915_READ(PIPEASTAT);
373 pipeb_stats = I915_READ(PIPEBSTAT); 527 pipeb_stats = I915_READ(PIPEBSTAT);
374 528
529 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
530 i915_handle_error(dev);
531
375 /* 532 /*
376 * Clear the PIPE(A|B)STAT regs before the IIR 533 * Clear the PIPE(A|B)STAT regs before the IIR
377 */ 534 */
@@ -403,86 +560,13 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
403 DRM_DEBUG("hotplug event received, stat 0x%08x\n", 560 DRM_DEBUG("hotplug event received, stat 0x%08x\n",
404 hotplug_status); 561 hotplug_status);
405 if (hotplug_status & dev_priv->hotplug_supported_mask) 562 if (hotplug_status & dev_priv->hotplug_supported_mask)
406 schedule_work(&dev_priv->hotplug_work); 563 queue_work(dev_priv->wq,
564 &dev_priv->hotplug_work);
407 565
408 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 566 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
409 I915_READ(PORT_HOTPLUG_STAT); 567 I915_READ(PORT_HOTPLUG_STAT);
410 } 568 }
411 569
412 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) {
413 u32 eir = I915_READ(EIR);
414
415 i915_capture_error_state(dev);
416
417 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
418 eir);
419 if (eir & I915_ERROR_PAGE_TABLE) {
420 u32 pgtbl_err = I915_READ(PGTBL_ER);
421 printk(KERN_ERR "page table error\n");
422 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
423 pgtbl_err);
424 I915_WRITE(PGTBL_ER, pgtbl_err);
425 (void)I915_READ(PGTBL_ER);
426 }
427 if (eir & I915_ERROR_MEMORY_REFRESH) {
428 printk(KERN_ERR "memory refresh error\n");
429 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
430 pipea_stats);
431 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
432 pipeb_stats);
433 /* pipestat has already been acked */
434 }
435 if (eir & I915_ERROR_INSTRUCTION) {
436 printk(KERN_ERR "instruction error\n");
437 printk(KERN_ERR " INSTPM: 0x%08x\n",
438 I915_READ(INSTPM));
439 if (!IS_I965G(dev)) {
440 u32 ipeir = I915_READ(IPEIR);
441
442 printk(KERN_ERR " IPEIR: 0x%08x\n",
443 I915_READ(IPEIR));
444 printk(KERN_ERR " IPEHR: 0x%08x\n",
445 I915_READ(IPEHR));
446 printk(KERN_ERR " INSTDONE: 0x%08x\n",
447 I915_READ(INSTDONE));
448 printk(KERN_ERR " ACTHD: 0x%08x\n",
449 I915_READ(ACTHD));
450 I915_WRITE(IPEIR, ipeir);
451 (void)I915_READ(IPEIR);
452 } else {
453 u32 ipeir = I915_READ(IPEIR_I965);
454
455 printk(KERN_ERR " IPEIR: 0x%08x\n",
456 I915_READ(IPEIR_I965));
457 printk(KERN_ERR " IPEHR: 0x%08x\n",
458 I915_READ(IPEHR_I965));
459 printk(KERN_ERR " INSTDONE: 0x%08x\n",
460 I915_READ(INSTDONE_I965));
461 printk(KERN_ERR " INSTPS: 0x%08x\n",
462 I915_READ(INSTPS));
463 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
464 I915_READ(INSTDONE1));
465 printk(KERN_ERR " ACTHD: 0x%08x\n",
466 I915_READ(ACTHD_I965));
467 I915_WRITE(IPEIR_I965, ipeir);
468 (void)I915_READ(IPEIR_I965);
469 }
470 }
471
472 I915_WRITE(EIR, eir);
473 (void)I915_READ(EIR);
474 eir = I915_READ(EIR);
475 if (eir) {
476 /*
477 * some errors might have become stuck,
478 * mask them.
479 */
480 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
481 I915_WRITE(EMR, I915_READ(EMR) | eir);
482 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
483 }
484 }
485
486 I915_WRITE(IIR, iir); 570 I915_WRITE(IIR, iir);
487 new_iir = I915_READ(IIR); /* Flush posted writes */ 571 new_iir = I915_READ(IIR); /* Flush posted writes */
488 572
@@ -830,6 +914,7 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
830 atomic_set(&dev_priv->irq_received, 0); 914 atomic_set(&dev_priv->irq_received, 0);
831 915
832 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); 916 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
917 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
833 918
834 if (IS_IGDNG(dev)) { 919 if (IS_IGDNG(dev)) {
835 igdng_irq_preinstall(dev); 920 igdng_irq_preinstall(dev);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6c0858484094..2955083aa471 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1395,6 +1395,7 @@
1395#define TV_V_CHROMA_42 0x684a8 1395#define TV_V_CHROMA_42 0x684a8
1396 1396
1397/* Display Port */ 1397/* Display Port */
1398#define DP_A 0x64000 /* eDP */
1398#define DP_B 0x64100 1399#define DP_B 0x64100
1399#define DP_C 0x64200 1400#define DP_C 0x64200
1400#define DP_D 0x64300 1401#define DP_D 0x64300
@@ -1437,13 +1438,22 @@
1437/* Mystic DPCD version 1.1 special mode */ 1438/* Mystic DPCD version 1.1 special mode */
1438#define DP_ENHANCED_FRAMING (1 << 18) 1439#define DP_ENHANCED_FRAMING (1 << 18)
1439 1440
1441/* eDP */
1442#define DP_PLL_FREQ_270MHZ (0 << 16)
1443#define DP_PLL_FREQ_160MHZ (1 << 16)
1444#define DP_PLL_FREQ_MASK (3 << 16)
1445
1440/** locked once port is enabled */ 1446/** locked once port is enabled */
1441#define DP_PORT_REVERSAL (1 << 15) 1447#define DP_PORT_REVERSAL (1 << 15)
1442 1448
1449/* eDP */
1450#define DP_PLL_ENABLE (1 << 14)
1451
1443/** sends the clock on lane 15 of the PEG for debug */ 1452/** sends the clock on lane 15 of the PEG for debug */
1444#define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 1453#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
1445 1454
1446#define DP_SCRAMBLING_DISABLE (1 << 12) 1455#define DP_SCRAMBLING_DISABLE (1 << 12)
1456#define DP_SCRAMBLING_DISABLE_IGDNG (1 << 7)
1447 1457
1448/** limit RGB values to avoid confusing TVs */ 1458/** limit RGB values to avoid confusing TVs */
1449#define DP_COLOR_RANGE_16_235 (1 << 8) 1459#define DP_COLOR_RANGE_16_235 (1 << 8)
@@ -1463,6 +1473,13 @@
1463 * is 20 bytes in each direction, hence the 5 fixed 1473 * is 20 bytes in each direction, hence the 5 fixed
1464 * data registers 1474 * data registers
1465 */ 1475 */
1476#define DPA_AUX_CH_CTL 0x64010
1477#define DPA_AUX_CH_DATA1 0x64014
1478#define DPA_AUX_CH_DATA2 0x64018
1479#define DPA_AUX_CH_DATA3 0x6401c
1480#define DPA_AUX_CH_DATA4 0x64020
1481#define DPA_AUX_CH_DATA5 0x64024
1482
1466#define DPB_AUX_CH_CTL 0x64110 1483#define DPB_AUX_CH_CTL 0x64110
1467#define DPB_AUX_CH_DATA1 0x64114 1484#define DPB_AUX_CH_DATA1 0x64114
1468#define DPB_AUX_CH_DATA2 0x64118 1485#define DPB_AUX_CH_DATA2 0x64118
@@ -1618,7 +1635,7 @@
1618#define I830_FIFO_LINE_SIZE 32 1635#define I830_FIFO_LINE_SIZE 32
1619#define I945_FIFO_SIZE 127 /* 945 & 965 */ 1636#define I945_FIFO_SIZE 127 /* 945 & 965 */
1620#define I915_FIFO_SIZE 95 1637#define I915_FIFO_SIZE 95
1621#define I855GM_FIFO_SIZE 255 1638#define I855GM_FIFO_SIZE 127 /* In cachelines */
1622#define I830_FIFO_SIZE 95 1639#define I830_FIFO_SIZE 95
1623#define I915_MAX_WM 0x3f 1640#define I915_MAX_WM 0x3f
1624 1641
@@ -1848,6 +1865,8 @@
1848#define PFA_CTL_1 0x68080 1865#define PFA_CTL_1 0x68080
1849#define PFB_CTL_1 0x68880 1866#define PFB_CTL_1 0x68880
1850#define PF_ENABLE (1<<31) 1867#define PF_ENABLE (1<<31)
1868#define PFA_WIN_SZ 0x68074
1869#define PFB_WIN_SZ 0x68874
1851 1870
1852/* legacy palette */ 1871/* legacy palette */
1853#define LGC_PALETTE_A 0x4a000 1872#define LGC_PALETTE_A 0x4a000
@@ -2208,4 +2227,28 @@
2208#define PCH_PP_OFF_DELAYS 0xc720c 2227#define PCH_PP_OFF_DELAYS 0xc720c
2209#define PCH_PP_DIVISOR 0xc7210 2228#define PCH_PP_DIVISOR 0xc7210
2210 2229
2230#define PCH_DP_B 0xe4100
2231#define PCH_DPB_AUX_CH_CTL 0xe4110
2232#define PCH_DPB_AUX_CH_DATA1 0xe4114
2233#define PCH_DPB_AUX_CH_DATA2 0xe4118
2234#define PCH_DPB_AUX_CH_DATA3 0xe411c
2235#define PCH_DPB_AUX_CH_DATA4 0xe4120
2236#define PCH_DPB_AUX_CH_DATA5 0xe4124
2237
2238#define PCH_DP_C 0xe4200
2239#define PCH_DPC_AUX_CH_CTL 0xe4210
2240#define PCH_DPC_AUX_CH_DATA1 0xe4214
2241#define PCH_DPC_AUX_CH_DATA2 0xe4218
2242#define PCH_DPC_AUX_CH_DATA3 0xe421c
2243#define PCH_DPC_AUX_CH_DATA4 0xe4220
2244#define PCH_DPC_AUX_CH_DATA5 0xe4224
2245
2246#define PCH_DP_D 0xe4300
2247#define PCH_DPD_AUX_CH_CTL 0xe4310
2248#define PCH_DPD_AUX_CH_DATA1 0xe4314
2249#define PCH_DPD_AUX_CH_DATA2 0xe4318
2250#define PCH_DPD_AUX_CH_DATA3 0xe431c
2251#define PCH_DPD_AUX_CH_DATA4 0xe4320
2252#define PCH_DPD_AUX_CH_DATA5 0xe4324
2253
2211#endif /* _I915_REG_H_ */ 2254#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 9e1d16e5c3ea..1d04e1904ac6 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -598,7 +598,7 @@ int i915_restore_state(struct drm_device *dev)
598 598
599 for (i = 0; i < 16; i++) { 599 for (i = 0; i < 16; i++) {
600 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]); 600 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
601 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]); 601 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);
602 } 602 }
603 for (i = 0; i < 3; i++) 603 for (i = 0; i < 3; i++)
604 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]); 604 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 7cc447191028..300aee3296c2 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -97,14 +97,13 @@ static void
97parse_lfp_panel_data(struct drm_i915_private *dev_priv, 97parse_lfp_panel_data(struct drm_i915_private *dev_priv,
98 struct bdb_header *bdb) 98 struct bdb_header *bdb)
99{ 99{
100 struct drm_device *dev = dev_priv->dev;
101 struct bdb_lvds_options *lvds_options; 100 struct bdb_lvds_options *lvds_options;
102 struct bdb_lvds_lfp_data *lvds_lfp_data; 101 struct bdb_lvds_lfp_data *lvds_lfp_data;
103 struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs; 102 struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs;
104 struct bdb_lvds_lfp_data_entry *entry; 103 struct bdb_lvds_lfp_data_entry *entry;
105 struct lvds_dvo_timing *dvo_timing; 104 struct lvds_dvo_timing *dvo_timing;
106 struct drm_display_mode *panel_fixed_mode; 105 struct drm_display_mode *panel_fixed_mode;
107 int lfp_data_size; 106 int lfp_data_size, dvo_timing_offset;
108 107
109 /* Defaults if we can't find VBT info */ 108 /* Defaults if we can't find VBT info */
110 dev_priv->lvds_dither = 0; 109 dev_priv->lvds_dither = 0;
@@ -133,14 +132,16 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
133 entry = (struct bdb_lvds_lfp_data_entry *) 132 entry = (struct bdb_lvds_lfp_data_entry *)
134 ((uint8_t *)lvds_lfp_data->data + (lfp_data_size * 133 ((uint8_t *)lvds_lfp_data->data + (lfp_data_size *
135 lvds_options->panel_type)); 134 lvds_options->panel_type));
135 dvo_timing_offset = lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset -
136 lvds_lfp_data_ptrs->ptr[0].fp_timing_offset;
136 137
137 /* On IGDNG mobile, LVDS data block removes panel fitting registers. 138 /*
138 So dec 2 dword from dvo_timing offset */ 139 * the size of fp_timing varies on the different platform.
139 if (IS_IGDNG(dev)) 140 * So calculate the DVO timing relative offset in LVDS data
140 dvo_timing = (struct lvds_dvo_timing *) 141 * entry to get the DVO timing entry
141 ((u8 *)&entry->dvo_timing - 8); 142 */
142 else 143 dvo_timing = (struct lvds_dvo_timing *)
143 dvo_timing = &entry->dvo_timing; 144 ((unsigned char *)entry + dvo_timing_offset);
144 145
145 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); 146 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
146 147
@@ -295,6 +296,25 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
295 } 296 }
296 return; 297 return;
297} 298}
299
300static void
301parse_driver_features(struct drm_i915_private *dev_priv,
302 struct bdb_header *bdb)
303{
304 struct drm_device *dev = dev_priv->dev;
305 struct bdb_driver_features *driver;
306
307 /* set default for chips without eDP */
308 if (!SUPPORTS_EDP(dev)) {
309 dev_priv->edp_support = 0;
310 return;
311 }
312
313 driver = find_section(bdb, BDB_DRIVER_FEATURES);
314 if (driver && driver->lvds_config == BDB_DRIVER_FEATURE_EDP)
315 dev_priv->edp_support = 1;
316}
317
298/** 318/**
299 * intel_init_bios - initialize VBIOS settings & find VBT 319 * intel_init_bios - initialize VBIOS settings & find VBT
300 * @dev: DRM device 320 * @dev: DRM device
@@ -345,6 +365,8 @@ intel_init_bios(struct drm_device *dev)
345 parse_lfp_panel_data(dev_priv, bdb); 365 parse_lfp_panel_data(dev_priv, bdb);
346 parse_sdvo_panel_data(dev_priv, bdb); 366 parse_sdvo_panel_data(dev_priv, bdb);
347 parse_sdvo_device_mapping(dev_priv, bdb); 367 parse_sdvo_device_mapping(dev_priv, bdb);
368 parse_driver_features(dev_priv, bdb);
369
348 pci_unmap_rom(pdev, bios); 370 pci_unmap_rom(pdev, bios);
349 371
350 return 0; 372 return 0;
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index fe72e1c225d8..0f8e5f69ac7a 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -381,6 +381,51 @@ struct bdb_sdvo_lvds_options {
381} __attribute__((packed)); 381} __attribute__((packed));
382 382
383 383
384#define BDB_DRIVER_FEATURE_NO_LVDS 0
385#define BDB_DRIVER_FEATURE_INT_LVDS 1
386#define BDB_DRIVER_FEATURE_SDVO_LVDS 2
387#define BDB_DRIVER_FEATURE_EDP 3
388
389struct bdb_driver_features {
390 u8 boot_dev_algorithm:1;
391 u8 block_display_switch:1;
392 u8 allow_display_switch:1;
393 u8 hotplug_dvo:1;
394 u8 dual_view_zoom:1;
395 u8 int15h_hook:1;
396 u8 sprite_in_clone:1;
397 u8 primary_lfp_id:1;
398
399 u16 boot_mode_x;
400 u16 boot_mode_y;
401 u8 boot_mode_bpp;
402 u8 boot_mode_refresh;
403
404 u16 enable_lfp_primary:1;
405 u16 selective_mode_pruning:1;
406 u16 dual_frequency:1;
407 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
408 u16 nt_clone_support:1;
409 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
410 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
411 u16 cui_aspect_scaling:1;
412 u16 preserve_aspect_ratio:1;
413 u16 sdvo_device_power_down:1;
414 u16 crt_hotplug:1;
415 u16 lvds_config:2;
416 u16 tv_hotplug:1;
417 u16 hdmi_config:2;
418
419 u8 static_display:1;
420 u8 reserved2:7;
421 u16 legacy_crt_max_x;
422 u16 legacy_crt_max_y;
423 u8 legacy_crt_max_refresh;
424
425 u8 hdmi_termination;
426 u8 custom_vbt_version;
427} __attribute__((packed));
428
384bool intel_init_bios(struct drm_device *dev); 429bool intel_init_bios(struct drm_device *dev);
385 430
386/* 431/*
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index d6a1a6e5539a..4cf8e2e88a40 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -156,6 +156,9 @@ static bool intel_igdng_crt_detect_hotplug(struct drm_connector *connector)
156 156
157 temp = adpa = I915_READ(PCH_ADPA); 157 temp = adpa = I915_READ(PCH_ADPA);
158 158
159 adpa &= ~ADPA_DAC_ENABLE;
160 I915_WRITE(PCH_ADPA, adpa);
161
159 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 162 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
160 163
161 adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 | 164 adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 |
@@ -169,13 +172,14 @@ static bool intel_igdng_crt_detect_hotplug(struct drm_connector *connector)
169 DRM_DEBUG("pch crt adpa 0x%x", adpa); 172 DRM_DEBUG("pch crt adpa 0x%x", adpa);
170 I915_WRITE(PCH_ADPA, adpa); 173 I915_WRITE(PCH_ADPA, adpa);
171 174
172 /* This might not be needed as not specified in spec...*/ 175 while ((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) != 0)
173 udelay(1000); 176 ;
174 177
175 /* Check the status to see if both blue and green are on now */ 178 /* Check the status to see if both blue and green are on now */
176 adpa = I915_READ(PCH_ADPA); 179 adpa = I915_READ(PCH_ADPA);
177 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) == 180 adpa &= ADPA_CRT_HOTPLUG_MONITOR_MASK;
178 ADPA_CRT_HOTPLUG_MONITOR_COLOR) 181 if ((adpa == ADPA_CRT_HOTPLUG_MONITOR_COLOR) ||
182 (adpa == ADPA_CRT_HOTPLUG_MONITOR_MONO))
179 ret = true; 183 ret = true;
180 else 184 else
181 ret = false; 185 ret = false;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 508838ee31e0..d6fce2133413 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -34,6 +34,8 @@
34 34
35#include "drm_crtc_helper.h" 35#include "drm_crtc_helper.h"
36 36
37#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
38
37bool intel_pipe_has_type (struct drm_crtc *crtc, int type); 39bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
38static void intel_update_watermarks(struct drm_device *dev); 40static void intel_update_watermarks(struct drm_device *dev);
39 41
@@ -88,7 +90,7 @@ struct intel_limit {
88#define I8XX_P2_SLOW 4 90#define I8XX_P2_SLOW 4
89#define I8XX_P2_FAST 2 91#define I8XX_P2_FAST 2
90#define I8XX_P2_LVDS_SLOW 14 92#define I8XX_P2_LVDS_SLOW 14
91#define I8XX_P2_LVDS_FAST 14 /* No fast option */ 93#define I8XX_P2_LVDS_FAST 7
92#define I8XX_P2_SLOW_LIMIT 165000 94#define I8XX_P2_SLOW_LIMIT 165000
93 95
94#define I9XX_DOT_MIN 20000 96#define I9XX_DOT_MIN 20000
@@ -268,6 +270,9 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
268static bool 270static bool
269intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, 271intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
270 int target, int refclk, intel_clock_t *best_clock); 272 int target, int refclk, intel_clock_t *best_clock);
273static bool
274intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc,
275 int target, int refclk, intel_clock_t *best_clock);
271 276
272static const intel_limit_t intel_limits_i8xx_dvo = { 277static const intel_limit_t intel_limits_i8xx_dvo = {
273 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, 278 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
@@ -598,6 +603,23 @@ bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
598 return false; 603 return false;
599} 604}
600 605
606struct drm_connector *
607intel_pipe_get_output (struct drm_crtc *crtc)
608{
609 struct drm_device *dev = crtc->dev;
610 struct drm_mode_config *mode_config = &dev->mode_config;
611 struct drm_connector *l_entry, *ret = NULL;
612
613 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
614 if (l_entry->encoder &&
615 l_entry->encoder->crtc == crtc) {
616 ret = l_entry;
617 break;
618 }
619 }
620 return ret;
621}
622
601#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) 623#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
602/** 624/**
603 * Returns whether the given set of divisors are valid for a given refclk with 625 * Returns whether the given set of divisors are valid for a given refclk with
@@ -645,7 +667,7 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
645 int err = target; 667 int err = target;
646 668
647 if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 669 if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
648 (I915_READ(LVDS) & LVDS_PORT_EN) != 0) { 670 (I915_READ(LVDS)) != 0) {
649 /* 671 /*
650 * For LVDS, if the panel is on, just rely on its current 672 * For LVDS, if the panel is on, just rely on its current
651 * settings for dual-channel. We haven't figured out how to 673 * settings for dual-channel. We haven't figured out how to
@@ -752,6 +774,30 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
752} 774}
753 775
754static bool 776static bool
777intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
778 int target, int refclk, intel_clock_t *best_clock)
779{
780 struct drm_device *dev = crtc->dev;
781 intel_clock_t clock;
782 if (target < 200000) {
783 clock.n = 1;
784 clock.p1 = 2;
785 clock.p2 = 10;
786 clock.m1 = 12;
787 clock.m2 = 9;
788 } else {
789 clock.n = 2;
790 clock.p1 = 1;
791 clock.p2 = 10;
792 clock.m1 = 14;
793 clock.m2 = 8;
794 }
795 intel_clock(dev, refclk, &clock);
796 memcpy(best_clock, &clock, sizeof(intel_clock_t));
797 return true;
798}
799
800static bool
755intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 801intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
756 int target, int refclk, intel_clock_t *best_clock) 802 int target, int refclk, intel_clock_t *best_clock)
757{ 803{
@@ -763,6 +809,14 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
763 int err_most = 47; 809 int err_most = 47;
764 found = false; 810 found = false;
765 811
812 /* eDP has only 2 clock choice, no n/m/p setting */
813 if (HAS_eDP)
814 return true;
815
816 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
817 return intel_find_pll_igdng_dp(limit, crtc, target,
818 refclk, best_clock);
819
766 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 820 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
767 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == 821 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
768 LVDS_CLKB_POWER_UP) 822 LVDS_CLKB_POWER_UP)
@@ -998,6 +1052,90 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
998 return 0; 1052 return 0;
999} 1053}
1000 1054
1055/* Disable the VGA plane that we never use */
1056static void i915_disable_vga (struct drm_device *dev)
1057{
1058 struct drm_i915_private *dev_priv = dev->dev_private;
1059 u8 sr1;
1060 u32 vga_reg;
1061
1062 if (IS_IGDNG(dev))
1063 vga_reg = CPU_VGACNTRL;
1064 else
1065 vga_reg = VGACNTRL;
1066
1067 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1068 return;
1069
1070 I915_WRITE8(VGA_SR_INDEX, 1);
1071 sr1 = I915_READ8(VGA_SR_DATA);
1072 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1073 udelay(100);
1074
1075 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1076}
1077
1078static void igdng_disable_pll_edp (struct drm_crtc *crtc)
1079{
1080 struct drm_device *dev = crtc->dev;
1081 struct drm_i915_private *dev_priv = dev->dev_private;
1082 u32 dpa_ctl;
1083
1084 DRM_DEBUG("\n");
1085 dpa_ctl = I915_READ(DP_A);
1086 dpa_ctl &= ~DP_PLL_ENABLE;
1087 I915_WRITE(DP_A, dpa_ctl);
1088}
1089
1090static void igdng_enable_pll_edp (struct drm_crtc *crtc)
1091{
1092 struct drm_device *dev = crtc->dev;
1093 struct drm_i915_private *dev_priv = dev->dev_private;
1094 u32 dpa_ctl;
1095
1096 dpa_ctl = I915_READ(DP_A);
1097 dpa_ctl |= DP_PLL_ENABLE;
1098 I915_WRITE(DP_A, dpa_ctl);
1099 udelay(200);
1100}
1101
1102
1103static void igdng_set_pll_edp (struct drm_crtc *crtc, int clock)
1104{
1105 struct drm_device *dev = crtc->dev;
1106 struct drm_i915_private *dev_priv = dev->dev_private;
1107 u32 dpa_ctl;
1108
1109 DRM_DEBUG("eDP PLL enable for clock %d\n", clock);
1110 dpa_ctl = I915_READ(DP_A);
1111 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1112
1113 if (clock < 200000) {
1114 u32 temp;
1115 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1116 /* workaround for 160Mhz:
1117 1) program 0x4600c bits 15:0 = 0x8124
1118 2) program 0x46010 bit 0 = 1
1119 3) program 0x46034 bit 24 = 1
1120 4) program 0x64000 bit 14 = 1
1121 */
1122 temp = I915_READ(0x4600c);
1123 temp &= 0xffff0000;
1124 I915_WRITE(0x4600c, temp | 0x8124);
1125
1126 temp = I915_READ(0x46010);
1127 I915_WRITE(0x46010, temp | 1);
1128
1129 temp = I915_READ(0x46034);
1130 I915_WRITE(0x46034, temp | (1 << 24));
1131 } else {
1132 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1133 }
1134 I915_WRITE(DP_A, dpa_ctl);
1135
1136 udelay(500);
1137}
1138
1001static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode) 1139static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1002{ 1140{
1003 struct drm_device *dev = crtc->dev; 1141 struct drm_device *dev = crtc->dev;
@@ -1015,6 +1153,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1015 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR; 1153 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1016 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF; 1154 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1017 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1; 1155 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1156 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1018 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; 1157 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1019 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; 1158 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1020 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; 1159 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
@@ -1028,7 +1167,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1028 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B; 1167 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1029 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B; 1168 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1030 u32 temp; 1169 u32 temp;
1031 int tries = 5, j; 1170 int tries = 5, j, n;
1032 1171
1033 /* XXX: When our outputs are all unaware of DPMS modes other than off 1172 /* XXX: When our outputs are all unaware of DPMS modes other than off
1034 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. 1173 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
@@ -1038,27 +1177,32 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1038 case DRM_MODE_DPMS_STANDBY: 1177 case DRM_MODE_DPMS_STANDBY:
1039 case DRM_MODE_DPMS_SUSPEND: 1178 case DRM_MODE_DPMS_SUSPEND:
1040 DRM_DEBUG("crtc %d dpms on\n", pipe); 1179 DRM_DEBUG("crtc %d dpms on\n", pipe);
1041 /* enable PCH DPLL */ 1180 if (HAS_eDP) {
1042 temp = I915_READ(pch_dpll_reg); 1181 /* enable eDP PLL */
1043 if ((temp & DPLL_VCO_ENABLE) == 0) { 1182 igdng_enable_pll_edp(crtc);
1044 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE); 1183 } else {
1045 I915_READ(pch_dpll_reg); 1184 /* enable PCH DPLL */
1046 } 1185 temp = I915_READ(pch_dpll_reg);
1047 1186 if ((temp & DPLL_VCO_ENABLE) == 0) {
1048 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 1187 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1049 temp = I915_READ(fdi_rx_reg); 1188 I915_READ(pch_dpll_reg);
1050 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE | 1189 }
1051 FDI_SEL_PCDCLK |
1052 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1053 I915_READ(fdi_rx_reg);
1054 udelay(200);
1055 1190
1056 /* Enable CPU FDI TX PLL, always on for IGDNG */ 1191 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1057 temp = I915_READ(fdi_tx_reg); 1192 temp = I915_READ(fdi_rx_reg);
1058 if ((temp & FDI_TX_PLL_ENABLE) == 0) { 1193 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1059 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE); 1194 FDI_SEL_PCDCLK |
1060 I915_READ(fdi_tx_reg); 1195 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1061 udelay(100); 1196 I915_READ(fdi_rx_reg);
1197 udelay(200);
1198
1199 /* Enable CPU FDI TX PLL, always on for IGDNG */
1200 temp = I915_READ(fdi_tx_reg);
1201 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1202 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1203 I915_READ(fdi_tx_reg);
1204 udelay(100);
1205 }
1062 } 1206 }
1063 1207
1064 /* Enable CPU pipe */ 1208 /* Enable CPU pipe */
@@ -1077,122 +1221,126 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1077 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); 1221 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1078 } 1222 }
1079 1223
1080 /* enable CPU FDI TX and PCH FDI RX */ 1224 if (!HAS_eDP) {
1081 temp = I915_READ(fdi_tx_reg); 1225 /* enable CPU FDI TX and PCH FDI RX */
1082 temp |= FDI_TX_ENABLE; 1226 temp = I915_READ(fdi_tx_reg);
1083 temp |= FDI_DP_PORT_WIDTH_X4; /* default */ 1227 temp |= FDI_TX_ENABLE;
1084 temp &= ~FDI_LINK_TRAIN_NONE; 1228 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1085 temp |= FDI_LINK_TRAIN_PATTERN_1; 1229 temp &= ~FDI_LINK_TRAIN_NONE;
1086 I915_WRITE(fdi_tx_reg, temp); 1230 temp |= FDI_LINK_TRAIN_PATTERN_1;
1087 I915_READ(fdi_tx_reg); 1231 I915_WRITE(fdi_tx_reg, temp);
1232 I915_READ(fdi_tx_reg);
1088 1233
1089 temp = I915_READ(fdi_rx_reg); 1234 temp = I915_READ(fdi_rx_reg);
1090 temp &= ~FDI_LINK_TRAIN_NONE; 1235 temp &= ~FDI_LINK_TRAIN_NONE;
1091 temp |= FDI_LINK_TRAIN_PATTERN_1; 1236 temp |= FDI_LINK_TRAIN_PATTERN_1;
1092 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE); 1237 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1093 I915_READ(fdi_rx_reg); 1238 I915_READ(fdi_rx_reg);
1094 1239
1095 udelay(150); 1240 udelay(150);
1096 1241
1097 /* Train FDI. */ 1242 /* Train FDI. */
1098 /* umask FDI RX Interrupt symbol_lock and bit_lock bit 1243 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1099 for train result */ 1244 for train result */
1100 temp = I915_READ(fdi_rx_imr_reg); 1245 temp = I915_READ(fdi_rx_imr_reg);
1101 temp &= ~FDI_RX_SYMBOL_LOCK; 1246 temp &= ~FDI_RX_SYMBOL_LOCK;
1102 temp &= ~FDI_RX_BIT_LOCK; 1247 temp &= ~FDI_RX_BIT_LOCK;
1103 I915_WRITE(fdi_rx_imr_reg, temp); 1248 I915_WRITE(fdi_rx_imr_reg, temp);
1104 I915_READ(fdi_rx_imr_reg); 1249 I915_READ(fdi_rx_imr_reg);
1105 udelay(150); 1250 udelay(150);
1106 1251
1107 temp = I915_READ(fdi_rx_iir_reg); 1252 temp = I915_READ(fdi_rx_iir_reg);
1108 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); 1253 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1109 1254
1110 if ((temp & FDI_RX_BIT_LOCK) == 0) { 1255 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1111 for (j = 0; j < tries; j++) { 1256 for (j = 0; j < tries; j++) {
1112 temp = I915_READ(fdi_rx_iir_reg); 1257 temp = I915_READ(fdi_rx_iir_reg);
1113 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); 1258 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1114 if (temp & FDI_RX_BIT_LOCK) 1259 if (temp & FDI_RX_BIT_LOCK)
1115 break; 1260 break;
1116 udelay(200); 1261 udelay(200);
1117 } 1262 }
1118 if (j != tries) 1263 if (j != tries)
1264 I915_WRITE(fdi_rx_iir_reg,
1265 temp | FDI_RX_BIT_LOCK);
1266 else
1267 DRM_DEBUG("train 1 fail\n");
1268 } else {
1119 I915_WRITE(fdi_rx_iir_reg, 1269 I915_WRITE(fdi_rx_iir_reg,
1120 temp | FDI_RX_BIT_LOCK); 1270 temp | FDI_RX_BIT_LOCK);
1121 else 1271 DRM_DEBUG("train 1 ok 2!\n");
1122 DRM_DEBUG("train 1 fail\n"); 1272 }
1123 } else { 1273 temp = I915_READ(fdi_tx_reg);
1124 I915_WRITE(fdi_rx_iir_reg, 1274 temp &= ~FDI_LINK_TRAIN_NONE;
1125 temp | FDI_RX_BIT_LOCK); 1275 temp |= FDI_LINK_TRAIN_PATTERN_2;
1126 DRM_DEBUG("train 1 ok 2!\n"); 1276 I915_WRITE(fdi_tx_reg, temp);
1127 } 1277
1128 temp = I915_READ(fdi_tx_reg); 1278 temp = I915_READ(fdi_rx_reg);
1129 temp &= ~FDI_LINK_TRAIN_NONE; 1279 temp &= ~FDI_LINK_TRAIN_NONE;
1130 temp |= FDI_LINK_TRAIN_PATTERN_2; 1280 temp |= FDI_LINK_TRAIN_PATTERN_2;
1131 I915_WRITE(fdi_tx_reg, temp); 1281 I915_WRITE(fdi_rx_reg, temp);
1132
1133 temp = I915_READ(fdi_rx_reg);
1134 temp &= ~FDI_LINK_TRAIN_NONE;
1135 temp |= FDI_LINK_TRAIN_PATTERN_2;
1136 I915_WRITE(fdi_rx_reg, temp);
1137 1282
1138 udelay(150); 1283 udelay(150);
1139 1284
1140 temp = I915_READ(fdi_rx_iir_reg); 1285 temp = I915_READ(fdi_rx_iir_reg);
1141 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); 1286 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1142 1287
1143 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) { 1288 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1144 for (j = 0; j < tries; j++) { 1289 for (j = 0; j < tries; j++) {
1145 temp = I915_READ(fdi_rx_iir_reg); 1290 temp = I915_READ(fdi_rx_iir_reg);
1146 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); 1291 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1147 if (temp & FDI_RX_SYMBOL_LOCK) 1292 if (temp & FDI_RX_SYMBOL_LOCK)
1148 break; 1293 break;
1149 udelay(200); 1294 udelay(200);
1150 } 1295 }
1151 if (j != tries) { 1296 if (j != tries) {
1297 I915_WRITE(fdi_rx_iir_reg,
1298 temp | FDI_RX_SYMBOL_LOCK);
1299 DRM_DEBUG("train 2 ok 1!\n");
1300 } else
1301 DRM_DEBUG("train 2 fail\n");
1302 } else {
1152 I915_WRITE(fdi_rx_iir_reg, 1303 I915_WRITE(fdi_rx_iir_reg,
1153 temp | FDI_RX_SYMBOL_LOCK); 1304 temp | FDI_RX_SYMBOL_LOCK);
1154 DRM_DEBUG("train 2 ok 1!\n"); 1305 DRM_DEBUG("train 2 ok 2!\n");
1155 } else 1306 }
1156 DRM_DEBUG("train 2 fail\n"); 1307 DRM_DEBUG("train done\n");
1157 } else {
1158 I915_WRITE(fdi_rx_iir_reg, temp | FDI_RX_SYMBOL_LOCK);
1159 DRM_DEBUG("train 2 ok 2!\n");
1160 }
1161 DRM_DEBUG("train done\n");
1162 1308
1163 /* set transcoder timing */ 1309 /* set transcoder timing */
1164 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg)); 1310 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1165 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg)); 1311 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1166 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg)); 1312 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1167 1313
1168 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg)); 1314 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1169 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg)); 1315 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1170 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg)); 1316 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1171 1317
1172 /* enable PCH transcoder */ 1318 /* enable PCH transcoder */
1173 temp = I915_READ(transconf_reg); 1319 temp = I915_READ(transconf_reg);
1174 I915_WRITE(transconf_reg, temp | TRANS_ENABLE); 1320 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1175 I915_READ(transconf_reg); 1321 I915_READ(transconf_reg);
1176 1322
1177 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0) 1323 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1178 ; 1324 ;
1179 1325
1180 /* enable normal */ 1326 /* enable normal */
1181 1327
1182 temp = I915_READ(fdi_tx_reg); 1328 temp = I915_READ(fdi_tx_reg);
1183 temp &= ~FDI_LINK_TRAIN_NONE; 1329 temp &= ~FDI_LINK_TRAIN_NONE;
1184 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE | 1330 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1185 FDI_TX_ENHANCE_FRAME_ENABLE); 1331 FDI_TX_ENHANCE_FRAME_ENABLE);
1186 I915_READ(fdi_tx_reg); 1332 I915_READ(fdi_tx_reg);
1187 1333
1188 temp = I915_READ(fdi_rx_reg); 1334 temp = I915_READ(fdi_rx_reg);
1189 temp &= ~FDI_LINK_TRAIN_NONE; 1335 temp &= ~FDI_LINK_TRAIN_NONE;
1190 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE | 1336 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1191 FDI_RX_ENHANCE_FRAME_ENABLE); 1337 FDI_RX_ENHANCE_FRAME_ENABLE);
1192 I915_READ(fdi_rx_reg); 1338 I915_READ(fdi_rx_reg);
1193 1339
1194 /* wait one idle pattern time */ 1340 /* wait one idle pattern time */
1195 udelay(100); 1341 udelay(100);
1342
1343 }
1196 1344
1197 intel_crtc_load_lut(crtc); 1345 intel_crtc_load_lut(crtc);
1198 1346
@@ -1200,8 +1348,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1200 case DRM_MODE_DPMS_OFF: 1348 case DRM_MODE_DPMS_OFF:
1201 DRM_DEBUG("crtc %d dpms off\n", pipe); 1349 DRM_DEBUG("crtc %d dpms off\n", pipe);
1202 1350
1203 /* Disable the VGA plane that we never use */ 1351 i915_disable_vga(dev);
1204 I915_WRITE(CPU_VGACNTRL, VGA_DISP_DISABLE);
1205 1352
1206 /* Disable display plane */ 1353 /* Disable display plane */
1207 temp = I915_READ(dspcntr_reg); 1354 temp = I915_READ(dspcntr_reg);
@@ -1217,17 +1364,23 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1217 if ((temp & PIPEACONF_ENABLE) != 0) { 1364 if ((temp & PIPEACONF_ENABLE) != 0) {
1218 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); 1365 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1219 I915_READ(pipeconf_reg); 1366 I915_READ(pipeconf_reg);
1367 n = 0;
1220 /* wait for cpu pipe off, pipe state */ 1368 /* wait for cpu pipe off, pipe state */
1221 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) 1369 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1222 ; 1370 n++;
1371 if (n < 60) {
1372 udelay(500);
1373 continue;
1374 } else {
1375 DRM_DEBUG("pipe %d off delay\n", pipe);
1376 break;
1377 }
1378 }
1223 } else 1379 } else
1224 DRM_DEBUG("crtc %d is disabled\n", pipe); 1380 DRM_DEBUG("crtc %d is disabled\n", pipe);
1225 1381
1226 /* IGDNG-A : disable cpu panel fitter ? */ 1382 if (HAS_eDP) {
1227 temp = I915_READ(pf_ctl_reg); 1383 igdng_disable_pll_edp(crtc);
1228 if ((temp & PF_ENABLE) != 0) {
1229 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1230 I915_READ(pf_ctl_reg);
1231 } 1384 }
1232 1385
1233 /* disable CPU FDI tx and PCH FDI rx */ 1386 /* disable CPU FDI tx and PCH FDI rx */
@@ -1239,6 +1392,8 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1239 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE); 1392 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1240 I915_READ(fdi_rx_reg); 1393 I915_READ(fdi_rx_reg);
1241 1394
1395 udelay(100);
1396
1242 /* still set train pattern 1 */ 1397 /* still set train pattern 1 */
1243 temp = I915_READ(fdi_tx_reg); 1398 temp = I915_READ(fdi_tx_reg);
1244 temp &= ~FDI_LINK_TRAIN_NONE; 1399 temp &= ~FDI_LINK_TRAIN_NONE;
@@ -1250,14 +1405,25 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1250 temp |= FDI_LINK_TRAIN_PATTERN_1; 1405 temp |= FDI_LINK_TRAIN_PATTERN_1;
1251 I915_WRITE(fdi_rx_reg, temp); 1406 I915_WRITE(fdi_rx_reg, temp);
1252 1407
1408 udelay(100);
1409
1253 /* disable PCH transcoder */ 1410 /* disable PCH transcoder */
1254 temp = I915_READ(transconf_reg); 1411 temp = I915_READ(transconf_reg);
1255 if ((temp & TRANS_ENABLE) != 0) { 1412 if ((temp & TRANS_ENABLE) != 0) {
1256 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE); 1413 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1257 I915_READ(transconf_reg); 1414 I915_READ(transconf_reg);
1415 n = 0;
1258 /* wait for PCH transcoder off, transcoder state */ 1416 /* wait for PCH transcoder off, transcoder state */
1259 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) 1417 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1260 ; 1418 n++;
1419 if (n < 60) {
1420 udelay(500);
1421 continue;
1422 } else {
1423 DRM_DEBUG("transcoder %d off delay\n", pipe);
1424 break;
1425 }
1426 }
1261 } 1427 }
1262 1428
1263 /* disable PCH DPLL */ 1429 /* disable PCH DPLL */
@@ -1275,6 +1441,22 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1275 I915_READ(fdi_rx_reg); 1441 I915_READ(fdi_rx_reg);
1276 } 1442 }
1277 1443
1444 /* Disable CPU FDI TX PLL */
1445 temp = I915_READ(fdi_tx_reg);
1446 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1447 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1448 I915_READ(fdi_tx_reg);
1449 udelay(100);
1450 }
1451
1452 /* Disable PF */
1453 temp = I915_READ(pf_ctl_reg);
1454 if ((temp & PF_ENABLE) != 0) {
1455 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1456 I915_READ(pf_ctl_reg);
1457 }
1458 I915_WRITE(pf_win_size, 0);
1459
1278 /* Wait for the clocks to turn off. */ 1460 /* Wait for the clocks to turn off. */
1279 udelay(150); 1461 udelay(150);
1280 break; 1462 break;
@@ -1342,7 +1524,7 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1342 //intel_crtc_dpms_video(crtc, FALSE); TODO 1524 //intel_crtc_dpms_video(crtc, FALSE); TODO
1343 1525
1344 /* Disable the VGA plane that we never use */ 1526 /* Disable the VGA plane that we never use */
1345 I915_WRITE(VGACNTRL, VGA_DISP_DISABLE); 1527 i915_disable_vga(dev);
1346 1528
1347 /* Disable display plane */ 1529 /* Disable display plane */
1348 temp = I915_READ(dspcntr_reg); 1530 temp = I915_READ(dspcntr_reg);
@@ -1623,48 +1805,72 @@ static struct intel_watermark_params igd_cursor_hplloff_wm = {
1623 IGD_FIFO_LINE_SIZE 1805 IGD_FIFO_LINE_SIZE
1624}; 1806};
1625static struct intel_watermark_params i945_wm_info = { 1807static struct intel_watermark_params i945_wm_info = {
1626 I915_FIFO_LINE_SIZE, 1808 I945_FIFO_SIZE,
1627 I915_MAX_WM, 1809 I915_MAX_WM,
1628 1, 1810 1,
1629 0, 1811 2,
1630 IGD_FIFO_LINE_SIZE 1812 I915_FIFO_LINE_SIZE
1631}; 1813};
1632static struct intel_watermark_params i915_wm_info = { 1814static struct intel_watermark_params i915_wm_info = {
1633 I945_FIFO_SIZE, 1815 I915_FIFO_SIZE,
1634 I915_MAX_WM, 1816 I915_MAX_WM,
1635 1, 1817 1,
1636 0, 1818 2,
1637 I915_FIFO_LINE_SIZE 1819 I915_FIFO_LINE_SIZE
1638}; 1820};
1639static struct intel_watermark_params i855_wm_info = { 1821static struct intel_watermark_params i855_wm_info = {
1640 I855GM_FIFO_SIZE, 1822 I855GM_FIFO_SIZE,
1641 I915_MAX_WM, 1823 I915_MAX_WM,
1642 1, 1824 1,
1643 0, 1825 2,
1644 I830_FIFO_LINE_SIZE 1826 I830_FIFO_LINE_SIZE
1645}; 1827};
1646static struct intel_watermark_params i830_wm_info = { 1828static struct intel_watermark_params i830_wm_info = {
1647 I830_FIFO_SIZE, 1829 I830_FIFO_SIZE,
1648 I915_MAX_WM, 1830 I915_MAX_WM,
1649 1, 1831 1,
1650 0, 1832 2,
1651 I830_FIFO_LINE_SIZE 1833 I830_FIFO_LINE_SIZE
1652}; 1834};
1653 1835
1836/**
1837 * intel_calculate_wm - calculate watermark level
1838 * @clock_in_khz: pixel clock
1839 * @wm: chip FIFO params
1840 * @pixel_size: display pixel size
1841 * @latency_ns: memory latency for the platform
1842 *
1843 * Calculate the watermark level (the level at which the display plane will
1844 * start fetching from memory again). Each chip has a different display
1845 * FIFO size and allocation, so the caller needs to figure that out and pass
1846 * in the correct intel_watermark_params structure.
1847 *
1848 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1849 * on the pixel size. When it reaches the watermark level, it'll start
1850 * fetching FIFO line sized based chunks from memory until the FIFO fills
1851 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1852 * will occur, and a display engine hang could result.
1853 */
1654static unsigned long intel_calculate_wm(unsigned long clock_in_khz, 1854static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1655 struct intel_watermark_params *wm, 1855 struct intel_watermark_params *wm,
1656 int pixel_size, 1856 int pixel_size,
1657 unsigned long latency_ns) 1857 unsigned long latency_ns)
1658{ 1858{
1659 unsigned long bytes_required, wm_size; 1859 long entries_required, wm_size;
1860
1861 entries_required = (clock_in_khz * pixel_size * latency_ns) / 1000000;
1862 entries_required /= wm->cacheline_size;
1660 1863
1661 bytes_required = (clock_in_khz * pixel_size * latency_ns) / 1000000; 1864 DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
1662 bytes_required /= wm->cacheline_size;
1663 wm_size = wm->fifo_size - bytes_required - wm->guard_size;
1664 1865
1665 if (wm_size > wm->max_wm) 1866 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
1867
1868 DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
1869
1870 /* Don't promote wm_size to unsigned... */
1871 if (wm_size > (long)wm->max_wm)
1666 wm_size = wm->max_wm; 1872 wm_size = wm->max_wm;
1667 if (wm_size == 0) 1873 if (wm_size <= 0)
1668 wm_size = wm->default_wm; 1874 wm_size = wm->default_wm;
1669 return wm_size; 1875 return wm_size;
1670} 1876}
@@ -1799,8 +2005,40 @@ static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
1799 return; 2005 return;
1800} 2006}
1801 2007
1802const static int latency_ns = 5000; /* default for non-igd platforms */ 2008const static int latency_ns = 3000; /* default for non-igd platforms */
1803 2009
2010static int intel_get_fifo_size(struct drm_device *dev, int plane)
2011{
2012 struct drm_i915_private *dev_priv = dev->dev_private;
2013 uint32_t dsparb = I915_READ(DSPARB);
2014 int size;
2015
2016 if (IS_I9XX(dev)) {
2017 if (plane == 0)
2018 size = dsparb & 0x7f;
2019 else
2020 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2021 (dsparb & 0x7f);
2022 } else if (IS_I85X(dev)) {
2023 if (plane == 0)
2024 size = dsparb & 0x1ff;
2025 else
2026 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2027 (dsparb & 0x1ff);
2028 size >>= 1; /* Convert to cachelines */
2029 } else if (IS_845G(dev)) {
2030 size = dsparb & 0x7f;
2031 size >>= 2; /* Convert to cachelines */
2032 } else {
2033 size = dsparb & 0x7f;
2034 size >>= 1; /* Convert to cachelines */
2035 }
2036
2037 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
2038 size);
2039
2040 return size;
2041}
1804 2042
1805static void i965_update_wm(struct drm_device *dev) 2043static void i965_update_wm(struct drm_device *dev)
1806{ 2044{
@@ -1817,101 +2055,89 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
1817 int planeb_clock, int sr_hdisplay, int pixel_size) 2055 int planeb_clock, int sr_hdisplay, int pixel_size)
1818{ 2056{
1819 struct drm_i915_private *dev_priv = dev->dev_private; 2057 struct drm_i915_private *dev_priv = dev->dev_private;
1820 uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK; 2058 uint32_t fwater_lo;
1821 uint32_t fwater_hi = I915_READ(FW_BLC2) & LM_FIFO_WATERMARK; 2059 uint32_t fwater_hi;
1822 int bsize, asize, cwm, bwm = 1, awm = 1, srwm = 1; 2060 int total_size, cacheline_size, cwm, srwm = 1;
1823 uint32_t dsparb = I915_READ(DSPARB); 2061 int planea_wm, planeb_wm;
1824 int planea_entries, planeb_entries; 2062 struct intel_watermark_params planea_params, planeb_params;
1825 struct intel_watermark_params *wm_params;
1826 unsigned long line_time_us; 2063 unsigned long line_time_us;
1827 int sr_clock, sr_entries = 0; 2064 int sr_clock, sr_entries = 0;
1828 2065
2066 /* Create copies of the base settings for each pipe */
1829 if (IS_I965GM(dev) || IS_I945GM(dev)) 2067 if (IS_I965GM(dev) || IS_I945GM(dev))
1830 wm_params = &i945_wm_info; 2068 planea_params = planeb_params = i945_wm_info;
1831 else if (IS_I9XX(dev)) 2069 else if (IS_I9XX(dev))
1832 wm_params = &i915_wm_info; 2070 planea_params = planeb_params = i915_wm_info;
1833 else 2071 else
1834 wm_params = &i855_wm_info; 2072 planea_params = planeb_params = i855_wm_info;
1835
1836 planea_entries = intel_calculate_wm(planea_clock, wm_params,
1837 pixel_size, latency_ns);
1838 planeb_entries = intel_calculate_wm(planeb_clock, wm_params,
1839 pixel_size, latency_ns);
1840
1841 DRM_DEBUG("FIFO entries - A: %d, B: %d\n", planea_entries,
1842 planeb_entries);
1843 2073
1844 if (IS_I9XX(dev)) { 2074 /* Grab a couple of global values before we overwrite them */
1845 asize = dsparb & 0x7f; 2075 total_size = planea_params.fifo_size;
1846 bsize = (dsparb >> DSPARB_CSTART_SHIFT) & 0x7f; 2076 cacheline_size = planea_params.cacheline_size;
1847 } else {
1848 asize = dsparb & 0x1ff;
1849 bsize = (dsparb >> DSPARB_BEND_SHIFT) & 0x1ff;
1850 }
1851 DRM_DEBUG("FIFO size - A: %d, B: %d\n", asize, bsize);
1852 2077
1853 /* Two extra entries for padding */ 2078 /* Update per-plane FIFO sizes */
1854 awm = asize - (planea_entries + 2); 2079 planea_params.fifo_size = intel_get_fifo_size(dev, 0);
1855 bwm = bsize - (planeb_entries + 2); 2080 planeb_params.fifo_size = intel_get_fifo_size(dev, 1);
1856 2081
1857 /* Sanity check against potentially bad FIFO allocations */ 2082 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
1858 if (awm <= 0) { 2083 pixel_size, latency_ns);
1859 /* pipe is on but has too few FIFO entries */ 2084 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
1860 if (planea_entries != 0) 2085 pixel_size, latency_ns);
1861 DRM_DEBUG("plane A needs more FIFO entries\n"); 2086 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1862 awm = 1;
1863 }
1864 if (bwm <= 0) {
1865 if (planeb_entries != 0)
1866 DRM_DEBUG("plane B needs more FIFO entries\n");
1867 bwm = 1;
1868 }
1869 2087
1870 /* 2088 /*
1871 * Overlay gets an aggressive default since video jitter is bad. 2089 * Overlay gets an aggressive default since video jitter is bad.
1872 */ 2090 */
1873 cwm = 2; 2091 cwm = 2;
1874 2092
1875 /* Calc sr entries for one pipe configs */ 2093 /* Calc sr entries for one plane configs */
1876 if (!planea_clock || !planeb_clock) { 2094 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2095 /* self-refresh has much higher latency */
2096 const static int sr_latency_ns = 6000;
2097
1877 sr_clock = planea_clock ? planea_clock : planeb_clock; 2098 sr_clock = planea_clock ? planea_clock : planeb_clock;
1878 line_time_us = (sr_hdisplay * 1000) / sr_clock; 2099 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
1879 sr_entries = (((latency_ns / line_time_us) + 1) * pixel_size * 2100
1880 sr_hdisplay) / 1000; 2101 /* Use ns/us then divide to preserve precision */
1881 sr_entries = roundup(sr_entries / wm_params->cacheline_size, 1); 2102 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
1882 if (sr_entries < wm_params->fifo_size) 2103 pixel_size * sr_hdisplay) / 1000;
1883 srwm = wm_params->fifo_size - sr_entries; 2104 sr_entries = roundup(sr_entries / cacheline_size, 1);
2105 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2106 srwm = total_size - sr_entries;
2107 if (srwm < 0)
2108 srwm = 1;
2109 if (IS_I9XX(dev))
2110 I915_WRITE(FW_BLC_SELF, (srwm & 0x3f));
1884 } 2111 }
1885 2112
1886 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 2113 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1887 awm, bwm, cwm, srwm); 2114 planea_wm, planeb_wm, cwm, srwm);
1888 2115
1889 fwater_lo = fwater_lo | ((bwm & 0x3f) << 16) | (awm & 0x3f); 2116 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1890 fwater_hi = fwater_hi | (cwm & 0x1f); 2117 fwater_hi = (cwm & 0x1f);
2118
2119 /* Set request length to 8 cachelines per fetch */
2120 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2121 fwater_hi = fwater_hi | (1 << 8);
1891 2122
1892 I915_WRITE(FW_BLC, fwater_lo); 2123 I915_WRITE(FW_BLC, fwater_lo);
1893 I915_WRITE(FW_BLC2, fwater_hi); 2124 I915_WRITE(FW_BLC2, fwater_hi);
1894 if (IS_I9XX(dev))
1895 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
1896} 2125}
1897 2126
1898static void i830_update_wm(struct drm_device *dev, int planea_clock, 2127static void i830_update_wm(struct drm_device *dev, int planea_clock,
1899 int pixel_size) 2128 int pixel_size)
1900{ 2129{
1901 struct drm_i915_private *dev_priv = dev->dev_private; 2130 struct drm_i915_private *dev_priv = dev->dev_private;
1902 uint32_t dsparb = I915_READ(DSPARB); 2131 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1903 uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK; 2132 int planea_wm;
1904 unsigned int asize, awm;
1905 int planea_entries;
1906
1907 planea_entries = intel_calculate_wm(planea_clock, &i830_wm_info,
1908 pixel_size, latency_ns);
1909 2133
1910 asize = dsparb & 0x7f; 2134 i830_wm_info.fifo_size = intel_get_fifo_size(dev, 0);
1911 2135
1912 awm = asize - planea_entries; 2136 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2137 pixel_size, latency_ns);
2138 fwater_lo |= (3<<8) | planea_wm;
1913 2139
1914 fwater_lo = fwater_lo | awm; 2140 DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
1915 2141
1916 I915_WRITE(FW_BLC, fwater_lo); 2142 I915_WRITE(FW_BLC, fwater_lo);
1917} 2143}
@@ -1984,7 +2210,7 @@ static void intel_update_watermarks(struct drm_device *dev)
1984 if (enabled <= 0) 2210 if (enabled <= 0)
1985 return; 2211 return;
1986 2212
1987 /* Single pipe configs can enable self refresh */ 2213 /* Single plane configs can enable self refresh */
1988 if (enabled == 1 && IS_IGD(dev)) 2214 if (enabled == 1 && IS_IGD(dev))
1989 igd_enable_cxsr(dev, sr_clock, pixel_size); 2215 igd_enable_cxsr(dev, sr_clock, pixel_size);
1990 else if (IS_IGD(dev)) 2216 else if (IS_IGD(dev))
@@ -2028,6 +2254,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2028 u32 dpll = 0, fp = 0, dspcntr, pipeconf; 2254 u32 dpll = 0, fp = 0, dspcntr, pipeconf;
2029 bool ok, is_sdvo = false, is_dvo = false; 2255 bool ok, is_sdvo = false, is_dvo = false;
2030 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; 2256 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2257 bool is_edp = false;
2031 struct drm_mode_config *mode_config = &dev->mode_config; 2258 struct drm_mode_config *mode_config = &dev->mode_config;
2032 struct drm_connector *connector; 2259 struct drm_connector *connector;
2033 const intel_limit_t *limit; 2260 const intel_limit_t *limit;
@@ -2043,6 +2270,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2043 int lvds_reg = LVDS; 2270 int lvds_reg = LVDS;
2044 u32 temp; 2271 u32 temp;
2045 int sdvo_pixel_multiply; 2272 int sdvo_pixel_multiply;
2273 int target_clock;
2046 2274
2047 drm_vblank_pre_modeset(dev, pipe); 2275 drm_vblank_pre_modeset(dev, pipe);
2048 2276
@@ -2074,6 +2302,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2074 case INTEL_OUTPUT_DISPLAYPORT: 2302 case INTEL_OUTPUT_DISPLAYPORT:
2075 is_dp = true; 2303 is_dp = true;
2076 break; 2304 break;
2305 case INTEL_OUTPUT_EDP:
2306 is_edp = true;
2307 break;
2077 } 2308 }
2078 2309
2079 num_outputs++; 2310 num_outputs++;
@@ -2125,11 +2356,29 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2125 } 2356 }
2126 2357
2127 /* FDI link */ 2358 /* FDI link */
2128 if (IS_IGDNG(dev)) 2359 if (IS_IGDNG(dev)) {
2129 igdng_compute_m_n(3, 4, /* lane num 4 */ 2360 int lane, link_bw;
2130 adjusted_mode->clock, 2361 /* eDP doesn't require FDI link, so just set DP M/N
2131 270000, /* lane clock */ 2362 according to current link config */
2132 &m_n); 2363 if (is_edp) {
2364 struct drm_connector *edp;
2365 target_clock = mode->clock;
2366 edp = intel_pipe_get_output(crtc);
2367 intel_edp_link_config(to_intel_output(edp),
2368 &lane, &link_bw);
2369 } else {
2370 /* DP over FDI requires target mode clock
2371 instead of link clock */
2372 if (is_dp)
2373 target_clock = mode->clock;
2374 else
2375 target_clock = adjusted_mode->clock;
2376 lane = 4;
2377 link_bw = 270000;
2378 }
2379 igdng_compute_m_n(3, lane, target_clock,
2380 link_bw, &m_n);
2381 }
2133 2382
2134 if (IS_IGD(dev)) 2383 if (IS_IGD(dev))
2135 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; 2384 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
@@ -2250,29 +2499,15 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2250 dpll_reg = pch_dpll_reg; 2499 dpll_reg = pch_dpll_reg;
2251 } 2500 }
2252 2501
2253 if (dpll & DPLL_VCO_ENABLE) { 2502 if (is_edp) {
2503 igdng_disable_pll_edp(crtc);
2504 } else if ((dpll & DPLL_VCO_ENABLE)) {
2254 I915_WRITE(fp_reg, fp); 2505 I915_WRITE(fp_reg, fp);
2255 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); 2506 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
2256 I915_READ(dpll_reg); 2507 I915_READ(dpll_reg);
2257 udelay(150); 2508 udelay(150);
2258 } 2509 }
2259 2510
2260 if (IS_IGDNG(dev)) {
2261 /* enable PCH clock reference source */
2262 /* XXX need to change the setting for other outputs */
2263 u32 temp;
2264 temp = I915_READ(PCH_DREF_CONTROL);
2265 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2266 temp |= DREF_NONSPREAD_CK505_ENABLE;
2267 temp &= ~DREF_SSC_SOURCE_MASK;
2268 temp |= DREF_SSC_SOURCE_ENABLE;
2269 temp &= ~DREF_SSC1_ENABLE;
2270 /* if no eDP, disable source output to CPU */
2271 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2272 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2273 I915_WRITE(PCH_DREF_CONTROL, temp);
2274 }
2275
2276 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 2511 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
2277 * This is an exception to the general rule that mode_set doesn't turn 2512 * This is an exception to the general rule that mode_set doesn't turn
2278 * things on. 2513 * things on.
@@ -2304,23 +2539,25 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2304 if (is_dp) 2539 if (is_dp)
2305 intel_dp_set_m_n(crtc, mode, adjusted_mode); 2540 intel_dp_set_m_n(crtc, mode, adjusted_mode);
2306 2541
2307 I915_WRITE(fp_reg, fp); 2542 if (!is_edp) {
2308 I915_WRITE(dpll_reg, dpll); 2543 I915_WRITE(fp_reg, fp);
2309 I915_READ(dpll_reg);
2310 /* Wait for the clocks to stabilize. */
2311 udelay(150);
2312
2313 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
2314 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2315 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
2316 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
2317 } else {
2318 /* write it again -- the BIOS does, after all */
2319 I915_WRITE(dpll_reg, dpll); 2544 I915_WRITE(dpll_reg, dpll);
2545 I915_READ(dpll_reg);
2546 /* Wait for the clocks to stabilize. */
2547 udelay(150);
2548
2549 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
2550 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2551 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
2552 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
2553 } else {
2554 /* write it again -- the BIOS does, after all */
2555 I915_WRITE(dpll_reg, dpll);
2556 }
2557 I915_READ(dpll_reg);
2558 /* Wait for the clocks to stabilize. */
2559 udelay(150);
2320 } 2560 }
2321 I915_READ(dpll_reg);
2322 /* Wait for the clocks to stabilize. */
2323 udelay(150);
2324 2561
2325 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | 2562 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
2326 ((adjusted_mode->crtc_htotal - 1) << 16)); 2563 ((adjusted_mode->crtc_htotal - 1) << 16));
@@ -2350,10 +2587,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2350 I915_WRITE(link_m1_reg, m_n.link_m); 2587 I915_WRITE(link_m1_reg, m_n.link_m);
2351 I915_WRITE(link_n1_reg, m_n.link_n); 2588 I915_WRITE(link_n1_reg, m_n.link_n);
2352 2589
2353 /* enable FDI RX PLL too */ 2590 if (is_edp) {
2354 temp = I915_READ(fdi_rx_reg); 2591 igdng_set_pll_edp(crtc, adjusted_mode->clock);
2355 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE); 2592 } else {
2356 udelay(200); 2593 /* enable FDI RX PLL too */
2594 temp = I915_READ(fdi_rx_reg);
2595 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
2596 udelay(200);
2597 }
2357 } 2598 }
2358 2599
2359 I915_WRITE(pipeconf_reg, pipeconf); 2600 I915_WRITE(pipeconf_reg, pipeconf);
@@ -2951,12 +3192,17 @@ static void intel_setup_outputs(struct drm_device *dev)
2951 if (IS_IGDNG(dev)) { 3192 if (IS_IGDNG(dev)) {
2952 int found; 3193 int found;
2953 3194
3195 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
3196 intel_dp_init(dev, DP_A);
3197
2954 if (I915_READ(HDMIB) & PORT_DETECTED) { 3198 if (I915_READ(HDMIB) & PORT_DETECTED) {
2955 /* check SDVOB */ 3199 /* check SDVOB */
2956 /* found = intel_sdvo_init(dev, HDMIB); */ 3200 /* found = intel_sdvo_init(dev, HDMIB); */
2957 found = 0; 3201 found = 0;
2958 if (!found) 3202 if (!found)
2959 intel_hdmi_init(dev, HDMIB); 3203 intel_hdmi_init(dev, HDMIB);
3204 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
3205 intel_dp_init(dev, PCH_DP_B);
2960 } 3206 }
2961 3207
2962 if (I915_READ(HDMIC) & PORT_DETECTED) 3208 if (I915_READ(HDMIC) & PORT_DETECTED)
@@ -2965,6 +3211,12 @@ static void intel_setup_outputs(struct drm_device *dev)
2965 if (I915_READ(HDMID) & PORT_DETECTED) 3211 if (I915_READ(HDMID) & PORT_DETECTED)
2966 intel_hdmi_init(dev, HDMID); 3212 intel_hdmi_init(dev, HDMID);
2967 3213
3214 if (I915_READ(PCH_DP_C) & DP_DETECTED)
3215 intel_dp_init(dev, PCH_DP_C);
3216
3217 if (I915_READ(PCH_DP_D) & DP_DETECTED)
3218 intel_dp_init(dev, PCH_DP_D);
3219
2968 } else if (IS_I9XX(dev)) { 3220 } else if (IS_I9XX(dev)) {
2969 int found; 3221 int found;
2970 u32 reg; 3222 u32 reg;
@@ -3039,6 +3291,10 @@ static void intel_setup_outputs(struct drm_device *dev)
3039 (1 << 1)); 3291 (1 << 1));
3040 clone_mask = (1 << INTEL_OUTPUT_DISPLAYPORT); 3292 clone_mask = (1 << INTEL_OUTPUT_DISPLAYPORT);
3041 break; 3293 break;
3294 case INTEL_OUTPUT_EDP:
3295 crtc_mask = (1 << 1);
3296 clone_mask = (1 << INTEL_OUTPUT_EDP);
3297 break;
3042 } 3298 }
3043 encoder->possible_crtcs = crtc_mask; 3299 encoder->possible_crtcs = crtc_mask;
3044 encoder->possible_clones = intel_connector_clones(dev, clone_mask); 3300 encoder->possible_clones = intel_connector_clones(dev, clone_mask);
@@ -3148,6 +3404,9 @@ void intel_modeset_init(struct drm_device *dev)
3148 if (IS_I965G(dev)) { 3404 if (IS_I965G(dev)) {
3149 dev->mode_config.max_width = 8192; 3405 dev->mode_config.max_width = 8192;
3150 dev->mode_config.max_height = 8192; 3406 dev->mode_config.max_height = 8192;
3407 } else if (IS_I9XX(dev)) {
3408 dev->mode_config.max_width = 4096;
3409 dev->mode_config.max_height = 4096;
3151 } else { 3410 } else {
3152 dev->mode_config.max_width = 2048; 3411 dev->mode_config.max_width = 2048;
3153 dev->mode_config.max_height = 2048; 3412 dev->mode_config.max_height = 2048;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6770ae88370d..a6ff15ac548a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -40,6 +40,8 @@
40 40
41#define DP_LINK_CONFIGURATION_SIZE 9 41#define DP_LINK_CONFIGURATION_SIZE 9
42 42
43#define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
44
43struct intel_dp_priv { 45struct intel_dp_priv {
44 uint32_t output_reg; 46 uint32_t output_reg;
45 uint32_t DP; 47 uint32_t DP;
@@ -63,6 +65,19 @@ intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
63static void 65static void
64intel_dp_link_down(struct intel_output *intel_output, uint32_t DP); 66intel_dp_link_down(struct intel_output *intel_output, uint32_t DP);
65 67
68void
69intel_edp_link_config (struct intel_output *intel_output,
70 int *lane_num, int *link_bw)
71{
72 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
73
74 *lane_num = dp_priv->lane_count;
75 if (dp_priv->link_bw == DP_LINK_BW_1_62)
76 *link_bw = 162000;
77 else if (dp_priv->link_bw == DP_LINK_BW_2_7)
78 *link_bw = 270000;
79}
80
66static int 81static int
67intel_dp_max_lane_count(struct intel_output *intel_output) 82intel_dp_max_lane_count(struct intel_output *intel_output)
68{ 83{
@@ -206,7 +221,13 @@ intel_dp_aux_ch(struct intel_output *intel_output,
206 * and would like to run at 2MHz. So, take the 221 * and would like to run at 2MHz. So, take the
207 * hrawclk value and divide by 2 and use that 222 * hrawclk value and divide by 2 and use that
208 */ 223 */
209 aux_clock_divider = intel_hrawclk(dev) / 2; 224 if (IS_eDP(intel_output))
225 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
226 else if (IS_IGDNG(dev))
227 aux_clock_divider = 62; /* IGDNG: input clock fixed at 125Mhz */
228 else
229 aux_clock_divider = intel_hrawclk(dev) / 2;
230
210 /* Must try at least 3 times according to DP spec */ 231 /* Must try at least 3 times according to DP spec */
211 for (try = 0; try < 5; try++) { 232 for (try = 0; try < 5; try++) {
212 /* Load the send data into the aux channel data registers */ 233 /* Load the send data into the aux channel data registers */
@@ -236,7 +257,7 @@ intel_dp_aux_ch(struct intel_output *intel_output,
236 } 257 }
237 258
238 /* Clear done status and any errors */ 259 /* Clear done status and any errors */
239 I915_WRITE(ch_ctl, (ctl | 260 I915_WRITE(ch_ctl, (status |
240 DP_AUX_CH_CTL_DONE | 261 DP_AUX_CH_CTL_DONE |
241 DP_AUX_CH_CTL_TIME_OUT_ERROR | 262 DP_AUX_CH_CTL_TIME_OUT_ERROR |
242 DP_AUX_CH_CTL_RECEIVE_ERROR)); 263 DP_AUX_CH_CTL_RECEIVE_ERROR));
@@ -295,7 +316,7 @@ intel_dp_aux_native_write(struct intel_output *intel_output,
295 return -1; 316 return -1;
296 msg[0] = AUX_NATIVE_WRITE << 4; 317 msg[0] = AUX_NATIVE_WRITE << 4;
297 msg[1] = address >> 8; 318 msg[1] = address >> 8;
298 msg[2] = address; 319 msg[2] = address & 0xff;
299 msg[3] = send_bytes - 1; 320 msg[3] = send_bytes - 1;
300 memcpy(&msg[4], send, send_bytes); 321 memcpy(&msg[4], send, send_bytes);
301 msg_bytes = send_bytes + 4; 322 msg_bytes = send_bytes + 4;
@@ -387,8 +408,8 @@ intel_dp_i2c_init(struct intel_output *intel_output, const char *name)
387 memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter)); 408 memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
388 dp_priv->adapter.owner = THIS_MODULE; 409 dp_priv->adapter.owner = THIS_MODULE;
389 dp_priv->adapter.class = I2C_CLASS_DDC; 410 dp_priv->adapter.class = I2C_CLASS_DDC;
390 strncpy (dp_priv->adapter.name, name, sizeof dp_priv->adapter.name - 1); 411 strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
391 dp_priv->adapter.name[sizeof dp_priv->adapter.name - 1] = '\0'; 412 dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
392 dp_priv->adapter.algo_data = &dp_priv->algo; 413 dp_priv->adapter.algo_data = &dp_priv->algo;
393 dp_priv->adapter.dev.parent = &intel_output->base.kdev; 414 dp_priv->adapter.dev.parent = &intel_output->base.kdev;
394 415
@@ -493,22 +514,40 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
493 intel_dp_compute_m_n(3, lane_count, 514 intel_dp_compute_m_n(3, lane_count,
494 mode->clock, adjusted_mode->clock, &m_n); 515 mode->clock, adjusted_mode->clock, &m_n);
495 516
496 if (intel_crtc->pipe == 0) { 517 if (IS_IGDNG(dev)) {
497 I915_WRITE(PIPEA_GMCH_DATA_M, 518 if (intel_crtc->pipe == 0) {
498 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 519 I915_WRITE(TRANSA_DATA_M1,
499 m_n.gmch_m); 520 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
500 I915_WRITE(PIPEA_GMCH_DATA_N, 521 m_n.gmch_m);
501 m_n.gmch_n); 522 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
502 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m); 523 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
503 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n); 524 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
525 } else {
526 I915_WRITE(TRANSB_DATA_M1,
527 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
528 m_n.gmch_m);
529 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
530 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
531 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
532 }
504 } else { 533 } else {
505 I915_WRITE(PIPEB_GMCH_DATA_M, 534 if (intel_crtc->pipe == 0) {
506 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 535 I915_WRITE(PIPEA_GMCH_DATA_M,
507 m_n.gmch_m); 536 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
508 I915_WRITE(PIPEB_GMCH_DATA_N, 537 m_n.gmch_m);
509 m_n.gmch_n); 538 I915_WRITE(PIPEA_GMCH_DATA_N,
510 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m); 539 m_n.gmch_n);
511 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n); 540 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
541 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
542 } else {
543 I915_WRITE(PIPEB_GMCH_DATA_M,
544 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
545 m_n.gmch_m);
546 I915_WRITE(PIPEB_GMCH_DATA_N,
547 m_n.gmch_n);
548 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
549 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
550 }
512 } 551 }
513} 552}
514 553
@@ -556,8 +595,38 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
556 595
557 if (intel_crtc->pipe == 1) 596 if (intel_crtc->pipe == 1)
558 dp_priv->DP |= DP_PIPEB_SELECT; 597 dp_priv->DP |= DP_PIPEB_SELECT;
598
599 if (IS_eDP(intel_output)) {
600 /* don't miss out required setting for eDP */
601 dp_priv->DP |= DP_PLL_ENABLE;
602 if (adjusted_mode->clock < 200000)
603 dp_priv->DP |= DP_PLL_FREQ_160MHZ;
604 else
605 dp_priv->DP |= DP_PLL_FREQ_270MHZ;
606 }
559} 607}
560 608
609static void igdng_edp_backlight_on (struct drm_device *dev)
610{
611 struct drm_i915_private *dev_priv = dev->dev_private;
612 u32 pp;
613
614 DRM_DEBUG("\n");
615 pp = I915_READ(PCH_PP_CONTROL);
616 pp |= EDP_BLC_ENABLE;
617 I915_WRITE(PCH_PP_CONTROL, pp);
618}
619
620static void igdng_edp_backlight_off (struct drm_device *dev)
621{
622 struct drm_i915_private *dev_priv = dev->dev_private;
623 u32 pp;
624
625 DRM_DEBUG("\n");
626 pp = I915_READ(PCH_PP_CONTROL);
627 pp &= ~EDP_BLC_ENABLE;
628 I915_WRITE(PCH_PP_CONTROL, pp);
629}
561 630
562static void 631static void
563intel_dp_dpms(struct drm_encoder *encoder, int mode) 632intel_dp_dpms(struct drm_encoder *encoder, int mode)
@@ -569,11 +638,17 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
569 uint32_t dp_reg = I915_READ(dp_priv->output_reg); 638 uint32_t dp_reg = I915_READ(dp_priv->output_reg);
570 639
571 if (mode != DRM_MODE_DPMS_ON) { 640 if (mode != DRM_MODE_DPMS_ON) {
572 if (dp_reg & DP_PORT_EN) 641 if (dp_reg & DP_PORT_EN) {
573 intel_dp_link_down(intel_output, dp_priv->DP); 642 intel_dp_link_down(intel_output, dp_priv->DP);
643 if (IS_eDP(intel_output))
644 igdng_edp_backlight_off(dev);
645 }
574 } else { 646 } else {
575 if (!(dp_reg & DP_PORT_EN)) 647 if (!(dp_reg & DP_PORT_EN)) {
576 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration); 648 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
649 if (IS_eDP(intel_output))
650 igdng_edp_backlight_on(dev);
651 }
577 } 652 }
578 dp_priv->dpms_mode = mode; 653 dp_priv->dpms_mode = mode;
579} 654}
@@ -935,6 +1010,23 @@ intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
935 struct drm_i915_private *dev_priv = dev->dev_private; 1010 struct drm_i915_private *dev_priv = dev->dev_private;
936 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 1011 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
937 1012
1013 DRM_DEBUG("\n");
1014
1015 if (IS_eDP(intel_output)) {
1016 DP &= ~DP_PLL_ENABLE;
1017 I915_WRITE(dp_priv->output_reg, DP);
1018 POSTING_READ(dp_priv->output_reg);
1019 udelay(100);
1020 }
1021
1022 DP &= ~DP_LINK_TRAIN_MASK;
1023 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1024 POSTING_READ(dp_priv->output_reg);
1025
1026 udelay(17000);
1027
1028 if (IS_eDP(intel_output))
1029 DP |= DP_LINK_TRAIN_OFF;
938 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN); 1030 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
939 POSTING_READ(dp_priv->output_reg); 1031 POSTING_READ(dp_priv->output_reg);
940} 1032}
@@ -978,6 +1070,24 @@ intel_dp_check_link_status(struct intel_output *intel_output)
978 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration); 1070 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
979} 1071}
980 1072
1073static enum drm_connector_status
1074igdng_dp_detect(struct drm_connector *connector)
1075{
1076 struct intel_output *intel_output = to_intel_output(connector);
1077 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1078 enum drm_connector_status status;
1079
1080 status = connector_status_disconnected;
1081 if (intel_dp_aux_native_read(intel_output,
1082 0x000, dp_priv->dpcd,
1083 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1084 {
1085 if (dp_priv->dpcd[0] != 0)
1086 status = connector_status_connected;
1087 }
1088 return status;
1089}
1090
981/** 1091/**
982 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. 1092 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
983 * 1093 *
@@ -996,6 +1106,9 @@ intel_dp_detect(struct drm_connector *connector)
996 1106
997 dp_priv->has_audio = false; 1107 dp_priv->has_audio = false;
998 1108
1109 if (IS_IGDNG(dev))
1110 return igdng_dp_detect(connector);
1111
999 temp = I915_READ(PORT_HOTPLUG_EN); 1112 temp = I915_READ(PORT_HOTPLUG_EN);
1000 1113
1001 I915_WRITE(PORT_HOTPLUG_EN, 1114 I915_WRITE(PORT_HOTPLUG_EN,
@@ -1039,11 +1152,27 @@ intel_dp_detect(struct drm_connector *connector)
1039static int intel_dp_get_modes(struct drm_connector *connector) 1152static int intel_dp_get_modes(struct drm_connector *connector)
1040{ 1153{
1041 struct intel_output *intel_output = to_intel_output(connector); 1154 struct intel_output *intel_output = to_intel_output(connector);
1155 struct drm_device *dev = intel_output->base.dev;
1156 struct drm_i915_private *dev_priv = dev->dev_private;
1157 int ret;
1042 1158
1043 /* We should parse the EDID data and find out if it has an audio sink 1159 /* We should parse the EDID data and find out if it has an audio sink
1044 */ 1160 */
1045 1161
1046 return intel_ddc_get_modes(intel_output); 1162 ret = intel_ddc_get_modes(intel_output);
1163 if (ret)
1164 return ret;
1165
1166 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1167 if (IS_eDP(intel_output)) {
1168 if (dev_priv->panel_fixed_mode != NULL) {
1169 struct drm_display_mode *mode;
1170 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1171 drm_mode_probed_add(connector, mode);
1172 return 1;
1173 }
1174 }
1175 return 0;
1047} 1176}
1048 1177
1049static void 1178static void
@@ -1106,6 +1235,7 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1106 struct drm_connector *connector; 1235 struct drm_connector *connector;
1107 struct intel_output *intel_output; 1236 struct intel_output *intel_output;
1108 struct intel_dp_priv *dp_priv; 1237 struct intel_dp_priv *dp_priv;
1238 const char *name = NULL;
1109 1239
1110 intel_output = kcalloc(sizeof(struct intel_output) + 1240 intel_output = kcalloc(sizeof(struct intel_output) +
1111 sizeof(struct intel_dp_priv), 1, GFP_KERNEL); 1241 sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
@@ -1119,7 +1249,10 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1119 DRM_MODE_CONNECTOR_DisplayPort); 1249 DRM_MODE_CONNECTOR_DisplayPort);
1120 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 1250 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1121 1251
1122 intel_output->type = INTEL_OUTPUT_DISPLAYPORT; 1252 if (output_reg == DP_A)
1253 intel_output->type = INTEL_OUTPUT_EDP;
1254 else
1255 intel_output->type = INTEL_OUTPUT_DISPLAYPORT;
1123 1256
1124 connector->interlace_allowed = true; 1257 connector->interlace_allowed = true;
1125 connector->doublescan_allowed = 0; 1258 connector->doublescan_allowed = 0;
@@ -1139,12 +1272,41 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1139 drm_sysfs_connector_add(connector); 1272 drm_sysfs_connector_add(connector);
1140 1273
1141 /* Set up the DDC bus. */ 1274 /* Set up the DDC bus. */
1142 intel_dp_i2c_init(intel_output, 1275 switch (output_reg) {
1143 (output_reg == DP_B) ? "DPDDC-B" : 1276 case DP_A:
1144 (output_reg == DP_C) ? "DPDDC-C" : "DPDDC-D"); 1277 name = "DPDDC-A";
1278 break;
1279 case DP_B:
1280 case PCH_DP_B:
1281 name = "DPDDC-B";
1282 break;
1283 case DP_C:
1284 case PCH_DP_C:
1285 name = "DPDDC-C";
1286 break;
1287 case DP_D:
1288 case PCH_DP_D:
1289 name = "DPDDC-D";
1290 break;
1291 }
1292
1293 intel_dp_i2c_init(intel_output, name);
1294
1145 intel_output->ddc_bus = &dp_priv->adapter; 1295 intel_output->ddc_bus = &dp_priv->adapter;
1146 intel_output->hot_plug = intel_dp_hot_plug; 1296 intel_output->hot_plug = intel_dp_hot_plug;
1147 1297
1298 if (output_reg == DP_A) {
1299 /* initialize panel mode from VBT if available for eDP */
1300 if (dev_priv->lfp_lvds_vbt_mode) {
1301 dev_priv->panel_fixed_mode =
1302 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1303 if (dev_priv->panel_fixed_mode) {
1304 dev_priv->panel_fixed_mode->type |=
1305 DRM_MODE_TYPE_PREFERRED;
1306 }
1307 }
1308 }
1309
1148 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 1310 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1149 * 0xd. Failure to do so will result in spurious interrupts being 1311 * 0xd. Failure to do so will result in spurious interrupts being
1150 * generated on the port when a cable is not attached. 1312 * generated on the port when a cable is not attached.
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 004541c935a8..d6f92ea1b553 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -55,6 +55,7 @@
55#define INTEL_OUTPUT_TVOUT 5 55#define INTEL_OUTPUT_TVOUT 5
56#define INTEL_OUTPUT_HDMI 6 56#define INTEL_OUTPUT_HDMI 6
57#define INTEL_OUTPUT_DISPLAYPORT 7 57#define INTEL_OUTPUT_DISPLAYPORT 7
58#define INTEL_OUTPUT_EDP 8
58 59
59#define INTEL_DVO_CHIP_NONE 0 60#define INTEL_DVO_CHIP_NONE 0
60#define INTEL_DVO_CHIP_LVDS 1 61#define INTEL_DVO_CHIP_LVDS 1
@@ -121,6 +122,8 @@ extern void intel_dp_init(struct drm_device *dev, int dp_reg);
121void 122void
122intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 123intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
123 struct drm_display_mode *adjusted_mode); 124 struct drm_display_mode *adjusted_mode);
125extern void intel_edp_link_config (struct intel_output *, int *, int *);
126
124 127
125extern void intel_crtc_load_lut(struct drm_crtc *crtc); 128extern void intel_crtc_load_lut(struct drm_crtc *crtc);
126extern void intel_encoder_prepare (struct drm_encoder *encoder); 129extern void intel_encoder_prepare (struct drm_encoder *encoder);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 9e30daae37dc..1842290cded3 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -130,16 +130,17 @@ static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
130} 130}
131 131
132static enum drm_connector_status 132static enum drm_connector_status
133intel_hdmi_edid_detect(struct drm_connector *connector) 133intel_hdmi_detect(struct drm_connector *connector)
134{ 134{
135 struct intel_output *intel_output = to_intel_output(connector); 135 struct intel_output *intel_output = to_intel_output(connector);
136 struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv; 136 struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv;
137 struct edid *edid = NULL; 137 struct edid *edid = NULL;
138 enum drm_connector_status status = connector_status_disconnected; 138 enum drm_connector_status status = connector_status_disconnected;
139 139
140 hdmi_priv->has_hdmi_sink = false;
140 edid = drm_get_edid(&intel_output->base, 141 edid = drm_get_edid(&intel_output->base,
141 intel_output->ddc_bus); 142 intel_output->ddc_bus);
142 hdmi_priv->has_hdmi_sink = false; 143
143 if (edid) { 144 if (edid) {
144 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 145 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
145 status = connector_status_connected; 146 status = connector_status_connected;
@@ -148,65 +149,8 @@ intel_hdmi_edid_detect(struct drm_connector *connector)
148 intel_output->base.display_info.raw_edid = NULL; 149 intel_output->base.display_info.raw_edid = NULL;
149 kfree(edid); 150 kfree(edid);
150 } 151 }
151 return status;
152}
153
154static enum drm_connector_status
155igdng_hdmi_detect(struct drm_connector *connector)
156{
157 struct intel_output *intel_output = to_intel_output(connector);
158 struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv;
159
160 /* FIXME hotplug detect */
161
162 hdmi_priv->has_hdmi_sink = false;
163 return intel_hdmi_edid_detect(connector);
164}
165 152
166static enum drm_connector_status 153 return status;
167intel_hdmi_detect(struct drm_connector *connector)
168{
169 struct drm_device *dev = connector->dev;
170 struct drm_i915_private *dev_priv = dev->dev_private;
171 struct intel_output *intel_output = to_intel_output(connector);
172 struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv;
173 u32 temp, bit;
174
175 if (IS_IGDNG(dev))
176 return igdng_hdmi_detect(connector);
177
178 temp = I915_READ(PORT_HOTPLUG_EN);
179
180 switch (hdmi_priv->sdvox_reg) {
181 case SDVOB:
182 temp |= HDMIB_HOTPLUG_INT_EN;
183 break;
184 case SDVOC:
185 temp |= HDMIC_HOTPLUG_INT_EN;
186 break;
187 default:
188 return connector_status_unknown;
189 }
190
191 I915_WRITE(PORT_HOTPLUG_EN, temp);
192
193 POSTING_READ(PORT_HOTPLUG_EN);
194
195 switch (hdmi_priv->sdvox_reg) {
196 case SDVOB:
197 bit = HDMIB_HOTPLUG_INT_STATUS;
198 break;
199 case SDVOC:
200 bit = HDMIC_HOTPLUG_INT_STATUS;
201 break;
202 default:
203 return connector_status_unknown;
204 }
205
206 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) != 0)
207 return intel_hdmi_edid_detect(connector);
208 else
209 return connector_status_disconnected;
210} 154}
211 155
212static int intel_hdmi_get_modes(struct drm_connector *connector) 156static int intel_hdmi_get_modes(struct drm_connector *connector)
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 9ab38efffecf..3f445a80c552 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -780,6 +780,14 @@ static const struct dmi_system_id intel_no_lvds[] = {
780 }, 780 },
781 { 781 {
782 .callback = intel_no_lvds_dmi_callback, 782 .callback = intel_no_lvds_dmi_callback,
783 .ident = "AOpen Mini PC MP915",
784 .matches = {
785 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
786 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
787 },
788 },
789 {
790 .callback = intel_no_lvds_dmi_callback,
783 .ident = "Aopen i945GTt-VFA", 791 .ident = "Aopen i945GTt-VFA",
784 .matches = { 792 .matches = {
785 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), 793 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
@@ -884,6 +892,10 @@ void intel_lvds_init(struct drm_device *dev)
884 if (IS_IGDNG(dev)) { 892 if (IS_IGDNG(dev)) {
885 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) 893 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
886 return; 894 return;
895 if (dev_priv->edp_support) {
896 DRM_DEBUG("disable LVDS for eDP support\n");
897 return;
898 }
887 gpio = PCH_GPIOC; 899 gpio = PCH_GPIOC;
888 } 900 }
889 901
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 4f0c30948bc4..5371d9332554 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -31,6 +31,7 @@
31#include "drm.h" 31#include "drm.h"
32#include "drm_crtc.h" 32#include "drm_crtc.h"
33#include "intel_drv.h" 33#include "intel_drv.h"
34#include "drm_edid.h"
34#include "i915_drm.h" 35#include "i915_drm.h"
35#include "i915_drv.h" 36#include "i915_drv.h"
36#include "intel_sdvo_regs.h" 37#include "intel_sdvo_regs.h"
@@ -55,6 +56,12 @@ struct intel_sdvo_priv {
55 /* Pixel clock limitations reported by the SDVO device, in kHz */ 56 /* Pixel clock limitations reported by the SDVO device, in kHz */
56 int pixel_clock_min, pixel_clock_max; 57 int pixel_clock_min, pixel_clock_max;
57 58
59 /*
60 * For multiple function SDVO device,
61 * this is for current attached outputs.
62 */
63 uint16_t attached_output;
64
58 /** 65 /**
59 * This is set if we're going to treat the device as TV-out. 66 * This is set if we're going to treat the device as TV-out.
60 * 67 *
@@ -114,6 +121,9 @@ struct intel_sdvo_priv {
114 u32 save_SDVOX; 121 u32 save_SDVOX;
115}; 122};
116 123
124static bool
125intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags);
126
117/** 127/**
118 * Writes the SDVOB or SDVOC with the given value, but always writes both 128 * Writes the SDVOB or SDVOC with the given value, but always writes both
119 * SDVOB and SDVOC to work around apparent hardware issues (according to 129 * SDVOB and SDVOC to work around apparent hardware issues (according to
@@ -1435,41 +1445,96 @@ void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1435 intel_sdvo_read_response(intel_output, &response, 2); 1445 intel_sdvo_read_response(intel_output, &response, 2);
1436} 1446}
1437 1447
1438static void 1448static bool
1439intel_sdvo_hdmi_sink_detect(struct drm_connector *connector) 1449intel_sdvo_multifunc_encoder(struct intel_output *intel_output)
1450{
1451 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1452 int caps = 0;
1453
1454 if (sdvo_priv->caps.output_flags &
1455 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1456 caps++;
1457 if (sdvo_priv->caps.output_flags &
1458 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1459 caps++;
1460 if (sdvo_priv->caps.output_flags &
1461 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID0))
1462 caps++;
1463 if (sdvo_priv->caps.output_flags &
1464 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1465 caps++;
1466 if (sdvo_priv->caps.output_flags &
1467 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1468 caps++;
1469
1470 if (sdvo_priv->caps.output_flags &
1471 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1472 caps++;
1473
1474 if (sdvo_priv->caps.output_flags &
1475 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1476 caps++;
1477
1478 return (caps > 1);
1479}
1480
1481enum drm_connector_status
1482intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
1440{ 1483{
1441 struct intel_output *intel_output = to_intel_output(connector); 1484 struct intel_output *intel_output = to_intel_output(connector);
1442 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 1485 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1486 enum drm_connector_status status = connector_status_connected;
1443 struct edid *edid = NULL; 1487 struct edid *edid = NULL;
1444 1488
1445 edid = drm_get_edid(&intel_output->base, 1489 edid = drm_get_edid(&intel_output->base,
1446 intel_output->ddc_bus); 1490 intel_output->ddc_bus);
1447 if (edid != NULL) { 1491 if (edid != NULL) {
1448 sdvo_priv->is_hdmi = drm_detect_hdmi_monitor(edid); 1492 /* Don't report the output as connected if it's a DVI-I
1493 * connector with a non-digital EDID coming out.
1494 */
1495 if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1496 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1497 sdvo_priv->is_hdmi =
1498 drm_detect_hdmi_monitor(edid);
1499 else
1500 status = connector_status_disconnected;
1501 }
1502
1449 kfree(edid); 1503 kfree(edid);
1450 intel_output->base.display_info.raw_edid = NULL; 1504 intel_output->base.display_info.raw_edid = NULL;
1451 } 1505
1506 } else if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1507 status = connector_status_disconnected;
1508
1509 return status;
1452} 1510}
1453 1511
1454static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector) 1512static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1455{ 1513{
1456 u8 response[2]; 1514 uint16_t response;
1457 u8 status; 1515 u8 status;
1458 struct intel_output *intel_output = to_intel_output(connector); 1516 struct intel_output *intel_output = to_intel_output(connector);
1517 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1459 1518
1460 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0); 1519 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
1461 status = intel_sdvo_read_response(intel_output, &response, 2); 1520 status = intel_sdvo_read_response(intel_output, &response, 2);
1462 1521
1463 DRM_DEBUG("SDVO response %d %d\n", response[0], response[1]); 1522 DRM_DEBUG("SDVO response %d %d\n", response & 0xff, response >> 8);
1464 1523
1465 if (status != SDVO_CMD_STATUS_SUCCESS) 1524 if (status != SDVO_CMD_STATUS_SUCCESS)
1466 return connector_status_unknown; 1525 return connector_status_unknown;
1467 1526
1468 if ((response[0] != 0) || (response[1] != 0)) { 1527 if (response == 0)
1469 intel_sdvo_hdmi_sink_detect(connector);
1470 return connector_status_connected;
1471 } else
1472 return connector_status_disconnected; 1528 return connector_status_disconnected;
1529
1530 if (intel_sdvo_multifunc_encoder(intel_output) &&
1531 sdvo_priv->attached_output != response) {
1532 if (sdvo_priv->controlled_output != response &&
1533 intel_sdvo_output_setup(intel_output, response) != true)
1534 return connector_status_unknown;
1535 sdvo_priv->attached_output = response;
1536 }
1537 return intel_sdvo_hdmi_sink_detect(connector, response);
1473} 1538}
1474 1539
1475static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) 1540static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
@@ -1866,16 +1931,101 @@ intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device)
1866 return 0x72; 1931 return 0x72;
1867} 1932}
1868 1933
1934static bool
1935intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
1936{
1937 struct drm_connector *connector = &intel_output->base;
1938 struct drm_encoder *encoder = &intel_output->enc;
1939 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1940 bool ret = true, registered = false;
1941
1942 sdvo_priv->is_tv = false;
1943 intel_output->needs_tv_clock = false;
1944 sdvo_priv->is_lvds = false;
1945
1946 if (device_is_registered(&connector->kdev)) {
1947 drm_sysfs_connector_remove(connector);
1948 registered = true;
1949 }
1950
1951 if (flags &
1952 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1953 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
1954 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
1955 else
1956 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
1957
1958 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
1959 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
1960
1961 if (intel_sdvo_get_supp_encode(intel_output,
1962 &sdvo_priv->encode) &&
1963 intel_sdvo_get_digital_encoding_mode(intel_output) &&
1964 sdvo_priv->is_hdmi) {
1965 /* enable hdmi encoding mode if supported */
1966 intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
1967 intel_sdvo_set_colorimetry(intel_output,
1968 SDVO_COLORIMETRY_RGB256);
1969 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
1970 }
1971 } else if (flags & SDVO_OUTPUT_SVID0) {
1972
1973 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
1974 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
1975 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
1976 sdvo_priv->is_tv = true;
1977 intel_output->needs_tv_clock = true;
1978 } else if (flags & SDVO_OUTPUT_RGB0) {
1979
1980 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
1981 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
1982 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
1983 } else if (flags & SDVO_OUTPUT_RGB1) {
1984
1985 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
1986 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
1987 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
1988 } else if (flags & SDVO_OUTPUT_LVDS0) {
1989
1990 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
1991 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
1992 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
1993 sdvo_priv->is_lvds = true;
1994 } else if (flags & SDVO_OUTPUT_LVDS1) {
1995
1996 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
1997 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
1998 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
1999 sdvo_priv->is_lvds = true;
2000 } else {
2001
2002 unsigned char bytes[2];
2003
2004 sdvo_priv->controlled_output = 0;
2005 memcpy(bytes, &sdvo_priv->caps.output_flags, 2);
2006 DRM_DEBUG_KMS(I915_SDVO,
2007 "%s: Unknown SDVO output type (0x%02x%02x)\n",
2008 SDVO_NAME(sdvo_priv),
2009 bytes[0], bytes[1]);
2010 ret = false;
2011 }
2012
2013 if (ret && registered)
2014 ret = drm_sysfs_connector_add(connector) == 0 ? true : false;
2015
2016
2017 return ret;
2018
2019}
2020
1869bool intel_sdvo_init(struct drm_device *dev, int output_device) 2021bool intel_sdvo_init(struct drm_device *dev, int output_device)
1870{ 2022{
1871 struct drm_connector *connector; 2023 struct drm_connector *connector;
1872 struct intel_output *intel_output; 2024 struct intel_output *intel_output;
1873 struct intel_sdvo_priv *sdvo_priv; 2025 struct intel_sdvo_priv *sdvo_priv;
1874 2026
1875 int connector_type;
1876 u8 ch[0x40]; 2027 u8 ch[0x40];
1877 int i; 2028 int i;
1878 int encoder_type;
1879 2029
1880 intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL); 2030 intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
1881 if (!intel_output) { 2031 if (!intel_output) {
@@ -1925,88 +2075,28 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
1925 intel_output->ddc_bus->algo = &intel_sdvo_i2c_bit_algo; 2075 intel_output->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
1926 2076
1927 /* In defaut case sdvo lvds is false */ 2077 /* In defaut case sdvo lvds is false */
1928 sdvo_priv->is_lvds = false;
1929 intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps); 2078 intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
1930 2079
1931 if (sdvo_priv->caps.output_flags & 2080 if (intel_sdvo_output_setup(intel_output,
1932 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) { 2081 sdvo_priv->caps.output_flags) != true) {
1933 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0) 2082 DRM_DEBUG("SDVO output failed to setup on SDVO%c\n",
1934 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0; 2083 output_device == SDVOB ? 'B' : 'C');
1935 else
1936 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
1937
1938 encoder_type = DRM_MODE_ENCODER_TMDS;
1939 connector_type = DRM_MODE_CONNECTOR_DVID;
1940
1941 if (intel_sdvo_get_supp_encode(intel_output,
1942 &sdvo_priv->encode) &&
1943 intel_sdvo_get_digital_encoding_mode(intel_output) &&
1944 sdvo_priv->is_hdmi) {
1945 /* enable hdmi encoding mode if supported */
1946 intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
1947 intel_sdvo_set_colorimetry(intel_output,
1948 SDVO_COLORIMETRY_RGB256);
1949 connector_type = DRM_MODE_CONNECTOR_HDMIA;
1950 }
1951 }
1952 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_SVID0)
1953 {
1954 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
1955 encoder_type = DRM_MODE_ENCODER_TVDAC;
1956 connector_type = DRM_MODE_CONNECTOR_SVIDEO;
1957 sdvo_priv->is_tv = true;
1958 intel_output->needs_tv_clock = true;
1959 }
1960 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB0)
1961 {
1962 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
1963 encoder_type = DRM_MODE_ENCODER_DAC;
1964 connector_type = DRM_MODE_CONNECTOR_VGA;
1965 }
1966 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB1)
1967 {
1968 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
1969 encoder_type = DRM_MODE_ENCODER_DAC;
1970 connector_type = DRM_MODE_CONNECTOR_VGA;
1971 }
1972 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS0)
1973 {
1974 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
1975 encoder_type = DRM_MODE_ENCODER_LVDS;
1976 connector_type = DRM_MODE_CONNECTOR_LVDS;
1977 sdvo_priv->is_lvds = true;
1978 }
1979 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS1)
1980 {
1981 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
1982 encoder_type = DRM_MODE_ENCODER_LVDS;
1983 connector_type = DRM_MODE_CONNECTOR_LVDS;
1984 sdvo_priv->is_lvds = true;
1985 }
1986 else
1987 {
1988 unsigned char bytes[2];
1989
1990 sdvo_priv->controlled_output = 0;
1991 memcpy (bytes, &sdvo_priv->caps.output_flags, 2);
1992 DRM_DEBUG_KMS(I915_SDVO,
1993 "%s: Unknown SDVO output type (0x%02x%02x)\n",
1994 SDVO_NAME(sdvo_priv),
1995 bytes[0], bytes[1]);
1996 encoder_type = DRM_MODE_ENCODER_NONE;
1997 connector_type = DRM_MODE_CONNECTOR_Unknown;
1998 goto err_i2c; 2084 goto err_i2c;
1999 } 2085 }
2000 2086
2087
2001 connector = &intel_output->base; 2088 connector = &intel_output->base;
2002 drm_connector_init(dev, connector, &intel_sdvo_connector_funcs, 2089 drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
2003 connector_type); 2090 connector->connector_type);
2091
2004 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs); 2092 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2005 connector->interlace_allowed = 0; 2093 connector->interlace_allowed = 0;
2006 connector->doublescan_allowed = 0; 2094 connector->doublescan_allowed = 0;
2007 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 2095 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2008 2096
2009 drm_encoder_init(dev, &intel_output->enc, &intel_sdvo_enc_funcs, encoder_type); 2097 drm_encoder_init(dev, &intel_output->enc,
2098 &intel_sdvo_enc_funcs, intel_output->enc.encoder_type);
2099
2010 drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs); 2100 drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
2011 2101
2012 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc); 2102 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index a43c98e3f077..da4ab4dc1630 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1490,6 +1490,27 @@ static struct input_res {
1490 {"1920x1080", 1920, 1080}, 1490 {"1920x1080", 1920, 1080},
1491}; 1491};
1492 1492
1493/*
1494 * Chose preferred mode according to line number of TV format
1495 */
1496static void
1497intel_tv_chose_preferred_modes(struct drm_connector *connector,
1498 struct drm_display_mode *mode_ptr)
1499{
1500 struct intel_output *intel_output = to_intel_output(connector);
1501 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_output);
1502
1503 if (tv_mode->nbr_end < 480 && mode_ptr->vdisplay == 480)
1504 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1505 else if (tv_mode->nbr_end > 480) {
1506 if (tv_mode->progressive == true && tv_mode->nbr_end < 720) {
1507 if (mode_ptr->vdisplay == 720)
1508 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1509 } else if (mode_ptr->vdisplay == 1080)
1510 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1511 }
1512}
1513
1493/** 1514/**
1494 * Stub get_modes function. 1515 * Stub get_modes function.
1495 * 1516 *
@@ -1544,6 +1565,7 @@ intel_tv_get_modes(struct drm_connector *connector)
1544 mode_ptr->clock = (int) tmp; 1565 mode_ptr->clock = (int) tmp;
1545 1566
1546 mode_ptr->type = DRM_MODE_TYPE_DRIVER; 1567 mode_ptr->type = DRM_MODE_TYPE_DRIVER;
1568 intel_tv_chose_preferred_modes(connector, mode_ptr);
1547 drm_mode_probed_add(connector, mode_ptr); 1569 drm_mode_probed_add(connector, mode_ptr);
1548 count++; 1570 count++;
1549 } 1571 }
diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index 146f3570af8e..20f17908b036 100644
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -384,8 +384,9 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
384 DRM_INFO("Loading RV670 PFP Microcode\n"); 384 DRM_INFO("Loading RV670 PFP Microcode\n");
385 for (i = 0; i < PFP_UCODE_SIZE; i++) 385 for (i = 0; i < PFP_UCODE_SIZE; i++)
386 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]); 386 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]);
387 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) { 387 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
388 DRM_INFO("Loading RS780 CP Microcode\n"); 388 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
389 DRM_INFO("Loading RS780/RS880 CP Microcode\n");
389 for (i = 0; i < PM4_UCODE_SIZE; i++) { 390 for (i = 0; i < PM4_UCODE_SIZE; i++) {
390 RADEON_WRITE(R600_CP_ME_RAM_DATA, 391 RADEON_WRITE(R600_CP_ME_RAM_DATA,
391 RS780_cp_microcode[i][0]); 392 RS780_cp_microcode[i][0]);
@@ -396,7 +397,7 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
396 } 397 }
397 398
398 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 399 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
399 DRM_INFO("Loading RS780 PFP Microcode\n"); 400 DRM_INFO("Loading RS780/RS880 PFP Microcode\n");
400 for (i = 0; i < PFP_UCODE_SIZE; i++) 401 for (i = 0; i < PFP_UCODE_SIZE; i++)
401 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RS780_pfp_microcode[i]); 402 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RS780_pfp_microcode[i]);
402 } 403 }
@@ -783,6 +784,7 @@ static void r600_gfx_init(struct drm_device *dev,
783 break; 784 break;
784 case CHIP_RV610: 785 case CHIP_RV610:
785 case CHIP_RS780: 786 case CHIP_RS780:
787 case CHIP_RS880:
786 case CHIP_RV620: 788 case CHIP_RV620:
787 dev_priv->r600_max_pipes = 1; 789 dev_priv->r600_max_pipes = 1;
788 dev_priv->r600_max_tile_pipes = 1; 790 dev_priv->r600_max_tile_pipes = 1;
@@ -917,7 +919,8 @@ static void r600_gfx_init(struct drm_device *dev,
917 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 919 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
918 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 920 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
919 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 921 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
920 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) 922 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
923 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
921 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE); 924 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
922 else 925 else
923 RADEON_WRITE(R600_DB_DEBUG, 0); 926 RADEON_WRITE(R600_DB_DEBUG, 0);
@@ -935,7 +938,8 @@ static void r600_gfx_init(struct drm_device *dev,
935 sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES); 938 sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
936 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 939 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
937 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 940 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
938 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) { 941 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
942 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
939 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) | 943 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
940 R600_FETCH_FIFO_HIWATER(0xa) | 944 R600_FETCH_FIFO_HIWATER(0xa) |
941 R600_DONE_FIFO_HIWATER(0xe0) | 945 R600_DONE_FIFO_HIWATER(0xe0) |
@@ -978,7 +982,8 @@ static void r600_gfx_init(struct drm_device *dev,
978 R600_NUM_ES_STACK_ENTRIES(0)); 982 R600_NUM_ES_STACK_ENTRIES(0));
979 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 983 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
980 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 984 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
981 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) { 985 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
986 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
982 /* no vertex cache */ 987 /* no vertex cache */
983 sq_config &= ~R600_VC_ENABLE; 988 sq_config &= ~R600_VC_ENABLE;
984 989
@@ -1035,7 +1040,8 @@ static void r600_gfx_init(struct drm_device *dev,
1035 1040
1036 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 1041 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
1037 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 1042 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
1038 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) 1043 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
1044 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
1039 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY)); 1045 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
1040 else 1046 else
1041 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC)); 1047 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
@@ -1078,6 +1084,7 @@ static void r600_gfx_init(struct drm_device *dev,
1078 break; 1084 break;
1079 case CHIP_RV610: 1085 case CHIP_RV610:
1080 case CHIP_RS780: 1086 case CHIP_RS780:
1087 case CHIP_RS880:
1081 case CHIP_RV620: 1088 case CHIP_RV620:
1082 gs_prim_buffer_depth = 32; 1089 gs_prim_buffer_depth = 32;
1083 break; 1090 break;
@@ -1123,6 +1130,7 @@ static void r600_gfx_init(struct drm_device *dev,
1123 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1130 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1124 case CHIP_RV610: 1131 case CHIP_RV610:
1125 case CHIP_RS780: 1132 case CHIP_RS780:
1133 case CHIP_RS880:
1126 case CHIP_RV620: 1134 case CHIP_RV620:
1127 tc_cntl = R600_TC_L2_SIZE(8); 1135 tc_cntl = R600_TC_L2_SIZE(8);
1128 break; 1136 break;
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index a162ade74b7f..9ff6dcb97f9d 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -152,7 +152,9 @@ int radeon_mc_setup(struct radeon_device *rdev)
152 } 152 }
153 } else { 153 } else {
154 rdev->mc.vram_location = 0; 154 rdev->mc.vram_location = 0;
155 rdev->mc.gtt_location = rdev->mc.mc_vram_size; 155 tmp = rdev->mc.mc_vram_size;
156 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
157 rdev->mc.gtt_location = tmp;
156 } 158 }
157 DRM_INFO("radeon: VRAM %uM\n", rdev->mc.real_vram_size >> 20); 159 DRM_INFO("radeon: VRAM %uM\n", rdev->mc.real_vram_size >> 20);
158 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", 160 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 127d0456f628..3933f8216a34 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -143,6 +143,7 @@ enum radeon_family {
143 CHIP_RV635, 143 CHIP_RV635,
144 CHIP_RV670, 144 CHIP_RV670,
145 CHIP_RS780, 145 CHIP_RS780,
146 CHIP_RS880,
146 CHIP_RV770, 147 CHIP_RV770,
147 CHIP_RV730, 148 CHIP_RV730,
148 CHIP_RV710, 149 CHIP_RV710,
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index dd9ac2fed6d6..e98cae3bf4a6 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -106,7 +106,7 @@ static inline uint32_t radeon_object_flags_from_domain(uint32_t domain)
106 flags |= TTM_PL_FLAG_VRAM | TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED; 106 flags |= TTM_PL_FLAG_VRAM | TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED;
107 } 107 }
108 if (domain & RADEON_GEM_DOMAIN_GTT) { 108 if (domain & RADEON_GEM_DOMAIN_GTT) {
109 flags |= TTM_PL_FLAG_TT | TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED; 109 flags |= TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
110 } 110 }
111 if (domain & RADEON_GEM_DOMAIN_CPU) { 111 if (domain & RADEON_GEM_DOMAIN_CPU) {
112 flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING; 112 flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING;
diff --git a/drivers/input/keyboard/matrix_keypad.c b/drivers/input/keyboard/matrix_keypad.c
index e9b2e7cb05be..541b981ff075 100644
--- a/drivers/input/keyboard/matrix_keypad.c
+++ b/drivers/input/keyboard/matrix_keypad.c
@@ -27,6 +27,7 @@ struct matrix_keypad {
27 const struct matrix_keypad_platform_data *pdata; 27 const struct matrix_keypad_platform_data *pdata;
28 struct input_dev *input_dev; 28 struct input_dev *input_dev;
29 unsigned short *keycodes; 29 unsigned short *keycodes;
30 unsigned int row_shift;
30 31
31 uint32_t last_key_state[MATRIX_MAX_COLS]; 32 uint32_t last_key_state[MATRIX_MAX_COLS];
32 struct delayed_work work; 33 struct delayed_work work;
@@ -136,7 +137,7 @@ static void matrix_keypad_scan(struct work_struct *work)
136 if ((bits_changed & (1 << row)) == 0) 137 if ((bits_changed & (1 << row)) == 0)
137 continue; 138 continue;
138 139
139 code = (row << 4) + col; 140 code = MATRIX_SCAN_CODE(row, col, keypad->row_shift);
140 input_event(input_dev, EV_MSC, MSC_SCAN, code); 141 input_event(input_dev, EV_MSC, MSC_SCAN, code);
141 input_report_key(input_dev, 142 input_report_key(input_dev,
142 keypad->keycodes[code], 143 keypad->keycodes[code],
@@ -317,6 +318,7 @@ static int __devinit matrix_keypad_probe(struct platform_device *pdev)
317 struct matrix_keypad *keypad; 318 struct matrix_keypad *keypad;
318 struct input_dev *input_dev; 319 struct input_dev *input_dev;
319 unsigned short *keycodes; 320 unsigned short *keycodes;
321 unsigned int row_shift;
320 int i; 322 int i;
321 int err; 323 int err;
322 324
@@ -332,14 +334,11 @@ static int __devinit matrix_keypad_probe(struct platform_device *pdev)
332 return -EINVAL; 334 return -EINVAL;
333 } 335 }
334 336
335 if (!keymap_data->max_keymap_size) { 337 row_shift = get_count_order(pdata->num_col_gpios);
336 dev_err(&pdev->dev, "invalid keymap data supplied\n");
337 return -EINVAL;
338 }
339 338
340 keypad = kzalloc(sizeof(struct matrix_keypad), GFP_KERNEL); 339 keypad = kzalloc(sizeof(struct matrix_keypad), GFP_KERNEL);
341 keycodes = kzalloc(keymap_data->max_keymap_size * 340 keycodes = kzalloc((pdata->num_row_gpios << row_shift) *
342 sizeof(keypad->keycodes), 341 sizeof(*keycodes),
343 GFP_KERNEL); 342 GFP_KERNEL);
344 input_dev = input_allocate_device(); 343 input_dev = input_allocate_device();
345 if (!keypad || !keycodes || !input_dev) { 344 if (!keypad || !keycodes || !input_dev) {
@@ -350,6 +349,7 @@ static int __devinit matrix_keypad_probe(struct platform_device *pdev)
350 keypad->input_dev = input_dev; 349 keypad->input_dev = input_dev;
351 keypad->pdata = pdata; 350 keypad->pdata = pdata;
352 keypad->keycodes = keycodes; 351 keypad->keycodes = keycodes;
352 keypad->row_shift = row_shift;
353 keypad->stopped = true; 353 keypad->stopped = true;
354 INIT_DELAYED_WORK(&keypad->work, matrix_keypad_scan); 354 INIT_DELAYED_WORK(&keypad->work, matrix_keypad_scan);
355 spin_lock_init(&keypad->lock); 355 spin_lock_init(&keypad->lock);
@@ -363,7 +363,7 @@ static int __devinit matrix_keypad_probe(struct platform_device *pdev)
363 363
364 input_dev->keycode = keycodes; 364 input_dev->keycode = keycodes;
365 input_dev->keycodesize = sizeof(*keycodes); 365 input_dev->keycodesize = sizeof(*keycodes);
366 input_dev->keycodemax = keymap_data->max_keymap_size; 366 input_dev->keycodemax = pdata->num_row_gpios << keypad->row_shift;
367 367
368 for (i = 0; i < keymap_data->keymap_size; i++) { 368 for (i = 0; i < keymap_data->keymap_size; i++) {
369 unsigned int key = keymap_data->keymap[i]; 369 unsigned int key = keymap_data->keymap[i];
@@ -371,7 +371,7 @@ static int __devinit matrix_keypad_probe(struct platform_device *pdev)
371 unsigned int col = KEY_COL(key); 371 unsigned int col = KEY_COL(key);
372 unsigned short code = KEY_VAL(key); 372 unsigned short code = KEY_VAL(key);
373 373
374 keycodes[(row << 4) + col] = code; 374 keycodes[MATRIX_SCAN_CODE(row, col, row_shift)] = code;
375 __set_bit(code, input_dev->keybit); 375 __set_bit(code, input_dev->keybit);
376 } 376 }
377 __clear_bit(KEY_RESERVED, input_dev->keybit); 377 __clear_bit(KEY_RESERVED, input_dev->keybit);
diff --git a/drivers/input/misc/wistron_btns.c b/drivers/input/misc/wistron_btns.c
index 26e17a9a22eb..27ee976eb54c 100644
--- a/drivers/input/misc/wistron_btns.c
+++ b/drivers/input/misc/wistron_btns.c
@@ -611,6 +611,20 @@ static struct key_entry keymap_wistron_generic[] __initdata = {
611 { KE_END, 0 } 611 { KE_END, 0 }
612}; 612};
613 613
614static struct key_entry keymap_prestigio[] __initdata = {
615 { KE_KEY, 0x11, {KEY_PROG1} },
616 { KE_KEY, 0x12, {KEY_PROG2} },
617 { KE_WIFI, 0x30 },
618 { KE_KEY, 0x22, {KEY_REWIND} },
619 { KE_KEY, 0x23, {KEY_FORWARD} },
620 { KE_KEY, 0x24, {KEY_PLAYPAUSE} },
621 { KE_KEY, 0x25, {KEY_STOPCD} },
622 { KE_KEY, 0x31, {KEY_MAIL} },
623 { KE_KEY, 0x36, {KEY_WWW} },
624 { KE_END, 0 }
625};
626
627
614/* 628/*
615 * If your machine is not here (which is currently rather likely), please send 629 * If your machine is not here (which is currently rather likely), please send
616 * a list of buttons and their key codes (reported when loading this module 630 * a list of buttons and their key codes (reported when loading this module
@@ -971,6 +985,8 @@ static int __init select_keymap(void)
971 if (keymap_name != NULL) { 985 if (keymap_name != NULL) {
972 if (strcmp (keymap_name, "1557/MS2141") == 0) 986 if (strcmp (keymap_name, "1557/MS2141") == 0)
973 keymap = keymap_wistron_ms2141; 987 keymap = keymap_wistron_ms2141;
988 else if (strcmp (keymap_name, "prestigio") == 0)
989 keymap = keymap_prestigio;
974 else if (strcmp (keymap_name, "generic") == 0) 990 else if (strcmp (keymap_name, "generic") == 0)
975 keymap = keymap_wistron_generic; 991 keymap = keymap_wistron_generic;
976 else { 992 else {
diff --git a/drivers/input/serio/i8042-x86ia64io.h b/drivers/input/serio/i8042-x86ia64io.h
index 924e8ed7f2cf..ae04d8a494e5 100644
--- a/drivers/input/serio/i8042-x86ia64io.h
+++ b/drivers/input/serio/i8042-x86ia64io.h
@@ -78,6 +78,14 @@ static struct dmi_system_id __initdata i8042_dmi_noloop_table[] = {
78 }, 78 },
79 }, 79 },
80 { 80 {
81 .ident = "ASUS G1S",
82 .matches = {
83 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer Inc."),
84 DMI_MATCH(DMI_BOARD_NAME, "G1S"),
85 DMI_MATCH(DMI_BOARD_VERSION, "1.0"),
86 },
87 },
88 {
81 /* AUX LOOP command does not raise AUX IRQ */ 89 /* AUX LOOP command does not raise AUX IRQ */
82 .ident = "ASUS P65UP5", 90 .ident = "ASUS P65UP5",
83 .matches = { 91 .matches = {
diff --git a/drivers/mmc/host/sdhci-of.c b/drivers/mmc/host/sdhci-of.c
index 908844327db0..1e8aa590bb39 100644
--- a/drivers/mmc/host/sdhci-of.c
+++ b/drivers/mmc/host/sdhci-of.c
@@ -234,7 +234,7 @@ static int __devinit sdhci_of_probe(struct of_device *ofdev,
234 return -ENODEV; 234 return -ENODEV;
235 235
236 host = sdhci_alloc_host(&ofdev->dev, sizeof(*of_host)); 236 host = sdhci_alloc_host(&ofdev->dev, sizeof(*of_host));
237 if (!host) 237 if (IS_ERR(host))
238 return -ENOMEM; 238 return -ENOMEM;
239 239
240 of_host = sdhci_priv(host); 240 of_host = sdhci_priv(host);
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index 0b98654d8eed..7a58bd5522fd 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -284,13 +284,6 @@ config MTD_L440GX
284 284
285 BE VERY CAREFUL. 285 BE VERY CAREFUL.
286 286
287config MTD_SBC8240
288 tristate "Flash device on SBC8240"
289 depends on MTD_JEDECPROBE && 8260
290 help
291 Flash access on the SBC8240 board from Wind River. See
292 <http://www.windriver.com/products/sbc8240/>
293
294config MTD_TQM8XXL 287config MTD_TQM8XXL
295 tristate "CFI Flash device mapped on TQM8XXL" 288 tristate "CFI Flash device mapped on TQM8XXL"
296 depends on MTD_CFI && TQM8xxL 289 depends on MTD_CFI && TQM8xxL
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
index 8bae7f9850c0..5beb0662d724 100644
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -50,7 +50,6 @@ obj-$(CONFIG_MTD_UCLINUX) += uclinux.o
50obj-$(CONFIG_MTD_NETtel) += nettel.o 50obj-$(CONFIG_MTD_NETtel) += nettel.o
51obj-$(CONFIG_MTD_SCB2_FLASH) += scb2_flash.o 51obj-$(CONFIG_MTD_SCB2_FLASH) += scb2_flash.o
52obj-$(CONFIG_MTD_H720X) += h720x-flash.o 52obj-$(CONFIG_MTD_H720X) += h720x-flash.o
53obj-$(CONFIG_MTD_SBC8240) += sbc8240.o
54obj-$(CONFIG_MTD_IXP4XX) += ixp4xx.o 53obj-$(CONFIG_MTD_IXP4XX) += ixp4xx.o
55obj-$(CONFIG_MTD_IXP2000) += ixp2000.o 54obj-$(CONFIG_MTD_IXP2000) += ixp2000.o
56obj-$(CONFIG_MTD_WRSBC8260) += wr_sbc82xx_flash.o 55obj-$(CONFIG_MTD_WRSBC8260) += wr_sbc82xx_flash.o
diff --git a/drivers/mtd/maps/sbc8240.c b/drivers/mtd/maps/sbc8240.c
index d5374cdcb163..e69de29bb2d1 100644
--- a/drivers/mtd/maps/sbc8240.c
+++ b/drivers/mtd/maps/sbc8240.c
@@ -1,250 +0,0 @@
1/*
2 * Handle mapping of the flash memory access routines on the SBC8240 board.
3 *
4 * Carolyn Smith, Tektronix, Inc.
5 *
6 * This code is GPLed
7 */
8
9/*
10 * The SBC8240 has 2 flash banks.
11 * Bank 0 is a 512 KiB AMD AM29F040B; 8 x 64 KiB sectors.
12 * It contains the U-Boot code (7 sectors) and the environment (1 sector).
13 * Bank 1 is 4 x 1 MiB AMD AM29LV800BT; 15 x 64 KiB sectors, 1 x 32 KiB sector,
14 * 2 x 8 KiB sectors, 1 x 16 KiB sectors.
15 * Both parts are JEDEC compatible.
16 */
17
18#include <linux/module.h>
19#include <linux/types.h>
20#include <linux/kernel.h>
21#include <asm/io.h>
22
23#include <linux/mtd/mtd.h>
24#include <linux/mtd/map.h>
25#include <linux/mtd/cfi.h>
26
27#ifdef CONFIG_MTD_PARTITIONS
28#include <linux/mtd/partitions.h>
29#endif
30
31#define DEBUG
32
33#ifdef DEBUG
34# define debugk(fmt,args...) printk(fmt ,##args)
35#else
36# define debugk(fmt,args...)
37#endif
38
39
40#define WINDOW_ADDR0 0xFFF00000 /* 512 KiB */
41#define WINDOW_SIZE0 0x00080000
42#define BUSWIDTH0 1
43
44#define WINDOW_ADDR1 0xFF000000 /* 4 MiB */
45#define WINDOW_SIZE1 0x00400000
46#define BUSWIDTH1 8
47
48#define MSG_PREFIX "sbc8240:" /* prefix for our printk()'s */
49#define MTDID "sbc8240-%d" /* for mtdparts= partitioning */
50
51
52static struct map_info sbc8240_map[2] = {
53 {
54 .name = "sbc8240 Flash Bank #0",
55 .size = WINDOW_SIZE0,
56 .bankwidth = BUSWIDTH0,
57 },
58 {
59 .name = "sbc8240 Flash Bank #1",
60 .size = WINDOW_SIZE1,
61 .bankwidth = BUSWIDTH1,
62 }
63};
64
65#define NUM_FLASH_BANKS ARRAY_SIZE(sbc8240_map)
66
67/*
68 * The following defines the partition layout of SBC8240 boards.
69 *
70 * See include/linux/mtd/partitions.h for definition of the
71 * mtd_partition structure.
72 *
73 * The *_max_flash_size is the maximum possible mapped flash size
74 * which is not necessarily the actual flash size. It must correspond
75 * to the value specified in the mapping definition defined by the
76 * "struct map_desc *_io_desc" for the corresponding machine.
77 */
78
79#ifdef CONFIG_MTD_PARTITIONS
80
81static struct mtd_partition sbc8240_uboot_partitions [] = {
82 /* Bank 0 */
83 {
84 .name = "U-boot", /* U-Boot Firmware */
85 .offset = 0,
86 .size = 0x00070000, /* 7 x 64 KiB sectors */
87 .mask_flags = MTD_WRITEABLE, /* force read-only */
88 },
89 {
90 .name = "environment", /* U-Boot environment */
91 .offset = 0x00070000,
92 .size = 0x00010000, /* 1 x 64 KiB sector */
93 },
94};
95
96static struct mtd_partition sbc8240_fs_partitions [] = {
97 {
98 .name = "jffs", /* JFFS filesystem */
99 .offset = 0,
100 .size = 0x003C0000, /* 4 * 15 * 64KiB */
101 },
102 {
103 .name = "tmp32",
104 .offset = 0x003C0000,
105 .size = 0x00020000, /* 4 * 32KiB */
106 },
107 {
108 .name = "tmp8a",
109 .offset = 0x003E0000,
110 .size = 0x00008000, /* 4 * 8KiB */
111 },
112 {
113 .name = "tmp8b",
114 .offset = 0x003E8000,
115 .size = 0x00008000, /* 4 * 8KiB */
116 },
117 {
118 .name = "tmp16",
119 .offset = 0x003F0000,
120 .size = 0x00010000, /* 4 * 16KiB */
121 }
122};
123
124/* trivial struct to describe partition information */
125struct mtd_part_def
126{
127 int nums;
128 unsigned char *type;
129 struct mtd_partition* mtd_part;
130};
131
132static struct mtd_info *sbc8240_mtd[NUM_FLASH_BANKS];
133static struct mtd_part_def sbc8240_part_banks[NUM_FLASH_BANKS];
134
135
136#endif /* CONFIG_MTD_PARTITIONS */
137
138
139static int __init init_sbc8240_mtd (void)
140{
141 static struct _cjs {
142 u_long addr;
143 u_long size;
144 } pt[NUM_FLASH_BANKS] = {
145 {
146 .addr = WINDOW_ADDR0,
147 .size = WINDOW_SIZE0
148 },
149 {
150 .addr = WINDOW_ADDR1,
151 .size = WINDOW_SIZE1
152 },
153 };
154
155 int devicesfound = 0;
156 int i,j;
157
158 for (i = 0; i < NUM_FLASH_BANKS; i++) {
159 printk (KERN_NOTICE MSG_PREFIX
160 "Probing 0x%08lx at 0x%08lx\n", pt[i].size, pt[i].addr);
161
162 sbc8240_map[i].map_priv_1 =
163 (unsigned long) ioremap (pt[i].addr, pt[i].size);
164 if (!sbc8240_map[i].map_priv_1) {
165 printk (MSG_PREFIX "failed to ioremap\n");
166 for (j = 0; j < i; j++) {
167 iounmap((void *) sbc8240_map[j].map_priv_1);
168 sbc8240_map[j].map_priv_1 = 0;
169 }
170 return -EIO;
171 }
172 simple_map_init(&sbc8240_mtd[i]);
173
174 sbc8240_mtd[i] = do_map_probe("jedec_probe", &sbc8240_map[i]);
175
176 if (sbc8240_mtd[i]) {
177 sbc8240_mtd[i]->module = THIS_MODULE;
178 devicesfound++;
179 } else {
180 if (sbc8240_map[i].map_priv_1) {
181 iounmap((void *) sbc8240_map[i].map_priv_1);
182 sbc8240_map[i].map_priv_1 = 0;
183 }
184 }
185 }
186
187 if (!devicesfound) {
188 printk(KERN_NOTICE MSG_PREFIX
189 "No suppported flash chips found!\n");
190 return -ENXIO;
191 }
192
193#ifdef CONFIG_MTD_PARTITIONS
194 sbc8240_part_banks[0].mtd_part = sbc8240_uboot_partitions;
195 sbc8240_part_banks[0].type = "static image";
196 sbc8240_part_banks[0].nums = ARRAY_SIZE(sbc8240_uboot_partitions);
197 sbc8240_part_banks[1].mtd_part = sbc8240_fs_partitions;
198 sbc8240_part_banks[1].type = "static file system";
199 sbc8240_part_banks[1].nums = ARRAY_SIZE(sbc8240_fs_partitions);
200
201 for (i = 0; i < NUM_FLASH_BANKS; i++) {
202
203 if (!sbc8240_mtd[i]) continue;
204 if (sbc8240_part_banks[i].nums == 0) {
205 printk (KERN_NOTICE MSG_PREFIX
206 "No partition info available, registering whole device\n");
207 add_mtd_device(sbc8240_mtd[i]);
208 } else {
209 printk (KERN_NOTICE MSG_PREFIX
210 "Using %s partition definition\n", sbc8240_part_banks[i].mtd_part->name);
211 add_mtd_partitions (sbc8240_mtd[i],
212 sbc8240_part_banks[i].mtd_part,
213 sbc8240_part_banks[i].nums);
214 }
215 }
216#else
217 printk(KERN_NOTICE MSG_PREFIX
218 "Registering %d flash banks at once\n", devicesfound);
219
220 for (i = 0; i < devicesfound; i++) {
221 add_mtd_device(sbc8240_mtd[i]);
222 }
223#endif /* CONFIG_MTD_PARTITIONS */
224
225 return devicesfound == 0 ? -ENXIO : 0;
226}
227
228static void __exit cleanup_sbc8240_mtd (void)
229{
230 int i;
231
232 for (i = 0; i < NUM_FLASH_BANKS; i++) {
233 if (sbc8240_mtd[i]) {
234 del_mtd_device (sbc8240_mtd[i]);
235 map_destroy (sbc8240_mtd[i]);
236 }
237 if (sbc8240_map[i].map_priv_1) {
238 iounmap ((void *) sbc8240_map[i].map_priv_1);
239 sbc8240_map[i].map_priv_1 = 0;
240 }
241 }
242}
243
244module_init (init_sbc8240_mtd);
245module_exit (cleanup_sbc8240_mtd);
246
247MODULE_LICENSE ("GPL");
248MODULE_AUTHOR ("Carolyn Smith <carolyn.smith@tektronix.com>");
249MODULE_DESCRIPTION ("MTD map driver for SBC8240 boards");
250
diff --git a/drivers/mtd/mtd_blkdevs.c b/drivers/mtd/mtd_blkdevs.c
index c3f62654b6df..7baba40c1ed2 100644
--- a/drivers/mtd/mtd_blkdevs.c
+++ b/drivers/mtd/mtd_blkdevs.c
@@ -144,7 +144,7 @@ static int blktrans_open(struct block_device *bdev, fmode_t mode)
144 struct mtd_blktrans_ops *tr = dev->tr; 144 struct mtd_blktrans_ops *tr = dev->tr;
145 int ret = -ENODEV; 145 int ret = -ENODEV;
146 146
147 if (!try_module_get(dev->mtd->owner)) 147 if (!get_mtd_device(NULL, dev->mtd->index))
148 goto out; 148 goto out;
149 149
150 if (!try_module_get(tr->owner)) 150 if (!try_module_get(tr->owner))
@@ -158,7 +158,7 @@ static int blktrans_open(struct block_device *bdev, fmode_t mode)
158 ret = 0; 158 ret = 0;
159 if (tr->open && (ret = tr->open(dev))) { 159 if (tr->open && (ret = tr->open(dev))) {
160 dev->mtd->usecount--; 160 dev->mtd->usecount--;
161 module_put(dev->mtd->owner); 161 put_mtd_device(dev->mtd);
162 out_tr: 162 out_tr:
163 module_put(tr->owner); 163 module_put(tr->owner);
164 } 164 }
@@ -177,7 +177,7 @@ static int blktrans_release(struct gendisk *disk, fmode_t mode)
177 177
178 if (!ret) { 178 if (!ret) {
179 dev->mtd->usecount--; 179 dev->mtd->usecount--;
180 module_put(dev->mtd->owner); 180 put_mtd_device(dev->mtd);
181 module_put(tr->owner); 181 module_put(tr->owner);
182 } 182 }
183 183
diff --git a/drivers/mtd/mtdblock.c b/drivers/mtd/mtdblock.c
index 208c6faa0358..77db5ce24d92 100644
--- a/drivers/mtd/mtdblock.c
+++ b/drivers/mtd/mtdblock.c
@@ -29,6 +29,8 @@ static struct mtdblk_dev {
29 enum { STATE_EMPTY, STATE_CLEAN, STATE_DIRTY } cache_state; 29 enum { STATE_EMPTY, STATE_CLEAN, STATE_DIRTY } cache_state;
30} *mtdblks[MAX_MTD_DEVICES]; 30} *mtdblks[MAX_MTD_DEVICES];
31 31
32static struct mutex mtdblks_lock;
33
32/* 34/*
33 * Cache stuff... 35 * Cache stuff...
34 * 36 *
@@ -270,15 +272,19 @@ static int mtdblock_open(struct mtd_blktrans_dev *mbd)
270 272
271 DEBUG(MTD_DEBUG_LEVEL1,"mtdblock_open\n"); 273 DEBUG(MTD_DEBUG_LEVEL1,"mtdblock_open\n");
272 274
275 mutex_lock(&mtdblks_lock);
273 if (mtdblks[dev]) { 276 if (mtdblks[dev]) {
274 mtdblks[dev]->count++; 277 mtdblks[dev]->count++;
278 mutex_unlock(&mtdblks_lock);
275 return 0; 279 return 0;
276 } 280 }
277 281
278 /* OK, it's not open. Create cache info for it */ 282 /* OK, it's not open. Create cache info for it */
279 mtdblk = kzalloc(sizeof(struct mtdblk_dev), GFP_KERNEL); 283 mtdblk = kzalloc(sizeof(struct mtdblk_dev), GFP_KERNEL);
280 if (!mtdblk) 284 if (!mtdblk) {
285 mutex_unlock(&mtdblks_lock);
281 return -ENOMEM; 286 return -ENOMEM;
287 }
282 288
283 mtdblk->count = 1; 289 mtdblk->count = 1;
284 mtdblk->mtd = mtd; 290 mtdblk->mtd = mtd;
@@ -291,6 +297,7 @@ static int mtdblock_open(struct mtd_blktrans_dev *mbd)
291 } 297 }
292 298
293 mtdblks[dev] = mtdblk; 299 mtdblks[dev] = mtdblk;
300 mutex_unlock(&mtdblks_lock);
294 301
295 DEBUG(MTD_DEBUG_LEVEL1, "ok\n"); 302 DEBUG(MTD_DEBUG_LEVEL1, "ok\n");
296 303
@@ -304,6 +311,8 @@ static int mtdblock_release(struct mtd_blktrans_dev *mbd)
304 311
305 DEBUG(MTD_DEBUG_LEVEL1, "mtdblock_release\n"); 312 DEBUG(MTD_DEBUG_LEVEL1, "mtdblock_release\n");
306 313
314 mutex_lock(&mtdblks_lock);
315
307 mutex_lock(&mtdblk->cache_mutex); 316 mutex_lock(&mtdblk->cache_mutex);
308 write_cached_data(mtdblk); 317 write_cached_data(mtdblk);
309 mutex_unlock(&mtdblk->cache_mutex); 318 mutex_unlock(&mtdblk->cache_mutex);
@@ -316,6 +325,9 @@ static int mtdblock_release(struct mtd_blktrans_dev *mbd)
316 vfree(mtdblk->cache_data); 325 vfree(mtdblk->cache_data);
317 kfree(mtdblk); 326 kfree(mtdblk);
318 } 327 }
328
329 mutex_unlock(&mtdblks_lock);
330
319 DEBUG(MTD_DEBUG_LEVEL1, "ok\n"); 331 DEBUG(MTD_DEBUG_LEVEL1, "ok\n");
320 332
321 return 0; 333 return 0;
@@ -376,6 +388,8 @@ static struct mtd_blktrans_ops mtdblock_tr = {
376 388
377static int __init init_mtdblock(void) 389static int __init init_mtdblock(void)
378{ 390{
391 mutex_init(&mtdblks_lock);
392
379 return register_mtd_blktrans(&mtdblock_tr); 393 return register_mtd_blktrans(&mtdblock_tr);
380} 394}
381 395
diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
index fac54a3fa3f1..00ebf7af7467 100644
--- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c
@@ -65,8 +65,8 @@ static void mtd_release(struct device *dev)
65static int mtd_cls_suspend(struct device *dev, pm_message_t state) 65static int mtd_cls_suspend(struct device *dev, pm_message_t state)
66{ 66{
67 struct mtd_info *mtd = dev_to_mtd(dev); 67 struct mtd_info *mtd = dev_to_mtd(dev);
68 68
69 if (mtd->suspend) 69 if (mtd && mtd->suspend)
70 return mtd->suspend(mtd); 70 return mtd->suspend(mtd);
71 else 71 else
72 return 0; 72 return 0;
@@ -76,7 +76,7 @@ static int mtd_cls_resume(struct device *dev)
76{ 76{
77 struct mtd_info *mtd = dev_to_mtd(dev); 77 struct mtd_info *mtd = dev_to_mtd(dev);
78 78
79 if (mtd->resume) 79 if (mtd && mtd->resume)
80 mtd->resume(mtd); 80 mtd->resume(mtd);
81 return 0; 81 return 0;
82} 82}
@@ -298,6 +298,7 @@ int add_mtd_device(struct mtd_info *mtd)
298 mtd->dev.class = &mtd_class; 298 mtd->dev.class = &mtd_class;
299 mtd->dev.devt = MTD_DEVT(i); 299 mtd->dev.devt = MTD_DEVT(i);
300 dev_set_name(&mtd->dev, "mtd%d", i); 300 dev_set_name(&mtd->dev, "mtd%d", i);
301 dev_set_drvdata(&mtd->dev, mtd);
301 if (device_register(&mtd->dev) != 0) { 302 if (device_register(&mtd->dev) != 0) {
302 mtd_table[i] = NULL; 303 mtd_table[i] = NULL;
303 break; 304 break;
diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index 38d656b9b2ee..0108ed42e877 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -266,7 +266,7 @@ static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
266 266
267 if (ONENAND_CURRENT_BUFFERRAM(this)) { 267 if (ONENAND_CURRENT_BUFFERRAM(this)) {
268 if (area == ONENAND_DATARAM) 268 if (area == ONENAND_DATARAM)
269 return mtd->writesize; 269 return this->writesize;
270 if (area == ONENAND_SPARERAM) 270 if (area == ONENAND_SPARERAM)
271 return mtd->oobsize; 271 return mtd->oobsize;
272 } 272 }
@@ -770,6 +770,7 @@ static int __devexit omap2_onenand_remove(struct platform_device *pdev)
770 } 770 }
771 iounmap(c->onenand.base); 771 iounmap(c->onenand.base);
772 release_mem_region(c->phys_base, ONENAND_IO_SIZE); 772 release_mem_region(c->phys_base, ONENAND_IO_SIZE);
773 gpmc_cs_free(c->gpmc_cs);
773 kfree(c); 774 kfree(c);
774 775
775 return 0; 776 return 0;
diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c
index 0f2034c3ed2f..e4d9ef0c965a 100644
--- a/drivers/mtd/ubi/eba.c
+++ b/drivers/mtd/ubi/eba.c
@@ -1254,6 +1254,7 @@ out_free:
1254 if (!ubi->volumes[i]) 1254 if (!ubi->volumes[i])
1255 continue; 1255 continue;
1256 kfree(ubi->volumes[i]->eba_tbl); 1256 kfree(ubi->volumes[i]->eba_tbl);
1257 ubi->volumes[i]->eba_tbl = NULL;
1257 } 1258 }
1258 return err; 1259 return err;
1259} 1260}
diff --git a/drivers/mtd/ubi/scan.c b/drivers/mtd/ubi/scan.c
index a423131b6171..b847745394b4 100644
--- a/drivers/mtd/ubi/scan.c
+++ b/drivers/mtd/ubi/scan.c
@@ -781,11 +781,22 @@ static int process_eb(struct ubi_device *ubi, struct ubi_scan_info *si,
781 return -EINVAL; 781 return -EINVAL;
782 } 782 }
783 783
784 /*
785 * Make sure that all PEBs have the same image sequence number.
786 * This allows us to detect situations when users flash UBI
787 * images incorrectly, so that the flash has the new UBI image
788 * and leftovers from the old one. This feature was added
789 * relatively recently, and the sequence number was always
790 * zero, because old UBI implementations always set it to zero.
791 * For this reasons, we do not panic if some PEBs have zero
792 * sequence number, while other PEBs have non-zero sequence
793 * number.
794 */
784 image_seq = be32_to_cpu(ech->image_seq); 795 image_seq = be32_to_cpu(ech->image_seq);
785 if (!si->image_seq_set) { 796 if (!si->image_seq_set) {
786 ubi->image_seq = image_seq; 797 ubi->image_seq = image_seq;
787 si->image_seq_set = 1; 798 si->image_seq_set = 1;
788 } else if (ubi->image_seq != image_seq) { 799 } else if (ubi->image_seq && ubi->image_seq != image_seq) {
789 ubi_err("bad image sequence number %d in PEB %d, " 800 ubi_err("bad image sequence number %d in PEB %d, "
790 "expected %d", image_seq, pnum, ubi->image_seq); 801 "expected %d", image_seq, pnum, ubi->image_seq);
791 ubi_dbg_dump_ec_hdr(ech); 802 ubi_dbg_dump_ec_hdr(ech);
diff --git a/drivers/pci/hotplug/sgi_hotplug.c b/drivers/pci/hotplug/sgi_hotplug.c
index a4494d78e7c2..8aebe1e9d3d6 100644
--- a/drivers/pci/hotplug/sgi_hotplug.c
+++ b/drivers/pci/hotplug/sgi_hotplug.c
@@ -90,11 +90,10 @@ static struct hotplug_slot_ops sn_hotplug_slot_ops = {
90 90
91static DEFINE_MUTEX(sn_hotplug_mutex); 91static DEFINE_MUTEX(sn_hotplug_mutex);
92 92
93static ssize_t path_show (struct hotplug_slot *bss_hotplug_slot, 93static ssize_t path_show(struct pci_slot *pci_slot, char *buf)
94 char *buf)
95{ 94{
96 int retval = -ENOENT; 95 int retval = -ENOENT;
97 struct slot *slot = bss_hotplug_slot->private; 96 struct slot *slot = pci_slot->hotplug->private;
98 97
99 if (!slot) 98 if (!slot)
100 return retval; 99 return retval;
@@ -103,7 +102,7 @@ static ssize_t path_show (struct hotplug_slot *bss_hotplug_slot,
103 return retval; 102 return retval;
104} 103}
105 104
106static struct hotplug_slot_attribute sn_slot_path_attr = __ATTR_RO(path); 105static struct pci_slot_attribute sn_slot_path_attr = __ATTR_RO(path);
107 106
108static int sn_pci_slot_valid(struct pci_bus *pci_bus, int device) 107static int sn_pci_slot_valid(struct pci_bus *pci_bus, int device)
109{ 108{
diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c
index ebc9b8dca881..2314ad7ee5fe 100644
--- a/drivers/pci/intel-iommu.c
+++ b/drivers/pci/intel-iommu.c
@@ -1505,7 +1505,6 @@ static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1505 } 1505 }
1506 1506
1507 set_bit(num, iommu->domain_ids); 1507 set_bit(num, iommu->domain_ids);
1508 set_bit(iommu->seq_id, &domain->iommu_bmp);
1509 iommu->domains[num] = domain; 1508 iommu->domains[num] = domain;
1510 id = num; 1509 id = num;
1511 } 1510 }
@@ -1648,6 +1647,14 @@ static int domain_context_mapped(struct pci_dev *pdev)
1648 tmp->devfn); 1647 tmp->devfn);
1649} 1648}
1650 1649
1650/* Returns a number of VTD pages, but aligned to MM page size */
1651static inline unsigned long aligned_nrpages(unsigned long host_addr,
1652 size_t size)
1653{
1654 host_addr &= ~PAGE_MASK;
1655 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1656}
1657
1651static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, 1658static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1652 struct scatterlist *sg, unsigned long phys_pfn, 1659 struct scatterlist *sg, unsigned long phys_pfn,
1653 unsigned long nr_pages, int prot) 1660 unsigned long nr_pages, int prot)
@@ -1675,7 +1682,7 @@ static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1675 uint64_t tmp; 1682 uint64_t tmp;
1676 1683
1677 if (!sg_res) { 1684 if (!sg_res) {
1678 sg_res = (sg->offset + sg->length + VTD_PAGE_SIZE - 1) >> VTD_PAGE_SHIFT; 1685 sg_res = aligned_nrpages(sg->offset, sg->length);
1679 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset; 1686 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1680 sg->dma_length = sg->length; 1687 sg->dma_length = sg->length;
1681 pteval = page_to_phys(sg_page(sg)) | prot; 1688 pteval = page_to_phys(sg_page(sg)) | prot;
@@ -2415,14 +2422,6 @@ error:
2415 return ret; 2422 return ret;
2416} 2423}
2417 2424
2418/* Returns a number of VTD pages, but aligned to MM page size */
2419static inline unsigned long aligned_nrpages(unsigned long host_addr,
2420 size_t size)
2421{
2422 host_addr &= ~PAGE_MASK;
2423 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
2424}
2425
2426/* This takes a number of _MM_ pages, not VTD pages */ 2425/* This takes a number of _MM_ pages, not VTD pages */
2427static struct iova *intel_alloc_iova(struct device *dev, 2426static struct iova *intel_alloc_iova(struct device *dev,
2428 struct dmar_domain *domain, 2427 struct dmar_domain *domain,
@@ -2551,6 +2550,7 @@ static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2551 int prot = 0; 2550 int prot = 0;
2552 int ret; 2551 int ret;
2553 struct intel_iommu *iommu; 2552 struct intel_iommu *iommu;
2553 unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
2554 2554
2555 BUG_ON(dir == DMA_NONE); 2555 BUG_ON(dir == DMA_NONE);
2556 2556
@@ -2585,7 +2585,7 @@ static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2585 * is not a big problem 2585 * is not a big problem
2586 */ 2586 */
2587 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo), 2587 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
2588 paddr >> VTD_PAGE_SHIFT, size, prot); 2588 mm_to_dma_pfn(paddr_pfn), size, prot);
2589 if (ret) 2589 if (ret)
2590 goto error; 2590 goto error;
2591 2591
@@ -2875,7 +2875,7 @@ static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int ne
2875 2875
2876 start_vpfn = mm_to_dma_pfn(iova->pfn_lo); 2876 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
2877 2877
2878 ret = domain_sg_mapping(domain, start_vpfn, sglist, mm_to_dma_pfn(size), prot); 2878 ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
2879 if (unlikely(ret)) { 2879 if (unlikely(ret)) {
2880 /* clear the page */ 2880 /* clear the page */
2881 dma_pte_clear_range(domain, start_vpfn, 2881 dma_pte_clear_range(domain, start_vpfn,
@@ -3408,6 +3408,7 @@ static int md_domain_init(struct dmar_domain *domain, int guest_width)
3408 3408
3409 domain->iommu_count = 0; 3409 domain->iommu_count = 0;
3410 domain->iommu_coherency = 0; 3410 domain->iommu_coherency = 0;
3411 domain->iommu_snooping = 0;
3411 domain->max_addr = 0; 3412 domain->max_addr = 0;
3412 3413
3413 /* always allocate the top pgd */ 3414 /* always allocate the top pgd */
diff --git a/drivers/serial/s3c2400.c b/drivers/serial/s3c2400.c
index fb00ed5296e6..fed1a9a1ffb4 100644
--- a/drivers/serial/s3c2400.c
+++ b/drivers/serial/s3c2400.c
@@ -76,7 +76,7 @@ static int s3c2400_serial_probe(struct platform_device *dev)
76 return s3c24xx_serial_probe(dev, &s3c2400_uart_inf); 76 return s3c24xx_serial_probe(dev, &s3c2400_uart_inf);
77} 77}
78 78
79static struct platform_driver s3c2400_serial_drv = { 79static struct platform_driver s3c2400_serial_driver = {
80 .probe = s3c2400_serial_probe, 80 .probe = s3c2400_serial_probe,
81 .remove = __devexit_p(s3c24xx_serial_remove), 81 .remove = __devexit_p(s3c24xx_serial_remove),
82 .driver = { 82 .driver = {
@@ -85,16 +85,16 @@ static struct platform_driver s3c2400_serial_drv = {
85 }, 85 },
86}; 86};
87 87
88s3c24xx_console_init(&s3c2400_serial_drv, &s3c2400_uart_inf); 88s3c24xx_console_init(&s3c2400_serial_driver, &s3c2400_uart_inf);
89 89
90static inline int s3c2400_serial_init(void) 90static inline int s3c2400_serial_init(void)
91{ 91{
92 return s3c24xx_serial_init(&s3c2400_serial_drv, &s3c2400_uart_inf); 92 return s3c24xx_serial_init(&s3c2400_serial_driver, &s3c2400_uart_inf);
93} 93}
94 94
95static inline void s3c2400_serial_exit(void) 95static inline void s3c2400_serial_exit(void)
96{ 96{
97 platform_driver_unregister(&s3c2400_serial_drv); 97 platform_driver_unregister(&s3c2400_serial_driver);
98} 98}
99 99
100module_init(s3c2400_serial_init); 100module_init(s3c2400_serial_init);
diff --git a/drivers/serial/s3c2410.c b/drivers/serial/s3c2410.c
index b5d7cbcba2ae..c99f0821cae3 100644
--- a/drivers/serial/s3c2410.c
+++ b/drivers/serial/s3c2410.c
@@ -88,7 +88,7 @@ static int s3c2410_serial_probe(struct platform_device *dev)
88 return s3c24xx_serial_probe(dev, &s3c2410_uart_inf); 88 return s3c24xx_serial_probe(dev, &s3c2410_uart_inf);
89} 89}
90 90
91static struct platform_driver s3c2410_serial_drv = { 91static struct platform_driver s3c2410_serial_driver = {
92 .probe = s3c2410_serial_probe, 92 .probe = s3c2410_serial_probe,
93 .remove = __devexit_p(s3c24xx_serial_remove), 93 .remove = __devexit_p(s3c24xx_serial_remove),
94 .driver = { 94 .driver = {
@@ -97,16 +97,16 @@ static struct platform_driver s3c2410_serial_drv = {
97 }, 97 },
98}; 98};
99 99
100s3c24xx_console_init(&s3c2410_serial_drv, &s3c2410_uart_inf); 100s3c24xx_console_init(&s3c2410_serial_driver, &s3c2410_uart_inf);
101 101
102static int __init s3c2410_serial_init(void) 102static int __init s3c2410_serial_init(void)
103{ 103{
104 return s3c24xx_serial_init(&s3c2410_serial_drv, &s3c2410_uart_inf); 104 return s3c24xx_serial_init(&s3c2410_serial_driver, &s3c2410_uart_inf);
105} 105}
106 106
107static void __exit s3c2410_serial_exit(void) 107static void __exit s3c2410_serial_exit(void)
108{ 108{
109 platform_driver_unregister(&s3c2410_serial_drv); 109 platform_driver_unregister(&s3c2410_serial_driver);
110} 110}
111 111
112module_init(s3c2410_serial_init); 112module_init(s3c2410_serial_init);
diff --git a/drivers/serial/s3c2412.c b/drivers/serial/s3c2412.c
index 11dcb90bdfef..6e057d8809d3 100644
--- a/drivers/serial/s3c2412.c
+++ b/drivers/serial/s3c2412.c
@@ -121,7 +121,7 @@ static int s3c2412_serial_probe(struct platform_device *dev)
121 return s3c24xx_serial_probe(dev, &s3c2412_uart_inf); 121 return s3c24xx_serial_probe(dev, &s3c2412_uart_inf);
122} 122}
123 123
124static struct platform_driver s3c2412_serial_drv = { 124static struct platform_driver s3c2412_serial_driver = {
125 .probe = s3c2412_serial_probe, 125 .probe = s3c2412_serial_probe,
126 .remove = __devexit_p(s3c24xx_serial_remove), 126 .remove = __devexit_p(s3c24xx_serial_remove),
127 .driver = { 127 .driver = {
@@ -130,16 +130,16 @@ static struct platform_driver s3c2412_serial_drv = {
130 }, 130 },
131}; 131};
132 132
133s3c24xx_console_init(&s3c2412_serial_drv, &s3c2412_uart_inf); 133s3c24xx_console_init(&s3c2412_serial_driver, &s3c2412_uart_inf);
134 134
135static inline int s3c2412_serial_init(void) 135static inline int s3c2412_serial_init(void)
136{ 136{
137 return s3c24xx_serial_init(&s3c2412_serial_drv, &s3c2412_uart_inf); 137 return s3c24xx_serial_init(&s3c2412_serial_driver, &s3c2412_uart_inf);
138} 138}
139 139
140static inline void s3c2412_serial_exit(void) 140static inline void s3c2412_serial_exit(void)
141{ 141{
142 platform_driver_unregister(&s3c2412_serial_drv); 142 platform_driver_unregister(&s3c2412_serial_driver);
143} 143}
144 144
145module_init(s3c2412_serial_init); 145module_init(s3c2412_serial_init);
diff --git a/drivers/serial/s3c2440.c b/drivers/serial/s3c2440.c
index 06c5b0cc47a3..69ff5d340f04 100644
--- a/drivers/serial/s3c2440.c
+++ b/drivers/serial/s3c2440.c
@@ -151,7 +151,7 @@ static int s3c2440_serial_probe(struct platform_device *dev)
151 return s3c24xx_serial_probe(dev, &s3c2440_uart_inf); 151 return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
152} 152}
153 153
154static struct platform_driver s3c2440_serial_drv = { 154static struct platform_driver s3c2440_serial_driver = {
155 .probe = s3c2440_serial_probe, 155 .probe = s3c2440_serial_probe,
156 .remove = __devexit_p(s3c24xx_serial_remove), 156 .remove = __devexit_p(s3c24xx_serial_remove),
157 .driver = { 157 .driver = {
@@ -160,16 +160,16 @@ static struct platform_driver s3c2440_serial_drv = {
160 }, 160 },
161}; 161};
162 162
163s3c24xx_console_init(&s3c2440_serial_drv, &s3c2440_uart_inf); 163s3c24xx_console_init(&s3c2440_serial_driver, &s3c2440_uart_inf);
164 164
165static int __init s3c2440_serial_init(void) 165static int __init s3c2440_serial_init(void)
166{ 166{
167 return s3c24xx_serial_init(&s3c2440_serial_drv, &s3c2440_uart_inf); 167 return s3c24xx_serial_init(&s3c2440_serial_driver, &s3c2440_uart_inf);
168} 168}
169 169
170static void __exit s3c2440_serial_exit(void) 170static void __exit s3c2440_serial_exit(void)
171{ 171{
172 platform_driver_unregister(&s3c2440_serial_drv); 172 platform_driver_unregister(&s3c2440_serial_driver);
173} 173}
174 174
175module_init(s3c2440_serial_init); 175module_init(s3c2440_serial_init);
diff --git a/drivers/serial/s3c24a0.c b/drivers/serial/s3c24a0.c
index 786a067d62ac..26c49e18bdd1 100644
--- a/drivers/serial/s3c24a0.c
+++ b/drivers/serial/s3c24a0.c
@@ -92,7 +92,7 @@ static int s3c24a0_serial_probe(struct platform_device *dev)
92 return s3c24xx_serial_probe(dev, &s3c24a0_uart_inf); 92 return s3c24xx_serial_probe(dev, &s3c24a0_uart_inf);
93} 93}
94 94
95static struct platform_driver s3c24a0_serial_drv = { 95static struct platform_driver s3c24a0_serial_driver = {
96 .probe = s3c24a0_serial_probe, 96 .probe = s3c24a0_serial_probe,
97 .remove = __devexit_p(s3c24xx_serial_remove), 97 .remove = __devexit_p(s3c24xx_serial_remove),
98 .driver = { 98 .driver = {
@@ -101,16 +101,16 @@ static struct platform_driver s3c24a0_serial_drv = {
101 }, 101 },
102}; 102};
103 103
104s3c24xx_console_init(&s3c24a0_serial_drv, &s3c24a0_uart_inf); 104s3c24xx_console_init(&s3c24a0_serial_driver, &s3c24a0_uart_inf);
105 105
106static int __init s3c24a0_serial_init(void) 106static int __init s3c24a0_serial_init(void)
107{ 107{
108 return s3c24xx_serial_init(&s3c24a0_serial_drv, &s3c24a0_uart_inf); 108 return s3c24xx_serial_init(&s3c24a0_serial_driver, &s3c24a0_uart_inf);
109} 109}
110 110
111static void __exit s3c24a0_serial_exit(void) 111static void __exit s3c24a0_serial_exit(void)
112{ 112{
113 platform_driver_unregister(&s3c24a0_serial_drv); 113 platform_driver_unregister(&s3c24a0_serial_driver);
114} 114}
115 115
116module_init(s3c24a0_serial_init); 116module_init(s3c24a0_serial_init);
diff --git a/drivers/serial/s3c6400.c b/drivers/serial/s3c6400.c
index 48f1a3781f0d..4be92ab50058 100644
--- a/drivers/serial/s3c6400.c
+++ b/drivers/serial/s3c6400.c
@@ -122,7 +122,7 @@ static int s3c6400_serial_probe(struct platform_device *dev)
122 return s3c24xx_serial_probe(dev, &s3c6400_uart_inf); 122 return s3c24xx_serial_probe(dev, &s3c6400_uart_inf);
123} 123}
124 124
125static struct platform_driver s3c6400_serial_drv = { 125static struct platform_driver s3c6400_serial_driver = {
126 .probe = s3c6400_serial_probe, 126 .probe = s3c6400_serial_probe,
127 .remove = __devexit_p(s3c24xx_serial_remove), 127 .remove = __devexit_p(s3c24xx_serial_remove),
128 .driver = { 128 .driver = {
@@ -131,16 +131,16 @@ static struct platform_driver s3c6400_serial_drv = {
131 }, 131 },
132}; 132};
133 133
134s3c24xx_console_init(&s3c6400_serial_drv, &s3c6400_uart_inf); 134s3c24xx_console_init(&s3c6400_serial_driver, &s3c6400_uart_inf);
135 135
136static int __init s3c6400_serial_init(void) 136static int __init s3c6400_serial_init(void)
137{ 137{
138 return s3c24xx_serial_init(&s3c6400_serial_drv, &s3c6400_uart_inf); 138 return s3c24xx_serial_init(&s3c6400_serial_driver, &s3c6400_uart_inf);
139} 139}
140 140
141static void __exit s3c6400_serial_exit(void) 141static void __exit s3c6400_serial_exit(void)
142{ 142{
143 platform_driver_unregister(&s3c6400_serial_drv); 143 platform_driver_unregister(&s3c6400_serial_driver);
144} 144}
145 145
146module_init(s3c6400_serial_init); 146module_init(s3c6400_serial_init);
diff --git a/drivers/serial/serial_ks8695.c b/drivers/serial/serial_ks8695.c
index 998e89dc5aaf..e0665630e4da 100644
--- a/drivers/serial/serial_ks8695.c
+++ b/drivers/serial/serial_ks8695.c
@@ -549,7 +549,7 @@ static struct uart_port ks8695uart_ports[SERIAL_KS8695_NR] = {
549 .mapbase = KS8695_UART_VA, 549 .mapbase = KS8695_UART_VA,
550 .iotype = SERIAL_IO_MEM, 550 .iotype = SERIAL_IO_MEM,
551 .irq = KS8695_IRQ_UART_TX, 551 .irq = KS8695_IRQ_UART_TX,
552 .uartclk = CLOCK_TICK_RATE * 16, 552 .uartclk = KS8695_CLOCK_RATE * 16,
553 .fifosize = 16, 553 .fifosize = 16,
554 .ops = &ks8695uart_pops, 554 .ops = &ks8695uart_pops,
555 .flags = ASYNC_BOOT_AUTOCONF, 555 .flags = ASYNC_BOOT_AUTOCONF,
diff --git a/drivers/staging/b3dfg/Kconfig b/drivers/staging/b3dfg/Kconfig
index 524231047de5..9e6573cf97d3 100644
--- a/drivers/staging/b3dfg/Kconfig
+++ b/drivers/staging/b3dfg/Kconfig
@@ -1,5 +1,6 @@
1config B3DFG 1config B3DFG
2 tristate "Brontes 3d Frame Framegrabber" 2 tristate "Brontes 3d Frame Framegrabber"
3 depends on PCI
3 default n 4 default n
4 ---help--- 5 ---help---
5 This driver provides support for the Brontes 3d Framegrabber 6 This driver provides support for the Brontes 3d Framegrabber
diff --git a/drivers/staging/heci/Kconfig b/drivers/staging/heci/Kconfig
index ae8d588d3a27..c7206f8bcd93 100644
--- a/drivers/staging/heci/Kconfig
+++ b/drivers/staging/heci/Kconfig
@@ -1,5 +1,6 @@
1config HECI 1config HECI
2 tristate "Intel Management Engine Interface (MEI) Support" 2 tristate "Intel Management Engine Interface (MEI) Support"
3 depends on PCI
3 ---help--- 4 ---help---
4 The Intel Management Engine Interface (Intel MEI) driver allows 5 The Intel Management Engine Interface (Intel MEI) driver allows
5 applications to access the Active Management Technology 6 applications to access the Active Management Technology
diff --git a/drivers/staging/rspiusb/rspiusb.c b/drivers/staging/rspiusb/rspiusb.c
index 2f8155c1968b..04e2f92c0f62 100644
--- a/drivers/staging/rspiusb/rspiusb.c
+++ b/drivers/staging/rspiusb/rspiusb.c
@@ -716,6 +716,8 @@ static int MapUserBuffer(struct ioctl_struct *io, struct device_extension *pdx)
716 pdx->PixelUrb[frameInfo][i]->transfer_flags = 716 pdx->PixelUrb[frameInfo][i]->transfer_flags =
717 URB_NO_TRANSFER_DMA_MAP | URB_NO_INTERRUPT; 717 URB_NO_TRANSFER_DMA_MAP | URB_NO_INTERRUPT;
718 } 718 }
719 if (i == 0)
720 return -EINVAL;
719 /* only interrupt when last URB completes */ 721 /* only interrupt when last URB completes */
720 pdx->PixelUrb[frameInfo][--i]->transfer_flags &= ~URB_NO_INTERRUPT; 722 pdx->PixelUrb[frameInfo][--i]->transfer_flags &= ~URB_NO_INTERRUPT;
721 pdx->pendedPixelUrbs[frameInfo] = 723 pdx->pendedPixelUrbs[frameInfo] =
diff --git a/drivers/staging/rt2860/rt_linux.h b/drivers/staging/rt2860/rt_linux.h
index 85175c182432..25b53ac3f820 100644
--- a/drivers/staging/rt2860/rt_linux.h
+++ b/drivers/staging/rt2860/rt_linux.h
@@ -43,9 +43,6 @@
43#include "rtmp_type.h" 43#include "rtmp_type.h"
44#include <linux/module.h> 44#include <linux/module.h>
45#include <linux/kernel.h> 45#include <linux/kernel.h>
46#if !defined(RT2860) && !defined(RT30xx)
47#include <linux/kthread.h>
48#endif
49 46
50#include <linux/spinlock.h> 47#include <linux/spinlock.h>
51#include <linux/init.h> 48#include <linux/init.h>
@@ -166,9 +163,7 @@ typedef int (*HARD_START_XMIT_FUNC)(struct sk_buff *skb, struct net_device *net_
166 163
167#ifndef RT30xx 164#ifndef RT30xx
168typedef struct pid * THREAD_PID; 165typedef struct pid * THREAD_PID;
169#ifdef RT2860
170#define THREAD_PID_INIT_VALUE NULL 166#define THREAD_PID_INIT_VALUE NULL
171#endif
172#define GET_PID(_v) find_get_pid(_v) 167#define GET_PID(_v) find_get_pid(_v)
173#define GET_PID_NUMBER(_v) pid_nr(_v) 168#define GET_PID_NUMBER(_v) pid_nr(_v)
174#define CHECK_PID_LEGALITY(_pid) if (pid_nr(_pid) >= 0) 169#define CHECK_PID_LEGALITY(_pid) if (pid_nr(_pid) >= 0)
@@ -188,12 +183,12 @@ struct os_cookie {
188 dma_addr_t pAd_pa; 183 dma_addr_t pAd_pa;
189#endif 184#endif
190#ifdef RT2870 185#ifdef RT2870
191 struct usb_device *pUsb_Dev; 186 struct usb_device *pUsb_Dev;
192 187
193#ifndef RT30xx 188#ifndef RT30xx
194 struct task_struct *MLMEThr_task; 189 THREAD_PID MLMEThr_pid;
195 struct task_struct *RTUSBCmdThr_task; 190 THREAD_PID RTUSBCmdThr_pid;
196 struct task_struct *TimerQThr_task; 191 THREAD_PID TimerQThr_pid;
197#endif 192#endif
198#ifdef RT30xx 193#ifdef RT30xx
199 struct pid *MLMEThr_pid; 194 struct pid *MLMEThr_pid;
diff --git a/drivers/staging/rt2870/2870_main_dev.c b/drivers/staging/rt2870/2870_main_dev.c
index dd01c64fbf61..a4e8696ca39c 100644
--- a/drivers/staging/rt2870/2870_main_dev.c
+++ b/drivers/staging/rt2870/2870_main_dev.c
@@ -235,7 +235,7 @@ INT MlmeThread(
235 DBGPRINT(RT_DEBUG_TRACE,( "<---%s\n",__func__)); 235 DBGPRINT(RT_DEBUG_TRACE,( "<---%s\n",__func__));
236 236
237#ifndef RT30xx 237#ifndef RT30xx
238 pObj->MLMEThr_task = NULL; 238 pObj->MLMEThr_pid = THREAD_PID_INIT_VALUE;
239#endif 239#endif
240#ifdef RT30xx 240#ifdef RT30xx
241 pObj->MLMEThr_pid = NULL; 241 pObj->MLMEThr_pid = NULL;
@@ -348,7 +348,7 @@ INT RTUSBCmdThread(
348 DBGPRINT(RT_DEBUG_TRACE,( "<---RTUSBCmdThread\n")); 348 DBGPRINT(RT_DEBUG_TRACE,( "<---RTUSBCmdThread\n"));
349 349
350#ifndef RT30xx 350#ifndef RT30xx
351 pObj->RTUSBCmdThr_task = NULL; 351 pObj->RTUSBCmdThr_pid = THREAD_PID_INIT_VALUE;
352#endif 352#endif
353#ifdef RT30xx 353#ifdef RT30xx
354 pObj->RTUSBCmdThr_pid = NULL; 354 pObj->RTUSBCmdThr_pid = NULL;
@@ -447,7 +447,7 @@ INT TimerQThread(
447 DBGPRINT(RT_DEBUG_TRACE,( "<---%s\n",__func__)); 447 DBGPRINT(RT_DEBUG_TRACE,( "<---%s\n",__func__));
448 448
449#ifndef RT30xx 449#ifndef RT30xx
450 pObj->TimerQThr_task = NULL; 450 pObj->TimerQThr_pid = THREAD_PID_INIT_VALUE;
451#endif 451#endif
452#ifdef RT30xx 452#ifdef RT30xx
453 pObj->TimerQThr_pid = NULL; 453 pObj->TimerQThr_pid = NULL;
@@ -883,46 +883,69 @@ VOID RT28xxThreadTerminate(
883 883
884 // Terminate Threads 884 // Terminate Threads
885#ifndef RT30xx 885#ifndef RT30xx
886 BUG_ON(pObj->TimerQThr_task == NULL); 886 CHECK_PID_LEGALITY(pObj->TimerQThr_pid)
887 CHECK_PID_LEGALITY(task_pid(pObj->TimerQThr_task))
888 { 887 {
889 POS_COOKIE pObj = (POS_COOKIE)pAd->OS_Cookie; 888 POS_COOKIE pObj = (POS_COOKIE)pAd->OS_Cookie;
890 889
891 printk(KERN_DEBUG "Terminate the TimerQThr pid=%d!\n", 890 printk("Terminate the TimerQThr_pid=%d!\n", GET_PID_NUMBER(pObj->TimerQThr_pid));
892 pid_nr(task_pid(pObj->TimerQThr_task)));
893 mb(); 891 mb();
894 pAd->TimerFunc_kill = 1; 892 pAd->TimerFunc_kill = 1;
895 mb(); 893 mb();
896 kthread_stop(pObj->TimerQThr_task); 894 ret = KILL_THREAD_PID(pObj->TimerQThr_pid, SIGTERM, 1);
897 pObj->TimerQThr_task = NULL; 895 if (ret)
896 {
897 printk(KERN_WARNING "%s: unable to stop TimerQThread, pid=%d, ret=%d!\n",
898 pAd->net_dev->name, GET_PID_NUMBER(pObj->TimerQThr_pid), ret);
899 }
900 else
901 {
902 wait_for_completion(&pAd->TimerQComplete);
903 pObj->TimerQThr_pid = THREAD_PID_INIT_VALUE;
904 }
898 } 905 }
899 906
900 BUG_ON(pObj->MLMEThr_task == NULL); 907 CHECK_PID_LEGALITY(pObj->MLMEThr_pid)
901 CHECK_PID_LEGALITY(task_pid(pObj->MLMEThr_task))
902 { 908 {
903 printk(KERN_DEBUG "Terminate the MLMEThr pid=%d!\n", 909 printk("Terminate the MLMEThr_pid=%d!\n", GET_PID_NUMBER(pObj->MLMEThr_pid));
904 pid_nr(task_pid(pObj->MLMEThr_task)));
905 mb(); 910 mb();
906 pAd->mlme_kill = 1; 911 pAd->mlme_kill = 1;
907 //RT28XX_MLME_HANDLER(pAd); 912 //RT28XX_MLME_HANDLER(pAd);
908 mb(); 913 mb();
909 kthread_stop(pObj->MLMEThr_task); 914 ret = KILL_THREAD_PID(pObj->MLMEThr_pid, SIGTERM, 1);
910 pObj->MLMEThr_task = NULL; 915 if (ret)
916 {
917 printk (KERN_WARNING "%s: unable to Mlme thread, pid=%d, ret=%d!\n",
918 pAd->net_dev->name, GET_PID_NUMBER(pObj->MLMEThr_pid), ret);
919 }
920 else
921 {
922 //wait_for_completion (&pAd->notify);
923 wait_for_completion (&pAd->mlmeComplete);
924 pObj->MLMEThr_pid = THREAD_PID_INIT_VALUE;
925 }
911 } 926 }
912 927
913 BUG_ON(pObj->RTUSBCmdThr_task == NULL); 928 CHECK_PID_LEGALITY(pObj->RTUSBCmdThr_pid)
914 CHECK_PID_LEGALITY(task_pid(pObj->RTUSBCmdThr_task))
915 { 929 {
916 printk(KERN_DEBUG "Terminate the RTUSBCmdThr pid=%d!\n", 930 printk("Terminate the RTUSBCmdThr_pid=%d!\n", GET_PID_NUMBER(pObj->RTUSBCmdThr_pid));
917 pid_nr(task_pid(pObj->RTUSBCmdThr_task)));
918 mb(); 931 mb();
919 NdisAcquireSpinLock(&pAd->CmdQLock); 932 NdisAcquireSpinLock(&pAd->CmdQLock);
920 pAd->CmdQ.CmdQState = RT2870_THREAD_STOPED; 933 pAd->CmdQ.CmdQState = RT2870_THREAD_STOPED;
921 NdisReleaseSpinLock(&pAd->CmdQLock); 934 NdisReleaseSpinLock(&pAd->CmdQLock);
922 mb(); 935 mb();
923 //RTUSBCMDUp(pAd); 936 //RTUSBCMDUp(pAd);
924 kthread_stop(pObj->RTUSBCmdThr_task); 937 ret = KILL_THREAD_PID(pObj->RTUSBCmdThr_pid, SIGTERM, 1);
925 pObj->RTUSBCmdThr_task = NULL; 938 if (ret)
939 {
940 printk(KERN_WARNING "%s: unable to RTUSBCmd thread, pid=%d, ret=%d!\n",
941 pAd->net_dev->name, GET_PID_NUMBER(pObj->RTUSBCmdThr_pid), ret);
942 }
943 else
944 {
945 //wait_for_completion (&pAd->notify);
946 wait_for_completion (&pAd->CmdQComplete);
947 pObj->RTUSBCmdThr_pid = THREAD_PID_INIT_VALUE;
948 }
926 } 949 }
927#endif 950#endif
928#ifdef RT30xx 951#ifdef RT30xx
@@ -1045,7 +1068,7 @@ BOOLEAN RT28XXChipsetCheck(
1045 dev_p->descriptor.idProduct == rtusb_usb_id[i].idProduct) 1068 dev_p->descriptor.idProduct == rtusb_usb_id[i].idProduct)
1046 { 1069 {
1047#ifndef RT30xx 1070#ifndef RT30xx
1048 printk(KERN_DEBUG "rt2870: idVendor = 0x%x, idProduct = 0x%x\n", 1071 printk("rt2870: idVendor = 0x%x, idProduct = 0x%x\n",
1049#endif 1072#endif
1050#ifdef RT30xx 1073#ifdef RT30xx
1051 printk("rt2870: idVendor = 0x%x, idProduct = 0x%x\n", 1074 printk("rt2870: idVendor = 0x%x, idProduct = 0x%x\n",
diff --git a/drivers/staging/rt2870/common/2870_rtmp_init.c b/drivers/staging/rt2870/common/2870_rtmp_init.c
index 0f4c8af97e47..80909e9ab5ae 100644
--- a/drivers/staging/rt2870/common/2870_rtmp_init.c
+++ b/drivers/staging/rt2870/common/2870_rtmp_init.c
@@ -700,8 +700,8 @@ NDIS_STATUS AdapterBlockAllocateMemory(
700 usb_dev = pObj->pUsb_Dev; 700 usb_dev = pObj->pUsb_Dev;
701 701
702#ifndef RT30xx 702#ifndef RT30xx
703 pObj->MLMEThr_task = NULL; 703 pObj->MLMEThr_pid = THREAD_PID_INIT_VALUE;
704 pObj->RTUSBCmdThr_task = NULL; 704 pObj->RTUSBCmdThr_pid = THREAD_PID_INIT_VALUE;
705#endif 705#endif
706#ifdef RT30xx 706#ifdef RT30xx
707 pObj->MLMEThr_pid = NULL; 707 pObj->MLMEThr_pid = NULL;
@@ -743,7 +743,7 @@ NDIS_STATUS CreateThreads(
743 PRTMP_ADAPTER pAd = net_dev->ml_priv; 743 PRTMP_ADAPTER pAd = net_dev->ml_priv;
744 POS_COOKIE pObj = (POS_COOKIE) pAd->OS_Cookie; 744 POS_COOKIE pObj = (POS_COOKIE) pAd->OS_Cookie;
745#ifndef RT30xx 745#ifndef RT30xx
746 struct task_struct *tsk; 746 pid_t pid_number = -1;
747#endif 747#endif
748#ifdef RT30xx 748#ifdef RT30xx
749 pid_t pid_number; 749 pid_t pid_number;
@@ -762,10 +762,10 @@ NDIS_STATUS CreateThreads(
762 762
763 // Creat MLME Thread 763 // Creat MLME Thread
764#ifndef RT30xx 764#ifndef RT30xx
765 pObj->MLMEThr_task = NULL; 765 pObj->MLMEThr_pid= THREAD_PID_INIT_VALUE;
766 tsk = kthread_run(MlmeThread, pAd, "%s", pAd->net_dev->name); 766 pid_number = kernel_thread(MlmeThread, pAd, CLONE_VM);
767 767 if (pid_number < 0)
768 if (IS_ERR(tsk)) { 768 {
769#endif 769#endif
770#ifdef RT30xx 770#ifdef RT30xx
771 pObj->MLMEThr_pid = NULL; 771 pObj->MLMEThr_pid = NULL;
@@ -778,7 +778,7 @@ NDIS_STATUS CreateThreads(
778 } 778 }
779 779
780#ifndef RT30xx 780#ifndef RT30xx
781 pObj->MLMEThr_task = tsk; 781 pObj->MLMEThr_pid = GET_PID(pid_number);
782#endif 782#endif
783#ifdef RT30xx 783#ifdef RT30xx
784 pObj->MLMEThr_pid = find_get_pid(pid_number); 784 pObj->MLMEThr_pid = find_get_pid(pid_number);
@@ -788,10 +788,9 @@ NDIS_STATUS CreateThreads(
788 788
789 // Creat Command Thread 789 // Creat Command Thread
790#ifndef RT30xx 790#ifndef RT30xx
791 pObj->RTUSBCmdThr_task = NULL; 791 pObj->RTUSBCmdThr_pid= THREAD_PID_INIT_VALUE;
792 tsk = kthread_run(RTUSBCmdThread, pAd, "%s", pAd->net_dev->name); 792 pid_number = kernel_thread(RTUSBCmdThread, pAd, CLONE_VM);
793 793 if (pid_number < 0)
794 if (IS_ERR(tsk) < 0)
795#endif 794#endif
796#ifdef RT30xx 795#ifdef RT30xx
797 pObj->RTUSBCmdThr_pid = NULL; 796 pObj->RTUSBCmdThr_pid = NULL;
@@ -804,7 +803,7 @@ NDIS_STATUS CreateThreads(
804 } 803 }
805 804
806#ifndef RT30xx 805#ifndef RT30xx
807 pObj->RTUSBCmdThr_task = tsk; 806 pObj->RTUSBCmdThr_pid = GET_PID(pid_number);
808#endif 807#endif
809#ifdef RT30xx 808#ifdef RT30xx
810 pObj->RTUSBCmdThr_pid = find_get_pid(pid_number); 809 pObj->RTUSBCmdThr_pid = find_get_pid(pid_number);
@@ -812,9 +811,9 @@ NDIS_STATUS CreateThreads(
812 wait_for_completion(&(pAd->CmdQComplete)); 811 wait_for_completion(&(pAd->CmdQComplete));
813 812
814#ifndef RT30xx 813#ifndef RT30xx
815 pObj->TimerQThr_task = NULL; 814 pObj->TimerQThr_pid= THREAD_PID_INIT_VALUE;
816 tsk = kthread_run(TimerQThread, pAd, "%s", pAd->net_dev->name); 815 pid_number = kernel_thread(TimerQThread, pAd, CLONE_VM);
817 if (IS_ERR(tsk) < 0) 816 if (pid_number < 0)
818#endif 817#endif
819#ifdef RT30xx 818#ifdef RT30xx
820 pObj->TimerQThr_pid = NULL; 819 pObj->TimerQThr_pid = NULL;
@@ -826,7 +825,7 @@ NDIS_STATUS CreateThreads(
826 return NDIS_STATUS_FAILURE; 825 return NDIS_STATUS_FAILURE;
827 } 826 }
828#ifndef RT30xx 827#ifndef RT30xx
829 pObj->TimerQThr_task = tsk; 828 pObj->TimerQThr_pid = GET_PID(pid_number);
830#endif 829#endif
831#ifdef RT30xx 830#ifdef RT30xx
832 pObj->TimerQThr_pid = find_get_pid(pid_number); 831 pObj->TimerQThr_pid = find_get_pid(pid_number);
diff --git a/drivers/staging/rt2870/common/rtusb_io.c b/drivers/staging/rt2870/common/rtusb_io.c
index fd1b0c18f2a0..704b5c2d5091 100644
--- a/drivers/staging/rt2870/common/rtusb_io.c
+++ b/drivers/staging/rt2870/common/rtusb_io.c
@@ -984,8 +984,7 @@ NDIS_STATUS RTUSBEnqueueCmdFromNdis(
984 POS_COOKIE pObj = (POS_COOKIE) pAd->OS_Cookie; 984 POS_COOKIE pObj = (POS_COOKIE) pAd->OS_Cookie;
985 985
986#ifndef RT30xx 986#ifndef RT30xx
987 BUG_ON(pObj->RTUSBCmdThr_task == NULL); 987 CHECK_PID_LEGALITY(pObj->RTUSBCmdThr_pid)
988 CHECK_PID_LEGALITY(task_pid(pObj->RTUSBCmdThr_task))
989#endif 988#endif
990#ifdef RT30xx 989#ifdef RT30xx
991 if (pObj->RTUSBCmdThr_pid < 0) 990 if (pObj->RTUSBCmdThr_pid < 0)
diff --git a/drivers/staging/rt2870/rt2870.h b/drivers/staging/rt2870/rt2870.h
index 29e3b53e52a1..2b8872b2fd9d 100644
--- a/drivers/staging/rt2870/rt2870.h
+++ b/drivers/staging/rt2870/rt2870.h
@@ -79,6 +79,7 @@
79{ \ 79{ \
80 {USB_DEVICE(0x148F,0x2770)}, /* Ralink */ \ 80 {USB_DEVICE(0x148F,0x2770)}, /* Ralink */ \
81 {USB_DEVICE(0x1737,0x0071)}, /* Linksys WUSB600N */ \ 81 {USB_DEVICE(0x1737,0x0071)}, /* Linksys WUSB600N */ \
82 {USB_DEVICE(0x1737,0x0070)}, /* Linksys */ \
82 {USB_DEVICE(0x148F,0x2870)}, /* Ralink */ \ 83 {USB_DEVICE(0x148F,0x2870)}, /* Ralink */ \
83 {USB_DEVICE(0x148F,0x3070)}, /* Ralink */ \ 84 {USB_DEVICE(0x148F,0x3070)}, /* Ralink */ \
84 {USB_DEVICE(0x0B05,0x1731)}, /* Asus */ \ 85 {USB_DEVICE(0x0B05,0x1731)}, /* Asus */ \
@@ -93,12 +94,14 @@
93 {USB_DEVICE(0x14B2,0x3C06)}, /* Conceptronic */ \ 94 {USB_DEVICE(0x14B2,0x3C06)}, /* Conceptronic */ \
94 {USB_DEVICE(0x14B2,0x3C28)}, /* Conceptronic */ \ 95 {USB_DEVICE(0x14B2,0x3C28)}, /* Conceptronic */ \
95 {USB_DEVICE(0x2019,0xED06)}, /* Planex Communications, Inc. */ \ 96 {USB_DEVICE(0x2019,0xED06)}, /* Planex Communications, Inc. */ \
97 {USB_DEVICE(0x2019,0xED14)}, /* Planex Communications, Inc. */ \
96 {USB_DEVICE(0x2019,0xAB25)}, /* Planex Communications, Inc. RT3070 */ \ 98 {USB_DEVICE(0x2019,0xAB25)}, /* Planex Communications, Inc. RT3070 */ \
97 {USB_DEVICE(0x07D1,0x3C09)}, /* D-Link */ \ 99 {USB_DEVICE(0x07D1,0x3C09)}, /* D-Link */ \
98 {USB_DEVICE(0x07D1,0x3C11)}, /* D-Link */ \ 100 {USB_DEVICE(0x07D1,0x3C11)}, /* D-Link */ \
99 {USB_DEVICE(0x14B2,0x3C07)}, /* AL */ \ 101 {USB_DEVICE(0x14B2,0x3C07)}, /* AL */ \
100 {USB_DEVICE(0x14B2,0x3C12)}, /* AL */ \ 102 {USB_DEVICE(0x14B2,0x3C12)}, /* AL */ \
101 {USB_DEVICE(0x050D,0x8053)}, /* Belkin */ \ 103 {USB_DEVICE(0x050D,0x8053)}, /* Belkin */ \
104 {USB_DEVICE(0x050D,0x815C)}, /* Belkin */ \
102 {USB_DEVICE(0x14B2,0x3C23)}, /* Airlink */ \ 105 {USB_DEVICE(0x14B2,0x3C23)}, /* Airlink */ \
103 {USB_DEVICE(0x14B2,0x3C27)}, /* Airlink */ \ 106 {USB_DEVICE(0x14B2,0x3C27)}, /* Airlink */ \
104 {USB_DEVICE(0x07AA,0x002F)}, /* Corega */ \ 107 {USB_DEVICE(0x07AA,0x002F)}, /* Corega */ \
@@ -587,16 +590,14 @@ VOID RTUSBBulkRxComplete(purbb_t pUrb, struct pt_regs *pt_regs);
587#define RTUSBMlmeUp(pAd) \ 590#define RTUSBMlmeUp(pAd) \
588{ \ 591{ \
589 POS_COOKIE pObj = (POS_COOKIE) pAd->OS_Cookie; \ 592 POS_COOKIE pObj = (POS_COOKIE) pAd->OS_Cookie; \
590 BUG_ON(pObj->MLMEThr_task == NULL); \ 593 CHECK_PID_LEGALITY(pObj->MLMEThr_pid) \
591 CHECK_PID_LEGALITY(task_pid(pObj->MLMEThr_task)) \
592 up(&(pAd->mlme_semaphore)); \ 594 up(&(pAd->mlme_semaphore)); \
593} 595}
594 596
595#define RTUSBCMDUp(pAd) \ 597#define RTUSBCMDUp(pAd) \
596{ \ 598{ \
597 POS_COOKIE pObj = (POS_COOKIE) pAd->OS_Cookie; \ 599 POS_COOKIE pObj = (POS_COOKIE) pAd->OS_Cookie; \
598 BUG_ON(pObj->RTUSBCmdThr_task == NULL); \ 600 CHECK_PID_LEGALITY(pObj->RTUSBCmdThr_pid) \
599 CHECK_PID_LEGALITY(task_pid(pObj->RTUSBCmdThr_task)) \
600 up(&(pAd->RTUSBCmd_semaphore)); \ 601 up(&(pAd->RTUSBCmd_semaphore)); \
601} 602}
602#endif 603#endif
diff --git a/drivers/staging/rtl8192su/ieee80211.h b/drivers/staging/rtl8192su/ieee80211.h
index 0edb09a536f9..ea9739318037 100644
--- a/drivers/staging/rtl8192su/ieee80211.h
+++ b/drivers/staging/rtl8192su/ieee80211.h
@@ -2645,7 +2645,7 @@ extern int ieee80211_encrypt_fragment(
2645 struct sk_buff *frag, 2645 struct sk_buff *frag,
2646 int hdr_len); 2646 int hdr_len);
2647 2647
2648extern int ieee80211_xmit(struct sk_buff *skb, 2648extern int rtl8192_ieee80211_xmit(struct sk_buff *skb,
2649 struct net_device *dev); 2649 struct net_device *dev);
2650extern void ieee80211_txb_free(struct ieee80211_txb *); 2650extern void ieee80211_txb_free(struct ieee80211_txb *);
2651 2651
diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211.h b/drivers/staging/rtl8192su/ieee80211/ieee80211.h
index 720bfcbfadc1..5e3a2cbed2b1 100644
--- a/drivers/staging/rtl8192su/ieee80211/ieee80211.h
+++ b/drivers/staging/rtl8192su/ieee80211/ieee80211.h
@@ -2645,7 +2645,7 @@ extern int ieee80211_encrypt_fragment(
2645 struct sk_buff *frag, 2645 struct sk_buff *frag,
2646 int hdr_len); 2646 int hdr_len);
2647 2647
2648extern int ieee80211_xmit(struct sk_buff *skb, 2648extern int rtl8192_ieee80211_xmit(struct sk_buff *skb,
2649 struct net_device *dev); 2649 struct net_device *dev);
2650extern void ieee80211_txb_free(struct ieee80211_txb *); 2650extern void ieee80211_txb_free(struct ieee80211_txb *);
2651 2651
diff --git a/drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c b/drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c
index 7294572b990f..cba12b84be5c 100644
--- a/drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c
+++ b/drivers/staging/rtl8192su/ieee80211/ieee80211_tx.c
@@ -618,7 +618,7 @@ void ieee80211_query_seqnum(struct ieee80211_device*ieee, struct sk_buff* skb, u
618 } 618 }
619} 619}
620 620
621int ieee80211_xmit(struct sk_buff *skb, struct net_device *dev) 621int rtl8192_ieee80211_xmit(struct sk_buff *skb, struct net_device *dev)
622{ 622{
623#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)) 623#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0))
624 struct ieee80211_device *ieee = netdev_priv(dev); 624 struct ieee80211_device *ieee = netdev_priv(dev);
@@ -943,5 +943,6 @@ int ieee80211_xmit(struct sk_buff *skb, struct net_device *dev)
943 return 1; 943 return 1;
944 944
945} 945}
946EXPORT_SYMBOL(rtl8192_ieee80211_xmit);
946 947
947EXPORT_SYMBOL(ieee80211_txb_free); 948EXPORT_SYMBOL(ieee80211_txb_free);
diff --git a/drivers/staging/rtl8192su/r8192U_core.c b/drivers/staging/rtl8192su/r8192U_core.c
index 4ab250743e81..70f81a8f1291 100644
--- a/drivers/staging/rtl8192su/r8192U_core.c
+++ b/drivers/staging/rtl8192su/r8192U_core.c
@@ -12142,7 +12142,7 @@ static const struct net_device_ops rtl8192_netdev_ops = {
12142 .ndo_set_mac_address = r8192_set_mac_adr, 12142 .ndo_set_mac_address = r8192_set_mac_adr,
12143 .ndo_validate_addr = eth_validate_addr, 12143 .ndo_validate_addr = eth_validate_addr,
12144 .ndo_change_mtu = eth_change_mtu, 12144 .ndo_change_mtu = eth_change_mtu,
12145 .ndo_start_xmit = ieee80211_xmit, 12145 .ndo_start_xmit = rtl8192_ieee80211_xmit,
12146}; 12146};
12147 12147
12148#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) 12148#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c
index e1f89416ef8c..2bfc41ece0e1 100644
--- a/drivers/usb/class/cdc-acm.c
+++ b/drivers/usb/class/cdc-acm.c
@@ -387,7 +387,6 @@ static void acm_rx_tasklet(unsigned long _acm)
387 struct acm_ru *rcv; 387 struct acm_ru *rcv;
388 unsigned long flags; 388 unsigned long flags;
389 unsigned char throttled; 389 unsigned char throttled;
390 struct usb_host_endpoint *ep;
391 390
392 dbg("Entering acm_rx_tasklet"); 391 dbg("Entering acm_rx_tasklet");
393 392
@@ -463,14 +462,12 @@ urbs:
463 462
464 rcv->buffer = buf; 463 rcv->buffer = buf;
465 464
466 ep = (usb_pipein(acm->rx_endpoint) ? acm->dev->ep_in : acm->dev->ep_out) 465 if (acm->is_int_ep)
467 [usb_pipeendpoint(acm->rx_endpoint)];
468 if (usb_endpoint_xfer_int(&ep->desc))
469 usb_fill_int_urb(rcv->urb, acm->dev, 466 usb_fill_int_urb(rcv->urb, acm->dev,
470 acm->rx_endpoint, 467 acm->rx_endpoint,
471 buf->base, 468 buf->base,
472 acm->readsize, 469 acm->readsize,
473 acm_read_bulk, rcv, ep->desc.bInterval); 470 acm_read_bulk, rcv, acm->bInterval);
474 else 471 else
475 usb_fill_bulk_urb(rcv->urb, acm->dev, 472 usb_fill_bulk_urb(rcv->urb, acm->dev,
476 acm->rx_endpoint, 473 acm->rx_endpoint,
@@ -1183,6 +1180,9 @@ made_compressed_probe:
1183 spin_lock_init(&acm->read_lock); 1180 spin_lock_init(&acm->read_lock);
1184 mutex_init(&acm->mutex); 1181 mutex_init(&acm->mutex);
1185 acm->rx_endpoint = usb_rcvbulkpipe(usb_dev, epread->bEndpointAddress); 1182 acm->rx_endpoint = usb_rcvbulkpipe(usb_dev, epread->bEndpointAddress);
1183 acm->is_int_ep = usb_endpoint_xfer_int(epread);
1184 if (acm->is_int_ep)
1185 acm->bInterval = epread->bInterval;
1186 tty_port_init(&acm->port); 1186 tty_port_init(&acm->port);
1187 acm->port.ops = &acm_port_ops; 1187 acm->port.ops = &acm_port_ops;
1188 1188
diff --git a/drivers/usb/class/cdc-acm.h b/drivers/usb/class/cdc-acm.h
index 1602324808ba..c4a0ee8ffccf 100644
--- a/drivers/usb/class/cdc-acm.h
+++ b/drivers/usb/class/cdc-acm.h
@@ -126,6 +126,8 @@ struct acm {
126 unsigned int ctrl_caps; /* control capabilities from the class specific header */ 126 unsigned int ctrl_caps; /* control capabilities from the class specific header */
127 unsigned int susp_count; /* number of suspended interfaces */ 127 unsigned int susp_count; /* number of suspended interfaces */
128 int combined_interfaces:1; /* control and data collapsed */ 128 int combined_interfaces:1; /* control and data collapsed */
129 int is_int_ep:1; /* interrupt endpoints contrary to spec used */
130 u8 bInterval;
129 struct acm_wb *delayed_wb; /* write queued for a device about to be woken */ 131 struct acm_wb *delayed_wb; /* write queued for a device about to be woken */
130}; 132};
131 133
diff --git a/drivers/usb/core/devio.c b/drivers/usb/core/devio.c
index 38b8bce782d6..4247eccf858c 100644
--- a/drivers/usb/core/devio.c
+++ b/drivers/usb/core/devio.c
@@ -595,7 +595,7 @@ static int usbdev_open(struct inode *inode, struct file *file)
595 if (!ps) 595 if (!ps)
596 goto out; 596 goto out;
597 597
598 ret = -ENOENT; 598 ret = -ENODEV;
599 599
600 /* usbdev device-node */ 600 /* usbdev device-node */
601 if (imajor(inode) == USB_DEVICE_MAJOR) 601 if (imajor(inode) == USB_DEVICE_MAJOR)
@@ -1321,7 +1321,8 @@ static int get_urb32(struct usbdevfs_urb *kurb,
1321 struct usbdevfs_urb32 __user *uurb) 1321 struct usbdevfs_urb32 __user *uurb)
1322{ 1322{
1323 __u32 uptr; 1323 __u32 uptr;
1324 if (get_user(kurb->type, &uurb->type) || 1324 if (!access_ok(VERIFY_READ, uurb, sizeof(*uurb)) ||
1325 __get_user(kurb->type, &uurb->type) ||
1325 __get_user(kurb->endpoint, &uurb->endpoint) || 1326 __get_user(kurb->endpoint, &uurb->endpoint) ||
1326 __get_user(kurb->status, &uurb->status) || 1327 __get_user(kurb->status, &uurb->status) ||
1327 __get_user(kurb->flags, &uurb->flags) || 1328 __get_user(kurb->flags, &uurb->flags) ||
@@ -1536,8 +1537,9 @@ static int proc_ioctl_compat(struct dev_state *ps, compat_uptr_t arg)
1536 u32 udata; 1537 u32 udata;
1537 1538
1538 uioc = compat_ptr((long)arg); 1539 uioc = compat_ptr((long)arg);
1539 if (get_user(ctrl.ifno, &uioc->ifno) || 1540 if (!access_ok(VERIFY_READ, uioc, sizeof(*uioc)) ||
1540 get_user(ctrl.ioctl_code, &uioc->ioctl_code) || 1541 __get_user(ctrl.ifno, &uioc->ifno) ||
1542 __get_user(ctrl.ioctl_code, &uioc->ioctl_code) ||
1541 __get_user(udata, &uioc->data)) 1543 __get_user(udata, &uioc->data))
1542 return -EFAULT; 1544 return -EFAULT;
1543 ctrl.data = compat_ptr(udata); 1545 ctrl.data = compat_ptr(udata);
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 7d03549c3339..11c627ce6022 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -903,7 +903,8 @@ static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
903 /* already started */ 903 /* already started */
904 break; 904 break;
905 case QH_STATE_IDLE: 905 case QH_STATE_IDLE:
906 WARN_ON(1); 906 /* QH might be waiting for a Clear-TT-Buffer */
907 qh_completions(ehci, qh);
907 break; 908 break;
908 } 909 }
909 break; 910 break;
diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c
index 9a1384747f3b..7673554fa64d 100644
--- a/drivers/usb/host/ehci-q.c
+++ b/drivers/usb/host/ehci-q.c
@@ -375,12 +375,11 @@ qh_completions (struct ehci_hcd *ehci, struct ehci_qh *qh)
375 */ 375 */
376 if ((token & QTD_STS_XACT) && 376 if ((token & QTD_STS_XACT) &&
377 QTD_CERR(token) == 0 && 377 QTD_CERR(token) == 0 &&
378 --qh->xacterrs > 0 && 378 ++qh->xacterrs < QH_XACTERR_MAX &&
379 !urb->unlinked) { 379 !urb->unlinked) {
380 ehci_dbg(ehci, 380 ehci_dbg(ehci,
381 "detected XactErr len %zu/%zu retry %d\n", 381 "detected XactErr len %zu/%zu retry %d\n",
382 qtd->length - QTD_LENGTH(token), qtd->length, 382 qtd->length - QTD_LENGTH(token), qtd->length, qh->xacterrs);
383 QH_XACTERR_MAX - qh->xacterrs);
384 383
385 /* reset the token in the qtd and the 384 /* reset the token in the qtd and the
386 * qh overlay (which still contains 385 * qh overlay (which still contains
@@ -494,7 +493,7 @@ halt:
494 last = qtd; 493 last = qtd;
495 494
496 /* reinit the xacterr counter for the next qtd */ 495 /* reinit the xacterr counter for the next qtd */
497 qh->xacterrs = QH_XACTERR_MAX; 496 qh->xacterrs = 0;
498 } 497 }
499 498
500 /* last urb's completion might still need calling */ 499 /* last urb's completion might still need calling */
@@ -940,7 +939,8 @@ static void qh_link_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
940 head->qh_next.qh = qh; 939 head->qh_next.qh = qh;
941 head->hw_next = dma; 940 head->hw_next = dma;
942 941
943 qh->xacterrs = QH_XACTERR_MAX; 942 qh_get(qh);
943 qh->xacterrs = 0;
944 qh->qh_state = QH_STATE_LINKED; 944 qh->qh_state = QH_STATE_LINKED;
945 /* qtd completions reported later by interrupt */ 945 /* qtd completions reported later by interrupt */
946} 946}
@@ -1080,7 +1080,7 @@ submit_async (
1080 * the HC and TT handle it when the TT has a buffer ready. 1080 * the HC and TT handle it when the TT has a buffer ready.
1081 */ 1081 */
1082 if (likely (qh->qh_state == QH_STATE_IDLE)) 1082 if (likely (qh->qh_state == QH_STATE_IDLE))
1083 qh_link_async (ehci, qh_get (qh)); 1083 qh_link_async(ehci, qh);
1084 done: 1084 done:
1085 spin_unlock_irqrestore (&ehci->lock, flags); 1085 spin_unlock_irqrestore (&ehci->lock, flags);
1086 if (unlikely (qh == NULL)) 1086 if (unlikely (qh == NULL))
@@ -1115,8 +1115,6 @@ static void end_unlink_async (struct ehci_hcd *ehci)
1115 && HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) 1115 && HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
1116 qh_link_async (ehci, qh); 1116 qh_link_async (ehci, qh);
1117 else { 1117 else {
1118 qh_put (qh); // refcount from async list
1119
1120 /* it's not free to turn the async schedule on/off; leave it 1118 /* it's not free to turn the async schedule on/off; leave it
1121 * active but idle for a while once it empties. 1119 * active but idle for a while once it empties.
1122 */ 1120 */
@@ -1124,6 +1122,7 @@ static void end_unlink_async (struct ehci_hcd *ehci)
1124 && ehci->async->qh_next.qh == NULL) 1122 && ehci->async->qh_next.qh == NULL)
1125 timer_action (ehci, TIMER_ASYNC_OFF); 1123 timer_action (ehci, TIMER_ASYNC_OFF);
1126 } 1124 }
1125 qh_put(qh); /* refcount from async list */
1127 1126
1128 if (next) { 1127 if (next) {
1129 ehci->reclaim = NULL; 1128 ehci->reclaim = NULL;
diff --git a/drivers/usb/host/ehci-sched.c b/drivers/usb/host/ehci-sched.c
index 74f7f83b29ad..edd61ee90323 100644
--- a/drivers/usb/host/ehci-sched.c
+++ b/drivers/usb/host/ehci-sched.c
@@ -542,6 +542,7 @@ static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
542 } 542 }
543 } 543 }
544 qh->qh_state = QH_STATE_LINKED; 544 qh->qh_state = QH_STATE_LINKED;
545 qh->xacterrs = 0;
545 qh_get (qh); 546 qh_get (qh);
546 547
547 /* update per-qh bandwidth for usbfs */ 548 /* update per-qh bandwidth for usbfs */
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index 70073b157f0a..803adcb5ac1d 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -12,6 +12,7 @@ config USB_MUSB_HDRC
12 depends on !SUPERH 12 depends on !SUPERH
13 select NOP_USB_XCEIV if ARCH_DAVINCI 13 select NOP_USB_XCEIV if ARCH_DAVINCI
14 select TWL4030_USB if MACH_OMAP_3430SDP 14 select TWL4030_USB if MACH_OMAP_3430SDP
15 select NOP_USB_XCEIV if MACH_OMAP3EVM
15 select USB_OTG_UTILS 16 select USB_OTG_UTILS
16 tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)' 17 tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)'
17 help 18 help
diff --git a/drivers/usb/serial/ftdi_sio.c b/drivers/usb/serial/ftdi_sio.c
index b574878c78b2..8fec5d4455c9 100644
--- a/drivers/usb/serial/ftdi_sio.c
+++ b/drivers/usb/serial/ftdi_sio.c
@@ -699,6 +699,9 @@ static struct usb_device_id id_table_combined [] = {
699 .driver_info = (kernel_ulong_t)&ftdi_jtag_quirk }, 699 .driver_info = (kernel_ulong_t)&ftdi_jtag_quirk },
700 { USB_DEVICE(LARSENBRUSGAARD_VID, LB_ALTITRACK_PID) }, 700 { USB_DEVICE(LARSENBRUSGAARD_VID, LB_ALTITRACK_PID) },
701 { USB_DEVICE(GN_OTOMETRICS_VID, AURICAL_USB_PID) }, 701 { USB_DEVICE(GN_OTOMETRICS_VID, AURICAL_USB_PID) },
702 { USB_DEVICE(BAYER_VID, BAYER_CONTOUR_CABLE_PID) },
703 { USB_DEVICE(FTDI_VID, MARVELL_OPENRD_PID),
704 .driver_info = (kernel_ulong_t)&ftdi_jtag_quirk },
702 { }, /* Optional parameter entry */ 705 { }, /* Optional parameter entry */
703 { } /* Terminating entry */ 706 { } /* Terminating entry */
704}; 707};
diff --git a/drivers/usb/serial/ftdi_sio.h b/drivers/usb/serial/ftdi_sio.h
index 24dbd99e87d7..8c92b88166ae 100644
--- a/drivers/usb/serial/ftdi_sio.h
+++ b/drivers/usb/serial/ftdi_sio.h
@@ -954,6 +954,20 @@
954#define AURICAL_USB_PID 0x0010 /* Aurical USB Audiometer */ 954#define AURICAL_USB_PID 0x0010 /* Aurical USB Audiometer */
955 955
956/* 956/*
957 * Bayer Ascensia Contour blood glucose meter USB-converter cable.
958 * http://winglucofacts.com/cables/
959 */
960#define BAYER_VID 0x1A79
961#define BAYER_CONTOUR_CABLE_PID 0x6001
962
963/*
964 * Marvell OpenRD Base, Client
965 * http://www.open-rd.org
966 * OpenRD Base, Client use VID 0x0403
967 */
968#define MARVELL_OPENRD_PID 0x9e90
969
970/*
957 * BmRequestType: 1100 0000b 971 * BmRequestType: 1100 0000b
958 * bRequest: FTDI_E2_READ 972 * bRequest: FTDI_E2_READ
959 * wValue: 0 973 * wValue: 0
diff --git a/drivers/usb/serial/pl2303.c b/drivers/usb/serial/pl2303.c
index 7d15bfa7c2db..3e86815b2705 100644
--- a/drivers/usb/serial/pl2303.c
+++ b/drivers/usb/serial/pl2303.c
@@ -95,6 +95,7 @@ static struct usb_device_id id_table [] = {
95 { USB_DEVICE(SUPERIAL_VENDOR_ID, SUPERIAL_PRODUCT_ID) }, 95 { USB_DEVICE(SUPERIAL_VENDOR_ID, SUPERIAL_PRODUCT_ID) },
96 { USB_DEVICE(HP_VENDOR_ID, HP_LD220_PRODUCT_ID) }, 96 { USB_DEVICE(HP_VENDOR_ID, HP_LD220_PRODUCT_ID) },
97 { USB_DEVICE(CRESSI_VENDOR_ID, CRESSI_EDY_PRODUCT_ID) }, 97 { USB_DEVICE(CRESSI_VENDOR_ID, CRESSI_EDY_PRODUCT_ID) },
98 { USB_DEVICE(SONY_VENDOR_ID, SONY_QN3USB_PRODUCT_ID) },
98 { } /* Terminating entry */ 99 { } /* Terminating entry */
99}; 100};
100 101
diff --git a/drivers/usb/serial/pl2303.h b/drivers/usb/serial/pl2303.h
index 12aac7d2462d..ee9505e1dd92 100644
--- a/drivers/usb/serial/pl2303.h
+++ b/drivers/usb/serial/pl2303.h
@@ -126,3 +126,7 @@
126/* Cressi Edy (diving computer) PC interface */ 126/* Cressi Edy (diving computer) PC interface */
127#define CRESSI_VENDOR_ID 0x04b8 127#define CRESSI_VENDOR_ID 0x04b8
128#define CRESSI_EDY_PRODUCT_ID 0x0521 128#define CRESSI_EDY_PRODUCT_ID 0x0521
129
130/* Sony, USB data cable for CMD-Jxx mobile phones */
131#define SONY_VENDOR_ID 0x054c
132#define SONY_QN3USB_PRODUCT_ID 0x0437
diff --git a/drivers/usb/storage/unusual_devs.h b/drivers/usb/storage/unusual_devs.h
index 1b9c5dd0fb27..7477d411959f 100644
--- a/drivers/usb/storage/unusual_devs.h
+++ b/drivers/usb/storage/unusual_devs.h
@@ -838,6 +838,13 @@ UNUSUAL_DEV( 0x066f, 0x8000, 0x0001, 0x0001,
838 US_SC_DEVICE, US_PR_DEVICE, NULL, 838 US_SC_DEVICE, US_PR_DEVICE, NULL,
839 US_FL_FIX_CAPACITY ), 839 US_FL_FIX_CAPACITY ),
840 840
841/* Reported by Rogerio Brito <rbrito@ime.usp.br> */
842UNUSUAL_DEV( 0x067b, 0x2317, 0x0001, 0x001,
843 "Prolific Technology, Inc.",
844 "Mass Storage Device",
845 US_SC_DEVICE, US_PR_DEVICE, NULL,
846 US_FL_NOT_LOCKABLE ),
847
841/* Reported by Richard -=[]=- <micro_flyer@hotmail.com> */ 848/* Reported by Richard -=[]=- <micro_flyer@hotmail.com> */
842/* Change to bcdDeviceMin (0x0100 to 0x0001) reported by 849/* Change to bcdDeviceMin (0x0100 to 0x0001) reported by
843 * Thomas Bartosik <tbartdev@gmx-topmail.de> */ 850 * Thomas Bartosik <tbartdev@gmx-topmail.de> */
diff --git a/drivers/video/console/fbcon.c b/drivers/video/console/fbcon.c
index 471a9a60376a..3a44695b9c09 100644
--- a/drivers/video/console/fbcon.c
+++ b/drivers/video/console/fbcon.c
@@ -1082,7 +1082,6 @@ static void fbcon_init(struct vc_data *vc, int init)
1082 new_rows = FBCON_SWAP(ops->rotate, info->var.yres, info->var.xres); 1082 new_rows = FBCON_SWAP(ops->rotate, info->var.yres, info->var.xres);
1083 new_cols /= vc->vc_font.width; 1083 new_cols /= vc->vc_font.width;
1084 new_rows /= vc->vc_font.height; 1084 new_rows /= vc->vc_font.height;
1085 vc_resize(vc, new_cols, new_rows);
1086 1085
1087 /* 1086 /*
1088 * We must always set the mode. The mode of the previous console 1087 * We must always set the mode. The mode of the previous console
@@ -1111,10 +1110,11 @@ static void fbcon_init(struct vc_data *vc, int init)
1111 * vc_{cols,rows}, but we must not set those if we are only 1110 * vc_{cols,rows}, but we must not set those if we are only
1112 * resizing the console. 1111 * resizing the console.
1113 */ 1112 */
1114 if (!init) { 1113 if (init) {
1115 vc->vc_cols = new_cols; 1114 vc->vc_cols = new_cols;
1116 vc->vc_rows = new_rows; 1115 vc->vc_rows = new_rows;
1117 } 1116 } else
1117 vc_resize(vc, new_cols, new_rows);
1118 1118
1119 if (logo) 1119 if (logo)
1120 fbcon_prepare_logo(vc, info, cols, rows, new_cols, new_rows); 1120 fbcon_prepare_logo(vc, info, cols, rows, new_cols, new_rows);
diff --git a/drivers/video/console/fbcon_rotate.h b/drivers/video/console/fbcon_rotate.h
index 75be5ce53dc5..e233444cda66 100644
--- a/drivers/video/console/fbcon_rotate.h
+++ b/drivers/video/console/fbcon_rotate.h
@@ -45,7 +45,7 @@ static inline void rotate_ud(const char *in, char *out, u32 width, u32 height)
45 width = (width + 7) & ~7; 45 width = (width + 7) & ~7;
46 46
47 for (i = 0; i < height; i++) { 47 for (i = 0; i < height; i++) {
48 for (j = 0; j < width; j++) { 48 for (j = 0; j < width - shift; j++) {
49 if (pattern_test_bit(j, i, width, in)) 49 if (pattern_test_bit(j, i, width, in))
50 pattern_set_bit(width - (1 + j + shift), 50 pattern_set_bit(width - (1 + j + shift),
51 height - (1 + i), 51 height - (1 + i),
diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c
index f8778cde2183..054ef29be479 100644
--- a/drivers/video/mx3fb.c
+++ b/drivers/video/mx3fb.c
@@ -669,7 +669,8 @@ static uint32_t bpp_to_pixfmt(int bpp)
669} 669}
670 670
671static int mx3fb_blank(int blank, struct fb_info *fbi); 671static int mx3fb_blank(int blank, struct fb_info *fbi);
672static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len); 672static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
673 bool lock);
673static int mx3fb_unmap_video_memory(struct fb_info *fbi); 674static int mx3fb_unmap_video_memory(struct fb_info *fbi);
674 675
675/** 676/**
@@ -711,12 +712,7 @@ static void mx3fb_dma_done(void *arg)
711 complete(&mx3_fbi->flip_cmpl); 712 complete(&mx3_fbi->flip_cmpl);
712} 713}
713 714
714/** 715static int __set_par(struct fb_info *fbi, bool lock)
715 * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
716 * @fbi: framebuffer information pointer.
717 * @return: 0 on success or negative error code on failure.
718 */
719static int mx3fb_set_par(struct fb_info *fbi)
720{ 716{
721 u32 mem_len; 717 u32 mem_len;
722 struct ipu_di_signal_cfg sig_cfg; 718 struct ipu_di_signal_cfg sig_cfg;
@@ -727,10 +723,6 @@ static int mx3fb_set_par(struct fb_info *fbi)
727 struct idmac_video_param *video = &ichan->params.video; 723 struct idmac_video_param *video = &ichan->params.video;
728 struct scatterlist *sg = mx3_fbi->sg; 724 struct scatterlist *sg = mx3_fbi->sg;
729 725
730 dev_dbg(mx3fb->dev, "%s [%c]\n", __func__, list_empty(&ichan->queue) ? '-' : '+');
731
732 mutex_lock(&mx3_fbi->mutex);
733
734 /* Total cleanup */ 726 /* Total cleanup */
735 if (mx3_fbi->txd) 727 if (mx3_fbi->txd)
736 sdc_disable_channel(mx3_fbi); 728 sdc_disable_channel(mx3_fbi);
@@ -742,10 +734,8 @@ static int mx3fb_set_par(struct fb_info *fbi)
742 if (fbi->fix.smem_start) 734 if (fbi->fix.smem_start)
743 mx3fb_unmap_video_memory(fbi); 735 mx3fb_unmap_video_memory(fbi);
744 736
745 if (mx3fb_map_video_memory(fbi, mem_len) < 0) { 737 if (mx3fb_map_video_memory(fbi, mem_len, lock) < 0)
746 mutex_unlock(&mx3_fbi->mutex);
747 return -ENOMEM; 738 return -ENOMEM;
748 }
749 } 739 }
750 740
751 sg_init_table(&sg[0], 1); 741 sg_init_table(&sg[0], 1);
@@ -791,7 +781,6 @@ static int mx3fb_set_par(struct fb_info *fbi)
791 fbi->var.vsync_len, 781 fbi->var.vsync_len,
792 fbi->var.lower_margin + 782 fbi->var.lower_margin +
793 fbi->var.vsync_len, sig_cfg) != 0) { 783 fbi->var.vsync_len, sig_cfg) != 0) {
794 mutex_unlock(&mx3_fbi->mutex);
795 dev_err(fbi->device, 784 dev_err(fbi->device,
796 "mx3fb: Error initializing panel.\n"); 785 "mx3fb: Error initializing panel.\n");
797 return -EINVAL; 786 return -EINVAL;
@@ -810,9 +799,30 @@ static int mx3fb_set_par(struct fb_info *fbi)
810 if (mx3_fbi->blank == FB_BLANK_UNBLANK) 799 if (mx3_fbi->blank == FB_BLANK_UNBLANK)
811 sdc_enable_channel(mx3_fbi); 800 sdc_enable_channel(mx3_fbi);
812 801
802 return 0;
803}
804
805/**
806 * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
807 * @fbi: framebuffer information pointer.
808 * @return: 0 on success or negative error code on failure.
809 */
810static int mx3fb_set_par(struct fb_info *fbi)
811{
812 struct mx3fb_info *mx3_fbi = fbi->par;
813 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
814 struct idmac_channel *ichan = mx3_fbi->idmac_channel;
815 int ret;
816
817 dev_dbg(mx3fb->dev, "%s [%c]\n", __func__, list_empty(&ichan->queue) ? '-' : '+');
818
819 mutex_lock(&mx3_fbi->mutex);
820
821 ret = __set_par(fbi, true);
822
813 mutex_unlock(&mx3_fbi->mutex); 823 mutex_unlock(&mx3_fbi->mutex);
814 824
815 return 0; 825 return ret;
816} 826}
817 827
818/** 828/**
@@ -966,21 +976,11 @@ static int mx3fb_setcolreg(unsigned int regno, unsigned int red,
966 return ret; 976 return ret;
967} 977}
968 978
969/** 979static void __blank(int blank, struct fb_info *fbi)
970 * mx3fb_blank() - blank the display.
971 */
972static int mx3fb_blank(int blank, struct fb_info *fbi)
973{ 980{
974 struct mx3fb_info *mx3_fbi = fbi->par; 981 struct mx3fb_info *mx3_fbi = fbi->par;
975 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; 982 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
976 983
977 dev_dbg(fbi->device, "%s, blank = %d, base %p, len %u\n", __func__,
978 blank, fbi->screen_base, fbi->fix.smem_len);
979
980 if (mx3_fbi->blank == blank)
981 return 0;
982
983 mutex_lock(&mx3_fbi->mutex);
984 mx3_fbi->blank = blank; 984 mx3_fbi->blank = blank;
985 985
986 switch (blank) { 986 switch (blank) {
@@ -999,6 +999,23 @@ static int mx3fb_blank(int blank, struct fb_info *fbi)
999 sdc_set_brightness(mx3fb, mx3fb->backlight_level); 999 sdc_set_brightness(mx3fb, mx3fb->backlight_level);
1000 break; 1000 break;
1001 } 1001 }
1002}
1003
1004/**
1005 * mx3fb_blank() - blank the display.
1006 */
1007static int mx3fb_blank(int blank, struct fb_info *fbi)
1008{
1009 struct mx3fb_info *mx3_fbi = fbi->par;
1010
1011 dev_dbg(fbi->device, "%s, blank = %d, base %p, len %u\n", __func__,
1012 blank, fbi->screen_base, fbi->fix.smem_len);
1013
1014 if (mx3_fbi->blank == blank)
1015 return 0;
1016
1017 mutex_lock(&mx3_fbi->mutex);
1018 __blank(blank, fbi);
1002 mutex_unlock(&mx3_fbi->mutex); 1019 mutex_unlock(&mx3_fbi->mutex);
1003 1020
1004 return 0; 1021 return 0;
@@ -1198,6 +1215,7 @@ static int mx3fb_resume(struct platform_device *pdev)
1198 * mx3fb_map_video_memory() - allocates the DRAM memory for the frame buffer. 1215 * mx3fb_map_video_memory() - allocates the DRAM memory for the frame buffer.
1199 * @fbi: framebuffer information pointer 1216 * @fbi: framebuffer information pointer
1200 * @mem_len: length of mapped memory 1217 * @mem_len: length of mapped memory
1218 * @lock: do not lock during initialisation
1201 * @return: Error code indicating success or failure 1219 * @return: Error code indicating success or failure
1202 * 1220 *
1203 * This buffer is remapped into a non-cached, non-buffered, memory region to 1221 * This buffer is remapped into a non-cached, non-buffered, memory region to
@@ -1205,7 +1223,8 @@ static int mx3fb_resume(struct platform_device *pdev)
1205 * area is remapped, all virtual memory access to the video memory should occur 1223 * area is remapped, all virtual memory access to the video memory should occur
1206 * at the new region. 1224 * at the new region.
1207 */ 1225 */
1208static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len) 1226static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
1227 bool lock)
1209{ 1228{
1210 int retval = 0; 1229 int retval = 0;
1211 dma_addr_t addr; 1230 dma_addr_t addr;
@@ -1221,10 +1240,12 @@ static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len)
1221 goto err0; 1240 goto err0;
1222 } 1241 }
1223 1242
1224 mutex_lock(&fbi->mm_lock); 1243 if (lock)
1244 mutex_lock(&fbi->mm_lock);
1225 fbi->fix.smem_start = addr; 1245 fbi->fix.smem_start = addr;
1226 fbi->fix.smem_len = mem_len; 1246 fbi->fix.smem_len = mem_len;
1227 mutex_unlock(&fbi->mm_lock); 1247 if (lock)
1248 mutex_unlock(&fbi->mm_lock);
1228 1249
1229 dev_dbg(fbi->device, "allocated fb @ p=0x%08x, v=0x%p, size=%d.\n", 1250 dev_dbg(fbi->device, "allocated fb @ p=0x%08x, v=0x%p, size=%d.\n",
1230 (uint32_t) fbi->fix.smem_start, fbi->screen_base, fbi->fix.smem_len); 1251 (uint32_t) fbi->fix.smem_start, fbi->screen_base, fbi->fix.smem_len);
@@ -1365,6 +1386,11 @@ static int init_fb_chan(struct mx3fb_data *mx3fb, struct idmac_channel *ichan)
1365 init_completion(&mx3fbi->flip_cmpl); 1386 init_completion(&mx3fbi->flip_cmpl);
1366 disable_irq(ichan->eof_irq); 1387 disable_irq(ichan->eof_irq);
1367 dev_dbg(mx3fb->dev, "disabling irq %d\n", ichan->eof_irq); 1388 dev_dbg(mx3fb->dev, "disabling irq %d\n", ichan->eof_irq);
1389 ret = __set_par(fbi, false);
1390 if (ret < 0)
1391 goto esetpar;
1392
1393 __blank(FB_BLANK_UNBLANK, fbi);
1368 1394
1369 dev_info(dev, "registered, using mode %s\n", fb_mode); 1395 dev_info(dev, "registered, using mode %s\n", fb_mode);
1370 1396
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index fcd53ceb88fa..c8960003f47d 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -2407,14 +2407,14 @@ int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
2407 viafb_dvi_set_mode(viafb_get_mode_index 2407 viafb_dvi_set_mode(viafb_get_mode_index
2408 (viaparinfo->tmds_setting_info->h_active, 2408 (viaparinfo->tmds_setting_info->h_active,
2409 viaparinfo->tmds_setting_info-> 2409 viaparinfo->tmds_setting_info->
2410 v_active, 1), 2410 v_active),
2411 video_bpp1, viaparinfo-> 2411 video_bpp1, viaparinfo->
2412 tmds_setting_info->iga_path); 2412 tmds_setting_info->iga_path);
2413 } else { 2413 } else {
2414 viafb_dvi_set_mode(viafb_get_mode_index 2414 viafb_dvi_set_mode(viafb_get_mode_index
2415 (viaparinfo->tmds_setting_info->h_active, 2415 (viaparinfo->tmds_setting_info->h_active,
2416 viaparinfo-> 2416 viaparinfo->
2417 tmds_setting_info->v_active, 0), 2417 tmds_setting_info->v_active),
2418 video_bpp, viaparinfo-> 2418 video_bpp, viaparinfo->
2419 tmds_setting_info->iga_path); 2419 tmds_setting_info->iga_path);
2420 } 2420 }
diff --git a/drivers/video/via/lcd.c b/drivers/video/via/lcd.c
index 6c7290a6a447..78c6b3387947 100644
--- a/drivers/video/via/lcd.c
+++ b/drivers/video/via/lcd.c
@@ -580,10 +580,7 @@ static void load_lcd_k400_patch_tbl(int set_hres, int set_vres,
580 int reg_num = 0; 580 int reg_num = 0;
581 struct io_reg *lcd_patch_reg = NULL; 581 struct io_reg *lcd_patch_reg = NULL;
582 582
583 if (viaparinfo->lvds_setting_info->iga_path == IGA2) 583 vmode_index = viafb_get_mode_index(set_hres, set_vres);
584 vmode_index = viafb_get_mode_index(set_hres, set_vres, 1);
585 else
586 vmode_index = viafb_get_mode_index(set_hres, set_vres, 0);
587 switch (panel_id) { 584 switch (panel_id) {
588 /* LCD 800x600 */ 585 /* LCD 800x600 */
589 case LCD_PANEL_ID1_800X600: 586 case LCD_PANEL_ID1_800X600:
@@ -761,10 +758,7 @@ static void load_lcd_p880_patch_tbl(int set_hres, int set_vres,
761 int reg_num = 0; 758 int reg_num = 0;
762 struct io_reg *lcd_patch_reg = NULL; 759 struct io_reg *lcd_patch_reg = NULL;
763 760
764 if (viaparinfo->lvds_setting_info->iga_path == IGA2) 761 vmode_index = viafb_get_mode_index(set_hres, set_vres);
765 vmode_index = viafb_get_mode_index(set_hres, set_vres, 1);
766 else
767 vmode_index = viafb_get_mode_index(set_hres, set_vres, 0);
768 762
769 switch (panel_id) { 763 switch (panel_id) {
770 case LCD_PANEL_ID5_1400X1050: 764 case LCD_PANEL_ID5_1400X1050:
@@ -832,10 +826,7 @@ static void load_lcd_patch_regs(int set_hres, int set_vres,
832{ 826{
833 int vmode_index; 827 int vmode_index;
834 828
835 if (viaparinfo->lvds_setting_info->iga_path == IGA2) 829 vmode_index = viafb_get_mode_index(set_hres, set_vres);
836 vmode_index = viafb_get_mode_index(set_hres, set_vres, 1);
837 else
838 vmode_index = viafb_get_mode_index(set_hres, set_vres, 0);
839 830
840 viafb_unlock_crt(); 831 viafb_unlock_crt();
841 832
diff --git a/drivers/video/via/viafbdev.c b/drivers/video/via/viafbdev.c
index a0fec298216e..72833f3334b5 100644
--- a/drivers/video/via/viafbdev.c
+++ b/drivers/video/via/viafbdev.c
@@ -32,7 +32,6 @@ static u32 pseudo_pal[17];
32/* video mode */ 32/* video mode */
33static char *viafb_mode = "640x480"; 33static char *viafb_mode = "640x480";
34static char *viafb_mode1 = "640x480"; 34static char *viafb_mode1 = "640x480";
35static int viafb_resMode = VIA_RES_640X480;
36 35
37/* Added for specifying active devices.*/ 36/* Added for specifying active devices.*/
38char *viafb_active_dev = ""; 37char *viafb_active_dev = "";
@@ -56,47 +55,47 @@ static void viafb_get_video_device(u32 *video_dev_info);
56 55
57/* Mode information */ 56/* Mode information */
58static const struct viafb_modeinfo viafb_modentry[] = { 57static const struct viafb_modeinfo viafb_modentry[] = {
59 {480, 640, VIA_RES_480X640, "480x640"}, 58 {480, 640, VIA_RES_480X640},
60 {640, 480, VIA_RES_640X480, "640x480"}, 59 {640, 480, VIA_RES_640X480},
61 {800, 480, VIA_RES_800X480, "800x480"}, 60 {800, 480, VIA_RES_800X480},
62 {800, 600, VIA_RES_800X600, "800x600"}, 61 {800, 600, VIA_RES_800X600},
63 {1024, 768, VIA_RES_1024X768, "1024x768"}, 62 {1024, 768, VIA_RES_1024X768},
64 {1152, 864, VIA_RES_1152X864, "1152x864"}, 63 {1152, 864, VIA_RES_1152X864},
65 {1280, 1024, VIA_RES_1280X1024, "1280x1024"}, 64 {1280, 1024, VIA_RES_1280X1024},
66 {1600, 1200, VIA_RES_1600X1200, "1600x1200"}, 65 {1600, 1200, VIA_RES_1600X1200},
67 {1440, 1050, VIA_RES_1440X1050, "1440x1050"}, 66 {1440, 1050, VIA_RES_1440X1050},
68 {1280, 768, VIA_RES_1280X768, "1280x768"}, 67 {1280, 768, VIA_RES_1280X768,},
69 {1280, 800, VIA_RES_1280X800, "1280x800"}, 68 {1280, 800, VIA_RES_1280X800},
70 {1280, 960, VIA_RES_1280X960, "1280x960"}, 69 {1280, 960, VIA_RES_1280X960},
71 {1920, 1440, VIA_RES_1920X1440, "1920x1440"}, 70 {1920, 1440, VIA_RES_1920X1440},
72 {848, 480, VIA_RES_848X480, "848x480"}, 71 {848, 480, VIA_RES_848X480},
73 {1400, 1050, VIA_RES_1400X1050, "1400x1050"}, 72 {1400, 1050, VIA_RES_1400X1050},
74 {720, 480, VIA_RES_720X480, "720x480"}, 73 {720, 480, VIA_RES_720X480},
75 {720, 576, VIA_RES_720X576, "720x576"}, 74 {720, 576, VIA_RES_720X576},
76 {1024, 512, VIA_RES_1024X512, "1024x512"}, 75 {1024, 512, VIA_RES_1024X512},
77 {1024, 576, VIA_RES_1024X576, "1024x576"}, 76 {1024, 576, VIA_RES_1024X576},
78 {1024, 600, VIA_RES_1024X600, "1024x600"}, 77 {1024, 600, VIA_RES_1024X600},
79 {1280, 720, VIA_RES_1280X720, "1280x720"}, 78 {1280, 720, VIA_RES_1280X720},
80 {1920, 1080, VIA_RES_1920X1080, "1920x1080"}, 79 {1920, 1080, VIA_RES_1920X1080},
81 {1366, 768, VIA_RES_1368X768, "1368x768"}, 80 {1366, 768, VIA_RES_1368X768},
82 {1680, 1050, VIA_RES_1680X1050, "1680x1050"}, 81 {1680, 1050, VIA_RES_1680X1050},
83 {960, 600, VIA_RES_960X600, "960x600"}, 82 {960, 600, VIA_RES_960X600},
84 {1000, 600, VIA_RES_1000X600, "1000x600"}, 83 {1000, 600, VIA_RES_1000X600},
85 {1024, 576, VIA_RES_1024X576, "1024x576"}, 84 {1024, 576, VIA_RES_1024X576},
86 {1024, 600, VIA_RES_1024X600, "1024x600"}, 85 {1024, 600, VIA_RES_1024X600},
87 {1088, 612, VIA_RES_1088X612, "1088x612"}, 86 {1088, 612, VIA_RES_1088X612},
88 {1152, 720, VIA_RES_1152X720, "1152x720"}, 87 {1152, 720, VIA_RES_1152X720},
89 {1200, 720, VIA_RES_1200X720, "1200x720"}, 88 {1200, 720, VIA_RES_1200X720},
90 {1280, 600, VIA_RES_1280X600, "1280x600"}, 89 {1280, 600, VIA_RES_1280X600},
91 {1360, 768, VIA_RES_1360X768, "1360x768"}, 90 {1360, 768, VIA_RES_1360X768},
92 {1440, 900, VIA_RES_1440X900, "1440x900"}, 91 {1440, 900, VIA_RES_1440X900},
93 {1600, 900, VIA_RES_1600X900, "1600x900"}, 92 {1600, 900, VIA_RES_1600X900},
94 {1600, 1024, VIA_RES_1600X1024, "1600x1024"}, 93 {1600, 1024, VIA_RES_1600X1024},
95 {1792, 1344, VIA_RES_1792X1344, "1792x1344"}, 94 {1792, 1344, VIA_RES_1792X1344},
96 {1856, 1392, VIA_RES_1856X1392, "1856x1392"}, 95 {1856, 1392, VIA_RES_1856X1392},
97 {1920, 1200, VIA_RES_1920X1200, "1920x1200"}, 96 {1920, 1200, VIA_RES_1920X1200},
98 {2048, 1536, VIA_RES_2048X1536, "2048x1536"}, 97 {2048, 1536, VIA_RES_2048X1536},
99 {0, 0, VIA_RES_INVALID, "640x480"} 98 {0, 0, VIA_RES_INVALID}
100}; 99};
101 100
102static struct fb_ops viafb_ops; 101static struct fb_ops viafb_ops;
@@ -177,7 +176,7 @@ static int viafb_check_var(struct fb_var_screeninfo *var,
177 if (var->vmode & FB_VMODE_INTERLACED || var->vmode & FB_VMODE_DOUBLE) 176 if (var->vmode & FB_VMODE_INTERLACED || var->vmode & FB_VMODE_DOUBLE)
178 return -EINVAL; 177 return -EINVAL;
179 178
180 vmode_index = viafb_get_mode_index(var->xres, var->yres, 0); 179 vmode_index = viafb_get_mode_index(var->xres, var->yres);
181 if (vmode_index == VIA_RES_INVALID) { 180 if (vmode_index == VIA_RES_INVALID) {
182 DEBUG_MSG(KERN_INFO 181 DEBUG_MSG(KERN_INFO
183 "viafb: Mode %dx%dx%d not supported!!\n", 182 "viafb: Mode %dx%dx%d not supported!!\n",
@@ -233,14 +232,14 @@ static int viafb_set_par(struct fb_info *info)
233 viafb_update_device_setting(info->var.xres, info->var.yres, 232 viafb_update_device_setting(info->var.xres, info->var.yres,
234 info->var.bits_per_pixel, viafb_refresh, 0); 233 info->var.bits_per_pixel, viafb_refresh, 0);
235 234
236 vmode_index = viafb_get_mode_index(info->var.xres, info->var.yres, 0); 235 vmode_index = viafb_get_mode_index(info->var.xres, info->var.yres);
237 236
238 if (viafb_SAMM_ON == 1) { 237 if (viafb_SAMM_ON == 1) {
239 DEBUG_MSG(KERN_INFO 238 DEBUG_MSG(KERN_INFO
240 "viafb_second_xres = %d, viafb_second_yres = %d, bpp = %d\n", 239 "viafb_second_xres = %d, viafb_second_yres = %d, bpp = %d\n",
241 viafb_second_xres, viafb_second_yres, viafb_bpp1); 240 viafb_second_xres, viafb_second_yres, viafb_bpp1);
242 vmode_index1 = viafb_get_mode_index(viafb_second_xres, 241 vmode_index1 = viafb_get_mode_index(viafb_second_xres,
243 viafb_second_yres, 1); 242 viafb_second_yres);
244 DEBUG_MSG(KERN_INFO "->viafb_SAMM_ON: index=%d\n", 243 DEBUG_MSG(KERN_INFO "->viafb_SAMM_ON: index=%d\n",
245 vmode_index1); 244 vmode_index1);
246 245
@@ -1262,7 +1261,7 @@ static int viafb_sync(struct fb_info *info)
1262 return 0; 1261 return 0;
1263} 1262}
1264 1263
1265int viafb_get_mode_index(int hres, int vres, int flag) 1264int viafb_get_mode_index(int hres, int vres)
1266{ 1265{
1267 u32 i; 1266 u32 i;
1268 DEBUG_MSG(KERN_INFO "viafb_get_mode_index!\n"); 1267 DEBUG_MSG(KERN_INFO "viafb_get_mode_index!\n");
@@ -1272,13 +1271,7 @@ int viafb_get_mode_index(int hres, int vres, int flag)
1272 viafb_modentry[i].yres == vres) 1271 viafb_modentry[i].yres == vres)
1273 break; 1272 break;
1274 1273
1275 viafb_resMode = viafb_modentry[i].mode_index; 1274 return viafb_modentry[i].mode_index;
1276 if (flag)
1277 viafb_mode1 = viafb_modentry[i].mode_res;
1278 else
1279 viafb_mode = viafb_modentry[i].mode_res;
1280
1281 return viafb_resMode;
1282} 1275}
1283 1276
1284static void check_available_device_to_enable(int device_id) 1277static void check_available_device_to_enable(int device_id)
@@ -2199,7 +2192,7 @@ static int __devinit via_pci_probe(void)
2199 strict_strtoul(tmpc, 0, &default_xres); 2192 strict_strtoul(tmpc, 0, &default_xres);
2200 strict_strtoul(tmpm, 0, &default_yres); 2193 strict_strtoul(tmpm, 0, &default_yres);
2201 2194
2202 vmode_index = viafb_get_mode_index(default_xres, default_yres, 0); 2195 vmode_index = viafb_get_mode_index(default_xres, default_yres);
2203 DEBUG_MSG(KERN_INFO "0->index=%d\n", vmode_index); 2196 DEBUG_MSG(KERN_INFO "0->index=%d\n", vmode_index);
2204 2197
2205 if (viafb_SAMM_ON == 1) { 2198 if (viafb_SAMM_ON == 1) {
diff --git a/drivers/video/via/viafbdev.h b/drivers/video/via/viafbdev.h
index a4158e872878..227b000feb38 100644
--- a/drivers/video/via/viafbdev.h
+++ b/drivers/video/via/viafbdev.h
@@ -81,7 +81,6 @@ struct viafb_modeinfo {
81 u32 xres; 81 u32 xres;
82 u32 yres; 82 u32 yres;
83 int mode_index; 83 int mode_index;
84 char *mode_res;
85}; 84};
86extern unsigned int viafb_second_virtual_yres; 85extern unsigned int viafb_second_virtual_yres;
87extern unsigned int viafb_second_virtual_xres; 86extern unsigned int viafb_second_virtual_xres;
@@ -102,7 +101,7 @@ extern int strict_strtoul(const char *cp, unsigned int base,
102void viafb_memory_pitch_patch(struct fb_info *info); 101void viafb_memory_pitch_patch(struct fb_info *info);
103void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh, 102void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
104 int mode_index); 103 int mode_index);
105int viafb_get_mode_index(int hres, int vres, int flag); 104int viafb_get_mode_index(int hres, int vres);
106u8 viafb_gpio_i2c_read_lvds(struct lvds_setting_information 105u8 viafb_gpio_i2c_read_lvds(struct lvds_setting_information
107 *plvds_setting_info, struct lvds_chip_information 106 *plvds_setting_info, struct lvds_chip_information
108 *plvds_chip_info, u8 index); 107 *plvds_chip_info, u8 index);
diff --git a/drivers/w1/masters/omap_hdq.c b/drivers/w1/masters/omap_hdq.c
index a7e3b706b9d3..0d92969404c3 100644
--- a/drivers/w1/masters/omap_hdq.c
+++ b/drivers/w1/masters/omap_hdq.c
@@ -687,6 +687,7 @@ static int omap_hdq_remove(struct platform_device *pdev)
687 687
688 if (hdq_data->hdq_usecount) { 688 if (hdq_data->hdq_usecount) {
689 dev_dbg(&pdev->dev, "removed when use count is not zero\n"); 689 dev_dbg(&pdev->dev, "removed when use count is not zero\n");
690 mutex_unlock(&hdq_data->hdq_mutex);
690 return -EBUSY; 691 return -EBUSY;
691 } 692 }
692 693
diff --git a/drivers/watchdog/ks8695_wdt.c b/drivers/watchdog/ks8695_wdt.c
index 00b03eb43bf0..e1c82769b08e 100644
--- a/drivers/watchdog/ks8695_wdt.c
+++ b/drivers/watchdog/ks8695_wdt.c
@@ -66,7 +66,7 @@ static inline void ks8695_wdt_stop(void)
66static inline void ks8695_wdt_start(void) 66static inline void ks8695_wdt_start(void)
67{ 67{
68 unsigned long tmcon; 68 unsigned long tmcon;
69 unsigned long tval = wdt_time * CLOCK_TICK_RATE; 69 unsigned long tval = wdt_time * KS8695_CLOCK_RATE;
70 70
71 spin_lock(&ks8695_lock); 71 spin_lock(&ks8695_lock);
72 /* disable timer0 */ 72 /* disable timer0 */
@@ -103,7 +103,7 @@ static inline void ks8695_wdt_reload(void)
103static int ks8695_wdt_settimeout(int new_time) 103static int ks8695_wdt_settimeout(int new_time)
104{ 104{
105 /* 105 /*
106 * All counting occurs at SLOW_CLOCK / 128 = 0.256 Hz 106 * All counting occurs at KS8695_CLOCK_RATE / 128 = 0.256 Hz
107 * 107 *
108 * Since WDV is a 16-bit counter, the maximum period is 108 * Since WDV is a 16-bit counter, the maximum period is
109 * 65536 / 0.256 = 256 seconds. 109 * 65536 / 0.256 = 256 seconds.
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-27 02:57:05 -0500