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-rw-r--r--drivers/net/wireless/ath9k/calib.c145
-rw-r--r--drivers/net/wireless/ath9k/eeprom.h2
-rw-r--r--drivers/net/wireless/ath9k/hw.c20
-rw-r--r--drivers/net/wireless/ath9k/initvals.h107
-rw-r--r--drivers/net/wireless/ath9k/phy.h4
5 files changed, 195 insertions, 83 deletions
diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c
index 1c074c059b5c..a652e9bb16de 100644
--- a/drivers/net/wireless/ath9k/calib.c
+++ b/drivers/net/wireless/ath9k/calib.c
@@ -745,43 +745,6 @@ static void ath9k_olc_temp_compensation(struct ath_hw *ah)
745 } 745 }
746} 746}
747 747
748bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
749 u8 rxchainmask, bool longcal,
750 bool *isCalDone)
751{
752 struct hal_cal_list *currCal = ah->cal_list_curr;
753
754 *isCalDone = true;
755
756 if (currCal &&
757 (currCal->calState == CAL_RUNNING ||
758 currCal->calState == CAL_WAITING)) {
759 ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal,
760 isCalDone);
761 if (*isCalDone) {
762 ah->cal_list_curr = currCal = currCal->calNext;
763
764 if (currCal->calState == CAL_WAITING) {
765 *isCalDone = false;
766 ath9k_hw_reset_calibration(ah, currCal);
767 }
768 }
769 }
770
771 if (longcal) {
772 if (OLC_FOR_AR9280_20_LATER)
773 ath9k_olc_temp_compensation(ah);
774 ath9k_hw_getnf(ah, chan);
775 ath9k_hw_loadnf(ah, ah->curchan);
776 ath9k_hw_start_nfcal(ah);
777
778 if (chan->channelFlags & CHANNEL_CW_INT)
779 chan->channelFlags &= ~CHANNEL_CW_INT;
780 }
781
782 return true;
783}
784
785static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah) 748static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah)
786{ 749{
787 750
@@ -877,22 +840,104 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah)
877 840
878} 841}
879 842
843bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
844 u8 rxchainmask, bool longcal,
845 bool *isCalDone)
846{
847 struct hal_cal_list *currCal = ah->cal_list_curr;
848
849 *isCalDone = true;
850
851 if (currCal &&
852 (currCal->calState == CAL_RUNNING ||
853 currCal->calState == CAL_WAITING)) {
854 ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal,
855 isCalDone);
856 if (*isCalDone) {
857 ah->cal_list_curr = currCal = currCal->calNext;
858
859 if (currCal->calState == CAL_WAITING) {
860 *isCalDone = false;
861 ath9k_hw_reset_calibration(ah, currCal);
862 }
863 }
864 }
865
866 if (longcal) {
867 if (AR_SREV_9285(ah) && AR_SREV_9285_11_OR_LATER(ah))
868 ath9k_hw_9285_pa_cal(ah);
869
870 if (OLC_FOR_AR9280_20_LATER)
871 ath9k_olc_temp_compensation(ah);
872 ath9k_hw_getnf(ah, chan);
873 ath9k_hw_loadnf(ah, ah->curchan);
874 ath9k_hw_start_nfcal(ah);
875
876 if (chan->channelFlags & CHANNEL_CW_INT)
877 chan->channelFlags &= ~CHANNEL_CW_INT;
878 }
879
880 return true;
881}
882
883bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
884{
885 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
886 if (chan->channelFlags & CHANNEL_HT20) {
887 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
888 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
889 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
890 AR_PHY_AGC_CONTROL_FLTR_CAL);
891 REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
892 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
893 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
894 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
895 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset "
896 "calibration failed to complete in "
897 "1ms; noisy ??\n");
898 return false;
899 }
900 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
901 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
902 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
903 }
904 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
905 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
906 REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
907 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
908 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
909 0, AH_WAIT_TIMEOUT)) {
910 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset calibration "
911 "failed to complete in 1ms; noisy ??\n");
912 return false;
913 }
914
915 REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
916 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
917 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
918
919 return true;
920}
921
880bool ath9k_hw_init_cal(struct ath_hw *ah, 922bool ath9k_hw_init_cal(struct ath_hw *ah,
881 struct ath9k_channel *chan) 923 struct ath9k_channel *chan)
882{ 924{
883 if (AR_SREV_9280_10_OR_LATER(ah)) { 925 if (AR_SREV_9285(ah) && AR_SREV_9285_12_OR_LATER(ah)) {
926 if (!ar9285_clc(ah, chan))
927 return false;
928 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
884 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); 929 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
885 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); 930 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
886 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); 931 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
887 932
888 /* Kick off the cal */ 933 /* Kick off the cal */
889 REG_WRITE(ah, AR_PHY_AGC_CONTROL, 934 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
890 REG_READ(ah, AR_PHY_AGC_CONTROL) | 935 REG_READ(ah, AR_PHY_AGC_CONTROL) |
891 AR_PHY_AGC_CONTROL_CAL); 936 AR_PHY_AGC_CONTROL_CAL);
892 937
893 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, 938 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
894 AR_PHY_AGC_CONTROL_CAL, 0, 939 AR_PHY_AGC_CONTROL_CAL, 0,
895 AH_WAIT_TIMEOUT)) { 940 AH_WAIT_TIMEOUT)) {
896 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 941 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
897 "offset calibration failed to complete in 1ms; " 942 "offset calibration failed to complete in 1ms; "
898 "noisy environment?\n"); 943 "noisy environment?\n");
@@ -906,11 +951,11 @@ bool ath9k_hw_init_cal(struct ath_hw *ah,
906 951
907 /* Calibrate the AGC */ 952 /* Calibrate the AGC */
908 REG_WRITE(ah, AR_PHY_AGC_CONTROL, 953 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
909 REG_READ(ah, AR_PHY_AGC_CONTROL) | 954 REG_READ(ah, AR_PHY_AGC_CONTROL) |
910 AR_PHY_AGC_CONTROL_CAL); 955 AR_PHY_AGC_CONTROL_CAL);
911 956
912 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 957 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
913 0, AH_WAIT_TIMEOUT)) { 958 0, AH_WAIT_TIMEOUT)) {
914 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 959 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
915 "offset calibration failed to complete in 1ms; " 960 "offset calibration failed to complete in 1ms; "
916 "noisy environment?\n"); 961 "noisy environment?\n");
@@ -928,8 +973,8 @@ bool ath9k_hw_init_cal(struct ath_hw *ah,
928 973
929 /* Do NF Calibration */ 974 /* Do NF Calibration */
930 REG_WRITE(ah, AR_PHY_AGC_CONTROL, 975 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
931 REG_READ(ah, AR_PHY_AGC_CONTROL) | 976 REG_READ(ah, AR_PHY_AGC_CONTROL) |
932 AR_PHY_AGC_CONTROL_NF); 977 AR_PHY_AGC_CONTROL_NF);
933 978
934 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL; 979 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
935 980
@@ -938,19 +983,19 @@ bool ath9k_hw_init_cal(struct ath_hw *ah,
938 INIT_CAL(&ah->adcgain_caldata); 983 INIT_CAL(&ah->adcgain_caldata);
939 INSERT_CAL(ah, &ah->adcgain_caldata); 984 INSERT_CAL(ah, &ah->adcgain_caldata);
940 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 985 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
941 "enabling ADC Gain Calibration.\n"); 986 "enabling ADC Gain Calibration.\n");
942 } 987 }
943 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) { 988 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
944 INIT_CAL(&ah->adcdc_caldata); 989 INIT_CAL(&ah->adcdc_caldata);
945 INSERT_CAL(ah, &ah->adcdc_caldata); 990 INSERT_CAL(ah, &ah->adcdc_caldata);
946 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 991 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
947 "enabling ADC DC Calibration.\n"); 992 "enabling ADC DC Calibration.\n");
948 } 993 }
949 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) { 994 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
950 INIT_CAL(&ah->iq_caldata); 995 INIT_CAL(&ah->iq_caldata);
951 INSERT_CAL(ah, &ah->iq_caldata); 996 INSERT_CAL(ah, &ah->iq_caldata);
952 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 997 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
953 "enabling IQ Calibration.\n"); 998 "enabling IQ Calibration.\n");
954 } 999 }
955 1000
956 ah->cal_list_curr = ah->cal_list; 1001 ah->cal_list_curr = ah->cal_list;
diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h
index 6296e3eff10b..d6f6108f63c7 100644
--- a/drivers/net/wireless/ath9k/eeprom.h
+++ b/drivers/net/wireless/ath9k/eeprom.h
@@ -261,7 +261,7 @@ struct base_eep_header_4k {
261 u16 deviceCap; 261 u16 deviceCap;
262 u32 binBuildNumber; 262 u32 binBuildNumber;
263 u8 deviceType; 263 u8 deviceType;
264 u8 futureBase[1]; 264 u8 txGainType;
265} __packed; 265} __packed;
266 266
267 267
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c
index eb750a503999..cdc9d15e8419 100644
--- a/drivers/net/wireless/ath9k/hw.c
+++ b/drivers/net/wireless/ath9k/hw.c
@@ -678,6 +678,7 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
678 ah->hw_version.macVersion, ah->hw_version.macRev); 678 ah->hw_version.macVersion, ah->hw_version.macRev);
679 679
680 if (AR_SREV_9285_12_OR_LATER(ah)) { 680 if (AR_SREV_9285_12_OR_LATER(ah)) {
681
681 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, 682 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
682 ARRAY_SIZE(ar9285Modes_9285_1_2), 6); 683 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
683 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2, 684 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
@@ -817,6 +818,22 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
817 if (ecode != 0) 818 if (ecode != 0)
818 goto bad; 819 goto bad;
819 820
821 if (AR_SREV_9285_12_OR_LATER(ah)) {
822 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
823
824 /* txgain table */
825 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
826 INIT_INI_ARRAY(&ah->iniModesTxGain,
827 ar9285Modes_high_power_tx_gain_9285_1_2,
828 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
829 } else {
830 INIT_INI_ARRAY(&ah->iniModesTxGain,
831 ar9285Modes_original_tx_gain_9285_1_2,
832 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
833 }
834
835 }
836
820 /* rxgain table */ 837 /* rxgain table */
821 if (AR_SREV_9280_20(ah)) 838 if (AR_SREV_9280_20(ah))
822 ath9k_hw_init_rxgain_ini(ah); 839 ath9k_hw_init_rxgain_ini(ah);
@@ -1293,7 +1310,8 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
1293 if (AR_SREV_9280(ah)) 1310 if (AR_SREV_9280(ah))
1294 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); 1311 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1295 1312
1296 if (AR_SREV_9280(ah)) 1313 if (AR_SREV_9280(ah) || (AR_SREV_9285(ah) &&
1314 AR_SREV_9285_12_OR_LATER(ah)))
1297 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 1315 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1298 1316
1299 for (i = 0; i < ah->iniCommon.ia_rows; i++) { 1317 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
diff --git a/drivers/net/wireless/ath9k/initvals.h b/drivers/net/wireless/ath9k/initvals.h
index d49236368a1c..c32bc3b00d95 100644
--- a/drivers/net/wireless/ath9k/initvals.h
+++ b/drivers/net/wireless/ath9k/initvals.h
@@ -4121,6 +4121,7 @@ static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285[][2] = {
4121 {0x00004044, 0x00000000 }, 4121 {0x00004044, 0x00000000 },
4122}; 4122};
4123 4123
4124/* AR9285 v1_2 PCI Register Writes. Created: 03/04/09 */
4124static const u_int32_t ar9285Modes_9285_1_2[][6] = { 4125static const u_int32_t ar9285Modes_9285_1_2[][6] = {
4125 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 }, 4126 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
4126 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 }, 4127 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
@@ -4155,7 +4156,7 @@ static const u_int32_t ar9285Modes_9285_1_2[][6] = {
4155 { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 }, 4156 { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
4156 { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 }, 4157 { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
4157 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 }, 4158 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
4158 { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 }, 4159 { 0x000099c8, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329 },
4159 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 }, 4160 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
4160 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 }, 4161 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
4161 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 4162 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
@@ -4421,25 +4422,6 @@ static const u_int32_t ar9285Modes_9285_1_2[][6] = {
4421 { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a }, 4422 { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
4422 { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 }, 4423 { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
4423 { 0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000 }, 4424 { 0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000 },
4424 { 0x0000a274, 0x0a81c652, 0x0a81c652, 0x0a820652, 0x0a820652, 0x0a82a652 },
4425 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
4426 { 0x0000a304, 0x00000000, 0x00000000, 0x00007201, 0x00007201, 0x00000000 },
4427 { 0x0000a308, 0x00000000, 0x00000000, 0x00010408, 0x00010408, 0x00000000 },
4428 { 0x0000a30c, 0x00000000, 0x00000000, 0x0001860a, 0x0001860a, 0x00000000 },
4429 { 0x0000a310, 0x00000000, 0x00000000, 0x00020818, 0x00020818, 0x00000000 },
4430 { 0x0000a314, 0x00000000, 0x00000000, 0x00024858, 0x00024858, 0x00000000 },
4431 { 0x0000a318, 0x00000000, 0x00000000, 0x00026859, 0x00026859, 0x00000000 },
4432 { 0x0000a31c, 0x00000000, 0x00000000, 0x0002985b, 0x0002985b, 0x00000000 },
4433 { 0x0000a320, 0x00000000, 0x00000000, 0x0002b89a, 0x0002b89a, 0x00000000 },
4434 { 0x0000a324, 0x00000000, 0x00000000, 0x0002d89b, 0x0002d89b, 0x00000000 },
4435 { 0x0000a328, 0x00000000, 0x00000000, 0x0002f89c, 0x0002f89c, 0x00000000 },
4436 { 0x0000a32c, 0x00000000, 0x00000000, 0x0003189d, 0x0003189d, 0x00000000 },
4437 { 0x0000a330, 0x00000000, 0x00000000, 0x0003389e, 0x0003389e, 0x00000000 },
4438 { 0x0000a334, 0x00000000, 0x00000000, 0x000368de, 0x000368de, 0x00000000 },
4439 { 0x0000a338, 0x00000000, 0x00000000, 0x0003891e, 0x0003891e, 0x00000000 },
4440 { 0x0000a33c, 0x00000000, 0x00000000, 0x0003a95e, 0x0003a95e, 0x00000000 },
4441 { 0x0000a340, 0x00000000, 0x00000000, 0x0003e9df, 0x0003e9df, 0x00000000 },
4442 { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
4443 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e }, 4425 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
4444}; 4426};
4445 4427
@@ -4569,7 +4551,7 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = {
4569 { 0x00008110, 0x00000168 }, 4551 { 0x00008110, 0x00000168 },
4570 { 0x00008118, 0x000100aa }, 4552 { 0x00008118, 0x000100aa },
4571 { 0x0000811c, 0x00003210 }, 4553 { 0x0000811c, 0x00003210 },
4572 { 0x00008120, 0x08f04800 }, 4554 { 0x00008120, 0x08f04810 },
4573 { 0x00008124, 0x00000000 }, 4555 { 0x00008124, 0x00000000 },
4574 { 0x00008128, 0x00000000 }, 4556 { 0x00008128, 0x00000000 },
4575 { 0x0000812c, 0x00000000 }, 4557 { 0x0000812c, 0x00000000 },
@@ -4585,7 +4567,7 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = {
4585 { 0x00008178, 0x00000100 }, 4567 { 0x00008178, 0x00000100 },
4586 { 0x0000817c, 0x00000000 }, 4568 { 0x0000817c, 0x00000000 },
4587 { 0x000081c0, 0x00000000 }, 4569 { 0x000081c0, 0x00000000 },
4588 { 0x000081d0, 0x00003210 }, 4570 { 0x000081d0, 0x0000320a },
4589 { 0x000081ec, 0x00000000 }, 4571 { 0x000081ec, 0x00000000 },
4590 { 0x000081f0, 0x00000000 }, 4572 { 0x000081f0, 0x00000000 },
4591 { 0x000081f4, 0x00000000 }, 4573 { 0x000081f4, 0x00000000 },
@@ -4709,8 +4691,6 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = {
4709 { 0x0000a268, 0x00000000 }, 4691 { 0x0000a268, 0x00000000 },
4710 { 0x0000a26c, 0x0ebae9e6 }, 4692 { 0x0000a26c, 0x0ebae9e6 },
4711 { 0x0000d270, 0x0d820820 }, 4693 { 0x0000d270, 0x0d820820 },
4712 { 0x0000a278, 0x318c6318 },
4713 { 0x0000a27c, 0x050c0318 },
4714 { 0x0000d35c, 0x07ffffef }, 4694 { 0x0000d35c, 0x07ffffef },
4715 { 0x0000d360, 0x0fffffe7 }, 4695 { 0x0000d360, 0x0fffffe7 },
4716 { 0x0000d364, 0x17ffffe5 }, 4696 { 0x0000d364, 0x17ffffe5 },
@@ -4725,8 +4705,6 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = {
4725 { 0x0000a388, 0x0c000000 }, 4705 { 0x0000a388, 0x0c000000 },
4726 { 0x0000a38c, 0x20202020 }, 4706 { 0x0000a38c, 0x20202020 },
4727 { 0x0000a390, 0x20202020 }, 4707 { 0x0000a390, 0x20202020 },
4728 { 0x0000a394, 0x318c6318 },
4729 { 0x0000a398, 0x00000318 },
4730 { 0x0000a39c, 0x00000001 }, 4708 { 0x0000a39c, 0x00000001 },
4731 { 0x0000a3a0, 0x00000000 }, 4709 { 0x0000a3a0, 0x00000000 },
4732 { 0x0000a3a4, 0x00000000 }, 4710 { 0x0000a3a4, 0x00000000 },
@@ -4741,8 +4719,6 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = {
4741 { 0x0000a3cc, 0x20202020 }, 4719 { 0x0000a3cc, 0x20202020 },
4742 { 0x0000a3d0, 0x20202020 }, 4720 { 0x0000a3d0, 0x20202020 },
4743 { 0x0000a3d4, 0x20202020 }, 4721 { 0x0000a3d4, 0x20202020 },
4744 { 0x0000a3dc, 0x318c6318 },
4745 { 0x0000a3e0, 0x00000318 },
4746 { 0x0000a3e4, 0x00000000 }, 4722 { 0x0000a3e4, 0x00000000 },
4747 { 0x0000a3e8, 0x18c43433 }, 4723 { 0x0000a3e8, 0x18c43433 },
4748 { 0x0000a3ec, 0x00f70081 }, 4724 { 0x0000a3ec, 0x00f70081 },
@@ -4753,13 +4729,11 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = {
4753 { 0x00007810, 0x71c0d388 }, 4729 { 0x00007810, 0x71c0d388 },
4754 { 0x00007814, 0x924934a8 }, 4730 { 0x00007814, 0x924934a8 },
4755 { 0x0000781c, 0x00000000 }, 4731 { 0x0000781c, 0x00000000 },
4756 { 0x00007820, 0x00000c04 },
4757 { 0x00007824, 0x00d86fff }, 4732 { 0x00007824, 0x00d86fff },
4758 { 0x00007828, 0x26d2491b }, 4733 { 0x00007828, 0x26d2491b },
4759 { 0x0000782c, 0x6e36d97b }, 4734 { 0x0000782c, 0x6e36d97b },
4760 { 0x00007830, 0xedb6d96e }, 4735 { 0x00007830, 0xedb6d96e },
4761 { 0x00007834, 0x71400087 }, 4736 { 0x00007834, 0x71400087 },
4762 { 0x00007838, 0xfac68801 },
4763 { 0x0000783c, 0x0001fffe }, 4737 { 0x0000783c, 0x0001fffe },
4764 { 0x00007840, 0xffeb1a20 }, 4738 { 0x00007840, 0xffeb1a20 },
4765 { 0x00007844, 0x000c0db6 }, 4739 { 0x00007844, 0x000c0db6 },
@@ -4772,10 +4746,81 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = {
4772 { 0x00007860, 0x21084210 }, 4746 { 0x00007860, 0x21084210 },
4773 { 0x00007864, 0xf7d7ffde }, 4747 { 0x00007864, 0xf7d7ffde },
4774 { 0x00007868, 0xc2034080 }, 4748 { 0x00007868, 0xc2034080 },
4775 { 0x0000786c, 0x48609eb4 },
4776 { 0x00007870, 0x10142c00 }, 4749 { 0x00007870, 0x10142c00 },
4777}; 4750};
4778 4751
4752static const u_int32_t ar9285Modes_high_power_tx_gain_9285_1_2[][6] = {
4753 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
4754 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
4755 { 0x0000a304, 0x00000000, 0x00000000, 0x00005200, 0x00005200, 0x00000000 },
4756 { 0x0000a308, 0x00000000, 0x00000000, 0x00007201, 0x00007201, 0x00000000 },
4757 { 0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240, 0x00000000 },
4758 { 0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241, 0x00000000 },
4759 { 0x0000a314, 0x00000000, 0x00000000, 0x0000f440, 0x0000f440, 0x00000000 },
4760 { 0x0000a318, 0x00000000, 0x00000000, 0x00014640, 0x00014640, 0x00000000 },
4761 { 0x0000a31c, 0x00000000, 0x00000000, 0x00018680, 0x00018680, 0x00000000 },
4762 { 0x0000a320, 0x00000000, 0x00000000, 0x00019841, 0x00019841, 0x00000000 },
4763 { 0x0000a324, 0x00000000, 0x00000000, 0x0001ca40, 0x0001ca40, 0x00000000 },
4764 { 0x0000a328, 0x00000000, 0x00000000, 0x0001fa80, 0x0001fa80, 0x00000000 },
4765 { 0x0000a32c, 0x00000000, 0x00000000, 0x00023ac0, 0x00023ac0, 0x00000000 },
4766 { 0x0000a330, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40, 0x00000000 },
4767 { 0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82, 0x00000000 },
4768 { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
4769 { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
4770 { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
4771 { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
4772 { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
4773 { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
4774 { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
4775 { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
4776 { 0x00007838, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803 },
4777 { 0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe },
4778 { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 },
4779 { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a21a652, 0x0a21a652, 0x0a22a652 },
4780 { 0x0000a278, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce },
4781 { 0x0000a27c, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce },
4782 { 0x0000a394, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce },
4783 { 0x0000a398, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce },
4784 { 0x0000a3dc, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce },
4785 { 0x0000a3e0, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce },
4786};
4787
4788static const u_int32_t ar9285Modes_original_tx_gain_9285_1_2[][6] = {
4789 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
4790 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
4791 { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
4792 { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
4793 { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 },
4794 { 0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618, 0x00000000 },
4795 { 0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9, 0x00000000 },
4796 { 0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710, 0x00000000 },
4797 { 0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718, 0x00000000 },
4798 { 0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758, 0x00000000 },
4799 { 0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a, 0x00000000 },
4800 { 0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c, 0x00000000 },
4801 { 0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e, 0x00000000 },
4802 { 0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f, 0x00000000 },
4803 { 0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df, 0x00000000 },
4804 { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 },
4805 { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 },
4806 { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
4807 { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
4808 { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
4809 { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
4810 { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
4811 { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
4812 { 0x00007838, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801 },
4813 { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 },
4814 { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 },
4815 { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652, 0x0a22a652 },
4816 { 0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
4817 { 0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c },
4818 { 0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
4819 { 0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
4820 { 0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c },
4821 { 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
4822};
4823
4779static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = { 4824static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = {
4780 {0x00004040, 0x9248fd00 }, 4825 {0x00004040, 0x9248fd00 },
4781 {0x00004040, 0x24924924 }, 4826 {0x00004040, 0x24924924 },
diff --git a/drivers/net/wireless/ath9k/phy.h b/drivers/net/wireless/ath9k/phy.h
index 6222e32c7748..1eac8c707342 100644
--- a/drivers/net/wireless/ath9k/phy.h
+++ b/drivers/net/wireless/ath9k/phy.h
@@ -446,6 +446,9 @@ bool ath9k_hw_init_rf(struct ath_hw *ah,
446#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 446#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
447#define AR_PHY_TPCRG1_PD_GAIN_3_S 20 447#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
448 448
449#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
450#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
451
449#define AR_PHY_TX_PWRCTRL4 0xa264 452#define AR_PHY_TX_PWRCTRL4 0xa264
450#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001 453#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
451#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0 454#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0
@@ -513,6 +516,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah,
513/* Carrier leak calibration control, do it after AGC calibration */ 516/* Carrier leak calibration control, do it after AGC calibration */
514#define AR_PHY_CL_CAL_CTL 0xA358 517#define AR_PHY_CL_CAL_CTL 0xA358
515#define AR_PHY_CL_CAL_ENABLE 0x00000002 518#define AR_PHY_CL_CAL_ENABLE 0x00000002
519#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
516 520
517#define AR_PHY_POWER_TX_RATE5 0xA38C 521#define AR_PHY_POWER_TX_RATE5 0xA38C
518#define AR_PHY_POWER_TX_RATE6 0xA390 522#define AR_PHY_POWER_TX_RATE6 0xA390
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-07 11:29:12 -0500