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-rw-r--r--drivers/ata/ahci.c11
-rw-r--r--drivers/ata/libata-core.c67
-rw-r--r--drivers/ata/pata_scc.c13
-rw-r--r--drivers/ata/sata_inic162x.c2
4 files changed, 59 insertions, 34 deletions
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 49cf4cf1a5a2..93bcb2cb3d35 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1153,15 +1153,8 @@ static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1153 tf.ctl &= ~ATA_SRST; 1153 tf.ctl &= ~ATA_SRST;
1154 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1154 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1155 1155
1156 /* spec mandates ">= 2ms" before checking status. 1156 /* wait a while before checking status */
1157 * We wait 150ms, because that was the magic delay used for 1157 ata_wait_after_reset(ap, deadline);
1158 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1159 * between when the ATA command register is written, and then
1160 * status is checked. Because waiting for "a while" before
1161 * checking status is fine, post SRST, we perform this magic
1162 * delay here as well.
1163 */
1164 msleep(150);
1165 1158
1166 rc = ata_wait_ready(ap, deadline); 1159 rc = ata_wait_ready(ap, deadline);
1167 /* link occupied, -ENODEV too is an error */ 1160 /* link occupied, -ENODEV too is an error */
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 50ae20101d10..8ee56e5cfb0c 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -3118,6 +3118,55 @@ int ata_busy_sleep(struct ata_port *ap,
3118} 3118}
3119 3119
3120/** 3120/**
3121 * ata_wait_after_reset - wait before checking status after reset
3122 * @ap: port containing status register to be polled
3123 * @deadline: deadline jiffies for the operation
3124 *
3125 * After reset, we need to pause a while before reading status.
3126 * Also, certain combination of controller and device report 0xff
3127 * for some duration (e.g. until SATA PHY is up and running)
3128 * which is interpreted as empty port in ATA world. This
3129 * function also waits for such devices to get out of 0xff
3130 * status.
3131 *
3132 * LOCKING:
3133 * Kernel thread context (may sleep).
3134 */
3135void ata_wait_after_reset(struct ata_port *ap, unsigned long deadline)
3136{
3137 unsigned long until = jiffies + ATA_TMOUT_FF_WAIT;
3138
3139 if (time_before(until, deadline))
3140 deadline = until;
3141
3142 /* Spec mandates ">= 2ms" before checking status. We wait
3143 * 150ms, because that was the magic delay used for ATAPI
3144 * devices in Hale Landis's ATADRVR, for the period of time
3145 * between when the ATA command register is written, and then
3146 * status is checked. Because waiting for "a while" before
3147 * checking status is fine, post SRST, we perform this magic
3148 * delay here as well.
3149 *
3150 * Old drivers/ide uses the 2mS rule and then waits for ready.
3151 */
3152 msleep(150);
3153
3154 /* Wait for 0xff to clear. Some SATA devices take a long time
3155 * to clear 0xff after reset. For example, HHD424020F7SV00
3156 * iVDR needs >= 800ms while. Quantum GoVault needs even more
3157 * than that.
3158 */
3159 while (1) {
3160 u8 status = ata_chk_status(ap);
3161
3162 if (status != 0xff || time_after(jiffies, deadline))
3163 return;
3164
3165 msleep(50);
3166 }
3167}
3168
3169/**
3121 * ata_wait_ready - sleep until BSY clears, or timeout 3170 * ata_wait_ready - sleep until BSY clears, or timeout
3122 * @ap: port containing status register to be polled 3171 * @ap: port containing status register to be polled
3123 * @deadline: deadline jiffies for the operation 3172 * @deadline: deadline jiffies for the operation
@@ -3254,17 +3303,8 @@ static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
3254 ap->ops->set_piomode(ap, dev); 3303 ap->ops->set_piomode(ap, dev);
3255 } 3304 }
3256 3305
3257 /* spec mandates ">= 2ms" before checking status. 3306 /* wait a while before checking status */
3258 * We wait 150ms, because that was the magic delay used for 3307 ata_wait_after_reset(ap, deadline);
3259 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
3260 * between when the ATA command register is written, and then
3261 * status is checked. Because waiting for "a while" before
3262 * checking status is fine, post SRST, we perform this magic
3263 * delay here as well.
3264 *
3265 * Old drivers/ide uses the 2mS rule and then waits for ready
3266 */
3267 msleep(150);
3268 3308
3269 /* Before we perform post reset processing we want to see if 3309 /* Before we perform post reset processing we want to see if
3270 * the bus shows 0xFF because the odd clown forgets the D7 3310 * the bus shows 0xFF because the odd clown forgets the D7
@@ -3691,8 +3731,8 @@ int sata_std_hardreset(struct ata_link *link, unsigned int *class,
3691 return 0; 3731 return 0;
3692 } 3732 }
3693 3733
3694 /* wait a while before checking status, see SRST for more info */ 3734 /* wait a while before checking status */
3695 msleep(150); 3735 ata_wait_after_reset(ap, deadline);
3696 3736
3697 /* If PMP is supported, we have to do follow-up SRST. Note 3737 /* If PMP is supported, we have to do follow-up SRST. Note
3698 * that some PMPs don't send D2H Reg FIS after hardreset at 3738 * that some PMPs don't send D2H Reg FIS after hardreset at
@@ -7358,6 +7398,7 @@ EXPORT_SYMBOL_GPL(ata_port_disable);
7358EXPORT_SYMBOL_GPL(ata_ratelimit); 7398EXPORT_SYMBOL_GPL(ata_ratelimit);
7359EXPORT_SYMBOL_GPL(ata_wait_register); 7399EXPORT_SYMBOL_GPL(ata_wait_register);
7360EXPORT_SYMBOL_GPL(ata_busy_sleep); 7400EXPORT_SYMBOL_GPL(ata_busy_sleep);
7401EXPORT_SYMBOL_GPL(ata_wait_after_reset);
7361EXPORT_SYMBOL_GPL(ata_wait_ready); 7402EXPORT_SYMBOL_GPL(ata_wait_ready);
7362EXPORT_SYMBOL_GPL(ata_port_queue_task); 7403EXPORT_SYMBOL_GPL(ata_port_queue_task);
7363EXPORT_SYMBOL_GPL(ata_scsi_ioctl); 7404EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
diff --git a/drivers/ata/pata_scc.c b/drivers/ata/pata_scc.c
index 55576138faea..ea2ef9fc15be 100644
--- a/drivers/ata/pata_scc.c
+++ b/drivers/ata/pata_scc.c
@@ -570,17 +570,8 @@ static unsigned int scc_bus_softreset(struct ata_port *ap, unsigned int devmask,
570 udelay(20); 570 udelay(20);
571 out_be32(ioaddr->ctl_addr, ap->ctl); 571 out_be32(ioaddr->ctl_addr, ap->ctl);
572 572
573 /* spec mandates ">= 2ms" before checking status. 573 /* wait a while before checking status */
574 * We wait 150ms, because that was the magic delay used for 574 ata_wait_after_reset(ap, deadline);
575 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
576 * between when the ATA command register is written, and then
577 * status is checked. Because waiting for "a while" before
578 * checking status is fine, post SRST, we perform this magic
579 * delay here as well.
580 *
581 * Old drivers/ide uses the 2mS rule and then waits for ready
582 */
583 msleep(150);
584 575
585 /* Before we perform post reset processing we want to see if 576 /* Before we perform post reset processing we want to see if
586 * the bus shows 0xFF because the odd clown forgets the D7 577 * the bus shows 0xFF because the odd clown forgets the D7
diff --git a/drivers/ata/sata_inic162x.c b/drivers/ata/sata_inic162x.c
index 08595f34b3e8..b97d077e61b5 100644
--- a/drivers/ata/sata_inic162x.c
+++ b/drivers/ata/sata_inic162x.c
@@ -448,7 +448,7 @@ static int inic_hardreset(struct ata_link *link, unsigned int *class,
448 struct ata_taskfile tf; 448 struct ata_taskfile tf;
449 449
450 /* wait a while before checking status */ 450 /* wait a while before checking status */
451 msleep(150); 451 ata_wait_after_reset(ap, deadline);
452 452
453 rc = ata_wait_ready(ap, deadline); 453 rc = ata_wait_ready(ap, deadline);
454 /* link occupied, -ENODEV too is an error */ 454 /* link occupied, -ENODEV too is an error */