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-rw-r--r--drivers/usb/gadget/Kconfig36
-rw-r--r--drivers/usb/gadget/gadget_chips.h2
-rw-r--r--drivers/usb/gadget/m66592-udc.c255
-rw-r--r--drivers/usb/gadget/m66592-udc.h610
4 files changed, 450 insertions, 453 deletions
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 1553e9a649cd..767aed5b4bea 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -177,6 +177,24 @@ config USB_PXA2XX_SMALL
177 default y if USB_ETH 177 default y if USB_ETH
178 default y if USB_G_SERIAL 178 default y if USB_G_SERIAL
179 179
180config USB_GADGET_M66592
181 boolean "Renesas M66592 USB Peripheral Controller"
182 select USB_GADGET_DUALSPEED
183 help
184 M66592 is a discrete USB peripheral controller chip that
185 supports both full and high speed USB 2.0 data transfers.
186 It has seven configurable endpoints, and endpoint zero.
187
188 Say "y" to link the driver statically, or "m" to build a
189 dynamically linked module called "m66592_udc" and force all
190 gadget drivers to also be dynamically linked.
191
192config USB_M66592
193 tristate
194 depends on USB_GADGET_M66592
195 default USB_GADGET
196 select USB_GADGET_SELECTED
197
180config USB_GADGET_GOKU 198config USB_GADGET_GOKU
181 boolean "Toshiba TC86C001 'Goku-S'" 199 boolean "Toshiba TC86C001 'Goku-S'"
182 depends on PCI 200 depends on PCI
@@ -282,24 +300,6 @@ config USB_AT91
282 depends on USB_GADGET_AT91 300 depends on USB_GADGET_AT91
283 default USB_GADGET 301 default USB_GADGET
284 302
285config USB_GADGET_M66592
286 boolean "M66592 driver"
287 select USB_GADGET_DUALSPEED
288 help
289 M66592 is a USB 2.0 peripheral controller.
290
291 It has seven configurable endpoints, and endpoint zero.
292
293 Say "y" to link the driver statically, or "m" to build a
294 dynamically linked module called "m66592_udc" and force all
295 gadget drivers to also be dynamically linked.
296
297config USB_M66592
298 tristate
299 depends on USB_GADGET_M66592
300 default USB_GADGET
301 select USB_GADGET_SELECTED
302
303config USB_GADGET_DUMMY_HCD 303config USB_GADGET_DUMMY_HCD
304 boolean "Dummy HCD (DEVELOPMENT)" 304 boolean "Dummy HCD (DEVELOPMENT)"
305 depends on (USB=y || (USB=m && USB_GADGET=m)) && EXPERIMENTAL 305 depends on (USB=y || (USB=m && USB_GADGET=m)) && EXPERIMENTAL
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index e7fbefefe7b0..f7f159c1002b 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -211,6 +211,6 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
211 else if (gadget_is_amd5536udc(gadget)) 211 else if (gadget_is_amd5536udc(gadget))
212 return 0x20; 212 return 0x20;
213 else if (gadget_is_m66592(gadget)) 213 else if (gadget_is_m66592(gadget))
214 return 0x20; 214 return 0x21;
215 return -ENOENT; 215 return -ENOENT;
216} 216}
diff --git a/drivers/usb/gadget/m66592-udc.c b/drivers/usb/gadget/m66592-udc.c
index 0174a322e007..700dda8a9157 100644
--- a/drivers/usb/gadget/m66592-udc.c
+++ b/drivers/usb/gadget/m66592-udc.c
@@ -21,26 +21,18 @@
21 */ 21 */
22 22
23#include <linux/module.h> 23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/sched.h>
26#include <linux/smp_lock.h>
27#include <linux/errno.h>
28#include <linux/init.h>
29#include <linux/timer.h>
30#include <linux/delay.h>
31#include <linux/list.h>
32#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <linux/delay.h>
26#include <linux/io.h>
33#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28
34#include <linux/usb/ch9.h> 29#include <linux/usb/ch9.h>
35#include <linux/usb_gadget.h> 30#include <linux/usb_gadget.h>
36 31
37#include <asm/io.h>
38#include <asm/irq.h>
39#include <asm/system.h>
40
41#include "m66592-udc.h" 32#include "m66592-udc.h"
42 33
43MODULE_DESCRIPTION("M66592 USB gadget driiver"); 34
35MODULE_DESCRIPTION("M66592 USB gadget driver");
44MODULE_LICENSE("GPL"); 36MODULE_LICENSE("GPL");
45MODULE_AUTHOR("Yoshihiro Shimoda"); 37MODULE_AUTHOR("Yoshihiro Shimoda");
46 38
@@ -49,16 +41,21 @@ MODULE_AUTHOR("Yoshihiro Shimoda");
49/* module parameters */ 41/* module parameters */
50static unsigned short clock = M66592_XTAL24; 42static unsigned short clock = M66592_XTAL24;
51module_param(clock, ushort, 0644); 43module_param(clock, ushort, 0644);
52MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0(default=16384)"); 44MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0 "
45 "(default=16384)");
46
53static unsigned short vif = M66592_LDRV; 47static unsigned short vif = M66592_LDRV;
54module_param(vif, ushort, 0644); 48module_param(vif, ushort, 0644);
55MODULE_PARM_DESC(vif, "input VIF: 3.3V=32768, 1.5V=0(default=32768)"); 49MODULE_PARM_DESC(vif, "input VIF: 3.3V=32768, 1.5V=0 (default=32768)");
56static unsigned short endian = 0; 50
51static unsigned short endian;
57module_param(endian, ushort, 0644); 52module_param(endian, ushort, 0644);
58MODULE_PARM_DESC(endian, "data endian: big=256, little=0(default=0)"); 53MODULE_PARM_DESC(endian, "data endian: big=256, little=0 (default=0)");
54
59static unsigned short irq_sense = M66592_INTL; 55static unsigned short irq_sense = M66592_INTL;
60module_param(irq_sense, ushort, 0644); 56module_param(irq_sense, ushort, 0644);
61MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=2, falling edge=0(default=2)"); 57MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=2, falling edge=0 "
58 "(default=2)");
62 59
63static const char udc_name[] = "m66592_udc"; 60static const char udc_name[] = "m66592_udc";
64static const char *m66592_ep_name[] = { 61static const char *m66592_ep_name[] = {
@@ -72,8 +69,8 @@ static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
72 gfp_t gfp_flags); 69 gfp_t gfp_flags);
73 70
74static void transfer_complete(struct m66592_ep *ep, 71static void transfer_complete(struct m66592_ep *ep,
75 struct m66592_request *req, 72 struct m66592_request *req, int status);
76 int status); 73
77/*-------------------------------------------------------------------------*/ 74/*-------------------------------------------------------------------------*/
78static inline u16 get_usb_speed(struct m66592 *m66592) 75static inline u16 get_usb_speed(struct m66592 *m66592)
79{ 76{
@@ -81,25 +78,25 @@ static inline u16 get_usb_speed(struct m66592 *m66592)
81} 78}
82 79
83static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum, 80static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum,
84 unsigned long reg) 81 unsigned long reg)
85{ 82{
86 u16 tmp; 83 u16 tmp;
87 84
88 tmp = m66592_read(m66592, M66592_INTENB0); 85 tmp = m66592_read(m66592, M66592_INTENB0);
89 m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE, 86 m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
90 M66592_INTENB0); 87 M66592_INTENB0);
91 m66592_bset(m66592, (1 << pipenum), reg); 88 m66592_bset(m66592, (1 << pipenum), reg);
92 m66592_write(m66592, tmp, M66592_INTENB0); 89 m66592_write(m66592, tmp, M66592_INTENB0);
93} 90}
94 91
95static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum, 92static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum,
96 unsigned long reg) 93 unsigned long reg)
97{ 94{
98 u16 tmp; 95 u16 tmp;
99 96
100 tmp = m66592_read(m66592, M66592_INTENB0); 97 tmp = m66592_read(m66592, M66592_INTENB0);
101 m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE, 98 m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
102 M66592_INTENB0); 99 M66592_INTENB0);
103 m66592_bclr(m66592, (1 << pipenum), reg); 100 m66592_bclr(m66592, (1 << pipenum), reg);
104 m66592_write(m66592, tmp, M66592_INTENB0); 101 m66592_write(m66592, tmp, M66592_INTENB0);
105} 102}
@@ -108,17 +105,19 @@ static void m66592_usb_connect(struct m66592 *m66592)
108{ 105{
109 m66592_bset(m66592, M66592_CTRE, M66592_INTENB0); 106 m66592_bset(m66592, M66592_CTRE, M66592_INTENB0);
110 m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL, 107 m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
111 M66592_INTENB0); 108 M66592_INTENB0);
112 m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0); 109 m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
113 110
114 m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG); 111 m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
115} 112}
116 113
117static void m66592_usb_disconnect(struct m66592 *m66592) 114static void m66592_usb_disconnect(struct m66592 *m66592)
115__releases(m66592->lock)
116__acquires(m66592->lock)
118{ 117{
119 m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0); 118 m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0);
120 m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL, 119 m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
121 M66592_INTENB0); 120 M66592_INTENB0);
122 m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0); 121 m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
123 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG); 122 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
124 123
@@ -148,7 +147,7 @@ static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum)
148} 147}
149 148
150static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum, 149static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum,
151 u16 pid) 150 u16 pid)
152{ 151{
153 unsigned long offset; 152 unsigned long offset;
154 153
@@ -250,7 +249,7 @@ static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
250} 249}
251 250
252static int pipe_buffer_setting(struct m66592 *m66592, 251static int pipe_buffer_setting(struct m66592 *m66592,
253 struct m66592_pipe_info *info) 252 struct m66592_pipe_info *info)
254{ 253{
255 u16 bufnum = 0, buf_bsize = 0; 254 u16 bufnum = 0, buf_bsize = 0;
256 u16 pipecfg = 0; 255 u16 pipecfg = 0;
@@ -287,7 +286,7 @@ static int pipe_buffer_setting(struct m66592 *m66592,
287 } 286 }
288 if (m66592->bi_bufnum > M66592_MAX_BUFNUM) { 287 if (m66592->bi_bufnum > M66592_MAX_BUFNUM) {
289 printk(KERN_ERR "m66592 pipe memory is insufficient(%d)\n", 288 printk(KERN_ERR "m66592 pipe memory is insufficient(%d)\n",
290 m66592->bi_bufnum); 289 m66592->bi_bufnum);
291 return -ENOMEM; 290 return -ENOMEM;
292 } 291 }
293 292
@@ -328,7 +327,7 @@ static void pipe_buffer_release(struct m66592 *m66592,
328 m66592->bulk--; 327 m66592->bulk--;
329 } else 328 } else
330 printk(KERN_ERR "ep_release: unexpect pipenum (%d)\n", 329 printk(KERN_ERR "ep_release: unexpect pipenum (%d)\n",
331 info->pipe); 330 info->pipe);
332} 331}
333 332
334static void pipe_initialize(struct m66592_ep *ep) 333static void pipe_initialize(struct m66592_ep *ep)
@@ -350,8 +349,8 @@ static void pipe_initialize(struct m66592_ep *ep)
350} 349}
351 350
352static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep, 351static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
353 const struct usb_endpoint_descriptor *desc, 352 const struct usb_endpoint_descriptor *desc,
354 u16 pipenum, int dma) 353 u16 pipenum, int dma)
355{ 354{
356 if ((pipenum != 0) && dma) { 355 if ((pipenum != 0) && dma) {
357 if (m66592->num_dma == 0) { 356 if (m66592->num_dma == 0) {
@@ -385,7 +384,7 @@ static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
385 384
386 ep->pipectr = get_pipectr_addr(pipenum); 385 ep->pipectr = get_pipectr_addr(pipenum);
387 ep->pipenum = pipenum; 386 ep->pipenum = pipenum;
388 ep->ep.maxpacket = desc->wMaxPacketSize; 387 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
389 m66592->pipenum2ep[pipenum] = ep; 388 m66592->pipenum2ep[pipenum] = ep;
390 m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep; 389 m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep;
391 INIT_LIST_HEAD(&ep->queue); 390 INIT_LIST_HEAD(&ep->queue);
@@ -407,7 +406,7 @@ static void m66592_ep_release(struct m66592_ep *ep)
407} 406}
408 407
409static int alloc_pipe_config(struct m66592_ep *ep, 408static int alloc_pipe_config(struct m66592_ep *ep,
410 const struct usb_endpoint_descriptor *desc) 409 const struct usb_endpoint_descriptor *desc)
411{ 410{
412 struct m66592 *m66592 = ep->m66592; 411 struct m66592 *m66592 = ep->m66592;
413 struct m66592_pipe_info info; 412 struct m66592_pipe_info info;
@@ -419,15 +418,15 @@ static int alloc_pipe_config(struct m66592_ep *ep,
419 418
420 BUG_ON(ep->pipenum); 419 BUG_ON(ep->pipenum);
421 420
422 switch(desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { 421 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
423 case USB_ENDPOINT_XFER_BULK: 422 case USB_ENDPOINT_XFER_BULK:
424 if (m66592->bulk >= M66592_MAX_NUM_BULK) { 423 if (m66592->bulk >= M66592_MAX_NUM_BULK) {
425 if (m66592->isochronous >= M66592_MAX_NUM_ISOC) { 424 if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
426 printk(KERN_ERR "bulk pipe is insufficient\n"); 425 printk(KERN_ERR "bulk pipe is insufficient\n");
427 return -ENODEV; 426 return -ENODEV;
428 } else { 427 } else {
429 info.pipe = M66592_BASE_PIPENUM_ISOC + 428 info.pipe = M66592_BASE_PIPENUM_ISOC
430 m66592->isochronous; 429 + m66592->isochronous;
431 counter = &m66592->isochronous; 430 counter = &m66592->isochronous;
432 } 431 }
433 } else { 432 } else {
@@ -462,7 +461,7 @@ static int alloc_pipe_config(struct m66592_ep *ep,
462 ep->type = info.type; 461 ep->type = info.type;
463 462
464 info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; 463 info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
465 info.maxpacket = desc->wMaxPacketSize; 464 info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
466 info.interval = desc->bInterval; 465 info.interval = desc->bInterval;
467 if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) 466 if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
468 info.dir_in = 1; 467 info.dir_in = 1;
@@ -525,8 +524,8 @@ static void start_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
525 524
526 pipe_change(m66592, ep->pipenum); 525 pipe_change(m66592, ep->pipenum);
527 m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0, 526 m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0,
528 (M66592_ISEL | M66592_CURPIPE), 527 (M66592_ISEL | M66592_CURPIPE),
529 M66592_CFIFOSEL); 528 M66592_CFIFOSEL);
530 m66592_write(m66592, M66592_BCLR, ep->fifoctr); 529 m66592_write(m66592, M66592_BCLR, ep->fifoctr);
531 if (req->req.length == 0) { 530 if (req->req.length == 0) {
532 m66592_bset(m66592, M66592_BVAL, ep->fifoctr); 531 m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
@@ -561,8 +560,8 @@ static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req)
561 560
562 if (ep->pipenum == 0) { 561 if (ep->pipenum == 0) {
563 m66592_mdfy(m66592, M66592_PIPE0, 562 m66592_mdfy(m66592, M66592_PIPE0,
564 (M66592_ISEL | M66592_CURPIPE), 563 (M66592_ISEL | M66592_CURPIPE),
565 M66592_CFIFOSEL); 564 M66592_CFIFOSEL);
566 m66592_write(m66592, M66592_BCLR, ep->fifoctr); 565 m66592_write(m66592, M66592_BCLR, ep->fifoctr);
567 pipe_start(m66592, pipenum); 566 pipe_start(m66592, pipenum);
568 pipe_irq_enable(m66592, pipenum); 567 pipe_irq_enable(m66592, pipenum);
@@ -572,8 +571,9 @@ static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req)
572 pipe_change(m66592, pipenum); 571 pipe_change(m66592, pipenum);
573 m66592_bset(m66592, M66592_TRENB, ep->fifosel); 572 m66592_bset(m66592, M66592_TRENB, ep->fifosel);
574 m66592_write(m66592, 573 m66592_write(m66592,
575 (req->req.length + ep->ep.maxpacket - 1) / 574 (req->req.length + ep->ep.maxpacket - 1)
576 ep->ep.maxpacket, ep->fifotrn); 575 / ep->ep.maxpacket,
576 ep->fifotrn);
577 } 577 }
578 pipe_start(m66592, pipenum); /* trigger once */ 578 pipe_start(m66592, pipenum); /* trigger once */
579 pipe_irq_enable(m66592, pipenum); 579 pipe_irq_enable(m66592, pipenum);
@@ -614,7 +614,7 @@ static void start_ep0(struct m66592_ep *ep, struct m66592_request *req)
614static void init_controller(struct m66592 *m66592) 614static void init_controller(struct m66592 *m66592)
615{ 615{
616 m66592_bset(m66592, (vif & M66592_LDRV) | (endian & M66592_BIGEND), 616 m66592_bset(m66592, (vif & M66592_LDRV) | (endian & M66592_BIGEND),
617 M66592_PINCFG); 617 M66592_PINCFG);
618 m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */ 618 m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
619 m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL, M66592_SYSCFG); 619 m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL, M66592_SYSCFG);
620 620
@@ -634,7 +634,7 @@ static void init_controller(struct m66592 *m66592)
634 634
635 m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1); 635 m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1);
636 m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR, 636 m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR,
637 M66592_DMA0CFG); 637 M66592_DMA0CFG);
638} 638}
639 639
640static void disable_controller(struct m66592 *m66592) 640static void disable_controller(struct m66592 *m66592)
@@ -659,8 +659,9 @@ static void m66592_start_xclock(struct m66592 *m66592)
659 659
660/*-------------------------------------------------------------------------*/ 660/*-------------------------------------------------------------------------*/
661static void transfer_complete(struct m66592_ep *ep, 661static void transfer_complete(struct m66592_ep *ep,
662 struct m66592_request *req, 662 struct m66592_request *req, int status)
663 int status) 663__releases(m66592->lock)
664__acquires(m66592->lock)
664{ 665{
665 int restart = 0; 666 int restart = 0;
666 667
@@ -680,8 +681,9 @@ static void transfer_complete(struct m66592_ep *ep,
680 if (!list_empty(&ep->queue)) 681 if (!list_empty(&ep->queue))
681 restart = 1; 682 restart = 1;
682 683
683 if (likely(req->req.complete)) 684 spin_unlock(&ep->m66592->lock);
684 req->req.complete(&ep->ep, &req->req); 685 req->req.complete(&ep->ep, &req->req);
686 spin_lock(&ep->m66592->lock);
685 687
686 if (restart) { 688 if (restart) {
687 req = list_entry(ep->queue.next, struct m66592_request, queue); 689 req = list_entry(ep->queue.next, struct m66592_request, queue);
@@ -693,7 +695,7 @@ static void transfer_complete(struct m66592_ep *ep,
693static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req) 695static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
694{ 696{
695 int i; 697 int i;
696 volatile u16 tmp; 698 u16 tmp;
697 unsigned bufsize; 699 unsigned bufsize;
698 size_t size; 700 size_t size;
699 void *buf; 701 void *buf;
@@ -731,8 +733,9 @@ static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
731 req->req.actual += size; 733 req->req.actual += size;
732 734
733 /* check transfer finish */ 735 /* check transfer finish */
734 if ((!req->req.zero && (req->req.actual == req->req.length)) || 736 if ((!req->req.zero && (req->req.actual == req->req.length))
735 (size % ep->ep.maxpacket) || (size == 0)) { 737 || (size % ep->ep.maxpacket)
738 || (size == 0)) {
736 disable_irq_ready(m66592, pipenum); 739 disable_irq_ready(m66592, pipenum);
737 disable_irq_empty(m66592, pipenum); 740 disable_irq_empty(m66592, pipenum);
738 } else { 741 } else {
@@ -768,16 +771,19 @@ static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req)
768 /* write fifo */ 771 /* write fifo */
769 if (req->req.buf) { 772 if (req->req.buf) {
770 m66592_write_fifo(m66592, ep->fifoaddr, buf, size); 773 m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
771 if ((size == 0) || ((size % ep->ep.maxpacket) != 0) || 774 if ((size == 0)
772 ((bufsize != ep->ep.maxpacket) && (bufsize > size))) 775 || ((size % ep->ep.maxpacket) != 0)
776 || ((bufsize != ep->ep.maxpacket)
777 && (bufsize > size)))
773 m66592_bset(m66592, M66592_BVAL, ep->fifoctr); 778 m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
774 } 779 }
775 780
776 /* update parameters */ 781 /* update parameters */
777 req->req.actual += size; 782 req->req.actual += size;
778 /* check transfer finish */ 783 /* check transfer finish */
779 if ((!req->req.zero && (req->req.actual == req->req.length)) || 784 if ((!req->req.zero && (req->req.actual == req->req.length))
780 (size % ep->ep.maxpacket) || (size == 0)) { 785 || (size % ep->ep.maxpacket)
786 || (size == 0)) {
781 disable_irq_ready(m66592, pipenum); 787 disable_irq_ready(m66592, pipenum);
782 enable_irq_empty(m66592, pipenum); 788 enable_irq_empty(m66592, pipenum);
783 } else { 789 } else {
@@ -821,8 +827,9 @@ static void irq_packet_read(struct m66592_ep *ep, struct m66592_request *req)
821 req->req.actual += size; 827 req->req.actual += size;
822 828
823 /* check transfer finish */ 829 /* check transfer finish */
824 if ((!req->req.zero && (req->req.actual == req->req.length)) || 830 if ((!req->req.zero && (req->req.actual == req->req.length))
825 (size % ep->ep.maxpacket) || (size == 0)) { 831 || (size % ep->ep.maxpacket)
832 || (size == 0)) {
826 pipe_stop(m66592, pipenum); 833 pipe_stop(m66592, pipenum);
827 pipe_irq_disable(m66592, pipenum); 834 pipe_irq_disable(m66592, pipenum);
828 finish = 1; 835 finish = 1;
@@ -850,7 +857,7 @@ static void irq_pipe_ready(struct m66592 *m66592, u16 status, u16 enb)
850 if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) { 857 if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) {
851 m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS); 858 m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS);
852 m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE, 859 m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE,
853 M66592_CFIFOSEL); 860 M66592_CFIFOSEL);
854 861
855 ep = &m66592->ep[0]; 862 ep = &m66592->ep[0];
856 req = list_entry(ep->queue.next, struct m66592_request, queue); 863 req = list_entry(ep->queue.next, struct m66592_request, queue);
@@ -909,23 +916,26 @@ static void irq_pipe_empty(struct m66592 *m66592, u16 status, u16 enb)
909} 916}
910 917
911static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl) 918static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
919__releases(m66592->lock)
920__acquires(m66592->lock)
912{ 921{
913 struct m66592_ep *ep; 922 struct m66592_ep *ep;
914 u16 pid; 923 u16 pid;
915 u16 status = 0; 924 u16 status = 0;
925 u16 w_index = le16_to_cpu(ctrl->wIndex);
916 926
917 switch (ctrl->bRequestType & USB_RECIP_MASK) { 927 switch (ctrl->bRequestType & USB_RECIP_MASK) {
918 case USB_RECIP_DEVICE: 928 case USB_RECIP_DEVICE:
919 status = 1; /* selfpower */ 929 status = 1 << USB_DEVICE_SELF_POWERED;
920 break; 930 break;
921 case USB_RECIP_INTERFACE: 931 case USB_RECIP_INTERFACE:
922 status = 0; 932 status = 0;
923 break; 933 break;
924 case USB_RECIP_ENDPOINT: 934 case USB_RECIP_ENDPOINT:
925 ep = m66592->epaddr2ep[ctrl->wIndex&USB_ENDPOINT_NUMBER_MASK]; 935 ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
926 pid = control_reg_get_pid(m66592, ep->pipenum); 936 pid = control_reg_get_pid(m66592, ep->pipenum);
927 if (pid == M66592_PID_STALL) 937 if (pid == M66592_PID_STALL)
928 status = 1; 938 status = 1 << USB_ENDPOINT_HALT;
929 else 939 else
930 status = 0; 940 status = 0;
931 break; 941 break;
@@ -934,11 +944,13 @@ static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
934 return; /* exit */ 944 return; /* exit */
935 } 945 }
936 946
937 *m66592->ep0_buf = status; 947 m66592->ep0_data = cpu_to_le16(status);
938 m66592->ep0_req->buf = m66592->ep0_buf; 948 m66592->ep0_req->buf = &m66592->ep0_data;
939 m66592->ep0_req->length = 2; 949 m66592->ep0_req->length = 2;
940 /* AV: what happens if we get called again before that gets through? */ 950 /* AV: what happens if we get called again before that gets through? */
951 spin_unlock(&m66592->lock);
941 m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL); 952 m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL);
953 spin_lock(&m66592->lock);
942} 954}
943 955
944static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl) 956static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
@@ -953,8 +965,9 @@ static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
953 case USB_RECIP_ENDPOINT: { 965 case USB_RECIP_ENDPOINT: {
954 struct m66592_ep *ep; 966 struct m66592_ep *ep;
955 struct m66592_request *req; 967 struct m66592_request *req;
968 u16 w_index = le16_to_cpu(ctrl->wIndex);
956 969
957 ep = m66592->epaddr2ep[ctrl->wIndex&USB_ENDPOINT_NUMBER_MASK]; 970 ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
958 pipe_stop(m66592, ep->pipenum); 971 pipe_stop(m66592, ep->pipenum);
959 control_reg_sqclr(m66592, ep->pipenum); 972 control_reg_sqclr(m66592, ep->pipenum);
960 973
@@ -989,8 +1002,9 @@ static void set_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
989 break; 1002 break;
990 case USB_RECIP_ENDPOINT: { 1003 case USB_RECIP_ENDPOINT: {
991 struct m66592_ep *ep; 1004 struct m66592_ep *ep;
1005 u16 w_index = le16_to_cpu(ctrl->wIndex);
992 1006
993 ep = m66592->epaddr2ep[ctrl->wIndex&USB_ENDPOINT_NUMBER_MASK]; 1007 ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
994 pipe_stall(m66592, ep->pipenum); 1008 pipe_stall(m66592, ep->pipenum);
995 1009
996 control_end(m66592, 1); 1010 control_end(m66592, 1);
@@ -1066,14 +1080,16 @@ static void irq_device_state(struct m66592 *m66592)
1066 } 1080 }
1067 if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG) 1081 if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG)
1068 m66592_update_usb_speed(m66592); 1082 m66592_update_usb_speed(m66592);
1069 if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS) && 1083 if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS)
1070 m66592->gadget.speed == USB_SPEED_UNKNOWN) 1084 && m66592->gadget.speed == USB_SPEED_UNKNOWN)
1071 m66592_update_usb_speed(m66592); 1085 m66592_update_usb_speed(m66592);
1072 1086
1073 m66592->old_dvsq = dvsq; 1087 m66592->old_dvsq = dvsq;
1074} 1088}
1075 1089
1076static void irq_control_stage(struct m66592 *m66592) 1090static void irq_control_stage(struct m66592 *m66592)
1091__releases(m66592->lock)
1092__acquires(m66592->lock)
1077{ 1093{
1078 struct usb_ctrlrequest ctrl; 1094 struct usb_ctrlrequest ctrl;
1079 u16 ctsq; 1095 u16 ctsq;
@@ -1095,8 +1111,10 @@ static void irq_control_stage(struct m66592 *m66592)
1095 case M66592_CS_WRDS: 1111 case M66592_CS_WRDS:
1096 case M66592_CS_WRND: 1112 case M66592_CS_WRND:
1097 if (setup_packet(m66592, &ctrl)) { 1113 if (setup_packet(m66592, &ctrl)) {
1114 spin_unlock(&m66592->lock);
1098 if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0) 1115 if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0)
1099 pipe_stall(m66592, 0); 1116 pipe_stall(m66592, 0);
1117 spin_lock(&m66592->lock);
1100 } 1118 }
1101 break; 1119 break;
1102 case M66592_CS_RDSS: 1120 case M66592_CS_RDSS:
@@ -1119,6 +1137,8 @@ static irqreturn_t m66592_irq(int irq, void *_m66592)
1119 u16 savepipe; 1137 u16 savepipe;
1120 u16 mask0; 1138 u16 mask0;
1121 1139
1140 spin_lock(&m66592->lock);
1141
1122 intsts0 = m66592_read(m66592, M66592_INTSTS0); 1142 intsts0 = m66592_read(m66592, M66592_INTSTS0);
1123 intenb0 = m66592_read(m66592, M66592_INTENB0); 1143 intenb0 = m66592_read(m66592, M66592_INTENB0);
1124 1144
@@ -1134,27 +1154,27 @@ static irqreturn_t m66592_irq(int irq, void *_m66592)
1134 bempenb = m66592_read(m66592, M66592_BEMPENB); 1154 bempenb = m66592_read(m66592, M66592_BEMPENB);
1135 1155
1136 if (mask0 & M66592_VBINT) { 1156 if (mask0 & M66592_VBINT) {
1137 m66592_write(m66592, (u16)~M66592_VBINT, 1157 m66592_write(m66592, 0xffff & ~M66592_VBINT,
1138 M66592_INTSTS0); 1158 M66592_INTSTS0);
1139 m66592_start_xclock(m66592); 1159 m66592_start_xclock(m66592);
1140 1160
1141 /* start vbus sampling */ 1161 /* start vbus sampling */
1142 m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0) 1162 m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0)
1143 & M66592_VBSTS; 1163 & M66592_VBSTS;
1144 m66592->scount = M66592_MAX_SAMPLING; 1164 m66592->scount = M66592_MAX_SAMPLING;
1145 1165
1146 mod_timer(&m66592->timer, 1166 mod_timer(&m66592->timer,
1147 jiffies + msecs_to_jiffies(50)); 1167 jiffies + msecs_to_jiffies(50));
1148 } 1168 }
1149 if (intsts0 & M66592_DVSQ) 1169 if (intsts0 & M66592_DVSQ)
1150 irq_device_state(m66592); 1170 irq_device_state(m66592);
1151 1171
1152 if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE) && 1172 if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE)
1153 (brdysts & brdyenb)) { 1173 && (brdysts & brdyenb)) {
1154 irq_pipe_ready(m66592, brdysts, brdyenb); 1174 irq_pipe_ready(m66592, brdysts, brdyenb);
1155 } 1175 }
1156 if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE) && 1176 if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE)
1157 (bempsts & bempenb)) { 1177 && (bempsts & bempenb)) {
1158 irq_pipe_empty(m66592, bempsts, bempenb); 1178 irq_pipe_empty(m66592, bempsts, bempenb);
1159 } 1179 }
1160 1180
@@ -1164,6 +1184,7 @@ static irqreturn_t m66592_irq(int irq, void *_m66592)
1164 1184
1165 m66592_write(m66592, savepipe, M66592_CFIFOSEL); 1185 m66592_write(m66592, savepipe, M66592_CFIFOSEL);
1166 1186
1187 spin_unlock(&m66592->lock);
1167 return IRQ_HANDLED; 1188 return IRQ_HANDLED;
1168} 1189}
1169 1190
@@ -1191,13 +1212,13 @@ static void m66592_timer(unsigned long _m66592)
1191 m66592_usb_disconnect(m66592); 1212 m66592_usb_disconnect(m66592);
1192 } else { 1213 } else {
1193 mod_timer(&m66592->timer, 1214 mod_timer(&m66592->timer,
1194 jiffies + msecs_to_jiffies(50)); 1215 jiffies + msecs_to_jiffies(50));
1195 } 1216 }
1196 } else { 1217 } else {
1197 m66592->scount = M66592_MAX_SAMPLING; 1218 m66592->scount = M66592_MAX_SAMPLING;
1198 m66592->old_vbus = tmp; 1219 m66592->old_vbus = tmp;
1199 mod_timer(&m66592->timer, 1220 mod_timer(&m66592->timer,
1200 jiffies + msecs_to_jiffies(50)); 1221 jiffies + msecs_to_jiffies(50));
1201 } 1222 }
1202 } 1223 }
1203 spin_unlock_irqrestore(&m66592->lock, flags); 1224 spin_unlock_irqrestore(&m66592->lock, flags);
@@ -1335,11 +1356,6 @@ out:
1335 return ret; 1356 return ret;
1336} 1357}
1337 1358
1338static int m66592_fifo_status(struct usb_ep *_ep)
1339{
1340 return -EOPNOTSUPP;
1341}
1342
1343static void m66592_fifo_flush(struct usb_ep *_ep) 1359static void m66592_fifo_flush(struct usb_ep *_ep)
1344{ 1360{
1345 struct m66592_ep *ep; 1361 struct m66592_ep *ep;
@@ -1365,7 +1381,6 @@ static struct usb_ep_ops m66592_ep_ops = {
1365 .dequeue = m66592_dequeue, 1381 .dequeue = m66592_dequeue,
1366 1382
1367 .set_halt = m66592_set_halt, 1383 .set_halt = m66592_set_halt,
1368 .fifo_status = m66592_fifo_status,
1369 .fifo_flush = m66592_fifo_flush, 1384 .fifo_flush = m66592_fifo_flush,
1370}; 1385};
1371 1386
@@ -1377,11 +1392,10 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1377 struct m66592 *m66592 = the_controller; 1392 struct m66592 *m66592 = the_controller;
1378 int retval; 1393 int retval;
1379 1394
1380 if (!driver || 1395 if (!driver
1381 driver->speed != USB_SPEED_HIGH || 1396 || driver->speed != USB_SPEED_HIGH
1382 !driver->bind || 1397 || !driver->bind
1383 !driver->unbind || 1398 || !driver->setup)
1384 !driver->setup)
1385 return -EINVAL; 1399 return -EINVAL;
1386 if (!m66592) 1400 if (!m66592)
1387 return -ENODEV; 1401 return -ENODEV;
@@ -1413,8 +1427,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1413 m66592->old_vbus = m66592_read(m66592, 1427 m66592->old_vbus = m66592_read(m66592,
1414 M66592_INTSTS0) & M66592_VBSTS; 1428 M66592_INTSTS0) & M66592_VBSTS;
1415 m66592->scount = M66592_MAX_SAMPLING; 1429 m66592->scount = M66592_MAX_SAMPLING;
1416 mod_timer(&m66592->timer, 1430 mod_timer(&m66592->timer, jiffies + msecs_to_jiffies(50));
1417 jiffies + msecs_to_jiffies(50));
1418 } 1431 }
1419 1432
1420 return 0; 1433 return 0;
@@ -1432,6 +1445,9 @@ int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1432 struct m66592 *m66592 = the_controller; 1445 struct m66592 *m66592 = the_controller;
1433 unsigned long flags; 1446 unsigned long flags;
1434 1447
1448 if (driver != m66592->driver || !driver->unbind)
1449 return -EINVAL;
1450
1435 spin_lock_irqsave(&m66592->lock, flags); 1451 spin_lock_irqsave(&m66592->lock, flags);
1436 if (m66592->gadget.speed != USB_SPEED_UNKNOWN) 1452 if (m66592->gadget.speed != USB_SPEED_UNKNOWN)
1437 m66592_usb_disconnect(m66592); 1453 m66592_usb_disconnect(m66592);
@@ -1461,46 +1477,35 @@ static struct usb_gadget_ops m66592_gadget_ops = {
1461 .get_frame = m66592_get_frame, 1477 .get_frame = m66592_get_frame,
1462}; 1478};
1463 1479
1464#if defined(CONFIG_PM) 1480static int __exit m66592_remove(struct platform_device *pdev)
1465static int m66592_suspend(struct platform_device *pdev, pm_message_t state)
1466{
1467 pdev->dev.power.power_state = state;
1468 return 0;
1469}
1470
1471static int m66592_resume(struct platform_device *pdev)
1472{
1473 pdev->dev.power.power_state = PMSG_ON;
1474 return 0;
1475}
1476#else /* if defined(CONFIG_PM) */
1477#define m66592_suspend NULL
1478#define m66592_resume NULL
1479#endif
1480
1481static int __init_or_module m66592_remove(struct platform_device *pdev)
1482{ 1481{
1483 struct m66592 *m66592 = dev_get_drvdata(&pdev->dev); 1482 struct m66592 *m66592 = dev_get_drvdata(&pdev->dev);
1484 1483
1485 del_timer_sync(&m66592->timer); 1484 del_timer_sync(&m66592->timer);
1486 iounmap(m66592->reg); 1485 iounmap(m66592->reg);
1487 free_irq(platform_get_irq(pdev, 0), m66592); 1486 free_irq(platform_get_irq(pdev, 0), m66592);
1487 m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
1488 kfree(m66592); 1488 kfree(m66592);
1489 return 0; 1489 return 0;
1490} 1490}
1491 1491
1492static void nop_completion(struct usb_ep *ep, struct usb_request *r)
1493{
1494}
1495
1492#define resource_len(r) (((r)->end - (r)->start) + 1) 1496#define resource_len(r) (((r)->end - (r)->start) + 1)
1497
1493static int __init m66592_probe(struct platform_device *pdev) 1498static int __init m66592_probe(struct platform_device *pdev)
1494{ 1499{
1495 struct resource *res = NULL; 1500 struct resource *res;
1496 int irq = -1; 1501 int irq;
1497 void __iomem *reg = NULL; 1502 void __iomem *reg = NULL;
1498 struct m66592 *m66592 = NULL; 1503 struct m66592 *m66592 = NULL;
1499 int ret = 0; 1504 int ret = 0;
1500 int i; 1505 int i;
1501 1506
1502 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1507 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1503 (char *)udc_name); 1508 (char *)udc_name);
1504 if (!res) { 1509 if (!res) {
1505 ret = -ENODEV; 1510 ret = -ENODEV;
1506 printk(KERN_ERR "platform_get_resource_byname error.\n"); 1511 printk(KERN_ERR "platform_get_resource_byname error.\n");
@@ -1548,7 +1553,7 @@ static int __init m66592_probe(struct platform_device *pdev)
1548 m66592->bi_bufnum = M66592_BASE_BUFNUM; 1553 m66592->bi_bufnum = M66592_BASE_BUFNUM;
1549 1554
1550 ret = request_irq(irq, m66592_irq, IRQF_DISABLED | IRQF_SHARED, 1555 ret = request_irq(irq, m66592_irq, IRQF_DISABLED | IRQF_SHARED,
1551 udc_name, m66592); 1556 udc_name, m66592);
1552 if (ret < 0) { 1557 if (ret < 0) {
1553 printk(KERN_ERR "request_irq error (%d)\n", ret); 1558 printk(KERN_ERR "request_irq error (%d)\n", ret);
1554 goto clean_up; 1559 goto clean_up;
@@ -1563,7 +1568,7 @@ static int __init m66592_probe(struct platform_device *pdev)
1563 if (i != 0) { 1568 if (i != 0) {
1564 INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list); 1569 INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list);
1565 list_add_tail(&m66592->ep[i].ep.ep_list, 1570 list_add_tail(&m66592->ep[i].ep.ep_list,
1566 &m66592->gadget.ep_list); 1571 &m66592->gadget.ep_list);
1567 } 1572 }
1568 ep->m66592 = m66592; 1573 ep->m66592 = m66592;
1569 INIT_LIST_HEAD(&ep->queue); 1574 INIT_LIST_HEAD(&ep->queue);
@@ -1583,20 +1588,18 @@ static int __init m66592_probe(struct platform_device *pdev)
1583 1588
1584 the_controller = m66592; 1589 the_controller = m66592;
1585 1590
1586 /* AV: leaks */
1587 m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL); 1591 m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL);
1588 if (m66592->ep0_req == NULL) 1592 if (m66592->ep0_req == NULL)
1589 goto clean_up; 1593 goto clean_up2;
1590 /* AV: leaks, and do we really need it separately allocated? */ 1594 m66592->ep0_req->complete = nop_completion;
1591 m66592->ep0_buf = kzalloc(2, GFP_KERNEL);
1592 if (m66592->ep0_buf == NULL)
1593 goto clean_up;
1594 1595
1595 init_controller(m66592); 1596 init_controller(m66592);
1596 1597
1597 printk("driver %s, %s\n", udc_name, DRIVER_VERSION); 1598 dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
1598 return 0; 1599 return 0;
1599 1600
1601clean_up2:
1602 free_irq(irq, m66592);
1600clean_up: 1603clean_up:
1601 if (m66592) { 1604 if (m66592) {
1602 if (m66592->ep0_req) 1605 if (m66592->ep0_req)
@@ -1611,10 +1614,7 @@ clean_up:
1611 1614
1612/*-------------------------------------------------------------------------*/ 1615/*-------------------------------------------------------------------------*/
1613static struct platform_driver m66592_driver = { 1616static struct platform_driver m66592_driver = {
1614 .probe = m66592_probe, 1617 .remove = __exit_p(m66592_remove),
1615 .remove = m66592_remove,
1616 .suspend = m66592_suspend,
1617 .resume = m66592_resume,
1618 .driver = { 1618 .driver = {
1619 .name = (char *) udc_name, 1619 .name = (char *) udc_name,
1620 }, 1620 },
@@ -1622,7 +1622,7 @@ static struct platform_driver m66592_driver = {
1622 1622
1623static int __init m66592_udc_init(void) 1623static int __init m66592_udc_init(void)
1624{ 1624{
1625 return platform_driver_register(&m66592_driver); 1625 return platform_driver_probe(&m66592_driver, m66592_probe);
1626} 1626}
1627module_init(m66592_udc_init); 1627module_init(m66592_udc_init);
1628 1628
@@ -1631,4 +1631,3 @@ static void __exit m66592_udc_cleanup(void)
1631 platform_driver_unregister(&m66592_driver); 1631 platform_driver_unregister(&m66592_driver);
1632} 1632}
1633module_exit(m66592_udc_cleanup); 1633module_exit(m66592_udc_cleanup);
1634
diff --git a/drivers/usb/gadget/m66592-udc.h b/drivers/usb/gadget/m66592-udc.h
index 26b54f8b8945..bfa0c645f229 100644
--- a/drivers/usb/gadget/m66592-udc.h
+++ b/drivers/usb/gadget/m66592-udc.h
@@ -24,73 +24,73 @@
24#define __M66592_UDC_H__ 24#define __M66592_UDC_H__
25 25
26#define M66592_SYSCFG 0x00 26#define M66592_SYSCFG 0x00
27#define M66592_XTAL 0xC000 /* b15-14: Crystal selection */ 27#define M66592_XTAL 0xC000 /* b15-14: Crystal selection */
28#define M66592_XTAL48 0x8000 /* 48MHz */ 28#define M66592_XTAL48 0x8000 /* 48MHz */
29#define M66592_XTAL24 0x4000 /* 24MHz */ 29#define M66592_XTAL24 0x4000 /* 24MHz */
30#define M66592_XTAL12 0x0000 /* 12MHz */ 30#define M66592_XTAL12 0x0000 /* 12MHz */
31#define M66592_XCKE 0x2000 /* b13: External clock enable */ 31#define M66592_XCKE 0x2000 /* b13: External clock enable */
32#define M66592_RCKE 0x1000 /* b12: Register clock enable */ 32#define M66592_RCKE 0x1000 /* b12: Register clock enable */
33#define M66592_PLLC 0x0800 /* b11: PLL control */ 33#define M66592_PLLC 0x0800 /* b11: PLL control */
34#define M66592_SCKE 0x0400 /* b10: USB clock enable */ 34#define M66592_SCKE 0x0400 /* b10: USB clock enable */
35#define M66592_ATCKM 0x0100 /* b8: Automatic supply functional enable */ 35#define M66592_ATCKM 0x0100 /* b8: Automatic clock supply */
36#define M66592_HSE 0x0080 /* b7: Hi-speed enable */ 36#define M66592_HSE 0x0080 /* b7: Hi-speed enable */
37#define M66592_DCFM 0x0040 /* b6: Controller function select */ 37#define M66592_DCFM 0x0040 /* b6: Controller function select */
38#define M66592_DMRPD 0x0020 /* b5: D- pull down control */ 38#define M66592_DMRPD 0x0020 /* b5: D- pull down control */
39#define M66592_DPRPU 0x0010 /* b4: D+ pull up control */ 39#define M66592_DPRPU 0x0010 /* b4: D+ pull up control */
40#define M66592_FSRPC 0x0004 /* b2: Full-speed receiver enable */ 40#define M66592_FSRPC 0x0004 /* b2: Full-speed receiver enable */
41#define M66592_PCUT 0x0002 /* b1: Low power sleep enable */ 41#define M66592_PCUT 0x0002 /* b1: Low power sleep enable */
42#define M66592_USBE 0x0001 /* b0: USB module operation enable */ 42#define M66592_USBE 0x0001 /* b0: USB module operation enable */
43 43
44#define M66592_SYSSTS 0x02 44#define M66592_SYSSTS 0x02
45#define M66592_LNST 0x0003 /* b1-0: D+, D- line status */ 45#define M66592_LNST 0x0003 /* b1-0: D+, D- line status */
46#define M66592_SE1 0x0003 /* SE1 */ 46#define M66592_SE1 0x0003 /* SE1 */
47#define M66592_KSTS 0x0002 /* K State */ 47#define M66592_KSTS 0x0002 /* K State */
48#define M66592_JSTS 0x0001 /* J State */ 48#define M66592_JSTS 0x0001 /* J State */
49#define M66592_SE0 0x0000 /* SE0 */ 49#define M66592_SE0 0x0000 /* SE0 */
50 50
51#define M66592_DVSTCTR 0x04 51#define M66592_DVSTCTR 0x04
52#define M66592_WKUP 0x0100 /* b8: Remote wakeup */ 52#define M66592_WKUP 0x0100 /* b8: Remote wakeup */
53#define M66592_RWUPE 0x0080 /* b7: Remote wakeup sense */ 53#define M66592_RWUPE 0x0080 /* b7: Remote wakeup sense */
54#define M66592_USBRST 0x0040 /* b6: USB reset enable */ 54#define M66592_USBRST 0x0040 /* b6: USB reset enable */
55#define M66592_RESUME 0x0020 /* b5: Resume enable */ 55#define M66592_RESUME 0x0020 /* b5: Resume enable */
56#define M66592_UACT 0x0010 /* b4: USB bus enable */ 56#define M66592_UACT 0x0010 /* b4: USB bus enable */
57#define M66592_RHST 0x0003 /* b1-0: Reset handshake status */ 57#define M66592_RHST 0x0003 /* b1-0: Reset handshake status */
58#define M66592_HSMODE 0x0003 /* Hi-Speed mode */ 58#define M66592_HSMODE 0x0003 /* Hi-Speed mode */
59#define M66592_FSMODE 0x0002 /* Full-Speed mode */ 59#define M66592_FSMODE 0x0002 /* Full-Speed mode */
60#define M66592_HSPROC 0x0001 /* HS handshake is processing */ 60#define M66592_HSPROC 0x0001 /* HS handshake is processing */
61 61
62#define M66592_TESTMODE 0x06 62#define M66592_TESTMODE 0x06
63#define M66592_UTST 0x000F /* b4-0: Test select */ 63#define M66592_UTST 0x000F /* b4-0: Test select */
64#define M66592_H_TST_PACKET 0x000C /* HOST TEST Packet */ 64#define M66592_H_TST_PACKET 0x000C /* HOST TEST Packet */
65#define M66592_H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */ 65#define M66592_H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
66#define M66592_H_TST_K 0x000A /* HOST TEST K */ 66#define M66592_H_TST_K 0x000A /* HOST TEST K */
67#define M66592_H_TST_J 0x0009 /* HOST TEST J */ 67#define M66592_H_TST_J 0x0009 /* HOST TEST J */
68#define M66592_H_TST_NORMAL 0x0000 /* HOST Normal Mode */ 68#define M66592_H_TST_NORMAL 0x0000 /* HOST Normal Mode */
69#define M66592_P_TST_PACKET 0x0004 /* PERI TEST Packet */ 69#define M66592_P_TST_PACKET 0x0004 /* PERI TEST Packet */
70#define M66592_P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */ 70#define M66592_P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
71#define M66592_P_TST_K 0x0002 /* PERI TEST K */ 71#define M66592_P_TST_K 0x0002 /* PERI TEST K */
72#define M66592_P_TST_J 0x0001 /* PERI TEST J */ 72#define M66592_P_TST_J 0x0001 /* PERI TEST J */
73#define M66592_P_TST_NORMAL 0x0000 /* PERI Normal Mode */ 73#define M66592_P_TST_NORMAL 0x0000 /* PERI Normal Mode */
74 74
75#define M66592_PINCFG 0x0A 75#define M66592_PINCFG 0x0A
76#define M66592_LDRV 0x8000 /* b15: Drive Current Adjust */ 76#define M66592_LDRV 0x8000 /* b15: Drive Current Adjust */
77#define M66592_BIGEND 0x0100 /* b8: Big endian mode */ 77#define M66592_BIGEND 0x0100 /* b8: Big endian mode */
78 78
79#define M66592_DMA0CFG 0x0C 79#define M66592_DMA0CFG 0x0C
80#define M66592_DMA1CFG 0x0E 80#define M66592_DMA1CFG 0x0E
81#define M66592_DREQA 0x4000 /* b14: Dreq active select */ 81#define M66592_DREQA 0x4000 /* b14: Dreq active select */
82#define M66592_BURST 0x2000 /* b13: Burst mode */ 82#define M66592_BURST 0x2000 /* b13: Burst mode */
83#define M66592_DACKA 0x0400 /* b10: Dack active select */ 83#define M66592_DACKA 0x0400 /* b10: Dack active select */
84#define M66592_DFORM 0x0380 /* b9-7: DMA mode select */ 84#define M66592_DFORM 0x0380 /* b9-7: DMA mode select */
85#define M66592_CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */ 85#define M66592_CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
86#define M66592_CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */ 86#define M66592_CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
87#define M66592_CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */ 87#define M66592_CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
88#define M66592_SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */ 88#define M66592_SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
89#define M66592_SPLIT_DACK_DSTB 0x0300 /* DACK + DSTB0 mode (SPLIT bus) */ 89#define M66592_SPLIT_DACK_DSTB 0x0300 /* DACK + DSTB0 mode (SPLIT bus) */
90#define M66592_DENDA 0x0040 /* b6: Dend active select */ 90#define M66592_DENDA 0x0040 /* b6: Dend active select */
91#define M66592_PKTM 0x0020 /* b5: Packet mode */ 91#define M66592_PKTM 0x0020 /* b5: Packet mode */
92#define M66592_DENDE 0x0010 /* b4: Dend enable */ 92#define M66592_DENDE 0x0010 /* b4: Dend enable */
93#define M66592_OBUS 0x0004 /* b2: OUTbus mode */ 93#define M66592_OBUS 0x0004 /* b2: OUTbus mode */
94 94
95#define M66592_CFIFO 0x10 95#define M66592_CFIFO 0x10
96#define M66592_D0FIFO 0x14 96#define M66592_D0FIFO 0x14
@@ -99,300 +99,300 @@
99#define M66592_CFIFOSEL 0x1E 99#define M66592_CFIFOSEL 0x1E
100#define M66592_D0FIFOSEL 0x24 100#define M66592_D0FIFOSEL 0x24
101#define M66592_D1FIFOSEL 0x2A 101#define M66592_D1FIFOSEL 0x2A
102#define M66592_RCNT 0x8000 /* b15: Read count mode */ 102#define M66592_RCNT 0x8000 /* b15: Read count mode */
103#define M66592_REW 0x4000 /* b14: Buffer rewind */ 103#define M66592_REW 0x4000 /* b14: Buffer rewind */
104#define M66592_DCLRM 0x2000 /* b13: DMA buffer clear mode */ 104#define M66592_DCLRM 0x2000 /* b13: DMA buffer clear mode */
105#define M66592_DREQE 0x1000 /* b12: DREQ output enable */ 105#define M66592_DREQE 0x1000 /* b12: DREQ output enable */
106#define M66592_MBW 0x0400 /* b10: Maximum bit width for FIFO access */ 106#define M66592_MBW 0x0400 /* b10: Maximum bit width for FIFO */
107#define M66592_MBW_8 0x0000 /* 8bit */ 107#define M66592_MBW_8 0x0000 /* 8bit */
108#define M66592_MBW_16 0x0400 /* 16bit */ 108#define M66592_MBW_16 0x0400 /* 16bit */
109#define M66592_TRENB 0x0200 /* b9: Transaction counter enable */ 109#define M66592_TRENB 0x0200 /* b9: Transaction counter enable */
110#define M66592_TRCLR 0x0100 /* b8: Transaction counter clear */ 110#define M66592_TRCLR 0x0100 /* b8: Transaction counter clear */
111#define M66592_DEZPM 0x0080 /* b7: Zero-length packet additional mode */ 111#define M66592_DEZPM 0x0080 /* b7: Zero-length packet mode */
112#define M66592_ISEL 0x0020 /* b5: DCP FIFO port direction select */ 112#define M66592_ISEL 0x0020 /* b5: DCP FIFO port direction select */
113#define M66592_CURPIPE 0x0007 /* b2-0: PIPE select */ 113#define M66592_CURPIPE 0x0007 /* b2-0: PIPE select */
114 114
115#define M66592_CFIFOCTR 0x20 115#define M66592_CFIFOCTR 0x20
116#define M66592_D0FIFOCTR 0x26 116#define M66592_D0FIFOCTR 0x26
117#define M66592_D1FIFOCTR 0x2c 117#define M66592_D1FIFOCTR 0x2c
118#define M66592_BVAL 0x8000 /* b15: Buffer valid flag */ 118#define M66592_BVAL 0x8000 /* b15: Buffer valid flag */
119#define M66592_BCLR 0x4000 /* b14: Buffer clear */ 119#define M66592_BCLR 0x4000 /* b14: Buffer clear */
120#define M66592_FRDY 0x2000 /* b13: FIFO ready */ 120#define M66592_FRDY 0x2000 /* b13: FIFO ready */
121#define M66592_DTLN 0x0FFF /* b11-0: FIFO received data length */ 121#define M66592_DTLN 0x0FFF /* b11-0: FIFO received data length */
122 122
123#define M66592_CFIFOSIE 0x22 123#define M66592_CFIFOSIE 0x22
124#define M66592_TGL 0x8000 /* b15: Buffer toggle */ 124#define M66592_TGL 0x8000 /* b15: Buffer toggle */
125#define M66592_SCLR 0x4000 /* b14: Buffer clear */ 125#define M66592_SCLR 0x4000 /* b14: Buffer clear */
126#define M66592_SBUSY 0x2000 /* b13: SIE_FIFO busy */ 126#define M66592_SBUSY 0x2000 /* b13: SIE_FIFO busy */
127 127
128#define M66592_D0FIFOTRN 0x28 128#define M66592_D0FIFOTRN 0x28
129#define M66592_D1FIFOTRN 0x2E 129#define M66592_D1FIFOTRN 0x2E
130#define M66592_TRNCNT 0xFFFF /* b15-0: Transaction counter */ 130#define M66592_TRNCNT 0xFFFF /* b15-0: Transaction counter */
131 131
132#define M66592_INTENB0 0x30 132#define M66592_INTENB0 0x30
133#define M66592_VBSE 0x8000 /* b15: VBUS interrupt */ 133#define M66592_VBSE 0x8000 /* b15: VBUS interrupt */
134#define M66592_RSME 0x4000 /* b14: Resume interrupt */ 134#define M66592_RSME 0x4000 /* b14: Resume interrupt */
135#define M66592_SOFE 0x2000 /* b13: Frame update interrupt */ 135#define M66592_SOFE 0x2000 /* b13: Frame update interrupt */
136#define M66592_DVSE 0x1000 /* b12: Device state transition interrupt */ 136#define M66592_DVSE 0x1000 /* b12: Device state transition interrupt */
137#define M66592_CTRE 0x0800 /* b11: Control transfer stage transition interrupt */ 137#define M66592_CTRE 0x0800 /* b11: Control transfer stage transition irq */
138#define M66592_BEMPE 0x0400 /* b10: Buffer empty interrupt */ 138#define M66592_BEMPE 0x0400 /* b10: Buffer empty interrupt */
139#define M66592_NRDYE 0x0200 /* b9: Buffer not ready interrupt */ 139#define M66592_NRDYE 0x0200 /* b9: Buffer not ready interrupt */
140#define M66592_BRDYE 0x0100 /* b8: Buffer ready interrupt */ 140#define M66592_BRDYE 0x0100 /* b8: Buffer ready interrupt */
141#define M66592_URST 0x0080 /* b7: USB reset detected interrupt */ 141#define M66592_URST 0x0080 /* b7: USB reset detected interrupt */
142#define M66592_SADR 0x0040 /* b6: Set address executed interrupt */ 142#define M66592_SADR 0x0040 /* b6: Set address executed interrupt */
143#define M66592_SCFG 0x0020 /* b5: Set configuration executed interrupt */ 143#define M66592_SCFG 0x0020 /* b5: Set configuration executed interrupt */
144#define M66592_SUSP 0x0010 /* b4: Suspend detected interrupt */ 144#define M66592_SUSP 0x0010 /* b4: Suspend detected interrupt */
145#define M66592_WDST 0x0008 /* b3: Control write data stage completed interrupt */ 145#define M66592_WDST 0x0008 /* b3: Control write data stage completed irq */
146#define M66592_RDST 0x0004 /* b2: Control read data stage completed interrupt */ 146#define M66592_RDST 0x0004 /* b2: Control read data stage completed irq */
147#define M66592_CMPL 0x0002 /* b1: Control transfer complete interrupt */ 147#define M66592_CMPL 0x0002 /* b1: Control transfer complete interrupt */
148#define M66592_SERR 0x0001 /* b0: Sequence error interrupt */ 148#define M66592_SERR 0x0001 /* b0: Sequence error interrupt */
149 149
150#define M66592_INTENB1 0x32 150#define M66592_INTENB1 0x32
151#define M66592_BCHGE 0x4000 /* b14: USB us chenge interrupt */ 151#define M66592_BCHGE 0x4000 /* b14: USB us chenge interrupt */
152#define M66592_DTCHE 0x1000 /* b12: Detach sense interrupt */ 152#define M66592_DTCHE 0x1000 /* b12: Detach sense interrupt */
153#define M66592_SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */ 153#define M66592_SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
154#define M66592_SACKE 0x0010 /* b4: SETUP ACK interrupt */ 154#define M66592_SACKE 0x0010 /* b4: SETUP ACK interrupt */
155#define M66592_BRDYM 0x0004 /* b2: BRDY clear timing */ 155#define M66592_BRDYM 0x0004 /* b2: BRDY clear timing */
156#define M66592_INTL 0x0002 /* b1: Interrupt sense select */ 156#define M66592_INTL 0x0002 /* b1: Interrupt sense select */
157#define M66592_PCSE 0x0001 /* b0: PCUT enable by CS assert */ 157#define M66592_PCSE 0x0001 /* b0: PCUT enable by CS assert */
158 158
159#define M66592_BRDYENB 0x36 159#define M66592_BRDYENB 0x36
160#define M66592_BRDYSTS 0x46 160#define M66592_BRDYSTS 0x46
161#define M66592_BRDY7 0x0080 /* b7: PIPE7 */ 161#define M66592_BRDY7 0x0080 /* b7: PIPE7 */
162#define M66592_BRDY6 0x0040 /* b6: PIPE6 */ 162#define M66592_BRDY6 0x0040 /* b6: PIPE6 */
163#define M66592_BRDY5 0x0020 /* b5: PIPE5 */ 163#define M66592_BRDY5 0x0020 /* b5: PIPE5 */
164#define M66592_BRDY4 0x0010 /* b4: PIPE4 */ 164#define M66592_BRDY4 0x0010 /* b4: PIPE4 */
165#define M66592_BRDY3 0x0008 /* b3: PIPE3 */ 165#define M66592_BRDY3 0x0008 /* b3: PIPE3 */
166#define M66592_BRDY2 0x0004 /* b2: PIPE2 */ 166#define M66592_BRDY2 0x0004 /* b2: PIPE2 */
167#define M66592_BRDY1 0x0002 /* b1: PIPE1 */ 167#define M66592_BRDY1 0x0002 /* b1: PIPE1 */
168#define M66592_BRDY0 0x0001 /* b1: PIPE0 */ 168#define M66592_BRDY0 0x0001 /* b1: PIPE0 */
169 169
170#define M66592_NRDYENB 0x38 170#define M66592_NRDYENB 0x38
171#define M66592_NRDYSTS 0x48 171#define M66592_NRDYSTS 0x48
172#define M66592_NRDY7 0x0080 /* b7: PIPE7 */ 172#define M66592_NRDY7 0x0080 /* b7: PIPE7 */
173#define M66592_NRDY6 0x0040 /* b6: PIPE6 */ 173#define M66592_NRDY6 0x0040 /* b6: PIPE6 */
174#define M66592_NRDY5 0x0020 /* b5: PIPE5 */ 174#define M66592_NRDY5 0x0020 /* b5: PIPE5 */
175#define M66592_NRDY4 0x0010 /* b4: PIPE4 */ 175#define M66592_NRDY4 0x0010 /* b4: PIPE4 */
176#define M66592_NRDY3 0x0008 /* b3: PIPE3 */ 176#define M66592_NRDY3 0x0008 /* b3: PIPE3 */
177#define M66592_NRDY2 0x0004 /* b2: PIPE2 */ 177#define M66592_NRDY2 0x0004 /* b2: PIPE2 */
178#define M66592_NRDY1 0x0002 /* b1: PIPE1 */ 178#define M66592_NRDY1 0x0002 /* b1: PIPE1 */
179#define M66592_NRDY0 0x0001 /* b1: PIPE0 */ 179#define M66592_NRDY0 0x0001 /* b1: PIPE0 */
180 180
181#define M66592_BEMPENB 0x3A 181#define M66592_BEMPENB 0x3A
182#define M66592_BEMPSTS 0x4A 182#define M66592_BEMPSTS 0x4A
183#define M66592_BEMP7 0x0080 /* b7: PIPE7 */ 183#define M66592_BEMP7 0x0080 /* b7: PIPE7 */
184#define M66592_BEMP6 0x0040 /* b6: PIPE6 */ 184#define M66592_BEMP6 0x0040 /* b6: PIPE6 */
185#define M66592_BEMP5 0x0020 /* b5: PIPE5 */ 185#define M66592_BEMP5 0x0020 /* b5: PIPE5 */
186#define M66592_BEMP4 0x0010 /* b4: PIPE4 */ 186#define M66592_BEMP4 0x0010 /* b4: PIPE4 */
187#define M66592_BEMP3 0x0008 /* b3: PIPE3 */ 187#define M66592_BEMP3 0x0008 /* b3: PIPE3 */
188#define M66592_BEMP2 0x0004 /* b2: PIPE2 */ 188#define M66592_BEMP2 0x0004 /* b2: PIPE2 */
189#define M66592_BEMP1 0x0002 /* b1: PIPE1 */ 189#define M66592_BEMP1 0x0002 /* b1: PIPE1 */
190#define M66592_BEMP0 0x0001 /* b0: PIPE0 */ 190#define M66592_BEMP0 0x0001 /* b0: PIPE0 */
191 191
192#define M66592_SOFCFG 0x3C 192#define M66592_SOFCFG 0x3C
193#define M66592_SOFM 0x000C /* b3-2: SOF palse mode */ 193#define M66592_SOFM 0x000C /* b3-2: SOF palse mode */
194#define M66592_SOF_125US 0x0008 /* SOF OUT 125us uFrame Signal */ 194#define M66592_SOF_125US 0x0008 /* SOF OUT 125us uFrame Signal */
195#define M66592_SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */ 195#define M66592_SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
196#define M66592_SOF_DISABLE 0x0000 /* SOF OUT Disable */ 196#define M66592_SOF_DISABLE 0x0000 /* SOF OUT Disable */
197 197
198#define M66592_INTSTS0 0x40 198#define M66592_INTSTS0 0x40
199#define M66592_VBINT 0x8000 /* b15: VBUS interrupt */ 199#define M66592_VBINT 0x8000 /* b15: VBUS interrupt */
200#define M66592_RESM 0x4000 /* b14: Resume interrupt */ 200#define M66592_RESM 0x4000 /* b14: Resume interrupt */
201#define M66592_SOFR 0x2000 /* b13: SOF frame update interrupt */ 201#define M66592_SOFR 0x2000 /* b13: SOF frame update interrupt */
202#define M66592_DVST 0x1000 /* b12: Device state transition interrupt */ 202#define M66592_DVST 0x1000 /* b12: Device state transition */
203#define M66592_CTRT 0x0800 /* b11: Control transfer stage transition interrupt */ 203#define M66592_CTRT 0x0800 /* b11: Control stage transition */
204#define M66592_BEMP 0x0400 /* b10: Buffer empty interrupt */ 204#define M66592_BEMP 0x0400 /* b10: Buffer empty interrupt */
205#define M66592_NRDY 0x0200 /* b9: Buffer not ready interrupt */ 205#define M66592_NRDY 0x0200 /* b9: Buffer not ready interrupt */
206#define M66592_BRDY 0x0100 /* b8: Buffer ready interrupt */ 206#define M66592_BRDY 0x0100 /* b8: Buffer ready interrupt */
207#define M66592_VBSTS 0x0080 /* b7: VBUS input port */ 207#define M66592_VBSTS 0x0080 /* b7: VBUS input port */
208#define M66592_DVSQ 0x0070 /* b6-4: Device state */ 208#define M66592_DVSQ 0x0070 /* b6-4: Device state */
209#define M66592_DS_SPD_CNFG 0x0070 /* Suspend Configured */ 209#define M66592_DS_SPD_CNFG 0x0070 /* Suspend Configured */
210#define M66592_DS_SPD_ADDR 0x0060 /* Suspend Address */ 210#define M66592_DS_SPD_ADDR 0x0060 /* Suspend Address */
211#define M66592_DS_SPD_DFLT 0x0050 /* Suspend Default */ 211#define M66592_DS_SPD_DFLT 0x0050 /* Suspend Default */
212#define M66592_DS_SPD_POWR 0x0040 /* Suspend Powered */ 212#define M66592_DS_SPD_POWR 0x0040 /* Suspend Powered */
213#define M66592_DS_SUSP 0x0040 /* Suspend */ 213#define M66592_DS_SUSP 0x0040 /* Suspend */
214#define M66592_DS_CNFG 0x0030 /* Configured */ 214#define M66592_DS_CNFG 0x0030 /* Configured */
215#define M66592_DS_ADDS 0x0020 /* Address */ 215#define M66592_DS_ADDS 0x0020 /* Address */
216#define M66592_DS_DFLT 0x0010 /* Default */ 216#define M66592_DS_DFLT 0x0010 /* Default */
217#define M66592_DS_POWR 0x0000 /* Powered */ 217#define M66592_DS_POWR 0x0000 /* Powered */
218#define M66592_DVSQS 0x0030 /* b5-4: Device state */ 218#define M66592_DVSQS 0x0030 /* b5-4: Device state */
219#define M66592_VALID 0x0008 /* b3: Setup packet detected flag */ 219#define M66592_VALID 0x0008 /* b3: Setup packet detected flag */
220#define M66592_CTSQ 0x0007 /* b2-0: Control transfer stage */ 220#define M66592_CTSQ 0x0007 /* b2-0: Control transfer stage */
221#define M66592_CS_SQER 0x0006 /* Sequence error */ 221#define M66592_CS_SQER 0x0006 /* Sequence error */
222#define M66592_CS_WRND 0x0005 /* Control write nodata status stage */ 222#define M66592_CS_WRND 0x0005 /* Control write nodata status */
223#define M66592_CS_WRSS 0x0004 /* Control write status stage */ 223#define M66592_CS_WRSS 0x0004 /* Control write status stage */
224#define M66592_CS_WRDS 0x0003 /* Control write data stage */ 224#define M66592_CS_WRDS 0x0003 /* Control write data stage */
225#define M66592_CS_RDSS 0x0002 /* Control read status stage */ 225#define M66592_CS_RDSS 0x0002 /* Control read status stage */
226#define M66592_CS_RDDS 0x0001 /* Control read data stage */ 226#define M66592_CS_RDDS 0x0001 /* Control read data stage */
227#define M66592_CS_IDST 0x0000 /* Idle or setup stage */ 227#define M66592_CS_IDST 0x0000 /* Idle or setup stage */
228 228
229#define M66592_INTSTS1 0x42 229#define M66592_INTSTS1 0x42
230#define M66592_BCHG 0x4000 /* b14: USB bus chenge interrupt */ 230#define M66592_BCHG 0x4000 /* b14: USB bus chenge interrupt */
231#define M66592_DTCH 0x1000 /* b12: Detach sense interrupt */ 231#define M66592_DTCH 0x1000 /* b12: Detach sense interrupt */
232#define M66592_SIGN 0x0020 /* b5: SETUP IGNORE interrupt */ 232#define M66592_SIGN 0x0020 /* b5: SETUP IGNORE interrupt */
233#define M66592_SACK 0x0010 /* b4: SETUP ACK interrupt */ 233#define M66592_SACK 0x0010 /* b4: SETUP ACK interrupt */
234 234
235#define M66592_FRMNUM 0x4C 235#define M66592_FRMNUM 0x4C
236#define M66592_OVRN 0x8000 /* b15: Overrun error */ 236#define M66592_OVRN 0x8000 /* b15: Overrun error */
237#define M66592_CRCE 0x4000 /* b14: Received data error */ 237#define M66592_CRCE 0x4000 /* b14: Received data error */
238#define M66592_SOFRM 0x0800 /* b11: SOF output mode */ 238#define M66592_SOFRM 0x0800 /* b11: SOF output mode */
239#define M66592_FRNM 0x07FF /* b10-0: Frame number */ 239#define M66592_FRNM 0x07FF /* b10-0: Frame number */
240 240
241#define M66592_UFRMNUM 0x4E 241#define M66592_UFRMNUM 0x4E
242#define M66592_UFRNM 0x0007 /* b2-0: Micro frame number */ 242#define M66592_UFRNM 0x0007 /* b2-0: Micro frame number */
243 243
244#define M66592_RECOVER 0x50 244#define M66592_RECOVER 0x50
245#define M66592_STSRECOV 0x0700 /* Status recovery */ 245#define M66592_STSRECOV 0x0700 /* Status recovery */
246#define M66592_STSR_HI 0x0400 /* FULL(0) or HI(1) Speed */ 246#define M66592_STSR_HI 0x0400 /* FULL(0) or HI(1) Speed */
247#define M66592_STSR_DEFAULT 0x0100 /* Default state */ 247#define M66592_STSR_DEFAULT 0x0100 /* Default state */
248#define M66592_STSR_ADDRESS 0x0200 /* Address state */ 248#define M66592_STSR_ADDRESS 0x0200 /* Address state */
249#define M66592_STSR_CONFIG 0x0300 /* Configured state */ 249#define M66592_STSR_CONFIG 0x0300 /* Configured state */
250#define M66592_USBADDR 0x007F /* b6-0: USB address */ 250#define M66592_USBADDR 0x007F /* b6-0: USB address */
251 251
252#define M66592_USBREQ 0x54 252#define M66592_USBREQ 0x54
253#define M66592_bRequest 0xFF00 /* b15-8: bRequest */ 253#define M66592_bRequest 0xFF00 /* b15-8: bRequest */
254#define M66592_GET_STATUS 0x0000 254#define M66592_GET_STATUS 0x0000
255#define M66592_CLEAR_FEATURE 0x0100 255#define M66592_CLEAR_FEATURE 0x0100
256#define M66592_ReqRESERVED 0x0200 256#define M66592_ReqRESERVED 0x0200
257#define M66592_SET_FEATURE 0x0300 257#define M66592_SET_FEATURE 0x0300
258#define M66592_ReqRESERVED1 0x0400 258#define M66592_ReqRESERVED1 0x0400
259#define M66592_SET_ADDRESS 0x0500 259#define M66592_SET_ADDRESS 0x0500
260#define M66592_GET_DESCRIPTOR 0x0600 260#define M66592_GET_DESCRIPTOR 0x0600
261#define M66592_SET_DESCRIPTOR 0x0700 261#define M66592_SET_DESCRIPTOR 0x0700
262#define M66592_GET_CONFIGURATION 0x0800 262#define M66592_GET_CONFIGURATION 0x0800
263#define M66592_SET_CONFIGURATION 0x0900 263#define M66592_SET_CONFIGURATION 0x0900
264#define M66592_GET_INTERFACE 0x0A00 264#define M66592_GET_INTERFACE 0x0A00
265#define M66592_SET_INTERFACE 0x0B00 265#define M66592_SET_INTERFACE 0x0B00
266#define M66592_SYNCH_FRAME 0x0C00 266#define M66592_SYNCH_FRAME 0x0C00
267#define M66592_bmRequestType 0x00FF /* b7-0: bmRequestType */ 267#define M66592_bmRequestType 0x00FF /* b7-0: bmRequestType */
268#define M66592_bmRequestTypeDir 0x0080 /* b7 : Data transfer direction */ 268#define M66592_bmRequestTypeDir 0x0080 /* b7 : Data direction */
269#define M66592_HOST_TO_DEVICE 0x0000 269#define M66592_HOST_TO_DEVICE 0x0000
270#define M66592_DEVICE_TO_HOST 0x0080 270#define M66592_DEVICE_TO_HOST 0x0080
271#define M66592_bmRequestTypeType 0x0060 /* b6-5: Type */ 271#define M66592_bmRequestTypeType 0x0060 /* b6-5: Type */
272#define M66592_STANDARD 0x0000 272#define M66592_STANDARD 0x0000
273#define M66592_CLASS 0x0020 273#define M66592_CLASS 0x0020
274#define M66592_VENDOR 0x0040 274#define M66592_VENDOR 0x0040
275#define M66592_bmRequestTypeRecip 0x001F /* b4-0: Recipient */ 275#define M66592_bmRequestTypeRecip 0x001F /* b4-0: Recipient */
276#define M66592_DEVICE 0x0000 276#define M66592_DEVICE 0x0000
277#define M66592_INTERFACE 0x0001 277#define M66592_INTERFACE 0x0001
278#define M66592_ENDPOINT 0x0002 278#define M66592_ENDPOINT 0x0002
279 279
280#define M66592_USBVAL 0x56 280#define M66592_USBVAL 0x56
281#define M66592_wValue 0xFFFF /* b15-0: wValue */ 281#define M66592_wValue 0xFFFF /* b15-0: wValue */
282/* Standard Feature Selector */ 282/* Standard Feature Selector */
283#define M66592_ENDPOINT_HALT 0x0000 283#define M66592_ENDPOINT_HALT 0x0000
284#define M66592_DEVICE_REMOTE_WAKEUP 0x0001 284#define M66592_DEVICE_REMOTE_WAKEUP 0x0001
285#define M66592_TEST_MODE 0x0002 285#define M66592_TEST_MODE 0x0002
286/* Descriptor Types */ 286/* Descriptor Types */
287#define M66592_DT_TYPE 0xFF00 287#define M66592_DT_TYPE 0xFF00
288#define M66592_GET_DT_TYPE(v) (((v) & DT_TYPE) >> 8) 288#define M66592_GET_DT_TYPE(v) (((v) & DT_TYPE) >> 8)
289#define M66592_DT_DEVICE 0x01 289#define M66592_DT_DEVICE 0x01
290#define M66592_DT_CONFIGURATION 0x02 290#define M66592_DT_CONFIGURATION 0x02
291#define M66592_DT_STRING 0x03 291#define M66592_DT_STRING 0x03
292#define M66592_DT_INTERFACE 0x04 292#define M66592_DT_INTERFACE 0x04
293#define M66592_DT_ENDPOINT 0x05 293#define M66592_DT_ENDPOINT 0x05
294#define M66592_DT_DEVICE_QUALIFIER 0x06 294#define M66592_DT_DEVICE_QUALIFIER 0x06
295#define M66592_DT_OTHER_SPEED_CONFIGURATION 0x07 295#define M66592_DT_OTHER_SPEED_CONFIGURATION 0x07
296#define M66592_DT_INTERFACE_POWER 0x08 296#define M66592_DT_INTERFACE_POWER 0x08
297#define M66592_DT_INDEX 0x00FF 297#define M66592_DT_INDEX 0x00FF
298#define M66592_CONF_NUM 0x00FF 298#define M66592_CONF_NUM 0x00FF
299#define M66592_ALT_SET 0x00FF 299#define M66592_ALT_SET 0x00FF
300 300
301#define M66592_USBINDEX 0x58 301#define M66592_USBINDEX 0x58
302#define M66592_wIndex 0xFFFF /* b15-0: wIndex */ 302#define M66592_wIndex 0xFFFF /* b15-0: wIndex */
303#define M66592_TEST_SELECT 0xFF00 /* b15-b8: Test Mode Selectors */ 303#define M66592_TEST_SELECT 0xFF00 /* b15-b8: Test Mode */
304#define M66592_TEST_J 0x0100 /* Test_J */ 304#define M66592_TEST_J 0x0100 /* Test_J */
305#define M66592_TEST_K 0x0200 /* Test_K */ 305#define M66592_TEST_K 0x0200 /* Test_K */
306#define M66592_TEST_SE0_NAK 0x0300 /* Test_SE0_NAK */ 306#define M66592_TEST_SE0_NAK 0x0300 /* Test_SE0_NAK */
307#define M66592_TEST_PACKET 0x0400 /* Test_Packet */ 307#define M66592_TEST_PACKET 0x0400 /* Test_Packet */
308#define M66592_TEST_FORCE_ENABLE 0x0500 /* Test_Force_Enable */ 308#define M66592_TEST_FORCE_ENABLE 0x0500 /* Test_Force_Enable */
309#define M66592_TEST_STSelectors 0x0600 /* Standard test selectors */ 309#define M66592_TEST_STSelectors 0x0600 /* Standard test selectors */
310#define M66592_TEST_Reserved 0x4000 /* Reserved */ 310#define M66592_TEST_Reserved 0x4000 /* Reserved */
311#define M66592_TEST_VSTModes 0xC000 /* Vendor-specific test modes */ 311#define M66592_TEST_VSTModes 0xC000 /* Vendor-specific tests */
312#define M66592_EP_DIR 0x0080 /* b7: Endpoint Direction */ 312#define M66592_EP_DIR 0x0080 /* b7: Endpoint Direction */
313#define M66592_EP_DIR_IN 0x0080 313#define M66592_EP_DIR_IN 0x0080
314#define M66592_EP_DIR_OUT 0x0000 314#define M66592_EP_DIR_OUT 0x0000
315 315
316#define M66592_USBLENG 0x5A 316#define M66592_USBLENG 0x5A
317#define M66592_wLength 0xFFFF /* b15-0: wLength */ 317#define M66592_wLength 0xFFFF /* b15-0: wLength */
318 318
319#define M66592_DCPCFG 0x5C 319#define M66592_DCPCFG 0x5C
320#define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode select */ 320#define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode */
321#define M66592_DIR 0x0010 /* b4: Control transfer DIR select */ 321#define M66592_DIR 0x0010 /* b4: Control transfer DIR select */
322 322
323#define M66592_DCPMAXP 0x5E 323#define M66592_DCPMAXP 0x5E
324#define M66592_DEVSEL 0xC000 /* b15-14: Device address select */ 324#define M66592_DEVSEL 0xC000 /* b15-14: Device address select */
325#define M66592_DEVICE_0 0x0000 /* Device address 0 */ 325#define M66592_DEVICE_0 0x0000 /* Device address 0 */
326#define M66592_DEVICE_1 0x4000 /* Device address 1 */ 326#define M66592_DEVICE_1 0x4000 /* Device address 1 */
327#define M66592_DEVICE_2 0x8000 /* Device address 2 */ 327#define M66592_DEVICE_2 0x8000 /* Device address 2 */
328#define M66592_DEVICE_3 0xC000 /* Device address 3 */ 328#define M66592_DEVICE_3 0xC000 /* Device address 3 */
329#define M66592_MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */ 329#define M66592_MAXP 0x007F /* b6-0: Maxpacket size of ep0 */
330 330
331#define M66592_DCPCTR 0x60 331#define M66592_DCPCTR 0x60
332#define M66592_BSTS 0x8000 /* b15: Buffer status */ 332#define M66592_BSTS 0x8000 /* b15: Buffer status */
333#define M66592_SUREQ 0x4000 /* b14: Send USB request */ 333#define M66592_SUREQ 0x4000 /* b14: Send USB request */
334#define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */ 334#define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */
335#define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */ 335#define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */
336#define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */ 336#define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */
337#define M66592_CCPL 0x0004 /* b2: Enable control transfer complete */ 337#define M66592_CCPL 0x0004 /* b2: control transfer complete */
338#define M66592_PID 0x0003 /* b1-0: Response PID */ 338#define M66592_PID 0x0003 /* b1-0: Response PID */
339#define M66592_PID_STALL 0x0002 /* STALL */ 339#define M66592_PID_STALL 0x0002 /* STALL */
340#define M66592_PID_BUF 0x0001 /* BUF */ 340#define M66592_PID_BUF 0x0001 /* BUF */
341#define M66592_PID_NAK 0x0000 /* NAK */ 341#define M66592_PID_NAK 0x0000 /* NAK */
342 342
343#define M66592_PIPESEL 0x64 343#define M66592_PIPESEL 0x64
344#define M66592_PIPENM 0x0007 /* b2-0: Pipe select */ 344#define M66592_PIPENM 0x0007 /* b2-0: Pipe select */
345#define M66592_PIPE0 0x0000 /* PIPE 0 */ 345#define M66592_PIPE0 0x0000 /* PIPE 0 */
346#define M66592_PIPE1 0x0001 /* PIPE 1 */ 346#define M66592_PIPE1 0x0001 /* PIPE 1 */
347#define M66592_PIPE2 0x0002 /* PIPE 2 */ 347#define M66592_PIPE2 0x0002 /* PIPE 2 */
348#define M66592_PIPE3 0x0003 /* PIPE 3 */ 348#define M66592_PIPE3 0x0003 /* PIPE 3 */
349#define M66592_PIPE4 0x0004 /* PIPE 4 */ 349#define M66592_PIPE4 0x0004 /* PIPE 4 */
350#define M66592_PIPE5 0x0005 /* PIPE 5 */ 350#define M66592_PIPE5 0x0005 /* PIPE 5 */
351#define M66592_PIPE6 0x0006 /* PIPE 6 */ 351#define M66592_PIPE6 0x0006 /* PIPE 6 */
352#define M66592_PIPE7 0x0007 /* PIPE 7 */ 352#define M66592_PIPE7 0x0007 /* PIPE 7 */
353 353
354#define M66592_PIPECFG 0x66 354#define M66592_PIPECFG 0x66
355#define M66592_TYP 0xC000 /* b15-14: Transfer type */ 355#define M66592_TYP 0xC000 /* b15-14: Transfer type */
356#define M66592_ISO 0xC000 /* Isochronous */ 356#define M66592_ISO 0xC000 /* Isochronous */
357#define M66592_INT 0x8000 /* Interrupt */ 357#define M66592_INT 0x8000 /* Interrupt */
358#define M66592_BULK 0x4000 /* Bulk */ 358#define M66592_BULK 0x4000 /* Bulk */
359#define M66592_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */ 359#define M66592_BFRE 0x0400 /* b10: Buffer ready interrupt mode */
360#define M66592_DBLB 0x0200 /* b9: Double buffer mode select */ 360#define M66592_DBLB 0x0200 /* b9: Double buffer mode select */
361#define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode select */ 361#define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode */
362#define M66592_SHTNAK 0x0080 /* b7: Transfer end NAK */ 362#define M66592_SHTNAK 0x0080 /* b7: Transfer end NAK */
363#define M66592_DIR 0x0010 /* b4: Transfer direction select */ 363#define M66592_DIR 0x0010 /* b4: Transfer direction select */
364#define M66592_DIR_H_OUT 0x0010 /* HOST OUT */ 364#define M66592_DIR_H_OUT 0x0010 /* HOST OUT */
365#define M66592_DIR_P_IN 0x0010 /* PERI IN */ 365#define M66592_DIR_P_IN 0x0010 /* PERI IN */
366#define M66592_DIR_H_IN 0x0000 /* HOST IN */ 366#define M66592_DIR_H_IN 0x0000 /* HOST IN */
367#define M66592_DIR_P_OUT 0x0000 /* PERI OUT */ 367#define M66592_DIR_P_OUT 0x0000 /* PERI OUT */
368#define M66592_EPNUM 0x000F /* b3-0: Eendpoint number select */ 368#define M66592_EPNUM 0x000F /* b3-0: Eendpoint number select */
369#define M66592_EP1 0x0001 369#define M66592_EP1 0x0001
370#define M66592_EP2 0x0002 370#define M66592_EP2 0x0002
371#define M66592_EP3 0x0003 371#define M66592_EP3 0x0003
372#define M66592_EP4 0x0004 372#define M66592_EP4 0x0004
373#define M66592_EP5 0x0005 373#define M66592_EP5 0x0005
374#define M66592_EP6 0x0006 374#define M66592_EP6 0x0006
375#define M66592_EP7 0x0007 375#define M66592_EP7 0x0007
376#define M66592_EP8 0x0008 376#define M66592_EP8 0x0008
377#define M66592_EP9 0x0009 377#define M66592_EP9 0x0009
378#define M66592_EP10 0x000A 378#define M66592_EP10 0x000A
379#define M66592_EP11 0x000B 379#define M66592_EP11 0x000B
380#define M66592_EP12 0x000C 380#define M66592_EP12 0x000C
381#define M66592_EP13 0x000D 381#define M66592_EP13 0x000D
382#define M66592_EP14 0x000E 382#define M66592_EP14 0x000E
383#define M66592_EP15 0x000F 383#define M66592_EP15 0x000F
384 384
385#define M66592_PIPEBUF 0x68 385#define M66592_PIPEBUF 0x68
386#define M66592_BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */ 386#define M66592_BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
387#define M66592_BUF_SIZE(x) ((((x) / 64) - 1) << 10) 387#define M66592_BUF_SIZE(x) ((((x) / 64) - 1) << 10)
388#define M66592_BUFNMB 0x00FF /* b7-0: Pipe buffer number */ 388#define M66592_BUFNMB 0x00FF /* b7-0: Pipe buffer number */
389 389
390#define M66592_PIPEMAXP 0x6A 390#define M66592_PIPEMAXP 0x6A
391#define M66592_MXPS 0x07FF /* b10-0: Maxpacket size */ 391#define M66592_MXPS 0x07FF /* b10-0: Maxpacket size */
392 392
393#define M66592_PIPEPERI 0x6C 393#define M66592_PIPEPERI 0x6C
394#define M66592_IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */ 394#define M66592_IFIS 0x1000 /* b12: ISO in-buffer flush mode */
395#define M66592_IITV 0x0007 /* b2-0: Isochronous interval */ 395#define M66592_IITV 0x0007 /* b2-0: ISO interval */
396 396
397#define M66592_PIPE1CTR 0x70 397#define M66592_PIPE1CTR 0x70
398#define M66592_PIPE2CTR 0x72 398#define M66592_PIPE2CTR 0x72
@@ -401,19 +401,17 @@
401#define M66592_PIPE5CTR 0x78 401#define M66592_PIPE5CTR 0x78
402#define M66592_PIPE6CTR 0x7A 402#define M66592_PIPE6CTR 0x7A
403#define M66592_PIPE7CTR 0x7C 403#define M66592_PIPE7CTR 0x7C
404#define M66592_BSTS 0x8000 /* b15: Buffer status */ 404#define M66592_BSTS 0x8000 /* b15: Buffer status */
405#define M66592_INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */ 405#define M66592_INBUFM 0x4000 /* b14: IN buffer monitor (PIPE 1-5) */
406#define M66592_ACLRM 0x0200 /* b9: Out buffer auto clear mode */ 406#define M66592_ACLRM 0x0200 /* b9: Out buffer auto clear mode */
407#define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */ 407#define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */
408#define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */ 408#define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */
409#define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */ 409#define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */
410#define M66592_PID 0x0003 /* b1-0: Response PID */ 410#define M66592_PID 0x0003 /* b1-0: Response PID */
411 411
412#define M66592_INVALID_REG 0x7E 412#define M66592_INVALID_REG 0x7E
413 413
414 414
415#define __iomem
416
417#define get_pipectr_addr(pipenum) (M66592_PIPE1CTR + (pipenum - 1) * 2) 415#define get_pipectr_addr(pipenum) (M66592_PIPE1CTR + (pipenum - 1) * 2)
418 416
419#define M66592_MAX_SAMPLING 10 417#define M66592_MAX_SAMPLING 10
@@ -449,7 +447,7 @@ struct m66592_ep {
449 struct m66592 *m66592; 447 struct m66592 *m66592;
450 448
451 struct list_head queue; 449 struct list_head queue;
452 unsigned busy:1; 450 unsigned busy:1;
453 unsigned internal_ccpl:1; /* use only control */ 451 unsigned internal_ccpl:1; /* use only control */
454 452
455 /* this member can able to after m66592_enable */ 453 /* this member can able to after m66592_enable */
@@ -477,7 +475,7 @@ struct m66592 {
477 struct m66592_ep *epaddr2ep[16]; 475 struct m66592_ep *epaddr2ep[16];
478 476
479 struct usb_request *ep0_req; /* for internal request */ 477 struct usb_request *ep0_req; /* for internal request */
480 u16 *ep0_buf; /* for internal request */ 478 u16 ep0_data; /* for internal request */
481 479
482 struct timer_list timer; 480 struct timer_list timer;
483 481
@@ -527,8 +525,8 @@ static inline u16 m66592_read(struct m66592 *m66592, unsigned long offset)
527} 525}
528 526
529static inline void m66592_read_fifo(struct m66592 *m66592, 527static inline void m66592_read_fifo(struct m66592 *m66592,
530 unsigned long offset, 528 unsigned long offset,
531 void *buf, unsigned long len) 529 void *buf, unsigned long len)
532{ 530{
533 unsigned long fifoaddr = (unsigned long)m66592->reg + offset; 531 unsigned long fifoaddr = (unsigned long)m66592->reg + offset;
534 532
@@ -543,8 +541,8 @@ static inline void m66592_write(struct m66592 *m66592, u16 val,
543} 541}
544 542
545static inline void m66592_write_fifo(struct m66592 *m66592, 543static inline void m66592_write_fifo(struct m66592 *m66592,
546 unsigned long offset, 544 unsigned long offset,
547 void *buf, unsigned long len) 545 void *buf, unsigned long len)
548{ 546{
549 unsigned long fifoaddr = (unsigned long)m66592->reg + offset; 547 unsigned long fifoaddr = (unsigned long)m66592->reg + offset;
550 unsigned long odd = len & 0x0001; 548 unsigned long odd = len & 0x0001;
@@ -558,7 +556,7 @@ static inline void m66592_write_fifo(struct m66592 *m66592,
558} 556}
559 557
560static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat, 558static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat,
561 unsigned long offset) 559 unsigned long offset)
562{ 560{
563 u16 tmp; 561 u16 tmp;
564 tmp = m66592_read(m66592, offset); 562 tmp = m66592_read(m66592, offset);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 16:40:09 -0500