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-rw-r--r--drivers/char/cs5535_gpio.c5
-rw-r--r--drivers/input/touchscreen/ads7846.c13
-rw-r--r--drivers/mmc/host/mmc_spi.c10
-rw-r--r--drivers/rtc/interface.c4
-rw-r--r--drivers/rtc/rtc-dev.c6
-rw-r--r--drivers/rtc/rtc-max6902.c12
-rw-r--r--drivers/spi/at25.c7
-rw-r--r--drivers/spi/spi.c19
-rw-r--r--drivers/spi/spi_bfin5xx.c866
9 files changed, 548 insertions, 394 deletions
diff --git a/drivers/char/cs5535_gpio.c b/drivers/char/cs5535_gpio.c
index fe6d2407baed..c2d23cae9515 100644
--- a/drivers/char/cs5535_gpio.c
+++ b/drivers/char/cs5535_gpio.c
@@ -104,6 +104,11 @@ static ssize_t cs5535_gpio_write(struct file *file, const char __user *data,
104 for (j = 0; j < ARRAY_SIZE(rm); j++) { 104 for (j = 0; j < ARRAY_SIZE(rm); j++) {
105 if (c == rm[j].on) { 105 if (c == rm[j].on) {
106 outl(m1, base + rm[j].wr_offset); 106 outl(m1, base + rm[j].wr_offset);
107 /* If enabling output, turn off AUX 1 and AUX 2 */
108 if (c == 'O') {
109 outl(m0, base + 0x10);
110 outl(m0, base + 0x14);
111 }
107 break; 112 break;
108 } else if (c == rm[j].off) { 113 } else if (c == rm[j].off) {
109 outl(m0, base + rm[j].wr_offset); 114 outl(m0, base + rm[j].wr_offset);
diff --git a/drivers/input/touchscreen/ads7846.c b/drivers/input/touchscreen/ads7846.c
index f59aecf5ec15..fd9c5d51870a 100644
--- a/drivers/input/touchscreen/ads7846.c
+++ b/drivers/input/touchscreen/ads7846.c
@@ -267,13 +267,12 @@ static int ads7846_read12_ser(struct device *dev, unsigned command)
267 ts->irq_disabled = 0; 267 ts->irq_disabled = 0;
268 enable_irq(spi->irq); 268 enable_irq(spi->irq);
269 269
270 if (req->msg.status) 270 if (status == 0) {
271 status = req->msg.status; 271 /* on-wire is a must-ignore bit, a BE12 value, then padding */
272 272 sample = be16_to_cpu(req->sample);
273 /* on-wire is a must-ignore bit, a BE12 value, then padding */ 273 sample = sample >> 3;
274 sample = be16_to_cpu(req->sample); 274 sample &= 0x0fff;
275 sample = sample >> 3; 275 }
276 sample &= 0x0fff;
277 276
278 kfree(req); 277 kfree(req);
279 return status ? status : sample; 278 return status ? status : sample;
diff --git a/drivers/mmc/host/mmc_spi.c b/drivers/mmc/host/mmc_spi.c
index a6469218f194..365024b83d3d 100644
--- a/drivers/mmc/host/mmc_spi.c
+++ b/drivers/mmc/host/mmc_spi.c
@@ -176,8 +176,6 @@ mmc_spi_readbytes(struct mmc_spi_host *host, unsigned len)
176 DMA_FROM_DEVICE); 176 DMA_FROM_DEVICE);
177 177
178 status = spi_sync(host->spi, &host->readback); 178 status = spi_sync(host->spi, &host->readback);
179 if (status == 0)
180 status = host->readback.status;
181 179
182 if (host->dma_dev) 180 if (host->dma_dev)
183 dma_sync_single_for_cpu(host->dma_dev, 181 dma_sync_single_for_cpu(host->dma_dev,
@@ -480,8 +478,6 @@ mmc_spi_command_send(struct mmc_spi_host *host,
480 DMA_BIDIRECTIONAL); 478 DMA_BIDIRECTIONAL);
481 } 479 }
482 status = spi_sync(host->spi, &host->m); 480 status = spi_sync(host->spi, &host->m);
483 if (status == 0)
484 status = host->m.status;
485 481
486 if (host->dma_dev) 482 if (host->dma_dev)
487 dma_sync_single_for_cpu(host->dma_dev, 483 dma_sync_single_for_cpu(host->dma_dev,
@@ -624,8 +620,6 @@ mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t)
624 DMA_BIDIRECTIONAL); 620 DMA_BIDIRECTIONAL);
625 621
626 status = spi_sync(spi, &host->m); 622 status = spi_sync(spi, &host->m);
627 if (status == 0)
628 status = host->m.status;
629 623
630 if (status != 0) { 624 if (status != 0) {
631 dev_dbg(&spi->dev, "write error (%d)\n", status); 625 dev_dbg(&spi->dev, "write error (%d)\n", status);
@@ -726,8 +720,6 @@ mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t)
726 } 720 }
727 721
728 status = spi_sync(spi, &host->m); 722 status = spi_sync(spi, &host->m);
729 if (status == 0)
730 status = host->m.status;
731 723
732 if (host->dma_dev) { 724 if (host->dma_dev) {
733 dma_sync_single_for_cpu(host->dma_dev, 725 dma_sync_single_for_cpu(host->dma_dev,
@@ -905,8 +897,6 @@ mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd,
905 DMA_BIDIRECTIONAL); 897 DMA_BIDIRECTIONAL);
906 898
907 tmp = spi_sync(spi, &host->m); 899 tmp = spi_sync(spi, &host->m);
908 if (tmp == 0)
909 tmp = host->m.status;
910 900
911 if (host->dma_dev) 901 if (host->dma_dev)
912 dma_sync_single_for_cpu(host->dma_dev, 902 dma_sync_single_for_cpu(host->dma_dev,
diff --git a/drivers/rtc/interface.c b/drivers/rtc/interface.c
index a4f56e95cf96..f1e00ff54ce8 100644
--- a/drivers/rtc/interface.c
+++ b/drivers/rtc/interface.c
@@ -293,7 +293,7 @@ int rtc_irq_register(struct rtc_device *rtc, struct rtc_task *task)
293 return -EINVAL; 293 return -EINVAL;
294 294
295 /* Cannot register while the char dev is in use */ 295 /* Cannot register while the char dev is in use */
296 if (test_and_set_bit(RTC_DEV_BUSY, &rtc->flags)) 296 if (test_and_set_bit_lock(RTC_DEV_BUSY, &rtc->flags))
297 return -EBUSY; 297 return -EBUSY;
298 298
299 spin_lock_irq(&rtc->irq_task_lock); 299 spin_lock_irq(&rtc->irq_task_lock);
@@ -303,7 +303,7 @@ int rtc_irq_register(struct rtc_device *rtc, struct rtc_task *task)
303 } 303 }
304 spin_unlock_irq(&rtc->irq_task_lock); 304 spin_unlock_irq(&rtc->irq_task_lock);
305 305
306 clear_bit(RTC_DEV_BUSY, &rtc->flags); 306 clear_bit_unlock(RTC_DEV_BUSY, &rtc->flags);
307 307
308 return retval; 308 return retval;
309} 309}
diff --git a/drivers/rtc/rtc-dev.c b/drivers/rtc/rtc-dev.c
index ae1bf177d625..025c60a17a4a 100644
--- a/drivers/rtc/rtc-dev.c
+++ b/drivers/rtc/rtc-dev.c
@@ -26,7 +26,7 @@ static int rtc_dev_open(struct inode *inode, struct file *file)
26 struct rtc_device, char_dev); 26 struct rtc_device, char_dev);
27 const struct rtc_class_ops *ops = rtc->ops; 27 const struct rtc_class_ops *ops = rtc->ops;
28 28
29 if (test_and_set_bit(RTC_DEV_BUSY, &rtc->flags)) 29 if (test_and_set_bit_lock(RTC_DEV_BUSY, &rtc->flags))
30 return -EBUSY; 30 return -EBUSY;
31 31
32 file->private_data = rtc; 32 file->private_data = rtc;
@@ -41,7 +41,7 @@ static int rtc_dev_open(struct inode *inode, struct file *file)
41 } 41 }
42 42
43 /* something has gone wrong */ 43 /* something has gone wrong */
44 clear_bit(RTC_DEV_BUSY, &rtc->flags); 44 clear_bit_unlock(RTC_DEV_BUSY, &rtc->flags);
45 return err; 45 return err;
46} 46}
47 47
@@ -402,7 +402,7 @@ static int rtc_dev_release(struct inode *inode, struct file *file)
402 if (rtc->ops->release) 402 if (rtc->ops->release)
403 rtc->ops->release(rtc->dev.parent); 403 rtc->ops->release(rtc->dev.parent);
404 404
405 clear_bit(RTC_DEV_BUSY, &rtc->flags); 405 clear_bit_unlock(RTC_DEV_BUSY, &rtc->flags);
406 return 0; 406 return 0;
407} 407}
408 408
diff --git a/drivers/rtc/rtc-max6902.c b/drivers/rtc/rtc-max6902.c
index 3e183cfee10f..1f956dc5d56e 100644
--- a/drivers/rtc/rtc-max6902.c
+++ b/drivers/rtc/rtc-max6902.c
@@ -89,13 +89,9 @@ static int max6902_get_reg(struct device *dev, unsigned char address,
89 89
90 /* do the i/o */ 90 /* do the i/o */
91 status = spi_sync(spi, &message); 91 status = spi_sync(spi, &message);
92 if (status == 0)
93 status = message.status;
94 else
95 return status;
96
97 *data = chip->rx_buf[1];
98 92
93 if (status == 0)
94 *data = chip->rx_buf[1];
99 return status; 95 return status;
100} 96}
101 97
@@ -125,9 +121,7 @@ static int max6902_get_datetime(struct device *dev, struct rtc_time *dt)
125 121
126 /* do the i/o */ 122 /* do the i/o */
127 status = spi_sync(spi, &message); 123 status = spi_sync(spi, &message);
128 if (status == 0) 124 if (status)
129 status = message.status;
130 else
131 return status; 125 return status;
132 126
133 /* The chip sends data in this order: 127 /* The chip sends data in this order:
diff --git a/drivers/spi/at25.c b/drivers/spi/at25.c
index e007833cca59..290dbe99647a 100644
--- a/drivers/spi/at25.c
+++ b/drivers/spi/at25.c
@@ -21,6 +21,13 @@
21#include <linux/spi/eeprom.h> 21#include <linux/spi/eeprom.h>
22 22
23 23
24/*
25 * NOTE: this is an *EEPROM* driver. The vagaries of product naming
26 * mean that some AT25 products are EEPROMs, and others are FLASH.
27 * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
28 * not this one!
29 */
30
24struct at25_data { 31struct at25_data {
25 struct spi_device *spi; 32 struct spi_device *spi;
26 struct mutex lock; 33 struct mutex lock;
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index b31f4431849b..93e9de46977a 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -541,10 +541,7 @@ static void spi_complete(void *arg)
541 * Also, the caller is guaranteeing that the memory associated with the 541 * Also, the caller is guaranteeing that the memory associated with the
542 * message will not be freed before this call returns. 542 * message will not be freed before this call returns.
543 * 543 *
544 * The return value is a negative error code if the message could not be 544 * It returns zero on success, else a negative error code.
545 * submitted, else zero. When the value is zero, then message->status is
546 * also defined; it's the completion code for the transfer, either zero
547 * or a negative error code from the controller driver.
548 */ 545 */
549int spi_sync(struct spi_device *spi, struct spi_message *message) 546int spi_sync(struct spi_device *spi, struct spi_message *message)
550{ 547{
@@ -554,8 +551,10 @@ int spi_sync(struct spi_device *spi, struct spi_message *message)
554 message->complete = spi_complete; 551 message->complete = spi_complete;
555 message->context = &done; 552 message->context = &done;
556 status = spi_async(spi, message); 553 status = spi_async(spi, message);
557 if (status == 0) 554 if (status == 0) {
558 wait_for_completion(&done); 555 wait_for_completion(&done);
556 status = message->status;
557 }
559 message->context = NULL; 558 message->context = NULL;
560 return status; 559 return status;
561} 560}
@@ -589,7 +588,7 @@ int spi_write_then_read(struct spi_device *spi,
589 const u8 *txbuf, unsigned n_tx, 588 const u8 *txbuf, unsigned n_tx,
590 u8 *rxbuf, unsigned n_rx) 589 u8 *rxbuf, unsigned n_rx)
591{ 590{
592 static DECLARE_MUTEX(lock); 591 static DEFINE_MUTEX(lock);
593 592
594 int status; 593 int status;
595 struct spi_message message; 594 struct spi_message message;
@@ -615,7 +614,7 @@ int spi_write_then_read(struct spi_device *spi,
615 } 614 }
616 615
617 /* ... unless someone else is using the pre-allocated buffer */ 616 /* ... unless someone else is using the pre-allocated buffer */
618 if (down_trylock(&lock)) { 617 if (!mutex_trylock(&lock)) {
619 local_buf = kmalloc(SPI_BUFSIZ, GFP_KERNEL); 618 local_buf = kmalloc(SPI_BUFSIZ, GFP_KERNEL);
620 if (!local_buf) 619 if (!local_buf)
621 return -ENOMEM; 620 return -ENOMEM;
@@ -628,13 +627,11 @@ int spi_write_then_read(struct spi_device *spi,
628 627
629 /* do the i/o */ 628 /* do the i/o */
630 status = spi_sync(spi, &message); 629 status = spi_sync(spi, &message);
631 if (status == 0) { 630 if (status == 0)
632 memcpy(rxbuf, x[1].rx_buf, n_rx); 631 memcpy(rxbuf, x[1].rx_buf, n_rx);
633 status = message.status;
634 }
635 632
636 if (x[0].tx_buf == buf) 633 if (x[0].tx_buf == buf)
637 up(&lock); 634 mutex_unlock(&lock);
638 else 635 else
639 kfree(local_buf); 636 kfree(local_buf);
640 637
diff --git a/drivers/spi/spi_bfin5xx.c b/drivers/spi/spi_bfin5xx.c
index 2ef11bb70b2e..22697b812205 100644
--- a/drivers/spi/spi_bfin5xx.c
+++ b/drivers/spi/spi_bfin5xx.c
@@ -1,17 +1,22 @@
1/* 1/*
2 * File: drivers/spi/bfin5xx_spi.c 2 * File: drivers/spi/bfin5xx_spi.c
3 * Based on: N/A 3 * Maintainer:
4 * Author: Luke Yang (Analog Devices Inc.) 4 * Bryan Wu <bryan.wu@analog.com>
5 * Original Author:
6 * Luke Yang (Analog Devices Inc.)
5 * 7 *
6 * Created: March. 10th 2006 8 * Created: March. 10th 2006
7 * Description: SPI controller driver for Blackfin 5xx 9 * Description: SPI controller driver for Blackfin BF5xx
8 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 10 * Bugs: Enter bugs at http://blackfin.uclinux.org/
9 * 11 *
10 * Modified: 12 * Modified:
11 * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang) 13 * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang)
12 * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang) 14 * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang)
15 * July 17, 2007 add support for BF54x SPI0 controller (Bryan Wu)
16 * July 30, 2007 add platfrom_resource interface to support multi-port
17 * SPI controller (Bryan Wu)
13 * 18 *
14 * Copyright 2004-2006 Analog Devices Inc. 19 * Copyright 2004-2007 Analog Devices Inc.
15 * 20 *
16 * This program is free software ; you can redistribute it and/or modify 21 * This program is free software ; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by 22 * it under the terms of the GNU General Public License as published by
@@ -31,50 +36,39 @@
31 36
32#include <linux/init.h> 37#include <linux/init.h>
33#include <linux/module.h> 38#include <linux/module.h>
39#include <linux/delay.h>
34#include <linux/device.h> 40#include <linux/device.h>
41#include <linux/io.h>
35#include <linux/ioport.h> 42#include <linux/ioport.h>
43#include <linux/irq.h>
36#include <linux/errno.h> 44#include <linux/errno.h>
37#include <linux/interrupt.h> 45#include <linux/interrupt.h>
38#include <linux/platform_device.h> 46#include <linux/platform_device.h>
39#include <linux/dma-mapping.h> 47#include <linux/dma-mapping.h>
40#include <linux/spi/spi.h> 48#include <linux/spi/spi.h>
41#include <linux/workqueue.h> 49#include <linux/workqueue.h>
42#include <linux/delay.h>
43 50
44#include <asm/io.h>
45#include <asm/irq.h>
46#include <asm/delay.h>
47#include <asm/dma.h> 51#include <asm/dma.h>
48 52#include <asm/portmux.h>
49#include <asm/bfin5xx_spi.h> 53#include <asm/bfin5xx_spi.h>
50 54
51MODULE_AUTHOR("Luke Yang"); 55#define DRV_NAME "bfin-spi"
52MODULE_DESCRIPTION("Blackfin 5xx SPI Contoller"); 56#define DRV_AUTHOR "Bryan Wu, Luke Yang"
53MODULE_LICENSE("GPL"); 57#define DRV_DESC "Blackfin BF5xx on-chip SPI Contoller Driver"
58#define DRV_VERSION "1.0"
54 59
55#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0) 60MODULE_AUTHOR(DRV_AUTHOR);
61MODULE_DESCRIPTION(DRV_DESC);
62MODULE_LICENSE("GPL");
56 63
57#define DEFINE_SPI_REG(reg, off) \ 64#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
58static inline u16 read_##reg(void) \
59 { return *(volatile unsigned short*)(SPI0_REGBASE + off); } \
60static inline void write_##reg(u16 v) \
61 {*(volatile unsigned short*)(SPI0_REGBASE + off) = v;\
62 SSYNC();}
63 65
64DEFINE_SPI_REG(CTRL, 0x00) 66#define START_STATE ((void *)0)
65DEFINE_SPI_REG(FLAG, 0x04) 67#define RUNNING_STATE ((void *)1)
66DEFINE_SPI_REG(STAT, 0x08) 68#define DONE_STATE ((void *)2)
67DEFINE_SPI_REG(TDBR, 0x0C) 69#define ERROR_STATE ((void *)-1)
68DEFINE_SPI_REG(RDBR, 0x10) 70#define QUEUE_RUNNING 0
69DEFINE_SPI_REG(BAUD, 0x14) 71#define QUEUE_STOPPED 1
70DEFINE_SPI_REG(SHAW, 0x18)
71#define START_STATE ((void*)0)
72#define RUNNING_STATE ((void*)1)
73#define DONE_STATE ((void*)2)
74#define ERROR_STATE ((void*)-1)
75#define QUEUE_RUNNING 0
76#define QUEUE_STOPPED 1
77int dma_requested;
78 72
79struct driver_data { 73struct driver_data {
80 /* Driver model hookup */ 74 /* Driver model hookup */
@@ -83,6 +77,12 @@ struct driver_data {
83 /* SPI framework hookup */ 77 /* SPI framework hookup */
84 struct spi_master *master; 78 struct spi_master *master;
85 79
80 /* Regs base of SPI controller */
81 void __iomem *regs_base;
82
83 /* Pin request list */
84 u16 *pin_req;
85
86 /* BFIN hookup */ 86 /* BFIN hookup */
87 struct bfin5xx_spi_master *master_info; 87 struct bfin5xx_spi_master *master_info;
88 88
@@ -107,12 +107,18 @@ struct driver_data {
107 void *tx_end; 107 void *tx_end;
108 void *rx; 108 void *rx;
109 void *rx_end; 109 void *rx_end;
110
111 /* DMA stuffs */
112 int dma_channel;
110 int dma_mapped; 113 int dma_mapped;
114 int dma_requested;
111 dma_addr_t rx_dma; 115 dma_addr_t rx_dma;
112 dma_addr_t tx_dma; 116 dma_addr_t tx_dma;
117
113 size_t rx_map_len; 118 size_t rx_map_len;
114 size_t tx_map_len; 119 size_t tx_map_len;
115 u8 n_bytes; 120 u8 n_bytes;
121 int cs_change;
116 void (*write) (struct driver_data *); 122 void (*write) (struct driver_data *);
117 void (*read) (struct driver_data *); 123 void (*read) (struct driver_data *);
118 void (*duplex) (struct driver_data *); 124 void (*duplex) (struct driver_data *);
@@ -129,28 +135,40 @@ struct chip_data {
129 u8 enable_dma; 135 u8 enable_dma;
130 u8 bits_per_word; /* 8 or 16 */ 136 u8 bits_per_word; /* 8 or 16 */
131 u8 cs_change_per_word; 137 u8 cs_change_per_word;
132 u8 cs_chg_udelay; 138 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
133 void (*write) (struct driver_data *); 139 void (*write) (struct driver_data *);
134 void (*read) (struct driver_data *); 140 void (*read) (struct driver_data *);
135 void (*duplex) (struct driver_data *); 141 void (*duplex) (struct driver_data *);
136}; 142};
137 143
144#define DEFINE_SPI_REG(reg, off) \
145static inline u16 read_##reg(struct driver_data *drv_data) \
146 { return bfin_read16(drv_data->regs_base + off); } \
147static inline void write_##reg(struct driver_data *drv_data, u16 v) \
148 { bfin_write16(drv_data->regs_base + off, v); }
149
150DEFINE_SPI_REG(CTRL, 0x00)
151DEFINE_SPI_REG(FLAG, 0x04)
152DEFINE_SPI_REG(STAT, 0x08)
153DEFINE_SPI_REG(TDBR, 0x0C)
154DEFINE_SPI_REG(RDBR, 0x10)
155DEFINE_SPI_REG(BAUD, 0x14)
156DEFINE_SPI_REG(SHAW, 0x18)
157
138static void bfin_spi_enable(struct driver_data *drv_data) 158static void bfin_spi_enable(struct driver_data *drv_data)
139{ 159{
140 u16 cr; 160 u16 cr;
141 161
142 cr = read_CTRL(); 162 cr = read_CTRL(drv_data);
143 write_CTRL(cr | BIT_CTL_ENABLE); 163 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
144 SSYNC();
145} 164}
146 165
147static void bfin_spi_disable(struct driver_data *drv_data) 166static void bfin_spi_disable(struct driver_data *drv_data)
148{ 167{
149 u16 cr; 168 u16 cr;
150 169
151 cr = read_CTRL(); 170 cr = read_CTRL(drv_data);
152 write_CTRL(cr & (~BIT_CTL_ENABLE)); 171 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
153 SSYNC();
154} 172}
155 173
156/* Caculate the SPI_BAUD register value based on input HZ */ 174/* Caculate the SPI_BAUD register value based on input HZ */
@@ -170,83 +188,71 @@ static int flush(struct driver_data *drv_data)
170 unsigned long limit = loops_per_jiffy << 1; 188 unsigned long limit = loops_per_jiffy << 1;
171 189
172 /* wait for stop and clear stat */ 190 /* wait for stop and clear stat */
173 while (!(read_STAT() & BIT_STAT_SPIF) && limit--) 191 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
174 continue; 192 cpu_relax();
175 193
176 write_STAT(BIT_STAT_CLR); 194 write_STAT(drv_data, BIT_STAT_CLR);
177 195
178 return limit; 196 return limit;
179} 197}
180 198
199/* Chip select operation functions for cs_change flag */
200static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
201{
202 u16 flag = read_FLAG(drv_data);
203
204 flag |= chip->flag;
205 flag &= ~(chip->flag << 8);
206
207 write_FLAG(drv_data, flag);
208}
209
210static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
211{
212 u16 flag = read_FLAG(drv_data);
213
214 flag |= (chip->flag << 8);
215
216 write_FLAG(drv_data, flag);
217
218 /* Move delay here for consistency */
219 if (chip->cs_chg_udelay)
220 udelay(chip->cs_chg_udelay);
221}
222
223#define MAX_SPI_SSEL 7
224
181/* stop controller and re-config current chip*/ 225/* stop controller and re-config current chip*/
182static void restore_state(struct driver_data *drv_data) 226static int restore_state(struct driver_data *drv_data)
183{ 227{
184 struct chip_data *chip = drv_data->cur_chip; 228 struct chip_data *chip = drv_data->cur_chip;
229 int ret = 0;
185 230
186 /* Clear status and disable clock */ 231 /* Clear status and disable clock */
187 write_STAT(BIT_STAT_CLR); 232 write_STAT(drv_data, BIT_STAT_CLR);
188 bfin_spi_disable(drv_data); 233 bfin_spi_disable(drv_data);
189 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); 234 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
190 235
191#if defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537) 236 /* Load the registers */
192 dev_dbg(&drv_data->pdev->dev, 237 write_CTRL(drv_data, chip->ctl_reg);
193 "chip select number is %d\n", chip->chip_select_num); 238 write_BAUD(drv_data, chip->baud);
194
195 switch (chip->chip_select_num) {
196 case 1:
197 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3c00);
198 SSYNC();
199 break;
200
201 case 2:
202 case 3:
203 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJSE_SPI);
204 SSYNC();
205 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);
206 SSYNC();
207 break;
208
209 case 4:
210 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS4E_SPI);
211 SSYNC();
212 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3840);
213 SSYNC();
214 break;
215 239
216 case 5: 240 bfin_spi_enable(drv_data);
217 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS5E_SPI); 241 cs_active(drv_data, chip);
218 SSYNC();
219 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3820);
220 SSYNC();
221 break;
222 242
223 case 6: 243 if (ret)
224 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS6E_SPI); 244 dev_dbg(&drv_data->pdev->dev,
225 SSYNC(); 245 ": request chip select number %d failed\n",
226 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3810); 246 chip->chip_select_num);
227 SSYNC();
228 break;
229 247
230 case 7: 248 return ret;
231 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJCE_SPI);
232 SSYNC();
233 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);
234 SSYNC();
235 break;
236 }
237#endif
238
239 /* Load the registers */
240 write_CTRL(chip->ctl_reg);
241 write_BAUD(chip->baud);
242 write_FLAG(chip->flag);
243} 249}
244 250
245/* used to kick off transfer in rx mode */ 251/* used to kick off transfer in rx mode */
246static unsigned short dummy_read(void) 252static unsigned short dummy_read(struct driver_data *drv_data)
247{ 253{
248 unsigned short tmp; 254 unsigned short tmp;
249 tmp = read_RDBR(); 255 tmp = read_RDBR(drv_data);
250 return tmp; 256 return tmp;
251} 257}
252 258
@@ -255,9 +261,9 @@ static void null_writer(struct driver_data *drv_data)
255 u8 n_bytes = drv_data->n_bytes; 261 u8 n_bytes = drv_data->n_bytes;
256 262
257 while (drv_data->tx < drv_data->tx_end) { 263 while (drv_data->tx < drv_data->tx_end) {
258 write_TDBR(0); 264 write_TDBR(drv_data, 0);
259 while ((read_STAT() & BIT_STAT_TXS)) 265 while ((read_STAT(drv_data) & BIT_STAT_TXS))
260 continue; 266 cpu_relax();
261 drv_data->tx += n_bytes; 267 drv_data->tx += n_bytes;
262 } 268 }
263} 269}
@@ -265,75 +271,78 @@ static void null_writer(struct driver_data *drv_data)
265static void null_reader(struct driver_data *drv_data) 271static void null_reader(struct driver_data *drv_data)
266{ 272{
267 u8 n_bytes = drv_data->n_bytes; 273 u8 n_bytes = drv_data->n_bytes;
268 dummy_read(); 274 dummy_read(drv_data);
269 275
270 while (drv_data->rx < drv_data->rx_end) { 276 while (drv_data->rx < drv_data->rx_end) {
271 while (!(read_STAT() & BIT_STAT_RXS)) 277 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
272 continue; 278 cpu_relax();
273 dummy_read(); 279 dummy_read(drv_data);
274 drv_data->rx += n_bytes; 280 drv_data->rx += n_bytes;
275 } 281 }
276} 282}
277 283
278static void u8_writer(struct driver_data *drv_data) 284static void u8_writer(struct driver_data *drv_data)
279{ 285{
280 dev_dbg(&drv_data->pdev->dev, 286 dev_dbg(&drv_data->pdev->dev,
281 "cr8-s is 0x%x\n", read_STAT()); 287 "cr8-s is 0x%x\n", read_STAT(drv_data));
288
289 /* poll for SPI completion before start */
290 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
291 cpu_relax();
292
282 while (drv_data->tx < drv_data->tx_end) { 293 while (drv_data->tx < drv_data->tx_end) {
283 write_TDBR(*(u8 *) (drv_data->tx)); 294 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
284 while (read_STAT() & BIT_STAT_TXS) 295 while (read_STAT(drv_data) & BIT_STAT_TXS)
285 continue; 296 cpu_relax();
286 ++drv_data->tx; 297 ++drv_data->tx;
287 } 298 }
288
289 /* poll for SPI completion before returning */
290 while (!(read_STAT() & BIT_STAT_SPIF))
291 continue;
292} 299}
293 300
294static void u8_cs_chg_writer(struct driver_data *drv_data) 301static void u8_cs_chg_writer(struct driver_data *drv_data)
295{ 302{
296 struct chip_data *chip = drv_data->cur_chip; 303 struct chip_data *chip = drv_data->cur_chip;
297 304
305 /* poll for SPI completion before start */
306 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
307 cpu_relax();
308
298 while (drv_data->tx < drv_data->tx_end) { 309 while (drv_data->tx < drv_data->tx_end) {
299 write_FLAG(chip->flag); 310 cs_active(drv_data, chip);
300 SSYNC(); 311
301 312 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
302 write_TDBR(*(u8 *) (drv_data->tx)); 313 while (read_STAT(drv_data) & BIT_STAT_TXS)
303 while (read_STAT() & BIT_STAT_TXS) 314 cpu_relax();
304 continue; 315
305 while (!(read_STAT() & BIT_STAT_SPIF)) 316 cs_deactive(drv_data, chip);
306 continue; 317
307 write_FLAG(0xFF00 | chip->flag);
308 SSYNC();
309 if (chip->cs_chg_udelay)
310 udelay(chip->cs_chg_udelay);
311 ++drv_data->tx; 318 ++drv_data->tx;
312 } 319 }
313 write_FLAG(0xFF00);
314 SSYNC();
315} 320}
316 321
317static void u8_reader(struct driver_data *drv_data) 322static void u8_reader(struct driver_data *drv_data)
318{ 323{
319 dev_dbg(&drv_data->pdev->dev, 324 dev_dbg(&drv_data->pdev->dev,
320 "cr-8 is 0x%x\n", read_STAT()); 325 "cr-8 is 0x%x\n", read_STAT(drv_data));
326
327 /* poll for SPI completion before start */
328 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
329 cpu_relax();
321 330
322 /* clear TDBR buffer before read(else it will be shifted out) */ 331 /* clear TDBR buffer before read(else it will be shifted out) */
323 write_TDBR(0xFFFF); 332 write_TDBR(drv_data, 0xFFFF);
324 333
325 dummy_read(); 334 dummy_read(drv_data);
326 335
327 while (drv_data->rx < drv_data->rx_end - 1) { 336 while (drv_data->rx < drv_data->rx_end - 1) {
328 while (!(read_STAT() & BIT_STAT_RXS)) 337 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
329 continue; 338 cpu_relax();
330 *(u8 *) (drv_data->rx) = read_RDBR(); 339 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
331 ++drv_data->rx; 340 ++drv_data->rx;
332 } 341 }
333 342
334 while (!(read_STAT() & BIT_STAT_RXS)) 343 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
335 continue; 344 cpu_relax();
336 *(u8 *) (drv_data->rx) = read_SHAW(); 345 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
337 ++drv_data->rx; 346 ++drv_data->rx;
338} 347}
339 348
@@ -341,36 +350,47 @@ static void u8_cs_chg_reader(struct driver_data *drv_data)
341{ 350{
342 struct chip_data *chip = drv_data->cur_chip; 351 struct chip_data *chip = drv_data->cur_chip;
343 352
344 while (drv_data->rx < drv_data->rx_end) { 353 /* poll for SPI completion before start */
345 write_FLAG(chip->flag); 354 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
346 SSYNC(); 355 cpu_relax();
347 356
348 read_RDBR(); /* kick off */ 357 /* clear TDBR buffer before read(else it will be shifted out) */
349 while (!(read_STAT() & BIT_STAT_RXS)) 358 write_TDBR(drv_data, 0xFFFF);
350 continue; 359
351 while (!(read_STAT() & BIT_STAT_SPIF)) 360 cs_active(drv_data, chip);
352 continue; 361 dummy_read(drv_data);
353 *(u8 *) (drv_data->rx) = read_SHAW(); 362
354 write_FLAG(0xFF00 | chip->flag); 363 while (drv_data->rx < drv_data->rx_end - 1) {
355 SSYNC(); 364 cs_deactive(drv_data, chip);
356 if (chip->cs_chg_udelay) 365
357 udelay(chip->cs_chg_udelay); 366 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
367 cpu_relax();
368 cs_active(drv_data, chip);
369 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
358 ++drv_data->rx; 370 ++drv_data->rx;
359 } 371 }
360 write_FLAG(0xFF00); 372 cs_deactive(drv_data, chip);
361 SSYNC(); 373
374 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
375 cpu_relax();
376 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
377 ++drv_data->rx;
362} 378}
363 379
364static void u8_duplex(struct driver_data *drv_data) 380static void u8_duplex(struct driver_data *drv_data)
365{ 381{
382 /* poll for SPI completion before start */
383 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
384 cpu_relax();
385
366 /* in duplex mode, clk is triggered by writing of TDBR */ 386 /* in duplex mode, clk is triggered by writing of TDBR */
367 while (drv_data->rx < drv_data->rx_end) { 387 while (drv_data->rx < drv_data->rx_end) {
368 write_TDBR(*(u8 *) (drv_data->tx)); 388 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
369 while (!(read_STAT() & BIT_STAT_SPIF)) 389 while (read_STAT(drv_data) & BIT_STAT_TXS)
370 continue; 390 cpu_relax();
371 while (!(read_STAT() & BIT_STAT_RXS)) 391 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
372 continue; 392 cpu_relax();
373 *(u8 *) (drv_data->rx) = read_RDBR(); 393 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
374 ++drv_data->rx; 394 ++drv_data->rx;
375 ++drv_data->tx; 395 ++drv_data->tx;
376 } 396 }
@@ -380,83 +400,89 @@ static void u8_cs_chg_duplex(struct driver_data *drv_data)
380{ 400{
381 struct chip_data *chip = drv_data->cur_chip; 401 struct chip_data *chip = drv_data->cur_chip;
382 402
403 /* poll for SPI completion before start */
404 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
405 cpu_relax();
406
383 while (drv_data->rx < drv_data->rx_end) { 407 while (drv_data->rx < drv_data->rx_end) {
384 write_FLAG(chip->flag); 408 cs_active(drv_data, chip);
385 SSYNC(); 409
386 410 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
387 write_TDBR(*(u8 *) (drv_data->tx)); 411 while (read_STAT(drv_data) & BIT_STAT_TXS)
388 while (!(read_STAT() & BIT_STAT_SPIF)) 412 cpu_relax();
389 continue; 413 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
390 while (!(read_STAT() & BIT_STAT_RXS)) 414 cpu_relax();
391 continue; 415 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
392 *(u8 *) (drv_data->rx) = read_RDBR(); 416
393 write_FLAG(0xFF00 | chip->flag); 417 cs_deactive(drv_data, chip);
394 SSYNC(); 418
395 if (chip->cs_chg_udelay)
396 udelay(chip->cs_chg_udelay);
397 ++drv_data->rx; 419 ++drv_data->rx;
398 ++drv_data->tx; 420 ++drv_data->tx;
399 } 421 }
400 write_FLAG(0xFF00);
401 SSYNC();
402} 422}
403 423
404static void u16_writer(struct driver_data *drv_data) 424static void u16_writer(struct driver_data *drv_data)
405{ 425{
406 dev_dbg(&drv_data->pdev->dev, 426 dev_dbg(&drv_data->pdev->dev,
407 "cr16 is 0x%x\n", read_STAT()); 427 "cr16 is 0x%x\n", read_STAT(drv_data));
428
429 /* poll for SPI completion before start */
430 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
431 cpu_relax();
408 432
409 while (drv_data->tx < drv_data->tx_end) { 433 while (drv_data->tx < drv_data->tx_end) {
410 write_TDBR(*(u16 *) (drv_data->tx)); 434 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
411 while ((read_STAT() & BIT_STAT_TXS)) 435 while ((read_STAT(drv_data) & BIT_STAT_TXS))
412 continue; 436 cpu_relax();
413 drv_data->tx += 2; 437 drv_data->tx += 2;
414 } 438 }
415
416 /* poll for SPI completion before returning */
417 while (!(read_STAT() & BIT_STAT_SPIF))
418 continue;
419} 439}
420 440
421static void u16_cs_chg_writer(struct driver_data *drv_data) 441static void u16_cs_chg_writer(struct driver_data *drv_data)
422{ 442{
423 struct chip_data *chip = drv_data->cur_chip; 443 struct chip_data *chip = drv_data->cur_chip;
424 444
445 /* poll for SPI completion before start */
446 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
447 cpu_relax();
448
425 while (drv_data->tx < drv_data->tx_end) { 449 while (drv_data->tx < drv_data->tx_end) {
426 write_FLAG(chip->flag); 450 cs_active(drv_data, chip);
427 SSYNC(); 451
428 452 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
429 write_TDBR(*(u16 *) (drv_data->tx)); 453 while ((read_STAT(drv_data) & BIT_STAT_TXS))
430 while ((read_STAT() & BIT_STAT_TXS)) 454 cpu_relax();
431 continue; 455
432 while (!(read_STAT() & BIT_STAT_SPIF)) 456 cs_deactive(drv_data, chip);
433 continue; 457
434 write_FLAG(0xFF00 | chip->flag);
435 SSYNC();
436 if (chip->cs_chg_udelay)
437 udelay(chip->cs_chg_udelay);
438 drv_data->tx += 2; 458 drv_data->tx += 2;
439 } 459 }
440 write_FLAG(0xFF00);
441 SSYNC();
442} 460}
443 461
444static void u16_reader(struct driver_data *drv_data) 462static void u16_reader(struct driver_data *drv_data)
445{ 463{
446 dev_dbg(&drv_data->pdev->dev, 464 dev_dbg(&drv_data->pdev->dev,
447 "cr-16 is 0x%x\n", read_STAT()); 465 "cr-16 is 0x%x\n", read_STAT(drv_data));
448 dummy_read(); 466
467 /* poll for SPI completion before start */
468 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
469 cpu_relax();
470
471 /* clear TDBR buffer before read(else it will be shifted out) */
472 write_TDBR(drv_data, 0xFFFF);
473
474 dummy_read(drv_data);
449 475
450 while (drv_data->rx < (drv_data->rx_end - 2)) { 476 while (drv_data->rx < (drv_data->rx_end - 2)) {
451 while (!(read_STAT() & BIT_STAT_RXS)) 477 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
452 continue; 478 cpu_relax();
453 *(u16 *) (drv_data->rx) = read_RDBR(); 479 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
454 drv_data->rx += 2; 480 drv_data->rx += 2;
455 } 481 }
456 482
457 while (!(read_STAT() & BIT_STAT_RXS)) 483 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
458 continue; 484 cpu_relax();
459 *(u16 *) (drv_data->rx) = read_SHAW(); 485 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
460 drv_data->rx += 2; 486 drv_data->rx += 2;
461} 487}
462 488
@@ -464,36 +490,47 @@ static void u16_cs_chg_reader(struct driver_data *drv_data)
464{ 490{
465 struct chip_data *chip = drv_data->cur_chip; 491 struct chip_data *chip = drv_data->cur_chip;
466 492
467 while (drv_data->rx < drv_data->rx_end) { 493 /* poll for SPI completion before start */
468 write_FLAG(chip->flag); 494 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
469 SSYNC(); 495 cpu_relax();
470 496
471 read_RDBR(); /* kick off */ 497 /* clear TDBR buffer before read(else it will be shifted out) */
472 while (!(read_STAT() & BIT_STAT_RXS)) 498 write_TDBR(drv_data, 0xFFFF);
473 continue; 499
474 while (!(read_STAT() & BIT_STAT_SPIF)) 500 cs_active(drv_data, chip);
475 continue; 501 dummy_read(drv_data);
476 *(u16 *) (drv_data->rx) = read_SHAW(); 502
477 write_FLAG(0xFF00 | chip->flag); 503 while (drv_data->rx < drv_data->rx_end - 2) {
478 SSYNC(); 504 cs_deactive(drv_data, chip);
479 if (chip->cs_chg_udelay) 505
480 udelay(chip->cs_chg_udelay); 506 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
507 cpu_relax();
508 cs_active(drv_data, chip);
509 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
481 drv_data->rx += 2; 510 drv_data->rx += 2;
482 } 511 }
483 write_FLAG(0xFF00); 512 cs_deactive(drv_data, chip);
484 SSYNC(); 513
514 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
515 cpu_relax();
516 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
517 drv_data->rx += 2;
485} 518}
486 519
487static void u16_duplex(struct driver_data *drv_data) 520static void u16_duplex(struct driver_data *drv_data)
488{ 521{
522 /* poll for SPI completion before start */
523 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
524 cpu_relax();
525
489 /* in duplex mode, clk is triggered by writing of TDBR */ 526 /* in duplex mode, clk is triggered by writing of TDBR */
490 while (drv_data->tx < drv_data->tx_end) { 527 while (drv_data->tx < drv_data->tx_end) {
491 write_TDBR(*(u16 *) (drv_data->tx)); 528 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
492 while (!(read_STAT() & BIT_STAT_SPIF)) 529 while (read_STAT(drv_data) & BIT_STAT_TXS)
493 continue; 530 cpu_relax();
494 while (!(read_STAT() & BIT_STAT_RXS)) 531 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
495 continue; 532 cpu_relax();
496 *(u16 *) (drv_data->rx) = read_RDBR(); 533 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
497 drv_data->rx += 2; 534 drv_data->rx += 2;
498 drv_data->tx += 2; 535 drv_data->tx += 2;
499 } 536 }
@@ -503,25 +540,25 @@ static void u16_cs_chg_duplex(struct driver_data *drv_data)
503{ 540{
504 struct chip_data *chip = drv_data->cur_chip; 541 struct chip_data *chip = drv_data->cur_chip;
505 542
543 /* poll for SPI completion before start */
544 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
545 cpu_relax();
546
506 while (drv_data->tx < drv_data->tx_end) { 547 while (drv_data->tx < drv_data->tx_end) {
507 write_FLAG(chip->flag); 548 cs_active(drv_data, chip);
508 SSYNC(); 549
509 550 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
510 write_TDBR(*(u16 *) (drv_data->tx)); 551 while (read_STAT(drv_data) & BIT_STAT_TXS)
511 while (!(read_STAT() & BIT_STAT_SPIF)) 552 cpu_relax();
512 continue; 553 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
513 while (!(read_STAT() & BIT_STAT_RXS)) 554 cpu_relax();
514 continue; 555 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
515 *(u16 *) (drv_data->rx) = read_RDBR(); 556
516 write_FLAG(0xFF00 | chip->flag); 557 cs_deactive(drv_data, chip);
517 SSYNC(); 558
518 if (chip->cs_chg_udelay)
519 udelay(chip->cs_chg_udelay);
520 drv_data->rx += 2; 559 drv_data->rx += 2;
521 drv_data->tx += 2; 560 drv_data->tx += 2;
522 } 561 }
523 write_FLAG(0xFF00);
524 SSYNC();
525} 562}
526 563
527/* test if ther is more transfer to be done */ 564/* test if ther is more transfer to be done */
@@ -546,6 +583,7 @@ static void *next_transfer(struct driver_data *drv_data)
546 */ 583 */
547static void giveback(struct driver_data *drv_data) 584static void giveback(struct driver_data *drv_data)
548{ 585{
586 struct chip_data *chip = drv_data->cur_chip;
549 struct spi_transfer *last_transfer; 587 struct spi_transfer *last_transfer;
550 unsigned long flags; 588 unsigned long flags;
551 struct spi_message *msg; 589 struct spi_message *msg;
@@ -565,10 +603,13 @@ static void giveback(struct driver_data *drv_data)
565 603
566 /* disable chip select signal. And not stop spi in autobuffer mode */ 604 /* disable chip select signal. And not stop spi in autobuffer mode */
567 if (drv_data->tx_dma != 0xFFFF) { 605 if (drv_data->tx_dma != 0xFFFF) {
568 write_FLAG(0xFF00); 606 cs_deactive(drv_data, chip);
569 bfin_spi_disable(drv_data); 607 bfin_spi_disable(drv_data);
570 } 608 }
571 609
610 if (!drv_data->cs_change)
611 cs_deactive(drv_data, chip);
612
572 if (msg->complete) 613 if (msg->complete)
573 msg->complete(msg->context); 614 msg->complete(msg->context);
574} 615}
@@ -576,14 +617,15 @@ static void giveback(struct driver_data *drv_data)
576static irqreturn_t dma_irq_handler(int irq, void *dev_id) 617static irqreturn_t dma_irq_handler(int irq, void *dev_id)
577{ 618{
578 struct driver_data *drv_data = (struct driver_data *)dev_id; 619 struct driver_data *drv_data = (struct driver_data *)dev_id;
620 struct chip_data *chip = drv_data->cur_chip;
579 struct spi_message *msg = drv_data->cur_msg; 621 struct spi_message *msg = drv_data->cur_msg;
580 622
581 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n"); 623 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
582 clear_dma_irqstat(CH_SPI); 624 clear_dma_irqstat(drv_data->dma_channel);
583 625
584 /* Wait for DMA to complete */ 626 /* Wait for DMA to complete */
585 while (get_dma_curr_irqstat(CH_SPI) & DMA_RUN) 627 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
586 continue; 628 cpu_relax();
587 629
588 /* 630 /*
589 * wait for the last transaction shifted out. HRM states: 631 * wait for the last transaction shifted out. HRM states:
@@ -592,18 +634,19 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
592 * register until it goes low for 2 successive reads 634 * register until it goes low for 2 successive reads
593 */ 635 */
594 if (drv_data->tx != NULL) { 636 if (drv_data->tx != NULL) {
595 while ((bfin_read_SPI_STAT() & TXS) || 637 while ((read_STAT(drv_data) & TXS) ||
596 (bfin_read_SPI_STAT() & TXS)) 638 (read_STAT(drv_data) & TXS))
597 continue; 639 cpu_relax();
598 } 640 }
599 641
600 while (!(bfin_read_SPI_STAT() & SPIF)) 642 while (!(read_STAT(drv_data) & SPIF))
601 continue; 643 cpu_relax();
602
603 bfin_spi_disable(drv_data);
604 644
605 msg->actual_length += drv_data->len_in_bytes; 645 msg->actual_length += drv_data->len_in_bytes;
606 646
647 if (drv_data->cs_change)
648 cs_deactive(drv_data, chip);
649
607 /* Move to next transfer */ 650 /* Move to next transfer */
608 msg->state = next_transfer(drv_data); 651 msg->state = next_transfer(drv_data);
609 652
@@ -613,8 +656,8 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
613 /* free the irq handler before next transfer */ 656 /* free the irq handler before next transfer */
614 dev_dbg(&drv_data->pdev->dev, 657 dev_dbg(&drv_data->pdev->dev,
615 "disable dma channel irq%d\n", 658 "disable dma channel irq%d\n",
616 CH_SPI); 659 drv_data->dma_channel);
617 dma_disable_irq(CH_SPI); 660 dma_disable_irq(drv_data->dma_channel);
618 661
619 return IRQ_HANDLED; 662 return IRQ_HANDLED;
620} 663}
@@ -690,31 +733,67 @@ static void pump_transfers(unsigned long data)
690 drv_data->rx_dma = transfer->rx_dma; 733 drv_data->rx_dma = transfer->rx_dma;
691 drv_data->tx_dma = transfer->tx_dma; 734 drv_data->tx_dma = transfer->tx_dma;
692 drv_data->len_in_bytes = transfer->len; 735 drv_data->len_in_bytes = transfer->len;
736 drv_data->cs_change = transfer->cs_change;
737
738 /* Bits per word setup */
739 switch (transfer->bits_per_word) {
740 case 8:
741 drv_data->n_bytes = 1;
742 width = CFG_SPI_WORDSIZE8;
743 drv_data->read = chip->cs_change_per_word ?
744 u8_cs_chg_reader : u8_reader;
745 drv_data->write = chip->cs_change_per_word ?
746 u8_cs_chg_writer : u8_writer;
747 drv_data->duplex = chip->cs_change_per_word ?
748 u8_cs_chg_duplex : u8_duplex;
749 break;
750
751 case 16:
752 drv_data->n_bytes = 2;
753 width = CFG_SPI_WORDSIZE16;
754 drv_data->read = chip->cs_change_per_word ?
755 u16_cs_chg_reader : u16_reader;
756 drv_data->write = chip->cs_change_per_word ?
757 u16_cs_chg_writer : u16_writer;
758 drv_data->duplex = chip->cs_change_per_word ?
759 u16_cs_chg_duplex : u16_duplex;
760 break;
761
762 default:
763 /* No change, the same as default setting */
764 drv_data->n_bytes = chip->n_bytes;
765 width = chip->width;
766 drv_data->write = drv_data->tx ? chip->write : null_writer;
767 drv_data->read = drv_data->rx ? chip->read : null_reader;
768 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
769 break;
770 }
771 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
772 cr |= (width << 8);
773 write_CTRL(drv_data, cr);
693 774
694 width = chip->width;
695 if (width == CFG_SPI_WORDSIZE16) { 775 if (width == CFG_SPI_WORDSIZE16) {
696 drv_data->len = (transfer->len) >> 1; 776 drv_data->len = (transfer->len) >> 1;
697 } else { 777 } else {
698 drv_data->len = transfer->len; 778 drv_data->len = transfer->len;
699 } 779 }
700 drv_data->write = drv_data->tx ? chip->write : null_writer; 780 dev_dbg(&drv_data->pdev->dev, "transfer: ",
701 drv_data->read = drv_data->rx ? chip->read : null_reader; 781 "drv_data->write is %p, chip->write is %p, null_wr is %p\n",
702 drv_data->duplex = chip->duplex ? chip->duplex : null_writer; 782 drv_data->write, chip->write, null_writer);
703 dev_dbg(&drv_data->pdev->dev,
704 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
705 drv_data->write, chip->write, null_writer);
706 783
707 /* speed and width has been set on per message */ 784 /* speed and width has been set on per message */
708 message->state = RUNNING_STATE; 785 message->state = RUNNING_STATE;
709 dma_config = 0; 786 dma_config = 0;
710 787
711 /* restore spi status for each spi transfer */ 788 /* Speed setup (surely valid because already checked) */
712 if (transfer->speed_hz) { 789 if (transfer->speed_hz)
713 write_BAUD(hz_to_spi_baud(transfer->speed_hz)); 790 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
714 } else { 791 else
715 write_BAUD(chip->baud); 792 write_BAUD(drv_data, chip->baud);
716 } 793
717 write_FLAG(chip->flag); 794 write_STAT(drv_data, BIT_STAT_CLR);
795 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
796 cs_active(drv_data, chip);
718 797
719 dev_dbg(&drv_data->pdev->dev, 798 dev_dbg(&drv_data->pdev->dev,
720 "now pumping a transfer: width is %d, len is %d\n", 799 "now pumping a transfer: width is %d, len is %d\n",
@@ -727,25 +806,25 @@ static void pump_transfers(unsigned long data)
727 */ 806 */
728 if (drv_data->cur_chip->enable_dma && drv_data->len > 6) { 807 if (drv_data->cur_chip->enable_dma && drv_data->len > 6) {
729 808
730 write_STAT(BIT_STAT_CLR); 809 disable_dma(drv_data->dma_channel);
731 disable_dma(CH_SPI); 810 clear_dma_irqstat(drv_data->dma_channel);
732 clear_dma_irqstat(CH_SPI);
733 bfin_spi_disable(drv_data); 811 bfin_spi_disable(drv_data);
734 812
735 /* config dma channel */ 813 /* config dma channel */
736 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); 814 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
737 if (width == CFG_SPI_WORDSIZE16) { 815 if (width == CFG_SPI_WORDSIZE16) {
738 set_dma_x_count(CH_SPI, drv_data->len); 816 set_dma_x_count(drv_data->dma_channel, drv_data->len);
739 set_dma_x_modify(CH_SPI, 2); 817 set_dma_x_modify(drv_data->dma_channel, 2);
740 dma_width = WDSIZE_16; 818 dma_width = WDSIZE_16;
741 } else { 819 } else {
742 set_dma_x_count(CH_SPI, drv_data->len); 820 set_dma_x_count(drv_data->dma_channel, drv_data->len);
743 set_dma_x_modify(CH_SPI, 1); 821 set_dma_x_modify(drv_data->dma_channel, 1);
744 dma_width = WDSIZE_8; 822 dma_width = WDSIZE_8;
745 } 823 }
746 824
747 /* set transfer width,direction. And enable spi */ 825 /* poll for SPI completion before start */
748 cr = (read_CTRL() & (~BIT_CTL_TIMOD)); 826 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
827 cpu_relax();
749 828
750 /* dirty hack for autobuffer DMA mode */ 829 /* dirty hack for autobuffer DMA mode */
751 if (drv_data->tx_dma == 0xFFFF) { 830 if (drv_data->tx_dma == 0xFFFF) {
@@ -755,13 +834,18 @@ static void pump_transfers(unsigned long data)
755 /* no irq in autobuffer mode */ 834 /* no irq in autobuffer mode */
756 dma_config = 835 dma_config =
757 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN); 836 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
758 set_dma_config(CH_SPI, dma_config); 837 set_dma_config(drv_data->dma_channel, dma_config);
759 set_dma_start_addr(CH_SPI, (unsigned long)drv_data->tx); 838 set_dma_start_addr(drv_data->dma_channel,
760 enable_dma(CH_SPI); 839 (unsigned long)drv_data->tx);
761 write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) | 840 enable_dma(drv_data->dma_channel);
762 (CFG_SPI_ENABLE << 14)); 841
763 842 /* start SPI transfer */
764 /* just return here, there can only be one transfer in this mode */ 843 write_CTRL(drv_data,
844 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
845
846 /* just return here, there can only be one transfer
847 * in this mode
848 */
765 message->status = 0; 849 message->status = 0;
766 giveback(drv_data); 850 giveback(drv_data);
767 return; 851 return;
@@ -772,58 +856,51 @@ static void pump_transfers(unsigned long data)
772 /* set transfer mode, and enable SPI */ 856 /* set transfer mode, and enable SPI */
773 dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n"); 857 dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
774 858
775 /* disable SPI before write to TDBR */
776 write_CTRL(cr & ~BIT_CTL_ENABLE);
777
778 /* clear tx reg soformer data is not shifted out */ 859 /* clear tx reg soformer data is not shifted out */
779 write_TDBR(0xFF); 860 write_TDBR(drv_data, 0xFFFF);
780 861
781 set_dma_x_count(CH_SPI, drv_data->len); 862 set_dma_x_count(drv_data->dma_channel, drv_data->len);
782 863
783 /* start dma */ 864 /* start dma */
784 dma_enable_irq(CH_SPI); 865 dma_enable_irq(drv_data->dma_channel);
785 dma_config = (WNR | RESTART | dma_width | DI_EN); 866 dma_config = (WNR | RESTART | dma_width | DI_EN);
786 set_dma_config(CH_SPI, dma_config); 867 set_dma_config(drv_data->dma_channel, dma_config);
787 set_dma_start_addr(CH_SPI, (unsigned long)drv_data->rx); 868 set_dma_start_addr(drv_data->dma_channel,
788 enable_dma(CH_SPI); 869 (unsigned long)drv_data->rx);
870 enable_dma(drv_data->dma_channel);
871
872 /* start SPI transfer */
873 write_CTRL(drv_data,
874 (cr | CFG_SPI_DMAREAD | BIT_CTL_ENABLE));
789 875
790 cr |=
791 CFG_SPI_DMAREAD | (width << 8) | (CFG_SPI_ENABLE <<
792 14);
793 /* set transfer mode, and enable SPI */
794 write_CTRL(cr);
795 } else if (drv_data->tx != NULL) { 876 } else if (drv_data->tx != NULL) {
796 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n"); 877 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
797 878
798 /* start dma */ 879 /* start dma */
799 dma_enable_irq(CH_SPI); 880 dma_enable_irq(drv_data->dma_channel);
800 dma_config = (RESTART | dma_width | DI_EN); 881 dma_config = (RESTART | dma_width | DI_EN);
801 set_dma_config(CH_SPI, dma_config); 882 set_dma_config(drv_data->dma_channel, dma_config);
802 set_dma_start_addr(CH_SPI, (unsigned long)drv_data->tx); 883 set_dma_start_addr(drv_data->dma_channel,
803 enable_dma(CH_SPI); 884 (unsigned long)drv_data->tx);
804 885 enable_dma(drv_data->dma_channel);
805 write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) | 886
806 (CFG_SPI_ENABLE << 14)); 887 /* start SPI transfer */
807 888 write_CTRL(drv_data,
889 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
808 } 890 }
809 } else { 891 } else {
810 /* IO mode write then read */ 892 /* IO mode write then read */
811 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); 893 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
812 894
813 write_STAT(BIT_STAT_CLR);
814
815 if (drv_data->tx != NULL && drv_data->rx != NULL) { 895 if (drv_data->tx != NULL && drv_data->rx != NULL) {
816 /* full duplex mode */ 896 /* full duplex mode */
817 BUG_ON((drv_data->tx_end - drv_data->tx) != 897 BUG_ON((drv_data->tx_end - drv_data->tx) !=
818 (drv_data->rx_end - drv_data->rx)); 898 (drv_data->rx_end - drv_data->rx));
819 cr = (read_CTRL() & (~BIT_CTL_TIMOD));
820 cr |= CFG_SPI_WRITE | (width << 8) |
821 (CFG_SPI_ENABLE << 14);
822 dev_dbg(&drv_data->pdev->dev, 899 dev_dbg(&drv_data->pdev->dev,
823 "IO duplex: cr is 0x%x\n", cr); 900 "IO duplex: cr is 0x%x\n", cr);
824 901
825 write_CTRL(cr); 902 /* set SPI transfer mode */
826 SSYNC(); 903 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
827 904
828 drv_data->duplex(drv_data); 905 drv_data->duplex(drv_data);
829 906
@@ -831,14 +908,11 @@ static void pump_transfers(unsigned long data)
831 tranf_success = 0; 908 tranf_success = 0;
832 } else if (drv_data->tx != NULL) { 909 } else if (drv_data->tx != NULL) {
833 /* write only half duplex */ 910 /* write only half duplex */
834 cr = (read_CTRL() & (~BIT_CTL_TIMOD)); 911 dev_dbg(&drv_data->pdev->dev,
835 cr |= CFG_SPI_WRITE | (width << 8) |
836 (CFG_SPI_ENABLE << 14);
837 dev_dbg(&drv_data->pdev->dev,
838 "IO write: cr is 0x%x\n", cr); 912 "IO write: cr is 0x%x\n", cr);
839 913
840 write_CTRL(cr); 914 /* set SPI transfer mode */
841 SSYNC(); 915 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
842 916
843 drv_data->write(drv_data); 917 drv_data->write(drv_data);
844 918
@@ -846,14 +920,11 @@ static void pump_transfers(unsigned long data)
846 tranf_success = 0; 920 tranf_success = 0;
847 } else if (drv_data->rx != NULL) { 921 } else if (drv_data->rx != NULL) {
848 /* read only half duplex */ 922 /* read only half duplex */
849 cr = (read_CTRL() & (~BIT_CTL_TIMOD)); 923 dev_dbg(&drv_data->pdev->dev,
850 cr |= CFG_SPI_READ | (width << 8) |
851 (CFG_SPI_ENABLE << 14);
852 dev_dbg(&drv_data->pdev->dev,
853 "IO read: cr is 0x%x\n", cr); 924 "IO read: cr is 0x%x\n", cr);
854 925
855 write_CTRL(cr); 926 /* set SPI transfer mode */
856 SSYNC(); 927 write_CTRL(drv_data, (cr | CFG_SPI_READ));
857 928
858 drv_data->read(drv_data); 929 drv_data->read(drv_data);
859 if (drv_data->rx != drv_data->rx_end) 930 if (drv_data->rx != drv_data->rx_end)
@@ -861,7 +932,7 @@ static void pump_transfers(unsigned long data)
861 } 932 }
862 933
863 if (!tranf_success) { 934 if (!tranf_success) {
864 dev_dbg(&drv_data->pdev->dev, 935 dev_dbg(&drv_data->pdev->dev,
865 "IO write error!\n"); 936 "IO write error!\n");
866 message->state = ERROR_STATE; 937 message->state = ERROR_STATE;
867 } else { 938 } else {
@@ -881,9 +952,11 @@ static void pump_transfers(unsigned long data)
881/* pop a msg from queue and kick off real transfer */ 952/* pop a msg from queue and kick off real transfer */
882static void pump_messages(struct work_struct *work) 953static void pump_messages(struct work_struct *work)
883{ 954{
884 struct driver_data *drv_data = container_of(work, struct driver_data, pump_messages); 955 struct driver_data *drv_data;
885 unsigned long flags; 956 unsigned long flags;
886 957
958 drv_data = container_of(work, struct driver_data, pump_messages);
959
887 /* Lock queue and check for queue work */ 960 /* Lock queue and check for queue work */
888 spin_lock_irqsave(&drv_data->lock, flags); 961 spin_lock_irqsave(&drv_data->lock, flags);
889 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) { 962 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
@@ -902,6 +975,14 @@ static void pump_messages(struct work_struct *work)
902 /* Extract head of queue */ 975 /* Extract head of queue */
903 drv_data->cur_msg = list_entry(drv_data->queue.next, 976 drv_data->cur_msg = list_entry(drv_data->queue.next,
904 struct spi_message, queue); 977 struct spi_message, queue);
978
979 /* Setup the SSP using the per chip configuration */
980 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
981 if (restore_state(drv_data)) {
982 spin_unlock_irqrestore(&drv_data->lock, flags);
983 return;
984 };
985
905 list_del_init(&drv_data->cur_msg->queue); 986 list_del_init(&drv_data->cur_msg->queue);
906 987
907 /* Initial message state */ 988 /* Initial message state */
@@ -909,15 +990,12 @@ static void pump_messages(struct work_struct *work)
909 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, 990 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
910 struct spi_transfer, transfer_list); 991 struct spi_transfer, transfer_list);
911 992
912 /* Setup the SSP using the per chip configuration */ 993 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
913 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); 994 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
914 restore_state(drv_data); 995 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
996 drv_data->cur_chip->ctl_reg);
997
915 dev_dbg(&drv_data->pdev->dev, 998 dev_dbg(&drv_data->pdev->dev,
916 "got a message to pump, state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
917 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
918 drv_data->cur_chip->ctl_reg);
919
920 dev_dbg(&drv_data->pdev->dev,
921 "the first transfer len is %d\n", 999 "the first transfer len is %d\n",
922 drv_data->cur_transfer->len); 1000 drv_data->cur_transfer->len);
923 1001
@@ -959,6 +1037,22 @@ static int transfer(struct spi_device *spi, struct spi_message *msg)
959 return 0; 1037 return 0;
960} 1038}
961 1039
1040#define MAX_SPI_SSEL 7
1041
1042static u16 ssel[3][MAX_SPI_SSEL] = {
1043 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1044 P_SPI0_SSEL4, P_SPI0_SSEL5,
1045 P_SPI0_SSEL6, P_SPI0_SSEL7},
1046
1047 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1048 P_SPI1_SSEL4, P_SPI1_SSEL5,
1049 P_SPI1_SSEL6, P_SPI1_SSEL7},
1050
1051 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1052 P_SPI2_SSEL4, P_SPI2_SSEL5,
1053 P_SPI2_SSEL6, P_SPI2_SSEL7},
1054};
1055
962/* first setup for new devices */ 1056/* first setup for new devices */
963static int setup(struct spi_device *spi) 1057static int setup(struct spi_device *spi)
964{ 1058{
@@ -993,6 +1087,18 @@ static int setup(struct spi_device *spi)
993 1087
994 /* chip_info isn't always needed */ 1088 /* chip_info isn't always needed */
995 if (chip_info) { 1089 if (chip_info) {
1090 /* Make sure people stop trying to set fields via ctl_reg
1091 * when they should actually be using common SPI framework.
1092 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1093 * Not sure if a user actually needs/uses any of these,
1094 * but let's assume (for now) they do.
1095 */
1096 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1097 dev_err(&spi->dev, "do not set bits in ctl_reg "
1098 "that the SPI framework manages\n");
1099 return -EINVAL;
1100 }
1101
996 chip->enable_dma = chip_info->enable_dma != 0 1102 chip->enable_dma = chip_info->enable_dma != 0
997 && drv_data->master_info->enable_dma; 1103 && drv_data->master_info->enable_dma;
998 chip->ctl_reg = chip_info->ctl_reg; 1104 chip->ctl_reg = chip_info->ctl_reg;
@@ -1015,20 +1121,20 @@ static int setup(struct spi_device *spi)
1015 * if any one SPI chip is registered and wants DMA, request the 1121 * if any one SPI chip is registered and wants DMA, request the
1016 * DMA channel for it 1122 * DMA channel for it
1017 */ 1123 */
1018 if (chip->enable_dma && !dma_requested) { 1124 if (chip->enable_dma && !drv_data->dma_requested) {
1019 /* register dma irq handler */ 1125 /* register dma irq handler */
1020 if (request_dma(CH_SPI, "BF53x_SPI_DMA") < 0) { 1126 if (request_dma(drv_data->dma_channel, "BF53x_SPI_DMA") < 0) {
1021 dev_dbg(&spi->dev, 1127 dev_dbg(&spi->dev,
1022 "Unable to request BlackFin SPI DMA channel\n"); 1128 "Unable to request BlackFin SPI DMA channel\n");
1023 return -ENODEV; 1129 return -ENODEV;
1024 } 1130 }
1025 if (set_dma_callback(CH_SPI, (void *)dma_irq_handler, drv_data) 1131 if (set_dma_callback(drv_data->dma_channel,
1026 < 0) { 1132 (void *)dma_irq_handler, drv_data) < 0) {
1027 dev_dbg(&spi->dev, "Unable to set dma callback\n"); 1133 dev_dbg(&spi->dev, "Unable to set dma callback\n");
1028 return -EPERM; 1134 return -EPERM;
1029 } 1135 }
1030 dma_disable_irq(CH_SPI); 1136 dma_disable_irq(drv_data->dma_channel);
1031 dma_requested = 1; 1137 drv_data->dma_requested = 1;
1032 } 1138 }
1033 1139
1034 /* 1140 /*
@@ -1077,6 +1183,14 @@ static int setup(struct spi_device *spi)
1077 1183
1078 spi_set_ctldata(spi, chip); 1184 spi_set_ctldata(spi, chip);
1079 1185
1186 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1187 if ((chip->chip_select_num > 0)
1188 && (chip->chip_select_num <= spi->master->num_chipselect))
1189 peripheral_request(ssel[spi->master->bus_num]
1190 [chip->chip_select_num-1], DRV_NAME);
1191
1192 cs_deactive(drv_data, chip);
1193
1080 return 0; 1194 return 0;
1081} 1195}
1082 1196
@@ -1088,6 +1202,11 @@ static void cleanup(struct spi_device *spi)
1088{ 1202{
1089 struct chip_data *chip = spi_get_ctldata(spi); 1203 struct chip_data *chip = spi_get_ctldata(spi);
1090 1204
1205 if ((chip->chip_select_num > 0)
1206 && (chip->chip_select_num <= spi->master->num_chipselect))
1207 peripheral_free(ssel[spi->master->bus_num]
1208 [chip->chip_select_num-1]);
1209
1091 kfree(chip); 1210 kfree(chip);
1092} 1211}
1093 1212
@@ -1183,6 +1302,7 @@ static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1183 struct bfin5xx_spi_master *platform_info; 1302 struct bfin5xx_spi_master *platform_info;
1184 struct spi_master *master; 1303 struct spi_master *master;
1185 struct driver_data *drv_data = 0; 1304 struct driver_data *drv_data = 0;
1305 struct resource *res;
1186 int status = 0; 1306 int status = 0;
1187 1307
1188 platform_info = dev->platform_data; 1308 platform_info = dev->platform_data;
@@ -1193,10 +1313,12 @@ static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1193 dev_err(&pdev->dev, "can not alloc spi_master\n"); 1313 dev_err(&pdev->dev, "can not alloc spi_master\n");
1194 return -ENOMEM; 1314 return -ENOMEM;
1195 } 1315 }
1316
1196 drv_data = spi_master_get_devdata(master); 1317 drv_data = spi_master_get_devdata(master);
1197 drv_data->master = master; 1318 drv_data->master = master;
1198 drv_data->master_info = platform_info; 1319 drv_data->master_info = platform_info;
1199 drv_data->pdev = pdev; 1320 drv_data->pdev = pdev;
1321 drv_data->pin_req = platform_info->pin_req;
1200 1322
1201 master->bus_num = pdev->id; 1323 master->bus_num = pdev->id;
1202 master->num_chipselect = platform_info->num_chipselect; 1324 master->num_chipselect = platform_info->num_chipselect;
@@ -1204,15 +1326,38 @@ static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1204 master->setup = setup; 1326 master->setup = setup;
1205 master->transfer = transfer; 1327 master->transfer = transfer;
1206 1328
1329 /* Find and map our resources */
1330 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1331 if (res == NULL) {
1332 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1333 status = -ENOENT;
1334 goto out_error_get_res;
1335 }
1336
1337 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1338 if (drv_data->regs_base == NULL) {
1339 dev_err(dev, "Cannot map IO\n");
1340 status = -ENXIO;
1341 goto out_error_ioremap;
1342 }
1343
1344 drv_data->dma_channel = platform_get_irq(pdev, 0);
1345 if (drv_data->dma_channel < 0) {
1346 dev_err(dev, "No DMA channel specified\n");
1347 status = -ENOENT;
1348 goto out_error_no_dma_ch;
1349 }
1350
1207 /* Initial and start queue */ 1351 /* Initial and start queue */
1208 status = init_queue(drv_data); 1352 status = init_queue(drv_data);
1209 if (status != 0) { 1353 if (status != 0) {
1210 dev_err(&pdev->dev, "problem initializing queue\n"); 1354 dev_err(dev, "problem initializing queue\n");
1211 goto out_error_queue_alloc; 1355 goto out_error_queue_alloc;
1212 } 1356 }
1357
1213 status = start_queue(drv_data); 1358 status = start_queue(drv_data);
1214 if (status != 0) { 1359 if (status != 0) {
1215 dev_err(&pdev->dev, "problem starting queue\n"); 1360 dev_err(dev, "problem starting queue\n");
1216 goto out_error_queue_alloc; 1361 goto out_error_queue_alloc;
1217 } 1362 }
1218 1363
@@ -1220,15 +1365,30 @@ static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1220 platform_set_drvdata(pdev, drv_data); 1365 platform_set_drvdata(pdev, drv_data);
1221 status = spi_register_master(master); 1366 status = spi_register_master(master);
1222 if (status != 0) { 1367 if (status != 0) {
1223 dev_err(&pdev->dev, "problem registering spi master\n"); 1368 dev_err(dev, "problem registering spi master\n");
1224 goto out_error_queue_alloc; 1369 goto out_error_queue_alloc;
1225 } 1370 }
1226 dev_dbg(&pdev->dev, "controller probe successfully\n"); 1371
1372 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1373 if (status != 0) {
1374 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1375 goto out_error;
1376 }
1377
1378 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1379 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1380 drv_data->dma_channel);
1227 return status; 1381 return status;
1228 1382
1229 out_error_queue_alloc: 1383out_error_queue_alloc:
1230 destroy_queue(drv_data); 1384 destroy_queue(drv_data);
1385out_error_no_dma_ch:
1386 iounmap((void *) drv_data->regs_base);
1387out_error_ioremap:
1388out_error_get_res:
1389out_error:
1231 spi_master_put(master); 1390 spi_master_put(master);
1391
1232 return status; 1392 return status;
1233} 1393}
1234 1394
@@ -1251,13 +1411,15 @@ static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1251 1411
1252 /* Release DMA */ 1412 /* Release DMA */
1253 if (drv_data->master_info->enable_dma) { 1413 if (drv_data->master_info->enable_dma) {
1254 if (dma_channel_active(CH_SPI)) 1414 if (dma_channel_active(drv_data->dma_channel))
1255 free_dma(CH_SPI); 1415 free_dma(drv_data->dma_channel);
1256 } 1416 }
1257 1417
1258 /* Disconnect from the SPI framework */ 1418 /* Disconnect from the SPI framework */
1259 spi_unregister_master(drv_data->master); 1419 spi_unregister_master(drv_data->master);
1260 1420
1421 peripheral_free_list(drv_data->pin_req);
1422
1261 /* Prevent double remove */ 1423 /* Prevent double remove */
1262 platform_set_drvdata(pdev, NULL); 1424 platform_set_drvdata(pdev, NULL);
1263 1425
@@ -1305,7 +1467,7 @@ static int bfin5xx_spi_resume(struct platform_device *pdev)
1305MODULE_ALIAS("bfin-spi-master"); /* for platform bus hotplug */ 1467MODULE_ALIAS("bfin-spi-master"); /* for platform bus hotplug */
1306static struct platform_driver bfin5xx_spi_driver = { 1468static struct platform_driver bfin5xx_spi_driver = {
1307 .driver = { 1469 .driver = {
1308 .name = "bfin-spi-master", 1470 .name = DRV_NAME,
1309 .owner = THIS_MODULE, 1471 .owner = THIS_MODULE,
1310 }, 1472 },
1311 .suspend = bfin5xx_spi_suspend, 1473 .suspend = bfin5xx_spi_suspend,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 08:56:54 -0500