diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/bnx2x_link.c | 35 | ||||
-rw-r--r-- | drivers/net/bnx2x_reg.h | 4 |
2 files changed, 33 insertions, 6 deletions
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c index f4c699ecfb41..2463de8fe862 100644 --- a/drivers/net/bnx2x_link.c +++ b/drivers/net/bnx2x_link.c | |||
@@ -174,13 +174,34 @@ | |||
174 | (_bank + (_addr & 0xf)), \ | 174 | (_bank + (_addr & 0xf)), \ |
175 | _val) | 175 | _val) |
176 | 176 | ||
177 | static void bnx2x_set_phy_mdio(struct link_params *params) | 177 | static void bnx2x_set_serdes_access(struct link_params *params) |
178 | { | 178 | { |
179 | struct bnx2x *bp = params->bp; | 179 | struct bnx2x *bp = params->bp; |
180 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + | 180 | u32 emac_base = (params->port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
181 | params->port*0x18, 0); | 181 | /* Set Clause 22 */ |
182 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, | 182 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 1); |
183 | DEFAULT_PHY_DEV_ADDR); | 183 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); |
184 | udelay(500); | ||
185 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); | ||
186 | udelay(500); | ||
187 | /* Set Clause 45 */ | ||
188 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 0); | ||
189 | } | ||
190 | static void bnx2x_set_phy_mdio(struct link_params *params, u8 phy_flags) | ||
191 | { | ||
192 | struct bnx2x *bp = params->bp; | ||
193 | if (phy_flags & PHY_XGXS_FLAG) { | ||
194 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + | ||
195 | params->port*0x18, 0); | ||
196 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, | ||
197 | DEFAULT_PHY_DEV_ADDR); | ||
198 | } else { | ||
199 | bnx2x_set_serdes_access(params); | ||
200 | |||
201 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + | ||
202 | params->port*0x10, | ||
203 | DEFAULT_PHY_DEV_ADDR); | ||
204 | } | ||
184 | } | 205 | } |
185 | 206 | ||
186 | static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) | 207 | static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) |
@@ -520,7 +541,7 @@ static void bnx2x_phy_deassert(struct link_params *params, u8 phy_flags) | |||
520 | udelay(500); | 541 | udelay(500); |
521 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, | 542 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, |
522 | val); | 543 | val); |
523 | bnx2x_set_phy_mdio(params); | 544 | bnx2x_set_phy_mdio(params, phy_flags); |
524 | } | 545 | } |
525 | 546 | ||
526 | void bnx2x_link_status_update(struct link_params *params, | 547 | void bnx2x_link_status_update(struct link_params *params, |
@@ -996,6 +1017,8 @@ static u8 bnx2x_reset_unicore(struct link_params *params) | |||
996 | (mii_control | | 1017 | (mii_control | |
997 | MDIO_COMBO_IEEO_MII_CONTROL_RESET)); | 1018 | MDIO_COMBO_IEEO_MII_CONTROL_RESET)); |
998 | 1019 | ||
1020 | bnx2x_set_serdes_access(params); | ||
1021 | |||
999 | /* wait for the reset to self clear */ | 1022 | /* wait for the reset to self clear */ |
1000 | for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { | 1023 | for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { |
1001 | udelay(5); | 1024 | udelay(5); |
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h index b6c924934a00..d3086e924709 100644 --- a/drivers/net/bnx2x_reg.h +++ b/drivers/net/bnx2x_reg.h | |||
@@ -1815,6 +1815,10 @@ | |||
1815 | #define NIG_REG_PRS_EOP_OUT_EN 0x10104 | 1815 | #define NIG_REG_PRS_EOP_OUT_EN 0x10104 |
1816 | /* [RW 1] Input enable for RX parser request IF */ | 1816 | /* [RW 1] Input enable for RX parser request IF */ |
1817 | #define NIG_REG_PRS_REQ_IN_EN 0x100b8 | 1817 | #define NIG_REG_PRS_REQ_IN_EN 0x100b8 |
1818 | /* [RW 5] control to serdes - CL45 DEVAD */ | ||
1819 | #define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370 | ||
1820 | /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */ | ||
1821 | #define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c | ||
1818 | /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */ | 1822 | /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */ |
1819 | #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374 | 1823 | #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374 |
1820 | /* [R 1] status from serdes0 that inputs to interrupt logic of link status */ | 1824 | /* [R 1] status from serdes0 that inputs to interrupt logic of link status */ |