diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/media/common/tuners/mxl5007t.c | 268 |
1 files changed, 135 insertions, 133 deletions
diff --git a/drivers/media/common/tuners/mxl5007t.c b/drivers/media/common/tuners/mxl5007t.c index b13de8c4662a..2d02698d4f4f 100644 --- a/drivers/media/common/tuners/mxl5007t.c +++ b/drivers/media/common/tuners/mxl5007t.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * mxl5007t.c - driver for the MaxLinear MxL5007T silicon tuner | 2 | * mxl5007t.c - driver for the MaxLinear MxL5007T silicon tuner |
3 | * | 3 | * |
4 | * Copyright (C) 2008 Michael Krufky <mkrufky@linuxtv.org> | 4 | * Copyright (C) 2008, 2009 Michael Krufky <mkrufky@linuxtv.org> |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License as published by | 7 | * it under the terms of the GNU General Public License as published by |
@@ -66,15 +66,17 @@ MODULE_PARM_DESC(debug, "set debug level"); | |||
66 | #define MHz 1000000 | 66 | #define MHz 1000000 |
67 | 67 | ||
68 | enum mxl5007t_mode { | 68 | enum mxl5007t_mode { |
69 | MxL_MODE_OTA_DVBT_ATSC = 0, | 69 | MxL_MODE_ISDBT = 0, |
70 | MxL_MODE_OTA_ISDBT = 4, | 70 | MxL_MODE_DVBT = 1, |
71 | MxL_MODE_CABLE_DIGITAL = 0x10, | 71 | MxL_MODE_ATSC = 2, |
72 | MxL_MODE_CABLE = 0x10, | ||
72 | }; | 73 | }; |
73 | 74 | ||
74 | enum mxl5007t_chip_version { | 75 | enum mxl5007t_chip_version { |
75 | MxL_UNKNOWN_ID = 0x00, | 76 | MxL_UNKNOWN_ID = 0x00, |
76 | MxL_5007_V1_F1 = 0x11, | 77 | MxL_5007_V1_F1 = 0x11, |
77 | MxL_5007_V1_F2 = 0x12, | 78 | MxL_5007_V1_F2 = 0x12, |
79 | MxL_5007_V4 = 0x14, | ||
78 | MxL_5007_V2_100_F1 = 0x21, | 80 | MxL_5007_V2_100_F1 = 0x21, |
79 | MxL_5007_V2_100_F2 = 0x22, | 81 | MxL_5007_V2_100_F2 = 0x22, |
80 | MxL_5007_V2_200_F1 = 0x23, | 82 | MxL_5007_V2_200_F1 = 0x23, |
@@ -89,67 +91,61 @@ struct reg_pair_t { | |||
89 | /* ------------------------------------------------------------------------- */ | 91 | /* ------------------------------------------------------------------------- */ |
90 | 92 | ||
91 | static struct reg_pair_t init_tab[] = { | 93 | static struct reg_pair_t init_tab[] = { |
92 | { 0x0b, 0x44 }, /* XTAL */ | 94 | { 0x02, 0x06 }, |
93 | { 0x0c, 0x60 }, /* IF */ | 95 | { 0x03, 0x48 }, |
94 | { 0x10, 0x00 }, /* MISC */ | 96 | { 0x05, 0x04 }, |
95 | { 0x12, 0xca }, /* IDAC */ | 97 | { 0x06, 0x10 }, |
96 | { 0x16, 0x90 }, /* MODE */ | 98 | { 0x2e, 0x15 }, /* OVERRIDE */ |
97 | { 0x32, 0x38 }, /* MODE Analog/Digital */ | 99 | { 0x30, 0x10 }, /* OVERRIDE */ |
98 | { 0xd8, 0x18 }, /* CLK_OUT_ENABLE */ | 100 | { 0x45, 0x58 }, /* OVERRIDE */ |
99 | { 0x2c, 0x34 }, /* OVERRIDE */ | 101 | { 0x48, 0x19 }, /* OVERRIDE */ |
100 | { 0x4d, 0x40 }, /* OVERRIDE */ | 102 | { 0x52, 0x03 }, /* OVERRIDE */ |
101 | { 0x7f, 0x02 }, /* OVERRIDE */ | 103 | { 0x53, 0x44 }, /* OVERRIDE */ |
102 | { 0x9a, 0x52 }, /* OVERRIDE */ | 104 | { 0x6a, 0x4b }, /* OVERRIDE */ |
103 | { 0x48, 0x5a }, /* OVERRIDE */ | 105 | { 0x76, 0x00 }, /* OVERRIDE */ |
104 | { 0x76, 0x1a }, /* OVERRIDE */ | 106 | { 0x78, 0x18 }, /* OVERRIDE */ |
105 | { 0x6a, 0x48 }, /* OVERRIDE */ | 107 | { 0x7a, 0x17 }, /* OVERRIDE */ |
106 | { 0x64, 0x28 }, /* OVERRIDE */ | 108 | { 0x85, 0x06 }, /* OVERRIDE */ |
107 | { 0x66, 0xe6 }, /* OVERRIDE */ | 109 | { 0x01, 0x01 }, /* TOP_MASTER_ENABLE */ |
108 | { 0x35, 0x0e }, /* OVERRIDE */ | ||
109 | { 0x7e, 0x01 }, /* OVERRIDE */ | ||
110 | { 0x83, 0x00 }, /* OVERRIDE */ | ||
111 | { 0x04, 0x0b }, /* OVERRIDE */ | ||
112 | { 0x05, 0x01 }, /* TOP_MASTER_ENABLE */ | ||
113 | { 0, 0 } | 110 | { 0, 0 } |
114 | }; | 111 | }; |
115 | 112 | ||
116 | static struct reg_pair_t init_tab_cable[] = { | 113 | static struct reg_pair_t init_tab_cable[] = { |
117 | { 0x0b, 0x44 }, /* XTAL */ | 114 | { 0x02, 0x06 }, |
118 | { 0x0c, 0x60 }, /* IF */ | 115 | { 0x03, 0x48 }, |
119 | { 0x10, 0x00 }, /* MISC */ | 116 | { 0x05, 0x04 }, |
120 | { 0x12, 0xca }, /* IDAC */ | 117 | { 0x06, 0x10 }, |
121 | { 0x16, 0x90 }, /* MODE */ | 118 | { 0x09, 0x3f }, |
122 | { 0x32, 0x38 }, /* MODE A/D */ | 119 | { 0x0a, 0x3f }, |
123 | { 0x71, 0x3f }, /* TOP1 */ | 120 | { 0x0b, 0x3f }, |
124 | { 0x72, 0x3f }, /* TOP2 */ | 121 | { 0x2e, 0x15 }, /* OVERRIDE */ |
125 | { 0x74, 0x3f }, /* TOP3 */ | 122 | { 0x30, 0x10 }, /* OVERRIDE */ |
126 | { 0xd8, 0x18 }, /* CLK_OUT_ENABLE */ | 123 | { 0x45, 0x58 }, /* OVERRIDE */ |
127 | { 0x2c, 0x34 }, /* OVERRIDE */ | 124 | { 0x48, 0x19 }, /* OVERRIDE */ |
128 | { 0x4d, 0x40 }, /* OVERRIDE */ | 125 | { 0x52, 0x03 }, /* OVERRIDE */ |
129 | { 0x7f, 0x02 }, /* OVERRIDE */ | 126 | { 0x53, 0x44 }, /* OVERRIDE */ |
130 | { 0x9a, 0x52 }, /* OVERRIDE */ | 127 | { 0x6a, 0x4b }, /* OVERRIDE */ |
131 | { 0x48, 0x5a }, /* OVERRIDE */ | 128 | { 0x76, 0x00 }, /* OVERRIDE */ |
132 | { 0x76, 0x1a }, /* OVERRIDE */ | 129 | { 0x78, 0x18 }, /* OVERRIDE */ |
133 | { 0x6a, 0x48 }, /* OVERRIDE */ | 130 | { 0x7a, 0x17 }, /* OVERRIDE */ |
134 | { 0x64, 0x28 }, /* OVERRIDE */ | 131 | { 0x85, 0x06 }, /* OVERRIDE */ |
135 | { 0x66, 0xe6 }, /* OVERRIDE */ | 132 | { 0x01, 0x01 }, /* TOP_MASTER_ENABLE */ |
136 | { 0x35, 0x0e }, /* OVERRIDE */ | ||
137 | { 0x7e, 0x01 }, /* OVERRIDE */ | ||
138 | { 0x04, 0x0b }, /* OVERRIDE */ | ||
139 | { 0x68, 0xb4 }, /* OVERRIDE */ | ||
140 | { 0x36, 0x00 }, /* OVERRIDE */ | ||
141 | { 0x05, 0x01 }, /* TOP_MASTER_ENABLE */ | ||
142 | { 0, 0 } | 133 | { 0, 0 } |
143 | }; | 134 | }; |
144 | 135 | ||
145 | /* ------------------------------------------------------------------------- */ | 136 | /* ------------------------------------------------------------------------- */ |
146 | 137 | ||
147 | static struct reg_pair_t reg_pair_rftune[] = { | 138 | static struct reg_pair_t reg_pair_rftune[] = { |
148 | { 0x11, 0x00 }, /* abort tune */ | 139 | { 0x0f, 0x00 }, /* abort tune */ |
149 | { 0x13, 0x15 }, | 140 | { 0x0c, 0x15 }, |
150 | { 0x14, 0x40 }, | 141 | { 0x0d, 0x40 }, |
151 | { 0x15, 0x0e }, | 142 | { 0x0e, 0x0e }, |
152 | { 0x11, 0x02 }, /* start tune */ | 143 | { 0x1f, 0x87 }, /* OVERRIDE */ |
144 | { 0x20, 0x1f }, /* OVERRIDE */ | ||
145 | { 0x21, 0x87 }, /* OVERRIDE */ | ||
146 | { 0x22, 0x1f }, /* OVERRIDE */ | ||
147 | { 0x80, 0x01 }, /* freq dependent */ | ||
148 | { 0x0f, 0x01 }, /* start tune */ | ||
153 | { 0, 0 } | 149 | { 0, 0 } |
154 | }; | 150 | }; |
155 | 151 | ||
@@ -220,19 +216,20 @@ static void mxl5007t_set_mode_bits(struct mxl5007t_state *state, | |||
220 | s32 if_diff_out_level) | 216 | s32 if_diff_out_level) |
221 | { | 217 | { |
222 | switch (mode) { | 218 | switch (mode) { |
223 | case MxL_MODE_OTA_DVBT_ATSC: | 219 | case MxL_MODE_ATSC: |
224 | set_reg_bits(state->tab_init, 0x32, 0x0f, 0x06); | 220 | set_reg_bits(state->tab_init, 0x06, 0x1f, 0x12); |
225 | set_reg_bits(state->tab_init, 0x35, 0xff, 0x0e); | ||
226 | break; | 221 | break; |
227 | case MxL_MODE_OTA_ISDBT: | 222 | case MxL_MODE_DVBT: |
228 | set_reg_bits(state->tab_init, 0x32, 0x0f, 0x06); | 223 | set_reg_bits(state->tab_init, 0x06, 0x1f, 0x11); |
229 | set_reg_bits(state->tab_init, 0x35, 0xff, 0x12); | ||
230 | break; | 224 | break; |
231 | case MxL_MODE_CABLE_DIGITAL: | 225 | case MxL_MODE_ISDBT: |
232 | set_reg_bits(state->tab_init_cable, 0x71, 0xff, 0x01); | 226 | set_reg_bits(state->tab_init, 0x06, 0x1f, 0x10); |
233 | set_reg_bits(state->tab_init_cable, 0x72, 0xff, | 227 | break; |
228 | case MxL_MODE_CABLE: | ||
229 | set_reg_bits(state->tab_init_cable, 0x09, 0xff, 0xc1); | ||
230 | set_reg_bits(state->tab_init_cable, 0x0a, 0xff, | ||
234 | 8 - if_diff_out_level); | 231 | 8 - if_diff_out_level); |
235 | set_reg_bits(state->tab_init_cable, 0x74, 0xff, 0x17); | 232 | set_reg_bits(state->tab_init_cable, 0x0b, 0xff, 0x17); |
236 | break; | 233 | break; |
237 | default: | 234 | default: |
238 | mxl_fail(-EINVAL); | 235 | mxl_fail(-EINVAL); |
@@ -251,43 +248,43 @@ static void mxl5007t_set_if_freq_bits(struct mxl5007t_state *state, | |||
251 | val = 0x00; | 248 | val = 0x00; |
252 | break; | 249 | break; |
253 | case MxL_IF_4_5_MHZ: | 250 | case MxL_IF_4_5_MHZ: |
254 | val = 0x20; | 251 | val = 0x02; |
255 | break; | 252 | break; |
256 | case MxL_IF_4_57_MHZ: | 253 | case MxL_IF_4_57_MHZ: |
257 | val = 0x30; | 254 | val = 0x03; |
258 | break; | 255 | break; |
259 | case MxL_IF_5_MHZ: | 256 | case MxL_IF_5_MHZ: |
260 | val = 0x40; | 257 | val = 0x04; |
261 | break; | 258 | break; |
262 | case MxL_IF_5_38_MHZ: | 259 | case MxL_IF_5_38_MHZ: |
263 | val = 0x50; | 260 | val = 0x05; |
264 | break; | 261 | break; |
265 | case MxL_IF_6_MHZ: | 262 | case MxL_IF_6_MHZ: |
266 | val = 0x60; | 263 | val = 0x06; |
267 | break; | 264 | break; |
268 | case MxL_IF_6_28_MHZ: | 265 | case MxL_IF_6_28_MHZ: |
269 | val = 0x70; | 266 | val = 0x07; |
270 | break; | 267 | break; |
271 | case MxL_IF_9_1915_MHZ: | 268 | case MxL_IF_9_1915_MHZ: |
272 | val = 0x80; | 269 | val = 0x08; |
273 | break; | 270 | break; |
274 | case MxL_IF_35_25_MHZ: | 271 | case MxL_IF_35_25_MHZ: |
275 | val = 0x90; | 272 | val = 0x09; |
276 | break; | 273 | break; |
277 | case MxL_IF_36_15_MHZ: | 274 | case MxL_IF_36_15_MHZ: |
278 | val = 0xa0; | 275 | val = 0x0a; |
279 | break; | 276 | break; |
280 | case MxL_IF_44_MHZ: | 277 | case MxL_IF_44_MHZ: |
281 | val = 0xb0; | 278 | val = 0x0b; |
282 | break; | 279 | break; |
283 | default: | 280 | default: |
284 | mxl_fail(-EINVAL); | 281 | mxl_fail(-EINVAL); |
285 | return; | 282 | return; |
286 | } | 283 | } |
287 | set_reg_bits(state->tab_init, 0x0c, 0xf0, val); | 284 | set_reg_bits(state->tab_init, 0x02, 0x0f, val); |
288 | 285 | ||
289 | /* set inverted IF or normal IF */ | 286 | /* set inverted IF or normal IF */ |
290 | set_reg_bits(state->tab_init, 0x0c, 0x08, invert_if ? 0x08 : 0x00); | 287 | set_reg_bits(state->tab_init, 0x02, 0x10, invert_if ? 0x10 : 0x00); |
291 | 288 | ||
292 | return; | 289 | return; |
293 | } | 290 | } |
@@ -295,56 +292,68 @@ static void mxl5007t_set_if_freq_bits(struct mxl5007t_state *state, | |||
295 | static void mxl5007t_set_xtal_freq_bits(struct mxl5007t_state *state, | 292 | static void mxl5007t_set_xtal_freq_bits(struct mxl5007t_state *state, |
296 | enum mxl5007t_xtal_freq xtal_freq) | 293 | enum mxl5007t_xtal_freq xtal_freq) |
297 | { | 294 | { |
298 | u8 val; | ||
299 | |||
300 | switch (xtal_freq) { | 295 | switch (xtal_freq) { |
301 | case MxL_XTAL_16_MHZ: | 296 | case MxL_XTAL_16_MHZ: |
302 | val = 0x00; /* select xtal freq & Ref Freq */ | 297 | /* select xtal freq & ref freq */ |
298 | set_reg_bits(state->tab_init, 0x03, 0xf0, 0x00); | ||
299 | set_reg_bits(state->tab_init, 0x05, 0x0f, 0x00); | ||
303 | break; | 300 | break; |
304 | case MxL_XTAL_20_MHZ: | 301 | case MxL_XTAL_20_MHZ: |
305 | val = 0x11; | 302 | set_reg_bits(state->tab_init, 0x03, 0xf0, 0x10); |
303 | set_reg_bits(state->tab_init, 0x05, 0x0f, 0x01); | ||
306 | break; | 304 | break; |
307 | case MxL_XTAL_20_25_MHZ: | 305 | case MxL_XTAL_20_25_MHZ: |
308 | val = 0x22; | 306 | set_reg_bits(state->tab_init, 0x03, 0xf0, 0x20); |
307 | set_reg_bits(state->tab_init, 0x05, 0x0f, 0x02); | ||
309 | break; | 308 | break; |
310 | case MxL_XTAL_20_48_MHZ: | 309 | case MxL_XTAL_20_48_MHZ: |
311 | val = 0x33; | 310 | set_reg_bits(state->tab_init, 0x03, 0xf0, 0x30); |
311 | set_reg_bits(state->tab_init, 0x05, 0x0f, 0x03); | ||
312 | break; | 312 | break; |
313 | case MxL_XTAL_24_MHZ: | 313 | case MxL_XTAL_24_MHZ: |
314 | val = 0x44; | 314 | set_reg_bits(state->tab_init, 0x03, 0xf0, 0x40); |
315 | set_reg_bits(state->tab_init, 0x05, 0x0f, 0x04); | ||
315 | break; | 316 | break; |
316 | case MxL_XTAL_25_MHZ: | 317 | case MxL_XTAL_25_MHZ: |
317 | val = 0x55; | 318 | set_reg_bits(state->tab_init, 0x03, 0xf0, 0x50); |
319 | set_reg_bits(state->tab_init, 0x05, 0x0f, 0x05); | ||
318 | break; | 320 | break; |
319 | case MxL_XTAL_25_14_MHZ: | 321 | case MxL_XTAL_25_14_MHZ: |
320 | val = 0x66; | 322 | set_reg_bits(state->tab_init, 0x03, 0xf0, 0x60); |
323 | set_reg_bits(state->tab_init, 0x05, 0x0f, 0x06); | ||
321 | break; | 324 | break; |
322 | case MxL_XTAL_27_MHZ: | 325 | case MxL_XTAL_27_MHZ: |
323 | val = 0x77; | 326 | set_reg_bits(state->tab_init, 0x03, 0xf0, 0x70); |
327 | set_reg_bits(state->tab_init, 0x05, 0x0f, 0x07); | ||
324 | break; | 328 | break; |
325 | case MxL_XTAL_28_8_MHZ: | 329 | case MxL_XTAL_28_8_MHZ: |
326 | val = 0x88; | 330 | set_reg_bits(state->tab_init, 0x03, 0xf0, 0x80); |
331 | set_reg_bits(state->tab_init, 0x05, 0x0f, 0x08); | ||
327 | break; | 332 | break; |
328 | case MxL_XTAL_32_MHZ: | 333 | case MxL_XTAL_32_MHZ: |
329 | val = 0x99; | 334 | set_reg_bits(state->tab_init, 0x03, 0xf0, 0x90); |
335 | set_reg_bits(state->tab_init, 0x05, 0x0f, 0x09); | ||
330 | break; | 336 | break; |
331 | case MxL_XTAL_40_MHZ: | 337 | case MxL_XTAL_40_MHZ: |
332 | val = 0xaa; | 338 | set_reg_bits(state->tab_init, 0x03, 0xf0, 0xa0); |
339 | set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0a); | ||
333 | break; | 340 | break; |
334 | case MxL_XTAL_44_MHZ: | 341 | case MxL_XTAL_44_MHZ: |
335 | val = 0xbb; | 342 | set_reg_bits(state->tab_init, 0x03, 0xf0, 0xb0); |
343 | set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0b); | ||
336 | break; | 344 | break; |
337 | case MxL_XTAL_48_MHZ: | 345 | case MxL_XTAL_48_MHZ: |
338 | val = 0xcc; | 346 | set_reg_bits(state->tab_init, 0x03, 0xf0, 0xc0); |
347 | set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0c); | ||
339 | break; | 348 | break; |
340 | case MxL_XTAL_49_3811_MHZ: | 349 | case MxL_XTAL_49_3811_MHZ: |
341 | val = 0xdd; | 350 | set_reg_bits(state->tab_init, 0x03, 0xf0, 0xd0); |
351 | set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0d); | ||
342 | break; | 352 | break; |
343 | default: | 353 | default: |
344 | mxl_fail(-EINVAL); | 354 | mxl_fail(-EINVAL); |
345 | return; | 355 | return; |
346 | } | 356 | } |
347 | set_reg_bits(state->tab_init, 0x0b, 0xff, val); | ||
348 | 357 | ||
349 | return; | 358 | return; |
350 | } | 359 | } |
@@ -361,16 +370,11 @@ static struct reg_pair_t *mxl5007t_calc_init_regs(struct mxl5007t_state *state, | |||
361 | mxl5007t_set_if_freq_bits(state, cfg->if_freq_hz, cfg->invert_if); | 370 | mxl5007t_set_if_freq_bits(state, cfg->if_freq_hz, cfg->invert_if); |
362 | mxl5007t_set_xtal_freq_bits(state, cfg->xtal_freq_hz); | 371 | mxl5007t_set_xtal_freq_bits(state, cfg->xtal_freq_hz); |
363 | 372 | ||
364 | set_reg_bits(state->tab_init, 0x10, 0x40, cfg->loop_thru_enable << 6); | 373 | set_reg_bits(state->tab_init, 0x04, 0x01, cfg->loop_thru_enable); |
365 | 374 | set_reg_bits(state->tab_init, 0x03, 0x08, cfg->clk_out_enable << 3); | |
366 | set_reg_bits(state->tab_init, 0xd8, 0x08, cfg->clk_out_enable << 3); | 375 | set_reg_bits(state->tab_init, 0x03, 0x07, cfg->clk_out_amp); |
367 | 376 | ||
368 | set_reg_bits(state->tab_init, 0x10, 0x07, cfg->clk_out_amp); | 377 | if (mode >= MxL_MODE_CABLE) { |
369 | |||
370 | /* set IDAC to automatic mode control by AGC */ | ||
371 | set_reg_bits(state->tab_init, 0x12, 0x80, 0x00); | ||
372 | |||
373 | if (mode >= MxL_MODE_CABLE_DIGITAL) { | ||
374 | copy_reg_bits(state->tab_init, state->tab_init_cable); | 378 | copy_reg_bits(state->tab_init, state->tab_init_cable); |
375 | return state->tab_init_cable; | 379 | return state->tab_init_cable; |
376 | } else | 380 | } else |
@@ -396,7 +400,7 @@ static void mxl5007t_set_bw_bits(struct mxl5007t_state *state, | |||
396 | * and DIG_MODEINDEX_CSF */ | 400 | * and DIG_MODEINDEX_CSF */ |
397 | break; | 401 | break; |
398 | case MxL_BW_7MHz: | 402 | case MxL_BW_7MHz: |
399 | val = 0x21; | 403 | val = 0x2a; |
400 | break; | 404 | break; |
401 | case MxL_BW_8MHz: | 405 | case MxL_BW_8MHz: |
402 | val = 0x3f; | 406 | val = 0x3f; |
@@ -405,7 +409,7 @@ static void mxl5007t_set_bw_bits(struct mxl5007t_state *state, | |||
405 | mxl_fail(-EINVAL); | 409 | mxl_fail(-EINVAL); |
406 | return; | 410 | return; |
407 | } | 411 | } |
408 | set_reg_bits(state->tab_rftune, 0x13, 0x3f, val); | 412 | set_reg_bits(state->tab_rftune, 0x0c, 0x3f, val); |
409 | 413 | ||
410 | return; | 414 | return; |
411 | } | 415 | } |
@@ -442,8 +446,11 @@ reg_pair_t *mxl5007t_calc_rf_tune_regs(struct mxl5007t_state *state, | |||
442 | if (temp > 7812) | 446 | if (temp > 7812) |
443 | dig_rf_freq++; | 447 | dig_rf_freq++; |
444 | 448 | ||
445 | set_reg_bits(state->tab_rftune, 0x14, 0xff, (u8)dig_rf_freq); | 449 | set_reg_bits(state->tab_rftune, 0x0d, 0xff, (u8) dig_rf_freq); |
446 | set_reg_bits(state->tab_rftune, 0x15, 0xff, (u8)(dig_rf_freq >> 8)); | 450 | set_reg_bits(state->tab_rftune, 0x0e, 0xff, (u8) (dig_rf_freq >> 8)); |
451 | |||
452 | if (rf_freq >= 333000000) | ||
453 | set_reg_bits(state->tab_rftune, 0x80, 0x40, 0x40); | ||
447 | 454 | ||
448 | return state->tab_rftune; | 455 | return state->tab_rftune; |
449 | } | 456 | } |
@@ -500,9 +507,10 @@ static int mxl5007t_read_reg(struct mxl5007t_state *state, u8 reg, u8 *val) | |||
500 | static int mxl5007t_soft_reset(struct mxl5007t_state *state) | 507 | static int mxl5007t_soft_reset(struct mxl5007t_state *state) |
501 | { | 508 | { |
502 | u8 d = 0xff; | 509 | u8 d = 0xff; |
503 | struct i2c_msg msg = { .addr = state->i2c_props.addr, .flags = 0, | 510 | struct i2c_msg msg = { |
504 | .buf = &d, .len = 1 }; | 511 | .addr = state->i2c_props.addr, .flags = 0, |
505 | 512 | .buf = &d, .len = 1 | |
513 | }; | ||
506 | int ret = i2c_transfer(state->i2c_props.adap, &msg, 1); | 514 | int ret = i2c_transfer(state->i2c_props.adap, &msg, 1); |
507 | 515 | ||
508 | if (ret != 1) { | 516 | if (ret != 1) { |
@@ -529,9 +537,6 @@ static int mxl5007t_tuner_init(struct mxl5007t_state *state, | |||
529 | if (mxl_fail(ret)) | 537 | if (mxl_fail(ret)) |
530 | goto fail; | 538 | goto fail; |
531 | mdelay(1); | 539 | mdelay(1); |
532 | |||
533 | ret = mxl5007t_write_reg(state, 0x2c, 0x35); | ||
534 | mxl_fail(ret); | ||
535 | fail: | 540 | fail: |
536 | return ret; | 541 | return ret; |
537 | } | 542 | } |
@@ -564,7 +569,7 @@ static int mxl5007t_synth_lock_status(struct mxl5007t_state *state, | |||
564 | *rf_locked = 0; | 569 | *rf_locked = 0; |
565 | *ref_locked = 0; | 570 | *ref_locked = 0; |
566 | 571 | ||
567 | ret = mxl5007t_read_reg(state, 0xcf, &d); | 572 | ret = mxl5007t_read_reg(state, 0xd8, &d); |
568 | if (mxl_fail(ret)) | 573 | if (mxl_fail(ret)) |
569 | goto fail; | 574 | goto fail; |
570 | 575 | ||
@@ -619,11 +624,11 @@ static int mxl5007t_set_params(struct dvb_frontend *fe, | |||
619 | switch (params->u.vsb.modulation) { | 624 | switch (params->u.vsb.modulation) { |
620 | case VSB_8: | 625 | case VSB_8: |
621 | case VSB_16: | 626 | case VSB_16: |
622 | mode = MxL_MODE_OTA_DVBT_ATSC; | 627 | mode = MxL_MODE_ATSC; |
623 | break; | 628 | break; |
624 | case QAM_64: | 629 | case QAM_64: |
625 | case QAM_256: | 630 | case QAM_256: |
626 | mode = MxL_MODE_CABLE_DIGITAL; | 631 | mode = MxL_MODE_CABLE; |
627 | break; | 632 | break; |
628 | default: | 633 | default: |
629 | mxl_err("modulation not set!"); | 634 | mxl_err("modulation not set!"); |
@@ -645,7 +650,7 @@ static int mxl5007t_set_params(struct dvb_frontend *fe, | |||
645 | mxl_err("bandwidth not set!"); | 650 | mxl_err("bandwidth not set!"); |
646 | return -EINVAL; | 651 | return -EINVAL; |
647 | } | 652 | } |
648 | mode = MxL_MODE_OTA_DVBT_ATSC; | 653 | mode = MxL_MODE_DVBT; |
649 | } else { | 654 | } else { |
650 | mxl_err("modulation type not supported!"); | 655 | mxl_err("modulation type not supported!"); |
651 | return -EINVAL; | 656 | return -EINVAL; |
@@ -682,18 +687,14 @@ static int mxl5007t_init(struct dvb_frontend *fe) | |||
682 | { | 687 | { |
683 | struct mxl5007t_state *state = fe->tuner_priv; | 688 | struct mxl5007t_state *state = fe->tuner_priv; |
684 | int ret; | 689 | int ret; |
685 | u8 d; | ||
686 | 690 | ||
687 | if (fe->ops.i2c_gate_ctrl) | 691 | if (fe->ops.i2c_gate_ctrl) |
688 | fe->ops.i2c_gate_ctrl(fe, 1); | 692 | fe->ops.i2c_gate_ctrl(fe, 1); |
689 | 693 | ||
690 | ret = mxl5007t_read_reg(state, 0x05, &d); | 694 | /* wake from standby */ |
691 | if (mxl_fail(ret)) | 695 | ret = mxl5007t_write_reg(state, 0x01, 0x01); |
692 | goto fail; | ||
693 | |||
694 | ret = mxl5007t_write_reg(state, 0x05, d | 0x01); | ||
695 | mxl_fail(ret); | 696 | mxl_fail(ret); |
696 | fail: | 697 | |
697 | if (fe->ops.i2c_gate_ctrl) | 698 | if (fe->ops.i2c_gate_ctrl) |
698 | fe->ops.i2c_gate_ctrl(fe, 0); | 699 | fe->ops.i2c_gate_ctrl(fe, 0); |
699 | 700 | ||
@@ -704,18 +705,16 @@ static int mxl5007t_sleep(struct dvb_frontend *fe) | |||
704 | { | 705 | { |
705 | struct mxl5007t_state *state = fe->tuner_priv; | 706 | struct mxl5007t_state *state = fe->tuner_priv; |
706 | int ret; | 707 | int ret; |
707 | u8 d; | ||
708 | 708 | ||
709 | if (fe->ops.i2c_gate_ctrl) | 709 | if (fe->ops.i2c_gate_ctrl) |
710 | fe->ops.i2c_gate_ctrl(fe, 1); | 710 | fe->ops.i2c_gate_ctrl(fe, 1); |
711 | 711 | ||
712 | ret = mxl5007t_read_reg(state, 0x05, &d); | 712 | /* enter standby mode */ |
713 | if (mxl_fail(ret)) | 713 | ret = mxl5007t_write_reg(state, 0x01, 0x00); |
714 | goto fail; | ||
715 | |||
716 | ret = mxl5007t_write_reg(state, 0x05, d & ~0x01); | ||
717 | mxl_fail(ret); | 714 | mxl_fail(ret); |
718 | fail: | 715 | ret = mxl5007t_write_reg(state, 0x0f, 0x00); |
716 | mxl_fail(ret); | ||
717 | |||
719 | if (fe->ops.i2c_gate_ctrl) | 718 | if (fe->ops.i2c_gate_ctrl) |
720 | fe->ops.i2c_gate_ctrl(fe, 0); | 719 | fe->ops.i2c_gate_ctrl(fe, 0); |
721 | 720 | ||
@@ -775,7 +774,7 @@ static int mxl5007t_get_chip_id(struct mxl5007t_state *state) | |||
775 | int ret; | 774 | int ret; |
776 | u8 id; | 775 | u8 id; |
777 | 776 | ||
778 | ret = mxl5007t_read_reg(state, 0xd3, &id); | 777 | ret = mxl5007t_read_reg(state, 0xd9, &id); |
779 | if (mxl_fail(ret)) | 778 | if (mxl_fail(ret)) |
780 | goto fail; | 779 | goto fail; |
781 | 780 | ||
@@ -798,6 +797,9 @@ static int mxl5007t_get_chip_id(struct mxl5007t_state *state) | |||
798 | case MxL_5007_V2_200_F2: | 797 | case MxL_5007_V2_200_F2: |
799 | name = "MxL5007.v2.200.f2"; | 798 | name = "MxL5007.v2.200.f2"; |
800 | break; | 799 | break; |
800 | case MxL_5007_V4: | ||
801 | name = "MxL5007T.v4"; | ||
802 | break; | ||
801 | default: | 803 | default: |
802 | name = "MxL5007T"; | 804 | name = "MxL5007T"; |
803 | printk(KERN_WARNING "%s: unknown rev (%02x)\n", __func__, id); | 805 | printk(KERN_WARNING "%s: unknown rev (%02x)\n", __func__, id); |
@@ -870,7 +872,7 @@ EXPORT_SYMBOL_GPL(mxl5007t_attach); | |||
870 | MODULE_DESCRIPTION("MaxLinear MxL5007T Silicon IC tuner driver"); | 872 | MODULE_DESCRIPTION("MaxLinear MxL5007T Silicon IC tuner driver"); |
871 | MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>"); | 873 | MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>"); |
872 | MODULE_LICENSE("GPL"); | 874 | MODULE_LICENSE("GPL"); |
873 | MODULE_VERSION("0.1"); | 875 | MODULE_VERSION("0.2"); |
874 | 876 | ||
875 | /* | 877 | /* |
876 | * Overrides for Emacs so that we follow Linus's tabbing style. | 878 | * Overrides for Emacs so that we follow Linus's tabbing style. |