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-rw-r--r--drivers/char/Kconfig15
-rw-r--r--drivers/char/Makefile1
-rw-r--r--drivers/char/mxser_new.c3183
-rw-r--r--drivers/char/mxser_new.h450
4 files changed, 3649 insertions, 0 deletions
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 24f922f12783..b10f4d8fdc7f 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -201,6 +201,21 @@ config MOXA_SMARTIO
201 The module will be called mxser. If you want to do that, say M 201 The module will be called mxser. If you want to do that, say M
202 here. 202 here.
203 203
204config MOXA_SMARTIO_NEW
205 tristate "Moxa SmartIO support v. 2.0 (EXPERIMENTAL)"
206 depends on SERIAL_NONSTANDARD
207 help
208 Say Y here if you have a Moxa SmartIO multiport serial card and/or
209 want to help develop a new version of this driver.
210
211 This is upgraded (1.9.1) driver from original Moxa drivers with
212 changes finally resulting in PCI probing.
213
214 Use at your own risk.
215
216 This driver can also be built as a module. The module will be called
217 mxser_new. If you want to do that, say M here.
218
204config ISI 219config ISI
205 tristate "Multi-Tech multiport card support (EXPERIMENTAL)" 220 tristate "Multi-Tech multiport card support (EXPERIMENTAL)"
206 depends on SERIAL_NONSTANDARD 221 depends on SERIAL_NONSTANDARD
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
index b1fcdab90947..fc110637ced6 100644
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_MOXA_INTELLIO) += moxa.o
31obj-$(CONFIG_A2232) += ser_a2232.o generic_serial.o 31obj-$(CONFIG_A2232) += ser_a2232.o generic_serial.o
32obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o 32obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o
33obj-$(CONFIG_MOXA_SMARTIO) += mxser.o 33obj-$(CONFIG_MOXA_SMARTIO) += mxser.o
34obj-$(CONFIG_MOXA_SMARTIO_NEW) += mxser_new.o
34obj-$(CONFIG_COMPUTONE) += ip2/ 35obj-$(CONFIG_COMPUTONE) += ip2/
35obj-$(CONFIG_RISCOM8) += riscom8.o 36obj-$(CONFIG_RISCOM8) += riscom8.o
36obj-$(CONFIG_ISI) += isicom.o 37obj-$(CONFIG_ISI) += isicom.o
diff --git a/drivers/char/mxser_new.c b/drivers/char/mxser_new.c
new file mode 100644
index 000000000000..a3aff0bd8e23
--- /dev/null
+++ b/drivers/char/mxser_new.c
@@ -0,0 +1,3183 @@
1/*
2 * mxser.c -- MOXA Smartio/Industio family multiport serial driver.
3 *
4 * Copyright (C) 1999-2001 Moxa Technologies (support@moxa.com.tw).
5 *
6 * This code is loosely based on the Linux serial driver, written by
7 * Linus Torvalds, Theodore T'so and others.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 * Original release 10/26/00
24 *
25 * 02/06/01 Support MOXA Industio family boards.
26 * 02/06/01 Support TIOCGICOUNT.
27 * 02/06/01 Fix the problem for connecting to serial mouse.
28 * 02/06/01 Fix the problem for H/W flow control.
29 * 02/06/01 Fix the compling warning when CONFIG_PCI
30 * don't be defined.
31 *
32 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
33 * <alan@redhat.com>. The original 1.8 code is available on www.moxa.com.
34 * - Fixed x86_64 cleanness
35 * - Fixed sleep with spinlock held in mxser_send_break
36 */
37
38
39#include <linux/module.h>
40#include <linux/autoconf.h>
41#include <linux/errno.h>
42#include <linux/signal.h>
43#include <linux/sched.h>
44#include <linux/timer.h>
45#include <linux/interrupt.h>
46#include <linux/tty.h>
47#include <linux/tty_flip.h>
48#include <linux/serial.h>
49#include <linux/serial_reg.h>
50#include <linux/major.h>
51#include <linux/string.h>
52#include <linux/fcntl.h>
53#include <linux/ptrace.h>
54#include <linux/gfp.h>
55#include <linux/ioport.h>
56#include <linux/mm.h>
57#include <linux/smp_lock.h>
58#include <linux/delay.h>
59#include <linux/pci.h>
60
61#include <asm/system.h>
62#include <asm/io.h>
63#include <asm/irq.h>
64#include <asm/bitops.h>
65#include <asm/uaccess.h>
66
67#include "mxser.h"
68
69#define MXSER_VERSION "1.8"
70#define MXSERMAJOR 174
71#define MXSERCUMAJOR 175
72
73#define MXSER_EVENT_TXLOW 1
74#define MXSER_EVENT_HANGUP 2
75
76#define MXSER_BOARDS 4 /* Max. boards */
77#define MXSER_PORTS 32 /* Max. ports */
78#define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
79#define MXSER_ISR_PASS_LIMIT 256
80
81#define MXSER_ERR_IOADDR -1
82#define MXSER_ERR_IRQ -2
83#define MXSER_ERR_IRQ_CONFLIT -3
84#define MXSER_ERR_VECTOR -4
85
86#define SERIAL_TYPE_NORMAL 1
87#define SERIAL_TYPE_CALLOUT 2
88
89#define WAKEUP_CHARS 256
90
91#define UART_MCR_AFE 0x20
92#define UART_LSR_SPECIAL 0x1E
93
94#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK|\
95 IXON|IXOFF))
96
97#define IRQ_T(info) ((info->flags & ASYNC_SHARE_IRQ) ? IRQF_SHARED : IRQF_DISABLED)
98
99#define C168_ASIC_ID 1
100#define C104_ASIC_ID 2
101#define C102_ASIC_ID 0xB
102#define CI132_ASIC_ID 4
103#define CI134_ASIC_ID 3
104#define CI104J_ASIC_ID 5
105
106enum {
107 MXSER_BOARD_C168_ISA = 1,
108 MXSER_BOARD_C104_ISA,
109 MXSER_BOARD_CI104J,
110 MXSER_BOARD_C168_PCI,
111 MXSER_BOARD_C104_PCI,
112 MXSER_BOARD_C102_ISA,
113 MXSER_BOARD_CI132,
114 MXSER_BOARD_CI134,
115 MXSER_BOARD_CP132,
116 MXSER_BOARD_CP114,
117 MXSER_BOARD_CT114,
118 MXSER_BOARD_CP102,
119 MXSER_BOARD_CP104U,
120 MXSER_BOARD_CP168U,
121 MXSER_BOARD_CP132U,
122 MXSER_BOARD_CP134U,
123 MXSER_BOARD_CP104JU,
124 MXSER_BOARD_RC7000,
125 MXSER_BOARD_CP118U,
126 MXSER_BOARD_CP102UL,
127 MXSER_BOARD_CP102U,
128};
129
130static char *mxser_brdname[] = {
131 "C168 series",
132 "C104 series",
133 "CI-104J series",
134 "C168H/PCI series",
135 "C104H/PCI series",
136 "C102 series",
137 "CI-132 series",
138 "CI-134 series",
139 "CP-132 series",
140 "CP-114 series",
141 "CT-114 series",
142 "CP-102 series",
143 "CP-104U series",
144 "CP-168U series",
145 "CP-132U series",
146 "CP-134U series",
147 "CP-104JU series",
148 "Moxa UC7000 Serial",
149 "CP-118U series",
150 "CP-102UL series",
151 "CP-102U series",
152};
153
154static int mxser_numports[] = {
155 8, /* C168-ISA */
156 4, /* C104-ISA */
157 4, /* CI104J */
158 8, /* C168-PCI */
159 4, /* C104-PCI */
160 2, /* C102-ISA */
161 2, /* CI132 */
162 4, /* CI134 */
163 2, /* CP132 */
164 4, /* CP114 */
165 4, /* CT114 */
166 2, /* CP102 */
167 4, /* CP104U */
168 8, /* CP168U */
169 2, /* CP132U */
170 4, /* CP134U */
171 4, /* CP104JU */
172 8, /* RC7000 */
173 8, /* CP118U */
174 2, /* CP102UL */
175 2, /* CP102U */
176};
177
178#define UART_TYPE_NUM 2
179
180static const unsigned int Gmoxa_uart_id[UART_TYPE_NUM] = {
181 MOXA_MUST_MU150_HWID,
182 MOXA_MUST_MU860_HWID
183};
184
185/* This is only for PCI */
186#define UART_INFO_NUM 3
187struct mxpciuart_info {
188 int type;
189 int tx_fifo;
190 int rx_fifo;
191 int xmit_fifo_size;
192 int rx_high_water;
193 int rx_trigger;
194 int rx_low_water;
195 long max_baud;
196};
197
198static const struct mxpciuart_info Gpci_uart_info[UART_INFO_NUM] = {
199 {MOXA_OTHER_UART, 16, 16, 16, 14, 14, 1, 921600L},
200 {MOXA_MUST_MU150_HWID, 64, 64, 64, 48, 48, 16, 230400L},
201 {MOXA_MUST_MU860_HWID, 128, 128, 128, 96, 96, 32, 921600L}
202};
203
204
205#ifdef CONFIG_PCI
206
207static struct pci_device_id mxser_pcibrds[] = {
208 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_C168, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_C168_PCI},
209 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_C104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_C104_PCI},
210 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP132},
211 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP114},
212 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CT114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CT114},
213 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP102},
214 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104U, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP104U},
215 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168U, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP168U},
216 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132U, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP132U},
217 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134U, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP134U},
218 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104JU, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP104JU},
219 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_RC7000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_RC7000},
220 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118U, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP118U},
221 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102UL, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP102UL},
222 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102U, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP102U},
223 {0}
224};
225
226MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
227
228
229#endif
230
231typedef struct _moxa_pci_info {
232 unsigned short busNum;
233 unsigned short devNum;
234 struct pci_dev *pdev; /* add by Victor Yu. 06-23-2003 */
235} moxa_pci_info;
236
237static int ioaddr[MXSER_BOARDS] = { 0, 0, 0, 0 };
238static int ttymajor = MXSERMAJOR;
239static int calloutmajor = MXSERCUMAJOR;
240static int verbose = 0;
241
242/* Variables for insmod */
243
244MODULE_AUTHOR("Casper Yang");
245MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
246module_param_array(ioaddr, int, NULL, 0);
247module_param(ttymajor, int, 0);
248module_param(calloutmajor, int, 0);
249module_param(verbose, bool, 0);
250MODULE_LICENSE("GPL");
251
252struct mxser_log {
253 int tick;
254 unsigned long rxcnt[MXSER_PORTS];
255 unsigned long txcnt[MXSER_PORTS];
256};
257
258
259struct mxser_mon {
260 unsigned long rxcnt;
261 unsigned long txcnt;
262 unsigned long up_rxcnt;
263 unsigned long up_txcnt;
264 int modem_status;
265 unsigned char hold_reason;
266};
267
268struct mxser_mon_ext {
269 unsigned long rx_cnt[32];
270 unsigned long tx_cnt[32];
271 unsigned long up_rxcnt[32];
272 unsigned long up_txcnt[32];
273 int modem_status[32];
274
275 long baudrate[32];
276 int databits[32];
277 int stopbits[32];
278 int parity[32];
279 int flowctrl[32];
280 int fifo[32];
281 int iftype[32];
282};
283
284struct mxser_hwconf {
285 int board_type;
286 int ports;
287 int irq;
288 int vector;
289 int vector_mask;
290 int uart_type;
291 int ioaddr[MXSER_PORTS_PER_BOARD];
292 int baud_base[MXSER_PORTS_PER_BOARD];
293 moxa_pci_info pciInfo;
294 int IsMoxaMustChipFlag; /* add by Victor Yu. 08-30-2002 */
295 int MaxCanSetBaudRate[MXSER_PORTS_PER_BOARD]; /* add by Victor Yu. 09-04-2002 */
296 int opmode_ioaddr[MXSER_PORTS_PER_BOARD]; /* add by Victor Yu. 01-05-2004 */
297};
298
299struct mxser_struct {
300 int port;
301 int base; /* port base address */
302 int irq; /* port using irq no. */
303 int vector; /* port irq vector */
304 int vectormask; /* port vector mask */
305 int rx_high_water;
306 int rx_trigger; /* Rx fifo trigger level */
307 int rx_low_water;
308 int baud_base; /* max. speed */
309 int flags; /* defined in tty.h */
310 int type; /* UART type */
311 struct tty_struct *tty;
312 int read_status_mask;
313 int ignore_status_mask;
314 int xmit_fifo_size;
315 int custom_divisor;
316 int x_char; /* xon/xoff character */
317 int close_delay;
318 unsigned short closing_wait;
319 int IER; /* Interrupt Enable Register */
320 int MCR; /* Modem control register */
321 unsigned long event;
322 int count; /* # of fd on device */
323 int blocked_open; /* # of blocked opens */
324 long session; /* Session of opening process */
325 long pgrp; /* pgrp of opening process */
326 unsigned char *xmit_buf;
327 int xmit_head;
328 int xmit_tail;
329 int xmit_cnt;
330 struct work_struct tqueue;
331 struct termios normal_termios;
332 struct termios callout_termios;
333 wait_queue_head_t open_wait;
334 wait_queue_head_t close_wait;
335 wait_queue_head_t delta_msr_wait;
336 struct async_icount icount; /* kernel counters for the 4 input interrupts */
337 int timeout;
338 int IsMoxaMustChipFlag; /* add by Victor Yu. 08-30-2002 */
339 int MaxCanSetBaudRate; /* add by Victor Yu. 09-04-2002 */
340 int opmode_ioaddr; /* add by Victor Yu. 01-05-2004 */
341 unsigned char stop_rx;
342 unsigned char ldisc_stop_rx;
343 long realbaud;
344 struct mxser_mon mon_data;
345 unsigned char err_shadow;
346 spinlock_t slock;
347};
348
349struct mxser_mstatus {
350 tcflag_t cflag;
351 int cts;
352 int dsr;
353 int ri;
354 int dcd;
355};
356
357static struct mxser_mstatus GMStatus[MXSER_PORTS];
358
359static int mxserBoardCAP[MXSER_BOARDS] = {
360 0, 0, 0, 0
361 /* 0x180, 0x280, 0x200, 0x320 */
362};
363
364static struct tty_driver *mxvar_sdriver;
365static struct mxser_struct mxvar_table[MXSER_PORTS];
366static struct tty_struct *mxvar_tty[MXSER_PORTS + 1];
367static struct termios *mxvar_termios[MXSER_PORTS + 1];
368static struct termios *mxvar_termios_locked[MXSER_PORTS + 1];
369static struct mxser_log mxvar_log;
370static int mxvar_diagflag;
371static unsigned char mxser_msr[MXSER_PORTS + 1];
372static struct mxser_mon_ext mon_data_ext;
373static int mxser_set_baud_method[MXSER_PORTS + 1];
374static spinlock_t gm_lock;
375
376/*
377 * This is used to figure out the divisor speeds and the timeouts
378 */
379
380static struct mxser_hwconf mxsercfg[MXSER_BOARDS];
381
382/*
383 * static functions:
384 */
385
386static void mxser_getcfg(int board, struct mxser_hwconf *hwconf);
387static int mxser_init(void);
388
389/* static void mxser_poll(unsigned long); */
390static int mxser_get_ISA_conf(int, struct mxser_hwconf *);
391static int mxser_get_PCI_conf(int, int, int, struct mxser_hwconf *);
392static void mxser_do_softint(void *);
393static int mxser_open(struct tty_struct *, struct file *);
394static void mxser_close(struct tty_struct *, struct file *);
395static int mxser_write(struct tty_struct *, const unsigned char *, int);
396static int mxser_write_room(struct tty_struct *);
397static void mxser_flush_buffer(struct tty_struct *);
398static int mxser_chars_in_buffer(struct tty_struct *);
399static void mxser_flush_chars(struct tty_struct *);
400static void mxser_put_char(struct tty_struct *, unsigned char);
401static int mxser_ioctl(struct tty_struct *, struct file *, uint, ulong);
402static int mxser_ioctl_special(unsigned int, void __user *);
403static void mxser_throttle(struct tty_struct *);
404static void mxser_unthrottle(struct tty_struct *);
405static void mxser_set_termios(struct tty_struct *, struct termios *);
406static void mxser_stop(struct tty_struct *);
407static void mxser_start(struct tty_struct *);
408static void mxser_hangup(struct tty_struct *);
409static void mxser_rs_break(struct tty_struct *, int);
410static irqreturn_t mxser_interrupt(int, void *, struct pt_regs *);
411static void mxser_receive_chars(struct mxser_struct *, int *);
412static void mxser_transmit_chars(struct mxser_struct *);
413static void mxser_check_modem_status(struct mxser_struct *, int);
414static int mxser_block_til_ready(struct tty_struct *, struct file *, struct mxser_struct *);
415static int mxser_startup(struct mxser_struct *);
416static void mxser_shutdown(struct mxser_struct *);
417static int mxser_change_speed(struct mxser_struct *, struct termios *old_termios);
418static int mxser_get_serial_info(struct mxser_struct *, struct serial_struct __user *);
419static int mxser_set_serial_info(struct mxser_struct *, struct serial_struct __user *);
420static int mxser_get_lsr_info(struct mxser_struct *, unsigned int __user *);
421static void mxser_send_break(struct mxser_struct *, int);
422static int mxser_tiocmget(struct tty_struct *, struct file *);
423static int mxser_tiocmset(struct tty_struct *, struct file *, unsigned int, unsigned int);
424static int mxser_set_baud(struct mxser_struct *info, long newspd);
425static void mxser_wait_until_sent(struct tty_struct *tty, int timeout);
426
427static void mxser_startrx(struct tty_struct *tty);
428static void mxser_stoprx(struct tty_struct *tty);
429
430
431static int CheckIsMoxaMust(int io)
432{
433 u8 oldmcr, hwid;
434 int i;
435
436 outb(0, io + UART_LCR);
437 DISABLE_MOXA_MUST_ENCHANCE_MODE(io);
438 oldmcr = inb(io + UART_MCR);
439 outb(0, io + UART_MCR);
440 SET_MOXA_MUST_XON1_VALUE(io, 0x11);
441 if ((hwid = inb(io + UART_MCR)) != 0) {
442 outb(oldmcr, io + UART_MCR);
443 return MOXA_OTHER_UART;
444 }
445
446 GET_MOXA_MUST_HARDWARE_ID(io, &hwid);
447 for (i = 0; i < UART_TYPE_NUM; i++) {
448 if (hwid == Gmoxa_uart_id[i])
449 return (int)hwid;
450 }
451 return MOXA_OTHER_UART;
452}
453
454/* above is modified by Victor Yu. 08-15-2002 */
455
456static const struct tty_operations mxser_ops = {
457 .open = mxser_open,
458 .close = mxser_close,
459 .write = mxser_write,
460 .put_char = mxser_put_char,
461 .flush_chars = mxser_flush_chars,
462 .write_room = mxser_write_room,
463 .chars_in_buffer = mxser_chars_in_buffer,
464 .flush_buffer = mxser_flush_buffer,
465 .ioctl = mxser_ioctl,
466 .throttle = mxser_throttle,
467 .unthrottle = mxser_unthrottle,
468 .set_termios = mxser_set_termios,
469 .stop = mxser_stop,
470 .start = mxser_start,
471 .hangup = mxser_hangup,
472 .break_ctl = mxser_rs_break,
473 .wait_until_sent = mxser_wait_until_sent,
474 .tiocmget = mxser_tiocmget,
475 .tiocmset = mxser_tiocmset,
476};
477
478/*
479 * The MOXA Smartio/Industio serial driver boot-time initialization code!
480 */
481
482static int __init mxser_module_init(void)
483{
484 int ret;
485
486 if (verbose)
487 printk(KERN_DEBUG "Loading module mxser ...\n");
488 ret = mxser_init();
489 if (verbose)
490 printk(KERN_DEBUG "Done.\n");
491 return ret;
492}
493
494static void __exit mxser_module_exit(void)
495{
496 int i, err;
497
498 if (verbose)
499 printk(KERN_DEBUG "Unloading module mxser ...\n");
500
501 err = tty_unregister_driver(mxvar_sdriver);
502 if (!err)
503 put_tty_driver(mxvar_sdriver);
504 else
505 printk(KERN_ERR "Couldn't unregister MOXA Smartio/Industio family serial driver\n");
506
507 for (i = 0; i < MXSER_BOARDS; i++) {
508 struct pci_dev *pdev;
509
510 if (mxsercfg[i].board_type == -1)
511 continue;
512 else {
513 pdev = mxsercfg[i].pciInfo.pdev;
514 free_irq(mxsercfg[i].irq, &mxvar_table[i * MXSER_PORTS_PER_BOARD]);
515 if (pdev != NULL) { /* PCI */
516 release_region(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
517 release_region(pci_resource_start(pdev, 3), pci_resource_len(pdev, 3));
518 pci_dev_put(pdev);
519 } else {
520 release_region(mxsercfg[i].ioaddr[0], 8 * mxsercfg[i].ports);
521 release_region(mxsercfg[i].vector, 1);
522 }
523 }
524 }
525 if (verbose)
526 printk(KERN_DEBUG "Done.\n");
527}
528
529static void process_txrx_fifo(struct mxser_struct *info)
530{
531 int i;
532
533 if ((info->type == PORT_16450) || (info->type == PORT_8250)) {
534 info->rx_trigger = 1;
535 info->rx_high_water = 1;
536 info->rx_low_water = 1;
537 info->xmit_fifo_size = 1;
538 } else {
539 for (i = 0; i < UART_INFO_NUM; i++) {
540 if (info->IsMoxaMustChipFlag == Gpci_uart_info[i].type) {
541 info->rx_trigger = Gpci_uart_info[i].rx_trigger;
542 info->rx_low_water = Gpci_uart_info[i].rx_low_water;
543 info->rx_high_water = Gpci_uart_info[i].rx_high_water;
544 info->xmit_fifo_size = Gpci_uart_info[i].xmit_fifo_size;
545 break;
546 }
547 }
548 }
549}
550
551static int mxser_initbrd(int board, struct mxser_hwconf *hwconf)
552{
553 struct mxser_struct *info;
554 int retval;
555 int i, n;
556
557 n = board * MXSER_PORTS_PER_BOARD;
558 info = &mxvar_table[n];
559 /*if (verbose) */ {
560 printk(KERN_DEBUG " ttyM%d - ttyM%d ",
561 n, n + hwconf->ports - 1);
562 printk(" max. baud rate = %d bps.\n",
563 hwconf->MaxCanSetBaudRate[0]);
564 }
565
566 for (i = 0; i < hwconf->ports; i++, n++, info++) {
567 info->port = n;
568 info->base = hwconf->ioaddr[i];
569 info->irq = hwconf->irq;
570 info->vector = hwconf->vector;
571 info->vectormask = hwconf->vector_mask;
572 info->opmode_ioaddr = hwconf->opmode_ioaddr[i]; /* add by Victor Yu. 01-05-2004 */
573 info->stop_rx = 0;
574 info->ldisc_stop_rx = 0;
575
576 info->IsMoxaMustChipFlag = hwconf->IsMoxaMustChipFlag;
577 /* Enhance mode enabled here */
578 if (info->IsMoxaMustChipFlag != MOXA_OTHER_UART) {
579 ENABLE_MOXA_MUST_ENCHANCE_MODE(info->base);
580 }
581
582 info->flags = ASYNC_SHARE_IRQ;
583 info->type = hwconf->uart_type;
584 info->baud_base = hwconf->baud_base[i];
585
586 info->MaxCanSetBaudRate = hwconf->MaxCanSetBaudRate[i];
587
588 process_txrx_fifo(info);
589
590
591 info->custom_divisor = hwconf->baud_base[i] * 16;
592 info->close_delay = 5 * HZ / 10;
593 info->closing_wait = 30 * HZ;
594 INIT_WORK(&info->tqueue, mxser_do_softint, info);
595 info->normal_termios = mxvar_sdriver->init_termios;
596 init_waitqueue_head(&info->open_wait);
597 init_waitqueue_head(&info->close_wait);
598 init_waitqueue_head(&info->delta_msr_wait);
599 memset(&info->mon_data, 0, sizeof(struct mxser_mon));
600 info->err_shadow = 0;
601 spin_lock_init(&info->slock);
602 }
603 /*
604 * Allocate the IRQ if necessary
605 */
606
607
608 /* before set INT ISR, disable all int */
609 for (i = 0; i < hwconf->ports; i++) {
610 outb(inb(hwconf->ioaddr[i] + UART_IER) & 0xf0,
611 hwconf->ioaddr[i] + UART_IER);
612 }
613
614 n = board * MXSER_PORTS_PER_BOARD;
615 info = &mxvar_table[n];
616
617 retval = request_irq(hwconf->irq, mxser_interrupt, IRQ_T(info),
618 "mxser", info);
619 if (retval) {
620 printk(KERN_ERR "Board %d: %s",
621 board, mxser_brdname[hwconf->board_type - 1]);
622 printk(" Request irq failed, IRQ (%d) may conflict with"
623 " another device.\n", info->irq);
624 return retval;
625 }
626 return 0;
627}
628
629static void mxser_getcfg(int board, struct mxser_hwconf *hwconf)
630{
631 mxsercfg[board] = *hwconf;
632}
633
634#ifdef CONFIG_PCI
635static int mxser_get_PCI_conf(int busnum, int devnum, int board_type, struct mxser_hwconf *hwconf)
636{
637 int i, j;
638 /* unsigned int val; */
639 unsigned int ioaddress;
640 struct pci_dev *pdev = hwconf->pciInfo.pdev;
641
642 /* io address */
643 hwconf->board_type = board_type;
644 hwconf->ports = mxser_numports[board_type - 1];
645 ioaddress = pci_resource_start(pdev, 2);
646 request_region(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2),
647 "mxser(IO)");
648
649 for (i = 0; i < hwconf->ports; i++)
650 hwconf->ioaddr[i] = ioaddress + 8 * i;
651
652 /* vector */
653 ioaddress = pci_resource_start(pdev, 3);
654 request_region(pci_resource_start(pdev, 3), pci_resource_len(pdev, 3),
655 "mxser(vector)");
656 hwconf->vector = ioaddress;
657
658 /* irq */
659 hwconf->irq = hwconf->pciInfo.pdev->irq;
660
661 hwconf->IsMoxaMustChipFlag = CheckIsMoxaMust(hwconf->ioaddr[0]);
662 hwconf->uart_type = PORT_16550A;
663 hwconf->vector_mask = 0;
664
665
666 for (i = 0; i < hwconf->ports; i++) {
667 for (j = 0; j < UART_INFO_NUM; j++) {
668 if (Gpci_uart_info[j].type == hwconf->IsMoxaMustChipFlag) {
669 hwconf->MaxCanSetBaudRate[i] = Gpci_uart_info[j].max_baud;
670
671 /* exception....CP-102 */
672 if (board_type == MXSER_BOARD_CP102)
673 hwconf->MaxCanSetBaudRate[i] = 921600;
674 break;
675 }
676 }
677 }
678
679 if (hwconf->IsMoxaMustChipFlag == MOXA_MUST_MU860_HWID) {
680 for (i = 0; i < hwconf->ports; i++) {
681 if (i < 4)
682 hwconf->opmode_ioaddr[i] = ioaddress + 4;
683 else
684 hwconf->opmode_ioaddr[i] = ioaddress + 0x0c;
685 }
686 outb(0, ioaddress + 4); /* default set to RS232 mode */
687 outb(0, ioaddress + 0x0c); /* default set to RS232 mode */
688 }
689
690 for (i = 0; i < hwconf->ports; i++) {
691 hwconf->vector_mask |= (1 << i);
692 hwconf->baud_base[i] = 921600;
693 }
694 return 0;
695}
696#endif
697
698static int mxser_init(void)
699{
700 int i, m, retval, b, n;
701 struct pci_dev *pdev = NULL;
702 int index;
703 unsigned char busnum, devnum;
704 struct mxser_hwconf hwconf;
705
706 mxvar_sdriver = alloc_tty_driver(MXSER_PORTS + 1);
707 if (!mxvar_sdriver)
708 return -ENOMEM;
709 spin_lock_init(&gm_lock);
710
711 for (i = 0; i < MXSER_BOARDS; i++) {
712 mxsercfg[i].board_type = -1;
713 }
714
715 printk(KERN_INFO "MOXA Smartio/Industio family driver version %s\n",
716 MXSER_VERSION);
717
718 /* Initialize the tty_driver structure */
719 memset(mxvar_sdriver, 0, sizeof(struct tty_driver));
720 mxvar_sdriver->magic = TTY_DRIVER_MAGIC;
721 mxvar_sdriver->name = "ttyM";
722 mxvar_sdriver->major = ttymajor;
723 mxvar_sdriver->minor_start = 0;
724 mxvar_sdriver->num = MXSER_PORTS + 1;
725 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
726 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
727 mxvar_sdriver->init_termios = tty_std_termios;
728 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
729 mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW;
730 tty_set_operations(mxvar_sdriver, &mxser_ops);
731 mxvar_sdriver->ttys = mxvar_tty;
732 mxvar_sdriver->termios = mxvar_termios;
733 mxvar_sdriver->termios_locked = mxvar_termios_locked;
734
735 mxvar_diagflag = 0;
736 memset(mxvar_table, 0, MXSER_PORTS * sizeof(struct mxser_struct));
737 memset(&mxvar_log, 0, sizeof(struct mxser_log));
738
739 memset(&mxser_msr, 0, sizeof(unsigned char) * (MXSER_PORTS + 1));
740 memset(&mon_data_ext, 0, sizeof(struct mxser_mon_ext));
741 memset(&mxser_set_baud_method, 0, sizeof(int) * (MXSER_PORTS + 1));
742 memset(&hwconf, 0, sizeof(struct mxser_hwconf));
743
744 m = 0;
745 /* Start finding ISA boards here */
746 for (b = 0; b < MXSER_BOARDS && m < MXSER_BOARDS; b++) {
747 int cap;
748
749 if (!(cap = mxserBoardCAP[b]))
750 continue;
751
752 retval = mxser_get_ISA_conf(cap, &hwconf);
753
754 if (retval != 0)
755 printk(KERN_INFO "Found MOXA %s board (CAP=0x%x)\n",
756 mxser_brdname[hwconf.board_type - 1], ioaddr[b]);
757
758 if (retval <= 0) {
759 if (retval == MXSER_ERR_IRQ)
760 printk(KERN_ERR "Invalid interrupt number, "
761 "board not configured\n");
762 else if (retval == MXSER_ERR_IRQ_CONFLIT)
763 printk(KERN_ERR "Invalid interrupt number, "
764 "board not configured\n");
765 else if (retval == MXSER_ERR_VECTOR)
766 printk(KERN_ERR "Invalid interrupt vector, "
767 "board not configured\n");
768 else if (retval == MXSER_ERR_IOADDR)
769 printk(KERN_ERR "Invalid I/O address, "
770 "board not configured\n");
771
772 continue;
773 }
774
775 hwconf.pciInfo.busNum = 0;
776 hwconf.pciInfo.devNum = 0;
777 hwconf.pciInfo.pdev = NULL;
778
779 mxser_getcfg(m, &hwconf);
780 /*
781 * init mxsercfg first,
782 * or mxsercfg data is not correct on ISR.
783 */
784 /* mxser_initbrd will hook ISR. */
785 if (mxser_initbrd(m, &hwconf) < 0)
786 continue;
787
788 m++;
789 }
790
791 /* Start finding ISA boards from module arg */
792 for (b = 0; b < MXSER_BOARDS && m < MXSER_BOARDS; b++) {
793 int cap;
794
795 if (!(cap = ioaddr[b]))
796 continue;
797
798 retval = mxser_get_ISA_conf(cap, &hwconf);
799
800 if (retval != 0)
801 printk(KERN_INFO "Found MOXA %s board (CAP=0x%x)\n",
802 mxser_brdname[hwconf.board_type - 1], ioaddr[b]);
803
804 if (retval <= 0) {
805 if (retval == MXSER_ERR_IRQ)
806 printk(KERN_ERR "Invalid interrupt number, "
807 "board not configured\n");
808 else if (retval == MXSER_ERR_IRQ_CONFLIT)
809 printk(KERN_ERR "Invalid interrupt number, "
810 "board not configured\n");
811 else if (retval == MXSER_ERR_VECTOR)
812 printk(KERN_ERR "Invalid interrupt vector, "
813 "board not configured\n");
814 else if (retval == MXSER_ERR_IOADDR)
815 printk(KERN_ERR "Invalid I/O address, "
816 "board not configured\n");
817
818 continue;
819 }
820
821 hwconf.pciInfo.busNum = 0;
822 hwconf.pciInfo.devNum = 0;
823 hwconf.pciInfo.pdev = NULL;
824
825 mxser_getcfg(m, &hwconf);
826 /*
827 * init mxsercfg first,
828 * or mxsercfg data is not correct on ISR.
829 */
830 /* mxser_initbrd will hook ISR. */
831 if (mxser_initbrd(m, &hwconf) < 0)
832 continue;
833
834 m++;
835 }
836
837 /* start finding PCI board here */
838#ifdef CONFIG_PCI
839 n = ARRAY_SIZE(mxser_pcibrds) - 1;
840 index = 0;
841 b = 0;
842 while (b < n) {
843 pdev = pci_get_device(mxser_pcibrds[b].vendor,
844 mxser_pcibrds[b].device, pdev);
845 if (pdev == NULL) {
846 b++;
847 continue;
848 }
849 hwconf.pciInfo.busNum = busnum = pdev->bus->number;
850 hwconf.pciInfo.devNum = devnum = PCI_SLOT(pdev->devfn) << 3;
851 hwconf.pciInfo.pdev = pdev;
852 printk(KERN_INFO "Found MOXA %s board(BusNo=%d,DevNo=%d)\n",
853 mxser_brdname[(int) (mxser_pcibrds[b].driver_data) - 1],
854 busnum, devnum >> 3);
855 index++;
856 if (m >= MXSER_BOARDS)
857 printk(KERN_ERR
858 "Too many Smartio/Industio family boards find "
859 "(maximum %d), board not configured\n",
860 MXSER_BOARDS);
861 else {
862 if (pci_enable_device(pdev)) {
863 printk(KERN_ERR "Moxa SmartI/O PCI enable "
864 "fail !\n");
865 continue;
866 }
867 retval = mxser_get_PCI_conf(busnum, devnum,
868 (int)mxser_pcibrds[b].driver_data,
869 &hwconf);
870 if (retval < 0) {
871 if (retval == MXSER_ERR_IRQ)
872 printk(KERN_ERR
873 "Invalid interrupt number, "
874 "board not configured\n");
875 else if (retval == MXSER_ERR_IRQ_CONFLIT)
876 printk(KERN_ERR
877 "Invalid interrupt number, "
878 "board not configured\n");
879 else if (retval == MXSER_ERR_VECTOR)
880 printk(KERN_ERR
881 "Invalid interrupt vector, "
882 "board not configured\n");
883 else if (retval == MXSER_ERR_IOADDR)
884 printk(KERN_ERR
885 "Invalid I/O address, "
886 "board not configured\n");
887 continue;
888 }
889 mxser_getcfg(m, &hwconf);
890 /* init mxsercfg first,
891 * or mxsercfg data is not correct on ISR.
892 */
893 /* mxser_initbrd will hook ISR. */
894 if (mxser_initbrd(m, &hwconf) < 0)
895 continue;
896 m++;
897 /* Keep an extra reference if we succeeded. It will
898 be returned at unload time */
899 pci_dev_get(pdev);
900 }
901 }
902#endif
903
904 retval = tty_register_driver(mxvar_sdriver);
905 if (retval) {
906 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family"
907 " driver !\n");
908 put_tty_driver(mxvar_sdriver);
909
910 for (i = 0; i < MXSER_BOARDS; i++) {
911 if (mxsercfg[i].board_type == -1)
912 continue;
913 else {
914 free_irq(mxsercfg[i].irq, &mxvar_table[i * MXSER_PORTS_PER_BOARD]);
915 /* todo: release io, vector */
916 }
917 }
918 return retval;
919 }
920
921 return 0;
922}
923
924static void mxser_do_softint(void *private_)
925{
926 struct mxser_struct *info = private_;
927 struct tty_struct *tty;
928
929 tty = info->tty;
930
931 if (tty) {
932 if (test_and_clear_bit(MXSER_EVENT_TXLOW, &info->event))
933 tty_wakeup(tty);
934 if (test_and_clear_bit(MXSER_EVENT_HANGUP, &info->event))
935 tty_hangup(tty);
936 }
937}
938
939static unsigned char mxser_get_msr(int baseaddr, int mode, int port, struct mxser_struct *info)
940{
941 unsigned char status = 0;
942
943 status = inb(baseaddr + UART_MSR);
944
945 mxser_msr[port] &= 0x0F;
946 mxser_msr[port] |= status;
947 status = mxser_msr[port];
948 if (mode)
949 mxser_msr[port] = 0;
950
951 return status;
952}
953
954/*
955 * This routine is called whenever a serial port is opened. It
956 * enables interrupts for a serial port, linking in its async structure into
957 * the IRQ chain. It also performs the serial-specific
958 * initialization for the tty structure.
959 */
960static int mxser_open(struct tty_struct *tty, struct file *filp)
961{
962 struct mxser_struct *info;
963 int retval, line;
964
965 /* initialize driver_data in case something fails */
966 tty->driver_data = NULL;
967
968 line = tty->index;
969 if (line == MXSER_PORTS)
970 return 0;
971 if (line < 0 || line > MXSER_PORTS)
972 return -ENODEV;
973 info = mxvar_table + line;
974 if (!info->base)
975 return -ENODEV;
976
977 tty->driver_data = info;
978 info->tty = tty;
979 /*
980 * Start up serial port
981 */
982 retval = mxser_startup(info);
983 if (retval)
984 return retval;
985
986 retval = mxser_block_til_ready(tty, filp, info);
987 if (retval)
988 return retval;
989
990 info->count++;
991
992 if ((info->count == 1) && (info->flags & ASYNC_SPLIT_TERMIOS)) {
993 if (tty->driver->subtype == SERIAL_TYPE_NORMAL)
994 *tty->termios = info->normal_termios;
995 else
996 *tty->termios = info->callout_termios;
997 mxser_change_speed(info, NULL);
998 }
999
1000 info->session = current->signal->session;
1001 info->pgrp = process_group(current);
1002
1003 /*
1004 status = mxser_get_msr(info->base, 0, info->port);
1005 mxser_check_modem_status(info, status);
1006 */
1007
1008/* unmark here for very high baud rate (ex. 921600 bps) used */
1009 tty->low_latency = 1;
1010 return 0;
1011}
1012
1013/*
1014 * This routine is called when the serial port gets closed. First, we
1015 * wait for the last remaining data to be sent. Then, we unlink its
1016 * async structure from the interrupt chain if necessary, and we free
1017 * that IRQ if nothing is left in the chain.
1018 */
1019static void mxser_close(struct tty_struct *tty, struct file *filp)
1020{
1021 struct mxser_struct *info = tty->driver_data;
1022
1023 unsigned long timeout;
1024 unsigned long flags;
1025 struct tty_ldisc *ld;
1026
1027 if (tty->index == MXSER_PORTS)
1028 return;
1029 if (!info)
1030 return;
1031
1032 spin_lock_irqsave(&info->slock, flags);
1033
1034 if (tty_hung_up_p(filp)) {
1035 spin_unlock_irqrestore(&info->slock, flags);
1036 return;
1037 }
1038 if ((tty->count == 1) && (info->count != 1)) {
1039 /*
1040 * Uh, oh. tty->count is 1, which means that the tty
1041 * structure will be freed. Info->count should always
1042 * be one in these conditions. If it's greater than
1043 * one, we've got real problems, since it means the
1044 * serial port won't be shutdown.
1045 */
1046 printk(KERN_ERR "mxser_close: bad serial port count; "
1047 "tty->count is 1, info->count is %d\n", info->count);
1048 info->count = 1;
1049 }
1050 if (--info->count < 0) {
1051 printk(KERN_ERR "mxser_close: bad serial port count for "
1052 "ttys%d: %d\n", info->port, info->count);
1053 info->count = 0;
1054 }
1055 if (info->count) {
1056 spin_unlock_irqrestore(&info->slock, flags);
1057 return;
1058 }
1059 info->flags |= ASYNC_CLOSING;
1060 spin_unlock_irqrestore(&info->slock, flags);
1061 /*
1062 * Save the termios structure, since this port may have
1063 * separate termios for callout and dialin.
1064 */
1065 if (info->flags & ASYNC_NORMAL_ACTIVE)
1066 info->normal_termios = *tty->termios;
1067 /*
1068 * Now we wait for the transmit buffer to clear; and we notify
1069 * the line discipline to only process XON/XOFF characters.
1070 */
1071 tty->closing = 1;
1072 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE)
1073 tty_wait_until_sent(tty, info->closing_wait);
1074 /*
1075 * At this point we stop accepting input. To do this, we
1076 * disable the receive line status interrupts, and tell the
1077 * interrupt driver to stop checking the data ready bit in the
1078 * line status register.
1079 */
1080 info->IER &= ~UART_IER_RLSI;
1081 if (info->IsMoxaMustChipFlag)
1082 info->IER &= ~MOXA_MUST_RECV_ISR;
1083/* by William
1084 info->read_status_mask &= ~UART_LSR_DR;
1085*/
1086 if (info->flags & ASYNC_INITIALIZED) {
1087 outb(info->IER, info->base + UART_IER);
1088 /*
1089 * Before we drop DTR, make sure the UART transmitter
1090 * has completely drained; this is especially
1091 * important if there is a transmit FIFO!
1092 */
1093 timeout = jiffies + HZ;
1094 while (!(inb(info->base + UART_LSR) & UART_LSR_TEMT)) {
1095 schedule_timeout_interruptible(5);
1096 if (time_after(jiffies, timeout))
1097 break;
1098 }
1099 }
1100 mxser_shutdown(info);
1101
1102 if (tty->driver->flush_buffer)
1103 tty->driver->flush_buffer(tty);
1104
1105 ld = tty_ldisc_ref(tty);
1106 if (ld) {
1107 if (ld->flush_buffer)
1108 ld->flush_buffer(tty);
1109 tty_ldisc_deref(ld);
1110 }
1111
1112 tty->closing = 0;
1113 info->event = 0;
1114 info->tty = NULL;
1115 if (info->blocked_open) {
1116 if (info->close_delay)
1117 schedule_timeout_interruptible(info->close_delay);
1118 wake_up_interruptible(&info->open_wait);
1119 }
1120
1121 info->flags &= ~(ASYNC_NORMAL_ACTIVE | ASYNC_CLOSING);
1122 wake_up_interruptible(&info->close_wait);
1123
1124}
1125
1126static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count)
1127{
1128 int c, total = 0;
1129 struct mxser_struct *info = tty->driver_data;
1130 unsigned long flags;
1131
1132 if (!info->xmit_buf)
1133 return 0;
1134
1135 while (1) {
1136 c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
1137 SERIAL_XMIT_SIZE - info->xmit_head));
1138 if (c <= 0)
1139 break;
1140
1141 memcpy(info->xmit_buf + info->xmit_head, buf, c);
1142 spin_lock_irqsave(&info->slock, flags);
1143 info->xmit_head = (info->xmit_head + c) &
1144 (SERIAL_XMIT_SIZE - 1);
1145 info->xmit_cnt += c;
1146 spin_unlock_irqrestore(&info->slock, flags);
1147
1148 buf += c;
1149 count -= c;
1150 total += c;
1151 }
1152
1153 if (info->xmit_cnt && !tty->stopped && !(info->IER & UART_IER_THRI)) {
1154 if (!tty->hw_stopped ||
1155 (info->type == PORT_16550A) ||
1156 (info->IsMoxaMustChipFlag)) {
1157 spin_lock_irqsave(&info->slock, flags);
1158 info->IER |= UART_IER_THRI;
1159 outb(info->IER, info->base + UART_IER);
1160 spin_unlock_irqrestore(&info->slock, flags);
1161 }
1162 }
1163 return total;
1164}
1165
1166static void mxser_put_char(struct tty_struct *tty, unsigned char ch)
1167{
1168 struct mxser_struct *info = tty->driver_data;
1169 unsigned long flags;
1170
1171 if (!info->xmit_buf)
1172 return;
1173
1174 if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1)
1175 return;
1176
1177 spin_lock_irqsave(&info->slock, flags);
1178 info->xmit_buf[info->xmit_head++] = ch;
1179 info->xmit_head &= SERIAL_XMIT_SIZE - 1;
1180 info->xmit_cnt++;
1181 spin_unlock_irqrestore(&info->slock, flags);
1182 if (!tty->stopped && !(info->IER & UART_IER_THRI)) {
1183 if (!tty->hw_stopped ||
1184 (info->type == PORT_16550A) ||
1185 info->IsMoxaMustChipFlag) {
1186 spin_lock_irqsave(&info->slock, flags);
1187 info->IER |= UART_IER_THRI;
1188 outb(info->IER, info->base + UART_IER);
1189 spin_unlock_irqrestore(&info->slock, flags);
1190 }
1191 }
1192}
1193
1194
1195static void mxser_flush_chars(struct tty_struct *tty)
1196{
1197 struct mxser_struct *info = tty->driver_data;
1198 unsigned long flags;
1199
1200 if (info->xmit_cnt <= 0 ||
1201 tty->stopped ||
1202 !info->xmit_buf ||
1203 (tty->hw_stopped &&
1204 (info->type != PORT_16550A) &&
1205 (!info->IsMoxaMustChipFlag)
1206 ))
1207 return;
1208
1209 spin_lock_irqsave(&info->slock, flags);
1210
1211 info->IER |= UART_IER_THRI;
1212 outb(info->IER, info->base + UART_IER);
1213
1214 spin_unlock_irqrestore(&info->slock, flags);
1215}
1216
1217static int mxser_write_room(struct tty_struct *tty)
1218{
1219 struct mxser_struct *info = tty->driver_data;
1220 int ret;
1221
1222 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
1223 if (ret < 0)
1224 ret = 0;
1225 return ret;
1226}
1227
1228static int mxser_chars_in_buffer(struct tty_struct *tty)
1229{
1230 struct mxser_struct *info = tty->driver_data;
1231 return info->xmit_cnt;
1232}
1233
1234static void mxser_flush_buffer(struct tty_struct *tty)
1235{
1236 struct mxser_struct *info = tty->driver_data;
1237 char fcr;
1238 unsigned long flags;
1239
1240
1241 spin_lock_irqsave(&info->slock, flags);
1242 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1243
1244 /* below added by shinhay */
1245 fcr = inb(info->base + UART_FCR);
1246 outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
1247 info->base + UART_FCR);
1248 outb(fcr, info->base + UART_FCR);
1249
1250 spin_unlock_irqrestore(&info->slock, flags);
1251 /* above added by shinhay */
1252
1253 wake_up_interruptible(&tty->write_wait);
1254 if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) && tty->ldisc.write_wakeup)
1255 (tty->ldisc.write_wakeup) (tty);
1256}
1257
1258static int mxser_ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg)
1259{
1260 struct mxser_struct *info = tty->driver_data;
1261 int retval;
1262 struct async_icount cprev, cnow; /* kernel counter temps */
1263 struct serial_icounter_struct __user *p_cuser;
1264 unsigned long templ;
1265 unsigned long flags;
1266 void __user *argp = (void __user *)arg;
1267
1268 if (tty->index == MXSER_PORTS)
1269 return mxser_ioctl_special(cmd, argp);
1270
1271 /* following add by Victor Yu. 01-05-2004 */
1272 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) {
1273 int opmode, p;
1274 static unsigned char ModeMask[] = { 0xfc, 0xf3, 0xcf, 0x3f };
1275 int shiftbit;
1276 unsigned char val, mask;
1277
1278 p = info->port % 4;
1279 if (cmd == MOXA_SET_OP_MODE) {
1280 if (get_user(opmode, (int __user *) argp))
1281 return -EFAULT;
1282 if (opmode != RS232_MODE &&
1283 opmode != RS485_2WIRE_MODE &&
1284 opmode != RS422_MODE &&
1285 opmode != RS485_4WIRE_MODE)
1286 return -EFAULT;
1287 mask = ModeMask[p];
1288 shiftbit = p * 2;
1289 val = inb(info->opmode_ioaddr);
1290 val &= mask;
1291 val |= (opmode << shiftbit);
1292 outb(val, info->opmode_ioaddr);
1293 } else {
1294 shiftbit = p * 2;
1295 opmode = inb(info->opmode_ioaddr) >> shiftbit;
1296 opmode &= OP_MODE_MASK;
1297 if (copy_to_user(argp, &opmode, sizeof(int)))
1298 return -EFAULT;
1299 }
1300 return 0;
1301 }
1302 /* above add by Victor Yu. 01-05-2004 */
1303
1304 if ((cmd != TIOCGSERIAL) && (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1305 if (tty->flags & (1 << TTY_IO_ERROR))
1306 return -EIO;
1307 }
1308 switch (cmd) {
1309 case TCSBRK: /* SVID version: non-zero arg --> no break */
1310 retval = tty_check_change(tty);
1311 if (retval)
1312 return retval;
1313 tty_wait_until_sent(tty, 0);
1314 if (!arg)
1315 mxser_send_break(info, HZ / 4); /* 1/4 second */
1316 return 0;
1317 case TCSBRKP: /* support for POSIX tcsendbreak() */
1318 retval = tty_check_change(tty);
1319 if (retval)
1320 return retval;
1321 tty_wait_until_sent(tty, 0);
1322 mxser_send_break(info, arg ? arg * (HZ / 10) : HZ / 4);
1323 return 0;
1324 case TIOCGSOFTCAR:
1325 return put_user(C_CLOCAL(tty) ? 1 : 0, (unsigned long __user *)argp);
1326 case TIOCSSOFTCAR:
1327 if (get_user(templ, (unsigned long __user *) argp))
1328 return -EFAULT;
1329 arg = templ;
1330 tty->termios->c_cflag = ((tty->termios->c_cflag & ~CLOCAL) | (arg ? CLOCAL : 0));
1331 return 0;
1332 case TIOCGSERIAL:
1333 return mxser_get_serial_info(info, argp);
1334 case TIOCSSERIAL:
1335 return mxser_set_serial_info(info, argp);
1336 case TIOCSERGETLSR: /* Get line status register */
1337 return mxser_get_lsr_info(info, argp);
1338 /*
1339 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1340 * - mask passed in arg for lines of interest
1341 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1342 * Caller should use TIOCGICOUNT to see which one it was
1343 */
1344 case TIOCMIWAIT: {
1345 DECLARE_WAITQUEUE(wait, current);
1346 int ret;
1347 spin_lock_irqsave(&info->slock, flags);
1348 cprev = info->icount; /* note the counters on entry */
1349 spin_unlock_irqrestore(&info->slock, flags);
1350
1351 add_wait_queue(&info->delta_msr_wait, &wait);
1352 while (1) {
1353 spin_lock_irqsave(&info->slock, flags);
1354 cnow = info->icount; /* atomic copy */
1355 spin_unlock_irqrestore(&info->slock, flags);
1356
1357 set_current_state(TASK_INTERRUPTIBLE);
1358 if (((arg & TIOCM_RNG) &&
1359 (cnow.rng != cprev.rng)) ||
1360 ((arg & TIOCM_DSR) &&
1361 (cnow.dsr != cprev.dsr)) ||
1362 ((arg & TIOCM_CD) &&
1363 (cnow.dcd != cprev.dcd)) ||
1364 ((arg & TIOCM_CTS) &&
1365 (cnow.cts != cprev.cts))) {
1366 ret = 0;
1367 break;
1368 }
1369 /* see if a signal did it */
1370 if (signal_pending(current)) {
1371 ret = -ERESTARTSYS;
1372 break;
1373 }
1374 cprev = cnow;
1375 }
1376 current->state = TASK_RUNNING;
1377 remove_wait_queue(&info->delta_msr_wait, &wait);
1378 break;
1379 }
1380 /* NOTREACHED */
1381 /*
1382 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1383 * Return: write counters to the user passed counter struct
1384 * NB: both 1->0 and 0->1 transitions are counted except for
1385 * RI where only 0->1 is counted.
1386 */
1387 case TIOCGICOUNT:
1388 spin_lock_irqsave(&info->slock, flags);
1389 cnow = info->icount;
1390 spin_unlock_irqrestore(&info->slock, flags);
1391 p_cuser = argp;
1392 /* modified by casper 1/11/2000 */
1393 if (put_user(cnow.frame, &p_cuser->frame))
1394 return -EFAULT;
1395 if (put_user(cnow.brk, &p_cuser->brk))
1396 return -EFAULT;
1397 if (put_user(cnow.overrun, &p_cuser->overrun))
1398 return -EFAULT;
1399 if (put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1400 return -EFAULT;
1401 if (put_user(cnow.parity, &p_cuser->parity))
1402 return -EFAULT;
1403 if (put_user(cnow.rx, &p_cuser->rx))
1404 return -EFAULT;
1405 if (put_user(cnow.tx, &p_cuser->tx))
1406 return -EFAULT;
1407 put_user(cnow.cts, &p_cuser->cts);
1408 put_user(cnow.dsr, &p_cuser->dsr);
1409 put_user(cnow.rng, &p_cuser->rng);
1410 put_user(cnow.dcd, &p_cuser->dcd);
1411 return 0;
1412 case MOXA_HighSpeedOn:
1413 return put_user(info->baud_base != 115200 ? 1 : 0, (int __user *)argp);
1414 case MOXA_SDS_RSTICOUNTER: {
1415 info->mon_data.rxcnt = 0;
1416 info->mon_data.txcnt = 0;
1417 return 0;
1418 }
1419/* (above) added by James. */
1420 case MOXA_ASPP_SETBAUD:{
1421 long baud;
1422 if (get_user(baud, (long __user *)argp))
1423 return -EFAULT;
1424 mxser_set_baud(info, baud);
1425 return 0;
1426 }
1427 case MOXA_ASPP_GETBAUD:
1428 if (copy_to_user(argp, &info->realbaud, sizeof(long)))
1429 return -EFAULT;
1430
1431 return 0;
1432
1433 case MOXA_ASPP_OQUEUE:{
1434 int len, lsr;
1435
1436 len = mxser_chars_in_buffer(tty);
1437
1438 lsr = inb(info->base + UART_LSR) & UART_LSR_TEMT;
1439
1440 len += (lsr ? 0 : 1);
1441
1442 if (copy_to_user(argp, &len, sizeof(int)))
1443 return -EFAULT;
1444
1445 return 0;
1446 }
1447 case MOXA_ASPP_MON: {
1448 int mcr, status;
1449
1450 /* info->mon_data.ser_param = tty->termios->c_cflag; */
1451
1452 status = mxser_get_msr(info->base, 1, info->port, info);
1453 mxser_check_modem_status(info, status);
1454
1455 mcr = inb(info->base + UART_MCR);
1456 if (mcr & MOXA_MUST_MCR_XON_FLAG)
1457 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFHOLD;
1458 else
1459 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFHOLD;
1460
1461 if (mcr & MOXA_MUST_MCR_TX_XON)
1462 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFXENT;
1463 else
1464 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFXENT;
1465
1466 if (info->tty->hw_stopped)
1467 info->mon_data.hold_reason |= NPPI_NOTIFY_CTSHOLD;
1468 else
1469 info->mon_data.hold_reason &= ~NPPI_NOTIFY_CTSHOLD;
1470
1471 if (copy_to_user(argp, &info->mon_data,
1472 sizeof(struct mxser_mon)))
1473 return -EFAULT;
1474
1475 return 0;
1476 }
1477
1478 case MOXA_ASPP_LSTATUS: {
1479 if (copy_to_user(argp, &info->err_shadow,
1480 sizeof(unsigned char)))
1481 return -EFAULT;
1482
1483 info->err_shadow = 0;
1484 return 0;
1485 }
1486 case MOXA_SET_BAUD_METHOD: {
1487 int method;
1488
1489 if (get_user(method, (int __user *)argp))
1490 return -EFAULT;
1491 mxser_set_baud_method[info->port] = method;
1492 if (copy_to_user(argp, &method, sizeof(int)))
1493 return -EFAULT;
1494
1495 return 0;
1496 }
1497 default:
1498 return -ENOIOCTLCMD;
1499 }
1500 return 0;
1501}
1502
1503#ifndef CMSPAR
1504#define CMSPAR 010000000000
1505#endif
1506
1507static int mxser_ioctl_special(unsigned int cmd, void __user *argp)
1508{
1509 int i, result, status;
1510
1511 switch (cmd) {
1512 case MOXA_GET_CONF:
1513 if (copy_to_user(argp, mxsercfg,
1514 sizeof(struct mxser_hwconf) * 4))
1515 return -EFAULT;
1516 return 0;
1517 case MOXA_GET_MAJOR:
1518 if (copy_to_user(argp, &ttymajor, sizeof(int)))
1519 return -EFAULT;
1520 return 0;
1521
1522 case MOXA_GET_CUMAJOR:
1523 if (copy_to_user(argp, &calloutmajor, sizeof(int)))
1524 return -EFAULT;
1525 return 0;
1526
1527 case MOXA_CHKPORTENABLE:
1528 result = 0;
1529 for (i = 0; i < MXSER_PORTS; i++) {
1530 if (mxvar_table[i].base)
1531 result |= (1 << i);
1532 }
1533 return put_user(result, (unsigned long __user *)argp);
1534 case MOXA_GETDATACOUNT:
1535 if (copy_to_user(argp, &mxvar_log, sizeof(mxvar_log)))
1536 return -EFAULT;
1537 return 0;
1538 case MOXA_GETMSTATUS:
1539 for (i = 0; i < MXSER_PORTS; i++) {
1540 GMStatus[i].ri = 0;
1541 if (!mxvar_table[i].base) {
1542 GMStatus[i].dcd = 0;
1543 GMStatus[i].dsr = 0;
1544 GMStatus[i].cts = 0;
1545 continue;
1546 }
1547
1548 if (!mxvar_table[i].tty || !mxvar_table[i].tty->termios)
1549 GMStatus[i].cflag = mxvar_table[i].normal_termios.c_cflag;
1550 else
1551 GMStatus[i].cflag = mxvar_table[i].tty->termios->c_cflag;
1552
1553 status = inb(mxvar_table[i].base + UART_MSR);
1554 if (status & 0x80 /*UART_MSR_DCD */ )
1555 GMStatus[i].dcd = 1;
1556 else
1557 GMStatus[i].dcd = 0;
1558
1559 if (status & 0x20 /*UART_MSR_DSR */ )
1560 GMStatus[i].dsr = 1;
1561 else
1562 GMStatus[i].dsr = 0;
1563
1564
1565 if (status & 0x10 /*UART_MSR_CTS */ )
1566 GMStatus[i].cts = 1;
1567 else
1568 GMStatus[i].cts = 0;
1569 }
1570 if (copy_to_user(argp, GMStatus,
1571 sizeof(struct mxser_mstatus) * MXSER_PORTS))
1572 return -EFAULT;
1573 return 0;
1574 case MOXA_ASPP_MON_EXT: {
1575 int status;
1576 int opmode, p;
1577 int shiftbit;
1578 unsigned cflag, iflag;
1579
1580 for (i = 0; i < MXSER_PORTS; i++) {
1581 if (!mxvar_table[i].base)
1582 continue;
1583
1584 status = mxser_get_msr(mxvar_table[i].base, 0,
1585 i, &(mxvar_table[i]));
1586 /*
1587 mxser_check_modem_status(&mxvar_table[i],
1588 status);
1589 */
1590 if (status & UART_MSR_TERI)
1591 mxvar_table[i].icount.rng++;
1592 if (status & UART_MSR_DDSR)
1593 mxvar_table[i].icount.dsr++;
1594 if (status & UART_MSR_DDCD)
1595 mxvar_table[i].icount.dcd++;
1596 if (status & UART_MSR_DCTS)
1597 mxvar_table[i].icount.cts++;
1598
1599 mxvar_table[i].mon_data.modem_status = status;
1600 mon_data_ext.rx_cnt[i] = mxvar_table[i].mon_data.rxcnt;
1601 mon_data_ext.tx_cnt[i] = mxvar_table[i].mon_data.txcnt;
1602 mon_data_ext.up_rxcnt[i] = mxvar_table[i].mon_data.up_rxcnt;
1603 mon_data_ext.up_txcnt[i] = mxvar_table[i].mon_data.up_txcnt;
1604 mon_data_ext.modem_status[i] = mxvar_table[i].mon_data.modem_status;
1605 mon_data_ext.baudrate[i] = mxvar_table[i].realbaud;
1606
1607 if (!mxvar_table[i].tty || !mxvar_table[i].tty->termios) {
1608 cflag = mxvar_table[i].normal_termios.c_cflag;
1609 iflag = mxvar_table[i].normal_termios.c_iflag;
1610 } else {
1611 cflag = mxvar_table[i].tty->termios->c_cflag;
1612 iflag = mxvar_table[i].tty->termios->c_iflag;
1613 }
1614
1615 mon_data_ext.databits[i] = cflag & CSIZE;
1616
1617 mon_data_ext.stopbits[i] = cflag & CSTOPB;
1618
1619 mon_data_ext.parity[i] = cflag & (PARENB | PARODD | CMSPAR);
1620
1621 mon_data_ext.flowctrl[i] = 0x00;
1622
1623 if (cflag & CRTSCTS)
1624 mon_data_ext.flowctrl[i] |= 0x03;
1625
1626 if (iflag & (IXON | IXOFF))
1627 mon_data_ext.flowctrl[i] |= 0x0C;
1628
1629 if (mxvar_table[i].type == PORT_16550A)
1630 mon_data_ext.fifo[i] = 1;
1631 else
1632 mon_data_ext.fifo[i] = 0;
1633
1634 p = i % 4;
1635 shiftbit = p * 2;
1636 opmode = inb(mxvar_table[i].opmode_ioaddr) >> shiftbit;
1637 opmode &= OP_MODE_MASK;
1638
1639 mon_data_ext.iftype[i] = opmode;
1640
1641 }
1642 if (copy_to_user(argp, &mon_data_ext, sizeof(struct mxser_mon_ext)))
1643 return -EFAULT;
1644
1645 return 0;
1646
1647 }
1648 default:
1649 return -ENOIOCTLCMD;
1650 }
1651 return 0;
1652}
1653
1654static void mxser_stoprx(struct tty_struct *tty)
1655{
1656 struct mxser_struct *info = tty->driver_data;
1657 /* unsigned long flags; */
1658
1659 info->ldisc_stop_rx = 1;
1660 if (I_IXOFF(tty)) {
1661 /* MX_LOCK(&info->slock); */
1662 /* following add by Victor Yu. 09-02-2002 */
1663 if (info->IsMoxaMustChipFlag) {
1664 info->IER &= ~MOXA_MUST_RECV_ISR;
1665 outb(info->IER, info->base + UART_IER);
1666 } else {
1667 /* above add by Victor Yu. 09-02-2002 */
1668 info->x_char = STOP_CHAR(tty);
1669 /* mask by Victor Yu. 09-02-2002 */
1670 /* outb(info->IER, 0); */
1671 outb(0, info->base + UART_IER);
1672 info->IER |= UART_IER_THRI;
1673 /* force Tx interrupt */
1674 outb(info->IER, info->base + UART_IER);
1675 } /* add by Victor Yu. 09-02-2002 */
1676 /* MX_UNLOCK(&info->slock); */
1677 }
1678
1679 if (info->tty->termios->c_cflag & CRTSCTS) {
1680 /* MX_LOCK(&info->slock); */
1681 info->MCR &= ~UART_MCR_RTS;
1682 outb(info->MCR, info->base + UART_MCR);
1683 /* MX_UNLOCK(&info->slock); */
1684 }
1685}
1686
1687static void mxser_startrx(struct tty_struct *tty)
1688{
1689 struct mxser_struct *info = tty->driver_data;
1690 /* unsigned long flags; */
1691
1692 info->ldisc_stop_rx = 0;
1693 if (I_IXOFF(tty)) {
1694 if (info->x_char)
1695 info->x_char = 0;
1696 else {
1697 /* MX_LOCK(&info->slock); */
1698
1699 /* following add by Victor Yu. 09-02-2002 */
1700 if (info->IsMoxaMustChipFlag) {
1701 info->IER |= MOXA_MUST_RECV_ISR;
1702 outb(info->IER, info->base + UART_IER);
1703 } else {
1704 /* above add by Victor Yu. 09-02-2002 */
1705
1706 info->x_char = START_CHAR(tty);
1707 /* mask by Victor Yu. 09-02-2002 */
1708 /* outb(info->IER, 0); */
1709 /* add by Victor Yu. 09-02-2002 */
1710 outb(0, info->base + UART_IER);
1711 /* force Tx interrupt */
1712 info->IER |= UART_IER_THRI;
1713 outb(info->IER, info->base + UART_IER);
1714 } /* add by Victor Yu. 09-02-2002 */
1715 /* MX_UNLOCK(&info->slock); */
1716 }
1717 }
1718
1719 if (info->tty->termios->c_cflag & CRTSCTS) {
1720 /* MX_LOCK(&info->slock); */
1721 info->MCR |= UART_MCR_RTS;
1722 outb(info->MCR, info->base + UART_MCR);
1723 /* MX_UNLOCK(&info->slock); */
1724 }
1725}
1726
1727/*
1728 * This routine is called by the upper-layer tty layer to signal that
1729 * incoming characters should be throttled.
1730 */
1731static void mxser_throttle(struct tty_struct *tty)
1732{
1733 /* struct mxser_struct *info = tty->driver_data; */
1734 /* unsigned long flags; */
1735
1736 /* MX_LOCK(&info->slock); */
1737 mxser_stoprx(tty);
1738 /* MX_UNLOCK(&info->slock); */
1739}
1740
1741static void mxser_unthrottle(struct tty_struct *tty)
1742{
1743 /* struct mxser_struct *info = tty->driver_data; */
1744 /* unsigned long flags; */
1745
1746 /* MX_LOCK(&info->slock); */
1747 mxser_startrx(tty);
1748 /* MX_UNLOCK(&info->slock); */
1749}
1750
1751static void mxser_set_termios(struct tty_struct *tty, struct termios *old_termios)
1752{
1753 struct mxser_struct *info = tty->driver_data;
1754 unsigned long flags;
1755
1756 if ((tty->termios->c_cflag != old_termios->c_cflag) ||
1757 (RELEVANT_IFLAG(tty->termios->c_iflag) != RELEVANT_IFLAG(old_termios->c_iflag))) {
1758
1759 mxser_change_speed(info, old_termios);
1760
1761 if ((old_termios->c_cflag & CRTSCTS) &&
1762 !(tty->termios->c_cflag & CRTSCTS)) {
1763 tty->hw_stopped = 0;
1764 mxser_start(tty);
1765 }
1766 }
1767
1768/* Handle sw stopped */
1769 if ((old_termios->c_iflag & IXON) &&
1770 !(tty->termios->c_iflag & IXON)) {
1771 tty->stopped = 0;
1772
1773 /* following add by Victor Yu. 09-02-2002 */
1774 if (info->IsMoxaMustChipFlag) {
1775 spin_lock_irqsave(&info->slock, flags);
1776 DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->base);
1777 spin_unlock_irqrestore(&info->slock, flags);
1778 }
1779 /* above add by Victor Yu. 09-02-2002 */
1780
1781 mxser_start(tty);
1782 }
1783}
1784
1785/*
1786 * mxser_stop() and mxser_start()
1787 *
1788 * This routines are called before setting or resetting tty->stopped.
1789 * They enable or disable transmitter interrupts, as necessary.
1790 */
1791static void mxser_stop(struct tty_struct *tty)
1792{
1793 struct mxser_struct *info = tty->driver_data;
1794 unsigned long flags;
1795
1796 spin_lock_irqsave(&info->slock, flags);
1797 if (info->IER & UART_IER_THRI) {
1798 info->IER &= ~UART_IER_THRI;
1799 outb(info->IER, info->base + UART_IER);
1800 }
1801 spin_unlock_irqrestore(&info->slock, flags);
1802}
1803
1804static void mxser_start(struct tty_struct *tty)
1805{
1806 struct mxser_struct *info = tty->driver_data;
1807 unsigned long flags;
1808
1809 spin_lock_irqsave(&info->slock, flags);
1810 if (info->xmit_cnt && info->xmit_buf && !(info->IER & UART_IER_THRI)) {
1811 info->IER |= UART_IER_THRI;
1812 outb(info->IER, info->base + UART_IER);
1813 }
1814 spin_unlock_irqrestore(&info->slock, flags);
1815}
1816
1817/*
1818 * mxser_wait_until_sent() --- wait until the transmitter is empty
1819 */
1820static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
1821{
1822 struct mxser_struct *info = tty->driver_data;
1823 unsigned long orig_jiffies, char_time;
1824 int lsr;
1825
1826 if (info->type == PORT_UNKNOWN)
1827 return;
1828
1829 if (info->xmit_fifo_size == 0)
1830 return; /* Just in case.... */
1831
1832 orig_jiffies = jiffies;
1833 /*
1834 * Set the check interval to be 1/5 of the estimated time to
1835 * send a single character, and make it at least 1. The check
1836 * interval should also be less than the timeout.
1837 *
1838 * Note: we have to use pretty tight timings here to satisfy
1839 * the NIST-PCTS.
1840 */
1841 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
1842 char_time = char_time / 5;
1843 if (char_time == 0)
1844 char_time = 1;
1845 if (timeout && timeout < char_time)
1846 char_time = timeout;
1847 /*
1848 * If the transmitter hasn't cleared in twice the approximate
1849 * amount of time to send the entire FIFO, it probably won't
1850 * ever clear. This assumes the UART isn't doing flow
1851 * control, which is currently the case. Hence, if it ever
1852 * takes longer than info->timeout, this is probably due to a
1853 * UART bug of some kind. So, we clamp the timeout parameter at
1854 * 2*info->timeout.
1855 */
1856 if (!timeout || timeout > 2 * info->timeout)
1857 timeout = 2 * info->timeout;
1858#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
1859 printk(KERN_DEBUG "In rs_wait_until_sent(%d) check=%lu...",
1860 timeout, char_time);
1861 printk("jiff=%lu...", jiffies);
1862#endif
1863 while (!((lsr = inb(info->base + UART_LSR)) & UART_LSR_TEMT)) {
1864#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
1865 printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
1866#endif
1867 schedule_timeout_interruptible(char_time);
1868 if (signal_pending(current))
1869 break;
1870 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1871 break;
1872 }
1873 set_current_state(TASK_RUNNING);
1874
1875#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
1876 printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
1877#endif
1878}
1879
1880
1881/*
1882 * This routine is called by tty_hangup() when a hangup is signaled.
1883 */
1884void mxser_hangup(struct tty_struct *tty)
1885{
1886 struct mxser_struct *info = tty->driver_data;
1887
1888 mxser_flush_buffer(tty);
1889 mxser_shutdown(info);
1890 info->event = 0;
1891 info->count = 0;
1892 info->flags &= ~ASYNC_NORMAL_ACTIVE;
1893 info->tty = NULL;
1894 wake_up_interruptible(&info->open_wait);
1895}
1896
1897
1898/* added by James 03-12-2004. */
1899/*
1900 * mxser_rs_break() --- routine which turns the break handling on or off
1901 */
1902static void mxser_rs_break(struct tty_struct *tty, int break_state)
1903{
1904 struct mxser_struct *info = tty->driver_data;
1905 unsigned long flags;
1906
1907 spin_lock_irqsave(&info->slock, flags);
1908 if (break_state == -1)
1909 outb(inb(info->base + UART_LCR) | UART_LCR_SBC,
1910 info->base + UART_LCR);
1911 else
1912 outb(inb(info->base + UART_LCR) & ~UART_LCR_SBC,
1913 info->base + UART_LCR);
1914 spin_unlock_irqrestore(&info->slock, flags);
1915}
1916
1917/* (above) added by James. */
1918
1919
1920/*
1921 * This is the serial driver's generic interrupt routine
1922 */
1923static irqreturn_t mxser_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1924{
1925 int status, iir, i;
1926 struct mxser_struct *info;
1927 struct mxser_struct *port;
1928 int max, irqbits, bits, msr;
1929 int pass_counter = 0;
1930 int handled = IRQ_NONE;
1931
1932 port = NULL;
1933 /* spin_lock(&gm_lock); */
1934
1935 for (i = 0; i < MXSER_BOARDS; i++) {
1936 if (dev_id == &(mxvar_table[i * MXSER_PORTS_PER_BOARD])) {
1937 port = dev_id;
1938 break;
1939 }
1940 }
1941
1942 if (i == MXSER_BOARDS)
1943 goto irq_stop;
1944 if (port == 0)
1945 goto irq_stop;
1946 max = mxser_numports[mxsercfg[i].board_type - 1];
1947 while (1) {
1948 irqbits = inb(port->vector) & port->vectormask;
1949 if (irqbits == port->vectormask)
1950 break;
1951
1952 handled = IRQ_HANDLED;
1953 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
1954 if (irqbits == port->vectormask)
1955 break;
1956 if (bits & irqbits)
1957 continue;
1958 info = port + i;
1959
1960 /* following add by Victor Yu. 09-13-2002 */
1961 iir = inb(info->base + UART_IIR);
1962 if (iir & UART_IIR_NO_INT)
1963 continue;
1964 iir &= MOXA_MUST_IIR_MASK;
1965 if (!info->tty) {
1966 status = inb(info->base + UART_LSR);
1967 outb(0x27, info->base + UART_FCR);
1968 inb(info->base + UART_MSR);
1969 continue;
1970 }
1971 /* above add by Victor Yu. 09-13-2002 */
1972 /*
1973 if (info->tty->flip.count < TTY_FLIPBUF_SIZE / 4) {
1974 info->IER |= MOXA_MUST_RECV_ISR;
1975 outb(info->IER, info->base + UART_IER);
1976 }
1977 */
1978
1979
1980 /* mask by Victor Yu. 09-13-2002
1981 if ( !info->tty ||
1982 (inb(info->base + UART_IIR) & UART_IIR_NO_INT) )
1983 continue;
1984 */
1985 /* mask by Victor Yu. 09-02-2002
1986 status = inb(info->base + UART_LSR) & info->read_status_mask;
1987 */
1988
1989 /* following add by Victor Yu. 09-02-2002 */
1990 status = inb(info->base + UART_LSR);
1991
1992 if (status & UART_LSR_PE)
1993 info->err_shadow |= NPPI_NOTIFY_PARITY;
1994 if (status & UART_LSR_FE)
1995 info->err_shadow |= NPPI_NOTIFY_FRAMING;
1996 if (status & UART_LSR_OE)
1997 info->err_shadow |= NPPI_NOTIFY_HW_OVERRUN;
1998 if (status & UART_LSR_BI)
1999 info->err_shadow |= NPPI_NOTIFY_BREAK;
2000
2001 if (info->IsMoxaMustChipFlag) {
2002 /*
2003 if ( (status & 0x02) && !(status & 0x01) ) {
2004 outb(info->base+UART_FCR, 0x23);
2005 continue;
2006 }
2007 */
2008 if (iir == MOXA_MUST_IIR_GDA ||
2009 iir == MOXA_MUST_IIR_RDA ||
2010 iir == MOXA_MUST_IIR_RTO ||
2011 iir == MOXA_MUST_IIR_LSR)
2012 mxser_receive_chars(info, &status);
2013
2014 } else {
2015 /* above add by Victor Yu. 09-02-2002 */
2016
2017 status &= info->read_status_mask;
2018 if (status & UART_LSR_DR)
2019 mxser_receive_chars(info, &status);
2020 }
2021 msr = inb(info->base + UART_MSR);
2022 if (msr & UART_MSR_ANY_DELTA) {
2023 mxser_check_modem_status(info, msr);
2024 }
2025 /* following add by Victor Yu. 09-13-2002 */
2026 if (info->IsMoxaMustChipFlag) {
2027 if ((iir == 0x02) && (status & UART_LSR_THRE)) {
2028 mxser_transmit_chars(info);
2029 }
2030 } else {
2031 /* above add by Victor Yu. 09-13-2002 */
2032
2033 if (status & UART_LSR_THRE) {
2034/* 8-2-99 by William
2035 if ( info->x_char || (info->xmit_cnt > 0) )
2036*/
2037 mxser_transmit_chars(info);
2038 }
2039 }
2040 }
2041 if (pass_counter++ > MXSER_ISR_PASS_LIMIT) {
2042 break; /* Prevent infinite loops */
2043 }
2044 }
2045
2046 irq_stop:
2047 /* spin_unlock(&gm_lock); */
2048 return handled;
2049}
2050
2051static void mxser_receive_chars(struct mxser_struct *info, int *status)
2052{
2053 struct tty_struct *tty = info->tty;
2054 unsigned char ch, gdl;
2055 int ignored = 0;
2056 int cnt = 0;
2057 int recv_room;
2058 int max = 256;
2059 unsigned long flags;
2060
2061 spin_lock_irqsave(&info->slock, flags);
2062
2063 recv_room = tty->receive_room;
2064 if ((recv_room == 0) && (!info->ldisc_stop_rx)) {
2065 /* mxser_throttle(tty); */
2066 mxser_stoprx(tty);
2067 /* return; */
2068 }
2069
2070 /* following add by Victor Yu. 09-02-2002 */
2071 if (info->IsMoxaMustChipFlag != MOXA_OTHER_UART) {
2072
2073 if (*status & UART_LSR_SPECIAL) {
2074 goto intr_old;
2075 }
2076 /* following add by Victor Yu. 02-11-2004 */
2077 if (info->IsMoxaMustChipFlag == MOXA_MUST_MU860_HWID &&
2078 (*status & MOXA_MUST_LSR_RERR))
2079 goto intr_old;
2080 /* above add by Victor Yu. 02-14-2004 */
2081 if (*status & MOXA_MUST_LSR_RERR)
2082 goto intr_old;
2083
2084 gdl = inb(info->base + MOXA_MUST_GDL_REGISTER);
2085
2086 /* add by Victor Yu. 02-11-2004 */
2087 if (info->IsMoxaMustChipFlag == MOXA_MUST_MU150_HWID)
2088 gdl &= MOXA_MUST_GDL_MASK;
2089 if (gdl >= recv_room) {
2090 if (!info->ldisc_stop_rx) {
2091 /* mxser_throttle(tty); */
2092 mxser_stoprx(tty);
2093 }
2094 /* return; */
2095 }
2096 while (gdl--) {
2097 ch = inb(info->base + UART_RX);
2098 tty_insert_flip_char(tty, ch, 0);
2099 cnt++;
2100 /*
2101 if ((cnt >= HI_WATER) && (info->stop_rx == 0)) {
2102 mxser_stoprx(tty);
2103 info->stop_rx = 1;
2104 break;
2105 } */
2106 }
2107 goto end_intr;
2108 }
2109 intr_old:
2110 /* above add by Victor Yu. 09-02-2002 */
2111
2112 do {
2113 if (max-- < 0)
2114 break;
2115 /*
2116 if ((cnt >= HI_WATER) && (info->stop_rx == 0)) {
2117 mxser_stoprx(tty);
2118 info->stop_rx=1;
2119 break;
2120 }
2121 */
2122
2123 ch = inb(info->base + UART_RX);
2124 /* following add by Victor Yu. 09-02-2002 */
2125 if (info->IsMoxaMustChipFlag && (*status & UART_LSR_OE) /*&& !(*status&UART_LSR_DR) */ )
2126 outb(0x23, info->base + UART_FCR);
2127 *status &= info->read_status_mask;
2128 /* above add by Victor Yu. 09-02-2002 */
2129 if (*status & info->ignore_status_mask) {
2130 if (++ignored > 100)
2131 break;
2132 } else {
2133 char flag = 0;
2134 if (*status & UART_LSR_SPECIAL) {
2135 if (*status & UART_LSR_BI) {
2136 flag = TTY_BREAK;
2137/* added by casper 1/11/2000 */
2138 info->icount.brk++;
2139/* */
2140 if (info->flags & ASYNC_SAK)
2141 do_SAK(tty);
2142 } else if (*status & UART_LSR_PE) {
2143 flag = TTY_PARITY;
2144/* added by casper 1/11/2000 */
2145 info->icount.parity++;
2146/* */
2147 } else if (*status & UART_LSR_FE) {
2148 flag = TTY_FRAME;
2149/* added by casper 1/11/2000 */
2150 info->icount.frame++;
2151/* */
2152 } else if (*status & UART_LSR_OE) {
2153 flag = TTY_OVERRUN;
2154/* added by casper 1/11/2000 */
2155 info->icount.overrun++;
2156/* */
2157 }
2158 }
2159 tty_insert_flip_char(tty, ch, flag);
2160 cnt++;
2161 if (cnt >= recv_room) {
2162 if (!info->ldisc_stop_rx) {
2163 /* mxser_throttle(tty); */
2164 mxser_stoprx(tty);
2165 }
2166 break;
2167 }
2168
2169 }
2170
2171 /* following add by Victor Yu. 09-02-2002 */
2172 if (info->IsMoxaMustChipFlag)
2173 break;
2174 /* above add by Victor Yu. 09-02-2002 */
2175
2176 /* mask by Victor Yu. 09-02-2002
2177 *status = inb(info->base + UART_LSR) & info->read_status_mask;
2178 */
2179 /* following add by Victor Yu. 09-02-2002 */
2180 *status = inb(info->base + UART_LSR);
2181 /* above add by Victor Yu. 09-02-2002 */
2182 } while (*status & UART_LSR_DR);
2183
2184end_intr: /* add by Victor Yu. 09-02-2002 */
2185 mxvar_log.rxcnt[info->port] += cnt;
2186 info->mon_data.rxcnt += cnt;
2187 info->mon_data.up_rxcnt += cnt;
2188 spin_unlock_irqrestore(&info->slock, flags);
2189
2190 tty_flip_buffer_push(tty);
2191}
2192
2193static void mxser_transmit_chars(struct mxser_struct *info)
2194{
2195 int count, cnt;
2196 unsigned long flags;
2197
2198 spin_lock_irqsave(&info->slock, flags);
2199
2200 if (info->x_char) {
2201 outb(info->x_char, info->base + UART_TX);
2202 info->x_char = 0;
2203 mxvar_log.txcnt[info->port]++;
2204 info->mon_data.txcnt++;
2205 info->mon_data.up_txcnt++;
2206
2207/* added by casper 1/11/2000 */
2208 info->icount.tx++;
2209/* */
2210 spin_unlock_irqrestore(&info->slock, flags);
2211 return;
2212 }
2213
2214 if (info->xmit_buf == 0) {
2215 spin_unlock_irqrestore(&info->slock, flags);
2216 return;
2217 }
2218
2219 if ((info->xmit_cnt <= 0) || info->tty->stopped ||
2220 (info->tty->hw_stopped &&
2221 (info->type != PORT_16550A) &&
2222 (!info->IsMoxaMustChipFlag))) {
2223 info->IER &= ~UART_IER_THRI;
2224 outb(info->IER, info->base + UART_IER);
2225 spin_unlock_irqrestore(&info->slock, flags);
2226 return;
2227 }
2228
2229 cnt = info->xmit_cnt;
2230 count = info->xmit_fifo_size;
2231 do {
2232 outb(info->xmit_buf[info->xmit_tail++],
2233 info->base + UART_TX);
2234 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE - 1);
2235 if (--info->xmit_cnt <= 0)
2236 break;
2237 } while (--count > 0);
2238 mxvar_log.txcnt[info->port] += (cnt - info->xmit_cnt);
2239
2240/* added by James 03-12-2004. */
2241 info->mon_data.txcnt += (cnt - info->xmit_cnt);
2242 info->mon_data.up_txcnt += (cnt - info->xmit_cnt);
2243/* (above) added by James. */
2244
2245/* added by casper 1/11/2000 */
2246 info->icount.tx += (cnt - info->xmit_cnt);
2247/* */
2248
2249 if (info->xmit_cnt < WAKEUP_CHARS) {
2250 set_bit(MXSER_EVENT_TXLOW, &info->event);
2251 schedule_work(&info->tqueue);
2252 }
2253 if (info->xmit_cnt <= 0) {
2254 info->IER &= ~UART_IER_THRI;
2255 outb(info->IER, info->base + UART_IER);
2256 }
2257 spin_unlock_irqrestore(&info->slock, flags);
2258}
2259
2260static void mxser_check_modem_status(struct mxser_struct *info, int status)
2261{
2262 /* update input line counters */
2263 if (status & UART_MSR_TERI)
2264 info->icount.rng++;
2265 if (status & UART_MSR_DDSR)
2266 info->icount.dsr++;
2267 if (status & UART_MSR_DDCD)
2268 info->icount.dcd++;
2269 if (status & UART_MSR_DCTS)
2270 info->icount.cts++;
2271 info->mon_data.modem_status = status;
2272 wake_up_interruptible(&info->delta_msr_wait);
2273
2274 if ((info->flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) {
2275 if (status & UART_MSR_DCD)
2276 wake_up_interruptible(&info->open_wait);
2277 schedule_work(&info->tqueue);
2278 }
2279
2280 if (info->flags & ASYNC_CTS_FLOW) {
2281 if (info->tty->hw_stopped) {
2282 if (status & UART_MSR_CTS) {
2283 info->tty->hw_stopped = 0;
2284
2285 if ((info->type != PORT_16550A) &&
2286 (!info->IsMoxaMustChipFlag)) {
2287 info->IER |= UART_IER_THRI;
2288 outb(info->IER, info->base + UART_IER);
2289 }
2290 set_bit(MXSER_EVENT_TXLOW, &info->event);
2291 schedule_work(&info->tqueue); }
2292 } else {
2293 if (!(status & UART_MSR_CTS)) {
2294 info->tty->hw_stopped = 1;
2295 if ((info->type != PORT_16550A) &&
2296 (!info->IsMoxaMustChipFlag)) {
2297 info->IER &= ~UART_IER_THRI;
2298 outb(info->IER, info->base + UART_IER);
2299 }
2300 }
2301 }
2302 }
2303}
2304
2305static int mxser_block_til_ready(struct tty_struct *tty, struct file *filp, struct mxser_struct *info)
2306{
2307 DECLARE_WAITQUEUE(wait, current);
2308 int retval;
2309 int do_clocal = 0;
2310 unsigned long flags;
2311
2312 /*
2313 * If non-blocking mode is set, or the port is not enabled,
2314 * then make the check up front and then exit.
2315 */
2316 if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) {
2317 info->flags |= ASYNC_NORMAL_ACTIVE;
2318 return 0;
2319 }
2320
2321 if (tty->termios->c_cflag & CLOCAL)
2322 do_clocal = 1;
2323
2324 /*
2325 * Block waiting for the carrier detect and the line to become
2326 * free (i.e., not in use by the callout). While we are in
2327 * this loop, info->count is dropped by one, so that
2328 * mxser_close() knows when to free things. We restore it upon
2329 * exit, either normal or abnormal.
2330 */
2331 retval = 0;
2332 add_wait_queue(&info->open_wait, &wait);
2333
2334 spin_lock_irqsave(&info->slock, flags);
2335 if (!tty_hung_up_p(filp))
2336 info->count--;
2337 spin_unlock_irqrestore(&info->slock, flags);
2338 info->blocked_open++;
2339 while (1) {
2340 spin_lock_irqsave(&info->slock, flags);
2341 outb(inb(info->base + UART_MCR) |
2342 UART_MCR_DTR | UART_MCR_RTS, info->base + UART_MCR);
2343 spin_unlock_irqrestore(&info->slock, flags);
2344 set_current_state(TASK_INTERRUPTIBLE);
2345 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)) {
2346 if (info->flags & ASYNC_HUP_NOTIFY)
2347 retval = -EAGAIN;
2348 else
2349 retval = -ERESTARTSYS;
2350 break;
2351 }
2352 if (!(info->flags & ASYNC_CLOSING) &&
2353 (do_clocal ||
2354 (inb(info->base + UART_MSR) & UART_MSR_DCD)))
2355 break;
2356 if (signal_pending(current)) {
2357 retval = -ERESTARTSYS;
2358 break;
2359 }
2360 schedule();
2361 }
2362 set_current_state(TASK_RUNNING);
2363 remove_wait_queue(&info->open_wait, &wait);
2364 if (!tty_hung_up_p(filp))
2365 info->count++;
2366 info->blocked_open--;
2367 if (retval)
2368 return retval;
2369 info->flags |= ASYNC_NORMAL_ACTIVE;
2370 return 0;
2371}
2372
2373static int mxser_startup(struct mxser_struct *info)
2374{
2375 unsigned long page;
2376 unsigned long flags;
2377
2378 page = __get_free_page(GFP_KERNEL);
2379 if (!page)
2380 return -ENOMEM;
2381
2382 spin_lock_irqsave(&info->slock, flags);
2383
2384 if (info->flags & ASYNC_INITIALIZED) {
2385 free_page(page);
2386 spin_unlock_irqrestore(&info->slock, flags);
2387 return 0;
2388 }
2389
2390 if (!info->base || !info->type) {
2391 if (info->tty)
2392 set_bit(TTY_IO_ERROR, &info->tty->flags);
2393 free_page(page);
2394 spin_unlock_irqrestore(&info->slock, flags);
2395 return 0;
2396 }
2397 if (info->xmit_buf)
2398 free_page(page);
2399 else
2400 info->xmit_buf = (unsigned char *) page;
2401
2402 /*
2403 * Clear the FIFO buffers and disable them
2404 * (they will be reenabled in mxser_change_speed())
2405 */
2406 if (info->IsMoxaMustChipFlag)
2407 outb((UART_FCR_CLEAR_RCVR |
2408 UART_FCR_CLEAR_XMIT |
2409 MOXA_MUST_FCR_GDA_MODE_ENABLE), info->base + UART_FCR);
2410 else
2411 outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
2412 info->base + UART_FCR);
2413
2414 /*
2415 * At this point there's no way the LSR could still be 0xFF;
2416 * if it is, then bail out, because there's likely no UART
2417 * here.
2418 */
2419 if (inb(info->base + UART_LSR) == 0xff) {
2420 spin_unlock_irqrestore(&info->slock, flags);
2421 if (capable(CAP_SYS_ADMIN)) {
2422 if (info->tty)
2423 set_bit(TTY_IO_ERROR, &info->tty->flags);
2424 return 0;
2425 } else
2426 return -ENODEV;
2427 }
2428
2429 /*
2430 * Clear the interrupt registers.
2431 */
2432 (void) inb(info->base + UART_LSR);
2433 (void) inb(info->base + UART_RX);
2434 (void) inb(info->base + UART_IIR);
2435 (void) inb(info->base + UART_MSR);
2436
2437 /*
2438 * Now, initialize the UART
2439 */
2440 outb(UART_LCR_WLEN8, info->base + UART_LCR); /* reset DLAB */
2441 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
2442 outb(info->MCR, info->base + UART_MCR);
2443
2444 /*
2445 * Finally, enable interrupts
2446 */
2447 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
2448 /* info->IER = UART_IER_RLSI | UART_IER_RDI; */
2449
2450 /* following add by Victor Yu. 08-30-2002 */
2451 if (info->IsMoxaMustChipFlag)
2452 info->IER |= MOXA_MUST_IER_EGDAI;
2453 /* above add by Victor Yu. 08-30-2002 */
2454 outb(info->IER, info->base + UART_IER); /* enable interrupts */
2455
2456 /*
2457 * And clear the interrupt registers again for luck.
2458 */
2459 (void) inb(info->base + UART_LSR);
2460 (void) inb(info->base + UART_RX);
2461 (void) inb(info->base + UART_IIR);
2462 (void) inb(info->base + UART_MSR);
2463
2464 if (info->tty)
2465 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2466 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2467
2468 /*
2469 * and set the speed of the serial port
2470 */
2471 spin_unlock_irqrestore(&info->slock, flags);
2472 mxser_change_speed(info, NULL);
2473
2474 info->flags |= ASYNC_INITIALIZED;
2475 return 0;
2476}
2477
2478/*
2479 * This routine will shutdown a serial port; interrupts maybe disabled, and
2480 * DTR is dropped if the hangup on close termio flag is on.
2481 */
2482static void mxser_shutdown(struct mxser_struct *info)
2483{
2484 unsigned long flags;
2485
2486 if (!(info->flags & ASYNC_INITIALIZED))
2487 return;
2488
2489 spin_lock_irqsave(&info->slock, flags);
2490
2491 /*
2492 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
2493 * here so the queue might never be waken up
2494 */
2495 wake_up_interruptible(&info->delta_msr_wait);
2496
2497 /*
2498 * Free the IRQ, if necessary
2499 */
2500 if (info->xmit_buf) {
2501 free_page((unsigned long) info->xmit_buf);
2502 info->xmit_buf = NULL;
2503 }
2504
2505 info->IER = 0;
2506 outb(0x00, info->base + UART_IER);
2507
2508 if (!info->tty || (info->tty->termios->c_cflag & HUPCL))
2509 info->MCR &= ~(UART_MCR_DTR | UART_MCR_RTS);
2510 outb(info->MCR, info->base + UART_MCR);
2511
2512 /* clear Rx/Tx FIFO's */
2513 /* following add by Victor Yu. 08-30-2002 */
2514 if (info->IsMoxaMustChipFlag)
2515 outb((UART_FCR_CLEAR_RCVR |
2516 UART_FCR_CLEAR_XMIT |
2517 MOXA_MUST_FCR_GDA_MODE_ENABLE), info->base + UART_FCR);
2518 else
2519 /* above add by Victor Yu. 08-30-2002 */
2520 outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
2521 info->base + UART_FCR);
2522
2523 /* read data port to reset things */
2524 (void) inb(info->base + UART_RX);
2525
2526 if (info->tty)
2527 set_bit(TTY_IO_ERROR, &info->tty->flags);
2528
2529 info->flags &= ~ASYNC_INITIALIZED;
2530
2531 /* following add by Victor Yu. 09-23-2002 */
2532 if (info->IsMoxaMustChipFlag)
2533 SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(info->base);
2534 /* above add by Victor Yu. 09-23-2002 */
2535
2536 spin_unlock_irqrestore(&info->slock, flags);
2537}
2538
2539/*
2540 * This routine is called to set the UART divisor registers to match
2541 * the specified baud rate for a serial port.
2542 */
2543static int mxser_change_speed(struct mxser_struct *info, struct termios *old_termios)
2544{
2545 unsigned cflag, cval, fcr;
2546 int ret = 0;
2547 unsigned char status;
2548 long baud;
2549 unsigned long flags;
2550
2551 if (!info->tty || !info->tty->termios)
2552 return ret;
2553 cflag = info->tty->termios->c_cflag;
2554 if (!(info->base))
2555 return ret;
2556
2557#ifndef B921600
2558#define B921600 (B460800 +1)
2559#endif
2560 if (mxser_set_baud_method[info->port] == 0) {
2561 baud = tty_get_baud_rate(info->tty);
2562 mxser_set_baud(info, baud);
2563 }
2564
2565 /* byte size and parity */
2566 switch (cflag & CSIZE) {
2567 case CS5:
2568 cval = 0x00;
2569 break;
2570 case CS6:
2571 cval = 0x01;
2572 break;
2573 case CS7:
2574 cval = 0x02;
2575 break;
2576 case CS8:
2577 cval = 0x03;
2578 break;
2579 default:
2580 cval = 0x00;
2581 break; /* too keep GCC shut... */
2582 }
2583 if (cflag & CSTOPB)
2584 cval |= 0x04;
2585 if (cflag & PARENB)
2586 cval |= UART_LCR_PARITY;
2587 if (!(cflag & PARODD))
2588 cval |= UART_LCR_EPAR;
2589 if (cflag & CMSPAR)
2590 cval |= UART_LCR_SPAR;
2591
2592 if ((info->type == PORT_8250) || (info->type == PORT_16450)) {
2593 if (info->IsMoxaMustChipFlag) {
2594 fcr = UART_FCR_ENABLE_FIFO;
2595 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
2596 SET_MOXA_MUST_FIFO_VALUE(info);
2597 } else
2598 fcr = 0;
2599 } else {
2600 fcr = UART_FCR_ENABLE_FIFO;
2601 /* following add by Victor Yu. 08-30-2002 */
2602 if (info->IsMoxaMustChipFlag) {
2603 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
2604 SET_MOXA_MUST_FIFO_VALUE(info);
2605 } else {
2606 /* above add by Victor Yu. 08-30-2002 */
2607 switch (info->rx_trigger) {
2608 case 1:
2609 fcr |= UART_FCR_TRIGGER_1;
2610 break;
2611 case 4:
2612 fcr |= UART_FCR_TRIGGER_4;
2613 break;
2614 case 8:
2615 fcr |= UART_FCR_TRIGGER_8;
2616 break;
2617 default:
2618 fcr |= UART_FCR_TRIGGER_14;
2619 break;
2620 }
2621 }
2622 }
2623
2624 /* CTS flow control flag and modem status interrupts */
2625 info->IER &= ~UART_IER_MSI;
2626 info->MCR &= ~UART_MCR_AFE;
2627 if (cflag & CRTSCTS) {
2628 info->flags |= ASYNC_CTS_FLOW;
2629 info->IER |= UART_IER_MSI;
2630 if ((info->type == PORT_16550A) || (info->IsMoxaMustChipFlag)) {
2631 info->MCR |= UART_MCR_AFE;
2632 /* status = mxser_get_msr(info->base, 0, info->port); */
2633/*
2634 save_flags(flags);
2635 cli();
2636 status = inb(baseaddr + UART_MSR);
2637 restore_flags(flags);
2638*/
2639 /* mxser_check_modem_status(info, status); */
2640 } else {
2641 /* status = mxser_get_msr(info->base, 0, info->port); */
2642 /* MX_LOCK(&info->slock); */
2643 status = inb(info->base + UART_MSR);
2644 /* MX_UNLOCK(&info->slock); */
2645 if (info->tty->hw_stopped) {
2646 if (status & UART_MSR_CTS) {
2647 info->tty->hw_stopped = 0;
2648 if ((info->type != PORT_16550A) &&
2649 (!info->IsMoxaMustChipFlag)) {
2650 info->IER |= UART_IER_THRI;
2651 outb(info->IER, info->base + UART_IER);
2652 }
2653 set_bit(MXSER_EVENT_TXLOW, &info->event);
2654 schedule_work(&info->tqueue); }
2655 } else {
2656 if (!(status & UART_MSR_CTS)) {
2657 info->tty->hw_stopped = 1;
2658 if ((info->type != PORT_16550A) &&
2659 (!info->IsMoxaMustChipFlag)) {
2660 info->IER &= ~UART_IER_THRI;
2661 outb(info->IER, info->base + UART_IER);
2662 }
2663 }
2664 }
2665 }
2666 } else {
2667 info->flags &= ~ASYNC_CTS_FLOW;
2668 }
2669 outb(info->MCR, info->base + UART_MCR);
2670 if (cflag & CLOCAL) {
2671 info->flags &= ~ASYNC_CHECK_CD;
2672 } else {
2673 info->flags |= ASYNC_CHECK_CD;
2674 info->IER |= UART_IER_MSI;
2675 }
2676 outb(info->IER, info->base + UART_IER);
2677
2678 /*
2679 * Set up parity check flag
2680 */
2681 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2682 if (I_INPCK(info->tty))
2683 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2684 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2685 info->read_status_mask |= UART_LSR_BI;
2686
2687 info->ignore_status_mask = 0;
2688
2689 if (I_IGNBRK(info->tty)) {
2690 info->ignore_status_mask |= UART_LSR_BI;
2691 info->read_status_mask |= UART_LSR_BI;
2692 /*
2693 * If we're ignore parity and break indicators, ignore
2694 * overruns too. (For real raw support).
2695 */
2696 if (I_IGNPAR(info->tty)) {
2697 info->ignore_status_mask |=
2698 UART_LSR_OE |
2699 UART_LSR_PE |
2700 UART_LSR_FE;
2701 info->read_status_mask |=
2702 UART_LSR_OE |
2703 UART_LSR_PE |
2704 UART_LSR_FE;
2705 }
2706 }
2707 /* following add by Victor Yu. 09-02-2002 */
2708 if (info->IsMoxaMustChipFlag) {
2709 spin_lock_irqsave(&info->slock, flags);
2710 SET_MOXA_MUST_XON1_VALUE(info->base, START_CHAR(info->tty));
2711 SET_MOXA_MUST_XOFF1_VALUE(info->base, STOP_CHAR(info->tty));
2712 if (I_IXON(info->tty)) {
2713 ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->base);
2714 } else {
2715 DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->base);
2716 }
2717 if (I_IXOFF(info->tty)) {
2718 ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->base);
2719 } else {
2720 DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->base);
2721 }
2722 /*
2723 if ( I_IXANY(info->tty) ) {
2724 info->MCR |= MOXA_MUST_MCR_XON_ANY;
2725 ENABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(info->base);
2726 } else {
2727 info->MCR &= ~MOXA_MUST_MCR_XON_ANY;
2728 DISABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(info->base);
2729 }
2730 */
2731 spin_unlock_irqrestore(&info->slock, flags);
2732 }
2733 /* above add by Victor Yu. 09-02-2002 */
2734
2735
2736 outb(fcr, info->base + UART_FCR); /* set fcr */
2737 outb(cval, info->base + UART_LCR);
2738
2739 return ret;
2740}
2741
2742
2743static int mxser_set_baud(struct mxser_struct *info, long newspd)
2744{
2745 int quot = 0;
2746 unsigned char cval;
2747 int ret = 0;
2748 unsigned long flags;
2749
2750 if (!info->tty || !info->tty->termios)
2751 return ret;
2752
2753 if (!(info->base))
2754 return ret;
2755
2756 if (newspd > info->MaxCanSetBaudRate)
2757 return 0;
2758
2759 info->realbaud = newspd;
2760 if (newspd == 134) {
2761 quot = (2 * info->baud_base / 269);
2762 } else if (newspd) {
2763 quot = info->baud_base / newspd;
2764 if (quot == 0)
2765 quot = 1;
2766 } else {
2767 quot = 0;
2768 }
2769
2770 info->timeout = ((info->xmit_fifo_size * HZ * 10 * quot) / info->baud_base);
2771 info->timeout += HZ / 50; /* Add .02 seconds of slop */
2772
2773 if (quot) {
2774 spin_lock_irqsave(&info->slock, flags);
2775 info->MCR |= UART_MCR_DTR;
2776 outb(info->MCR, info->base + UART_MCR);
2777 spin_unlock_irqrestore(&info->slock, flags);
2778 } else {
2779 spin_lock_irqsave(&info->slock, flags);
2780 info->MCR &= ~UART_MCR_DTR;
2781 outb(info->MCR, info->base + UART_MCR);
2782 spin_unlock_irqrestore(&info->slock, flags);
2783 return ret;
2784 }
2785
2786 cval = inb(info->base + UART_LCR);
2787
2788 outb(cval | UART_LCR_DLAB, info->base + UART_LCR); /* set DLAB */
2789
2790 outb(quot & 0xff, info->base + UART_DLL); /* LS of divisor */
2791 outb(quot >> 8, info->base + UART_DLM); /* MS of divisor */
2792 outb(cval, info->base + UART_LCR); /* reset DLAB */
2793
2794
2795 return ret;
2796}
2797
2798/*
2799 * ------------------------------------------------------------
2800 * friends of mxser_ioctl()
2801 * ------------------------------------------------------------
2802 */
2803static int mxser_get_serial_info(struct mxser_struct *info, struct serial_struct __user *retinfo)
2804{
2805 struct serial_struct tmp;
2806
2807 if (!retinfo)
2808 return -EFAULT;
2809 memset(&tmp, 0, sizeof(tmp));
2810 tmp.type = info->type;
2811 tmp.line = info->port;
2812 tmp.port = info->base;
2813 tmp.irq = info->irq;
2814 tmp.flags = info->flags;
2815 tmp.baud_base = info->baud_base;
2816 tmp.close_delay = info->close_delay;
2817 tmp.closing_wait = info->closing_wait;
2818 tmp.custom_divisor = info->custom_divisor;
2819 tmp.hub6 = 0;
2820 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
2821 return -EFAULT;
2822 return 0;
2823}
2824
2825static int mxser_set_serial_info(struct mxser_struct *info, struct serial_struct __user *new_info)
2826{
2827 struct serial_struct new_serial;
2828 unsigned int flags;
2829 int retval = 0;
2830
2831 if (!new_info || !info->base)
2832 return -EFAULT;
2833 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
2834 return -EFAULT;
2835
2836 if ((new_serial.irq != info->irq) ||
2837 (new_serial.port != info->base) ||
2838 (new_serial.custom_divisor != info->custom_divisor) ||
2839 (new_serial.baud_base != info->baud_base))
2840 return -EPERM;
2841
2842 flags = info->flags & ASYNC_SPD_MASK;
2843
2844 if (!capable(CAP_SYS_ADMIN)) {
2845 if ((new_serial.baud_base != info->baud_base) ||
2846 (new_serial.close_delay != info->close_delay) ||
2847 ((new_serial.flags & ~ASYNC_USR_MASK) != (info->flags & ~ASYNC_USR_MASK)))
2848 return -EPERM;
2849 info->flags = ((info->flags & ~ASYNC_USR_MASK) |
2850 (new_serial.flags & ASYNC_USR_MASK));
2851 } else {
2852 /*
2853 * OK, past this point, all the error checking has been done.
2854 * At this point, we start making changes.....
2855 */
2856 info->flags = ((info->flags & ~ASYNC_FLAGS) |
2857 (new_serial.flags & ASYNC_FLAGS));
2858 info->close_delay = new_serial.close_delay * HZ / 100;
2859 info->closing_wait = new_serial.closing_wait * HZ / 100;
2860 info->tty->low_latency =
2861 (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
2862 info->tty->low_latency = 0; /* (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; */
2863 }
2864
2865 /* added by casper, 3/17/2000, for mouse */
2866 info->type = new_serial.type;
2867
2868 process_txrx_fifo(info);
2869
2870 if (info->flags & ASYNC_INITIALIZED) {
2871 if (flags != (info->flags & ASYNC_SPD_MASK)) {
2872 mxser_change_speed(info, NULL);
2873 }
2874 } else {
2875 retval = mxser_startup(info);
2876 }
2877 return retval;
2878}
2879
2880/*
2881 * mxser_get_lsr_info - get line status register info
2882 *
2883 * Purpose: Let user call ioctl() to get info when the UART physically
2884 * is emptied. On bus types like RS485, the transmitter must
2885 * release the bus after transmitting. This must be done when
2886 * the transmit shift register is empty, not be done when the
2887 * transmit holding register is empty. This functionality
2888 * allows an RS485 driver to be written in user space.
2889 */
2890static int mxser_get_lsr_info(struct mxser_struct *info, unsigned int __user *value)
2891{
2892 unsigned char status;
2893 unsigned int result;
2894 unsigned long flags;
2895
2896 spin_lock_irqsave(&info->slock, flags);
2897 status = inb(info->base + UART_LSR);
2898 spin_unlock_irqrestore(&info->slock, flags);
2899 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
2900 return put_user(result, value);
2901}
2902
2903/*
2904 * This routine sends a break character out the serial port.
2905 */
2906static void mxser_send_break(struct mxser_struct *info, int duration)
2907{
2908 unsigned long flags;
2909
2910 if (!info->base)
2911 return;
2912 set_current_state(TASK_INTERRUPTIBLE);
2913 spin_lock_irqsave(&info->slock, flags);
2914 outb(inb(info->base + UART_LCR) | UART_LCR_SBC,
2915 info->base + UART_LCR);
2916 spin_unlock_irqrestore(&info->slock, flags);
2917 schedule_timeout(duration);
2918 spin_lock_irqsave(&info->slock, flags);
2919 outb(inb(info->base + UART_LCR) & ~UART_LCR_SBC,
2920 info->base + UART_LCR);
2921 spin_unlock_irqrestore(&info->slock, flags);
2922}
2923
2924static int mxser_tiocmget(struct tty_struct *tty, struct file *file)
2925{
2926 struct mxser_struct *info = tty->driver_data;
2927 unsigned char control, status;
2928 unsigned long flags;
2929
2930
2931 if (tty->index == MXSER_PORTS)
2932 return -ENOIOCTLCMD;
2933 if (tty->flags & (1 << TTY_IO_ERROR))
2934 return -EIO;
2935
2936 control = info->MCR;
2937
2938 spin_lock_irqsave(&info->slock, flags);
2939 status = inb(info->base + UART_MSR);
2940 if (status & UART_MSR_ANY_DELTA)
2941 mxser_check_modem_status(info, status);
2942 spin_unlock_irqrestore(&info->slock, flags);
2943 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
2944 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
2945 ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) |
2946 ((status & UART_MSR_RI) ? TIOCM_RNG : 0) |
2947 ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) |
2948 ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
2949}
2950
2951static int mxser_tiocmset(struct tty_struct *tty, struct file *file, unsigned int set, unsigned int clear)
2952{
2953 struct mxser_struct *info = tty->driver_data;
2954 unsigned long flags;
2955
2956
2957 if (tty->index == MXSER_PORTS)
2958 return -ENOIOCTLCMD;
2959 if (tty->flags & (1 << TTY_IO_ERROR))
2960 return -EIO;
2961
2962 spin_lock_irqsave(&info->slock, flags);
2963
2964 if (set & TIOCM_RTS)
2965 info->MCR |= UART_MCR_RTS;
2966 if (set & TIOCM_DTR)
2967 info->MCR |= UART_MCR_DTR;
2968
2969 if (clear & TIOCM_RTS)
2970 info->MCR &= ~UART_MCR_RTS;
2971 if (clear & TIOCM_DTR)
2972 info->MCR &= ~UART_MCR_DTR;
2973
2974 outb(info->MCR, info->base + UART_MCR);
2975 spin_unlock_irqrestore(&info->slock, flags);
2976 return 0;
2977}
2978
2979
2980static int mxser_read_register(int, unsigned short *);
2981static int mxser_program_mode(int);
2982static void mxser_normal_mode(int);
2983
2984static int mxser_get_ISA_conf(int cap, struct mxser_hwconf *hwconf)
2985{
2986 int id, i, bits;
2987 unsigned short regs[16], irq;
2988 unsigned char scratch, scratch2;
2989
2990 hwconf->IsMoxaMustChipFlag = MOXA_OTHER_UART;
2991
2992 id = mxser_read_register(cap, regs);
2993 if (id == C168_ASIC_ID) {
2994 hwconf->board_type = MXSER_BOARD_C168_ISA;
2995 hwconf->ports = 8;
2996 } else if (id == C104_ASIC_ID) {
2997 hwconf->board_type = MXSER_BOARD_C104_ISA;
2998 hwconf->ports = 4;
2999 } else if (id == C102_ASIC_ID) {
3000 hwconf->board_type = MXSER_BOARD_C102_ISA;
3001 hwconf->ports = 2;
3002 } else if (id == CI132_ASIC_ID) {
3003 hwconf->board_type = MXSER_BOARD_CI132;
3004 hwconf->ports = 2;
3005 } else if (id == CI134_ASIC_ID) {
3006 hwconf->board_type = MXSER_BOARD_CI134;
3007 hwconf->ports = 4;
3008 } else if (id == CI104J_ASIC_ID) {
3009 hwconf->board_type = MXSER_BOARD_CI104J;
3010 hwconf->ports = 4;
3011 } else
3012 return 0;
3013
3014 irq = 0;
3015 if (hwconf->ports == 2) {
3016 irq = regs[9] & 0xF000;
3017 irq = irq | (irq >> 4);
3018 if (irq != (regs[9] & 0xFF00))
3019 return MXSER_ERR_IRQ_CONFLIT;
3020 } else if (hwconf->ports == 4) {
3021 irq = regs[9] & 0xF000;
3022 irq = irq | (irq >> 4);
3023 irq = irq | (irq >> 8);
3024 if (irq != regs[9])
3025 return MXSER_ERR_IRQ_CONFLIT;
3026 } else if (hwconf->ports == 8) {
3027 irq = regs[9] & 0xF000;
3028 irq = irq | (irq >> 4);
3029 irq = irq | (irq >> 8);
3030 if ((irq != regs[9]) || (irq != regs[10]))
3031 return MXSER_ERR_IRQ_CONFLIT;
3032 }
3033
3034 if (!irq)
3035 return MXSER_ERR_IRQ;
3036 hwconf->irq = ((int)(irq & 0xF000) >> 12);
3037 for (i = 0; i < 8; i++)
3038 hwconf->ioaddr[i] = (int) regs[i + 1] & 0xFFF8;
3039 if ((regs[12] & 0x80) == 0)
3040 return MXSER_ERR_VECTOR;
3041 hwconf->vector = (int)regs[11]; /* interrupt vector */
3042 if (id == 1)
3043 hwconf->vector_mask = 0x00FF;
3044 else
3045 hwconf->vector_mask = 0x000F;
3046 for (i = 7, bits = 0x0100; i >= 0; i--, bits <<= 1) {
3047 if (regs[12] & bits) {
3048 hwconf->baud_base[i] = 921600;
3049 hwconf->MaxCanSetBaudRate[i] = 921600; /* add by Victor Yu. 09-04-2002 */
3050 } else {
3051 hwconf->baud_base[i] = 115200;
3052 hwconf->MaxCanSetBaudRate[i] = 115200; /* add by Victor Yu. 09-04-2002 */
3053 }
3054 }
3055 scratch2 = inb(cap + UART_LCR) & (~UART_LCR_DLAB);
3056 outb(scratch2 | UART_LCR_DLAB, cap + UART_LCR);
3057 outb(0, cap + UART_EFR); /* EFR is the same as FCR */
3058 outb(scratch2, cap + UART_LCR);
3059 outb(UART_FCR_ENABLE_FIFO, cap + UART_FCR);
3060 scratch = inb(cap + UART_IIR);
3061
3062 if (scratch & 0xC0)
3063 hwconf->uart_type = PORT_16550A;
3064 else
3065 hwconf->uart_type = PORT_16450;
3066 if (id == 1)
3067 hwconf->ports = 8;
3068 else
3069 hwconf->ports = 4;
3070 request_region(hwconf->ioaddr[0], 8 * hwconf->ports, "mxser(IO)");
3071 request_region(hwconf->vector, 1, "mxser(vector)");
3072 return hwconf->ports;
3073}
3074
3075#define CHIP_SK 0x01 /* Serial Data Clock in Eprom */
3076#define CHIP_DO 0x02 /* Serial Data Output in Eprom */
3077#define CHIP_CS 0x04 /* Serial Chip Select in Eprom */
3078#define CHIP_DI 0x08 /* Serial Data Input in Eprom */
3079#define EN_CCMD 0x000 /* Chip's command register */
3080#define EN0_RSARLO 0x008 /* Remote start address reg 0 */
3081#define EN0_RSARHI 0x009 /* Remote start address reg 1 */
3082#define EN0_RCNTLO 0x00A /* Remote byte count reg WR */
3083#define EN0_RCNTHI 0x00B /* Remote byte count reg WR */
3084#define EN0_DCFG 0x00E /* Data configuration reg WR */
3085#define EN0_PORT 0x010 /* Rcv missed frame error counter RD */
3086#define ENC_PAGE0 0x000 /* Select page 0 of chip registers */
3087#define ENC_PAGE3 0x0C0 /* Select page 3 of chip registers */
3088static int mxser_read_register(int port, unsigned short *regs)
3089{
3090 int i, k, value, id;
3091 unsigned int j;
3092
3093 id = mxser_program_mode(port);
3094 if (id < 0)
3095 return id;
3096 for (i = 0; i < 14; i++) {
3097 k = (i & 0x3F) | 0x180;
3098 for (j = 0x100; j > 0; j >>= 1) {
3099 outb(CHIP_CS, port);
3100 if (k & j) {
3101 outb(CHIP_CS | CHIP_DO, port);
3102 outb(CHIP_CS | CHIP_DO | CHIP_SK, port); /* A? bit of read */
3103 } else {
3104 outb(CHIP_CS, port);
3105 outb(CHIP_CS | CHIP_SK, port); /* A? bit of read */
3106 }
3107 }
3108 (void)inb(port);
3109 value = 0;
3110 for (k = 0, j = 0x8000; k < 16; k++, j >>= 1) {
3111 outb(CHIP_CS, port);
3112 outb(CHIP_CS | CHIP_SK, port);
3113 if (inb(port) & CHIP_DI)
3114 value |= j;
3115 }
3116 regs[i] = value;
3117 outb(0, port);
3118 }
3119 mxser_normal_mode(port);
3120 return id;
3121}
3122
3123static int mxser_program_mode(int port)
3124{
3125 int id, i, j, n;
3126 /* unsigned long flags; */
3127
3128 spin_lock(&gm_lock);
3129 outb(0, port);
3130 outb(0, port);
3131 outb(0, port);
3132 (void)inb(port);
3133 (void)inb(port);
3134 outb(0, port);
3135 (void)inb(port);
3136 /* restore_flags(flags); */
3137 spin_unlock(&gm_lock);
3138
3139 id = inb(port + 1) & 0x1F;
3140 if ((id != C168_ASIC_ID) &&
3141 (id != C104_ASIC_ID) &&
3142 (id != C102_ASIC_ID) &&
3143 (id != CI132_ASIC_ID) &&
3144 (id != CI134_ASIC_ID) &&
3145 (id != CI104J_ASIC_ID))
3146 return -1;
3147 for (i = 0, j = 0; i < 4; i++) {
3148 n = inb(port + 2);
3149 if (n == 'M') {
3150 j = 1;
3151 } else if ((j == 1) && (n == 1)) {
3152 j = 2;
3153 break;
3154 } else
3155 j = 0;
3156 }
3157 if (j != 2)
3158 id = -2;
3159 return id;
3160}
3161
3162static void mxser_normal_mode(int port)
3163{
3164 int i, n;
3165
3166 outb(0xA5, port + 1);
3167 outb(0x80, port + 3);
3168 outb(12, port + 0); /* 9600 bps */
3169 outb(0, port + 1);
3170 outb(0x03, port + 3); /* 8 data bits */
3171 outb(0x13, port + 4); /* loop back mode */
3172 for (i = 0; i < 16; i++) {
3173 n = inb(port + 5);
3174 if ((n & 0x61) == 0x60)
3175 break;
3176 if ((n & 1) == 1)
3177 (void)inb(port);
3178 }
3179 outb(0x00, port + 4);
3180}
3181
3182module_init(mxser_module_init);
3183module_exit(mxser_module_exit);
diff --git a/drivers/char/mxser_new.h b/drivers/char/mxser_new.h
new file mode 100644
index 000000000000..32ce1a800556
--- /dev/null
+++ b/drivers/char/mxser_new.h
@@ -0,0 +1,450 @@
1#ifndef _MXSER_H
2#define _MXSER_H
3
4/*
5 * Semi-public control interfaces
6 */
7
8/*
9 * MOXA ioctls
10 */
11
12#define MOXA 0x400
13#define MOXA_GETDATACOUNT (MOXA + 23)
14#define MOXA_GET_CONF (MOXA + 35)
15#define MOXA_DIAGNOSE (MOXA + 50)
16#define MOXA_CHKPORTENABLE (MOXA + 60)
17#define MOXA_HighSpeedOn (MOXA + 61)
18#define MOXA_GET_MAJOR (MOXA + 63)
19#define MOXA_GET_CUMAJOR (MOXA + 64)
20#define MOXA_GETMSTATUS (MOXA + 65)
21#define MOXA_SET_OP_MODE (MOXA + 66)
22#define MOXA_GET_OP_MODE (MOXA + 67)
23
24#define RS232_MODE 0
25#define RS485_2WIRE_MODE 1
26#define RS422_MODE 2
27#define RS485_4WIRE_MODE 3
28#define OP_MODE_MASK 3
29// above add by Victor Yu. 01-05-2004
30
31#define TTY_THRESHOLD_THROTTLE 128
32
33#define LO_WATER (TTY_FLIPBUF_SIZE)
34#define HI_WATER (TTY_FLIPBUF_SIZE*2*3/4)
35
36// added by James. 03-11-2004.
37#define MOXA_SDS_GETICOUNTER (MOXA + 68)
38#define MOXA_SDS_RSTICOUNTER (MOXA + 69)
39// (above) added by James.
40
41#define MOXA_ASPP_OQUEUE (MOXA + 70)
42#define MOXA_ASPP_SETBAUD (MOXA + 71)
43#define MOXA_ASPP_GETBAUD (MOXA + 72)
44#define MOXA_ASPP_MON (MOXA + 73)
45#define MOXA_ASPP_LSTATUS (MOXA + 74)
46#define MOXA_ASPP_MON_EXT (MOXA + 75)
47#define MOXA_SET_BAUD_METHOD (MOXA + 76)
48
49
50/* --------------------------------------------------- */
51
52#define NPPI_NOTIFY_PARITY 0x01
53#define NPPI_NOTIFY_FRAMING 0x02
54#define NPPI_NOTIFY_HW_OVERRUN 0x04
55#define NPPI_NOTIFY_SW_OVERRUN 0x08
56#define NPPI_NOTIFY_BREAK 0x10
57
58#define NPPI_NOTIFY_CTSHOLD 0x01 // Tx hold by CTS low
59#define NPPI_NOTIFY_DSRHOLD 0x02 // Tx hold by DSR low
60#define NPPI_NOTIFY_XOFFHOLD 0x08 // Tx hold by Xoff received
61#define NPPI_NOTIFY_XOFFXENT 0x10 // Xoff Sent
62
63//CheckIsMoxaMust return value
64#define MOXA_OTHER_UART 0x00
65#define MOXA_MUST_MU150_HWID 0x01
66#define MOXA_MUST_MU860_HWID 0x02
67
68// follow just for Moxa Must chip define.
69//
70// when LCR register (offset 0x03) write following value,
71// the Must chip will enter enchance mode. And write value
72// on EFR (offset 0x02) bit 6,7 to change bank.
73#define MOXA_MUST_ENTER_ENCHANCE 0xBF
74
75// when enhance mode enable, access on general bank register
76#define MOXA_MUST_GDL_REGISTER 0x07
77#define MOXA_MUST_GDL_MASK 0x7F
78#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
79
80#define MOXA_MUST_LSR_RERR 0x80 // error in receive FIFO
81// enchance register bank select and enchance mode setting register
82// when LCR register equal to 0xBF
83#define MOXA_MUST_EFR_REGISTER 0x02
84// enchance mode enable
85#define MOXA_MUST_EFR_EFRB_ENABLE 0x10
86// enchance reister bank set 0, 1, 2
87#define MOXA_MUST_EFR_BANK0 0x00
88#define MOXA_MUST_EFR_BANK1 0x40
89#define MOXA_MUST_EFR_BANK2 0x80
90#define MOXA_MUST_EFR_BANK3 0xC0
91#define MOXA_MUST_EFR_BANK_MASK 0xC0
92
93// set XON1 value register, when LCR=0xBF and change to bank0
94#define MOXA_MUST_XON1_REGISTER 0x04
95
96// set XON2 value register, when LCR=0xBF and change to bank0
97#define MOXA_MUST_XON2_REGISTER 0x05
98
99// set XOFF1 value register, when LCR=0xBF and change to bank0
100#define MOXA_MUST_XOFF1_REGISTER 0x06
101
102// set XOFF2 value register, when LCR=0xBF and change to bank0
103#define MOXA_MUST_XOFF2_REGISTER 0x07
104
105#define MOXA_MUST_RBRTL_REGISTER 0x04
106#define MOXA_MUST_RBRTH_REGISTER 0x05
107#define MOXA_MUST_RBRTI_REGISTER 0x06
108#define MOXA_MUST_THRTL_REGISTER 0x07
109#define MOXA_MUST_ENUM_REGISTER 0x04
110#define MOXA_MUST_HWID_REGISTER 0x05
111#define MOXA_MUST_ECR_REGISTER 0x06
112#define MOXA_MUST_CSR_REGISTER 0x07
113
114// good data mode enable
115#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20
116// only good data put into RxFIFO
117#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10
118
119// enable CTS interrupt
120#define MOXA_MUST_IER_ECTSI 0x80
121// enable RTS interrupt
122#define MOXA_MUST_IER_ERTSI 0x40
123// enable Xon/Xoff interrupt
124#define MOXA_MUST_IER_XINT 0x20
125// enable GDA interrupt
126#define MOXA_MUST_IER_EGDAI 0x10
127
128#define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
129
130// GDA interrupt pending
131#define MOXA_MUST_IIR_GDA 0x1C
132#define MOXA_MUST_IIR_RDA 0x04
133#define MOXA_MUST_IIR_RTO 0x0C
134#define MOXA_MUST_IIR_LSR 0x06
135
136// recieved Xon/Xoff or specical interrupt pending
137#define MOXA_MUST_IIR_XSC 0x10
138
139// RTS/CTS change state interrupt pending
140#define MOXA_MUST_IIR_RTSCTS 0x20
141#define MOXA_MUST_IIR_MASK 0x3E
142
143#define MOXA_MUST_MCR_XON_FLAG 0x40
144#define MOXA_MUST_MCR_XON_ANY 0x80
145#define MOXA_MUST_MCR_TX_XON 0x08
146
147
148// software flow control on chip mask value
149#define MOXA_MUST_EFR_SF_MASK 0x0F
150// send Xon1/Xoff1
151#define MOXA_MUST_EFR_SF_TX1 0x08
152// send Xon2/Xoff2
153#define MOXA_MUST_EFR_SF_TX2 0x04
154// send Xon1,Xon2/Xoff1,Xoff2
155#define MOXA_MUST_EFR_SF_TX12 0x0C
156// don't send Xon/Xoff
157#define MOXA_MUST_EFR_SF_TX_NO 0x00
158// Tx software flow control mask
159#define MOXA_MUST_EFR_SF_TX_MASK 0x0C
160// don't receive Xon/Xoff
161#define MOXA_MUST_EFR_SF_RX_NO 0x00
162// receive Xon1/Xoff1
163#define MOXA_MUST_EFR_SF_RX1 0x02
164// receive Xon2/Xoff2
165#define MOXA_MUST_EFR_SF_RX2 0x01
166// receive Xon1,Xon2/Xoff1,Xoff2
167#define MOXA_MUST_EFR_SF_RX12 0x03
168// Rx software flow control mask
169#define MOXA_MUST_EFR_SF_RX_MASK 0x03
170
171//#define MOXA_MUST_MIN_XOFFLIMIT 66
172//#define MOXA_MUST_MIN_XONLIMIT 20
173//#define ID1_RX_TRIG 120
174
175
176#define CHECK_MOXA_MUST_XOFFLIMIT(info) { \
177 if ( (info)->IsMoxaMustChipFlag && \
178 (info)->HandFlow.XoffLimit < MOXA_MUST_MIN_XOFFLIMIT ) { \
179 (info)->HandFlow.XoffLimit = MOXA_MUST_MIN_XOFFLIMIT; \
180 (info)->HandFlow.XonLimit = MOXA_MUST_MIN_XONLIMIT; \
181 } \
182}
183
184#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) { \
185 u8 __oldlcr, __efr; \
186 __oldlcr = inb((baseio)+UART_LCR); \
187 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
188 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
189 __efr |= MOXA_MUST_EFR_EFRB_ENABLE; \
190 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
191 outb(__oldlcr, (baseio)+UART_LCR); \
192}
193
194#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) { \
195 u8 __oldlcr, __efr; \
196 __oldlcr = inb((baseio)+UART_LCR); \
197 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
198 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
199 __efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \
200 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
201 outb(__oldlcr, (baseio)+UART_LCR); \
202}
203
204#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) { \
205 u8 __oldlcr, __efr; \
206 __oldlcr = inb((baseio)+UART_LCR); \
207 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
208 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
209 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
210 __efr |= MOXA_MUST_EFR_BANK0; \
211 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
212 outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \
213 outb(__oldlcr, (baseio)+UART_LCR); \
214}
215
216#define SET_MOXA_MUST_XON2_VALUE(baseio, Value) { \
217 u8 __oldlcr, __efr; \
218 __oldlcr = inb((baseio)+UART_LCR); \
219 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
220 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
221 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
222 __efr |= MOXA_MUST_EFR_BANK0; \
223 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
224 outb((u8)(Value), (baseio)+MOXA_MUST_XON2_REGISTER); \
225 outb(__oldlcr, (baseio)+UART_LCR); \
226}
227
228#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) { \
229 u8 __oldlcr, __efr; \
230 __oldlcr = inb((baseio)+UART_LCR); \
231 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
232 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
233 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
234 __efr |= MOXA_MUST_EFR_BANK0; \
235 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
236 outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \
237 outb(__oldlcr, (baseio)+UART_LCR); \
238}
239
240#define SET_MOXA_MUST_XOFF2_VALUE(baseio, Value) { \
241 u8 __oldlcr, __efr; \
242 __oldlcr = inb((baseio)+UART_LCR); \
243 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
244 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
245 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
246 __efr |= MOXA_MUST_EFR_BANK0; \
247 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
248 outb((u8)(Value), (baseio)+MOXA_MUST_XOFF2_REGISTER); \
249 outb(__oldlcr, (baseio)+UART_LCR); \
250}
251
252#define SET_MOXA_MUST_RBRTL_VALUE(baseio, Value) { \
253 u8 __oldlcr, __efr; \
254 __oldlcr = inb((baseio)+UART_LCR); \
255 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
256 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
257 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
258 __efr |= MOXA_MUST_EFR_BANK1; \
259 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
260 outb((u8)(Value), (baseio)+MOXA_MUST_RBRTL_REGISTER); \
261 outb(__oldlcr, (baseio)+UART_LCR); \
262}
263
264#define SET_MOXA_MUST_RBRTH_VALUE(baseio, Value) { \
265 u8 __oldlcr, __efr; \
266 __oldlcr = inb((baseio)+UART_LCR); \
267 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
268 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
269 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
270 __efr |= MOXA_MUST_EFR_BANK1; \
271 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
272 outb((u8)(Value), (baseio)+MOXA_MUST_RBRTH_REGISTER); \
273 outb(__oldlcr, (baseio)+UART_LCR); \
274}
275
276#define SET_MOXA_MUST_RBRTI_VALUE(baseio, Value) { \
277 u8 __oldlcr, __efr; \
278 __oldlcr = inb((baseio)+UART_LCR); \
279 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
280 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
281 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
282 __efr |= MOXA_MUST_EFR_BANK1; \
283 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
284 outb((u8)(Value), (baseio)+MOXA_MUST_RBRTI_REGISTER); \
285 outb(__oldlcr, (baseio)+UART_LCR); \
286}
287
288#define SET_MOXA_MUST_THRTL_VALUE(baseio, Value) { \
289 u8 __oldlcr, __efr; \
290 __oldlcr = inb((baseio)+UART_LCR); \
291 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
292 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
293 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
294 __efr |= MOXA_MUST_EFR_BANK1; \
295 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
296 outb((u8)(Value), (baseio)+MOXA_MUST_THRTL_REGISTER); \
297 outb(__oldlcr, (baseio)+UART_LCR); \
298}
299
300//#define MOXA_MUST_RBRL_VALUE 4
301#define SET_MOXA_MUST_FIFO_VALUE(info) { \
302 u8 __oldlcr, __efr; \
303 __oldlcr = inb((info)->base+UART_LCR); \
304 outb(MOXA_MUST_ENTER_ENCHANCE, (info)->base+UART_LCR); \
305 __efr = inb((info)->base+MOXA_MUST_EFR_REGISTER); \
306 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
307 __efr |= MOXA_MUST_EFR_BANK1; \
308 outb(__efr, (info)->base+MOXA_MUST_EFR_REGISTER); \
309 outb((u8)((info)->rx_high_water), (info)->base+MOXA_MUST_RBRTH_REGISTER); \
310 outb((u8)((info)->rx_trigger), (info)->base+MOXA_MUST_RBRTI_REGISTER); \
311 outb((u8)((info)->rx_low_water), (info)->base+MOXA_MUST_RBRTL_REGISTER); \
312 outb(__oldlcr, (info)->base+UART_LCR); \
313}
314
315
316
317#define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) { \
318 u8 __oldlcr, __efr; \
319 __oldlcr = inb((baseio)+UART_LCR); \
320 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
321 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
322 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
323 __efr |= MOXA_MUST_EFR_BANK2; \
324 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
325 outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER); \
326 outb(__oldlcr, (baseio)+UART_LCR); \
327}
328
329#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) { \
330 u8 __oldlcr, __efr; \
331 __oldlcr = inb((baseio)+UART_LCR); \
332 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
333 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
334 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
335 __efr |= MOXA_MUST_EFR_BANK2; \
336 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
337 *pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \
338 outb(__oldlcr, (baseio)+UART_LCR); \
339}
340
341#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) { \
342 u8 __oldlcr, __efr; \
343 __oldlcr = inb((baseio)+UART_LCR); \
344 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
345 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
346 __efr &= ~MOXA_MUST_EFR_SF_MASK; \
347 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
348 outb(__oldlcr, (baseio)+UART_LCR); \
349}
350
351#define SET_MOXA_MUST_JUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \
352 u8 __oldlcr, __efr; \
353 __oldlcr = inb((baseio)+UART_LCR); \
354 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
355 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
356 __efr &= ~MOXA_MUST_EFR_SF_MASK; \
357 __efr |= MOXA_MUST_EFR_SF_TX1; \
358 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
359 outb(__oldlcr, (baseio)+UART_LCR); \
360}
361
362#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \
363 u8 __oldlcr, __efr; \
364 __oldlcr = inb((baseio)+UART_LCR); \
365 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
366 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
367 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
368 __efr |= MOXA_MUST_EFR_SF_TX1; \
369 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
370 outb(__oldlcr, (baseio)+UART_LCR); \
371}
372
373#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \
374 u8 __oldlcr, __efr; \
375 __oldlcr = inb((baseio)+UART_LCR); \
376 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
377 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
378 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
379 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
380 outb(__oldlcr, (baseio)+UART_LCR); \
381}
382
383#define SET_MOXA_MUST_JUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \
384 u8 __oldlcr, __efr; \
385 __oldlcr = inb((baseio)+UART_LCR); \
386 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
387 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
388 __efr &= ~MOXA_MUST_EFR_SF_MASK; \
389 __efr |= MOXA_MUST_EFR_SF_RX1; \
390 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
391 outb(__oldlcr, (baseio)+UART_LCR); \
392}
393
394#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \
395 u8 __oldlcr, __efr; \
396 __oldlcr = inb((baseio)+UART_LCR); \
397 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
398 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
399 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
400 __efr |= MOXA_MUST_EFR_SF_RX1; \
401 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
402 outb(__oldlcr, (baseio)+UART_LCR); \
403}
404
405#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \
406 u8 __oldlcr, __efr; \
407 __oldlcr = inb((baseio)+UART_LCR); \
408 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
409 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
410 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
411 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
412 outb(__oldlcr, (baseio)+UART_LCR); \
413}
414
415#define ENABLE_MOXA_MUST_TX_RX_SOFTWARE_FLOW_CONTROL(baseio) { \
416 u8 __oldlcr, __efr; \
417 __oldlcr = inb((baseio)+UART_LCR); \
418 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
419 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
420 __efr &= ~MOXA_MUST_EFR_SF_MASK; \
421 __efr |= (MOXA_MUST_EFR_SF_RX1|MOXA_MUST_EFR_SF_TX1); \
422 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
423 outb(__oldlcr, (baseio)+UART_LCR); \
424}
425
426#define ENABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(baseio) { \
427 u8 __oldmcr; \
428 __oldmcr = inb((baseio)+UART_MCR); \
429 __oldmcr |= MOXA_MUST_MCR_XON_ANY; \
430 outb(__oldmcr, (baseio)+UART_MCR); \
431}
432
433#define DISABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(baseio) { \
434 u8 __oldmcr; \
435 __oldmcr = inb((baseio)+UART_MCR); \
436 __oldmcr &= ~MOXA_MUST_MCR_XON_ANY; \
437 outb(__oldmcr, (baseio)+UART_MCR); \
438}
439
440#define READ_MOXA_MUST_GDL(baseio) inb((baseio)+MOXA_MUST_GDL_REGISTER)
441
442
443#ifndef INIT_WORK
444#define INIT_WORK(_work, _func, _data){ \
445 _data->tqueue.routine = _func;\
446 _data->tqueue.data = _data;\
447 }
448#endif
449
450#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 01:21:06 -0500