diff options
Diffstat (limited to 'drivers')
174 files changed, 13454 insertions, 12402 deletions
diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c index a4fddb24476f..f6e54bf8dd96 100644 --- a/drivers/acpi/video.c +++ b/drivers/acpi/video.c | |||
@@ -285,7 +285,7 @@ static int acpi_video_device_brightness_open_fs(struct inode *inode, | |||
285 | struct file *file); | 285 | struct file *file); |
286 | static ssize_t acpi_video_device_write_brightness(struct file *file, | 286 | static ssize_t acpi_video_device_write_brightness(struct file *file, |
287 | const char __user *buffer, size_t count, loff_t *data); | 287 | const char __user *buffer, size_t count, loff_t *data); |
288 | static struct file_operations acpi_video_device_brightness_fops = { | 288 | static const struct file_operations acpi_video_device_brightness_fops = { |
289 | .owner = THIS_MODULE, | 289 | .owner = THIS_MODULE, |
290 | .open = acpi_video_device_brightness_open_fs, | 290 | .open = acpi_video_device_brightness_open_fs, |
291 | .read = seq_read, | 291 | .read = seq_read, |
diff --git a/drivers/atm/ambassador.c b/drivers/atm/ambassador.c index 703364b52170..66e181345b3a 100644 --- a/drivers/atm/ambassador.c +++ b/drivers/atm/ambassador.c | |||
@@ -1306,14 +1306,6 @@ static void amb_close (struct atm_vcc * atm_vcc) { | |||
1306 | return; | 1306 | return; |
1307 | } | 1307 | } |
1308 | 1308 | ||
1309 | /********** Set socket options for a VC **********/ | ||
1310 | |||
1311 | // int amb_getsockopt (struct atm_vcc * atm_vcc, int level, int optname, void * optval, int optlen); | ||
1312 | |||
1313 | /********** Set socket options for a VC **********/ | ||
1314 | |||
1315 | // int amb_setsockopt (struct atm_vcc * atm_vcc, int level, int optname, void * optval, int optlen); | ||
1316 | |||
1317 | /********** Send **********/ | 1309 | /********** Send **********/ |
1318 | 1310 | ||
1319 | static int amb_send (struct atm_vcc * atm_vcc, struct sk_buff * skb) { | 1311 | static int amb_send (struct atm_vcc * atm_vcc, struct sk_buff * skb) { |
diff --git a/drivers/atm/eni.c b/drivers/atm/eni.c index 5503bfc8e132..0c3026145443 100644 --- a/drivers/atm/eni.c +++ b/drivers/atm/eni.c | |||
@@ -2031,7 +2031,7 @@ static int eni_getsockopt(struct atm_vcc *vcc,int level,int optname, | |||
2031 | 2031 | ||
2032 | 2032 | ||
2033 | static int eni_setsockopt(struct atm_vcc *vcc,int level,int optname, | 2033 | static int eni_setsockopt(struct atm_vcc *vcc,int level,int optname, |
2034 | void __user *optval,int optlen) | 2034 | void __user *optval,unsigned int optlen) |
2035 | { | 2035 | { |
2036 | return -EINVAL; | 2036 | return -EINVAL; |
2037 | } | 2037 | } |
diff --git a/drivers/atm/firestream.c b/drivers/atm/firestream.c index b119640e1ee9..cd5049af47a9 100644 --- a/drivers/atm/firestream.c +++ b/drivers/atm/firestream.c | |||
@@ -1244,7 +1244,7 @@ static int fs_getsockopt(struct atm_vcc *vcc,int level,int optname, | |||
1244 | 1244 | ||
1245 | 1245 | ||
1246 | static int fs_setsockopt(struct atm_vcc *vcc,int level,int optname, | 1246 | static int fs_setsockopt(struct atm_vcc *vcc,int level,int optname, |
1247 | void __user *optval,int optlen) | 1247 | void __user *optval,unsigned int optlen) |
1248 | { | 1248 | { |
1249 | func_enter (); | 1249 | func_enter (); |
1250 | func_exit (); | 1250 | func_exit (); |
diff --git a/drivers/atm/fore200e.c b/drivers/atm/fore200e.c index 10f000dbe448..f766cc46b4c4 100644 --- a/drivers/atm/fore200e.c +++ b/drivers/atm/fore200e.c | |||
@@ -1795,7 +1795,7 @@ fore200e_getsockopt(struct atm_vcc* vcc, int level, int optname, void __user *op | |||
1795 | 1795 | ||
1796 | 1796 | ||
1797 | static int | 1797 | static int |
1798 | fore200e_setsockopt(struct atm_vcc* vcc, int level, int optname, void __user *optval, int optlen) | 1798 | fore200e_setsockopt(struct atm_vcc* vcc, int level, int optname, void __user *optval, unsigned int optlen) |
1799 | { | 1799 | { |
1800 | /* struct fore200e* fore200e = FORE200E_DEV(vcc->dev); */ | 1800 | /* struct fore200e* fore200e = FORE200E_DEV(vcc->dev); */ |
1801 | 1801 | ||
diff --git a/drivers/atm/he.c b/drivers/atm/he.c index 29e66d603d3c..70667033a568 100644 --- a/drivers/atm/he.c +++ b/drivers/atm/he.c | |||
@@ -921,9 +921,9 @@ out_free_rbpq_base: | |||
921 | he_dev->rbrq_phys); | 921 | he_dev->rbrq_phys); |
922 | i = CONFIG_RBPL_SIZE; | 922 | i = CONFIG_RBPL_SIZE; |
923 | out_free_rbpl_virt: | 923 | out_free_rbpl_virt: |
924 | while (--i) | 924 | while (i--) |
925 | pci_pool_free(he_dev->rbps_pool, he_dev->rbpl_virt[i].virt, | 925 | pci_pool_free(he_dev->rbpl_pool, he_dev->rbpl_virt[i].virt, |
926 | he_dev->rbps_base[i].phys); | 926 | he_dev->rbpl_base[i].phys); |
927 | kfree(he_dev->rbpl_virt); | 927 | kfree(he_dev->rbpl_virt); |
928 | 928 | ||
929 | out_free_rbpl_base: | 929 | out_free_rbpl_base: |
@@ -933,11 +933,11 @@ out_free_rbpl_base: | |||
933 | out_destroy_rbpl_pool: | 933 | out_destroy_rbpl_pool: |
934 | pci_pool_destroy(he_dev->rbpl_pool); | 934 | pci_pool_destroy(he_dev->rbpl_pool); |
935 | 935 | ||
936 | i = CONFIG_RBPL_SIZE; | 936 | i = CONFIG_RBPS_SIZE; |
937 | out_free_rbps_virt: | 937 | out_free_rbps_virt: |
938 | while (--i) | 938 | while (i--) |
939 | pci_pool_free(he_dev->rbpl_pool, he_dev->rbps_virt[i].virt, | 939 | pci_pool_free(he_dev->rbps_pool, he_dev->rbps_virt[i].virt, |
940 | he_dev->rbpl_base[i].phys); | 940 | he_dev->rbps_base[i].phys); |
941 | kfree(he_dev->rbps_virt); | 941 | kfree(he_dev->rbps_virt); |
942 | 942 | ||
943 | out_free_rbps_base: | 943 | out_free_rbps_base: |
diff --git a/drivers/atm/horizon.c b/drivers/atm/horizon.c index 01ce241dbeae..4e49021e67ee 100644 --- a/drivers/atm/horizon.c +++ b/drivers/atm/horizon.c | |||
@@ -2590,7 +2590,7 @@ static int hrz_getsockopt (struct atm_vcc * atm_vcc, int level, int optname, | |||
2590 | } | 2590 | } |
2591 | 2591 | ||
2592 | static int hrz_setsockopt (struct atm_vcc * atm_vcc, int level, int optname, | 2592 | static int hrz_setsockopt (struct atm_vcc * atm_vcc, int level, int optname, |
2593 | void *optval, int optlen) { | 2593 | void *optval, unsigned int optlen) { |
2594 | hrz_dev * dev = HRZ_DEV(atm_vcc->dev); | 2594 | hrz_dev * dev = HRZ_DEV(atm_vcc->dev); |
2595 | PRINTD (DBG_FLOW|DBG_VCC, "hrz_setsockopt"); | 2595 | PRINTD (DBG_FLOW|DBG_VCC, "hrz_setsockopt"); |
2596 | switch (level) { | 2596 | switch (level) { |
diff --git a/drivers/atm/iphase.c b/drivers/atm/iphase.c index 78c9736c3579..b2c1b37ab2e4 100644 --- a/drivers/atm/iphase.c +++ b/drivers/atm/iphase.c | |||
@@ -2862,7 +2862,7 @@ static int ia_getsockopt(struct atm_vcc *vcc, int level, int optname, | |||
2862 | } | 2862 | } |
2863 | 2863 | ||
2864 | static int ia_setsockopt(struct atm_vcc *vcc, int level, int optname, | 2864 | static int ia_setsockopt(struct atm_vcc *vcc, int level, int optname, |
2865 | void __user *optval, int optlen) | 2865 | void __user *optval, unsigned int optlen) |
2866 | { | 2866 | { |
2867 | IF_EVENT(printk(">ia_setsockopt\n");) | 2867 | IF_EVENT(printk(">ia_setsockopt\n");) |
2868 | return -EINVAL; | 2868 | return -EINVAL; |
diff --git a/drivers/atm/zatm.c b/drivers/atm/zatm.c index 752b1ba81f7e..2e9635be048c 100644 --- a/drivers/atm/zatm.c +++ b/drivers/atm/zatm.c | |||
@@ -1517,7 +1517,7 @@ static int zatm_getsockopt(struct atm_vcc *vcc,int level,int optname, | |||
1517 | 1517 | ||
1518 | 1518 | ||
1519 | static int zatm_setsockopt(struct atm_vcc *vcc,int level,int optname, | 1519 | static int zatm_setsockopt(struct atm_vcc *vcc,int level,int optname, |
1520 | void __user *optval,int optlen) | 1520 | void __user *optval,unsigned int optlen) |
1521 | { | 1521 | { |
1522 | return -EINVAL; | 1522 | return -EINVAL; |
1523 | } | 1523 | } |
diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c index 78852b103198..fb5be2d95d52 100644 --- a/drivers/block/cciss.c +++ b/drivers/block/cciss.c | |||
@@ -437,7 +437,7 @@ out: | |||
437 | return err; | 437 | return err; |
438 | } | 438 | } |
439 | 439 | ||
440 | static struct file_operations cciss_proc_fops = { | 440 | static const struct file_operations cciss_proc_fops = { |
441 | .owner = THIS_MODULE, | 441 | .owner = THIS_MODULE, |
442 | .open = cciss_seq_open, | 442 | .open = cciss_seq_open, |
443 | .read = seq_read, | 443 | .read = seq_read, |
diff --git a/drivers/char/apm-emulation.c b/drivers/char/apm-emulation.c index aaca40283be9..4f568cb9af3f 100644 --- a/drivers/char/apm-emulation.c +++ b/drivers/char/apm-emulation.c | |||
@@ -393,7 +393,7 @@ static int apm_open(struct inode * inode, struct file * filp) | |||
393 | return as ? 0 : -ENOMEM; | 393 | return as ? 0 : -ENOMEM; |
394 | } | 394 | } |
395 | 395 | ||
396 | static struct file_operations apm_bios_fops = { | 396 | static const struct file_operations apm_bios_fops = { |
397 | .owner = THIS_MODULE, | 397 | .owner = THIS_MODULE, |
398 | .read = apm_read, | 398 | .read = apm_read, |
399 | .poll = apm_poll, | 399 | .poll = apm_poll, |
diff --git a/drivers/char/bfin-otp.c b/drivers/char/bfin-otp.c index e3dd24bff514..836d4f0a876f 100644 --- a/drivers/char/bfin-otp.c +++ b/drivers/char/bfin-otp.c | |||
@@ -217,7 +217,7 @@ static long bfin_otp_ioctl(struct file *filp, unsigned cmd, unsigned long arg) | |||
217 | # define bfin_otp_ioctl NULL | 217 | # define bfin_otp_ioctl NULL |
218 | #endif | 218 | #endif |
219 | 219 | ||
220 | static struct file_operations bfin_otp_fops = { | 220 | static const struct file_operations bfin_otp_fops = { |
221 | .owner = THIS_MODULE, | 221 | .owner = THIS_MODULE, |
222 | .unlocked_ioctl = bfin_otp_ioctl, | 222 | .unlocked_ioctl = bfin_otp_ioctl, |
223 | .read = bfin_otp_read, | 223 | .read = bfin_otp_read, |
diff --git a/drivers/char/cyclades.c b/drivers/char/cyclades.c index df5038bbcbc2..4254457d3911 100644 --- a/drivers/char/cyclades.c +++ b/drivers/char/cyclades.c | |||
@@ -3354,7 +3354,7 @@ static int __init cy_detect_isa(void) | |||
3354 | continue; | 3354 | continue; |
3355 | } | 3355 | } |
3356 | #ifdef MODULE | 3356 | #ifdef MODULE |
3357 | if (isparam && irq[i]) | 3357 | if (isparam && i < NR_CARDS && irq[i]) |
3358 | cy_isa_irq = irq[i]; | 3358 | cy_isa_irq = irq[i]; |
3359 | else | 3359 | else |
3360 | #endif | 3360 | #endif |
diff --git a/drivers/char/hw_random/omap-rng.c b/drivers/char/hw_random/omap-rng.c index 00dd3de1be51..06aad0831c73 100644 --- a/drivers/char/hw_random/omap-rng.c +++ b/drivers/char/hw_random/omap-rng.c | |||
@@ -116,7 +116,7 @@ static int __devinit omap_rng_probe(struct platform_device *pdev) | |||
116 | if (!res) | 116 | if (!res) |
117 | return -ENOENT; | 117 | return -ENOENT; |
118 | 118 | ||
119 | mem = request_mem_region(res->start, res->end - res->start + 1, | 119 | mem = request_mem_region(res->start, resource_size(res), |
120 | pdev->name); | 120 | pdev->name); |
121 | if (mem == NULL) { | 121 | if (mem == NULL) { |
122 | ret = -EBUSY; | 122 | ret = -EBUSY; |
@@ -124,7 +124,7 @@ static int __devinit omap_rng_probe(struct platform_device *pdev) | |||
124 | } | 124 | } |
125 | 125 | ||
126 | dev_set_drvdata(&pdev->dev, mem); | 126 | dev_set_drvdata(&pdev->dev, mem); |
127 | rng_base = ioremap(res->start, res->end - res->start + 1); | 127 | rng_base = ioremap(res->start, resource_size(res)); |
128 | if (!rng_base) { | 128 | if (!rng_base) { |
129 | ret = -ENOMEM; | 129 | ret = -ENOMEM; |
130 | goto err_ioremap; | 130 | goto err_ioremap; |
diff --git a/drivers/char/pty.c b/drivers/char/pty.c index 53761cefa915..e066c4fdf81b 100644 --- a/drivers/char/pty.c +++ b/drivers/char/pty.c | |||
@@ -261,6 +261,9 @@ done: | |||
261 | return 0; | 261 | return 0; |
262 | } | 262 | } |
263 | 263 | ||
264 | /* Traditional BSD devices */ | ||
265 | #ifdef CONFIG_LEGACY_PTYS | ||
266 | |||
264 | static int pty_install(struct tty_driver *driver, struct tty_struct *tty) | 267 | static int pty_install(struct tty_driver *driver, struct tty_struct *tty) |
265 | { | 268 | { |
266 | struct tty_struct *o_tty; | 269 | struct tty_struct *o_tty; |
@@ -310,24 +313,6 @@ free_mem_out: | |||
310 | return -ENOMEM; | 313 | return -ENOMEM; |
311 | } | 314 | } |
312 | 315 | ||
313 | |||
314 | static const struct tty_operations pty_ops = { | ||
315 | .install = pty_install, | ||
316 | .open = pty_open, | ||
317 | .close = pty_close, | ||
318 | .write = pty_write, | ||
319 | .write_room = pty_write_room, | ||
320 | .flush_buffer = pty_flush_buffer, | ||
321 | .chars_in_buffer = pty_chars_in_buffer, | ||
322 | .unthrottle = pty_unthrottle, | ||
323 | .set_termios = pty_set_termios, | ||
324 | .resize = pty_resize | ||
325 | }; | ||
326 | |||
327 | /* Traditional BSD devices */ | ||
328 | #ifdef CONFIG_LEGACY_PTYS | ||
329 | static struct tty_driver *pty_driver, *pty_slave_driver; | ||
330 | |||
331 | static int pty_bsd_ioctl(struct tty_struct *tty, struct file *file, | 316 | static int pty_bsd_ioctl(struct tty_struct *tty, struct file *file, |
332 | unsigned int cmd, unsigned long arg) | 317 | unsigned int cmd, unsigned long arg) |
333 | { | 318 | { |
@@ -341,7 +326,12 @@ static int pty_bsd_ioctl(struct tty_struct *tty, struct file *file, | |||
341 | static int legacy_count = CONFIG_LEGACY_PTY_COUNT; | 326 | static int legacy_count = CONFIG_LEGACY_PTY_COUNT; |
342 | module_param(legacy_count, int, 0); | 327 | module_param(legacy_count, int, 0); |
343 | 328 | ||
344 | static const struct tty_operations pty_ops_bsd = { | 329 | /* |
330 | * The master side of a pty can do TIOCSPTLCK and thus | ||
331 | * has pty_bsd_ioctl. | ||
332 | */ | ||
333 | static const struct tty_operations master_pty_ops_bsd = { | ||
334 | .install = pty_install, | ||
345 | .open = pty_open, | 335 | .open = pty_open, |
346 | .close = pty_close, | 336 | .close = pty_close, |
347 | .write = pty_write, | 337 | .write = pty_write, |
@@ -354,8 +344,23 @@ static const struct tty_operations pty_ops_bsd = { | |||
354 | .resize = pty_resize | 344 | .resize = pty_resize |
355 | }; | 345 | }; |
356 | 346 | ||
347 | static const struct tty_operations slave_pty_ops_bsd = { | ||
348 | .install = pty_install, | ||
349 | .open = pty_open, | ||
350 | .close = pty_close, | ||
351 | .write = pty_write, | ||
352 | .write_room = pty_write_room, | ||
353 | .flush_buffer = pty_flush_buffer, | ||
354 | .chars_in_buffer = pty_chars_in_buffer, | ||
355 | .unthrottle = pty_unthrottle, | ||
356 | .set_termios = pty_set_termios, | ||
357 | .resize = pty_resize | ||
358 | }; | ||
359 | |||
357 | static void __init legacy_pty_init(void) | 360 | static void __init legacy_pty_init(void) |
358 | { | 361 | { |
362 | struct tty_driver *pty_driver, *pty_slave_driver; | ||
363 | |||
359 | if (legacy_count <= 0) | 364 | if (legacy_count <= 0) |
360 | return; | 365 | return; |
361 | 366 | ||
@@ -383,7 +388,7 @@ static void __init legacy_pty_init(void) | |||
383 | pty_driver->init_termios.c_ospeed = 38400; | 388 | pty_driver->init_termios.c_ospeed = 38400; |
384 | pty_driver->flags = TTY_DRIVER_RESET_TERMIOS | TTY_DRIVER_REAL_RAW; | 389 | pty_driver->flags = TTY_DRIVER_RESET_TERMIOS | TTY_DRIVER_REAL_RAW; |
385 | pty_driver->other = pty_slave_driver; | 390 | pty_driver->other = pty_slave_driver; |
386 | tty_set_operations(pty_driver, &pty_ops); | 391 | tty_set_operations(pty_driver, &master_pty_ops_bsd); |
387 | 392 | ||
388 | pty_slave_driver->owner = THIS_MODULE; | 393 | pty_slave_driver->owner = THIS_MODULE; |
389 | pty_slave_driver->driver_name = "pty_slave"; | 394 | pty_slave_driver->driver_name = "pty_slave"; |
@@ -399,7 +404,7 @@ static void __init legacy_pty_init(void) | |||
399 | pty_slave_driver->flags = TTY_DRIVER_RESET_TERMIOS | | 404 | pty_slave_driver->flags = TTY_DRIVER_RESET_TERMIOS | |
400 | TTY_DRIVER_REAL_RAW; | 405 | TTY_DRIVER_REAL_RAW; |
401 | pty_slave_driver->other = pty_driver; | 406 | pty_slave_driver->other = pty_driver; |
402 | tty_set_operations(pty_slave_driver, &pty_ops); | 407 | tty_set_operations(pty_slave_driver, &slave_pty_ops_bsd); |
403 | 408 | ||
404 | if (tty_register_driver(pty_driver)) | 409 | if (tty_register_driver(pty_driver)) |
405 | panic("Couldn't register pty driver"); | 410 | panic("Couldn't register pty driver"); |
diff --git a/drivers/char/serial167.c b/drivers/char/serial167.c index 5942a9d674c0..452370af95de 100644 --- a/drivers/char/serial167.c +++ b/drivers/char/serial167.c | |||
@@ -220,8 +220,7 @@ static inline int serial_paranoia_check(struct cyclades_port *info, char *name, | |||
220 | return 1; | 220 | return 1; |
221 | } | 221 | } |
222 | 222 | ||
223 | if ((long)info < (long)(&cy_port[0]) | 223 | if (info < &cy_port[0] || info >= &cy_port[NR_PORTS]) { |
224 | || (long)(&cy_port[NR_PORTS]) < (long)info) { | ||
225 | printk("Warning: cyclades_port out of range for (%s) in %s\n", | 224 | printk("Warning: cyclades_port out of range for (%s) in %s\n", |
226 | name, routine); | 225 | name, routine); |
227 | return 1; | 226 | return 1; |
@@ -520,15 +519,13 @@ static irqreturn_t cd2401_tx_interrupt(int irq, void *dev_id) | |||
520 | panic("TxInt on debug port!!!"); | 519 | panic("TxInt on debug port!!!"); |
521 | } | 520 | } |
522 | #endif | 521 | #endif |
523 | |||
524 | info = &cy_port[channel]; | ||
525 | |||
526 | /* validate the port number (as configured and open) */ | 522 | /* validate the port number (as configured and open) */ |
527 | if ((channel < 0) || (NR_PORTS <= channel)) { | 523 | if ((channel < 0) || (NR_PORTS <= channel)) { |
528 | base_addr[CyIER] &= ~(CyTxMpty | CyTxRdy); | 524 | base_addr[CyIER] &= ~(CyTxMpty | CyTxRdy); |
529 | base_addr[CyTEOIR] = CyNOTRANS; | 525 | base_addr[CyTEOIR] = CyNOTRANS; |
530 | return IRQ_HANDLED; | 526 | return IRQ_HANDLED; |
531 | } | 527 | } |
528 | info = &cy_port[channel]; | ||
532 | info->last_active = jiffies; | 529 | info->last_active = jiffies; |
533 | if (info->tty == 0) { | 530 | if (info->tty == 0) { |
534 | base_addr[CyIER] &= ~(CyTxMpty | CyTxRdy); | 531 | base_addr[CyIER] &= ~(CyTxMpty | CyTxRdy); |
diff --git a/drivers/char/tty_ldisc.c b/drivers/char/tty_ldisc.c index aafdbaebc16a..feb55075819b 100644 --- a/drivers/char/tty_ldisc.c +++ b/drivers/char/tty_ldisc.c | |||
@@ -518,7 +518,7 @@ static void tty_ldisc_restore(struct tty_struct *tty, struct tty_ldisc *old) | |||
518 | static int tty_ldisc_halt(struct tty_struct *tty) | 518 | static int tty_ldisc_halt(struct tty_struct *tty) |
519 | { | 519 | { |
520 | clear_bit(TTY_LDISC, &tty->flags); | 520 | clear_bit(TTY_LDISC, &tty->flags); |
521 | return cancel_delayed_work(&tty->buf.work); | 521 | return cancel_delayed_work_sync(&tty->buf.work); |
522 | } | 522 | } |
523 | 523 | ||
524 | /** | 524 | /** |
@@ -756,12 +756,9 @@ void tty_ldisc_hangup(struct tty_struct *tty) | |||
756 | * N_TTY. | 756 | * N_TTY. |
757 | */ | 757 | */ |
758 | if (tty->driver->flags & TTY_DRIVER_RESET_TERMIOS) { | 758 | if (tty->driver->flags & TTY_DRIVER_RESET_TERMIOS) { |
759 | /* Make sure the old ldisc is quiescent */ | ||
760 | tty_ldisc_halt(tty); | ||
761 | flush_scheduled_work(); | ||
762 | |||
763 | /* Avoid racing set_ldisc or tty_ldisc_release */ | 759 | /* Avoid racing set_ldisc or tty_ldisc_release */ |
764 | mutex_lock(&tty->ldisc_mutex); | 760 | mutex_lock(&tty->ldisc_mutex); |
761 | tty_ldisc_halt(tty); | ||
765 | if (tty->ldisc) { /* Not yet closed */ | 762 | if (tty->ldisc) { /* Not yet closed */ |
766 | /* Switch back to N_TTY */ | 763 | /* Switch back to N_TTY */ |
767 | tty_ldisc_reinit(tty); | 764 | tty_ldisc_reinit(tty); |
diff --git a/drivers/char/vt_ioctl.c b/drivers/char/vt_ioctl.c index 29c651ab0d78..6b36ee56e6fe 100644 --- a/drivers/char/vt_ioctl.c +++ b/drivers/char/vt_ioctl.c | |||
@@ -981,8 +981,10 @@ int vt_ioctl(struct tty_struct *tty, struct file * file, | |||
981 | goto eperm; | 981 | goto eperm; |
982 | 982 | ||
983 | if (copy_from_user(&vsa, (struct vt_setactivate __user *)arg, | 983 | if (copy_from_user(&vsa, (struct vt_setactivate __user *)arg, |
984 | sizeof(struct vt_setactivate))) | 984 | sizeof(struct vt_setactivate))) { |
985 | return -EFAULT; | 985 | ret = -EFAULT; |
986 | goto out; | ||
987 | } | ||
986 | if (vsa.console == 0 || vsa.console > MAX_NR_CONSOLES) | 988 | if (vsa.console == 0 || vsa.console > MAX_NR_CONSOLES) |
987 | ret = -ENXIO; | 989 | ret = -ENXIO; |
988 | else { | 990 | else { |
diff --git a/drivers/char/xilinx_hwicap/xilinx_hwicap.c b/drivers/char/xilinx_hwicap/xilinx_hwicap.c index f40ab699860f..4846d50199f3 100644 --- a/drivers/char/xilinx_hwicap/xilinx_hwicap.c +++ b/drivers/char/xilinx_hwicap/xilinx_hwicap.c | |||
@@ -559,7 +559,7 @@ static int hwicap_release(struct inode *inode, struct file *file) | |||
559 | return status; | 559 | return status; |
560 | } | 560 | } |
561 | 561 | ||
562 | static struct file_operations hwicap_fops = { | 562 | static const struct file_operations hwicap_fops = { |
563 | .owner = THIS_MODULE, | 563 | .owner = THIS_MODULE, |
564 | .write = hwicap_write, | 564 | .write = hwicap_write, |
565 | .read = hwicap_read, | 565 | .read = hwicap_read, |
diff --git a/drivers/connector/cn_queue.c b/drivers/connector/cn_queue.c index 4a1dfe1f4ba9..210338ea222f 100644 --- a/drivers/connector/cn_queue.c +++ b/drivers/connector/cn_queue.c | |||
@@ -78,18 +78,20 @@ void cn_queue_wrapper(struct work_struct *work) | |||
78 | struct cn_callback_entry *cbq = | 78 | struct cn_callback_entry *cbq = |
79 | container_of(work, struct cn_callback_entry, work); | 79 | container_of(work, struct cn_callback_entry, work); |
80 | struct cn_callback_data *d = &cbq->data; | 80 | struct cn_callback_data *d = &cbq->data; |
81 | struct cn_msg *msg = NLMSG_DATA(nlmsg_hdr(d->skb)); | ||
82 | struct netlink_skb_parms *nsp = &NETLINK_CB(d->skb); | ||
81 | 83 | ||
82 | d->callback(d->callback_priv); | 84 | d->callback(msg, nsp); |
83 | 85 | ||
84 | d->destruct_data(d->ddata); | 86 | kfree_skb(d->skb); |
85 | d->ddata = NULL; | 87 | d->skb = NULL; |
86 | 88 | ||
87 | kfree(d->free); | 89 | kfree(d->free); |
88 | } | 90 | } |
89 | 91 | ||
90 | static struct cn_callback_entry * | 92 | static struct cn_callback_entry * |
91 | cn_queue_alloc_callback_entry(char *name, struct cb_id *id, | 93 | cn_queue_alloc_callback_entry(char *name, struct cb_id *id, |
92 | void (*callback)(struct cn_msg *)) | 94 | void (*callback)(struct cn_msg *, struct netlink_skb_parms *)) |
93 | { | 95 | { |
94 | struct cn_callback_entry *cbq; | 96 | struct cn_callback_entry *cbq; |
95 | 97 | ||
@@ -123,7 +125,7 @@ int cn_cb_equal(struct cb_id *i1, struct cb_id *i2) | |||
123 | } | 125 | } |
124 | 126 | ||
125 | int cn_queue_add_callback(struct cn_queue_dev *dev, char *name, struct cb_id *id, | 127 | int cn_queue_add_callback(struct cn_queue_dev *dev, char *name, struct cb_id *id, |
126 | void (*callback)(struct cn_msg *)) | 128 | void (*callback)(struct cn_msg *, struct netlink_skb_parms *)) |
127 | { | 129 | { |
128 | struct cn_callback_entry *cbq, *__cbq; | 130 | struct cn_callback_entry *cbq, *__cbq; |
129 | int found = 0; | 131 | int found = 0; |
diff --git a/drivers/connector/connector.c b/drivers/connector/connector.c index 74f52af79563..f06024668f99 100644 --- a/drivers/connector/connector.c +++ b/drivers/connector/connector.c | |||
@@ -129,21 +129,19 @@ EXPORT_SYMBOL_GPL(cn_netlink_send); | |||
129 | /* | 129 | /* |
130 | * Callback helper - queues work and setup destructor for given data. | 130 | * Callback helper - queues work and setup destructor for given data. |
131 | */ | 131 | */ |
132 | static int cn_call_callback(struct cn_msg *msg, void (*destruct_data)(void *), void *data) | 132 | static int cn_call_callback(struct sk_buff *skb) |
133 | { | 133 | { |
134 | struct cn_callback_entry *__cbq, *__new_cbq; | 134 | struct cn_callback_entry *__cbq, *__new_cbq; |
135 | struct cn_dev *dev = &cdev; | 135 | struct cn_dev *dev = &cdev; |
136 | struct cn_msg *msg = NLMSG_DATA(nlmsg_hdr(skb)); | ||
136 | int err = -ENODEV; | 137 | int err = -ENODEV; |
137 | 138 | ||
138 | spin_lock_bh(&dev->cbdev->queue_lock); | 139 | spin_lock_bh(&dev->cbdev->queue_lock); |
139 | list_for_each_entry(__cbq, &dev->cbdev->queue_list, callback_entry) { | 140 | list_for_each_entry(__cbq, &dev->cbdev->queue_list, callback_entry) { |
140 | if (cn_cb_equal(&__cbq->id.id, &msg->id)) { | 141 | if (cn_cb_equal(&__cbq->id.id, &msg->id)) { |
141 | if (likely(!work_pending(&__cbq->work) && | 142 | if (likely(!work_pending(&__cbq->work) && |
142 | __cbq->data.ddata == NULL)) { | 143 | __cbq->data.skb == NULL)) { |
143 | __cbq->data.callback_priv = msg; | 144 | __cbq->data.skb = skb; |
144 | |||
145 | __cbq->data.ddata = data; | ||
146 | __cbq->data.destruct_data = destruct_data; | ||
147 | 145 | ||
148 | if (queue_cn_work(__cbq, &__cbq->work)) | 146 | if (queue_cn_work(__cbq, &__cbq->work)) |
149 | err = 0; | 147 | err = 0; |
@@ -156,10 +154,8 @@ static int cn_call_callback(struct cn_msg *msg, void (*destruct_data)(void *), v | |||
156 | __new_cbq = kzalloc(sizeof(struct cn_callback_entry), GFP_ATOMIC); | 154 | __new_cbq = kzalloc(sizeof(struct cn_callback_entry), GFP_ATOMIC); |
157 | if (__new_cbq) { | 155 | if (__new_cbq) { |
158 | d = &__new_cbq->data; | 156 | d = &__new_cbq->data; |
159 | d->callback_priv = msg; | 157 | d->skb = skb; |
160 | d->callback = __cbq->data.callback; | 158 | d->callback = __cbq->data.callback; |
161 | d->ddata = data; | ||
162 | d->destruct_data = destruct_data; | ||
163 | d->free = __new_cbq; | 159 | d->free = __new_cbq; |
164 | 160 | ||
165 | __new_cbq->pdev = __cbq->pdev; | 161 | __new_cbq->pdev = __cbq->pdev; |
@@ -191,7 +187,6 @@ static int cn_call_callback(struct cn_msg *msg, void (*destruct_data)(void *), v | |||
191 | */ | 187 | */ |
192 | static void cn_rx_skb(struct sk_buff *__skb) | 188 | static void cn_rx_skb(struct sk_buff *__skb) |
193 | { | 189 | { |
194 | struct cn_msg *msg; | ||
195 | struct nlmsghdr *nlh; | 190 | struct nlmsghdr *nlh; |
196 | int err; | 191 | int err; |
197 | struct sk_buff *skb; | 192 | struct sk_buff *skb; |
@@ -208,8 +203,7 @@ static void cn_rx_skb(struct sk_buff *__skb) | |||
208 | return; | 203 | return; |
209 | } | 204 | } |
210 | 205 | ||
211 | msg = NLMSG_DATA(nlh); | 206 | err = cn_call_callback(skb); |
212 | err = cn_call_callback(msg, (void (*)(void *))kfree_skb, skb); | ||
213 | if (err < 0) | 207 | if (err < 0) |
214 | kfree_skb(skb); | 208 | kfree_skb(skb); |
215 | } | 209 | } |
@@ -270,7 +264,7 @@ static void cn_notify(struct cb_id *id, u32 notify_event) | |||
270 | * May sleep. | 264 | * May sleep. |
271 | */ | 265 | */ |
272 | int cn_add_callback(struct cb_id *id, char *name, | 266 | int cn_add_callback(struct cb_id *id, char *name, |
273 | void (*callback)(struct cn_msg *)) | 267 | void (*callback)(struct cn_msg *, struct netlink_skb_parms *)) |
274 | { | 268 | { |
275 | int err; | 269 | int err; |
276 | struct cn_dev *dev = &cdev; | 270 | struct cn_dev *dev = &cdev; |
@@ -352,7 +346,7 @@ static int cn_ctl_msg_equals(struct cn_ctl_msg *m1, struct cn_ctl_msg *m2) | |||
352 | * | 346 | * |
353 | * Used for notification of a request's processing. | 347 | * Used for notification of a request's processing. |
354 | */ | 348 | */ |
355 | static void cn_callback(struct cn_msg *msg) | 349 | static void cn_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp) |
356 | { | 350 | { |
357 | struct cn_ctl_msg *ctl; | 351 | struct cn_ctl_msg *ctl; |
358 | struct cn_ctl_entry *ent; | 352 | struct cn_ctl_entry *ent; |
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index bb11a429394a..662ed923d9eb 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c | |||
@@ -1487,7 +1487,7 @@ static int gpiolib_open(struct inode *inode, struct file *file) | |||
1487 | return single_open(file, gpiolib_show, NULL); | 1487 | return single_open(file, gpiolib_show, NULL); |
1488 | } | 1488 | } |
1489 | 1489 | ||
1490 | static struct file_operations gpiolib_operations = { | 1490 | static const struct file_operations gpiolib_operations = { |
1491 | .open = gpiolib_open, | 1491 | .open = gpiolib_open, |
1492 | .read = seq_read, | 1492 | .read = seq_read, |
1493 | .llseek = seq_lseek, | 1493 | .llseek = seq_lseek, |
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index ba728ad77f2a..8e7b0ebece0c 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c | |||
@@ -482,6 +482,7 @@ void drm_connector_cleanup(struct drm_connector *connector) | |||
482 | list_for_each_entry_safe(mode, t, &connector->user_modes, head) | 482 | list_for_each_entry_safe(mode, t, &connector->user_modes, head) |
483 | drm_mode_remove(connector, mode); | 483 | drm_mode_remove(connector, mode); |
484 | 484 | ||
485 | kfree(connector->fb_helper_private); | ||
485 | mutex_lock(&dev->mode_config.mutex); | 486 | mutex_lock(&dev->mode_config.mutex); |
486 | drm_mode_object_put(dev, &connector->base); | 487 | drm_mode_object_put(dev, &connector->base); |
487 | list_del(&connector->head); | 488 | list_del(&connector->head); |
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index fe8697447f32..1fe4e1d344fd 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c | |||
@@ -32,6 +32,7 @@ | |||
32 | #include "drmP.h" | 32 | #include "drmP.h" |
33 | #include "drm_crtc.h" | 33 | #include "drm_crtc.h" |
34 | #include "drm_crtc_helper.h" | 34 | #include "drm_crtc_helper.h" |
35 | #include "drm_fb_helper.h" | ||
35 | 36 | ||
36 | static void drm_mode_validate_flag(struct drm_connector *connector, | 37 | static void drm_mode_validate_flag(struct drm_connector *connector, |
37 | int flags) | 38 | int flags) |
@@ -90,7 +91,15 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, | |||
90 | list_for_each_entry_safe(mode, t, &connector->modes, head) | 91 | list_for_each_entry_safe(mode, t, &connector->modes, head) |
91 | mode->status = MODE_UNVERIFIED; | 92 | mode->status = MODE_UNVERIFIED; |
92 | 93 | ||
93 | connector->status = connector->funcs->detect(connector); | 94 | if (connector->force) { |
95 | if (connector->force == DRM_FORCE_ON) | ||
96 | connector->status = connector_status_connected; | ||
97 | else | ||
98 | connector->status = connector_status_disconnected; | ||
99 | if (connector->funcs->force) | ||
100 | connector->funcs->force(connector); | ||
101 | } else | ||
102 | connector->status = connector->funcs->detect(connector); | ||
94 | 103 | ||
95 | if (connector->status == connector_status_disconnected) { | 104 | if (connector->status == connector_status_disconnected) { |
96 | DRM_DEBUG_KMS("%s is disconnected\n", | 105 | DRM_DEBUG_KMS("%s is disconnected\n", |
@@ -267,6 +276,65 @@ static struct drm_display_mode *drm_has_preferred_mode(struct drm_connector *con | |||
267 | return NULL; | 276 | return NULL; |
268 | } | 277 | } |
269 | 278 | ||
279 | static bool drm_has_cmdline_mode(struct drm_connector *connector) | ||
280 | { | ||
281 | struct drm_fb_helper_connector *fb_help_conn = connector->fb_helper_private; | ||
282 | struct drm_fb_helper_cmdline_mode *cmdline_mode; | ||
283 | |||
284 | if (!fb_help_conn) | ||
285 | return false; | ||
286 | |||
287 | cmdline_mode = &fb_help_conn->cmdline_mode; | ||
288 | return cmdline_mode->specified; | ||
289 | } | ||
290 | |||
291 | static struct drm_display_mode *drm_pick_cmdline_mode(struct drm_connector *connector, int width, int height) | ||
292 | { | ||
293 | struct drm_fb_helper_connector *fb_help_conn = connector->fb_helper_private; | ||
294 | struct drm_fb_helper_cmdline_mode *cmdline_mode; | ||
295 | struct drm_display_mode *mode = NULL; | ||
296 | |||
297 | if (!fb_help_conn) | ||
298 | return mode; | ||
299 | |||
300 | cmdline_mode = &fb_help_conn->cmdline_mode; | ||
301 | if (cmdline_mode->specified == false) | ||
302 | return mode; | ||
303 | |||
304 | /* attempt to find a matching mode in the list of modes | ||
305 | * we have gotten so far, if not add a CVT mode that conforms | ||
306 | */ | ||
307 | if (cmdline_mode->rb || cmdline_mode->margins) | ||
308 | goto create_mode; | ||
309 | |||
310 | list_for_each_entry(mode, &connector->modes, head) { | ||
311 | /* check width/height */ | ||
312 | if (mode->hdisplay != cmdline_mode->xres || | ||
313 | mode->vdisplay != cmdline_mode->yres) | ||
314 | continue; | ||
315 | |||
316 | if (cmdline_mode->refresh_specified) { | ||
317 | if (mode->vrefresh != cmdline_mode->refresh) | ||
318 | continue; | ||
319 | } | ||
320 | |||
321 | if (cmdline_mode->interlace) { | ||
322 | if (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) | ||
323 | continue; | ||
324 | } | ||
325 | return mode; | ||
326 | } | ||
327 | |||
328 | create_mode: | ||
329 | mode = drm_cvt_mode(connector->dev, cmdline_mode->xres, | ||
330 | cmdline_mode->yres, | ||
331 | cmdline_mode->refresh_specified ? cmdline_mode->refresh : 60, | ||
332 | cmdline_mode->rb, cmdline_mode->interlace, | ||
333 | cmdline_mode->margins); | ||
334 | list_add(&mode->head, &connector->modes); | ||
335 | return mode; | ||
336 | } | ||
337 | |||
270 | static bool drm_connector_enabled(struct drm_connector *connector, bool strict) | 338 | static bool drm_connector_enabled(struct drm_connector *connector, bool strict) |
271 | { | 339 | { |
272 | bool enable; | 340 | bool enable; |
@@ -317,10 +385,16 @@ static bool drm_target_preferred(struct drm_device *dev, | |||
317 | continue; | 385 | continue; |
318 | } | 386 | } |
319 | 387 | ||
320 | DRM_DEBUG_KMS("looking for preferred mode on connector %d\n", | 388 | DRM_DEBUG_KMS("looking for cmdline mode on connector %d\n", |
321 | connector->base.id); | 389 | connector->base.id); |
322 | 390 | ||
323 | modes[i] = drm_has_preferred_mode(connector, width, height); | 391 | /* got for command line mode first */ |
392 | modes[i] = drm_pick_cmdline_mode(connector, width, height); | ||
393 | if (!modes[i]) { | ||
394 | DRM_DEBUG_KMS("looking for preferred mode on connector %d\n", | ||
395 | connector->base.id); | ||
396 | modes[i] = drm_has_preferred_mode(connector, width, height); | ||
397 | } | ||
324 | /* No preferred modes, pick one off the list */ | 398 | /* No preferred modes, pick one off the list */ |
325 | if (!modes[i] && !list_empty(&connector->modes)) { | 399 | if (!modes[i] && !list_empty(&connector->modes)) { |
326 | list_for_each_entry(modes[i], &connector->modes, head) | 400 | list_for_each_entry(modes[i], &connector->modes, head) |
@@ -369,6 +443,8 @@ static int drm_pick_crtcs(struct drm_device *dev, | |||
369 | my_score = 1; | 443 | my_score = 1; |
370 | if (connector->status == connector_status_connected) | 444 | if (connector->status == connector_status_connected) |
371 | my_score++; | 445 | my_score++; |
446 | if (drm_has_cmdline_mode(connector)) | ||
447 | my_score++; | ||
372 | if (drm_has_preferred_mode(connector, width, height)) | 448 | if (drm_has_preferred_mode(connector, width, height)) |
373 | my_score++; | 449 | my_score++; |
374 | 450 | ||
@@ -943,6 +1019,8 @@ bool drm_helper_initial_config(struct drm_device *dev) | |||
943 | { | 1019 | { |
944 | int count = 0; | 1020 | int count = 0; |
945 | 1021 | ||
1022 | drm_fb_helper_parse_command_line(dev); | ||
1023 | |||
946 | count = drm_helper_probe_connector_modes(dev, | 1024 | count = drm_helper_probe_connector_modes(dev, |
947 | dev->mode_config.max_width, | 1025 | dev->mode_config.max_width, |
948 | dev->mode_config.max_height); | 1026 | dev->mode_config.max_height); |
@@ -950,7 +1028,7 @@ bool drm_helper_initial_config(struct drm_device *dev) | |||
950 | /* | 1028 | /* |
951 | * we shouldn't end up with no modes here. | 1029 | * we shouldn't end up with no modes here. |
952 | */ | 1030 | */ |
953 | WARN(!count, "Connected connector with 0 modes\n"); | 1031 | WARN(!count, "No connectors reported connected with modes\n"); |
954 | 1032 | ||
955 | drm_setup_crtcs(dev); | 1033 | drm_setup_crtcs(dev); |
956 | 1034 | ||
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 90d76bacff17..3c0d2b3aed76 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c | |||
@@ -109,7 +109,9 @@ static struct edid_quirk { | |||
109 | 109 | ||
110 | 110 | ||
111 | /* Valid EDID header has these bytes */ | 111 | /* Valid EDID header has these bytes */ |
112 | static u8 edid_header[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; | 112 | static const u8 edid_header[] = { |
113 | 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 | ||
114 | }; | ||
113 | 115 | ||
114 | /** | 116 | /** |
115 | * edid_is_valid - sanity check EDID data | 117 | * edid_is_valid - sanity check EDID data |
@@ -500,6 +502,19 @@ static struct drm_display_mode *drm_find_dmt(struct drm_device *dev, | |||
500 | } | 502 | } |
501 | return mode; | 503 | return mode; |
502 | } | 504 | } |
505 | |||
506 | /* | ||
507 | * 0 is reserved. The spec says 0x01 fill for unused timings. Some old | ||
508 | * monitors fill with ascii space (0x20) instead. | ||
509 | */ | ||
510 | static int | ||
511 | bad_std_timing(u8 a, u8 b) | ||
512 | { | ||
513 | return (a == 0x00 && b == 0x00) || | ||
514 | (a == 0x01 && b == 0x01) || | ||
515 | (a == 0x20 && b == 0x20); | ||
516 | } | ||
517 | |||
503 | /** | 518 | /** |
504 | * drm_mode_std - convert standard mode info (width, height, refresh) into mode | 519 | * drm_mode_std - convert standard mode info (width, height, refresh) into mode |
505 | * @t: standard timing params | 520 | * @t: standard timing params |
@@ -513,6 +528,7 @@ static struct drm_display_mode *drm_find_dmt(struct drm_device *dev, | |||
513 | */ | 528 | */ |
514 | struct drm_display_mode *drm_mode_std(struct drm_device *dev, | 529 | struct drm_display_mode *drm_mode_std(struct drm_device *dev, |
515 | struct std_timing *t, | 530 | struct std_timing *t, |
531 | int revision, | ||
516 | int timing_level) | 532 | int timing_level) |
517 | { | 533 | { |
518 | struct drm_display_mode *mode; | 534 | struct drm_display_mode *mode; |
@@ -523,14 +539,20 @@ struct drm_display_mode *drm_mode_std(struct drm_device *dev, | |||
523 | unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) | 539 | unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) |
524 | >> EDID_TIMING_VFREQ_SHIFT; | 540 | >> EDID_TIMING_VFREQ_SHIFT; |
525 | 541 | ||
542 | if (bad_std_timing(t->hsize, t->vfreq_aspect)) | ||
543 | return NULL; | ||
544 | |||
526 | /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ | 545 | /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ |
527 | hsize = t->hsize * 8 + 248; | 546 | hsize = t->hsize * 8 + 248; |
528 | /* vrefresh_rate = vfreq + 60 */ | 547 | /* vrefresh_rate = vfreq + 60 */ |
529 | vrefresh_rate = vfreq + 60; | 548 | vrefresh_rate = vfreq + 60; |
530 | /* the vdisplay is calculated based on the aspect ratio */ | 549 | /* the vdisplay is calculated based on the aspect ratio */ |
531 | if (aspect_ratio == 0) | 550 | if (aspect_ratio == 0) { |
532 | vsize = (hsize * 10) / 16; | 551 | if (revision < 3) |
533 | else if (aspect_ratio == 1) | 552 | vsize = hsize; |
553 | else | ||
554 | vsize = (hsize * 10) / 16; | ||
555 | } else if (aspect_ratio == 1) | ||
534 | vsize = (hsize * 3) / 4; | 556 | vsize = (hsize * 3) / 4; |
535 | else if (aspect_ratio == 2) | 557 | else if (aspect_ratio == 2) |
536 | vsize = (hsize * 4) / 5; | 558 | vsize = (hsize * 4) / 5; |
@@ -538,7 +560,8 @@ struct drm_display_mode *drm_mode_std(struct drm_device *dev, | |||
538 | vsize = (hsize * 9) / 16; | 560 | vsize = (hsize * 9) / 16; |
539 | /* HDTV hack */ | 561 | /* HDTV hack */ |
540 | if (hsize == 1360 && vsize == 765 && vrefresh_rate == 60) { | 562 | if (hsize == 1360 && vsize == 765 && vrefresh_rate == 60) { |
541 | mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); | 563 | mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, |
564 | false); | ||
542 | mode->hdisplay = 1366; | 565 | mode->hdisplay = 1366; |
543 | mode->vsync_start = mode->vsync_start - 1; | 566 | mode->vsync_start = mode->vsync_start - 1; |
544 | mode->vsync_end = mode->vsync_end - 1; | 567 | mode->vsync_end = mode->vsync_end - 1; |
@@ -557,7 +580,8 @@ struct drm_display_mode *drm_mode_std(struct drm_device *dev, | |||
557 | mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); | 580 | mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); |
558 | break; | 581 | break; |
559 | case LEVEL_CVT: | 582 | case LEVEL_CVT: |
560 | mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); | 583 | mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, |
584 | false); | ||
561 | break; | 585 | break; |
562 | } | 586 | } |
563 | return mode; | 587 | return mode; |
@@ -779,7 +803,7 @@ static int add_standard_modes(struct drm_connector *connector, struct edid *edid | |||
779 | continue; | 803 | continue; |
780 | 804 | ||
781 | newmode = drm_mode_std(dev, &edid->standard_timings[i], | 805 | newmode = drm_mode_std(dev, &edid->standard_timings[i], |
782 | timing_level); | 806 | edid->revision, timing_level); |
783 | if (newmode) { | 807 | if (newmode) { |
784 | drm_mode_probed_add(connector, newmode); | 808 | drm_mode_probed_add(connector, newmode); |
785 | modes++; | 809 | modes++; |
@@ -829,13 +853,13 @@ static int add_detailed_info(struct drm_connector *connector, | |||
829 | case EDID_DETAIL_MONITOR_CPDATA: | 853 | case EDID_DETAIL_MONITOR_CPDATA: |
830 | break; | 854 | break; |
831 | case EDID_DETAIL_STD_MODES: | 855 | case EDID_DETAIL_STD_MODES: |
832 | /* Five modes per detailed section */ | 856 | for (j = 0; j < 6; i++) { |
833 | for (j = 0; j < 5; i++) { | ||
834 | struct std_timing *std; | 857 | struct std_timing *std; |
835 | struct drm_display_mode *newmode; | 858 | struct drm_display_mode *newmode; |
836 | 859 | ||
837 | std = &data->data.timings[j]; | 860 | std = &data->data.timings[j]; |
838 | newmode = drm_mode_std(dev, std, | 861 | newmode = drm_mode_std(dev, std, |
862 | edid->revision, | ||
839 | timing_level); | 863 | timing_level); |
840 | if (newmode) { | 864 | if (newmode) { |
841 | drm_mode_probed_add(connector, newmode); | 865 | drm_mode_probed_add(connector, newmode); |
@@ -964,7 +988,9 @@ static int add_detailed_info_eedid(struct drm_connector *connector, | |||
964 | struct drm_display_mode *newmode; | 988 | struct drm_display_mode *newmode; |
965 | 989 | ||
966 | std = &data->data.timings[j]; | 990 | std = &data->data.timings[j]; |
967 | newmode = drm_mode_std(dev, std, timing_level); | 991 | newmode = drm_mode_std(dev, std, |
992 | edid->revision, | ||
993 | timing_level); | ||
968 | if (newmode) { | 994 | if (newmode) { |
969 | drm_mode_probed_add(connector, newmode); | 995 | drm_mode_probed_add(connector, newmode); |
970 | modes++; | 996 | modes++; |
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index 2c4671314884..819ddcbfcce5 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c | |||
@@ -40,6 +40,199 @@ MODULE_LICENSE("GPL and additional rights"); | |||
40 | 40 | ||
41 | static LIST_HEAD(kernel_fb_helper_list); | 41 | static LIST_HEAD(kernel_fb_helper_list); |
42 | 42 | ||
43 | int drm_fb_helper_add_connector(struct drm_connector *connector) | ||
44 | { | ||
45 | connector->fb_helper_private = kzalloc(sizeof(struct drm_fb_helper_connector), GFP_KERNEL); | ||
46 | if (!connector->fb_helper_private) | ||
47 | return -ENOMEM; | ||
48 | |||
49 | return 0; | ||
50 | } | ||
51 | EXPORT_SYMBOL(drm_fb_helper_add_connector); | ||
52 | |||
53 | static int my_atoi(const char *name) | ||
54 | { | ||
55 | int val = 0; | ||
56 | |||
57 | for (;; name++) { | ||
58 | switch (*name) { | ||
59 | case '0' ... '9': | ||
60 | val = 10*val+(*name-'0'); | ||
61 | break; | ||
62 | default: | ||
63 | return val; | ||
64 | } | ||
65 | } | ||
66 | } | ||
67 | |||
68 | /** | ||
69 | * drm_fb_helper_connector_parse_command_line - parse command line for connector | ||
70 | * @connector - connector to parse line for | ||
71 | * @mode_option - per connector mode option | ||
72 | * | ||
73 | * This parses the connector specific then generic command lines for | ||
74 | * modes and options to configure the connector. | ||
75 | * | ||
76 | * This uses the same parameters as the fb modedb.c, except for extra | ||
77 | * <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd] | ||
78 | * | ||
79 | * enable/enable Digital/disable bit at the end | ||
80 | */ | ||
81 | static bool drm_fb_helper_connector_parse_command_line(struct drm_connector *connector, | ||
82 | const char *mode_option) | ||
83 | { | ||
84 | const char *name; | ||
85 | unsigned int namelen; | ||
86 | int res_specified = 0, bpp_specified = 0, refresh_specified = 0; | ||
87 | unsigned int xres = 0, yres = 0, bpp = 32, refresh = 0; | ||
88 | int yres_specified = 0, cvt = 0, rb = 0, interlace = 0, margins = 0; | ||
89 | int i; | ||
90 | enum drm_connector_force force = DRM_FORCE_UNSPECIFIED; | ||
91 | struct drm_fb_helper_connector *fb_help_conn = connector->fb_helper_private; | ||
92 | struct drm_fb_helper_cmdline_mode *cmdline_mode; | ||
93 | |||
94 | if (!fb_help_conn) | ||
95 | return false; | ||
96 | |||
97 | cmdline_mode = &fb_help_conn->cmdline_mode; | ||
98 | if (!mode_option) | ||
99 | mode_option = fb_mode_option; | ||
100 | |||
101 | if (!mode_option) { | ||
102 | cmdline_mode->specified = false; | ||
103 | return false; | ||
104 | } | ||
105 | |||
106 | name = mode_option; | ||
107 | namelen = strlen(name); | ||
108 | for (i = namelen-1; i >= 0; i--) { | ||
109 | switch (name[i]) { | ||
110 | case '@': | ||
111 | namelen = i; | ||
112 | if (!refresh_specified && !bpp_specified && | ||
113 | !yres_specified) { | ||
114 | refresh = my_atoi(&name[i+1]); | ||
115 | refresh_specified = 1; | ||
116 | if (cvt || rb) | ||
117 | cvt = 0; | ||
118 | } else | ||
119 | goto done; | ||
120 | break; | ||
121 | case '-': | ||
122 | namelen = i; | ||
123 | if (!bpp_specified && !yres_specified) { | ||
124 | bpp = my_atoi(&name[i+1]); | ||
125 | bpp_specified = 1; | ||
126 | if (cvt || rb) | ||
127 | cvt = 0; | ||
128 | } else | ||
129 | goto done; | ||
130 | break; | ||
131 | case 'x': | ||
132 | if (!yres_specified) { | ||
133 | yres = my_atoi(&name[i+1]); | ||
134 | yres_specified = 1; | ||
135 | } else | ||
136 | goto done; | ||
137 | case '0' ... '9': | ||
138 | break; | ||
139 | case 'M': | ||
140 | if (!yres_specified) | ||
141 | cvt = 1; | ||
142 | break; | ||
143 | case 'R': | ||
144 | if (!cvt) | ||
145 | rb = 1; | ||
146 | break; | ||
147 | case 'm': | ||
148 | if (!cvt) | ||
149 | margins = 1; | ||
150 | break; | ||
151 | case 'i': | ||
152 | if (!cvt) | ||
153 | interlace = 1; | ||
154 | break; | ||
155 | case 'e': | ||
156 | force = DRM_FORCE_ON; | ||
157 | break; | ||
158 | case 'D': | ||
159 | if ((connector->connector_type != DRM_MODE_CONNECTOR_DVII) || | ||
160 | (connector->connector_type != DRM_MODE_CONNECTOR_HDMIB)) | ||
161 | force = DRM_FORCE_ON; | ||
162 | else | ||
163 | force = DRM_FORCE_ON_DIGITAL; | ||
164 | break; | ||
165 | case 'd': | ||
166 | force = DRM_FORCE_OFF; | ||
167 | break; | ||
168 | default: | ||
169 | goto done; | ||
170 | } | ||
171 | } | ||
172 | if (i < 0 && yres_specified) { | ||
173 | xres = my_atoi(name); | ||
174 | res_specified = 1; | ||
175 | } | ||
176 | done: | ||
177 | |||
178 | DRM_DEBUG_KMS("cmdline mode for connector %s %dx%d@%dHz%s%s%s\n", | ||
179 | drm_get_connector_name(connector), xres, yres, | ||
180 | (refresh) ? refresh : 60, (rb) ? " reduced blanking" : | ||
181 | "", (margins) ? " with margins" : "", (interlace) ? | ||
182 | " interlaced" : ""); | ||
183 | |||
184 | if (force) { | ||
185 | const char *s; | ||
186 | switch (force) { | ||
187 | case DRM_FORCE_OFF: s = "OFF"; break; | ||
188 | case DRM_FORCE_ON_DIGITAL: s = "ON - dig"; break; | ||
189 | default: | ||
190 | case DRM_FORCE_ON: s = "ON"; break; | ||
191 | } | ||
192 | |||
193 | DRM_INFO("forcing %s connector %s\n", | ||
194 | drm_get_connector_name(connector), s); | ||
195 | connector->force = force; | ||
196 | } | ||
197 | |||
198 | if (res_specified) { | ||
199 | cmdline_mode->specified = true; | ||
200 | cmdline_mode->xres = xres; | ||
201 | cmdline_mode->yres = yres; | ||
202 | } | ||
203 | |||
204 | if (refresh_specified) { | ||
205 | cmdline_mode->refresh_specified = true; | ||
206 | cmdline_mode->refresh = refresh; | ||
207 | } | ||
208 | |||
209 | if (bpp_specified) { | ||
210 | cmdline_mode->bpp_specified = true; | ||
211 | cmdline_mode->bpp = bpp; | ||
212 | } | ||
213 | cmdline_mode->rb = rb ? true : false; | ||
214 | cmdline_mode->cvt = cvt ? true : false; | ||
215 | cmdline_mode->interlace = interlace ? true : false; | ||
216 | |||
217 | return true; | ||
218 | } | ||
219 | |||
220 | int drm_fb_helper_parse_command_line(struct drm_device *dev) | ||
221 | { | ||
222 | struct drm_connector *connector; | ||
223 | |||
224 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | ||
225 | char *option = NULL; | ||
226 | |||
227 | /* do something on return - turn off connector maybe */ | ||
228 | if (fb_get_options(drm_get_connector_name(connector), &option)) | ||
229 | continue; | ||
230 | |||
231 | drm_fb_helper_connector_parse_command_line(connector, option); | ||
232 | } | ||
233 | return 0; | ||
234 | } | ||
235 | |||
43 | bool drm_fb_helper_force_kernel_mode(void) | 236 | bool drm_fb_helper_force_kernel_mode(void) |
44 | { | 237 | { |
45 | int i = 0; | 238 | int i = 0; |
@@ -87,6 +280,7 @@ void drm_fb_helper_restore(void) | |||
87 | } | 280 | } |
88 | EXPORT_SYMBOL(drm_fb_helper_restore); | 281 | EXPORT_SYMBOL(drm_fb_helper_restore); |
89 | 282 | ||
283 | #ifdef CONFIG_MAGIC_SYSRQ | ||
90 | static void drm_fb_helper_restore_work_fn(struct work_struct *ignored) | 284 | static void drm_fb_helper_restore_work_fn(struct work_struct *ignored) |
91 | { | 285 | { |
92 | drm_fb_helper_restore(); | 286 | drm_fb_helper_restore(); |
@@ -103,6 +297,7 @@ static struct sysrq_key_op sysrq_drm_fb_helper_restore_op = { | |||
103 | .help_msg = "force-fb(V)", | 297 | .help_msg = "force-fb(V)", |
104 | .action_msg = "Restore framebuffer console", | 298 | .action_msg = "Restore framebuffer console", |
105 | }; | 299 | }; |
300 | #endif | ||
106 | 301 | ||
107 | static void drm_fb_helper_on(struct fb_info *info) | 302 | static void drm_fb_helper_on(struct fb_info *info) |
108 | { | 303 | { |
@@ -484,6 +679,8 @@ int drm_fb_helper_single_fb_probe(struct drm_device *dev, | |||
484 | uint32_t fb_height, | 679 | uint32_t fb_height, |
485 | uint32_t surface_width, | 680 | uint32_t surface_width, |
486 | uint32_t surface_height, | 681 | uint32_t surface_height, |
682 | uint32_t surface_depth, | ||
683 | uint32_t surface_bpp, | ||
487 | struct drm_framebuffer **fb_ptr)) | 684 | struct drm_framebuffer **fb_ptr)) |
488 | { | 685 | { |
489 | struct drm_crtc *crtc; | 686 | struct drm_crtc *crtc; |
@@ -497,8 +694,43 @@ int drm_fb_helper_single_fb_probe(struct drm_device *dev, | |||
497 | struct drm_framebuffer *fb; | 694 | struct drm_framebuffer *fb; |
498 | struct drm_mode_set *modeset = NULL; | 695 | struct drm_mode_set *modeset = NULL; |
499 | struct drm_fb_helper *fb_helper; | 696 | struct drm_fb_helper *fb_helper; |
697 | uint32_t surface_depth = 24, surface_bpp = 32; | ||
500 | 698 | ||
501 | /* first up get a count of crtcs now in use and new min/maxes width/heights */ | 699 | /* first up get a count of crtcs now in use and new min/maxes width/heights */ |
700 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | ||
701 | struct drm_fb_helper_connector *fb_help_conn = connector->fb_helper_private; | ||
702 | |||
703 | struct drm_fb_helper_cmdline_mode *cmdline_mode; | ||
704 | |||
705 | if (!fb_help_conn) | ||
706 | continue; | ||
707 | |||
708 | cmdline_mode = &fb_help_conn->cmdline_mode; | ||
709 | |||
710 | if (cmdline_mode->bpp_specified) { | ||
711 | switch (cmdline_mode->bpp) { | ||
712 | case 8: | ||
713 | surface_depth = surface_bpp = 8; | ||
714 | break; | ||
715 | case 15: | ||
716 | surface_depth = 15; | ||
717 | surface_bpp = 16; | ||
718 | break; | ||
719 | case 16: | ||
720 | surface_depth = surface_bpp = 16; | ||
721 | break; | ||
722 | case 24: | ||
723 | surface_depth = surface_bpp = 24; | ||
724 | break; | ||
725 | case 32: | ||
726 | surface_depth = 24; | ||
727 | surface_bpp = 32; | ||
728 | break; | ||
729 | } | ||
730 | break; | ||
731 | } | ||
732 | } | ||
733 | |||
502 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | 734 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
503 | if (drm_helper_crtc_in_use(crtc)) { | 735 | if (drm_helper_crtc_in_use(crtc)) { |
504 | if (crtc->desired_mode) { | 736 | if (crtc->desired_mode) { |
@@ -527,7 +759,8 @@ int drm_fb_helper_single_fb_probe(struct drm_device *dev, | |||
527 | /* do we have an fb already? */ | 759 | /* do we have an fb already? */ |
528 | if (list_empty(&dev->mode_config.fb_kernel_list)) { | 760 | if (list_empty(&dev->mode_config.fb_kernel_list)) { |
529 | ret = (*fb_create)(dev, fb_width, fb_height, surface_width, | 761 | ret = (*fb_create)(dev, fb_width, fb_height, surface_width, |
530 | surface_height, &fb); | 762 | surface_height, surface_depth, surface_bpp, |
763 | &fb); | ||
531 | if (ret) | 764 | if (ret) |
532 | return -EINVAL; | 765 | return -EINVAL; |
533 | new_fb = 1; | 766 | new_fb = 1; |
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c index 49404ce1666e..51f677215f1d 100644 --- a/drivers/gpu/drm/drm_modes.c +++ b/drivers/gpu/drm/drm_modes.c | |||
@@ -88,7 +88,7 @@ EXPORT_SYMBOL(drm_mode_debug_printmodeline); | |||
88 | #define HV_FACTOR 1000 | 88 | #define HV_FACTOR 1000 |
89 | struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay, | 89 | struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay, |
90 | int vdisplay, int vrefresh, | 90 | int vdisplay, int vrefresh, |
91 | bool reduced, bool interlaced) | 91 | bool reduced, bool interlaced, bool margins) |
92 | { | 92 | { |
93 | /* 1) top/bottom margin size (% of height) - default: 1.8, */ | 93 | /* 1) top/bottom margin size (% of height) - default: 1.8, */ |
94 | #define CVT_MARGIN_PERCENTAGE 18 | 94 | #define CVT_MARGIN_PERCENTAGE 18 |
@@ -101,7 +101,6 @@ struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay, | |||
101 | /* Pixel Clock step (kHz) */ | 101 | /* Pixel Clock step (kHz) */ |
102 | #define CVT_CLOCK_STEP 250 | 102 | #define CVT_CLOCK_STEP 250 |
103 | struct drm_display_mode *drm_mode; | 103 | struct drm_display_mode *drm_mode; |
104 | bool margins = false; | ||
105 | unsigned int vfieldrate, hperiod; | 104 | unsigned int vfieldrate, hperiod; |
106 | int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync; | 105 | int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync; |
107 | int interlace; | 106 | int interlace; |
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c index 7ba4a232a97f..e85d7e9eed7d 100644 --- a/drivers/gpu/drm/i915/intel_fb.c +++ b/drivers/gpu/drm/i915/intel_fb.c | |||
@@ -110,6 +110,7 @@ EXPORT_SYMBOL(intelfb_resize); | |||
110 | static int intelfb_create(struct drm_device *dev, uint32_t fb_width, | 110 | static int intelfb_create(struct drm_device *dev, uint32_t fb_width, |
111 | uint32_t fb_height, uint32_t surface_width, | 111 | uint32_t fb_height, uint32_t surface_width, |
112 | uint32_t surface_height, | 112 | uint32_t surface_height, |
113 | uint32_t surface_depth, uint32_t surface_bpp, | ||
113 | struct drm_framebuffer **fb_p) | 114 | struct drm_framebuffer **fb_p) |
114 | { | 115 | { |
115 | struct fb_info *info; | 116 | struct fb_info *info; |
@@ -125,9 +126,9 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width, | |||
125 | mode_cmd.width = surface_width; | 126 | mode_cmd.width = surface_width; |
126 | mode_cmd.height = surface_height; | 127 | mode_cmd.height = surface_height; |
127 | 128 | ||
128 | mode_cmd.bpp = 32; | 129 | mode_cmd.bpp = surface_bpp; |
129 | mode_cmd.pitch = ALIGN(mode_cmd.width * ((mode_cmd.bpp + 1) / 8), 64); | 130 | mode_cmd.pitch = ALIGN(mode_cmd.width * ((mode_cmd.bpp + 1) / 8), 64); |
130 | mode_cmd.depth = 24; | 131 | mode_cmd.depth = surface_depth; |
131 | 132 | ||
132 | size = mode_cmd.pitch * mode_cmd.height; | 133 | size = mode_cmd.pitch * mode_cmd.height; |
133 | size = ALIGN(size, PAGE_SIZE); | 134 | size = ALIGN(size, PAGE_SIZE); |
diff --git a/drivers/gpu/drm/radeon/.gitignore b/drivers/gpu/drm/radeon/.gitignore new file mode 100644 index 000000000000..403eb3a5891f --- /dev/null +++ b/drivers/gpu/drm/radeon/.gitignore | |||
@@ -0,0 +1,3 @@ | |||
1 | mkregtable | ||
2 | *_reg_safe.h | ||
3 | |||
diff --git a/drivers/gpu/drm/radeon/avivod.h b/drivers/gpu/drm/radeon/avivod.h index e2b92c445bab..d4e6e6e4a938 100644 --- a/drivers/gpu/drm/radeon/avivod.h +++ b/drivers/gpu/drm/radeon/avivod.h | |||
@@ -57,13 +57,4 @@ | |||
57 | #define VGA_RENDER_CONTROL 0x0300 | 57 | #define VGA_RENDER_CONTROL 0x0300 |
58 | #define VGA_VSTATUS_CNTL_MASK 0x00030000 | 58 | #define VGA_VSTATUS_CNTL_MASK 0x00030000 |
59 | 59 | ||
60 | /* AVIVO disable VGA rendering */ | ||
61 | static inline void radeon_avivo_vga_render_disable(struct radeon_device *rdev) | ||
62 | { | ||
63 | u32 vga_render; | ||
64 | vga_render = RREG32(VGA_RENDER_CONTROL); | ||
65 | vga_render &= ~VGA_VSTATUS_CNTL_MASK; | ||
66 | WREG32(VGA_RENDER_CONTROL, vga_render); | ||
67 | } | ||
68 | |||
69 | #endif | 60 | #endif |
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index be51c5f7d0f6..e6cce24de802 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c | |||
@@ -863,13 +863,11 @@ int r100_cs_parse_packet0(struct radeon_cs_parser *p, | |||
863 | void r100_cs_dump_packet(struct radeon_cs_parser *p, | 863 | void r100_cs_dump_packet(struct radeon_cs_parser *p, |
864 | struct radeon_cs_packet *pkt) | 864 | struct radeon_cs_packet *pkt) |
865 | { | 865 | { |
866 | struct radeon_cs_chunk *ib_chunk; | ||
867 | volatile uint32_t *ib; | 866 | volatile uint32_t *ib; |
868 | unsigned i; | 867 | unsigned i; |
869 | unsigned idx; | 868 | unsigned idx; |
870 | 869 | ||
871 | ib = p->ib->ptr; | 870 | ib = p->ib->ptr; |
872 | ib_chunk = &p->chunks[p->chunk_ib_idx]; | ||
873 | idx = pkt->idx; | 871 | idx = pkt->idx; |
874 | for (i = 0; i <= (pkt->count + 1); i++, idx++) { | 872 | for (i = 0; i <= (pkt->count + 1); i++, idx++) { |
875 | DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); | 873 | DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); |
@@ -896,7 +894,7 @@ int r100_cs_packet_parse(struct radeon_cs_parser *p, | |||
896 | idx, ib_chunk->length_dw); | 894 | idx, ib_chunk->length_dw); |
897 | return -EINVAL; | 895 | return -EINVAL; |
898 | } | 896 | } |
899 | header = ib_chunk->kdata[idx]; | 897 | header = radeon_get_ib_value(p, idx); |
900 | pkt->idx = idx; | 898 | pkt->idx = idx; |
901 | pkt->type = CP_PACKET_GET_TYPE(header); | 899 | pkt->type = CP_PACKET_GET_TYPE(header); |
902 | pkt->count = CP_PACKET_GET_COUNT(header); | 900 | pkt->count = CP_PACKET_GET_COUNT(header); |
@@ -939,7 +937,6 @@ int r100_cs_packet_parse(struct radeon_cs_parser *p, | |||
939 | */ | 937 | */ |
940 | int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) | 938 | int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) |
941 | { | 939 | { |
942 | struct radeon_cs_chunk *ib_chunk; | ||
943 | struct drm_mode_object *obj; | 940 | struct drm_mode_object *obj; |
944 | struct drm_crtc *crtc; | 941 | struct drm_crtc *crtc; |
945 | struct radeon_crtc *radeon_crtc; | 942 | struct radeon_crtc *radeon_crtc; |
@@ -947,8 +944,9 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) | |||
947 | int crtc_id; | 944 | int crtc_id; |
948 | int r; | 945 | int r; |
949 | uint32_t header, h_idx, reg; | 946 | uint32_t header, h_idx, reg; |
947 | volatile uint32_t *ib; | ||
950 | 948 | ||
951 | ib_chunk = &p->chunks[p->chunk_ib_idx]; | 949 | ib = p->ib->ptr; |
952 | 950 | ||
953 | /* parse the wait until */ | 951 | /* parse the wait until */ |
954 | r = r100_cs_packet_parse(p, &waitreloc, p->idx); | 952 | r = r100_cs_packet_parse(p, &waitreloc, p->idx); |
@@ -963,24 +961,24 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) | |||
963 | return r; | 961 | return r; |
964 | } | 962 | } |
965 | 963 | ||
966 | if (ib_chunk->kdata[waitreloc.idx + 1] != RADEON_WAIT_CRTC_VLINE) { | 964 | if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { |
967 | DRM_ERROR("vline wait had illegal wait until\n"); | 965 | DRM_ERROR("vline wait had illegal wait until\n"); |
968 | r = -EINVAL; | 966 | r = -EINVAL; |
969 | return r; | 967 | return r; |
970 | } | 968 | } |
971 | 969 | ||
972 | /* jump over the NOP */ | 970 | /* jump over the NOP */ |
973 | r = r100_cs_packet_parse(p, &p3reloc, p->idx); | 971 | r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); |
974 | if (r) | 972 | if (r) |
975 | return r; | 973 | return r; |
976 | 974 | ||
977 | h_idx = p->idx - 2; | 975 | h_idx = p->idx - 2; |
978 | p->idx += waitreloc.count; | 976 | p->idx += waitreloc.count + 2; |
979 | p->idx += p3reloc.count; | 977 | p->idx += p3reloc.count + 2; |
980 | 978 | ||
981 | header = ib_chunk->kdata[h_idx]; | 979 | header = radeon_get_ib_value(p, h_idx); |
982 | crtc_id = ib_chunk->kdata[h_idx + 5]; | 980 | crtc_id = radeon_get_ib_value(p, h_idx + 5); |
983 | reg = ib_chunk->kdata[h_idx] >> 2; | 981 | reg = header >> 2; |
984 | mutex_lock(&p->rdev->ddev->mode_config.mutex); | 982 | mutex_lock(&p->rdev->ddev->mode_config.mutex); |
985 | obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); | 983 | obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); |
986 | if (!obj) { | 984 | if (!obj) { |
@@ -994,16 +992,16 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) | |||
994 | 992 | ||
995 | if (!crtc->enabled) { | 993 | if (!crtc->enabled) { |
996 | /* if the CRTC isn't enabled - we need to nop out the wait until */ | 994 | /* if the CRTC isn't enabled - we need to nop out the wait until */ |
997 | ib_chunk->kdata[h_idx + 2] = PACKET2(0); | 995 | ib[h_idx + 2] = PACKET2(0); |
998 | ib_chunk->kdata[h_idx + 3] = PACKET2(0); | 996 | ib[h_idx + 3] = PACKET2(0); |
999 | } else if (crtc_id == 1) { | 997 | } else if (crtc_id == 1) { |
1000 | switch (reg) { | 998 | switch (reg) { |
1001 | case AVIVO_D1MODE_VLINE_START_END: | 999 | case AVIVO_D1MODE_VLINE_START_END: |
1002 | header &= R300_CP_PACKET0_REG_MASK; | 1000 | header &= ~R300_CP_PACKET0_REG_MASK; |
1003 | header |= AVIVO_D2MODE_VLINE_START_END >> 2; | 1001 | header |= AVIVO_D2MODE_VLINE_START_END >> 2; |
1004 | break; | 1002 | break; |
1005 | case RADEON_CRTC_GUI_TRIG_VLINE: | 1003 | case RADEON_CRTC_GUI_TRIG_VLINE: |
1006 | header &= R300_CP_PACKET0_REG_MASK; | 1004 | header &= ~R300_CP_PACKET0_REG_MASK; |
1007 | header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; | 1005 | header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; |
1008 | break; | 1006 | break; |
1009 | default: | 1007 | default: |
@@ -1011,8 +1009,8 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) | |||
1011 | r = -EINVAL; | 1009 | r = -EINVAL; |
1012 | goto out; | 1010 | goto out; |
1013 | } | 1011 | } |
1014 | ib_chunk->kdata[h_idx] = header; | 1012 | ib[h_idx] = header; |
1015 | ib_chunk->kdata[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; | 1013 | ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; |
1016 | } | 1014 | } |
1017 | out: | 1015 | out: |
1018 | mutex_unlock(&p->rdev->ddev->mode_config.mutex); | 1016 | mutex_unlock(&p->rdev->ddev->mode_config.mutex); |
@@ -1033,7 +1031,6 @@ out: | |||
1033 | int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, | 1031 | int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, |
1034 | struct radeon_cs_reloc **cs_reloc) | 1032 | struct radeon_cs_reloc **cs_reloc) |
1035 | { | 1033 | { |
1036 | struct radeon_cs_chunk *ib_chunk; | ||
1037 | struct radeon_cs_chunk *relocs_chunk; | 1034 | struct radeon_cs_chunk *relocs_chunk; |
1038 | struct radeon_cs_packet p3reloc; | 1035 | struct radeon_cs_packet p3reloc; |
1039 | unsigned idx; | 1036 | unsigned idx; |
@@ -1044,7 +1041,6 @@ int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, | |||
1044 | return -EINVAL; | 1041 | return -EINVAL; |
1045 | } | 1042 | } |
1046 | *cs_reloc = NULL; | 1043 | *cs_reloc = NULL; |
1047 | ib_chunk = &p->chunks[p->chunk_ib_idx]; | ||
1048 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; | 1044 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; |
1049 | r = r100_cs_packet_parse(p, &p3reloc, p->idx); | 1045 | r = r100_cs_packet_parse(p, &p3reloc, p->idx); |
1050 | if (r) { | 1046 | if (r) { |
@@ -1057,7 +1053,7 @@ int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, | |||
1057 | r100_cs_dump_packet(p, &p3reloc); | 1053 | r100_cs_dump_packet(p, &p3reloc); |
1058 | return -EINVAL; | 1054 | return -EINVAL; |
1059 | } | 1055 | } |
1060 | idx = ib_chunk->kdata[p3reloc.idx + 1]; | 1056 | idx = radeon_get_ib_value(p, p3reloc.idx + 1); |
1061 | if (idx >= relocs_chunk->length_dw) { | 1057 | if (idx >= relocs_chunk->length_dw) { |
1062 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", | 1058 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", |
1063 | idx, relocs_chunk->length_dw); | 1059 | idx, relocs_chunk->length_dw); |
@@ -1126,7 +1122,6 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1126 | struct radeon_cs_packet *pkt, | 1122 | struct radeon_cs_packet *pkt, |
1127 | unsigned idx, unsigned reg) | 1123 | unsigned idx, unsigned reg) |
1128 | { | 1124 | { |
1129 | struct radeon_cs_chunk *ib_chunk; | ||
1130 | struct radeon_cs_reloc *reloc; | 1125 | struct radeon_cs_reloc *reloc; |
1131 | struct r100_cs_track *track; | 1126 | struct r100_cs_track *track; |
1132 | volatile uint32_t *ib; | 1127 | volatile uint32_t *ib; |
@@ -1134,11 +1129,13 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1134 | int r; | 1129 | int r; |
1135 | int i, face; | 1130 | int i, face; |
1136 | u32 tile_flags = 0; | 1131 | u32 tile_flags = 0; |
1132 | u32 idx_value; | ||
1137 | 1133 | ||
1138 | ib = p->ib->ptr; | 1134 | ib = p->ib->ptr; |
1139 | ib_chunk = &p->chunks[p->chunk_ib_idx]; | ||
1140 | track = (struct r100_cs_track *)p->track; | 1135 | track = (struct r100_cs_track *)p->track; |
1141 | 1136 | ||
1137 | idx_value = radeon_get_ib_value(p, idx); | ||
1138 | |||
1142 | switch (reg) { | 1139 | switch (reg) { |
1143 | case RADEON_CRTC_GUI_TRIG_VLINE: | 1140 | case RADEON_CRTC_GUI_TRIG_VLINE: |
1144 | r = r100_cs_packet_parse_vline(p); | 1141 | r = r100_cs_packet_parse_vline(p); |
@@ -1166,8 +1163,8 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1166 | return r; | 1163 | return r; |
1167 | } | 1164 | } |
1168 | track->zb.robj = reloc->robj; | 1165 | track->zb.robj = reloc->robj; |
1169 | track->zb.offset = ib_chunk->kdata[idx]; | 1166 | track->zb.offset = idx_value; |
1170 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); | 1167 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1171 | break; | 1168 | break; |
1172 | case RADEON_RB3D_COLOROFFSET: | 1169 | case RADEON_RB3D_COLOROFFSET: |
1173 | r = r100_cs_packet_next_reloc(p, &reloc); | 1170 | r = r100_cs_packet_next_reloc(p, &reloc); |
@@ -1178,8 +1175,8 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1178 | return r; | 1175 | return r; |
1179 | } | 1176 | } |
1180 | track->cb[0].robj = reloc->robj; | 1177 | track->cb[0].robj = reloc->robj; |
1181 | track->cb[0].offset = ib_chunk->kdata[idx]; | 1178 | track->cb[0].offset = idx_value; |
1182 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); | 1179 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1183 | break; | 1180 | break; |
1184 | case RADEON_PP_TXOFFSET_0: | 1181 | case RADEON_PP_TXOFFSET_0: |
1185 | case RADEON_PP_TXOFFSET_1: | 1182 | case RADEON_PP_TXOFFSET_1: |
@@ -1192,7 +1189,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1192 | r100_cs_dump_packet(p, pkt); | 1189 | r100_cs_dump_packet(p, pkt); |
1193 | return r; | 1190 | return r; |
1194 | } | 1191 | } |
1195 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); | 1192 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1196 | track->textures[i].robj = reloc->robj; | 1193 | track->textures[i].robj = reloc->robj; |
1197 | break; | 1194 | break; |
1198 | case RADEON_PP_CUBIC_OFFSET_T0_0: | 1195 | case RADEON_PP_CUBIC_OFFSET_T0_0: |
@@ -1208,8 +1205,8 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1208 | r100_cs_dump_packet(p, pkt); | 1205 | r100_cs_dump_packet(p, pkt); |
1209 | return r; | 1206 | return r; |
1210 | } | 1207 | } |
1211 | track->textures[0].cube_info[i].offset = ib_chunk->kdata[idx]; | 1208 | track->textures[0].cube_info[i].offset = idx_value; |
1212 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); | 1209 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1213 | track->textures[0].cube_info[i].robj = reloc->robj; | 1210 | track->textures[0].cube_info[i].robj = reloc->robj; |
1214 | break; | 1211 | break; |
1215 | case RADEON_PP_CUBIC_OFFSET_T1_0: | 1212 | case RADEON_PP_CUBIC_OFFSET_T1_0: |
@@ -1225,8 +1222,8 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1225 | r100_cs_dump_packet(p, pkt); | 1222 | r100_cs_dump_packet(p, pkt); |
1226 | return r; | 1223 | return r; |
1227 | } | 1224 | } |
1228 | track->textures[1].cube_info[i].offset = ib_chunk->kdata[idx]; | 1225 | track->textures[1].cube_info[i].offset = idx_value; |
1229 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); | 1226 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1230 | track->textures[1].cube_info[i].robj = reloc->robj; | 1227 | track->textures[1].cube_info[i].robj = reloc->robj; |
1231 | break; | 1228 | break; |
1232 | case RADEON_PP_CUBIC_OFFSET_T2_0: | 1229 | case RADEON_PP_CUBIC_OFFSET_T2_0: |
@@ -1242,12 +1239,12 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1242 | r100_cs_dump_packet(p, pkt); | 1239 | r100_cs_dump_packet(p, pkt); |
1243 | return r; | 1240 | return r; |
1244 | } | 1241 | } |
1245 | track->textures[2].cube_info[i].offset = ib_chunk->kdata[idx]; | 1242 | track->textures[2].cube_info[i].offset = idx_value; |
1246 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); | 1243 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1247 | track->textures[2].cube_info[i].robj = reloc->robj; | 1244 | track->textures[2].cube_info[i].robj = reloc->robj; |
1248 | break; | 1245 | break; |
1249 | case RADEON_RE_WIDTH_HEIGHT: | 1246 | case RADEON_RE_WIDTH_HEIGHT: |
1250 | track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF); | 1247 | track->maxy = ((idx_value >> 16) & 0x7FF); |
1251 | break; | 1248 | break; |
1252 | case RADEON_RB3D_COLORPITCH: | 1249 | case RADEON_RB3D_COLORPITCH: |
1253 | r = r100_cs_packet_next_reloc(p, &reloc); | 1250 | r = r100_cs_packet_next_reloc(p, &reloc); |
@@ -1263,17 +1260,17 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1263 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | 1260 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
1264 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; | 1261 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; |
1265 | 1262 | ||
1266 | tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); | 1263 | tmp = idx_value & ~(0x7 << 16); |
1267 | tmp |= tile_flags; | 1264 | tmp |= tile_flags; |
1268 | ib[idx] = tmp; | 1265 | ib[idx] = tmp; |
1269 | 1266 | ||
1270 | track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK; | 1267 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
1271 | break; | 1268 | break; |
1272 | case RADEON_RB3D_DEPTHPITCH: | 1269 | case RADEON_RB3D_DEPTHPITCH: |
1273 | track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK; | 1270 | track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; |
1274 | break; | 1271 | break; |
1275 | case RADEON_RB3D_CNTL: | 1272 | case RADEON_RB3D_CNTL: |
1276 | switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { | 1273 | switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
1277 | case 7: | 1274 | case 7: |
1278 | case 8: | 1275 | case 8: |
1279 | case 9: | 1276 | case 9: |
@@ -1291,13 +1288,13 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1291 | break; | 1288 | break; |
1292 | default: | 1289 | default: |
1293 | DRM_ERROR("Invalid color buffer format (%d) !\n", | 1290 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
1294 | ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); | 1291 | ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); |
1295 | return -EINVAL; | 1292 | return -EINVAL; |
1296 | } | 1293 | } |
1297 | track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE); | 1294 | track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); |
1298 | break; | 1295 | break; |
1299 | case RADEON_RB3D_ZSTENCILCNTL: | 1296 | case RADEON_RB3D_ZSTENCILCNTL: |
1300 | switch (ib_chunk->kdata[idx] & 0xf) { | 1297 | switch (idx_value & 0xf) { |
1301 | case 0: | 1298 | case 0: |
1302 | track->zb.cpp = 2; | 1299 | track->zb.cpp = 2; |
1303 | break; | 1300 | break; |
@@ -1321,44 +1318,44 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1321 | r100_cs_dump_packet(p, pkt); | 1318 | r100_cs_dump_packet(p, pkt); |
1322 | return r; | 1319 | return r; |
1323 | } | 1320 | } |
1324 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); | 1321 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1325 | break; | 1322 | break; |
1326 | case RADEON_PP_CNTL: | 1323 | case RADEON_PP_CNTL: |
1327 | { | 1324 | { |
1328 | uint32_t temp = ib_chunk->kdata[idx] >> 4; | 1325 | uint32_t temp = idx_value >> 4; |
1329 | for (i = 0; i < track->num_texture; i++) | 1326 | for (i = 0; i < track->num_texture; i++) |
1330 | track->textures[i].enabled = !!(temp & (1 << i)); | 1327 | track->textures[i].enabled = !!(temp & (1 << i)); |
1331 | } | 1328 | } |
1332 | break; | 1329 | break; |
1333 | case RADEON_SE_VF_CNTL: | 1330 | case RADEON_SE_VF_CNTL: |
1334 | track->vap_vf_cntl = ib_chunk->kdata[idx]; | 1331 | track->vap_vf_cntl = idx_value; |
1335 | break; | 1332 | break; |
1336 | case RADEON_SE_VTX_FMT: | 1333 | case RADEON_SE_VTX_FMT: |
1337 | track->vtx_size = r100_get_vtx_size(ib_chunk->kdata[idx]); | 1334 | track->vtx_size = r100_get_vtx_size(idx_value); |
1338 | break; | 1335 | break; |
1339 | case RADEON_PP_TEX_SIZE_0: | 1336 | case RADEON_PP_TEX_SIZE_0: |
1340 | case RADEON_PP_TEX_SIZE_1: | 1337 | case RADEON_PP_TEX_SIZE_1: |
1341 | case RADEON_PP_TEX_SIZE_2: | 1338 | case RADEON_PP_TEX_SIZE_2: |
1342 | i = (reg - RADEON_PP_TEX_SIZE_0) / 8; | 1339 | i = (reg - RADEON_PP_TEX_SIZE_0) / 8; |
1343 | track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1; | 1340 | track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; |
1344 | track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; | 1341 | track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; |
1345 | break; | 1342 | break; |
1346 | case RADEON_PP_TEX_PITCH_0: | 1343 | case RADEON_PP_TEX_PITCH_0: |
1347 | case RADEON_PP_TEX_PITCH_1: | 1344 | case RADEON_PP_TEX_PITCH_1: |
1348 | case RADEON_PP_TEX_PITCH_2: | 1345 | case RADEON_PP_TEX_PITCH_2: |
1349 | i = (reg - RADEON_PP_TEX_PITCH_0) / 8; | 1346 | i = (reg - RADEON_PP_TEX_PITCH_0) / 8; |
1350 | track->textures[i].pitch = ib_chunk->kdata[idx] + 32; | 1347 | track->textures[i].pitch = idx_value + 32; |
1351 | break; | 1348 | break; |
1352 | case RADEON_PP_TXFILTER_0: | 1349 | case RADEON_PP_TXFILTER_0: |
1353 | case RADEON_PP_TXFILTER_1: | 1350 | case RADEON_PP_TXFILTER_1: |
1354 | case RADEON_PP_TXFILTER_2: | 1351 | case RADEON_PP_TXFILTER_2: |
1355 | i = (reg - RADEON_PP_TXFILTER_0) / 24; | 1352 | i = (reg - RADEON_PP_TXFILTER_0) / 24; |
1356 | track->textures[i].num_levels = ((ib_chunk->kdata[idx] & RADEON_MAX_MIP_LEVEL_MASK) | 1353 | track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) |
1357 | >> RADEON_MAX_MIP_LEVEL_SHIFT); | 1354 | >> RADEON_MAX_MIP_LEVEL_SHIFT); |
1358 | tmp = (ib_chunk->kdata[idx] >> 23) & 0x7; | 1355 | tmp = (idx_value >> 23) & 0x7; |
1359 | if (tmp == 2 || tmp == 6) | 1356 | if (tmp == 2 || tmp == 6) |
1360 | track->textures[i].roundup_w = false; | 1357 | track->textures[i].roundup_w = false; |
1361 | tmp = (ib_chunk->kdata[idx] >> 27) & 0x7; | 1358 | tmp = (idx_value >> 27) & 0x7; |
1362 | if (tmp == 2 || tmp == 6) | 1359 | if (tmp == 2 || tmp == 6) |
1363 | track->textures[i].roundup_h = false; | 1360 | track->textures[i].roundup_h = false; |
1364 | break; | 1361 | break; |
@@ -1366,16 +1363,16 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1366 | case RADEON_PP_TXFORMAT_1: | 1363 | case RADEON_PP_TXFORMAT_1: |
1367 | case RADEON_PP_TXFORMAT_2: | 1364 | case RADEON_PP_TXFORMAT_2: |
1368 | i = (reg - RADEON_PP_TXFORMAT_0) / 24; | 1365 | i = (reg - RADEON_PP_TXFORMAT_0) / 24; |
1369 | if (ib_chunk->kdata[idx] & RADEON_TXFORMAT_NON_POWER2) { | 1366 | if (idx_value & RADEON_TXFORMAT_NON_POWER2) { |
1370 | track->textures[i].use_pitch = 1; | 1367 | track->textures[i].use_pitch = 1; |
1371 | } else { | 1368 | } else { |
1372 | track->textures[i].use_pitch = 0; | 1369 | track->textures[i].use_pitch = 0; |
1373 | track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); | 1370 | track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
1374 | track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); | 1371 | track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); |
1375 | } | 1372 | } |
1376 | if (ib_chunk->kdata[idx] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) | 1373 | if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) |
1377 | track->textures[i].tex_coord_type = 2; | 1374 | track->textures[i].tex_coord_type = 2; |
1378 | switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) { | 1375 | switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { |
1379 | case RADEON_TXFORMAT_I8: | 1376 | case RADEON_TXFORMAT_I8: |
1380 | case RADEON_TXFORMAT_RGB332: | 1377 | case RADEON_TXFORMAT_RGB332: |
1381 | case RADEON_TXFORMAT_Y8: | 1378 | case RADEON_TXFORMAT_Y8: |
@@ -1402,13 +1399,13 @@ static int r100_packet0_check(struct radeon_cs_parser *p, | |||
1402 | track->textures[i].cpp = 4; | 1399 | track->textures[i].cpp = 4; |
1403 | break; | 1400 | break; |
1404 | } | 1401 | } |
1405 | track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf); | 1402 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
1406 | track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf); | 1403 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); |
1407 | break; | 1404 | break; |
1408 | case RADEON_PP_CUBIC_FACES_0: | 1405 | case RADEON_PP_CUBIC_FACES_0: |
1409 | case RADEON_PP_CUBIC_FACES_1: | 1406 | case RADEON_PP_CUBIC_FACES_1: |
1410 | case RADEON_PP_CUBIC_FACES_2: | 1407 | case RADEON_PP_CUBIC_FACES_2: |
1411 | tmp = ib_chunk->kdata[idx]; | 1408 | tmp = idx_value; |
1412 | i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; | 1409 | i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; |
1413 | for (face = 0; face < 4; face++) { | 1410 | for (face = 0; face < 4; face++) { |
1414 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); | 1411 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); |
@@ -1427,15 +1424,14 @@ int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, | |||
1427 | struct radeon_cs_packet *pkt, | 1424 | struct radeon_cs_packet *pkt, |
1428 | struct radeon_object *robj) | 1425 | struct radeon_object *robj) |
1429 | { | 1426 | { |
1430 | struct radeon_cs_chunk *ib_chunk; | ||
1431 | unsigned idx; | 1427 | unsigned idx; |
1432 | 1428 | u32 value; | |
1433 | ib_chunk = &p->chunks[p->chunk_ib_idx]; | ||
1434 | idx = pkt->idx + 1; | 1429 | idx = pkt->idx + 1; |
1435 | if ((ib_chunk->kdata[idx+2] + 1) > radeon_object_size(robj)) { | 1430 | value = radeon_get_ib_value(p, idx + 2); |
1431 | if ((value + 1) > radeon_object_size(robj)) { | ||
1436 | DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " | 1432 | DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " |
1437 | "(need %u have %lu) !\n", | 1433 | "(need %u have %lu) !\n", |
1438 | ib_chunk->kdata[idx+2] + 1, | 1434 | value + 1, |
1439 | radeon_object_size(robj)); | 1435 | radeon_object_size(robj)); |
1440 | return -EINVAL; | 1436 | return -EINVAL; |
1441 | } | 1437 | } |
@@ -1445,59 +1441,20 @@ int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, | |||
1445 | static int r100_packet3_check(struct radeon_cs_parser *p, | 1441 | static int r100_packet3_check(struct radeon_cs_parser *p, |
1446 | struct radeon_cs_packet *pkt) | 1442 | struct radeon_cs_packet *pkt) |
1447 | { | 1443 | { |
1448 | struct radeon_cs_chunk *ib_chunk; | ||
1449 | struct radeon_cs_reloc *reloc; | 1444 | struct radeon_cs_reloc *reloc; |
1450 | struct r100_cs_track *track; | 1445 | struct r100_cs_track *track; |
1451 | unsigned idx; | 1446 | unsigned idx; |
1452 | unsigned i, c; | ||
1453 | volatile uint32_t *ib; | 1447 | volatile uint32_t *ib; |
1454 | int r; | 1448 | int r; |
1455 | 1449 | ||
1456 | ib = p->ib->ptr; | 1450 | ib = p->ib->ptr; |
1457 | ib_chunk = &p->chunks[p->chunk_ib_idx]; | ||
1458 | idx = pkt->idx + 1; | 1451 | idx = pkt->idx + 1; |
1459 | track = (struct r100_cs_track *)p->track; | 1452 | track = (struct r100_cs_track *)p->track; |
1460 | switch (pkt->opcode) { | 1453 | switch (pkt->opcode) { |
1461 | case PACKET3_3D_LOAD_VBPNTR: | 1454 | case PACKET3_3D_LOAD_VBPNTR: |
1462 | c = ib_chunk->kdata[idx++]; | 1455 | r = r100_packet3_load_vbpntr(p, pkt, idx); |
1463 | track->num_arrays = c; | 1456 | if (r) |
1464 | for (i = 0; i < (c - 1); i += 2, idx += 3) { | 1457 | return r; |
1465 | r = r100_cs_packet_next_reloc(p, &reloc); | ||
1466 | if (r) { | ||
1467 | DRM_ERROR("No reloc for packet3 %d\n", | ||
1468 | pkt->opcode); | ||
1469 | r100_cs_dump_packet(p, pkt); | ||
1470 | return r; | ||
1471 | } | ||
1472 | ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); | ||
1473 | track->arrays[i + 0].robj = reloc->robj; | ||
1474 | track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; | ||
1475 | track->arrays[i + 0].esize &= 0x7F; | ||
1476 | r = r100_cs_packet_next_reloc(p, &reloc); | ||
1477 | if (r) { | ||
1478 | DRM_ERROR("No reloc for packet3 %d\n", | ||
1479 | pkt->opcode); | ||
1480 | r100_cs_dump_packet(p, pkt); | ||
1481 | return r; | ||
1482 | } | ||
1483 | ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset); | ||
1484 | track->arrays[i + 1].robj = reloc->robj; | ||
1485 | track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24; | ||
1486 | track->arrays[i + 1].esize &= 0x7F; | ||
1487 | } | ||
1488 | if (c & 1) { | ||
1489 | r = r100_cs_packet_next_reloc(p, &reloc); | ||
1490 | if (r) { | ||
1491 | DRM_ERROR("No reloc for packet3 %d\n", | ||
1492 | pkt->opcode); | ||
1493 | r100_cs_dump_packet(p, pkt); | ||
1494 | return r; | ||
1495 | } | ||
1496 | ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); | ||
1497 | track->arrays[i + 0].robj = reloc->robj; | ||
1498 | track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; | ||
1499 | track->arrays[i + 0].esize &= 0x7F; | ||
1500 | } | ||
1501 | break; | 1458 | break; |
1502 | case PACKET3_INDX_BUFFER: | 1459 | case PACKET3_INDX_BUFFER: |
1503 | r = r100_cs_packet_next_reloc(p, &reloc); | 1460 | r = r100_cs_packet_next_reloc(p, &reloc); |
@@ -1506,7 +1463,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p, | |||
1506 | r100_cs_dump_packet(p, pkt); | 1463 | r100_cs_dump_packet(p, pkt); |
1507 | return r; | 1464 | return r; |
1508 | } | 1465 | } |
1509 | ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); | 1466 | ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); |
1510 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); | 1467 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
1511 | if (r) { | 1468 | if (r) { |
1512 | return r; | 1469 | return r; |
@@ -1520,27 +1477,27 @@ static int r100_packet3_check(struct radeon_cs_parser *p, | |||
1520 | r100_cs_dump_packet(p, pkt); | 1477 | r100_cs_dump_packet(p, pkt); |
1521 | return r; | 1478 | return r; |
1522 | } | 1479 | } |
1523 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); | 1480 | ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); |
1524 | track->num_arrays = 1; | 1481 | track->num_arrays = 1; |
1525 | track->vtx_size = r100_get_vtx_size(ib_chunk->kdata[idx+2]); | 1482 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); |
1526 | 1483 | ||
1527 | track->arrays[0].robj = reloc->robj; | 1484 | track->arrays[0].robj = reloc->robj; |
1528 | track->arrays[0].esize = track->vtx_size; | 1485 | track->arrays[0].esize = track->vtx_size; |
1529 | 1486 | ||
1530 | track->max_indx = ib_chunk->kdata[idx+1]; | 1487 | track->max_indx = radeon_get_ib_value(p, idx+1); |
1531 | 1488 | ||
1532 | track->vap_vf_cntl = ib_chunk->kdata[idx+3]; | 1489 | track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); |
1533 | track->immd_dwords = pkt->count - 1; | 1490 | track->immd_dwords = pkt->count - 1; |
1534 | r = r100_cs_track_check(p->rdev, track); | 1491 | r = r100_cs_track_check(p->rdev, track); |
1535 | if (r) | 1492 | if (r) |
1536 | return r; | 1493 | return r; |
1537 | break; | 1494 | break; |
1538 | case PACKET3_3D_DRAW_IMMD: | 1495 | case PACKET3_3D_DRAW_IMMD: |
1539 | if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) { | 1496 | if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
1540 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); | 1497 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1541 | return -EINVAL; | 1498 | return -EINVAL; |
1542 | } | 1499 | } |
1543 | track->vap_vf_cntl = ib_chunk->kdata[idx+1]; | 1500 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1544 | track->immd_dwords = pkt->count - 1; | 1501 | track->immd_dwords = pkt->count - 1; |
1545 | r = r100_cs_track_check(p->rdev, track); | 1502 | r = r100_cs_track_check(p->rdev, track); |
1546 | if (r) | 1503 | if (r) |
@@ -1548,11 +1505,11 @@ static int r100_packet3_check(struct radeon_cs_parser *p, | |||
1548 | break; | 1505 | break; |
1549 | /* triggers drawing using in-packet vertex data */ | 1506 | /* triggers drawing using in-packet vertex data */ |
1550 | case PACKET3_3D_DRAW_IMMD_2: | 1507 | case PACKET3_3D_DRAW_IMMD_2: |
1551 | if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) { | 1508 | if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { |
1552 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); | 1509 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1553 | return -EINVAL; | 1510 | return -EINVAL; |
1554 | } | 1511 | } |
1555 | track->vap_vf_cntl = ib_chunk->kdata[idx]; | 1512 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1556 | track->immd_dwords = pkt->count; | 1513 | track->immd_dwords = pkt->count; |
1557 | r = r100_cs_track_check(p->rdev, track); | 1514 | r = r100_cs_track_check(p->rdev, track); |
1558 | if (r) | 1515 | if (r) |
@@ -1560,28 +1517,28 @@ static int r100_packet3_check(struct radeon_cs_parser *p, | |||
1560 | break; | 1517 | break; |
1561 | /* triggers drawing using in-packet vertex data */ | 1518 | /* triggers drawing using in-packet vertex data */ |
1562 | case PACKET3_3D_DRAW_VBUF_2: | 1519 | case PACKET3_3D_DRAW_VBUF_2: |
1563 | track->vap_vf_cntl = ib_chunk->kdata[idx]; | 1520 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1564 | r = r100_cs_track_check(p->rdev, track); | 1521 | r = r100_cs_track_check(p->rdev, track); |
1565 | if (r) | 1522 | if (r) |
1566 | return r; | 1523 | return r; |
1567 | break; | 1524 | break; |
1568 | /* triggers drawing of vertex buffers setup elsewhere */ | 1525 | /* triggers drawing of vertex buffers setup elsewhere */ |
1569 | case PACKET3_3D_DRAW_INDX_2: | 1526 | case PACKET3_3D_DRAW_INDX_2: |
1570 | track->vap_vf_cntl = ib_chunk->kdata[idx]; | 1527 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1571 | r = r100_cs_track_check(p->rdev, track); | 1528 | r = r100_cs_track_check(p->rdev, track); |
1572 | if (r) | 1529 | if (r) |
1573 | return r; | 1530 | return r; |
1574 | break; | 1531 | break; |
1575 | /* triggers drawing using indices to vertex buffer */ | 1532 | /* triggers drawing using indices to vertex buffer */ |
1576 | case PACKET3_3D_DRAW_VBUF: | 1533 | case PACKET3_3D_DRAW_VBUF: |
1577 | track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; | 1534 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1578 | r = r100_cs_track_check(p->rdev, track); | 1535 | r = r100_cs_track_check(p->rdev, track); |
1579 | if (r) | 1536 | if (r) |
1580 | return r; | 1537 | return r; |
1581 | break; | 1538 | break; |
1582 | /* triggers drawing of vertex buffers setup elsewhere */ | 1539 | /* triggers drawing of vertex buffers setup elsewhere */ |
1583 | case PACKET3_3D_DRAW_INDX: | 1540 | case PACKET3_3D_DRAW_INDX: |
1584 | track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; | 1541 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1585 | r = r100_cs_track_check(p->rdev, track); | 1542 | r = r100_cs_track_check(p->rdev, track); |
1586 | if (r) | 1543 | if (r) |
1587 | return r; | 1544 | return r; |
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h index 70a82eda394a..0daf0d76a891 100644 --- a/drivers/gpu/drm/radeon/r100_track.h +++ b/drivers/gpu/drm/radeon/r100_track.h | |||
@@ -84,6 +84,8 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
84 | struct radeon_cs_packet *pkt, | 84 | struct radeon_cs_packet *pkt, |
85 | unsigned idx, unsigned reg); | 85 | unsigned idx, unsigned reg); |
86 | 86 | ||
87 | |||
88 | |||
87 | static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p, | 89 | static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p, |
88 | struct radeon_cs_packet *pkt, | 90 | struct radeon_cs_packet *pkt, |
89 | unsigned idx, | 91 | unsigned idx, |
@@ -93,9 +95,7 @@ static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p, | |||
93 | u32 tile_flags = 0; | 95 | u32 tile_flags = 0; |
94 | u32 tmp; | 96 | u32 tmp; |
95 | struct radeon_cs_reloc *reloc; | 97 | struct radeon_cs_reloc *reloc; |
96 | struct radeon_cs_chunk *ib_chunk; | 98 | u32 value; |
97 | |||
98 | ib_chunk = &p->chunks[p->chunk_ib_idx]; | ||
99 | 99 | ||
100 | r = r100_cs_packet_next_reloc(p, &reloc); | 100 | r = r100_cs_packet_next_reloc(p, &reloc); |
101 | if (r) { | 101 | if (r) { |
@@ -104,7 +104,8 @@ static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p, | |||
104 | r100_cs_dump_packet(p, pkt); | 104 | r100_cs_dump_packet(p, pkt); |
105 | return r; | 105 | return r; |
106 | } | 106 | } |
107 | tmp = ib_chunk->kdata[idx] & 0x003fffff; | 107 | value = radeon_get_ib_value(p, idx); |
108 | tmp = value & 0x003fffff; | ||
108 | tmp += (((u32)reloc->lobj.gpu_offset) >> 10); | 109 | tmp += (((u32)reloc->lobj.gpu_offset) >> 10); |
109 | 110 | ||
110 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) | 111 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
@@ -119,6 +120,64 @@ static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p, | |||
119 | } | 120 | } |
120 | 121 | ||
121 | tmp |= tile_flags; | 122 | tmp |= tile_flags; |
122 | p->ib->ptr[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp; | 123 | p->ib->ptr[idx] = (value & 0x3fc00000) | tmp; |
123 | return 0; | 124 | return 0; |
124 | } | 125 | } |
126 | |||
127 | static inline int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, | ||
128 | struct radeon_cs_packet *pkt, | ||
129 | int idx) | ||
130 | { | ||
131 | unsigned c, i; | ||
132 | struct radeon_cs_reloc *reloc; | ||
133 | struct r100_cs_track *track; | ||
134 | int r = 0; | ||
135 | volatile uint32_t *ib; | ||
136 | u32 idx_value; | ||
137 | |||
138 | ib = p->ib->ptr; | ||
139 | track = (struct r100_cs_track *)p->track; | ||
140 | c = radeon_get_ib_value(p, idx++) & 0x1F; | ||
141 | track->num_arrays = c; | ||
142 | for (i = 0; i < (c - 1); i+=2, idx+=3) { | ||
143 | r = r100_cs_packet_next_reloc(p, &reloc); | ||
144 | if (r) { | ||
145 | DRM_ERROR("No reloc for packet3 %d\n", | ||
146 | pkt->opcode); | ||
147 | r100_cs_dump_packet(p, pkt); | ||
148 | return r; | ||
149 | } | ||
150 | idx_value = radeon_get_ib_value(p, idx); | ||
151 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); | ||
152 | |||
153 | track->arrays[i + 0].esize = idx_value >> 8; | ||
154 | track->arrays[i + 0].robj = reloc->robj; | ||
155 | track->arrays[i + 0].esize &= 0x7F; | ||
156 | r = r100_cs_packet_next_reloc(p, &reloc); | ||
157 | if (r) { | ||
158 | DRM_ERROR("No reloc for packet3 %d\n", | ||
159 | pkt->opcode); | ||
160 | r100_cs_dump_packet(p, pkt); | ||
161 | return r; | ||
162 | } | ||
163 | ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); | ||
164 | track->arrays[i + 1].robj = reloc->robj; | ||
165 | track->arrays[i + 1].esize = idx_value >> 24; | ||
166 | track->arrays[i + 1].esize &= 0x7F; | ||
167 | } | ||
168 | if (c & 1) { | ||
169 | r = r100_cs_packet_next_reloc(p, &reloc); | ||
170 | if (r) { | ||
171 | DRM_ERROR("No reloc for packet3 %d\n", | ||
172 | pkt->opcode); | ||
173 | r100_cs_dump_packet(p, pkt); | ||
174 | return r; | ||
175 | } | ||
176 | idx_value = radeon_get_ib_value(p, idx); | ||
177 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); | ||
178 | track->arrays[i + 0].robj = reloc->robj; | ||
179 | track->arrays[i + 0].esize = idx_value >> 8; | ||
180 | track->arrays[i + 0].esize &= 0x7F; | ||
181 | } | ||
182 | return r; | ||
183 | } | ||
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c index 568c74bfba3d..cf7fea5ff2e5 100644 --- a/drivers/gpu/drm/radeon/r200.c +++ b/drivers/gpu/drm/radeon/r200.c | |||
@@ -96,7 +96,6 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
96 | struct radeon_cs_packet *pkt, | 96 | struct radeon_cs_packet *pkt, |
97 | unsigned idx, unsigned reg) | 97 | unsigned idx, unsigned reg) |
98 | { | 98 | { |
99 | struct radeon_cs_chunk *ib_chunk; | ||
100 | struct radeon_cs_reloc *reloc; | 99 | struct radeon_cs_reloc *reloc; |
101 | struct r100_cs_track *track; | 100 | struct r100_cs_track *track; |
102 | volatile uint32_t *ib; | 101 | volatile uint32_t *ib; |
@@ -105,11 +104,11 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
105 | int i; | 104 | int i; |
106 | int face; | 105 | int face; |
107 | u32 tile_flags = 0; | 106 | u32 tile_flags = 0; |
107 | u32 idx_value; | ||
108 | 108 | ||
109 | ib = p->ib->ptr; | 109 | ib = p->ib->ptr; |
110 | ib_chunk = &p->chunks[p->chunk_ib_idx]; | ||
111 | track = (struct r100_cs_track *)p->track; | 110 | track = (struct r100_cs_track *)p->track; |
112 | 111 | idx_value = radeon_get_ib_value(p, idx); | |
113 | switch (reg) { | 112 | switch (reg) { |
114 | case RADEON_CRTC_GUI_TRIG_VLINE: | 113 | case RADEON_CRTC_GUI_TRIG_VLINE: |
115 | r = r100_cs_packet_parse_vline(p); | 114 | r = r100_cs_packet_parse_vline(p); |
@@ -137,8 +136,8 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
137 | return r; | 136 | return r; |
138 | } | 137 | } |
139 | track->zb.robj = reloc->robj; | 138 | track->zb.robj = reloc->robj; |
140 | track->zb.offset = ib_chunk->kdata[idx]; | 139 | track->zb.offset = idx_value; |
141 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); | 140 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
142 | break; | 141 | break; |
143 | case RADEON_RB3D_COLOROFFSET: | 142 | case RADEON_RB3D_COLOROFFSET: |
144 | r = r100_cs_packet_next_reloc(p, &reloc); | 143 | r = r100_cs_packet_next_reloc(p, &reloc); |
@@ -149,8 +148,8 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
149 | return r; | 148 | return r; |
150 | } | 149 | } |
151 | track->cb[0].robj = reloc->robj; | 150 | track->cb[0].robj = reloc->robj; |
152 | track->cb[0].offset = ib_chunk->kdata[idx]; | 151 | track->cb[0].offset = idx_value; |
153 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); | 152 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
154 | break; | 153 | break; |
155 | case R200_PP_TXOFFSET_0: | 154 | case R200_PP_TXOFFSET_0: |
156 | case R200_PP_TXOFFSET_1: | 155 | case R200_PP_TXOFFSET_1: |
@@ -166,7 +165,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
166 | r100_cs_dump_packet(p, pkt); | 165 | r100_cs_dump_packet(p, pkt); |
167 | return r; | 166 | return r; |
168 | } | 167 | } |
169 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); | 168 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
170 | track->textures[i].robj = reloc->robj; | 169 | track->textures[i].robj = reloc->robj; |
171 | break; | 170 | break; |
172 | case R200_PP_CUBIC_OFFSET_F1_0: | 171 | case R200_PP_CUBIC_OFFSET_F1_0: |
@@ -208,12 +207,12 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
208 | r100_cs_dump_packet(p, pkt); | 207 | r100_cs_dump_packet(p, pkt); |
209 | return r; | 208 | return r; |
210 | } | 209 | } |
211 | track->textures[i].cube_info[face - 1].offset = ib_chunk->kdata[idx]; | 210 | track->textures[i].cube_info[face - 1].offset = idx_value; |
212 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); | 211 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
213 | track->textures[i].cube_info[face - 1].robj = reloc->robj; | 212 | track->textures[i].cube_info[face - 1].robj = reloc->robj; |
214 | break; | 213 | break; |
215 | case RADEON_RE_WIDTH_HEIGHT: | 214 | case RADEON_RE_WIDTH_HEIGHT: |
216 | track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF); | 215 | track->maxy = ((idx_value >> 16) & 0x7FF); |
217 | break; | 216 | break; |
218 | case RADEON_RB3D_COLORPITCH: | 217 | case RADEON_RB3D_COLORPITCH: |
219 | r = r100_cs_packet_next_reloc(p, &reloc); | 218 | r = r100_cs_packet_next_reloc(p, &reloc); |
@@ -229,17 +228,17 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
229 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | 228 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
230 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; | 229 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; |
231 | 230 | ||
232 | tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); | 231 | tmp = idx_value & ~(0x7 << 16); |
233 | tmp |= tile_flags; | 232 | tmp |= tile_flags; |
234 | ib[idx] = tmp; | 233 | ib[idx] = tmp; |
235 | 234 | ||
236 | track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK; | 235 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
237 | break; | 236 | break; |
238 | case RADEON_RB3D_DEPTHPITCH: | 237 | case RADEON_RB3D_DEPTHPITCH: |
239 | track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK; | 238 | track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; |
240 | break; | 239 | break; |
241 | case RADEON_RB3D_CNTL: | 240 | case RADEON_RB3D_CNTL: |
242 | switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { | 241 | switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
243 | case 7: | 242 | case 7: |
244 | case 8: | 243 | case 8: |
245 | case 9: | 244 | case 9: |
@@ -257,18 +256,18 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
257 | break; | 256 | break; |
258 | default: | 257 | default: |
259 | DRM_ERROR("Invalid color buffer format (%d) !\n", | 258 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
260 | ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); | 259 | ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); |
261 | return -EINVAL; | 260 | return -EINVAL; |
262 | } | 261 | } |
263 | if (ib_chunk->kdata[idx] & RADEON_DEPTHXY_OFFSET_ENABLE) { | 262 | if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) { |
264 | DRM_ERROR("No support for depth xy offset in kms\n"); | 263 | DRM_ERROR("No support for depth xy offset in kms\n"); |
265 | return -EINVAL; | 264 | return -EINVAL; |
266 | } | 265 | } |
267 | 266 | ||
268 | track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE); | 267 | track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); |
269 | break; | 268 | break; |
270 | case RADEON_RB3D_ZSTENCILCNTL: | 269 | case RADEON_RB3D_ZSTENCILCNTL: |
271 | switch (ib_chunk->kdata[idx] & 0xf) { | 270 | switch (idx_value & 0xf) { |
272 | case 0: | 271 | case 0: |
273 | track->zb.cpp = 2; | 272 | track->zb.cpp = 2; |
274 | break; | 273 | break; |
@@ -292,27 +291,27 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
292 | r100_cs_dump_packet(p, pkt); | 291 | r100_cs_dump_packet(p, pkt); |
293 | return r; | 292 | return r; |
294 | } | 293 | } |
295 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); | 294 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
296 | break; | 295 | break; |
297 | case RADEON_PP_CNTL: | 296 | case RADEON_PP_CNTL: |
298 | { | 297 | { |
299 | uint32_t temp = ib_chunk->kdata[idx] >> 4; | 298 | uint32_t temp = idx_value >> 4; |
300 | for (i = 0; i < track->num_texture; i++) | 299 | for (i = 0; i < track->num_texture; i++) |
301 | track->textures[i].enabled = !!(temp & (1 << i)); | 300 | track->textures[i].enabled = !!(temp & (1 << i)); |
302 | } | 301 | } |
303 | break; | 302 | break; |
304 | case RADEON_SE_VF_CNTL: | 303 | case RADEON_SE_VF_CNTL: |
305 | track->vap_vf_cntl = ib_chunk->kdata[idx]; | 304 | track->vap_vf_cntl = idx_value; |
306 | break; | 305 | break; |
307 | case 0x210c: | 306 | case 0x210c: |
308 | /* VAP_VF_MAX_VTX_INDX */ | 307 | /* VAP_VF_MAX_VTX_INDX */ |
309 | track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL; | 308 | track->max_indx = idx_value & 0x00FFFFFFUL; |
310 | break; | 309 | break; |
311 | case R200_SE_VTX_FMT_0: | 310 | case R200_SE_VTX_FMT_0: |
312 | track->vtx_size = r200_get_vtx_size_0(ib_chunk->kdata[idx]); | 311 | track->vtx_size = r200_get_vtx_size_0(idx_value); |
313 | break; | 312 | break; |
314 | case R200_SE_VTX_FMT_1: | 313 | case R200_SE_VTX_FMT_1: |
315 | track->vtx_size += r200_get_vtx_size_1(ib_chunk->kdata[idx]); | 314 | track->vtx_size += r200_get_vtx_size_1(idx_value); |
316 | break; | 315 | break; |
317 | case R200_PP_TXSIZE_0: | 316 | case R200_PP_TXSIZE_0: |
318 | case R200_PP_TXSIZE_1: | 317 | case R200_PP_TXSIZE_1: |
@@ -321,8 +320,8 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
321 | case R200_PP_TXSIZE_4: | 320 | case R200_PP_TXSIZE_4: |
322 | case R200_PP_TXSIZE_5: | 321 | case R200_PP_TXSIZE_5: |
323 | i = (reg - R200_PP_TXSIZE_0) / 32; | 322 | i = (reg - R200_PP_TXSIZE_0) / 32; |
324 | track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1; | 323 | track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; |
325 | track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; | 324 | track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; |
326 | break; | 325 | break; |
327 | case R200_PP_TXPITCH_0: | 326 | case R200_PP_TXPITCH_0: |
328 | case R200_PP_TXPITCH_1: | 327 | case R200_PP_TXPITCH_1: |
@@ -331,7 +330,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
331 | case R200_PP_TXPITCH_4: | 330 | case R200_PP_TXPITCH_4: |
332 | case R200_PP_TXPITCH_5: | 331 | case R200_PP_TXPITCH_5: |
333 | i = (reg - R200_PP_TXPITCH_0) / 32; | 332 | i = (reg - R200_PP_TXPITCH_0) / 32; |
334 | track->textures[i].pitch = ib_chunk->kdata[idx] + 32; | 333 | track->textures[i].pitch = idx_value + 32; |
335 | break; | 334 | break; |
336 | case R200_PP_TXFILTER_0: | 335 | case R200_PP_TXFILTER_0: |
337 | case R200_PP_TXFILTER_1: | 336 | case R200_PP_TXFILTER_1: |
@@ -340,12 +339,12 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
340 | case R200_PP_TXFILTER_4: | 339 | case R200_PP_TXFILTER_4: |
341 | case R200_PP_TXFILTER_5: | 340 | case R200_PP_TXFILTER_5: |
342 | i = (reg - R200_PP_TXFILTER_0) / 32; | 341 | i = (reg - R200_PP_TXFILTER_0) / 32; |
343 | track->textures[i].num_levels = ((ib_chunk->kdata[idx] & R200_MAX_MIP_LEVEL_MASK) | 342 | track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK) |
344 | >> R200_MAX_MIP_LEVEL_SHIFT); | 343 | >> R200_MAX_MIP_LEVEL_SHIFT); |
345 | tmp = (ib_chunk->kdata[idx] >> 23) & 0x7; | 344 | tmp = (idx_value >> 23) & 0x7; |
346 | if (tmp == 2 || tmp == 6) | 345 | if (tmp == 2 || tmp == 6) |
347 | track->textures[i].roundup_w = false; | 346 | track->textures[i].roundup_w = false; |
348 | tmp = (ib_chunk->kdata[idx] >> 27) & 0x7; | 347 | tmp = (idx_value >> 27) & 0x7; |
349 | if (tmp == 2 || tmp == 6) | 348 | if (tmp == 2 || tmp == 6) |
350 | track->textures[i].roundup_h = false; | 349 | track->textures[i].roundup_h = false; |
351 | break; | 350 | break; |
@@ -364,8 +363,8 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
364 | case R200_PP_TXFORMAT_X_4: | 363 | case R200_PP_TXFORMAT_X_4: |
365 | case R200_PP_TXFORMAT_X_5: | 364 | case R200_PP_TXFORMAT_X_5: |
366 | i = (reg - R200_PP_TXFORMAT_X_0) / 32; | 365 | i = (reg - R200_PP_TXFORMAT_X_0) / 32; |
367 | track->textures[i].txdepth = ib_chunk->kdata[idx] & 0x7; | 366 | track->textures[i].txdepth = idx_value & 0x7; |
368 | tmp = (ib_chunk->kdata[idx] >> 16) & 0x3; | 367 | tmp = (idx_value >> 16) & 0x3; |
369 | /* 2D, 3D, CUBE */ | 368 | /* 2D, 3D, CUBE */ |
370 | switch (tmp) { | 369 | switch (tmp) { |
371 | case 0: | 370 | case 0: |
@@ -389,14 +388,14 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
389 | case R200_PP_TXFORMAT_4: | 388 | case R200_PP_TXFORMAT_4: |
390 | case R200_PP_TXFORMAT_5: | 389 | case R200_PP_TXFORMAT_5: |
391 | i = (reg - R200_PP_TXFORMAT_0) / 32; | 390 | i = (reg - R200_PP_TXFORMAT_0) / 32; |
392 | if (ib_chunk->kdata[idx] & R200_TXFORMAT_NON_POWER2) { | 391 | if (idx_value & R200_TXFORMAT_NON_POWER2) { |
393 | track->textures[i].use_pitch = 1; | 392 | track->textures[i].use_pitch = 1; |
394 | } else { | 393 | } else { |
395 | track->textures[i].use_pitch = 0; | 394 | track->textures[i].use_pitch = 0; |
396 | track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); | 395 | track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
397 | track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); | 396 | track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); |
398 | } | 397 | } |
399 | switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) { | 398 | switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { |
400 | case R200_TXFORMAT_I8: | 399 | case R200_TXFORMAT_I8: |
401 | case R200_TXFORMAT_RGB332: | 400 | case R200_TXFORMAT_RGB332: |
402 | case R200_TXFORMAT_Y8: | 401 | case R200_TXFORMAT_Y8: |
@@ -424,8 +423,8 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
424 | track->textures[i].cpp = 4; | 423 | track->textures[i].cpp = 4; |
425 | break; | 424 | break; |
426 | } | 425 | } |
427 | track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf); | 426 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
428 | track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf); | 427 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); |
429 | break; | 428 | break; |
430 | case R200_PP_CUBIC_FACES_0: | 429 | case R200_PP_CUBIC_FACES_0: |
431 | case R200_PP_CUBIC_FACES_1: | 430 | case R200_PP_CUBIC_FACES_1: |
@@ -433,7 +432,7 @@ int r200_packet0_check(struct radeon_cs_parser *p, | |||
433 | case R200_PP_CUBIC_FACES_3: | 432 | case R200_PP_CUBIC_FACES_3: |
434 | case R200_PP_CUBIC_FACES_4: | 433 | case R200_PP_CUBIC_FACES_4: |
435 | case R200_PP_CUBIC_FACES_5: | 434 | case R200_PP_CUBIC_FACES_5: |
436 | tmp = ib_chunk->kdata[idx]; | 435 | tmp = idx_value; |
437 | i = (reg - R200_PP_CUBIC_FACES_0) / 32; | 436 | i = (reg - R200_PP_CUBIC_FACES_0) / 32; |
438 | for (face = 0; face < 4; face++) { | 437 | for (face = 0; face < 4; face++) { |
439 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); | 438 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); |
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index bb151ecdf8fc..1ebea8cc8c93 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c | |||
@@ -697,17 +697,18 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
697 | struct radeon_cs_packet *pkt, | 697 | struct radeon_cs_packet *pkt, |
698 | unsigned idx, unsigned reg) | 698 | unsigned idx, unsigned reg) |
699 | { | 699 | { |
700 | struct radeon_cs_chunk *ib_chunk; | ||
701 | struct radeon_cs_reloc *reloc; | 700 | struct radeon_cs_reloc *reloc; |
702 | struct r100_cs_track *track; | 701 | struct r100_cs_track *track; |
703 | volatile uint32_t *ib; | 702 | volatile uint32_t *ib; |
704 | uint32_t tmp, tile_flags = 0; | 703 | uint32_t tmp, tile_flags = 0; |
705 | unsigned i; | 704 | unsigned i; |
706 | int r; | 705 | int r; |
706 | u32 idx_value; | ||
707 | 707 | ||
708 | ib = p->ib->ptr; | 708 | ib = p->ib->ptr; |
709 | ib_chunk = &p->chunks[p->chunk_ib_idx]; | ||
710 | track = (struct r100_cs_track *)p->track; | 709 | track = (struct r100_cs_track *)p->track; |
710 | idx_value = radeon_get_ib_value(p, idx); | ||
711 | |||
711 | switch(reg) { | 712 | switch(reg) { |
712 | case AVIVO_D1MODE_VLINE_START_END: | 713 | case AVIVO_D1MODE_VLINE_START_END: |
713 | case RADEON_CRTC_GUI_TRIG_VLINE: | 714 | case RADEON_CRTC_GUI_TRIG_VLINE: |
@@ -738,8 +739,8 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
738 | return r; | 739 | return r; |
739 | } | 740 | } |
740 | track->cb[i].robj = reloc->robj; | 741 | track->cb[i].robj = reloc->robj; |
741 | track->cb[i].offset = ib_chunk->kdata[idx]; | 742 | track->cb[i].offset = idx_value; |
742 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); | 743 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
743 | break; | 744 | break; |
744 | case R300_ZB_DEPTHOFFSET: | 745 | case R300_ZB_DEPTHOFFSET: |
745 | r = r100_cs_packet_next_reloc(p, &reloc); | 746 | r = r100_cs_packet_next_reloc(p, &reloc); |
@@ -750,8 +751,8 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
750 | return r; | 751 | return r; |
751 | } | 752 | } |
752 | track->zb.robj = reloc->robj; | 753 | track->zb.robj = reloc->robj; |
753 | track->zb.offset = ib_chunk->kdata[idx]; | 754 | track->zb.offset = idx_value; |
754 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); | 755 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
755 | break; | 756 | break; |
756 | case R300_TX_OFFSET_0: | 757 | case R300_TX_OFFSET_0: |
757 | case R300_TX_OFFSET_0+4: | 758 | case R300_TX_OFFSET_0+4: |
@@ -777,32 +778,32 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
777 | r100_cs_dump_packet(p, pkt); | 778 | r100_cs_dump_packet(p, pkt); |
778 | return r; | 779 | return r; |
779 | } | 780 | } |
780 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); | 781 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
781 | track->textures[i].robj = reloc->robj; | 782 | track->textures[i].robj = reloc->robj; |
782 | break; | 783 | break; |
783 | /* Tracked registers */ | 784 | /* Tracked registers */ |
784 | case 0x2084: | 785 | case 0x2084: |
785 | /* VAP_VF_CNTL */ | 786 | /* VAP_VF_CNTL */ |
786 | track->vap_vf_cntl = ib_chunk->kdata[idx]; | 787 | track->vap_vf_cntl = idx_value; |
787 | break; | 788 | break; |
788 | case 0x20B4: | 789 | case 0x20B4: |
789 | /* VAP_VTX_SIZE */ | 790 | /* VAP_VTX_SIZE */ |
790 | track->vtx_size = ib_chunk->kdata[idx] & 0x7F; | 791 | track->vtx_size = idx_value & 0x7F; |
791 | break; | 792 | break; |
792 | case 0x2134: | 793 | case 0x2134: |
793 | /* VAP_VF_MAX_VTX_INDX */ | 794 | /* VAP_VF_MAX_VTX_INDX */ |
794 | track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL; | 795 | track->max_indx = idx_value & 0x00FFFFFFUL; |
795 | break; | 796 | break; |
796 | case 0x43E4: | 797 | case 0x43E4: |
797 | /* SC_SCISSOR1 */ | 798 | /* SC_SCISSOR1 */ |
798 | track->maxy = ((ib_chunk->kdata[idx] >> 13) & 0x1FFF) + 1; | 799 | track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; |
799 | if (p->rdev->family < CHIP_RV515) { | 800 | if (p->rdev->family < CHIP_RV515) { |
800 | track->maxy -= 1440; | 801 | track->maxy -= 1440; |
801 | } | 802 | } |
802 | break; | 803 | break; |
803 | case 0x4E00: | 804 | case 0x4E00: |
804 | /* RB3D_CCTL */ | 805 | /* RB3D_CCTL */ |
805 | track->num_cb = ((ib_chunk->kdata[idx] >> 5) & 0x3) + 1; | 806 | track->num_cb = ((idx_value >> 5) & 0x3) + 1; |
806 | break; | 807 | break; |
807 | case 0x4E38: | 808 | case 0x4E38: |
808 | case 0x4E3C: | 809 | case 0x4E3C: |
@@ -825,13 +826,13 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
825 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | 826 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
826 | tile_flags |= R300_COLOR_MICROTILE_ENABLE; | 827 | tile_flags |= R300_COLOR_MICROTILE_ENABLE; |
827 | 828 | ||
828 | tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); | 829 | tmp = idx_value & ~(0x7 << 16); |
829 | tmp |= tile_flags; | 830 | tmp |= tile_flags; |
830 | ib[idx] = tmp; | 831 | ib[idx] = tmp; |
831 | 832 | ||
832 | i = (reg - 0x4E38) >> 2; | 833 | i = (reg - 0x4E38) >> 2; |
833 | track->cb[i].pitch = ib_chunk->kdata[idx] & 0x3FFE; | 834 | track->cb[i].pitch = idx_value & 0x3FFE; |
834 | switch (((ib_chunk->kdata[idx] >> 21) & 0xF)) { | 835 | switch (((idx_value >> 21) & 0xF)) { |
835 | case 9: | 836 | case 9: |
836 | case 11: | 837 | case 11: |
837 | case 12: | 838 | case 12: |
@@ -854,13 +855,13 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
854 | break; | 855 | break; |
855 | default: | 856 | default: |
856 | DRM_ERROR("Invalid color buffer format (%d) !\n", | 857 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
857 | ((ib_chunk->kdata[idx] >> 21) & 0xF)); | 858 | ((idx_value >> 21) & 0xF)); |
858 | return -EINVAL; | 859 | return -EINVAL; |
859 | } | 860 | } |
860 | break; | 861 | break; |
861 | case 0x4F00: | 862 | case 0x4F00: |
862 | /* ZB_CNTL */ | 863 | /* ZB_CNTL */ |
863 | if (ib_chunk->kdata[idx] & 2) { | 864 | if (idx_value & 2) { |
864 | track->z_enabled = true; | 865 | track->z_enabled = true; |
865 | } else { | 866 | } else { |
866 | track->z_enabled = false; | 867 | track->z_enabled = false; |
@@ -868,7 +869,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
868 | break; | 869 | break; |
869 | case 0x4F10: | 870 | case 0x4F10: |
870 | /* ZB_FORMAT */ | 871 | /* ZB_FORMAT */ |
871 | switch ((ib_chunk->kdata[idx] & 0xF)) { | 872 | switch ((idx_value & 0xF)) { |
872 | case 0: | 873 | case 0: |
873 | case 1: | 874 | case 1: |
874 | track->zb.cpp = 2; | 875 | track->zb.cpp = 2; |
@@ -878,7 +879,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
878 | break; | 879 | break; |
879 | default: | 880 | default: |
880 | DRM_ERROR("Invalid z buffer format (%d) !\n", | 881 | DRM_ERROR("Invalid z buffer format (%d) !\n", |
881 | (ib_chunk->kdata[idx] & 0xF)); | 882 | (idx_value & 0xF)); |
882 | return -EINVAL; | 883 | return -EINVAL; |
883 | } | 884 | } |
884 | break; | 885 | break; |
@@ -897,17 +898,17 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
897 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | 898 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
898 | tile_flags |= R300_DEPTHMICROTILE_TILED;; | 899 | tile_flags |= R300_DEPTHMICROTILE_TILED;; |
899 | 900 | ||
900 | tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); | 901 | tmp = idx_value & ~(0x7 << 16); |
901 | tmp |= tile_flags; | 902 | tmp |= tile_flags; |
902 | ib[idx] = tmp; | 903 | ib[idx] = tmp; |
903 | 904 | ||
904 | track->zb.pitch = ib_chunk->kdata[idx] & 0x3FFC; | 905 | track->zb.pitch = idx_value & 0x3FFC; |
905 | break; | 906 | break; |
906 | case 0x4104: | 907 | case 0x4104: |
907 | for (i = 0; i < 16; i++) { | 908 | for (i = 0; i < 16; i++) { |
908 | bool enabled; | 909 | bool enabled; |
909 | 910 | ||
910 | enabled = !!(ib_chunk->kdata[idx] & (1 << i)); | 911 | enabled = !!(idx_value & (1 << i)); |
911 | track->textures[i].enabled = enabled; | 912 | track->textures[i].enabled = enabled; |
912 | } | 913 | } |
913 | break; | 914 | break; |
@@ -929,9 +930,9 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
929 | case 0x44FC: | 930 | case 0x44FC: |
930 | /* TX_FORMAT1_[0-15] */ | 931 | /* TX_FORMAT1_[0-15] */ |
931 | i = (reg - 0x44C0) >> 2; | 932 | i = (reg - 0x44C0) >> 2; |
932 | tmp = (ib_chunk->kdata[idx] >> 25) & 0x3; | 933 | tmp = (idx_value >> 25) & 0x3; |
933 | track->textures[i].tex_coord_type = tmp; | 934 | track->textures[i].tex_coord_type = tmp; |
934 | switch ((ib_chunk->kdata[idx] & 0x1F)) { | 935 | switch ((idx_value & 0x1F)) { |
935 | case R300_TX_FORMAT_X8: | 936 | case R300_TX_FORMAT_X8: |
936 | case R300_TX_FORMAT_Y4X4: | 937 | case R300_TX_FORMAT_Y4X4: |
937 | case R300_TX_FORMAT_Z3Y3X2: | 938 | case R300_TX_FORMAT_Z3Y3X2: |
@@ -971,7 +972,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
971 | break; | 972 | break; |
972 | default: | 973 | default: |
973 | DRM_ERROR("Invalid texture format %u\n", | 974 | DRM_ERROR("Invalid texture format %u\n", |
974 | (ib_chunk->kdata[idx] & 0x1F)); | 975 | (idx_value & 0x1F)); |
975 | return -EINVAL; | 976 | return -EINVAL; |
976 | break; | 977 | break; |
977 | } | 978 | } |
@@ -994,11 +995,11 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
994 | case 0x443C: | 995 | case 0x443C: |
995 | /* TX_FILTER0_[0-15] */ | 996 | /* TX_FILTER0_[0-15] */ |
996 | i = (reg - 0x4400) >> 2; | 997 | i = (reg - 0x4400) >> 2; |
997 | tmp = ib_chunk->kdata[idx] & 0x7; | 998 | tmp = idx_value & 0x7; |
998 | if (tmp == 2 || tmp == 4 || tmp == 6) { | 999 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
999 | track->textures[i].roundup_w = false; | 1000 | track->textures[i].roundup_w = false; |
1000 | } | 1001 | } |
1001 | tmp = (ib_chunk->kdata[idx] >> 3) & 0x7; | 1002 | tmp = (idx_value >> 3) & 0x7; |
1002 | if (tmp == 2 || tmp == 4 || tmp == 6) { | 1003 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
1003 | track->textures[i].roundup_h = false; | 1004 | track->textures[i].roundup_h = false; |
1004 | } | 1005 | } |
@@ -1021,12 +1022,12 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1021 | case 0x453C: | 1022 | case 0x453C: |
1022 | /* TX_FORMAT2_[0-15] */ | 1023 | /* TX_FORMAT2_[0-15] */ |
1023 | i = (reg - 0x4500) >> 2; | 1024 | i = (reg - 0x4500) >> 2; |
1024 | tmp = ib_chunk->kdata[idx] & 0x3FFF; | 1025 | tmp = idx_value & 0x3FFF; |
1025 | track->textures[i].pitch = tmp + 1; | 1026 | track->textures[i].pitch = tmp + 1; |
1026 | if (p->rdev->family >= CHIP_RV515) { | 1027 | if (p->rdev->family >= CHIP_RV515) { |
1027 | tmp = ((ib_chunk->kdata[idx] >> 15) & 1) << 11; | 1028 | tmp = ((idx_value >> 15) & 1) << 11; |
1028 | track->textures[i].width_11 = tmp; | 1029 | track->textures[i].width_11 = tmp; |
1029 | tmp = ((ib_chunk->kdata[idx] >> 16) & 1) << 11; | 1030 | tmp = ((idx_value >> 16) & 1) << 11; |
1030 | track->textures[i].height_11 = tmp; | 1031 | track->textures[i].height_11 = tmp; |
1031 | } | 1032 | } |
1032 | break; | 1033 | break; |
@@ -1048,15 +1049,15 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1048 | case 0x44BC: | 1049 | case 0x44BC: |
1049 | /* TX_FORMAT0_[0-15] */ | 1050 | /* TX_FORMAT0_[0-15] */ |
1050 | i = (reg - 0x4480) >> 2; | 1051 | i = (reg - 0x4480) >> 2; |
1051 | tmp = ib_chunk->kdata[idx] & 0x7FF; | 1052 | tmp = idx_value & 0x7FF; |
1052 | track->textures[i].width = tmp + 1; | 1053 | track->textures[i].width = tmp + 1; |
1053 | tmp = (ib_chunk->kdata[idx] >> 11) & 0x7FF; | 1054 | tmp = (idx_value >> 11) & 0x7FF; |
1054 | track->textures[i].height = tmp + 1; | 1055 | track->textures[i].height = tmp + 1; |
1055 | tmp = (ib_chunk->kdata[idx] >> 26) & 0xF; | 1056 | tmp = (idx_value >> 26) & 0xF; |
1056 | track->textures[i].num_levels = tmp; | 1057 | track->textures[i].num_levels = tmp; |
1057 | tmp = ib_chunk->kdata[idx] & (1 << 31); | 1058 | tmp = idx_value & (1 << 31); |
1058 | track->textures[i].use_pitch = !!tmp; | 1059 | track->textures[i].use_pitch = !!tmp; |
1059 | tmp = (ib_chunk->kdata[idx] >> 22) & 0xF; | 1060 | tmp = (idx_value >> 22) & 0xF; |
1060 | track->textures[i].txdepth = tmp; | 1061 | track->textures[i].txdepth = tmp; |
1061 | break; | 1062 | break; |
1062 | case R300_ZB_ZPASS_ADDR: | 1063 | case R300_ZB_ZPASS_ADDR: |
@@ -1067,7 +1068,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1067 | r100_cs_dump_packet(p, pkt); | 1068 | r100_cs_dump_packet(p, pkt); |
1068 | return r; | 1069 | return r; |
1069 | } | 1070 | } |
1070 | ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); | 1071 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
1071 | break; | 1072 | break; |
1072 | case 0x4be8: | 1073 | case 0x4be8: |
1073 | /* valid register only on RV530 */ | 1074 | /* valid register only on RV530 */ |
@@ -1085,60 +1086,20 @@ static int r300_packet0_check(struct radeon_cs_parser *p, | |||
1085 | static int r300_packet3_check(struct radeon_cs_parser *p, | 1086 | static int r300_packet3_check(struct radeon_cs_parser *p, |
1086 | struct radeon_cs_packet *pkt) | 1087 | struct radeon_cs_packet *pkt) |
1087 | { | 1088 | { |
1088 | struct radeon_cs_chunk *ib_chunk; | ||
1089 | |||
1090 | struct radeon_cs_reloc *reloc; | 1089 | struct radeon_cs_reloc *reloc; |
1091 | struct r100_cs_track *track; | 1090 | struct r100_cs_track *track; |
1092 | volatile uint32_t *ib; | 1091 | volatile uint32_t *ib; |
1093 | unsigned idx; | 1092 | unsigned idx; |
1094 | unsigned i, c; | ||
1095 | int r; | 1093 | int r; |
1096 | 1094 | ||
1097 | ib = p->ib->ptr; | 1095 | ib = p->ib->ptr; |
1098 | ib_chunk = &p->chunks[p->chunk_ib_idx]; | ||
1099 | idx = pkt->idx + 1; | 1096 | idx = pkt->idx + 1; |
1100 | track = (struct r100_cs_track *)p->track; | 1097 | track = (struct r100_cs_track *)p->track; |
1101 | switch(pkt->opcode) { | 1098 | switch(pkt->opcode) { |
1102 | case PACKET3_3D_LOAD_VBPNTR: | 1099 | case PACKET3_3D_LOAD_VBPNTR: |
1103 | c = ib_chunk->kdata[idx++] & 0x1F; | 1100 | r = r100_packet3_load_vbpntr(p, pkt, idx); |
1104 | track->num_arrays = c; | 1101 | if (r) |
1105 | for (i = 0; i < (c - 1); i+=2, idx+=3) { | 1102 | return r; |
1106 | r = r100_cs_packet_next_reloc(p, &reloc); | ||
1107 | if (r) { | ||
1108 | DRM_ERROR("No reloc for packet3 %d\n", | ||
1109 | pkt->opcode); | ||
1110 | r100_cs_dump_packet(p, pkt); | ||
1111 | return r; | ||
1112 | } | ||
1113 | ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); | ||
1114 | track->arrays[i + 0].robj = reloc->robj; | ||
1115 | track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; | ||
1116 | track->arrays[i + 0].esize &= 0x7F; | ||
1117 | r = r100_cs_packet_next_reloc(p, &reloc); | ||
1118 | if (r) { | ||
1119 | DRM_ERROR("No reloc for packet3 %d\n", | ||
1120 | pkt->opcode); | ||
1121 | r100_cs_dump_packet(p, pkt); | ||
1122 | return r; | ||
1123 | } | ||
1124 | ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset); | ||
1125 | track->arrays[i + 1].robj = reloc->robj; | ||
1126 | track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24; | ||
1127 | track->arrays[i + 1].esize &= 0x7F; | ||
1128 | } | ||
1129 | if (c & 1) { | ||
1130 | r = r100_cs_packet_next_reloc(p, &reloc); | ||
1131 | if (r) { | ||
1132 | DRM_ERROR("No reloc for packet3 %d\n", | ||
1133 | pkt->opcode); | ||
1134 | r100_cs_dump_packet(p, pkt); | ||
1135 | return r; | ||
1136 | } | ||
1137 | ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); | ||
1138 | track->arrays[i + 0].robj = reloc->robj; | ||
1139 | track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; | ||
1140 | track->arrays[i + 0].esize &= 0x7F; | ||
1141 | } | ||
1142 | break; | 1103 | break; |
1143 | case PACKET3_INDX_BUFFER: | 1104 | case PACKET3_INDX_BUFFER: |
1144 | r = r100_cs_packet_next_reloc(p, &reloc); | 1105 | r = r100_cs_packet_next_reloc(p, &reloc); |
@@ -1147,7 +1108,7 @@ static int r300_packet3_check(struct radeon_cs_parser *p, | |||
1147 | r100_cs_dump_packet(p, pkt); | 1108 | r100_cs_dump_packet(p, pkt); |
1148 | return r; | 1109 | return r; |
1149 | } | 1110 | } |
1150 | ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); | 1111 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); |
1151 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); | 1112 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
1152 | if (r) { | 1113 | if (r) { |
1153 | return r; | 1114 | return r; |
@@ -1158,11 +1119,11 @@ static int r300_packet3_check(struct radeon_cs_parser *p, | |||
1158 | /* Number of dwords is vtx_size * (num_vertices - 1) | 1119 | /* Number of dwords is vtx_size * (num_vertices - 1) |
1159 | * PRIM_WALK must be equal to 3 vertex data in embedded | 1120 | * PRIM_WALK must be equal to 3 vertex data in embedded |
1160 | * in cmd stream */ | 1121 | * in cmd stream */ |
1161 | if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) { | 1122 | if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
1162 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); | 1123 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1163 | return -EINVAL; | 1124 | return -EINVAL; |
1164 | } | 1125 | } |
1165 | track->vap_vf_cntl = ib_chunk->kdata[idx+1]; | 1126 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1166 | track->immd_dwords = pkt->count - 1; | 1127 | track->immd_dwords = pkt->count - 1; |
1167 | r = r100_cs_track_check(p->rdev, track); | 1128 | r = r100_cs_track_check(p->rdev, track); |
1168 | if (r) { | 1129 | if (r) { |
@@ -1173,11 +1134,11 @@ static int r300_packet3_check(struct radeon_cs_parser *p, | |||
1173 | /* Number of dwords is vtx_size * (num_vertices - 1) | 1134 | /* Number of dwords is vtx_size * (num_vertices - 1) |
1174 | * PRIM_WALK must be equal to 3 vertex data in embedded | 1135 | * PRIM_WALK must be equal to 3 vertex data in embedded |
1175 | * in cmd stream */ | 1136 | * in cmd stream */ |
1176 | if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) { | 1137 | if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { |
1177 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); | 1138 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1178 | return -EINVAL; | 1139 | return -EINVAL; |
1179 | } | 1140 | } |
1180 | track->vap_vf_cntl = ib_chunk->kdata[idx]; | 1141 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1181 | track->immd_dwords = pkt->count; | 1142 | track->immd_dwords = pkt->count; |
1182 | r = r100_cs_track_check(p->rdev, track); | 1143 | r = r100_cs_track_check(p->rdev, track); |
1183 | if (r) { | 1144 | if (r) { |
@@ -1185,28 +1146,28 @@ static int r300_packet3_check(struct radeon_cs_parser *p, | |||
1185 | } | 1146 | } |
1186 | break; | 1147 | break; |
1187 | case PACKET3_3D_DRAW_VBUF: | 1148 | case PACKET3_3D_DRAW_VBUF: |
1188 | track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; | 1149 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1189 | r = r100_cs_track_check(p->rdev, track); | 1150 | r = r100_cs_track_check(p->rdev, track); |
1190 | if (r) { | 1151 | if (r) { |
1191 | return r; | 1152 | return r; |
1192 | } | 1153 | } |
1193 | break; | 1154 | break; |
1194 | case PACKET3_3D_DRAW_VBUF_2: | 1155 | case PACKET3_3D_DRAW_VBUF_2: |
1195 | track->vap_vf_cntl = ib_chunk->kdata[idx]; | 1156 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1196 | r = r100_cs_track_check(p->rdev, track); | 1157 | r = r100_cs_track_check(p->rdev, track); |
1197 | if (r) { | 1158 | if (r) { |
1198 | return r; | 1159 | return r; |
1199 | } | 1160 | } |
1200 | break; | 1161 | break; |
1201 | case PACKET3_3D_DRAW_INDX: | 1162 | case PACKET3_3D_DRAW_INDX: |
1202 | track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; | 1163 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
1203 | r = r100_cs_track_check(p->rdev, track); | 1164 | r = r100_cs_track_check(p->rdev, track); |
1204 | if (r) { | 1165 | if (r) { |
1205 | return r; | 1166 | return r; |
1206 | } | 1167 | } |
1207 | break; | 1168 | break; |
1208 | case PACKET3_3D_DRAW_INDX_2: | 1169 | case PACKET3_3D_DRAW_INDX_2: |
1209 | track->vap_vf_cntl = ib_chunk->kdata[idx]; | 1170 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
1210 | r = r100_cs_track_check(p->rdev, track); | 1171 | r = r100_cs_track_check(p->rdev, track); |
1211 | if (r) { | 1172 | if (r) { |
1212 | return r; | 1173 | return r; |
diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h index e1d5e0331e19..868add6e166d 100644 --- a/drivers/gpu/drm/radeon/r500_reg.h +++ b/drivers/gpu/drm/radeon/r500_reg.h | |||
@@ -445,6 +445,8 @@ | |||
445 | #define AVIVO_D1MODE_VBLANK_STATUS 0x6534 | 445 | #define AVIVO_D1MODE_VBLANK_STATUS 0x6534 |
446 | # define AVIVO_VBLANK_ACK (1 << 4) | 446 | # define AVIVO_VBLANK_ACK (1 << 4) |
447 | #define AVIVO_D1MODE_VLINE_START_END 0x6538 | 447 | #define AVIVO_D1MODE_VLINE_START_END 0x6538 |
448 | #define AVIVO_D1MODE_VLINE_STATUS 0x653c | ||
449 | # define AVIVO_D1MODE_VLINE_STAT (1 << 12) | ||
448 | #define AVIVO_DxMODE_INT_MASK 0x6540 | 450 | #define AVIVO_DxMODE_INT_MASK 0x6540 |
449 | # define AVIVO_D1MODE_INT_MASK (1 << 0) | 451 | # define AVIVO_D1MODE_INT_MASK (1 << 0) |
450 | # define AVIVO_D2MODE_INT_MASK (1 << 8) | 452 | # define AVIVO_D2MODE_INT_MASK (1 << 8) |
@@ -502,6 +504,7 @@ | |||
502 | 504 | ||
503 | #define AVIVO_D2MODE_VBLANK_STATUS 0x6d34 | 505 | #define AVIVO_D2MODE_VBLANK_STATUS 0x6d34 |
504 | #define AVIVO_D2MODE_VLINE_START_END 0x6d38 | 506 | #define AVIVO_D2MODE_VLINE_START_END 0x6d38 |
507 | #define AVIVO_D2MODE_VLINE_STATUS 0x6d3c | ||
505 | #define AVIVO_D2MODE_VIEWPORT_START 0x6d80 | 508 | #define AVIVO_D2MODE_VIEWPORT_START 0x6d80 |
506 | #define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 | 509 | #define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 |
507 | #define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 | 510 | #define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 |
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c index d4b0b9d2e39b..0bf13fccdaf2 100644 --- a/drivers/gpu/drm/radeon/r520.c +++ b/drivers/gpu/drm/radeon/r520.c | |||
@@ -26,108 +26,13 @@ | |||
26 | * Jerome Glisse | 26 | * Jerome Glisse |
27 | */ | 27 | */ |
28 | #include "drmP.h" | 28 | #include "drmP.h" |
29 | #include "radeon_reg.h" | ||
30 | #include "radeon.h" | 29 | #include "radeon.h" |
30 | #include "atom.h" | ||
31 | #include "r520d.h" | ||
31 | 32 | ||
32 | /* r520,rv530,rv560,rv570,r580 depends on : */ | 33 | /* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */ |
33 | void r100_hdp_reset(struct radeon_device *rdev); | ||
34 | void r420_pipes_init(struct radeon_device *rdev); | ||
35 | void rs600_mc_disable_clients(struct radeon_device *rdev); | ||
36 | void rs600_disable_vga(struct radeon_device *rdev); | ||
37 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); | ||
38 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev); | ||
39 | 34 | ||
40 | /* This files gather functions specifics to: | 35 | static int r520_mc_wait_for_idle(struct radeon_device *rdev) |
41 | * r520,rv530,rv560,rv570,r580 | ||
42 | * | ||
43 | * Some of these functions might be used by newer ASICs. | ||
44 | */ | ||
45 | void r520_gpu_init(struct radeon_device *rdev); | ||
46 | int r520_mc_wait_for_idle(struct radeon_device *rdev); | ||
47 | |||
48 | |||
49 | /* | ||
50 | * MC | ||
51 | */ | ||
52 | int r520_mc_init(struct radeon_device *rdev) | ||
53 | { | ||
54 | uint32_t tmp; | ||
55 | int r; | ||
56 | |||
57 | if (r100_debugfs_rbbm_init(rdev)) { | ||
58 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); | ||
59 | } | ||
60 | if (rv515_debugfs_pipes_info_init(rdev)) { | ||
61 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); | ||
62 | } | ||
63 | if (rv515_debugfs_ga_info_init(rdev)) { | ||
64 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); | ||
65 | } | ||
66 | |||
67 | r520_gpu_init(rdev); | ||
68 | rv370_pcie_gart_disable(rdev); | ||
69 | |||
70 | /* Setup GPU memory space */ | ||
71 | rdev->mc.vram_location = 0xFFFFFFFFUL; | ||
72 | rdev->mc.gtt_location = 0xFFFFFFFFUL; | ||
73 | if (rdev->flags & RADEON_IS_AGP) { | ||
74 | r = radeon_agp_init(rdev); | ||
75 | if (r) { | ||
76 | printk(KERN_WARNING "[drm] Disabling AGP\n"); | ||
77 | rdev->flags &= ~RADEON_IS_AGP; | ||
78 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | ||
79 | } else { | ||
80 | rdev->mc.gtt_location = rdev->mc.agp_base; | ||
81 | } | ||
82 | } | ||
83 | r = radeon_mc_setup(rdev); | ||
84 | if (r) { | ||
85 | return r; | ||
86 | } | ||
87 | |||
88 | /* Program GPU memory space */ | ||
89 | rs600_mc_disable_clients(rdev); | ||
90 | if (r520_mc_wait_for_idle(rdev)) { | ||
91 | printk(KERN_WARNING "Failed to wait MC idle while " | ||
92 | "programming pipes. Bad things might happen.\n"); | ||
93 | } | ||
94 | /* Write VRAM size in case we are limiting it */ | ||
95 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); | ||
96 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; | ||
97 | tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16); | ||
98 | tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16); | ||
99 | WREG32_MC(R520_MC_FB_LOCATION, tmp); | ||
100 | WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); | ||
101 | WREG32(0x310, rdev->mc.vram_location); | ||
102 | if (rdev->flags & RADEON_IS_AGP) { | ||
103 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; | ||
104 | tmp = REG_SET(R520_MC_AGP_TOP, tmp >> 16); | ||
105 | tmp |= REG_SET(R520_MC_AGP_START, rdev->mc.gtt_location >> 16); | ||
106 | WREG32_MC(R520_MC_AGP_LOCATION, tmp); | ||
107 | WREG32_MC(R520_MC_AGP_BASE, rdev->mc.agp_base); | ||
108 | WREG32_MC(R520_MC_AGP_BASE_2, 0); | ||
109 | } else { | ||
110 | WREG32_MC(R520_MC_AGP_LOCATION, 0x0FFFFFFF); | ||
111 | WREG32_MC(R520_MC_AGP_BASE, 0); | ||
112 | WREG32_MC(R520_MC_AGP_BASE_2, 0); | ||
113 | } | ||
114 | return 0; | ||
115 | } | ||
116 | |||
117 | void r520_mc_fini(struct radeon_device *rdev) | ||
118 | { | ||
119 | } | ||
120 | |||
121 | |||
122 | /* | ||
123 | * Global GPU functions | ||
124 | */ | ||
125 | void r520_errata(struct radeon_device *rdev) | ||
126 | { | ||
127 | rdev->pll_errata = 0; | ||
128 | } | ||
129 | |||
130 | int r520_mc_wait_for_idle(struct radeon_device *rdev) | ||
131 | { | 36 | { |
132 | unsigned i; | 37 | unsigned i; |
133 | uint32_t tmp; | 38 | uint32_t tmp; |
@@ -143,12 +48,12 @@ int r520_mc_wait_for_idle(struct radeon_device *rdev) | |||
143 | return -1; | 48 | return -1; |
144 | } | 49 | } |
145 | 50 | ||
146 | void r520_gpu_init(struct radeon_device *rdev) | 51 | static void r520_gpu_init(struct radeon_device *rdev) |
147 | { | 52 | { |
148 | unsigned pipe_select_current, gb_pipe_select, tmp; | 53 | unsigned pipe_select_current, gb_pipe_select, tmp; |
149 | 54 | ||
150 | r100_hdp_reset(rdev); | 55 | r100_hdp_reset(rdev); |
151 | rs600_disable_vga(rdev); | 56 | rv515_vga_render_disable(rdev); |
152 | /* | 57 | /* |
153 | * DST_PIPE_CONFIG 0x170C | 58 | * DST_PIPE_CONFIG 0x170C |
154 | * GB_TILE_CONFIG 0x4018 | 59 | * GB_TILE_CONFIG 0x4018 |
@@ -186,10 +91,6 @@ void r520_gpu_init(struct radeon_device *rdev) | |||
186 | } | 91 | } |
187 | } | 92 | } |
188 | 93 | ||
189 | |||
190 | /* | ||
191 | * VRAM info | ||
192 | */ | ||
193 | static void r520_vram_get_type(struct radeon_device *rdev) | 94 | static void r520_vram_get_type(struct radeon_device *rdev) |
194 | { | 95 | { |
195 | uint32_t tmp; | 96 | uint32_t tmp; |
@@ -233,7 +134,168 @@ void r520_vram_info(struct radeon_device *rdev) | |||
233 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); | 134 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
234 | } | 135 | } |
235 | 136 | ||
236 | void r520_bandwidth_update(struct radeon_device *rdev) | 137 | void r520_mc_program(struct radeon_device *rdev) |
138 | { | ||
139 | struct rv515_mc_save save; | ||
140 | |||
141 | /* Stops all mc clients */ | ||
142 | rv515_mc_stop(rdev, &save); | ||
143 | |||
144 | /* Wait for mc idle */ | ||
145 | if (r520_mc_wait_for_idle(rdev)) | ||
146 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); | ||
147 | /* Write VRAM size in case we are limiting it */ | ||
148 | WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); | ||
149 | /* Program MC, should be a 32bits limited address space */ | ||
150 | WREG32_MC(R_000004_MC_FB_LOCATION, | ||
151 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | | ||
152 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); | ||
153 | WREG32(R_000134_HDP_FB_LOCATION, | ||
154 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); | ||
155 | if (rdev->flags & RADEON_IS_AGP) { | ||
156 | WREG32_MC(R_000005_MC_AGP_LOCATION, | ||
157 | S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) | | ||
158 | S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); | ||
159 | WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); | ||
160 | WREG32_MC(R_000007_AGP_BASE_2, | ||
161 | S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); | ||
162 | } else { | ||
163 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF); | ||
164 | WREG32_MC(R_000006_AGP_BASE, 0); | ||
165 | WREG32_MC(R_000007_AGP_BASE_2, 0); | ||
166 | } | ||
167 | |||
168 | rv515_mc_resume(rdev, &save); | ||
169 | } | ||
170 | |||
171 | static int r520_startup(struct radeon_device *rdev) | ||
172 | { | ||
173 | int r; | ||
174 | |||
175 | r520_mc_program(rdev); | ||
176 | /* Resume clock */ | ||
177 | rv515_clock_startup(rdev); | ||
178 | /* Initialize GPU configuration (# pipes, ...) */ | ||
179 | r520_gpu_init(rdev); | ||
180 | /* Initialize GART (initialize after TTM so we can allocate | ||
181 | * memory through TTM but finalize after TTM) */ | ||
182 | if (rdev->flags & RADEON_IS_PCIE) { | ||
183 | r = rv370_pcie_gart_enable(rdev); | ||
184 | if (r) | ||
185 | return r; | ||
186 | } | ||
187 | /* Enable IRQ */ | ||
188 | rdev->irq.sw_int = true; | ||
189 | r100_irq_set(rdev); | ||
190 | /* 1M ring buffer */ | ||
191 | r = r100_cp_init(rdev, 1024 * 1024); | ||
192 | if (r) { | ||
193 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); | ||
194 | return r; | ||
195 | } | ||
196 | r = r100_wb_init(rdev); | ||
197 | if (r) | ||
198 | dev_err(rdev->dev, "failled initializing WB (%d).\n", r); | ||
199 | r = r100_ib_init(rdev); | ||
200 | if (r) { | ||
201 | dev_err(rdev->dev, "failled initializing IB (%d).\n", r); | ||
202 | return r; | ||
203 | } | ||
204 | return 0; | ||
205 | } | ||
206 | |||
207 | int r520_resume(struct radeon_device *rdev) | ||
237 | { | 208 | { |
238 | rv515_bandwidth_avivo_update(rdev); | 209 | /* Make sur GART are not working */ |
210 | if (rdev->flags & RADEON_IS_PCIE) | ||
211 | rv370_pcie_gart_disable(rdev); | ||
212 | /* Resume clock before doing reset */ | ||
213 | rv515_clock_startup(rdev); | ||
214 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | ||
215 | if (radeon_gpu_reset(rdev)) { | ||
216 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | ||
217 | RREG32(R_000E40_RBBM_STATUS), | ||
218 | RREG32(R_0007C0_CP_STAT)); | ||
219 | } | ||
220 | /* post */ | ||
221 | atom_asic_init(rdev->mode_info.atom_context); | ||
222 | /* Resume clock after posting */ | ||
223 | rv515_clock_startup(rdev); | ||
224 | return r520_startup(rdev); | ||
225 | } | ||
226 | |||
227 | int r520_init(struct radeon_device *rdev) | ||
228 | { | ||
229 | int r; | ||
230 | |||
231 | rdev->new_init_path = true; | ||
232 | /* Initialize scratch registers */ | ||
233 | radeon_scratch_init(rdev); | ||
234 | /* Initialize surface registers */ | ||
235 | radeon_surface_init(rdev); | ||
236 | /* TODO: disable VGA need to use VGA request */ | ||
237 | /* BIOS*/ | ||
238 | if (!radeon_get_bios(rdev)) { | ||
239 | if (ASIC_IS_AVIVO(rdev)) | ||
240 | return -EINVAL; | ||
241 | } | ||
242 | if (rdev->is_atom_bios) { | ||
243 | r = radeon_atombios_init(rdev); | ||
244 | if (r) | ||
245 | return r; | ||
246 | } else { | ||
247 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); | ||
248 | return -EINVAL; | ||
249 | } | ||
250 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | ||
251 | if (radeon_gpu_reset(rdev)) { | ||
252 | dev_warn(rdev->dev, | ||
253 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | ||
254 | RREG32(R_000E40_RBBM_STATUS), | ||
255 | RREG32(R_0007C0_CP_STAT)); | ||
256 | } | ||
257 | /* check if cards are posted or not */ | ||
258 | if (!radeon_card_posted(rdev) && rdev->bios) { | ||
259 | DRM_INFO("GPU not posted. posting now...\n"); | ||
260 | atom_asic_init(rdev->mode_info.atom_context); | ||
261 | } | ||
262 | /* Initialize clocks */ | ||
263 | radeon_get_clock_info(rdev->ddev); | ||
264 | /* Get vram informations */ | ||
265 | r520_vram_info(rdev); | ||
266 | /* Initialize memory controller (also test AGP) */ | ||
267 | r = r420_mc_init(rdev); | ||
268 | if (r) | ||
269 | return r; | ||
270 | rv515_debugfs(rdev); | ||
271 | /* Fence driver */ | ||
272 | r = radeon_fence_driver_init(rdev); | ||
273 | if (r) | ||
274 | return r; | ||
275 | r = radeon_irq_kms_init(rdev); | ||
276 | if (r) | ||
277 | return r; | ||
278 | /* Memory manager */ | ||
279 | r = radeon_object_init(rdev); | ||
280 | if (r) | ||
281 | return r; | ||
282 | r = rv370_pcie_gart_init(rdev); | ||
283 | if (r) | ||
284 | return r; | ||
285 | rv515_set_safe_registers(rdev); | ||
286 | rdev->accel_working = true; | ||
287 | r = r520_startup(rdev); | ||
288 | if (r) { | ||
289 | /* Somethings want wront with the accel init stop accel */ | ||
290 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | ||
291 | rv515_suspend(rdev); | ||
292 | r100_cp_fini(rdev); | ||
293 | r100_wb_fini(rdev); | ||
294 | r100_ib_fini(rdev); | ||
295 | rv370_pcie_gart_fini(rdev); | ||
296 | radeon_agp_fini(rdev); | ||
297 | radeon_irq_kms_fini(rdev); | ||
298 | rdev->accel_working = false; | ||
299 | } | ||
300 | return 0; | ||
239 | } | 301 | } |
diff --git a/drivers/gpu/drm/radeon/r520d.h b/drivers/gpu/drm/radeon/r520d.h new file mode 100644 index 000000000000..61af61f644bc --- /dev/null +++ b/drivers/gpu/drm/radeon/r520d.h | |||
@@ -0,0 +1,187 @@ | |||
1 | /* | ||
2 | * Copyright 2008 Advanced Micro Devices, Inc. | ||
3 | * Copyright 2008 Red Hat Inc. | ||
4 | * Copyright 2009 Jerome Glisse. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
22 | * OTHER DEALINGS IN THE SOFTWARE. | ||
23 | * | ||
24 | * Authors: Dave Airlie | ||
25 | * Alex Deucher | ||
26 | * Jerome Glisse | ||
27 | */ | ||
28 | #ifndef __R520D_H__ | ||
29 | #define __R520D_H__ | ||
30 | |||
31 | /* Registers */ | ||
32 | #define R_0000F8_CONFIG_MEMSIZE 0x0000F8 | ||
33 | #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) | ||
34 | #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) | ||
35 | #define C_0000F8_CONFIG_MEMSIZE 0x00000000 | ||
36 | #define R_000134_HDP_FB_LOCATION 0x000134 | ||
37 | #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) | ||
38 | #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) | ||
39 | #define C_000134_HDP_FB_START 0xFFFF0000 | ||
40 | #define R_0007C0_CP_STAT 0x0007C0 | ||
41 | #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) | ||
42 | #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) | ||
43 | #define C_0007C0_MRU_BUSY 0xFFFFFFFE | ||
44 | #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) | ||
45 | #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) | ||
46 | #define C_0007C0_MWU_BUSY 0xFFFFFFFD | ||
47 | #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) | ||
48 | #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) | ||
49 | #define C_0007C0_RSIU_BUSY 0xFFFFFFFB | ||
50 | #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) | ||
51 | #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) | ||
52 | #define C_0007C0_RCIU_BUSY 0xFFFFFFF7 | ||
53 | #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) | ||
54 | #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) | ||
55 | #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF | ||
56 | #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) | ||
57 | #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) | ||
58 | #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF | ||
59 | #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) | ||
60 | #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) | ||
61 | #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF | ||
62 | #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) | ||
63 | #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) | ||
64 | #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF | ||
65 | #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) | ||
66 | #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) | ||
67 | #define C_0007C0_CSI_BUSY 0xFFFFDFFF | ||
68 | #define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) | ||
69 | #define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) | ||
70 | #define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF | ||
71 | #define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) | ||
72 | #define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) | ||
73 | #define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF | ||
74 | #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) | ||
75 | #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) | ||
76 | #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF | ||
77 | #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) | ||
78 | #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) | ||
79 | #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF | ||
80 | #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) | ||
81 | #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) | ||
82 | #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF | ||
83 | #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) | ||
84 | #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) | ||
85 | #define C_0007C0_CP_BUSY 0x7FFFFFFF | ||
86 | #define R_000E40_RBBM_STATUS 0x000E40 | ||
87 | #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) | ||
88 | #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) | ||
89 | #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 | ||
90 | #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) | ||
91 | #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) | ||
92 | #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF | ||
93 | #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) | ||
94 | #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) | ||
95 | #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF | ||
96 | #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) | ||
97 | #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) | ||
98 | #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF | ||
99 | #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) | ||
100 | #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) | ||
101 | #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF | ||
102 | #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) | ||
103 | #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) | ||
104 | #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF | ||
105 | #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) | ||
106 | #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) | ||
107 | #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF | ||
108 | #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) | ||
109 | #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) | ||
110 | #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF | ||
111 | #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) | ||
112 | #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) | ||
113 | #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF | ||
114 | #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) | ||
115 | #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) | ||
116 | #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF | ||
117 | #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) | ||
118 | #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) | ||
119 | #define C_000E40_E2_BUSY 0xFFFDFFFF | ||
120 | #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) | ||
121 | #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) | ||
122 | #define C_000E40_RB2D_BUSY 0xFFFBFFFF | ||
123 | #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) | ||
124 | #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) | ||
125 | #define C_000E40_RB3D_BUSY 0xFFF7FFFF | ||
126 | #define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) | ||
127 | #define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) | ||
128 | #define C_000E40_VAP_BUSY 0xFFEFFFFF | ||
129 | #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) | ||
130 | #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) | ||
131 | #define C_000E40_RE_BUSY 0xFFDFFFFF | ||
132 | #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) | ||
133 | #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) | ||
134 | #define C_000E40_TAM_BUSY 0xFFBFFFFF | ||
135 | #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) | ||
136 | #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) | ||
137 | #define C_000E40_TDM_BUSY 0xFF7FFFFF | ||
138 | #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) | ||
139 | #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) | ||
140 | #define C_000E40_PB_BUSY 0xFEFFFFFF | ||
141 | #define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) | ||
142 | #define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) | ||
143 | #define C_000E40_TIM_BUSY 0xFDFFFFFF | ||
144 | #define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) | ||
145 | #define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) | ||
146 | #define C_000E40_GA_BUSY 0xFBFFFFFF | ||
147 | #define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) | ||
148 | #define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) | ||
149 | #define C_000E40_CBA2D_BUSY 0xF7FFFFFF | ||
150 | #define S_000E40_RBBM_HIBUSY(x) (((x) & 0x1) << 28) | ||
151 | #define G_000E40_RBBM_HIBUSY(x) (((x) >> 28) & 0x1) | ||
152 | #define C_000E40_RBBM_HIBUSY 0xEFFFFFFF | ||
153 | #define S_000E40_SKID_CFBUSY(x) (((x) & 0x1) << 29) | ||
154 | #define G_000E40_SKID_CFBUSY(x) (((x) >> 29) & 0x1) | ||
155 | #define C_000E40_SKID_CFBUSY 0xDFFFFFFF | ||
156 | #define S_000E40_VAP_VF_BUSY(x) (((x) & 0x1) << 30) | ||
157 | #define G_000E40_VAP_VF_BUSY(x) (((x) >> 30) & 0x1) | ||
158 | #define C_000E40_VAP_VF_BUSY 0xBFFFFFFF | ||
159 | #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) | ||
160 | #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) | ||
161 | #define C_000E40_GUI_ACTIVE 0x7FFFFFFF | ||
162 | |||
163 | |||
164 | #define R_000004_MC_FB_LOCATION 0x000004 | ||
165 | #define S_000004_MC_FB_START(x) (((x) & 0xFFFF) << 0) | ||
166 | #define G_000004_MC_FB_START(x) (((x) >> 0) & 0xFFFF) | ||
167 | #define C_000004_MC_FB_START 0xFFFF0000 | ||
168 | #define S_000004_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) | ||
169 | #define G_000004_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) | ||
170 | #define C_000004_MC_FB_TOP 0x0000FFFF | ||
171 | #define R_000005_MC_AGP_LOCATION 0x000005 | ||
172 | #define S_000005_MC_AGP_START(x) (((x) & 0xFFFF) << 0) | ||
173 | #define G_000005_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) | ||
174 | #define C_000005_MC_AGP_START 0xFFFF0000 | ||
175 | #define S_000005_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) | ||
176 | #define G_000005_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) | ||
177 | #define C_000005_MC_AGP_TOP 0x0000FFFF | ||
178 | #define R_000006_AGP_BASE 0x000006 | ||
179 | #define S_000006_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) | ||
180 | #define G_000006_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) | ||
181 | #define C_000006_AGP_BASE_ADDR 0x00000000 | ||
182 | #define R_000007_AGP_BASE_2 0x000007 | ||
183 | #define S_000007_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) | ||
184 | #define G_000007_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) | ||
185 | #define C_000007_AGP_BASE_ADDR_2 0xFFFFFFF0 | ||
186 | |||
187 | #endif | ||
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index eab31c1d6df1..2e4e60edbff4 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -33,8 +33,8 @@ | |||
33 | #include "radeon.h" | 33 | #include "radeon.h" |
34 | #include "radeon_mode.h" | 34 | #include "radeon_mode.h" |
35 | #include "r600d.h" | 35 | #include "r600d.h" |
36 | #include "avivod.h" | ||
37 | #include "atom.h" | 36 | #include "atom.h" |
37 | #include "avivod.h" | ||
38 | 38 | ||
39 | #define PFP_UCODE_SIZE 576 | 39 | #define PFP_UCODE_SIZE 576 |
40 | #define PM4_UCODE_SIZE 1792 | 40 | #define PM4_UCODE_SIZE 1792 |
@@ -342,7 +342,7 @@ static void r600_mc_resume(struct radeon_device *rdev) | |||
342 | 342 | ||
343 | /* we need to own VRAM, so turn off the VGA renderer here | 343 | /* we need to own VRAM, so turn off the VGA renderer here |
344 | * to stop it overwriting our objects */ | 344 | * to stop it overwriting our objects */ |
345 | radeon_avivo_vga_render_disable(rdev); | 345 | rv515_vga_render_disable(rdev); |
346 | } | 346 | } |
347 | 347 | ||
348 | int r600_mc_init(struct radeon_device *rdev) | 348 | int r600_mc_init(struct radeon_device *rdev) |
@@ -380,6 +380,13 @@ int r600_mc_init(struct radeon_device *rdev) | |||
380 | /* Setup GPU memory space */ | 380 | /* Setup GPU memory space */ |
381 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); | 381 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); |
382 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); | 382 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); |
383 | |||
384 | if (rdev->mc.mc_vram_size > rdev->mc.aper_size) | ||
385 | rdev->mc.mc_vram_size = rdev->mc.aper_size; | ||
386 | |||
387 | if (rdev->mc.real_vram_size > rdev->mc.aper_size) | ||
388 | rdev->mc.real_vram_size = rdev->mc.aper_size; | ||
389 | |||
383 | if (rdev->flags & RADEON_IS_AGP) { | 390 | if (rdev->flags & RADEON_IS_AGP) { |
384 | r = radeon_agp_init(rdev); | 391 | r = radeon_agp_init(rdev); |
385 | if (r) | 392 | if (r) |
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index 33b89cd8743e..d28970db6a2d 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c | |||
@@ -28,7 +28,6 @@ | |||
28 | #include "drmP.h" | 28 | #include "drmP.h" |
29 | #include "radeon.h" | 29 | #include "radeon.h" |
30 | #include "r600d.h" | 30 | #include "r600d.h" |
31 | #include "avivod.h" | ||
32 | 31 | ||
33 | static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, | 32 | static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, |
34 | struct radeon_cs_reloc **cs_reloc); | 33 | struct radeon_cs_reloc **cs_reloc); |
@@ -57,7 +56,7 @@ int r600_cs_packet_parse(struct radeon_cs_parser *p, | |||
57 | idx, ib_chunk->length_dw); | 56 | idx, ib_chunk->length_dw); |
58 | return -EINVAL; | 57 | return -EINVAL; |
59 | } | 58 | } |
60 | header = ib_chunk->kdata[idx]; | 59 | header = radeon_get_ib_value(p, idx); |
61 | pkt->idx = idx; | 60 | pkt->idx = idx; |
62 | pkt->type = CP_PACKET_GET_TYPE(header); | 61 | pkt->type = CP_PACKET_GET_TYPE(header); |
63 | pkt->count = CP_PACKET_GET_COUNT(header); | 62 | pkt->count = CP_PACKET_GET_COUNT(header); |
@@ -98,7 +97,6 @@ int r600_cs_packet_parse(struct radeon_cs_parser *p, | |||
98 | static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, | 97 | static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, |
99 | struct radeon_cs_reloc **cs_reloc) | 98 | struct radeon_cs_reloc **cs_reloc) |
100 | { | 99 | { |
101 | struct radeon_cs_chunk *ib_chunk; | ||
102 | struct radeon_cs_chunk *relocs_chunk; | 100 | struct radeon_cs_chunk *relocs_chunk; |
103 | struct radeon_cs_packet p3reloc; | 101 | struct radeon_cs_packet p3reloc; |
104 | unsigned idx; | 102 | unsigned idx; |
@@ -109,7 +107,6 @@ static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, | |||
109 | return -EINVAL; | 107 | return -EINVAL; |
110 | } | 108 | } |
111 | *cs_reloc = NULL; | 109 | *cs_reloc = NULL; |
112 | ib_chunk = &p->chunks[p->chunk_ib_idx]; | ||
113 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; | 110 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; |
114 | r = r600_cs_packet_parse(p, &p3reloc, p->idx); | 111 | r = r600_cs_packet_parse(p, &p3reloc, p->idx); |
115 | if (r) { | 112 | if (r) { |
@@ -121,7 +118,7 @@ static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, | |||
121 | p3reloc.idx); | 118 | p3reloc.idx); |
122 | return -EINVAL; | 119 | return -EINVAL; |
123 | } | 120 | } |
124 | idx = ib_chunk->kdata[p3reloc.idx + 1]; | 121 | idx = radeon_get_ib_value(p, p3reloc.idx + 1); |
125 | if (idx >= relocs_chunk->length_dw) { | 122 | if (idx >= relocs_chunk->length_dw) { |
126 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", | 123 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", |
127 | idx, relocs_chunk->length_dw); | 124 | idx, relocs_chunk->length_dw); |
@@ -146,7 +143,6 @@ static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, | |||
146 | static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, | 143 | static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, |
147 | struct radeon_cs_reloc **cs_reloc) | 144 | struct radeon_cs_reloc **cs_reloc) |
148 | { | 145 | { |
149 | struct radeon_cs_chunk *ib_chunk; | ||
150 | struct radeon_cs_chunk *relocs_chunk; | 146 | struct radeon_cs_chunk *relocs_chunk; |
151 | struct radeon_cs_packet p3reloc; | 147 | struct radeon_cs_packet p3reloc; |
152 | unsigned idx; | 148 | unsigned idx; |
@@ -157,7 +153,6 @@ static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, | |||
157 | return -EINVAL; | 153 | return -EINVAL; |
158 | } | 154 | } |
159 | *cs_reloc = NULL; | 155 | *cs_reloc = NULL; |
160 | ib_chunk = &p->chunks[p->chunk_ib_idx]; | ||
161 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; | 156 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; |
162 | r = r600_cs_packet_parse(p, &p3reloc, p->idx); | 157 | r = r600_cs_packet_parse(p, &p3reloc, p->idx); |
163 | if (r) { | 158 | if (r) { |
@@ -169,7 +164,7 @@ static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, | |||
169 | p3reloc.idx); | 164 | p3reloc.idx); |
170 | return -EINVAL; | 165 | return -EINVAL; |
171 | } | 166 | } |
172 | idx = ib_chunk->kdata[p3reloc.idx + 1]; | 167 | idx = radeon_get_ib_value(p, p3reloc.idx + 1); |
173 | if (idx >= relocs_chunk->length_dw) { | 168 | if (idx >= relocs_chunk->length_dw) { |
174 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", | 169 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", |
175 | idx, relocs_chunk->length_dw); | 170 | idx, relocs_chunk->length_dw); |
@@ -181,13 +176,136 @@ static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, | |||
181 | return 0; | 176 | return 0; |
182 | } | 177 | } |
183 | 178 | ||
179 | /** | ||
180 | * r600_cs_packet_next_vline() - parse userspace VLINE packet | ||
181 | * @parser: parser structure holding parsing context. | ||
182 | * | ||
183 | * Userspace sends a special sequence for VLINE waits. | ||
184 | * PACKET0 - VLINE_START_END + value | ||
185 | * PACKET3 - WAIT_REG_MEM poll vline status reg | ||
186 | * RELOC (P3) - crtc_id in reloc. | ||
187 | * | ||
188 | * This function parses this and relocates the VLINE START END | ||
189 | * and WAIT_REG_MEM packets to the correct crtc. | ||
190 | * It also detects a switched off crtc and nulls out the | ||
191 | * wait in that case. | ||
192 | */ | ||
193 | static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p) | ||
194 | { | ||
195 | struct drm_mode_object *obj; | ||
196 | struct drm_crtc *crtc; | ||
197 | struct radeon_crtc *radeon_crtc; | ||
198 | struct radeon_cs_packet p3reloc, wait_reg_mem; | ||
199 | int crtc_id; | ||
200 | int r; | ||
201 | uint32_t header, h_idx, reg, wait_reg_mem_info; | ||
202 | volatile uint32_t *ib; | ||
203 | |||
204 | ib = p->ib->ptr; | ||
205 | |||
206 | /* parse the WAIT_REG_MEM */ | ||
207 | r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx); | ||
208 | if (r) | ||
209 | return r; | ||
210 | |||
211 | /* check its a WAIT_REG_MEM */ | ||
212 | if (wait_reg_mem.type != PACKET_TYPE3 || | ||
213 | wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { | ||
214 | DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n"); | ||
215 | r = -EINVAL; | ||
216 | return r; | ||
217 | } | ||
218 | |||
219 | wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); | ||
220 | /* bit 4 is reg (0) or mem (1) */ | ||
221 | if (wait_reg_mem_info & 0x10) { | ||
222 | DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n"); | ||
223 | r = -EINVAL; | ||
224 | return r; | ||
225 | } | ||
226 | /* waiting for value to be equal */ | ||
227 | if ((wait_reg_mem_info & 0x7) != 0x3) { | ||
228 | DRM_ERROR("vline WAIT_REG_MEM function not equal\n"); | ||
229 | r = -EINVAL; | ||
230 | return r; | ||
231 | } | ||
232 | if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) { | ||
233 | DRM_ERROR("vline WAIT_REG_MEM bad reg\n"); | ||
234 | r = -EINVAL; | ||
235 | return r; | ||
236 | } | ||
237 | |||
238 | if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) { | ||
239 | DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n"); | ||
240 | r = -EINVAL; | ||
241 | return r; | ||
242 | } | ||
243 | |||
244 | /* jump over the NOP */ | ||
245 | r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2); | ||
246 | if (r) | ||
247 | return r; | ||
248 | |||
249 | h_idx = p->idx - 2; | ||
250 | p->idx += wait_reg_mem.count + 2; | ||
251 | p->idx += p3reloc.count + 2; | ||
252 | |||
253 | header = radeon_get_ib_value(p, h_idx); | ||
254 | crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); | ||
255 | reg = header >> 2; | ||
256 | mutex_lock(&p->rdev->ddev->mode_config.mutex); | ||
257 | obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); | ||
258 | if (!obj) { | ||
259 | DRM_ERROR("cannot find crtc %d\n", crtc_id); | ||
260 | r = -EINVAL; | ||
261 | goto out; | ||
262 | } | ||
263 | crtc = obj_to_crtc(obj); | ||
264 | radeon_crtc = to_radeon_crtc(crtc); | ||
265 | crtc_id = radeon_crtc->crtc_id; | ||
266 | |||
267 | if (!crtc->enabled) { | ||
268 | /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */ | ||
269 | ib[h_idx + 2] = PACKET2(0); | ||
270 | ib[h_idx + 3] = PACKET2(0); | ||
271 | ib[h_idx + 4] = PACKET2(0); | ||
272 | ib[h_idx + 5] = PACKET2(0); | ||
273 | ib[h_idx + 6] = PACKET2(0); | ||
274 | ib[h_idx + 7] = PACKET2(0); | ||
275 | ib[h_idx + 8] = PACKET2(0); | ||
276 | } else if (crtc_id == 1) { | ||
277 | switch (reg) { | ||
278 | case AVIVO_D1MODE_VLINE_START_END: | ||
279 | header &= ~R600_CP_PACKET0_REG_MASK; | ||
280 | header |= AVIVO_D2MODE_VLINE_START_END >> 2; | ||
281 | break; | ||
282 | default: | ||
283 | DRM_ERROR("unknown crtc reloc\n"); | ||
284 | r = -EINVAL; | ||
285 | goto out; | ||
286 | } | ||
287 | ib[h_idx] = header; | ||
288 | ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2; | ||
289 | } | ||
290 | out: | ||
291 | mutex_unlock(&p->rdev->ddev->mode_config.mutex); | ||
292 | return r; | ||
293 | } | ||
294 | |||
184 | static int r600_packet0_check(struct radeon_cs_parser *p, | 295 | static int r600_packet0_check(struct radeon_cs_parser *p, |
185 | struct radeon_cs_packet *pkt, | 296 | struct radeon_cs_packet *pkt, |
186 | unsigned idx, unsigned reg) | 297 | unsigned idx, unsigned reg) |
187 | { | 298 | { |
299 | int r; | ||
300 | |||
188 | switch (reg) { | 301 | switch (reg) { |
189 | case AVIVO_D1MODE_VLINE_START_END: | 302 | case AVIVO_D1MODE_VLINE_START_END: |
190 | case AVIVO_D2MODE_VLINE_START_END: | 303 | r = r600_cs_packet_parse_vline(p); |
304 | if (r) { | ||
305 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | ||
306 | idx, reg); | ||
307 | return r; | ||
308 | } | ||
191 | break; | 309 | break; |
192 | default: | 310 | default: |
193 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", | 311 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", |
@@ -218,17 +336,18 @@ static int r600_cs_parse_packet0(struct radeon_cs_parser *p, | |||
218 | static int r600_packet3_check(struct radeon_cs_parser *p, | 336 | static int r600_packet3_check(struct radeon_cs_parser *p, |
219 | struct radeon_cs_packet *pkt) | 337 | struct radeon_cs_packet *pkt) |
220 | { | 338 | { |
221 | struct radeon_cs_chunk *ib_chunk; | ||
222 | struct radeon_cs_reloc *reloc; | 339 | struct radeon_cs_reloc *reloc; |
223 | volatile u32 *ib; | 340 | volatile u32 *ib; |
224 | unsigned idx; | 341 | unsigned idx; |
225 | unsigned i; | 342 | unsigned i; |
226 | unsigned start_reg, end_reg, reg; | 343 | unsigned start_reg, end_reg, reg; |
227 | int r; | 344 | int r; |
345 | u32 idx_value; | ||
228 | 346 | ||
229 | ib = p->ib->ptr; | 347 | ib = p->ib->ptr; |
230 | ib_chunk = &p->chunks[p->chunk_ib_idx]; | ||
231 | idx = pkt->idx + 1; | 348 | idx = pkt->idx + 1; |
349 | idx_value = radeon_get_ib_value(p, idx); | ||
350 | |||
232 | switch (pkt->opcode) { | 351 | switch (pkt->opcode) { |
233 | case PACKET3_START_3D_CMDBUF: | 352 | case PACKET3_START_3D_CMDBUF: |
234 | if (p->family >= CHIP_RV770 || pkt->count) { | 353 | if (p->family >= CHIP_RV770 || pkt->count) { |
@@ -259,8 +378,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
259 | DRM_ERROR("bad DRAW_INDEX\n"); | 378 | DRM_ERROR("bad DRAW_INDEX\n"); |
260 | return -EINVAL; | 379 | return -EINVAL; |
261 | } | 380 | } |
262 | ib[idx+0] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); | 381 | ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); |
263 | ib[idx+1] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | 382 | ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; |
264 | break; | 383 | break; |
265 | case PACKET3_DRAW_INDEX_AUTO: | 384 | case PACKET3_DRAW_INDEX_AUTO: |
266 | if (pkt->count != 1) { | 385 | if (pkt->count != 1) { |
@@ -281,14 +400,14 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
281 | return -EINVAL; | 400 | return -EINVAL; |
282 | } | 401 | } |
283 | /* bit 4 is reg (0) or mem (1) */ | 402 | /* bit 4 is reg (0) or mem (1) */ |
284 | if (ib_chunk->kdata[idx+0] & 0x10) { | 403 | if (idx_value & 0x10) { |
285 | r = r600_cs_packet_next_reloc(p, &reloc); | 404 | r = r600_cs_packet_next_reloc(p, &reloc); |
286 | if (r) { | 405 | if (r) { |
287 | DRM_ERROR("bad WAIT_REG_MEM\n"); | 406 | DRM_ERROR("bad WAIT_REG_MEM\n"); |
288 | return -EINVAL; | 407 | return -EINVAL; |
289 | } | 408 | } |
290 | ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); | 409 | ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); |
291 | ib[idx+2] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | 410 | ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; |
292 | } | 411 | } |
293 | break; | 412 | break; |
294 | case PACKET3_SURFACE_SYNC: | 413 | case PACKET3_SURFACE_SYNC: |
@@ -297,8 +416,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
297 | return -EINVAL; | 416 | return -EINVAL; |
298 | } | 417 | } |
299 | /* 0xffffffff/0x0 is flush all cache flag */ | 418 | /* 0xffffffff/0x0 is flush all cache flag */ |
300 | if (ib_chunk->kdata[idx+1] != 0xffffffff || | 419 | if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || |
301 | ib_chunk->kdata[idx+2] != 0) { | 420 | radeon_get_ib_value(p, idx + 2) != 0) { |
302 | r = r600_cs_packet_next_reloc(p, &reloc); | 421 | r = r600_cs_packet_next_reloc(p, &reloc); |
303 | if (r) { | 422 | if (r) { |
304 | DRM_ERROR("bad SURFACE_SYNC\n"); | 423 | DRM_ERROR("bad SURFACE_SYNC\n"); |
@@ -319,7 +438,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
319 | return -EINVAL; | 438 | return -EINVAL; |
320 | } | 439 | } |
321 | ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); | 440 | ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); |
322 | ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | 441 | ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; |
323 | } | 442 | } |
324 | break; | 443 | break; |
325 | case PACKET3_EVENT_WRITE_EOP: | 444 | case PACKET3_EVENT_WRITE_EOP: |
@@ -333,10 +452,10 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
333 | return -EINVAL; | 452 | return -EINVAL; |
334 | } | 453 | } |
335 | ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); | 454 | ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); |
336 | ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | 455 | ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; |
337 | break; | 456 | break; |
338 | case PACKET3_SET_CONFIG_REG: | 457 | case PACKET3_SET_CONFIG_REG: |
339 | start_reg = (ib[idx+0] << 2) + PACKET3_SET_CONFIG_REG_OFFSET; | 458 | start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET; |
340 | end_reg = 4 * pkt->count + start_reg - 4; | 459 | end_reg = 4 * pkt->count + start_reg - 4; |
341 | if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) || | 460 | if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) || |
342 | (start_reg >= PACKET3_SET_CONFIG_REG_END) || | 461 | (start_reg >= PACKET3_SET_CONFIG_REG_END) || |
@@ -356,7 +475,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
356 | } | 475 | } |
357 | break; | 476 | break; |
358 | case PACKET3_SET_CONTEXT_REG: | 477 | case PACKET3_SET_CONTEXT_REG: |
359 | start_reg = (ib[idx+0] << 2) + PACKET3_SET_CONTEXT_REG_OFFSET; | 478 | start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET; |
360 | end_reg = 4 * pkt->count + start_reg - 4; | 479 | end_reg = 4 * pkt->count + start_reg - 4; |
361 | if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) || | 480 | if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) || |
362 | (start_reg >= PACKET3_SET_CONTEXT_REG_END) || | 481 | (start_reg >= PACKET3_SET_CONTEXT_REG_END) || |
@@ -421,7 +540,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
421 | DRM_ERROR("bad SET_RESOURCE\n"); | 540 | DRM_ERROR("bad SET_RESOURCE\n"); |
422 | return -EINVAL; | 541 | return -EINVAL; |
423 | } | 542 | } |
424 | start_reg = (ib[idx+0] << 2) + PACKET3_SET_RESOURCE_OFFSET; | 543 | start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET; |
425 | end_reg = 4 * pkt->count + start_reg - 4; | 544 | end_reg = 4 * pkt->count + start_reg - 4; |
426 | if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) || | 545 | if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) || |
427 | (start_reg >= PACKET3_SET_RESOURCE_END) || | 546 | (start_reg >= PACKET3_SET_RESOURCE_END) || |
@@ -430,7 +549,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
430 | return -EINVAL; | 549 | return -EINVAL; |
431 | } | 550 | } |
432 | for (i = 0; i < (pkt->count / 7); i++) { | 551 | for (i = 0; i < (pkt->count / 7); i++) { |
433 | switch (G__SQ_VTX_CONSTANT_TYPE(ib[idx+(i*7)+6+1])) { | 552 | switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) { |
434 | case SQ_TEX_VTX_VALID_TEXTURE: | 553 | case SQ_TEX_VTX_VALID_TEXTURE: |
435 | /* tex base */ | 554 | /* tex base */ |
436 | r = r600_cs_packet_next_reloc(p, &reloc); | 555 | r = r600_cs_packet_next_reloc(p, &reloc); |
@@ -455,7 +574,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
455 | return -EINVAL; | 574 | return -EINVAL; |
456 | } | 575 | } |
457 | ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff); | 576 | ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff); |
458 | ib[idx+1+(i*7)+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff; | 577 | ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; |
459 | break; | 578 | break; |
460 | case SQ_TEX_VTX_INVALID_TEXTURE: | 579 | case SQ_TEX_VTX_INVALID_TEXTURE: |
461 | case SQ_TEX_VTX_INVALID_BUFFER: | 580 | case SQ_TEX_VTX_INVALID_BUFFER: |
@@ -466,7 +585,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
466 | } | 585 | } |
467 | break; | 586 | break; |
468 | case PACKET3_SET_ALU_CONST: | 587 | case PACKET3_SET_ALU_CONST: |
469 | start_reg = (ib[idx+0] << 2) + PACKET3_SET_ALU_CONST_OFFSET; | 588 | start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET; |
470 | end_reg = 4 * pkt->count + start_reg - 4; | 589 | end_reg = 4 * pkt->count + start_reg - 4; |
471 | if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) || | 590 | if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) || |
472 | (start_reg >= PACKET3_SET_ALU_CONST_END) || | 591 | (start_reg >= PACKET3_SET_ALU_CONST_END) || |
@@ -476,7 +595,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
476 | } | 595 | } |
477 | break; | 596 | break; |
478 | case PACKET3_SET_BOOL_CONST: | 597 | case PACKET3_SET_BOOL_CONST: |
479 | start_reg = (ib[idx+0] << 2) + PACKET3_SET_BOOL_CONST_OFFSET; | 598 | start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET; |
480 | end_reg = 4 * pkt->count + start_reg - 4; | 599 | end_reg = 4 * pkt->count + start_reg - 4; |
481 | if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) || | 600 | if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) || |
482 | (start_reg >= PACKET3_SET_BOOL_CONST_END) || | 601 | (start_reg >= PACKET3_SET_BOOL_CONST_END) || |
@@ -486,7 +605,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
486 | } | 605 | } |
487 | break; | 606 | break; |
488 | case PACKET3_SET_LOOP_CONST: | 607 | case PACKET3_SET_LOOP_CONST: |
489 | start_reg = (ib[idx+0] << 2) + PACKET3_SET_LOOP_CONST_OFFSET; | 608 | start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET; |
490 | end_reg = 4 * pkt->count + start_reg - 4; | 609 | end_reg = 4 * pkt->count + start_reg - 4; |
491 | if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) || | 610 | if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) || |
492 | (start_reg >= PACKET3_SET_LOOP_CONST_END) || | 611 | (start_reg >= PACKET3_SET_LOOP_CONST_END) || |
@@ -496,7 +615,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
496 | } | 615 | } |
497 | break; | 616 | break; |
498 | case PACKET3_SET_CTL_CONST: | 617 | case PACKET3_SET_CTL_CONST: |
499 | start_reg = (ib[idx+0] << 2) + PACKET3_SET_CTL_CONST_OFFSET; | 618 | start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET; |
500 | end_reg = 4 * pkt->count + start_reg - 4; | 619 | end_reg = 4 * pkt->count + start_reg - 4; |
501 | if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) || | 620 | if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) || |
502 | (start_reg >= PACKET3_SET_CTL_CONST_END) || | 621 | (start_reg >= PACKET3_SET_CTL_CONST_END) || |
@@ -510,7 +629,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
510 | DRM_ERROR("bad SET_SAMPLER\n"); | 629 | DRM_ERROR("bad SET_SAMPLER\n"); |
511 | return -EINVAL; | 630 | return -EINVAL; |
512 | } | 631 | } |
513 | start_reg = (ib[idx+0] << 2) + PACKET3_SET_SAMPLER_OFFSET; | 632 | start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET; |
514 | end_reg = 4 * pkt->count + start_reg - 4; | 633 | end_reg = 4 * pkt->count + start_reg - 4; |
515 | if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) || | 634 | if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) || |
516 | (start_reg >= PACKET3_SET_SAMPLER_END) || | 635 | (start_reg >= PACKET3_SET_SAMPLER_END) || |
@@ -602,6 +721,8 @@ static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error) | |||
602 | kfree(parser->relocs); | 721 | kfree(parser->relocs); |
603 | for (i = 0; i < parser->nchunks; i++) { | 722 | for (i = 0; i < parser->nchunks; i++) { |
604 | kfree(parser->chunks[i].kdata); | 723 | kfree(parser->chunks[i].kdata); |
724 | kfree(parser->chunks[i].kpage[0]); | ||
725 | kfree(parser->chunks[i].kpage[1]); | ||
605 | } | 726 | } |
606 | kfree(parser->chunks); | 727 | kfree(parser->chunks); |
607 | kfree(parser->chunks_array); | 728 | kfree(parser->chunks_array); |
@@ -639,7 +760,6 @@ int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, | |||
639 | * uncached). */ | 760 | * uncached). */ |
640 | ib_chunk = &parser.chunks[parser.chunk_ib_idx]; | 761 | ib_chunk = &parser.chunks[parser.chunk_ib_idx]; |
641 | parser.ib->length_dw = ib_chunk->length_dw; | 762 | parser.ib->length_dw = ib_chunk->length_dw; |
642 | memcpy((void *)parser.ib->ptr, ib_chunk->kdata, ib_chunk->length_dw*4); | ||
643 | *l = parser.ib->length_dw; | 763 | *l = parser.ib->length_dw; |
644 | r = r600_cs_parse(&parser); | 764 | r = r600_cs_parse(&parser); |
645 | if (r) { | 765 | if (r) { |
@@ -647,6 +767,12 @@ int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, | |||
647 | r600_cs_parser_fini(&parser, r); | 767 | r600_cs_parser_fini(&parser, r); |
648 | return r; | 768 | return r; |
649 | } | 769 | } |
770 | r = radeon_cs_finish_pages(&parser); | ||
771 | if (r) { | ||
772 | DRM_ERROR("Invalid command stream !\n"); | ||
773 | r600_cs_parser_fini(&parser, r); | ||
774 | return r; | ||
775 | } | ||
650 | r600_cs_parser_fini(&parser, r); | 776 | r600_cs_parser_fini(&parser, r); |
651 | return r; | 777 | return r; |
652 | } | 778 | } |
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 6311b1362594..950b346e343f 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -44,6 +44,24 @@ | |||
44 | * - TESTING, TESTING, TESTING | 44 | * - TESTING, TESTING, TESTING |
45 | */ | 45 | */ |
46 | 46 | ||
47 | /* Initialization path: | ||
48 | * We expect that acceleration initialization might fail for various | ||
49 | * reasons even thought we work hard to make it works on most | ||
50 | * configurations. In order to still have a working userspace in such | ||
51 | * situation the init path must succeed up to the memory controller | ||
52 | * initialization point. Failure before this point are considered as | ||
53 | * fatal error. Here is the init callchain : | ||
54 | * radeon_device_init perform common structure, mutex initialization | ||
55 | * asic_init setup the GPU memory layout and perform all | ||
56 | * one time initialization (failure in this | ||
57 | * function are considered fatal) | ||
58 | * asic_startup setup the GPU acceleration, in order to | ||
59 | * follow guideline the first thing this | ||
60 | * function should do is setting the GPU | ||
61 | * memory controller (only MC setup failure | ||
62 | * are considered as fatal) | ||
63 | */ | ||
64 | |||
47 | #include <asm/atomic.h> | 65 | #include <asm/atomic.h> |
48 | #include <linux/wait.h> | 66 | #include <linux/wait.h> |
49 | #include <linux/list.h> | 67 | #include <linux/list.h> |
@@ -342,7 +360,7 @@ struct radeon_ib { | |||
342 | unsigned long idx; | 360 | unsigned long idx; |
343 | uint64_t gpu_addr; | 361 | uint64_t gpu_addr; |
344 | struct radeon_fence *fence; | 362 | struct radeon_fence *fence; |
345 | volatile uint32_t *ptr; | 363 | uint32_t *ptr; |
346 | uint32_t length_dw; | 364 | uint32_t length_dw; |
347 | }; | 365 | }; |
348 | 366 | ||
@@ -415,7 +433,12 @@ struct radeon_cs_reloc { | |||
415 | struct radeon_cs_chunk { | 433 | struct radeon_cs_chunk { |
416 | uint32_t chunk_id; | 434 | uint32_t chunk_id; |
417 | uint32_t length_dw; | 435 | uint32_t length_dw; |
436 | int kpage_idx[2]; | ||
437 | uint32_t *kpage[2]; | ||
418 | uint32_t *kdata; | 438 | uint32_t *kdata; |
439 | void __user *user_ptr; | ||
440 | int last_copied_page; | ||
441 | int last_page_index; | ||
419 | }; | 442 | }; |
420 | 443 | ||
421 | struct radeon_cs_parser { | 444 | struct radeon_cs_parser { |
@@ -438,8 +461,38 @@ struct radeon_cs_parser { | |||
438 | struct radeon_ib *ib; | 461 | struct radeon_ib *ib; |
439 | void *track; | 462 | void *track; |
440 | unsigned family; | 463 | unsigned family; |
464 | int parser_error; | ||
441 | }; | 465 | }; |
442 | 466 | ||
467 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); | ||
468 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); | ||
469 | |||
470 | |||
471 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) | ||
472 | { | ||
473 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | ||
474 | u32 pg_idx, pg_offset; | ||
475 | u32 idx_value = 0; | ||
476 | int new_page; | ||
477 | |||
478 | pg_idx = (idx * 4) / PAGE_SIZE; | ||
479 | pg_offset = (idx * 4) % PAGE_SIZE; | ||
480 | |||
481 | if (ibc->kpage_idx[0] == pg_idx) | ||
482 | return ibc->kpage[0][pg_offset/4]; | ||
483 | if (ibc->kpage_idx[1] == pg_idx) | ||
484 | return ibc->kpage[1][pg_offset/4]; | ||
485 | |||
486 | new_page = radeon_cs_update_pages(p, pg_idx); | ||
487 | if (new_page < 0) { | ||
488 | p->parser_error = new_page; | ||
489 | return 0; | ||
490 | } | ||
491 | |||
492 | idx_value = ibc->kpage[new_page][pg_offset/4]; | ||
493 | return idx_value; | ||
494 | } | ||
495 | |||
443 | struct radeon_cs_packet { | 496 | struct radeon_cs_packet { |
444 | unsigned idx; | 497 | unsigned idx; |
445 | unsigned type; | 498 | unsigned type; |
@@ -943,6 +996,7 @@ extern void radeon_clocks_fini(struct radeon_device *rdev); | |||
943 | extern void radeon_scratch_init(struct radeon_device *rdev); | 996 | extern void radeon_scratch_init(struct radeon_device *rdev); |
944 | extern void radeon_surface_init(struct radeon_device *rdev); | 997 | extern void radeon_surface_init(struct radeon_device *rdev); |
945 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); | 998 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
999 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); | ||
946 | 1000 | ||
947 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ | 1001 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
948 | struct r100_mc_save { | 1002 | struct r100_mc_save { |
@@ -974,6 +1028,9 @@ extern void r100_vram_init_sizes(struct radeon_device *rdev); | |||
974 | extern void r100_wb_disable(struct radeon_device *rdev); | 1028 | extern void r100_wb_disable(struct radeon_device *rdev); |
975 | extern void r100_wb_fini(struct radeon_device *rdev); | 1029 | extern void r100_wb_fini(struct radeon_device *rdev); |
976 | extern int r100_wb_init(struct radeon_device *rdev); | 1030 | extern int r100_wb_init(struct radeon_device *rdev); |
1031 | extern void r100_hdp_reset(struct radeon_device *rdev); | ||
1032 | extern int r100_rb2d_reset(struct radeon_device *rdev); | ||
1033 | extern int r100_cp_reset(struct radeon_device *rdev); | ||
977 | 1034 | ||
978 | /* r300,r350,rv350,rv370,rv380 */ | 1035 | /* r300,r350,rv350,rv370,rv380 */ |
979 | extern void r300_set_reg_safe(struct radeon_device *rdev); | 1036 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
@@ -985,12 +1042,29 @@ extern int rv370_pcie_gart_enable(struct radeon_device *rdev); | |||
985 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); | 1042 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
986 | 1043 | ||
987 | /* r420,r423,rv410 */ | 1044 | /* r420,r423,rv410 */ |
1045 | extern int r420_mc_init(struct radeon_device *rdev); | ||
988 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); | 1046 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
989 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); | 1047 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
990 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); | 1048 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
1049 | extern void r420_pipes_init(struct radeon_device *rdev); | ||
991 | 1050 | ||
992 | /* rv515 */ | 1051 | /* rv515 */ |
1052 | struct rv515_mc_save { | ||
1053 | u32 d1vga_control; | ||
1054 | u32 d2vga_control; | ||
1055 | u32 vga_render_control; | ||
1056 | u32 vga_hdp_control; | ||
1057 | u32 d1crtc_control; | ||
1058 | u32 d2crtc_control; | ||
1059 | }; | ||
993 | extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); | 1060 | extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
1061 | extern void rv515_vga_render_disable(struct radeon_device *rdev); | ||
1062 | extern void rv515_set_safe_registers(struct radeon_device *rdev); | ||
1063 | extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); | ||
1064 | extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); | ||
1065 | extern void rv515_clock_startup(struct radeon_device *rdev); | ||
1066 | extern void rv515_debugfs(struct radeon_device *rdev); | ||
1067 | extern int rv515_suspend(struct radeon_device *rdev); | ||
994 | 1068 | ||
995 | /* rs690, rs740 */ | 1069 | /* rs690, rs740 */ |
996 | extern void rs690_line_buffer_adjust(struct radeon_device *rdev, | 1070 | extern void rs690_line_buffer_adjust(struct radeon_device *rdev, |
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 8968f78fa1e3..c8a4e7b5663d 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h | |||
@@ -420,41 +420,43 @@ static struct radeon_asic rs690_asic = { | |||
420 | * rv515 | 420 | * rv515 |
421 | */ | 421 | */ |
422 | int rv515_init(struct radeon_device *rdev); | 422 | int rv515_init(struct radeon_device *rdev); |
423 | void rv515_errata(struct radeon_device *rdev); | 423 | void rv515_fini(struct radeon_device *rdev); |
424 | void rv515_vram_info(struct radeon_device *rdev); | ||
425 | int rv515_gpu_reset(struct radeon_device *rdev); | 424 | int rv515_gpu_reset(struct radeon_device *rdev); |
426 | int rv515_mc_init(struct radeon_device *rdev); | ||
427 | void rv515_mc_fini(struct radeon_device *rdev); | ||
428 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); | 425 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
429 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | 426 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
430 | void rv515_ring_start(struct radeon_device *rdev); | 427 | void rv515_ring_start(struct radeon_device *rdev); |
431 | uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); | 428 | uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
432 | void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | 429 | void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
433 | void rv515_bandwidth_update(struct radeon_device *rdev); | 430 | void rv515_bandwidth_update(struct radeon_device *rdev); |
431 | int rv515_resume(struct radeon_device *rdev); | ||
432 | int rv515_suspend(struct radeon_device *rdev); | ||
434 | static struct radeon_asic rv515_asic = { | 433 | static struct radeon_asic rv515_asic = { |
435 | .init = &rv515_init, | 434 | .init = &rv515_init, |
436 | .errata = &rv515_errata, | 435 | .fini = &rv515_fini, |
437 | .vram_info = &rv515_vram_info, | 436 | .suspend = &rv515_suspend, |
437 | .resume = &rv515_resume, | ||
438 | .errata = NULL, | ||
439 | .vram_info = NULL, | ||
438 | .vga_set_state = &r100_vga_set_state, | 440 | .vga_set_state = &r100_vga_set_state, |
439 | .gpu_reset = &rv515_gpu_reset, | 441 | .gpu_reset = &rv515_gpu_reset, |
440 | .mc_init = &rv515_mc_init, | 442 | .mc_init = NULL, |
441 | .mc_fini = &rv515_mc_fini, | 443 | .mc_fini = NULL, |
442 | .wb_init = &r100_wb_init, | 444 | .wb_init = NULL, |
443 | .wb_fini = &r100_wb_fini, | 445 | .wb_fini = NULL, |
444 | .gart_init = &rv370_pcie_gart_init, | 446 | .gart_init = &rv370_pcie_gart_init, |
445 | .gart_fini = &rv370_pcie_gart_fini, | 447 | .gart_fini = &rv370_pcie_gart_fini, |
446 | .gart_enable = &rv370_pcie_gart_enable, | 448 | .gart_enable = NULL, |
447 | .gart_disable = &rv370_pcie_gart_disable, | 449 | .gart_disable = NULL, |
448 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, | 450 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
449 | .gart_set_page = &rv370_pcie_gart_set_page, | 451 | .gart_set_page = &rv370_pcie_gart_set_page, |
450 | .cp_init = &r100_cp_init, | 452 | .cp_init = NULL, |
451 | .cp_fini = &r100_cp_fini, | 453 | .cp_fini = NULL, |
452 | .cp_disable = &r100_cp_disable, | 454 | .cp_disable = NULL, |
453 | .cp_commit = &r100_cp_commit, | 455 | .cp_commit = &r100_cp_commit, |
454 | .ring_start = &rv515_ring_start, | 456 | .ring_start = &rv515_ring_start, |
455 | .ring_test = &r100_ring_test, | 457 | .ring_test = &r100_ring_test, |
456 | .ring_ib_execute = &r100_ring_ib_execute, | 458 | .ring_ib_execute = &r100_ring_ib_execute, |
457 | .ib_test = &r100_ib_test, | 459 | .ib_test = NULL, |
458 | .irq_set = &rs600_irq_set, | 460 | .irq_set = &rs600_irq_set, |
459 | .irq_process = &rs600_irq_process, | 461 | .irq_process = &rs600_irq_process, |
460 | .get_vblank_counter = &rs600_get_vblank_counter, | 462 | .get_vblank_counter = &rs600_get_vblank_counter, |
@@ -476,35 +478,35 @@ static struct radeon_asic rv515_asic = { | |||
476 | /* | 478 | /* |
477 | * r520,rv530,rv560,rv570,r580 | 479 | * r520,rv530,rv560,rv570,r580 |
478 | */ | 480 | */ |
479 | void r520_errata(struct radeon_device *rdev); | 481 | int r520_init(struct radeon_device *rdev); |
480 | void r520_vram_info(struct radeon_device *rdev); | 482 | int r520_resume(struct radeon_device *rdev); |
481 | int r520_mc_init(struct radeon_device *rdev); | ||
482 | void r520_mc_fini(struct radeon_device *rdev); | ||
483 | void r520_bandwidth_update(struct radeon_device *rdev); | ||
484 | static struct radeon_asic r520_asic = { | 483 | static struct radeon_asic r520_asic = { |
485 | .init = &rv515_init, | 484 | .init = &r520_init, |
486 | .errata = &r520_errata, | 485 | .fini = &rv515_fini, |
487 | .vram_info = &r520_vram_info, | 486 | .suspend = &rv515_suspend, |
487 | .resume = &r520_resume, | ||
488 | .errata = NULL, | ||
489 | .vram_info = NULL, | ||
488 | .vga_set_state = &r100_vga_set_state, | 490 | .vga_set_state = &r100_vga_set_state, |
489 | .gpu_reset = &rv515_gpu_reset, | 491 | .gpu_reset = &rv515_gpu_reset, |
490 | .mc_init = &r520_mc_init, | 492 | .mc_init = NULL, |
491 | .mc_fini = &r520_mc_fini, | 493 | .mc_fini = NULL, |
492 | .wb_init = &r100_wb_init, | 494 | .wb_init = NULL, |
493 | .wb_fini = &r100_wb_fini, | 495 | .wb_fini = NULL, |
494 | .gart_init = &rv370_pcie_gart_init, | 496 | .gart_init = NULL, |
495 | .gart_fini = &rv370_pcie_gart_fini, | 497 | .gart_fini = NULL, |
496 | .gart_enable = &rv370_pcie_gart_enable, | 498 | .gart_enable = NULL, |
497 | .gart_disable = &rv370_pcie_gart_disable, | 499 | .gart_disable = NULL, |
498 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, | 500 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
499 | .gart_set_page = &rv370_pcie_gart_set_page, | 501 | .gart_set_page = &rv370_pcie_gart_set_page, |
500 | .cp_init = &r100_cp_init, | 502 | .cp_init = NULL, |
501 | .cp_fini = &r100_cp_fini, | 503 | .cp_fini = NULL, |
502 | .cp_disable = &r100_cp_disable, | 504 | .cp_disable = NULL, |
503 | .cp_commit = &r100_cp_commit, | 505 | .cp_commit = &r100_cp_commit, |
504 | .ring_start = &rv515_ring_start, | 506 | .ring_start = &rv515_ring_start, |
505 | .ring_test = &r100_ring_test, | 507 | .ring_test = &r100_ring_test, |
506 | .ring_ib_execute = &r100_ring_ib_execute, | 508 | .ring_ib_execute = &r100_ring_ib_execute, |
507 | .ib_test = &r100_ib_test, | 509 | .ib_test = NULL, |
508 | .irq_set = &rs600_irq_set, | 510 | .irq_set = &rs600_irq_set, |
509 | .irq_process = &rs600_irq_process, | 511 | .irq_process = &rs600_irq_process, |
510 | .get_vblank_counter = &rs600_get_vblank_counter, | 512 | .get_vblank_counter = &rs600_get_vblank_counter, |
@@ -519,7 +521,7 @@ static struct radeon_asic r520_asic = { | |||
519 | .set_clock_gating = &radeon_atom_set_clock_gating, | 521 | .set_clock_gating = &radeon_atom_set_clock_gating, |
520 | .set_surface_reg = r100_set_surface_reg, | 522 | .set_surface_reg = r100_set_surface_reg, |
521 | .clear_surface_reg = r100_clear_surface_reg, | 523 | .clear_surface_reg = r100_clear_surface_reg, |
522 | .bandwidth_update = &r520_bandwidth_update, | 524 | .bandwidth_update = &rv515_bandwidth_update, |
523 | }; | 525 | }; |
524 | 526 | ||
525 | /* | 527 | /* |
@@ -596,7 +598,7 @@ static struct radeon_asic r600_asic = { | |||
596 | .set_clock_gating = &radeon_atom_set_clock_gating, | 598 | .set_clock_gating = &radeon_atom_set_clock_gating, |
597 | .set_surface_reg = r600_set_surface_reg, | 599 | .set_surface_reg = r600_set_surface_reg, |
598 | .clear_surface_reg = r600_clear_surface_reg, | 600 | .clear_surface_reg = r600_clear_surface_reg, |
599 | .bandwidth_update = &r520_bandwidth_update, | 601 | .bandwidth_update = &rv515_bandwidth_update, |
600 | }; | 602 | }; |
601 | 603 | ||
602 | /* | 604 | /* |
@@ -646,7 +648,7 @@ static struct radeon_asic rv770_asic = { | |||
646 | .set_clock_gating = &radeon_atom_set_clock_gating, | 648 | .set_clock_gating = &radeon_atom_set_clock_gating, |
647 | .set_surface_reg = r600_set_surface_reg, | 649 | .set_surface_reg = r600_set_surface_reg, |
648 | .clear_surface_reg = r600_clear_surface_reg, | 650 | .clear_surface_reg = r600_clear_surface_reg, |
649 | .bandwidth_update = &r520_bandwidth_update, | 651 | .bandwidth_update = &rv515_bandwidth_update, |
650 | }; | 652 | }; |
651 | 653 | ||
652 | #endif | 654 | #endif |
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index 743742128307..5b6c08cee40e 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c | |||
@@ -272,12 +272,9 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) | |||
272 | (le16_to_cpu(path->usConnObjectId) & | 272 | (le16_to_cpu(path->usConnObjectId) & |
273 | OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; | 273 | OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; |
274 | 274 | ||
275 | if ((le16_to_cpu(path->usDeviceTag) == | 275 | /* TODO CV support */ |
276 | ATOM_DEVICE_TV1_SUPPORT) | 276 | if (le16_to_cpu(path->usDeviceTag) == |
277 | || (le16_to_cpu(path->usDeviceTag) == | 277 | ATOM_DEVICE_CV_SUPPORT) |
278 | ATOM_DEVICE_TV2_SUPPORT) | ||
279 | || (le16_to_cpu(path->usDeviceTag) == | ||
280 | ATOM_DEVICE_CV_SUPPORT)) | ||
281 | continue; | 278 | continue; |
282 | 279 | ||
283 | if ((rdev->family == CHIP_RS780) && | 280 | if ((rdev->family == CHIP_RS780) && |
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c index af1d551f1a8f..e376be47a4a0 100644 --- a/drivers/gpu/drm/radeon/radeon_connectors.c +++ b/drivers/gpu/drm/radeon/radeon_connectors.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include "drmP.h" | 26 | #include "drmP.h" |
27 | #include "drm_edid.h" | 27 | #include "drm_edid.h" |
28 | #include "drm_crtc_helper.h" | 28 | #include "drm_crtc_helper.h" |
29 | #include "drm_fb_helper.h" | ||
29 | #include "radeon_drm.h" | 30 | #include "radeon_drm.h" |
30 | #include "radeon.h" | 31 | #include "radeon.h" |
31 | #include "atom.h" | 32 | #include "atom.h" |
@@ -245,7 +246,7 @@ static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_conn | |||
245 | if (common_modes[i].w < 320 || common_modes[i].h < 200) | 246 | if (common_modes[i].w < 320 || common_modes[i].h < 200) |
246 | continue; | 247 | continue; |
247 | 248 | ||
248 | mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false); | 249 | mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); |
249 | drm_mode_probed_add(connector, mode); | 250 | drm_mode_probed_add(connector, mode); |
250 | } | 251 | } |
251 | } | 252 | } |
@@ -559,7 +560,7 @@ static int radeon_tv_get_modes(struct drm_connector *connector) | |||
559 | radeon_add_common_modes(encoder, connector); | 560 | radeon_add_common_modes(encoder, connector); |
560 | else { | 561 | else { |
561 | /* only 800x600 is supported right now on pre-avivo chips */ | 562 | /* only 800x600 is supported right now on pre-avivo chips */ |
562 | tv_mode = drm_cvt_mode(dev, 800, 600, 60, false, false); | 563 | tv_mode = drm_cvt_mode(dev, 800, 600, 60, false, false, false); |
563 | tv_mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; | 564 | tv_mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; |
564 | drm_mode_probed_add(connector, tv_mode); | 565 | drm_mode_probed_add(connector, tv_mode); |
565 | } | 566 | } |
@@ -743,6 +744,15 @@ struct drm_encoder *radeon_dvi_encoder(struct drm_connector *connector) | |||
743 | return NULL; | 744 | return NULL; |
744 | } | 745 | } |
745 | 746 | ||
747 | static void radeon_dvi_force(struct drm_connector *connector) | ||
748 | { | ||
749 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | ||
750 | if (connector->force == DRM_FORCE_ON) | ||
751 | radeon_connector->use_digital = false; | ||
752 | if (connector->force == DRM_FORCE_ON_DIGITAL) | ||
753 | radeon_connector->use_digital = true; | ||
754 | } | ||
755 | |||
746 | struct drm_connector_helper_funcs radeon_dvi_connector_helper_funcs = { | 756 | struct drm_connector_helper_funcs radeon_dvi_connector_helper_funcs = { |
747 | .get_modes = radeon_dvi_get_modes, | 757 | .get_modes = radeon_dvi_get_modes, |
748 | .mode_valid = radeon_vga_mode_valid, | 758 | .mode_valid = radeon_vga_mode_valid, |
@@ -755,6 +765,7 @@ struct drm_connector_funcs radeon_dvi_connector_funcs = { | |||
755 | .fill_modes = drm_helper_probe_single_connector_modes, | 765 | .fill_modes = drm_helper_probe_single_connector_modes, |
756 | .set_property = radeon_connector_set_property, | 766 | .set_property = radeon_connector_set_property, |
757 | .destroy = radeon_connector_destroy, | 767 | .destroy = radeon_connector_destroy, |
768 | .force = radeon_dvi_force, | ||
758 | }; | 769 | }; |
759 | 770 | ||
760 | void | 771 | void |
@@ -771,6 +782,7 @@ radeon_add_atom_connector(struct drm_device *dev, | |||
771 | struct radeon_connector *radeon_connector; | 782 | struct radeon_connector *radeon_connector; |
772 | struct radeon_connector_atom_dig *radeon_dig_connector; | 783 | struct radeon_connector_atom_dig *radeon_dig_connector; |
773 | uint32_t subpixel_order = SubPixelNone; | 784 | uint32_t subpixel_order = SubPixelNone; |
785 | int ret; | ||
774 | 786 | ||
775 | /* fixme - tv/cv/din */ | 787 | /* fixme - tv/cv/din */ |
776 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) | 788 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) |
@@ -796,24 +808,30 @@ radeon_add_atom_connector(struct drm_device *dev, | |||
796 | switch (connector_type) { | 808 | switch (connector_type) { |
797 | case DRM_MODE_CONNECTOR_VGA: | 809 | case DRM_MODE_CONNECTOR_VGA: |
798 | drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); | 810 | drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); |
799 | drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); | 811 | ret = drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); |
812 | if (ret) | ||
813 | goto failed; | ||
800 | if (i2c_bus->valid) { | 814 | if (i2c_bus->valid) { |
801 | radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "VGA"); | 815 | radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "VGA"); |
802 | if (!radeon_connector->ddc_bus) | 816 | if (!radeon_connector->ddc_bus) |
803 | goto failed; | 817 | goto failed; |
804 | } | 818 | } |
819 | radeon_connector->dac_load_detect = true; | ||
805 | drm_connector_attach_property(&radeon_connector->base, | 820 | drm_connector_attach_property(&radeon_connector->base, |
806 | rdev->mode_info.load_detect_property, | 821 | rdev->mode_info.load_detect_property, |
807 | 1); | 822 | 1); |
808 | break; | 823 | break; |
809 | case DRM_MODE_CONNECTOR_DVIA: | 824 | case DRM_MODE_CONNECTOR_DVIA: |
810 | drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); | 825 | drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); |
811 | drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); | 826 | ret = drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); |
827 | if (ret) | ||
828 | goto failed; | ||
812 | if (i2c_bus->valid) { | 829 | if (i2c_bus->valid) { |
813 | radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); | 830 | radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); |
814 | if (!radeon_connector->ddc_bus) | 831 | if (!radeon_connector->ddc_bus) |
815 | goto failed; | 832 | goto failed; |
816 | } | 833 | } |
834 | radeon_connector->dac_load_detect = true; | ||
817 | drm_connector_attach_property(&radeon_connector->base, | 835 | drm_connector_attach_property(&radeon_connector->base, |
818 | rdev->mode_info.load_detect_property, | 836 | rdev->mode_info.load_detect_property, |
819 | 1); | 837 | 1); |
@@ -827,7 +845,9 @@ radeon_add_atom_connector(struct drm_device *dev, | |||
827 | radeon_dig_connector->igp_lane_info = igp_lane_info; | 845 | radeon_dig_connector->igp_lane_info = igp_lane_info; |
828 | radeon_connector->con_priv = radeon_dig_connector; | 846 | radeon_connector->con_priv = radeon_dig_connector; |
829 | drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); | 847 | drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); |
830 | drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); | 848 | ret = drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); |
849 | if (ret) | ||
850 | goto failed; | ||
831 | if (i2c_bus->valid) { | 851 | if (i2c_bus->valid) { |
832 | radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); | 852 | radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); |
833 | if (!radeon_connector->ddc_bus) | 853 | if (!radeon_connector->ddc_bus) |
@@ -837,6 +857,7 @@ radeon_add_atom_connector(struct drm_device *dev, | |||
837 | drm_connector_attach_property(&radeon_connector->base, | 857 | drm_connector_attach_property(&radeon_connector->base, |
838 | rdev->mode_info.coherent_mode_property, | 858 | rdev->mode_info.coherent_mode_property, |
839 | 1); | 859 | 1); |
860 | radeon_connector->dac_load_detect = true; | ||
840 | drm_connector_attach_property(&radeon_connector->base, | 861 | drm_connector_attach_property(&radeon_connector->base, |
841 | rdev->mode_info.load_detect_property, | 862 | rdev->mode_info.load_detect_property, |
842 | 1); | 863 | 1); |
@@ -850,7 +871,9 @@ radeon_add_atom_connector(struct drm_device *dev, | |||
850 | radeon_dig_connector->igp_lane_info = igp_lane_info; | 871 | radeon_dig_connector->igp_lane_info = igp_lane_info; |
851 | radeon_connector->con_priv = radeon_dig_connector; | 872 | radeon_connector->con_priv = radeon_dig_connector; |
852 | drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); | 873 | drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); |
853 | drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); | 874 | ret = drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); |
875 | if (ret) | ||
876 | goto failed; | ||
854 | if (i2c_bus->valid) { | 877 | if (i2c_bus->valid) { |
855 | radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "HDMI"); | 878 | radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "HDMI"); |
856 | if (!radeon_connector->ddc_bus) | 879 | if (!radeon_connector->ddc_bus) |
@@ -869,7 +892,9 @@ radeon_add_atom_connector(struct drm_device *dev, | |||
869 | radeon_dig_connector->igp_lane_info = igp_lane_info; | 892 | radeon_dig_connector->igp_lane_info = igp_lane_info; |
870 | radeon_connector->con_priv = radeon_dig_connector; | 893 | radeon_connector->con_priv = radeon_dig_connector; |
871 | drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); | 894 | drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); |
872 | drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); | 895 | ret = drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); |
896 | if (ret) | ||
897 | goto failed; | ||
873 | if (i2c_bus->valid) { | 898 | if (i2c_bus->valid) { |
874 | radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DP"); | 899 | radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DP"); |
875 | if (!radeon_connector->ddc_bus) | 900 | if (!radeon_connector->ddc_bus) |
@@ -882,11 +907,14 @@ radeon_add_atom_connector(struct drm_device *dev, | |||
882 | case DRM_MODE_CONNECTOR_9PinDIN: | 907 | case DRM_MODE_CONNECTOR_9PinDIN: |
883 | if (radeon_tv == 1) { | 908 | if (radeon_tv == 1) { |
884 | drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); | 909 | drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); |
885 | drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); | 910 | ret = drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); |
911 | if (ret) | ||
912 | goto failed; | ||
913 | radeon_connector->dac_load_detect = true; | ||
914 | drm_connector_attach_property(&radeon_connector->base, | ||
915 | rdev->mode_info.load_detect_property, | ||
916 | 1); | ||
886 | } | 917 | } |
887 | drm_connector_attach_property(&radeon_connector->base, | ||
888 | rdev->mode_info.load_detect_property, | ||
889 | 1); | ||
890 | break; | 918 | break; |
891 | case DRM_MODE_CONNECTOR_LVDS: | 919 | case DRM_MODE_CONNECTOR_LVDS: |
892 | radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); | 920 | radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); |
@@ -896,7 +924,9 @@ radeon_add_atom_connector(struct drm_device *dev, | |||
896 | radeon_dig_connector->igp_lane_info = igp_lane_info; | 924 | radeon_dig_connector->igp_lane_info = igp_lane_info; |
897 | radeon_connector->con_priv = radeon_dig_connector; | 925 | radeon_connector->con_priv = radeon_dig_connector; |
898 | drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); | 926 | drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); |
899 | drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); | 927 | ret = drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); |
928 | if (ret) | ||
929 | goto failed; | ||
900 | if (i2c_bus->valid) { | 930 | if (i2c_bus->valid) { |
901 | radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "LVDS"); | 931 | radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "LVDS"); |
902 | if (!radeon_connector->ddc_bus) | 932 | if (!radeon_connector->ddc_bus) |
@@ -932,6 +962,7 @@ radeon_add_legacy_connector(struct drm_device *dev, | |||
932 | struct drm_connector *connector; | 962 | struct drm_connector *connector; |
933 | struct radeon_connector *radeon_connector; | 963 | struct radeon_connector *radeon_connector; |
934 | uint32_t subpixel_order = SubPixelNone; | 964 | uint32_t subpixel_order = SubPixelNone; |
965 | int ret; | ||
935 | 966 | ||
936 | /* fixme - tv/cv/din */ | 967 | /* fixme - tv/cv/din */ |
937 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) | 968 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) |
@@ -957,24 +988,30 @@ radeon_add_legacy_connector(struct drm_device *dev, | |||
957 | switch (connector_type) { | 988 | switch (connector_type) { |
958 | case DRM_MODE_CONNECTOR_VGA: | 989 | case DRM_MODE_CONNECTOR_VGA: |
959 | drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); | 990 | drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); |
960 | drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); | 991 | ret = drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); |
992 | if (ret) | ||
993 | goto failed; | ||
961 | if (i2c_bus->valid) { | 994 | if (i2c_bus->valid) { |
962 | radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "VGA"); | 995 | radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "VGA"); |
963 | if (!radeon_connector->ddc_bus) | 996 | if (!radeon_connector->ddc_bus) |
964 | goto failed; | 997 | goto failed; |
965 | } | 998 | } |
999 | radeon_connector->dac_load_detect = true; | ||
966 | drm_connector_attach_property(&radeon_connector->base, | 1000 | drm_connector_attach_property(&radeon_connector->base, |
967 | rdev->mode_info.load_detect_property, | 1001 | rdev->mode_info.load_detect_property, |
968 | 1); | 1002 | 1); |
969 | break; | 1003 | break; |
970 | case DRM_MODE_CONNECTOR_DVIA: | 1004 | case DRM_MODE_CONNECTOR_DVIA: |
971 | drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); | 1005 | drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); |
972 | drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); | 1006 | ret = drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); |
1007 | if (ret) | ||
1008 | goto failed; | ||
973 | if (i2c_bus->valid) { | 1009 | if (i2c_bus->valid) { |
974 | radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); | 1010 | radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); |
975 | if (!radeon_connector->ddc_bus) | 1011 | if (!radeon_connector->ddc_bus) |
976 | goto failed; | 1012 | goto failed; |
977 | } | 1013 | } |
1014 | radeon_connector->dac_load_detect = true; | ||
978 | drm_connector_attach_property(&radeon_connector->base, | 1015 | drm_connector_attach_property(&radeon_connector->base, |
979 | rdev->mode_info.load_detect_property, | 1016 | rdev->mode_info.load_detect_property, |
980 | 1); | 1017 | 1); |
@@ -982,11 +1019,14 @@ radeon_add_legacy_connector(struct drm_device *dev, | |||
982 | case DRM_MODE_CONNECTOR_DVII: | 1019 | case DRM_MODE_CONNECTOR_DVII: |
983 | case DRM_MODE_CONNECTOR_DVID: | 1020 | case DRM_MODE_CONNECTOR_DVID: |
984 | drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); | 1021 | drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); |
985 | drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); | 1022 | ret = drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); |
1023 | if (ret) | ||
1024 | goto failed; | ||
986 | if (i2c_bus->valid) { | 1025 | if (i2c_bus->valid) { |
987 | radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); | 1026 | radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); |
988 | if (!radeon_connector->ddc_bus) | 1027 | if (!radeon_connector->ddc_bus) |
989 | goto failed; | 1028 | goto failed; |
1029 | radeon_connector->dac_load_detect = true; | ||
990 | drm_connector_attach_property(&radeon_connector->base, | 1030 | drm_connector_attach_property(&radeon_connector->base, |
991 | rdev->mode_info.load_detect_property, | 1031 | rdev->mode_info.load_detect_property, |
992 | 1); | 1032 | 1); |
@@ -998,7 +1038,10 @@ radeon_add_legacy_connector(struct drm_device *dev, | |||
998 | case DRM_MODE_CONNECTOR_9PinDIN: | 1038 | case DRM_MODE_CONNECTOR_9PinDIN: |
999 | if (radeon_tv == 1) { | 1039 | if (radeon_tv == 1) { |
1000 | drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); | 1040 | drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); |
1001 | drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); | 1041 | ret = drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); |
1042 | if (ret) | ||
1043 | goto failed; | ||
1044 | radeon_connector->dac_load_detect = true; | ||
1002 | drm_connector_attach_property(&radeon_connector->base, | 1045 | drm_connector_attach_property(&radeon_connector->base, |
1003 | rdev->mode_info.load_detect_property, | 1046 | rdev->mode_info.load_detect_property, |
1004 | 1); | 1047 | 1); |
@@ -1006,7 +1049,9 @@ radeon_add_legacy_connector(struct drm_device *dev, | |||
1006 | break; | 1049 | break; |
1007 | case DRM_MODE_CONNECTOR_LVDS: | 1050 | case DRM_MODE_CONNECTOR_LVDS: |
1008 | drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); | 1051 | drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); |
1009 | drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); | 1052 | ret = drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); |
1053 | if (ret) | ||
1054 | goto failed; | ||
1010 | if (i2c_bus->valid) { | 1055 | if (i2c_bus->valid) { |
1011 | radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "LVDS"); | 1056 | radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "LVDS"); |
1012 | if (!radeon_connector->ddc_bus) | 1057 | if (!radeon_connector->ddc_bus) |
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index 12f5990c2d2a..5ab2cf96a264 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c | |||
@@ -142,15 +142,31 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) | |||
142 | } | 142 | } |
143 | 143 | ||
144 | p->chunks[i].length_dw = user_chunk.length_dw; | 144 | p->chunks[i].length_dw = user_chunk.length_dw; |
145 | cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data; | 145 | p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data; |
146 | 146 | ||
147 | size = p->chunks[i].length_dw * sizeof(uint32_t); | 147 | cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data; |
148 | p->chunks[i].kdata = kmalloc(size, GFP_KERNEL); | 148 | if (p->chunks[i].chunk_id != RADEON_CHUNK_ID_IB) { |
149 | if (p->chunks[i].kdata == NULL) { | 149 | size = p->chunks[i].length_dw * sizeof(uint32_t); |
150 | return -ENOMEM; | 150 | p->chunks[i].kdata = kmalloc(size, GFP_KERNEL); |
151 | } | 151 | if (p->chunks[i].kdata == NULL) { |
152 | if (DRM_COPY_FROM_USER(p->chunks[i].kdata, cdata, size)) { | 152 | return -ENOMEM; |
153 | return -EFAULT; | 153 | } |
154 | if (DRM_COPY_FROM_USER(p->chunks[i].kdata, | ||
155 | p->chunks[i].user_ptr, size)) { | ||
156 | return -EFAULT; | ||
157 | } | ||
158 | } else { | ||
159 | p->chunks[i].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL); | ||
160 | p->chunks[i].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL); | ||
161 | if (p->chunks[i].kpage[0] == NULL || p->chunks[i].kpage[1] == NULL) { | ||
162 | kfree(p->chunks[i].kpage[0]); | ||
163 | kfree(p->chunks[i].kpage[1]); | ||
164 | return -ENOMEM; | ||
165 | } | ||
166 | p->chunks[i].kpage_idx[0] = -1; | ||
167 | p->chunks[i].kpage_idx[1] = -1; | ||
168 | p->chunks[i].last_copied_page = -1; | ||
169 | p->chunks[i].last_page_index = ((p->chunks[i].length_dw * 4) - 1) / PAGE_SIZE; | ||
154 | } | 170 | } |
155 | } | 171 | } |
156 | if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) { | 172 | if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) { |
@@ -190,6 +206,8 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error) | |||
190 | kfree(parser->relocs_ptr); | 206 | kfree(parser->relocs_ptr); |
191 | for (i = 0; i < parser->nchunks; i++) { | 207 | for (i = 0; i < parser->nchunks; i++) { |
192 | kfree(parser->chunks[i].kdata); | 208 | kfree(parser->chunks[i].kdata); |
209 | kfree(parser->chunks[i].kpage[0]); | ||
210 | kfree(parser->chunks[i].kpage[1]); | ||
193 | } | 211 | } |
194 | kfree(parser->chunks); | 212 | kfree(parser->chunks); |
195 | kfree(parser->chunks_array); | 213 | kfree(parser->chunks_array); |
@@ -238,8 +256,14 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |||
238 | * uncached). */ | 256 | * uncached). */ |
239 | ib_chunk = &parser.chunks[parser.chunk_ib_idx]; | 257 | ib_chunk = &parser.chunks[parser.chunk_ib_idx]; |
240 | parser.ib->length_dw = ib_chunk->length_dw; | 258 | parser.ib->length_dw = ib_chunk->length_dw; |
241 | memcpy((void *)parser.ib->ptr, ib_chunk->kdata, ib_chunk->length_dw*4); | ||
242 | r = radeon_cs_parse(&parser); | 259 | r = radeon_cs_parse(&parser); |
260 | if (r || parser.parser_error) { | ||
261 | DRM_ERROR("Invalid command stream !\n"); | ||
262 | radeon_cs_parser_fini(&parser, r); | ||
263 | mutex_unlock(&rdev->cs_mutex); | ||
264 | return r; | ||
265 | } | ||
266 | r = radeon_cs_finish_pages(&parser); | ||
243 | if (r) { | 267 | if (r) { |
244 | DRM_ERROR("Invalid command stream !\n"); | 268 | DRM_ERROR("Invalid command stream !\n"); |
245 | radeon_cs_parser_fini(&parser, r); | 269 | radeon_cs_parser_fini(&parser, r); |
@@ -254,3 +278,64 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |||
254 | mutex_unlock(&rdev->cs_mutex); | 278 | mutex_unlock(&rdev->cs_mutex); |
255 | return r; | 279 | return r; |
256 | } | 280 | } |
281 | |||
282 | int radeon_cs_finish_pages(struct radeon_cs_parser *p) | ||
283 | { | ||
284 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | ||
285 | int i; | ||
286 | int size = PAGE_SIZE; | ||
287 | |||
288 | for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) { | ||
289 | if (i == ibc->last_page_index) { | ||
290 | size = (ibc->length_dw * 4) % PAGE_SIZE; | ||
291 | if (size == 0) | ||
292 | size = PAGE_SIZE; | ||
293 | } | ||
294 | |||
295 | if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)), | ||
296 | ibc->user_ptr + (i * PAGE_SIZE), | ||
297 | size)) | ||
298 | return -EFAULT; | ||
299 | } | ||
300 | return 0; | ||
301 | } | ||
302 | |||
303 | int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx) | ||
304 | { | ||
305 | int new_page; | ||
306 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | ||
307 | int i; | ||
308 | int size = PAGE_SIZE; | ||
309 | |||
310 | for (i = ibc->last_copied_page + 1; i < pg_idx; i++) { | ||
311 | if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)), | ||
312 | ibc->user_ptr + (i * PAGE_SIZE), | ||
313 | PAGE_SIZE)) { | ||
314 | p->parser_error = -EFAULT; | ||
315 | return 0; | ||
316 | } | ||
317 | } | ||
318 | |||
319 | new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1; | ||
320 | |||
321 | if (pg_idx == ibc->last_page_index) { | ||
322 | size = (ibc->length_dw * 4) % PAGE_SIZE; | ||
323 | if (size == 0) | ||
324 | size = PAGE_SIZE; | ||
325 | } | ||
326 | |||
327 | if (DRM_COPY_FROM_USER(ibc->kpage[new_page], | ||
328 | ibc->user_ptr + (pg_idx * PAGE_SIZE), | ||
329 | size)) { | ||
330 | p->parser_error = -EFAULT; | ||
331 | return 0; | ||
332 | } | ||
333 | |||
334 | /* copy to IB here */ | ||
335 | memcpy((void *)(p->ib->ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size); | ||
336 | |||
337 | ibc->last_copied_page = pg_idx; | ||
338 | ibc->kpage_idx[new_page] = pg_idx; | ||
339 | |||
340 | return new_page; | ||
341 | } | ||
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index daf5db780956..ec835d56d30a 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c | |||
@@ -532,10 +532,13 @@ int radeon_device_init(struct radeon_device *rdev, | |||
532 | 532 | ||
533 | if (radeon_agpmode == -1) { | 533 | if (radeon_agpmode == -1) { |
534 | rdev->flags &= ~RADEON_IS_AGP; | 534 | rdev->flags &= ~RADEON_IS_AGP; |
535 | if (rdev->family >= CHIP_RV515 || | 535 | if (rdev->family >= CHIP_R600) { |
536 | rdev->family == CHIP_RV380 || | 536 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
537 | rdev->family == CHIP_RV410 || | 537 | rdev->flags |= RADEON_IS_PCIE; |
538 | rdev->family == CHIP_R423) { | 538 | } else if (rdev->family >= CHIP_RV515 || |
539 | rdev->family == CHIP_RV380 || | ||
540 | rdev->family == CHIP_RV410 || | ||
541 | rdev->family == CHIP_R423) { | ||
539 | DRM_INFO("Forcing AGP to PCIE mode\n"); | 542 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
540 | rdev->flags |= RADEON_IS_PCIE; | 543 | rdev->flags |= RADEON_IS_PCIE; |
541 | rdev->asic->gart_init = &rv370_pcie_gart_init; | 544 | rdev->asic->gart_init = &rv370_pcie_gart_init; |
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 50fce498910c..7f50fb864af8 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c | |||
@@ -62,9 +62,6 @@ void radeon_driver_irq_preinstall_kms(struct drm_device *dev); | |||
62 | int radeon_driver_irq_postinstall_kms(struct drm_device *dev); | 62 | int radeon_driver_irq_postinstall_kms(struct drm_device *dev); |
63 | void radeon_driver_irq_uninstall_kms(struct drm_device *dev); | 63 | void radeon_driver_irq_uninstall_kms(struct drm_device *dev); |
64 | irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS); | 64 | irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS); |
65 | int radeon_master_create_kms(struct drm_device *dev, struct drm_master *master); | ||
66 | void radeon_master_destroy_kms(struct drm_device *dev, | ||
67 | struct drm_master *master); | ||
68 | int radeon_dma_ioctl_kms(struct drm_device *dev, void *data, | 65 | int radeon_dma_ioctl_kms(struct drm_device *dev, void *data, |
69 | struct drm_file *file_priv); | 66 | struct drm_file *file_priv); |
70 | int radeon_gem_object_init(struct drm_gem_object *obj); | 67 | int radeon_gem_object_init(struct drm_gem_object *obj); |
@@ -260,8 +257,6 @@ static struct drm_driver kms_driver = { | |||
260 | .get_vblank_counter = radeon_get_vblank_counter_kms, | 257 | .get_vblank_counter = radeon_get_vblank_counter_kms, |
261 | .enable_vblank = radeon_enable_vblank_kms, | 258 | .enable_vblank = radeon_enable_vblank_kms, |
262 | .disable_vblank = radeon_disable_vblank_kms, | 259 | .disable_vblank = radeon_disable_vblank_kms, |
263 | .master_create = radeon_master_create_kms, | ||
264 | .master_destroy = radeon_master_destroy_kms, | ||
265 | #if defined(CONFIG_DEBUG_FS) | 260 | #if defined(CONFIG_DEBUG_FS) |
266 | .debugfs_init = radeon_debugfs_init, | 261 | .debugfs_init = radeon_debugfs_init, |
267 | .debugfs_cleanup = radeon_debugfs_cleanup, | 262 | .debugfs_cleanup = radeon_debugfs_cleanup, |
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c index 944e4fa78db5..1ba704eedefb 100644 --- a/drivers/gpu/drm/radeon/radeon_fb.c +++ b/drivers/gpu/drm/radeon/radeon_fb.c | |||
@@ -128,6 +128,7 @@ static struct drm_fb_helper_funcs radeon_fb_helper_funcs = { | |||
128 | int radeonfb_create(struct drm_device *dev, | 128 | int radeonfb_create(struct drm_device *dev, |
129 | uint32_t fb_width, uint32_t fb_height, | 129 | uint32_t fb_width, uint32_t fb_height, |
130 | uint32_t surface_width, uint32_t surface_height, | 130 | uint32_t surface_width, uint32_t surface_height, |
131 | uint32_t surface_depth, uint32_t surface_bpp, | ||
131 | struct drm_framebuffer **fb_p) | 132 | struct drm_framebuffer **fb_p) |
132 | { | 133 | { |
133 | struct radeon_device *rdev = dev->dev_private; | 134 | struct radeon_device *rdev = dev->dev_private; |
@@ -148,10 +149,10 @@ int radeonfb_create(struct drm_device *dev, | |||
148 | 149 | ||
149 | mode_cmd.width = surface_width; | 150 | mode_cmd.width = surface_width; |
150 | mode_cmd.height = surface_height; | 151 | mode_cmd.height = surface_height; |
151 | mode_cmd.bpp = 32; | 152 | mode_cmd.bpp = surface_bpp; |
152 | /* need to align pitch with crtc limits */ | 153 | /* need to align pitch with crtc limits */ |
153 | mode_cmd.pitch = radeon_align_pitch(rdev, mode_cmd.width, mode_cmd.bpp, fb_tiled) * ((mode_cmd.bpp + 1) / 8); | 154 | mode_cmd.pitch = radeon_align_pitch(rdev, mode_cmd.width, mode_cmd.bpp, fb_tiled) * ((mode_cmd.bpp + 1) / 8); |
154 | mode_cmd.depth = 24; | 155 | mode_cmd.depth = surface_depth; |
155 | 156 | ||
156 | size = mode_cmd.pitch * mode_cmd.height; | 157 | size = mode_cmd.pitch * mode_cmd.height; |
157 | aligned_size = ALIGN(size, PAGE_SIZE); | 158 | aligned_size = ALIGN(size, PAGE_SIZE); |
@@ -290,13 +291,26 @@ out: | |||
290 | return ret; | 291 | return ret; |
291 | } | 292 | } |
292 | 293 | ||
294 | static char *mode_option; | ||
295 | int radeon_parse_options(char *options) | ||
296 | { | ||
297 | char *this_opt; | ||
298 | |||
299 | if (!options || !*options) | ||
300 | return 0; | ||
301 | |||
302 | while ((this_opt = strsep(&options, ",")) != NULL) { | ||
303 | if (!*this_opt) | ||
304 | continue; | ||
305 | mode_option = this_opt; | ||
306 | } | ||
307 | return 0; | ||
308 | } | ||
309 | |||
293 | int radeonfb_probe(struct drm_device *dev) | 310 | int radeonfb_probe(struct drm_device *dev) |
294 | { | 311 | { |
295 | int ret; | 312 | return drm_fb_helper_single_fb_probe(dev, &radeonfb_create); |
296 | ret = drm_fb_helper_single_fb_probe(dev, &radeonfb_create); | ||
297 | return ret; | ||
298 | } | 313 | } |
299 | EXPORT_SYMBOL(radeonfb_probe); | ||
300 | 314 | ||
301 | int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb) | 315 | int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb) |
302 | { | 316 | { |
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c index 709bd892b3a9..ba128621057a 100644 --- a/drivers/gpu/drm/radeon/radeon_kms.c +++ b/drivers/gpu/drm/radeon/radeon_kms.c | |||
@@ -201,55 +201,6 @@ void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) | |||
201 | 201 | ||
202 | 202 | ||
203 | /* | 203 | /* |
204 | * For multiple master (like multiple X). | ||
205 | */ | ||
206 | struct drm_radeon_master_private { | ||
207 | drm_local_map_t *sarea; | ||
208 | drm_radeon_sarea_t *sarea_priv; | ||
209 | }; | ||
210 | |||
211 | int radeon_master_create_kms(struct drm_device *dev, struct drm_master *master) | ||
212 | { | ||
213 | struct drm_radeon_master_private *master_priv; | ||
214 | unsigned long sareapage; | ||
215 | int ret; | ||
216 | |||
217 | master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL); | ||
218 | if (master_priv == NULL) { | ||
219 | return -ENOMEM; | ||
220 | } | ||
221 | /* prebuild the SAREA */ | ||
222 | sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE); | ||
223 | ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, | ||
224 | _DRM_CONTAINS_LOCK, | ||
225 | &master_priv->sarea); | ||
226 | if (ret) { | ||
227 | DRM_ERROR("SAREA setup failed\n"); | ||
228 | return ret; | ||
229 | } | ||
230 | master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea); | ||
231 | master_priv->sarea_priv->pfCurrentPage = 0; | ||
232 | master->driver_priv = master_priv; | ||
233 | return 0; | ||
234 | } | ||
235 | |||
236 | void radeon_master_destroy_kms(struct drm_device *dev, | ||
237 | struct drm_master *master) | ||
238 | { | ||
239 | struct drm_radeon_master_private *master_priv = master->driver_priv; | ||
240 | |||
241 | if (master_priv == NULL) { | ||
242 | return; | ||
243 | } | ||
244 | if (master_priv->sarea) { | ||
245 | drm_rmmap_locked(dev, master_priv->sarea); | ||
246 | } | ||
247 | kfree(master_priv); | ||
248 | master->driver_priv = NULL; | ||
249 | } | ||
250 | |||
251 | |||
252 | /* | ||
253 | * IOCTL. | 204 | * IOCTL. |
254 | */ | 205 | */ |
255 | int radeon_dma_ioctl_kms(struct drm_device *dev, void *data, | 206 | int radeon_dma_ioctl_kms(struct drm_device *dev, void *data, |
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h index 21da871a793c..bfa1ab9c93e1 100644 --- a/drivers/gpu/drm/radeon/radeon_reg.h +++ b/drivers/gpu/drm/radeon/radeon_reg.h | |||
@@ -3333,6 +3333,7 @@ | |||
3333 | # define RADEON_CP_PACKET_MAX_DWORDS (1 << 12) | 3333 | # define RADEON_CP_PACKET_MAX_DWORDS (1 << 12) |
3334 | # define RADEON_CP_PACKET0_REG_MASK 0x000007ff | 3334 | # define RADEON_CP_PACKET0_REG_MASK 0x000007ff |
3335 | # define R300_CP_PACKET0_REG_MASK 0x00001fff | 3335 | # define R300_CP_PACKET0_REG_MASK 0x00001fff |
3336 | # define R600_CP_PACKET0_REG_MASK 0x0000ffff | ||
3336 | # define RADEON_CP_PACKET1_REG0_MASK 0x000007ff | 3337 | # define RADEON_CP_PACKET1_REG0_MASK 0x000007ff |
3337 | # define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 | 3338 | # define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 |
3338 | 3339 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 5b1cf04a011a..765bd184b6fc 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c | |||
@@ -689,9 +689,6 @@ struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev) | |||
689 | 689 | ||
690 | #define RADEON_DEBUGFS_MEM_TYPES 2 | 690 | #define RADEON_DEBUGFS_MEM_TYPES 2 |
691 | 691 | ||
692 | static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES]; | ||
693 | static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES][32]; | ||
694 | |||
695 | #if defined(CONFIG_DEBUG_FS) | 692 | #if defined(CONFIG_DEBUG_FS) |
696 | static int radeon_mm_dump_table(struct seq_file *m, void *data) | 693 | static int radeon_mm_dump_table(struct seq_file *m, void *data) |
697 | { | 694 | { |
@@ -711,9 +708,11 @@ static int radeon_mm_dump_table(struct seq_file *m, void *data) | |||
711 | 708 | ||
712 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev) | 709 | static int radeon_ttm_debugfs_init(struct radeon_device *rdev) |
713 | { | 710 | { |
711 | #if defined(CONFIG_DEBUG_FS) | ||
712 | static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES]; | ||
713 | static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES][32]; | ||
714 | unsigned i; | 714 | unsigned i; |
715 | 715 | ||
716 | #if defined(CONFIG_DEBUG_FS) | ||
717 | for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) { | 716 | for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) { |
718 | if (i == 0) | 717 | if (i == 0) |
719 | sprintf(radeon_mem_types_names[i], "radeon_vram_mm"); | 718 | sprintf(radeon_mem_types_names[i], "radeon_vram_mm"); |
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index 0e791e26def3..4a4fe1cb131c 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c | |||
@@ -28,7 +28,6 @@ | |||
28 | #include "drmP.h" | 28 | #include "drmP.h" |
29 | #include "radeon_reg.h" | 29 | #include "radeon_reg.h" |
30 | #include "radeon.h" | 30 | #include "radeon.h" |
31 | #include "avivod.h" | ||
32 | 31 | ||
33 | #include "rs600_reg_safe.h" | 32 | #include "rs600_reg_safe.h" |
34 | 33 | ||
@@ -45,7 +44,6 @@ void r420_pipes_init(struct radeon_device *rdev); | |||
45 | */ | 44 | */ |
46 | void rs600_gpu_init(struct radeon_device *rdev); | 45 | void rs600_gpu_init(struct radeon_device *rdev); |
47 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); | 46 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
48 | void rs600_disable_vga(struct radeon_device *rdev); | ||
49 | 47 | ||
50 | 48 | ||
51 | /* | 49 | /* |
@@ -198,7 +196,7 @@ void rs600_mc_disable_clients(struct radeon_device *rdev) | |||
198 | "programming pipes. Bad things might happen.\n"); | 196 | "programming pipes. Bad things might happen.\n"); |
199 | } | 197 | } |
200 | 198 | ||
201 | radeon_avivo_vga_render_disable(rdev); | 199 | rv515_vga_render_disable(rdev); |
202 | 200 | ||
203 | tmp = RREG32(AVIVO_D1VGA_CONTROL); | 201 | tmp = RREG32(AVIVO_D1VGA_CONTROL); |
204 | WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); | 202 | WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); |
@@ -346,20 +344,6 @@ u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) | |||
346 | /* | 344 | /* |
347 | * Global GPU functions | 345 | * Global GPU functions |
348 | */ | 346 | */ |
349 | void rs600_disable_vga(struct radeon_device *rdev) | ||
350 | { | ||
351 | unsigned tmp; | ||
352 | |||
353 | WREG32(0x330, 0); | ||
354 | WREG32(0x338, 0); | ||
355 | tmp = RREG32(0x300); | ||
356 | tmp &= ~(3 << 16); | ||
357 | WREG32(0x300, tmp); | ||
358 | WREG32(0x308, (1 << 8)); | ||
359 | WREG32(0x310, rdev->mc.vram_location); | ||
360 | WREG32(0x594, 0); | ||
361 | } | ||
362 | |||
363 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) | 347 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
364 | { | 348 | { |
365 | unsigned i; | 349 | unsigned i; |
@@ -385,7 +369,7 @@ void rs600_gpu_init(struct radeon_device *rdev) | |||
385 | { | 369 | { |
386 | /* FIXME: HDP same place on rs600 ? */ | 370 | /* FIXME: HDP same place on rs600 ? */ |
387 | r100_hdp_reset(rdev); | 371 | r100_hdp_reset(rdev); |
388 | rs600_disable_vga(rdev); | 372 | rv515_vga_render_disable(rdev); |
389 | /* FIXME: is this correct ? */ | 373 | /* FIXME: is this correct ? */ |
390 | r420_pipes_init(rdev); | 374 | r420_pipes_init(rdev); |
391 | if (rs600_mc_wait_for_idle(rdev)) { | 375 | if (rs600_mc_wait_for_idle(rdev)) { |
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c index 0f585ca8276d..7a0098ddf977 100644 --- a/drivers/gpu/drm/radeon/rs690.c +++ b/drivers/gpu/drm/radeon/rs690.c | |||
@@ -40,7 +40,6 @@ void rs400_gart_disable(struct radeon_device *rdev); | |||
40 | int rs400_gart_enable(struct radeon_device *rdev); | 40 | int rs400_gart_enable(struct radeon_device *rdev); |
41 | void rs400_gart_adjust_size(struct radeon_device *rdev); | 41 | void rs400_gart_adjust_size(struct radeon_device *rdev); |
42 | void rs600_mc_disable_clients(struct radeon_device *rdev); | 42 | void rs600_mc_disable_clients(struct radeon_device *rdev); |
43 | void rs600_disable_vga(struct radeon_device *rdev); | ||
44 | 43 | ||
45 | /* This files gather functions specifics to : | 44 | /* This files gather functions specifics to : |
46 | * rs690,rs740 | 45 | * rs690,rs740 |
@@ -125,7 +124,7 @@ void rs690_gpu_init(struct radeon_device *rdev) | |||
125 | { | 124 | { |
126 | /* FIXME: HDP same place on rs690 ? */ | 125 | /* FIXME: HDP same place on rs690 ? */ |
127 | r100_hdp_reset(rdev); | 126 | r100_hdp_reset(rdev); |
128 | rs600_disable_vga(rdev); | 127 | rv515_vga_render_disable(rdev); |
129 | /* FIXME: is this correct ? */ | 128 | /* FIXME: is this correct ? */ |
130 | r420_pipes_init(rdev); | 129 | r420_pipes_init(rdev); |
131 | if (rs690_mc_wait_for_idle(rdev)) { | 130 | if (rs690_mc_wait_for_idle(rdev)) { |
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c index fd799748e7d8..e53b5ca7a253 100644 --- a/drivers/gpu/drm/radeon/rv515.c +++ b/drivers/gpu/drm/radeon/rv515.c | |||
@@ -29,37 +29,17 @@ | |||
29 | #include "drmP.h" | 29 | #include "drmP.h" |
30 | #include "rv515d.h" | 30 | #include "rv515d.h" |
31 | #include "radeon.h" | 31 | #include "radeon.h" |
32 | 32 | #include "atom.h" | |
33 | #include "rv515_reg_safe.h" | 33 | #include "rv515_reg_safe.h" |
34 | /* rv515 depends on : */ | 34 | |
35 | void r100_hdp_reset(struct radeon_device *rdev); | 35 | /* This files gather functions specifics to: rv515 */ |
36 | int r100_cp_reset(struct radeon_device *rdev); | ||
37 | int r100_rb2d_reset(struct radeon_device *rdev); | ||
38 | int r100_gui_wait_for_idle(struct radeon_device *rdev); | ||
39 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); | ||
40 | void r420_pipes_init(struct radeon_device *rdev); | ||
41 | void rs600_mc_disable_clients(struct radeon_device *rdev); | ||
42 | void rs600_disable_vga(struct radeon_device *rdev); | ||
43 | |||
44 | /* This files gather functions specifics to: | ||
45 | * rv515 | ||
46 | * | ||
47 | * Some of these functions might be used by newer ASICs. | ||
48 | */ | ||
49 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); | 36 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
50 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev); | 37 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev); |
51 | void rv515_gpu_init(struct radeon_device *rdev); | 38 | void rv515_gpu_init(struct radeon_device *rdev); |
52 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); | 39 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
53 | 40 | ||
54 | 41 | void rv515_debugfs(struct radeon_device *rdev) | |
55 | /* | ||
56 | * MC | ||
57 | */ | ||
58 | int rv515_mc_init(struct radeon_device *rdev) | ||
59 | { | 42 | { |
60 | uint32_t tmp; | ||
61 | int r; | ||
62 | |||
63 | if (r100_debugfs_rbbm_init(rdev)) { | 43 | if (r100_debugfs_rbbm_init(rdev)) { |
64 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); | 44 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
65 | } | 45 | } |
@@ -69,67 +49,8 @@ int rv515_mc_init(struct radeon_device *rdev) | |||
69 | if (rv515_debugfs_ga_info_init(rdev)) { | 49 | if (rv515_debugfs_ga_info_init(rdev)) { |
70 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); | 50 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
71 | } | 51 | } |
72 | |||
73 | rv515_gpu_init(rdev); | ||
74 | rv370_pcie_gart_disable(rdev); | ||
75 | |||
76 | /* Setup GPU memory space */ | ||
77 | rdev->mc.vram_location = 0xFFFFFFFFUL; | ||
78 | rdev->mc.gtt_location = 0xFFFFFFFFUL; | ||
79 | if (rdev->flags & RADEON_IS_AGP) { | ||
80 | r = radeon_agp_init(rdev); | ||
81 | if (r) { | ||
82 | printk(KERN_WARNING "[drm] Disabling AGP\n"); | ||
83 | rdev->flags &= ~RADEON_IS_AGP; | ||
84 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | ||
85 | } else { | ||
86 | rdev->mc.gtt_location = rdev->mc.agp_base; | ||
87 | } | ||
88 | } | ||
89 | r = radeon_mc_setup(rdev); | ||
90 | if (r) { | ||
91 | return r; | ||
92 | } | ||
93 | |||
94 | /* Program GPU memory space */ | ||
95 | rs600_mc_disable_clients(rdev); | ||
96 | if (rv515_mc_wait_for_idle(rdev)) { | ||
97 | printk(KERN_WARNING "Failed to wait MC idle while " | ||
98 | "programming pipes. Bad things might happen.\n"); | ||
99 | } | ||
100 | /* Write VRAM size in case we are limiting it */ | ||
101 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); | ||
102 | tmp = REG_SET(MC_FB_START, rdev->mc.vram_location >> 16); | ||
103 | WREG32(0x134, tmp); | ||
104 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; | ||
105 | tmp = REG_SET(MC_FB_TOP, tmp >> 16); | ||
106 | tmp |= REG_SET(MC_FB_START, rdev->mc.vram_location >> 16); | ||
107 | WREG32_MC(MC_FB_LOCATION, tmp); | ||
108 | WREG32(HDP_FB_LOCATION, rdev->mc.vram_location >> 16); | ||
109 | WREG32(0x310, rdev->mc.vram_location); | ||
110 | if (rdev->flags & RADEON_IS_AGP) { | ||
111 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; | ||
112 | tmp = REG_SET(MC_AGP_TOP, tmp >> 16); | ||
113 | tmp |= REG_SET(MC_AGP_START, rdev->mc.gtt_location >> 16); | ||
114 | WREG32_MC(MC_AGP_LOCATION, tmp); | ||
115 | WREG32_MC(MC_AGP_BASE, rdev->mc.agp_base); | ||
116 | WREG32_MC(MC_AGP_BASE_2, 0); | ||
117 | } else { | ||
118 | WREG32_MC(MC_AGP_LOCATION, 0x0FFFFFFF); | ||
119 | WREG32_MC(MC_AGP_BASE, 0); | ||
120 | WREG32_MC(MC_AGP_BASE_2, 0); | ||
121 | } | ||
122 | return 0; | ||
123 | } | ||
124 | |||
125 | void rv515_mc_fini(struct radeon_device *rdev) | ||
126 | { | ||
127 | } | 52 | } |
128 | 53 | ||
129 | |||
130 | /* | ||
131 | * Global GPU functions | ||
132 | */ | ||
133 | void rv515_ring_start(struct radeon_device *rdev) | 54 | void rv515_ring_start(struct radeon_device *rdev) |
134 | { | 55 | { |
135 | int r; | 56 | int r; |
@@ -198,11 +119,6 @@ void rv515_ring_start(struct radeon_device *rdev) | |||
198 | radeon_ring_unlock_commit(rdev); | 119 | radeon_ring_unlock_commit(rdev); |
199 | } | 120 | } |
200 | 121 | ||
201 | void rv515_errata(struct radeon_device *rdev) | ||
202 | { | ||
203 | rdev->pll_errata = 0; | ||
204 | } | ||
205 | |||
206 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) | 122 | int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
207 | { | 123 | { |
208 | unsigned i; | 124 | unsigned i; |
@@ -219,6 +135,12 @@ int rv515_mc_wait_for_idle(struct radeon_device *rdev) | |||
219 | return -1; | 135 | return -1; |
220 | } | 136 | } |
221 | 137 | ||
138 | void rv515_vga_render_disable(struct radeon_device *rdev) | ||
139 | { | ||
140 | WREG32(R_000300_VGA_RENDER_CONTROL, | ||
141 | RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); | ||
142 | } | ||
143 | |||
222 | void rv515_gpu_init(struct radeon_device *rdev) | 144 | void rv515_gpu_init(struct radeon_device *rdev) |
223 | { | 145 | { |
224 | unsigned pipe_select_current, gb_pipe_select, tmp; | 146 | unsigned pipe_select_current, gb_pipe_select, tmp; |
@@ -231,7 +153,7 @@ void rv515_gpu_init(struct radeon_device *rdev) | |||
231 | "reseting GPU. Bad things might happen.\n"); | 153 | "reseting GPU. Bad things might happen.\n"); |
232 | } | 154 | } |
233 | 155 | ||
234 | rs600_disable_vga(rdev); | 156 | rv515_vga_render_disable(rdev); |
235 | 157 | ||
236 | r420_pipes_init(rdev); | 158 | r420_pipes_init(rdev); |
237 | gb_pipe_select = RREG32(0x402C); | 159 | gb_pipe_select = RREG32(0x402C); |
@@ -335,10 +257,6 @@ int rv515_gpu_reset(struct radeon_device *rdev) | |||
335 | return 0; | 257 | return 0; |
336 | } | 258 | } |
337 | 259 | ||
338 | |||
339 | /* | ||
340 | * VRAM info | ||
341 | */ | ||
342 | static void rv515_vram_get_type(struct radeon_device *rdev) | 260 | static void rv515_vram_get_type(struct radeon_device *rdev) |
343 | { | 261 | { |
344 | uint32_t tmp; | 262 | uint32_t tmp; |
@@ -374,10 +292,6 @@ void rv515_vram_info(struct radeon_device *rdev) | |||
374 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); | 292 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
375 | } | 293 | } |
376 | 294 | ||
377 | |||
378 | /* | ||
379 | * Indirect registers accessor | ||
380 | */ | ||
381 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) | 295 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
382 | { | 296 | { |
383 | uint32_t r; | 297 | uint32_t r; |
@@ -395,9 +309,6 @@ void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |||
395 | WREG32(MC_IND_INDEX, 0); | 309 | WREG32(MC_IND_INDEX, 0); |
396 | } | 310 | } |
397 | 311 | ||
398 | /* | ||
399 | * Debugfs info | ||
400 | */ | ||
401 | #if defined(CONFIG_DEBUG_FS) | 312 | #if defined(CONFIG_DEBUG_FS) |
402 | static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) | 313 | static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) |
403 | { | 314 | { |
@@ -459,13 +370,258 @@ int rv515_debugfs_ga_info_init(struct radeon_device *rdev) | |||
459 | #endif | 370 | #endif |
460 | } | 371 | } |
461 | 372 | ||
462 | /* | 373 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) |
463 | * Asic initialization | 374 | { |
464 | */ | 375 | save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL); |
465 | int rv515_init(struct radeon_device *rdev) | 376 | save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL); |
377 | save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); | ||
378 | save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); | ||
379 | save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL); | ||
380 | save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL); | ||
381 | |||
382 | /* Stop all video */ | ||
383 | WREG32(R_000330_D1VGA_CONTROL, 0); | ||
384 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); | ||
385 | WREG32(R_000300_VGA_RENDER_CONTROL, 0); | ||
386 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); | ||
387 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); | ||
388 | WREG32(R_006080_D1CRTC_CONTROL, 0); | ||
389 | WREG32(R_006880_D2CRTC_CONTROL, 0); | ||
390 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); | ||
391 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); | ||
392 | } | ||
393 | |||
394 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) | ||
395 | { | ||
396 | WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); | ||
397 | WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); | ||
398 | WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); | ||
399 | WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); | ||
400 | WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); | ||
401 | /* Unlock host access */ | ||
402 | WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); | ||
403 | mdelay(1); | ||
404 | /* Restore video state */ | ||
405 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); | ||
406 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); | ||
407 | WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control); | ||
408 | WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control); | ||
409 | WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); | ||
410 | WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); | ||
411 | WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control); | ||
412 | WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control); | ||
413 | WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); | ||
414 | } | ||
415 | |||
416 | void rv515_mc_program(struct radeon_device *rdev) | ||
417 | { | ||
418 | struct rv515_mc_save save; | ||
419 | |||
420 | /* Stops all mc clients */ | ||
421 | rv515_mc_stop(rdev, &save); | ||
422 | |||
423 | /* Wait for mc idle */ | ||
424 | if (rv515_mc_wait_for_idle(rdev)) | ||
425 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); | ||
426 | /* Write VRAM size in case we are limiting it */ | ||
427 | WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); | ||
428 | /* Program MC, should be a 32bits limited address space */ | ||
429 | WREG32_MC(R_000001_MC_FB_LOCATION, | ||
430 | S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | | ||
431 | S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); | ||
432 | WREG32(R_000134_HDP_FB_LOCATION, | ||
433 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); | ||
434 | if (rdev->flags & RADEON_IS_AGP) { | ||
435 | WREG32_MC(R_000002_MC_AGP_LOCATION, | ||
436 | S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | | ||
437 | S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); | ||
438 | WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); | ||
439 | WREG32_MC(R_000004_MC_AGP_BASE_2, | ||
440 | S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); | ||
441 | } else { | ||
442 | WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); | ||
443 | WREG32_MC(R_000003_MC_AGP_BASE, 0); | ||
444 | WREG32_MC(R_000004_MC_AGP_BASE_2, 0); | ||
445 | } | ||
446 | |||
447 | rv515_mc_resume(rdev, &save); | ||
448 | } | ||
449 | |||
450 | void rv515_clock_startup(struct radeon_device *rdev) | ||
451 | { | ||
452 | if (radeon_dynclks != -1 && radeon_dynclks) | ||
453 | radeon_atom_set_clock_gating(rdev, 1); | ||
454 | /* We need to force on some of the block */ | ||
455 | WREG32_PLL(R_00000F_CP_DYN_CNTL, | ||
456 | RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); | ||
457 | WREG32_PLL(R_000011_E2_DYN_CNTL, | ||
458 | RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); | ||
459 | WREG32_PLL(R_000013_IDCT_DYN_CNTL, | ||
460 | RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); | ||
461 | } | ||
462 | |||
463 | static int rv515_startup(struct radeon_device *rdev) | ||
464 | { | ||
465 | int r; | ||
466 | |||
467 | rv515_mc_program(rdev); | ||
468 | /* Resume clock */ | ||
469 | rv515_clock_startup(rdev); | ||
470 | /* Initialize GPU configuration (# pipes, ...) */ | ||
471 | rv515_gpu_init(rdev); | ||
472 | /* Initialize GART (initialize after TTM so we can allocate | ||
473 | * memory through TTM but finalize after TTM) */ | ||
474 | if (rdev->flags & RADEON_IS_PCIE) { | ||
475 | r = rv370_pcie_gart_enable(rdev); | ||
476 | if (r) | ||
477 | return r; | ||
478 | } | ||
479 | /* Enable IRQ */ | ||
480 | rdev->irq.sw_int = true; | ||
481 | r100_irq_set(rdev); | ||
482 | /* 1M ring buffer */ | ||
483 | r = r100_cp_init(rdev, 1024 * 1024); | ||
484 | if (r) { | ||
485 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); | ||
486 | return r; | ||
487 | } | ||
488 | r = r100_wb_init(rdev); | ||
489 | if (r) | ||
490 | dev_err(rdev->dev, "failled initializing WB (%d).\n", r); | ||
491 | r = r100_ib_init(rdev); | ||
492 | if (r) { | ||
493 | dev_err(rdev->dev, "failled initializing IB (%d).\n", r); | ||
494 | return r; | ||
495 | } | ||
496 | return 0; | ||
497 | } | ||
498 | |||
499 | int rv515_resume(struct radeon_device *rdev) | ||
500 | { | ||
501 | /* Make sur GART are not working */ | ||
502 | if (rdev->flags & RADEON_IS_PCIE) | ||
503 | rv370_pcie_gart_disable(rdev); | ||
504 | /* Resume clock before doing reset */ | ||
505 | rv515_clock_startup(rdev); | ||
506 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | ||
507 | if (radeon_gpu_reset(rdev)) { | ||
508 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | ||
509 | RREG32(R_000E40_RBBM_STATUS), | ||
510 | RREG32(R_0007C0_CP_STAT)); | ||
511 | } | ||
512 | /* post */ | ||
513 | atom_asic_init(rdev->mode_info.atom_context); | ||
514 | /* Resume clock after posting */ | ||
515 | rv515_clock_startup(rdev); | ||
516 | return rv515_startup(rdev); | ||
517 | } | ||
518 | |||
519 | int rv515_suspend(struct radeon_device *rdev) | ||
520 | { | ||
521 | r100_cp_disable(rdev); | ||
522 | r100_wb_disable(rdev); | ||
523 | r100_irq_disable(rdev); | ||
524 | if (rdev->flags & RADEON_IS_PCIE) | ||
525 | rv370_pcie_gart_disable(rdev); | ||
526 | return 0; | ||
527 | } | ||
528 | |||
529 | void rv515_set_safe_registers(struct radeon_device *rdev) | ||
466 | { | 530 | { |
467 | rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; | 531 | rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; |
468 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); | 532 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); |
533 | } | ||
534 | |||
535 | void rv515_fini(struct radeon_device *rdev) | ||
536 | { | ||
537 | rv515_suspend(rdev); | ||
538 | r100_cp_fini(rdev); | ||
539 | r100_wb_fini(rdev); | ||
540 | r100_ib_fini(rdev); | ||
541 | radeon_gem_fini(rdev); | ||
542 | rv370_pcie_gart_fini(rdev); | ||
543 | radeon_agp_fini(rdev); | ||
544 | radeon_irq_kms_fini(rdev); | ||
545 | radeon_fence_driver_fini(rdev); | ||
546 | radeon_object_fini(rdev); | ||
547 | radeon_atombios_fini(rdev); | ||
548 | kfree(rdev->bios); | ||
549 | rdev->bios = NULL; | ||
550 | } | ||
551 | |||
552 | int rv515_init(struct radeon_device *rdev) | ||
553 | { | ||
554 | int r; | ||
555 | |||
556 | rdev->new_init_path = true; | ||
557 | /* Initialize scratch registers */ | ||
558 | radeon_scratch_init(rdev); | ||
559 | /* Initialize surface registers */ | ||
560 | radeon_surface_init(rdev); | ||
561 | /* TODO: disable VGA need to use VGA request */ | ||
562 | /* BIOS*/ | ||
563 | if (!radeon_get_bios(rdev)) { | ||
564 | if (ASIC_IS_AVIVO(rdev)) | ||
565 | return -EINVAL; | ||
566 | } | ||
567 | if (rdev->is_atom_bios) { | ||
568 | r = radeon_atombios_init(rdev); | ||
569 | if (r) | ||
570 | return r; | ||
571 | } else { | ||
572 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); | ||
573 | return -EINVAL; | ||
574 | } | ||
575 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | ||
576 | if (radeon_gpu_reset(rdev)) { | ||
577 | dev_warn(rdev->dev, | ||
578 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | ||
579 | RREG32(R_000E40_RBBM_STATUS), | ||
580 | RREG32(R_0007C0_CP_STAT)); | ||
581 | } | ||
582 | /* check if cards are posted or not */ | ||
583 | if (!radeon_card_posted(rdev) && rdev->bios) { | ||
584 | DRM_INFO("GPU not posted. posting now...\n"); | ||
585 | atom_asic_init(rdev->mode_info.atom_context); | ||
586 | } | ||
587 | /* Initialize clocks */ | ||
588 | radeon_get_clock_info(rdev->ddev); | ||
589 | /* Get vram informations */ | ||
590 | rv515_vram_info(rdev); | ||
591 | /* Initialize memory controller (also test AGP) */ | ||
592 | r = r420_mc_init(rdev); | ||
593 | if (r) | ||
594 | return r; | ||
595 | rv515_debugfs(rdev); | ||
596 | /* Fence driver */ | ||
597 | r = radeon_fence_driver_init(rdev); | ||
598 | if (r) | ||
599 | return r; | ||
600 | r = radeon_irq_kms_init(rdev); | ||
601 | if (r) | ||
602 | return r; | ||
603 | /* Memory manager */ | ||
604 | r = radeon_object_init(rdev); | ||
605 | if (r) | ||
606 | return r; | ||
607 | r = rv370_pcie_gart_init(rdev); | ||
608 | if (r) | ||
609 | return r; | ||
610 | rv515_set_safe_registers(rdev); | ||
611 | rdev->accel_working = true; | ||
612 | r = rv515_startup(rdev); | ||
613 | if (r) { | ||
614 | /* Somethings want wront with the accel init stop accel */ | ||
615 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | ||
616 | rv515_suspend(rdev); | ||
617 | r100_cp_fini(rdev); | ||
618 | r100_wb_fini(rdev); | ||
619 | r100_ib_fini(rdev); | ||
620 | rv370_pcie_gart_fini(rdev); | ||
621 | radeon_agp_fini(rdev); | ||
622 | radeon_irq_kms_fini(rdev); | ||
623 | rdev->accel_working = false; | ||
624 | } | ||
469 | return 0; | 625 | return 0; |
470 | } | 626 | } |
471 | 627 | ||
diff --git a/drivers/gpu/drm/radeon/rv515d.h b/drivers/gpu/drm/radeon/rv515d.h index a65e17ec1c08..fc216e49384d 100644 --- a/drivers/gpu/drm/radeon/rv515d.h +++ b/drivers/gpu/drm/radeon/rv515d.h | |||
@@ -216,5 +216,388 @@ | |||
216 | #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) | 216 | #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) |
217 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) | 217 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) |
218 | 218 | ||
219 | #endif | 219 | /* Registers */ |
220 | #define R_0000F8_CONFIG_MEMSIZE 0x0000F8 | ||
221 | #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) | ||
222 | #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) | ||
223 | #define C_0000F8_CONFIG_MEMSIZE 0x00000000 | ||
224 | #define R_000134_HDP_FB_LOCATION 0x000134 | ||
225 | #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) | ||
226 | #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) | ||
227 | #define C_000134_HDP_FB_START 0xFFFF0000 | ||
228 | #define R_000300_VGA_RENDER_CONTROL 0x000300 | ||
229 | #define S_000300_VGA_BLINK_RATE(x) (((x) & 0x1F) << 0) | ||
230 | #define G_000300_VGA_BLINK_RATE(x) (((x) >> 0) & 0x1F) | ||
231 | #define C_000300_VGA_BLINK_RATE 0xFFFFFFE0 | ||
232 | #define S_000300_VGA_BLINK_MODE(x) (((x) & 0x3) << 5) | ||
233 | #define G_000300_VGA_BLINK_MODE(x) (((x) >> 5) & 0x3) | ||
234 | #define C_000300_VGA_BLINK_MODE 0xFFFFFF9F | ||
235 | #define S_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) & 0x1) << 7) | ||
236 | #define G_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) >> 7) & 0x1) | ||
237 | #define C_000300_VGA_CURSOR_BLINK_INVERT 0xFFFFFF7F | ||
238 | #define S_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) & 0x1) << 8) | ||
239 | #define G_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) >> 8) & 0x1) | ||
240 | #define C_000300_VGA_EXTD_ADDR_COUNT_ENABLE 0xFFFFFEFF | ||
241 | #define S_000300_VGA_VSTATUS_CNTL(x) (((x) & 0x3) << 16) | ||
242 | #define G_000300_VGA_VSTATUS_CNTL(x) (((x) >> 16) & 0x3) | ||
243 | #define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF | ||
244 | #define S_000300_VGA_LOCK_8DOT(x) (((x) & 0x1) << 24) | ||
245 | #define G_000300_VGA_LOCK_8DOT(x) (((x) >> 24) & 0x1) | ||
246 | #define C_000300_VGA_LOCK_8DOT 0xFEFFFFFF | ||
247 | #define S_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) & 0x1) << 25) | ||
248 | #define G_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) >> 25) & 0x1) | ||
249 | #define C_000300_VGAREG_LINECMP_COMPATIBILITY_SEL 0xFDFFFFFF | ||
250 | #define R_000310_VGA_MEMORY_BASE_ADDRESS 0x000310 | ||
251 | #define S_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) | ||
252 | #define G_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) | ||
253 | #define C_000310_VGA_MEMORY_BASE_ADDRESS 0x00000000 | ||
254 | #define R_000328_VGA_HDP_CONTROL 0x000328 | ||
255 | #define S_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) & 0x1) << 0) | ||
256 | #define G_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) >> 0) & 0x1) | ||
257 | #define C_000328_VGA_MEM_PAGE_SELECT_EN 0xFFFFFFFE | ||
258 | #define S_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) & 0x1) << 8) | ||
259 | #define G_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) >> 8) & 0x1) | ||
260 | #define C_000328_VGA_RBBM_LOCK_DISABLE 0xFFFFFEFF | ||
261 | #define S_000328_VGA_SOFT_RESET(x) (((x) & 0x1) << 16) | ||
262 | #define G_000328_VGA_SOFT_RESET(x) (((x) >> 16) & 0x1) | ||
263 | #define C_000328_VGA_SOFT_RESET 0xFFFEFFFF | ||
264 | #define S_000328_VGA_TEST_RESET_CONTROL(x) (((x) & 0x1) << 24) | ||
265 | #define G_000328_VGA_TEST_RESET_CONTROL(x) (((x) >> 24) & 0x1) | ||
266 | #define C_000328_VGA_TEST_RESET_CONTROL 0xFEFFFFFF | ||
267 | #define R_000330_D1VGA_CONTROL 0x000330 | ||
268 | #define S_000330_D1VGA_MODE_ENABLE(x) (((x) & 0x1) << 0) | ||
269 | #define G_000330_D1VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1) | ||
270 | #define C_000330_D1VGA_MODE_ENABLE 0xFFFFFFFE | ||
271 | #define S_000330_D1VGA_TIMING_SELECT(x) (((x) & 0x1) << 8) | ||
272 | #define G_000330_D1VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1) | ||
273 | #define C_000330_D1VGA_TIMING_SELECT 0xFFFFFEFF | ||
274 | #define S_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9) | ||
275 | #define G_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1) | ||
276 | #define C_000330_D1VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF | ||
277 | #define S_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10) | ||
278 | #define G_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1) | ||
279 | #define C_000330_D1VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF | ||
280 | #define S_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16) | ||
281 | #define G_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1) | ||
282 | #define C_000330_D1VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF | ||
283 | #define S_000330_D1VGA_ROTATE(x) (((x) & 0x3) << 24) | ||
284 | #define G_000330_D1VGA_ROTATE(x) (((x) >> 24) & 0x3) | ||
285 | #define C_000330_D1VGA_ROTATE 0xFCFFFFFF | ||
286 | #define R_000338_D2VGA_CONTROL 0x000338 | ||
287 | #define S_000338_D2VGA_MODE_ENABLE(x) (((x) & 0x1) << 0) | ||
288 | #define G_000338_D2VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1) | ||
289 | #define C_000338_D2VGA_MODE_ENABLE 0xFFFFFFFE | ||
290 | #define S_000338_D2VGA_TIMING_SELECT(x) (((x) & 0x1) << 8) | ||
291 | #define G_000338_D2VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1) | ||
292 | #define C_000338_D2VGA_TIMING_SELECT 0xFFFFFEFF | ||
293 | #define S_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9) | ||
294 | #define G_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1) | ||
295 | #define C_000338_D2VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF | ||
296 | #define S_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10) | ||
297 | #define G_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1) | ||
298 | #define C_000338_D2VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF | ||
299 | #define S_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16) | ||
300 | #define G_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1) | ||
301 | #define C_000338_D2VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF | ||
302 | #define S_000338_D2VGA_ROTATE(x) (((x) & 0x3) << 24) | ||
303 | #define G_000338_D2VGA_ROTATE(x) (((x) >> 24) & 0x3) | ||
304 | #define C_000338_D2VGA_ROTATE 0xFCFFFFFF | ||
305 | #define R_0007C0_CP_STAT 0x0007C0 | ||
306 | #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) | ||
307 | #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) | ||
308 | #define C_0007C0_MRU_BUSY 0xFFFFFFFE | ||
309 | #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) | ||
310 | #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) | ||
311 | #define C_0007C0_MWU_BUSY 0xFFFFFFFD | ||
312 | #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) | ||
313 | #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) | ||
314 | #define C_0007C0_RSIU_BUSY 0xFFFFFFFB | ||
315 | #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) | ||
316 | #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) | ||
317 | #define C_0007C0_RCIU_BUSY 0xFFFFFFF7 | ||
318 | #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) | ||
319 | #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) | ||
320 | #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF | ||
321 | #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) | ||
322 | #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) | ||
323 | #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF | ||
324 | #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) | ||
325 | #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) | ||
326 | #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF | ||
327 | #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) | ||
328 | #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) | ||
329 | #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF | ||
330 | #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) | ||
331 | #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) | ||
332 | #define C_0007C0_CSI_BUSY 0xFFFFDFFF | ||
333 | #define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) | ||
334 | #define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) | ||
335 | #define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF | ||
336 | #define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) | ||
337 | #define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) | ||
338 | #define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF | ||
339 | #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) | ||
340 | #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) | ||
341 | #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF | ||
342 | #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) | ||
343 | #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) | ||
344 | #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF | ||
345 | #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) | ||
346 | #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) | ||
347 | #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF | ||
348 | #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) | ||
349 | #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) | ||
350 | #define C_0007C0_CP_BUSY 0x7FFFFFFF | ||
351 | #define R_000E40_RBBM_STATUS 0x000E40 | ||
352 | #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) | ||
353 | #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) | ||
354 | #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 | ||
355 | #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) | ||
356 | #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) | ||
357 | #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF | ||
358 | #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) | ||
359 | #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) | ||
360 | #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF | ||
361 | #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) | ||
362 | #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) | ||
363 | #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF | ||
364 | #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) | ||
365 | #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) | ||
366 | #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF | ||
367 | #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) | ||
368 | #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) | ||
369 | #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF | ||
370 | #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) | ||
371 | #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) | ||
372 | #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF | ||
373 | #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) | ||
374 | #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) | ||
375 | #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF | ||
376 | #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) | ||
377 | #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) | ||
378 | #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF | ||
379 | #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) | ||
380 | #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) | ||
381 | #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF | ||
382 | #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) | ||
383 | #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) | ||
384 | #define C_000E40_E2_BUSY 0xFFFDFFFF | ||
385 | #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) | ||
386 | #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) | ||
387 | #define C_000E40_RB2D_BUSY 0xFFFBFFFF | ||
388 | #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) | ||
389 | #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) | ||
390 | #define C_000E40_RB3D_BUSY 0xFFF7FFFF | ||
391 | #define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) | ||
392 | #define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) | ||
393 | #define C_000E40_VAP_BUSY 0xFFEFFFFF | ||
394 | #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) | ||
395 | #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) | ||
396 | #define C_000E40_RE_BUSY 0xFFDFFFFF | ||
397 | #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) | ||
398 | #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) | ||
399 | #define C_000E40_TAM_BUSY 0xFFBFFFFF | ||
400 | #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) | ||
401 | #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) | ||
402 | #define C_000E40_TDM_BUSY 0xFF7FFFFF | ||
403 | #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) | ||
404 | #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) | ||
405 | #define C_000E40_PB_BUSY 0xFEFFFFFF | ||
406 | #define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) | ||
407 | #define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) | ||
408 | #define C_000E40_TIM_BUSY 0xFDFFFFFF | ||
409 | #define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) | ||
410 | #define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) | ||
411 | #define C_000E40_GA_BUSY 0xFBFFFFFF | ||
412 | #define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) | ||
413 | #define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) | ||
414 | #define C_000E40_CBA2D_BUSY 0xF7FFFFFF | ||
415 | #define S_000E40_RBBM_HIBUSY(x) (((x) & 0x1) << 28) | ||
416 | #define G_000E40_RBBM_HIBUSY(x) (((x) >> 28) & 0x1) | ||
417 | #define C_000E40_RBBM_HIBUSY 0xEFFFFFFF | ||
418 | #define S_000E40_SKID_CFBUSY(x) (((x) & 0x1) << 29) | ||
419 | #define G_000E40_SKID_CFBUSY(x) (((x) >> 29) & 0x1) | ||
420 | #define C_000E40_SKID_CFBUSY 0xDFFFFFFF | ||
421 | #define S_000E40_VAP_VF_BUSY(x) (((x) & 0x1) << 30) | ||
422 | #define G_000E40_VAP_VF_BUSY(x) (((x) >> 30) & 0x1) | ||
423 | #define C_000E40_VAP_VF_BUSY 0xBFFFFFFF | ||
424 | #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) | ||
425 | #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) | ||
426 | #define C_000E40_GUI_ACTIVE 0x7FFFFFFF | ||
427 | #define R_006080_D1CRTC_CONTROL 0x006080 | ||
428 | #define S_006080_D1CRTC_MASTER_EN(x) (((x) & 0x1) << 0) | ||
429 | #define G_006080_D1CRTC_MASTER_EN(x) (((x) >> 0) & 0x1) | ||
430 | #define C_006080_D1CRTC_MASTER_EN 0xFFFFFFFE | ||
431 | #define S_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4) | ||
432 | #define G_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1) | ||
433 | #define C_006080_D1CRTC_SYNC_RESET_SEL 0xFFFFFFEF | ||
434 | #define S_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8) | ||
435 | #define G_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3) | ||
436 | #define C_006080_D1CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF | ||
437 | #define S_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16) | ||
438 | #define G_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1) | ||
439 | #define C_006080_D1CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF | ||
440 | #define S_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24) | ||
441 | #define G_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1) | ||
442 | #define C_006080_D1CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF | ||
443 | #define R_0060E8_D1CRTC_UPDATE_LOCK 0x0060E8 | ||
444 | #define S_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0) | ||
445 | #define G_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1) | ||
446 | #define C_0060E8_D1CRTC_UPDATE_LOCK 0xFFFFFFFE | ||
447 | #define R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x006110 | ||
448 | #define S_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) | ||
449 | #define G_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) | ||
450 | #define C_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000 | ||
451 | #define R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x006118 | ||
452 | #define S_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) | ||
453 | #define G_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) | ||
454 | #define C_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000 | ||
455 | #define R_006880_D2CRTC_CONTROL 0x006880 | ||
456 | #define S_006880_D2CRTC_MASTER_EN(x) (((x) & 0x1) << 0) | ||
457 | #define G_006880_D2CRTC_MASTER_EN(x) (((x) >> 0) & 0x1) | ||
458 | #define C_006880_D2CRTC_MASTER_EN 0xFFFFFFFE | ||
459 | #define S_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4) | ||
460 | #define G_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1) | ||
461 | #define C_006880_D2CRTC_SYNC_RESET_SEL 0xFFFFFFEF | ||
462 | #define S_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8) | ||
463 | #define G_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3) | ||
464 | #define C_006880_D2CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF | ||
465 | #define S_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16) | ||
466 | #define G_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1) | ||
467 | #define C_006880_D2CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF | ||
468 | #define S_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24) | ||
469 | #define G_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1) | ||
470 | #define C_006880_D2CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF | ||
471 | #define R_0068E8_D2CRTC_UPDATE_LOCK 0x0068E8 | ||
472 | #define S_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0) | ||
473 | #define G_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1) | ||
474 | #define C_0068E8_D2CRTC_UPDATE_LOCK 0xFFFFFFFE | ||
475 | #define R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x006910 | ||
476 | #define S_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) | ||
477 | #define G_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) | ||
478 | #define C_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000 | ||
479 | #define R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x006918 | ||
480 | #define S_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) | ||
481 | #define G_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) | ||
482 | #define C_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000 | ||
483 | |||
484 | |||
485 | #define R_000001_MC_FB_LOCATION 0x000001 | ||
486 | #define S_000001_MC_FB_START(x) (((x) & 0xFFFF) << 0) | ||
487 | #define G_000001_MC_FB_START(x) (((x) >> 0) & 0xFFFF) | ||
488 | #define C_000001_MC_FB_START 0xFFFF0000 | ||
489 | #define S_000001_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) | ||
490 | #define G_000001_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) | ||
491 | #define C_000001_MC_FB_TOP 0x0000FFFF | ||
492 | #define R_000002_MC_AGP_LOCATION 0x000002 | ||
493 | #define S_000002_MC_AGP_START(x) (((x) & 0xFFFF) << 0) | ||
494 | #define G_000002_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) | ||
495 | #define C_000002_MC_AGP_START 0xFFFF0000 | ||
496 | #define S_000002_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) | ||
497 | #define G_000002_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) | ||
498 | #define C_000002_MC_AGP_TOP 0x0000FFFF | ||
499 | #define R_000003_MC_AGP_BASE 0x000003 | ||
500 | #define S_000003_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) | ||
501 | #define G_000003_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) | ||
502 | #define C_000003_AGP_BASE_ADDR 0x00000000 | ||
503 | #define R_000004_MC_AGP_BASE_2 0x000004 | ||
504 | #define S_000004_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) | ||
505 | #define G_000004_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) | ||
506 | #define C_000004_AGP_BASE_ADDR_2 0xFFFFFFF0 | ||
220 | 507 | ||
508 | |||
509 | #define R_00000F_CP_DYN_CNTL 0x00000F | ||
510 | #define S_00000F_CP_FORCEON(x) (((x) & 0x1) << 0) | ||
511 | #define G_00000F_CP_FORCEON(x) (((x) >> 0) & 0x1) | ||
512 | #define C_00000F_CP_FORCEON 0xFFFFFFFE | ||
513 | #define S_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) | ||
514 | #define G_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) | ||
515 | #define C_00000F_CP_MAX_DYN_STOP_LAT 0xFFFFFFFD | ||
516 | #define S_00000F_CP_CLOCK_STATUS(x) (((x) & 0x1) << 2) | ||
517 | #define G_00000F_CP_CLOCK_STATUS(x) (((x) >> 2) & 0x1) | ||
518 | #define C_00000F_CP_CLOCK_STATUS 0xFFFFFFFB | ||
519 | #define S_00000F_CP_PROG_SHUTOFF(x) (((x) & 0x1) << 3) | ||
520 | #define G_00000F_CP_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) | ||
521 | #define C_00000F_CP_PROG_SHUTOFF 0xFFFFFFF7 | ||
522 | #define S_00000F_CP_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) | ||
523 | #define G_00000F_CP_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) | ||
524 | #define C_00000F_CP_PROG_DELAY_VALUE 0xFFFFF00F | ||
525 | #define S_00000F_CP_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) | ||
526 | #define G_00000F_CP_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) | ||
527 | #define C_00000F_CP_LOWER_POWER_IDLE 0xFFF00FFF | ||
528 | #define S_00000F_CP_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) | ||
529 | #define G_00000F_CP_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) | ||
530 | #define C_00000F_CP_LOWER_POWER_IGNORE 0xFFEFFFFF | ||
531 | #define S_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) | ||
532 | #define G_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) | ||
533 | #define C_00000F_CP_NORMAL_POWER_IGNORE 0xFFDFFFFF | ||
534 | #define S_00000F_SPARE(x) (((x) & 0x3) << 22) | ||
535 | #define G_00000F_SPARE(x) (((x) >> 22) & 0x3) | ||
536 | #define C_00000F_SPARE 0xFF3FFFFF | ||
537 | #define S_00000F_CP_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) | ||
538 | #define G_00000F_CP_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) | ||
539 | #define C_00000F_CP_NORMAL_POWER_BUSY 0x00FFFFFF | ||
540 | #define R_000011_E2_DYN_CNTL 0x000011 | ||
541 | #define S_000011_E2_FORCEON(x) (((x) & 0x1) << 0) | ||
542 | #define G_000011_E2_FORCEON(x) (((x) >> 0) & 0x1) | ||
543 | #define C_000011_E2_FORCEON 0xFFFFFFFE | ||
544 | #define S_000011_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) | ||
545 | #define G_000011_E2_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) | ||
546 | #define C_000011_E2_MAX_DYN_STOP_LAT 0xFFFFFFFD | ||
547 | #define S_000011_E2_CLOCK_STATUS(x) (((x) & 0x1) << 2) | ||
548 | #define G_000011_E2_CLOCK_STATUS(x) (((x) >> 2) & 0x1) | ||
549 | #define C_000011_E2_CLOCK_STATUS 0xFFFFFFFB | ||
550 | #define S_000011_E2_PROG_SHUTOFF(x) (((x) & 0x1) << 3) | ||
551 | #define G_000011_E2_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) | ||
552 | #define C_000011_E2_PROG_SHUTOFF 0xFFFFFFF7 | ||
553 | #define S_000011_E2_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) | ||
554 | #define G_000011_E2_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) | ||
555 | #define C_000011_E2_PROG_DELAY_VALUE 0xFFFFF00F | ||
556 | #define S_000011_E2_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) | ||
557 | #define G_000011_E2_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) | ||
558 | #define C_000011_E2_LOWER_POWER_IDLE 0xFFF00FFF | ||
559 | #define S_000011_E2_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) | ||
560 | #define G_000011_E2_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) | ||
561 | #define C_000011_E2_LOWER_POWER_IGNORE 0xFFEFFFFF | ||
562 | #define S_000011_E2_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) | ||
563 | #define G_000011_E2_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) | ||
564 | #define C_000011_E2_NORMAL_POWER_IGNORE 0xFFDFFFFF | ||
565 | #define S_000011_SPARE(x) (((x) & 0x3) << 22) | ||
566 | #define G_000011_SPARE(x) (((x) >> 22) & 0x3) | ||
567 | #define C_000011_SPARE 0xFF3FFFFF | ||
568 | #define S_000011_E2_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) | ||
569 | #define G_000011_E2_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) | ||
570 | #define C_000011_E2_NORMAL_POWER_BUSY 0x00FFFFFF | ||
571 | #define R_000013_IDCT_DYN_CNTL 0x000013 | ||
572 | #define S_000013_IDCT_FORCEON(x) (((x) & 0x1) << 0) | ||
573 | #define G_000013_IDCT_FORCEON(x) (((x) >> 0) & 0x1) | ||
574 | #define C_000013_IDCT_FORCEON 0xFFFFFFFE | ||
575 | #define S_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) | ||
576 | #define G_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) | ||
577 | #define C_000013_IDCT_MAX_DYN_STOP_LAT 0xFFFFFFFD | ||
578 | #define S_000013_IDCT_CLOCK_STATUS(x) (((x) & 0x1) << 2) | ||
579 | #define G_000013_IDCT_CLOCK_STATUS(x) (((x) >> 2) & 0x1) | ||
580 | #define C_000013_IDCT_CLOCK_STATUS 0xFFFFFFFB | ||
581 | #define S_000013_IDCT_PROG_SHUTOFF(x) (((x) & 0x1) << 3) | ||
582 | #define G_000013_IDCT_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) | ||
583 | #define C_000013_IDCT_PROG_SHUTOFF 0xFFFFFFF7 | ||
584 | #define S_000013_IDCT_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) | ||
585 | #define G_000013_IDCT_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) | ||
586 | #define C_000013_IDCT_PROG_DELAY_VALUE 0xFFFFF00F | ||
587 | #define S_000013_IDCT_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) | ||
588 | #define G_000013_IDCT_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) | ||
589 | #define C_000013_IDCT_LOWER_POWER_IDLE 0xFFF00FFF | ||
590 | #define S_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) | ||
591 | #define G_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) | ||
592 | #define C_000013_IDCT_LOWER_POWER_IGNORE 0xFFEFFFFF | ||
593 | #define S_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) | ||
594 | #define G_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) | ||
595 | #define C_000013_IDCT_NORMAL_POWER_IGNORE 0xFFDFFFFF | ||
596 | #define S_000013_SPARE(x) (((x) & 0x3) << 22) | ||
597 | #define G_000013_SPARE(x) (((x) >> 22) & 0x3) | ||
598 | #define C_000013_SPARE 0xFF3FFFFF | ||
599 | #define S_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) | ||
600 | #define G_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) | ||
601 | #define C_000013_IDCT_NORMAL_POWER_BUSY 0x00FFFFFF | ||
602 | |||
603 | #endif | ||
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index b574c73a5109..e0b97d161397 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c | |||
@@ -31,8 +31,8 @@ | |||
31 | #include "radeon.h" | 31 | #include "radeon.h" |
32 | #include "radeon_drm.h" | 32 | #include "radeon_drm.h" |
33 | #include "rv770d.h" | 33 | #include "rv770d.h" |
34 | #include "avivod.h" | ||
35 | #include "atom.h" | 34 | #include "atom.h" |
35 | #include "avivod.h" | ||
36 | 36 | ||
37 | #define R700_PFP_UCODE_SIZE 848 | 37 | #define R700_PFP_UCODE_SIZE 848 |
38 | #define R700_PM4_UCODE_SIZE 1360 | 38 | #define R700_PM4_UCODE_SIZE 1360 |
@@ -231,7 +231,7 @@ static void rv770_mc_resume(struct radeon_device *rdev) | |||
231 | 231 | ||
232 | /* we need to own VRAM, so turn off the VGA renderer here | 232 | /* we need to own VRAM, so turn off the VGA renderer here |
233 | * to stop it overwriting our objects */ | 233 | * to stop it overwriting our objects */ |
234 | radeon_avivo_vga_render_disable(rdev); | 234 | rv515_vga_render_disable(rdev); |
235 | } | 235 | } |
236 | 236 | ||
237 | 237 | ||
@@ -801,6 +801,13 @@ int rv770_mc_init(struct radeon_device *rdev) | |||
801 | /* Setup GPU memory space */ | 801 | /* Setup GPU memory space */ |
802 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); | 802 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); |
803 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); | 803 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); |
804 | |||
805 | if (rdev->mc.mc_vram_size > rdev->mc.aper_size) | ||
806 | rdev->mc.mc_vram_size = rdev->mc.aper_size; | ||
807 | |||
808 | if (rdev->mc.real_vram_size > rdev->mc.aper_size) | ||
809 | rdev->mc.real_vram_size = rdev->mc.aper_size; | ||
810 | |||
804 | if (rdev->flags & RADEON_IS_AGP) { | 811 | if (rdev->flags & RADEON_IS_AGP) { |
805 | r = radeon_agp_init(rdev); | 812 | r = radeon_agp_init(rdev); |
806 | if (r) | 813 | if (r) |
diff --git a/drivers/hwmon/fschmd.c b/drivers/hwmon/fschmd.c index ea955edde87e..2a7a85a6dc36 100644 --- a/drivers/hwmon/fschmd.c +++ b/drivers/hwmon/fschmd.c | |||
@@ -915,7 +915,7 @@ static int watchdog_ioctl(struct inode *inode, struct file *filp, | |||
915 | return ret; | 915 | return ret; |
916 | } | 916 | } |
917 | 917 | ||
918 | static struct file_operations watchdog_fops = { | 918 | static const struct file_operations watchdog_fops = { |
919 | .owner = THIS_MODULE, | 919 | .owner = THIS_MODULE, |
920 | .llseek = no_llseek, | 920 | .llseek = no_llseek, |
921 | .open = watchdog_open, | 921 | .open = watchdog_open, |
diff --git a/drivers/input/input.c b/drivers/input/input.c index e828aab7dace..16ec33f27c5d 100644 --- a/drivers/input/input.c +++ b/drivers/input/input.c | |||
@@ -1273,6 +1273,7 @@ static int input_dev_uevent(struct device *device, struct kobj_uevent_env *env) | |||
1273 | } \ | 1273 | } \ |
1274 | } while (0) | 1274 | } while (0) |
1275 | 1275 | ||
1276 | #ifdef CONFIG_PM | ||
1276 | static void input_dev_reset(struct input_dev *dev, bool activate) | 1277 | static void input_dev_reset(struct input_dev *dev, bool activate) |
1277 | { | 1278 | { |
1278 | if (!dev->event) | 1279 | if (!dev->event) |
@@ -1287,7 +1288,6 @@ static void input_dev_reset(struct input_dev *dev, bool activate) | |||
1287 | } | 1288 | } |
1288 | } | 1289 | } |
1289 | 1290 | ||
1290 | #ifdef CONFIG_PM | ||
1291 | static int input_dev_suspend(struct device *dev) | 1291 | static int input_dev_suspend(struct device *dev) |
1292 | { | 1292 | { |
1293 | struct input_dev *input_dev = to_input_dev(dev); | 1293 | struct input_dev *input_dev = to_input_dev(dev); |
diff --git a/drivers/isdn/hardware/mISDN/Kconfig b/drivers/isdn/hardware/mISDN/Kconfig index bde55d7287fa..eadc1cd34a20 100644 --- a/drivers/isdn/hardware/mISDN/Kconfig +++ b/drivers/isdn/hardware/mISDN/Kconfig | |||
@@ -78,6 +78,7 @@ config MISDN_NETJET | |||
78 | depends on PCI | 78 | depends on PCI |
79 | select MISDN_IPAC | 79 | select MISDN_IPAC |
80 | select ISDN_HDLC | 80 | select ISDN_HDLC |
81 | select ISDN_I4L | ||
81 | help | 82 | help |
82 | Enable support for Traverse Technologies NETJet PCI cards. | 83 | Enable support for Traverse Technologies NETJet PCI cards. |
83 | 84 | ||
diff --git a/drivers/isdn/i4l/Kconfig b/drivers/isdn/i4l/Kconfig index dd744ffd240b..07c4e49f9e77 100644 --- a/drivers/isdn/i4l/Kconfig +++ b/drivers/isdn/i4l/Kconfig | |||
@@ -141,8 +141,7 @@ endmenu | |||
141 | endif | 141 | endif |
142 | 142 | ||
143 | config ISDN_HDLC | 143 | config ISDN_HDLC |
144 | tristate | 144 | tristate |
145 | depends on HISAX_ST5481 | ||
146 | select CRC_CCITT | 145 | select CRC_CCITT |
147 | select BITREVERSE | 146 | select BITREVERSE |
148 | 147 | ||
diff --git a/drivers/isdn/mISDN/socket.c b/drivers/isdn/mISDN/socket.c index c36f52137456..feb0fa45b664 100644 --- a/drivers/isdn/mISDN/socket.c +++ b/drivers/isdn/mISDN/socket.c | |||
@@ -415,7 +415,7 @@ data_sock_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg) | |||
415 | } | 415 | } |
416 | 416 | ||
417 | static int data_sock_setsockopt(struct socket *sock, int level, int optname, | 417 | static int data_sock_setsockopt(struct socket *sock, int level, int optname, |
418 | char __user *optval, int len) | 418 | char __user *optval, unsigned int len) |
419 | { | 419 | { |
420 | struct sock *sk = sock->sk; | 420 | struct sock *sk = sock->sk; |
421 | int err = 0, opt = 0; | 421 | int err = 0, opt = 0; |
diff --git a/drivers/lguest/lguest_user.c b/drivers/lguest/lguest_user.c index b4d3f7ca554f..bd1632388e4a 100644 --- a/drivers/lguest/lguest_user.c +++ b/drivers/lguest/lguest_user.c | |||
@@ -508,7 +508,7 @@ static int close(struct inode *inode, struct file *file) | |||
508 | * uses: reading and writing a character device called /dev/lguest. All the | 508 | * uses: reading and writing a character device called /dev/lguest. All the |
509 | * work happens in the read(), write() and close() routines: | 509 | * work happens in the read(), write() and close() routines: |
510 | */ | 510 | */ |
511 | static struct file_operations lguest_fops = { | 511 | static const struct file_operations lguest_fops = { |
512 | .owner = THIS_MODULE, | 512 | .owner = THIS_MODULE, |
513 | .release = close, | 513 | .release = close, |
514 | .write = write, | 514 | .write = write, |
diff --git a/drivers/md/dm-log-userspace-transfer.c b/drivers/md/dm-log-userspace-transfer.c index ba0edad2d048..54abf9e303b7 100644 --- a/drivers/md/dm-log-userspace-transfer.c +++ b/drivers/md/dm-log-userspace-transfer.c | |||
@@ -129,11 +129,13 @@ static int fill_pkg(struct cn_msg *msg, struct dm_ulog_request *tfr) | |||
129 | * This is the connector callback that delivers data | 129 | * This is the connector callback that delivers data |
130 | * that was sent from userspace. | 130 | * that was sent from userspace. |
131 | */ | 131 | */ |
132 | static void cn_ulog_callback(void *data) | 132 | static void cn_ulog_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp) |
133 | { | 133 | { |
134 | struct cn_msg *msg = (struct cn_msg *)data; | ||
135 | struct dm_ulog_request *tfr = (struct dm_ulog_request *)(msg + 1); | 134 | struct dm_ulog_request *tfr = (struct dm_ulog_request *)(msg + 1); |
136 | 135 | ||
136 | if (!cap_raised(nsp->eff_cap, CAP_SYS_ADMIN)) | ||
137 | return; | ||
138 | |||
137 | spin_lock(&receiving_list_lock); | 139 | spin_lock(&receiving_list_lock); |
138 | if (msg->len == 0) | 140 | if (msg->len == 0) |
139 | fill_pkg(msg, NULL); | 141 | fill_pkg(msg, NULL); |
diff --git a/drivers/media/dvb/dvb-core/dmxdev.c b/drivers/media/dvb/dvb-core/dmxdev.c index 3750ff48cba1..516414983593 100644 --- a/drivers/media/dvb/dvb-core/dmxdev.c +++ b/drivers/media/dvb/dvb-core/dmxdev.c | |||
@@ -1203,7 +1203,7 @@ static unsigned int dvb_dvr_poll(struct file *file, poll_table *wait) | |||
1203 | return mask; | 1203 | return mask; |
1204 | } | 1204 | } |
1205 | 1205 | ||
1206 | static struct file_operations dvb_dvr_fops = { | 1206 | static const struct file_operations dvb_dvr_fops = { |
1207 | .owner = THIS_MODULE, | 1207 | .owner = THIS_MODULE, |
1208 | .read = dvb_dvr_read, | 1208 | .read = dvb_dvr_read, |
1209 | .write = dvb_dvr_write, | 1209 | .write = dvb_dvr_write, |
diff --git a/drivers/media/dvb/firewire/firedtv-ci.c b/drivers/media/dvb/firewire/firedtv-ci.c index eeb80d0ea3ff..853e04b7cb36 100644 --- a/drivers/media/dvb/firewire/firedtv-ci.c +++ b/drivers/media/dvb/firewire/firedtv-ci.c | |||
@@ -215,7 +215,7 @@ static unsigned int fdtv_ca_io_poll(struct file *file, poll_table *wait) | |||
215 | return POLLIN; | 215 | return POLLIN; |
216 | } | 216 | } |
217 | 217 | ||
218 | static struct file_operations fdtv_ca_fops = { | 218 | static const struct file_operations fdtv_ca_fops = { |
219 | .owner = THIS_MODULE, | 219 | .owner = THIS_MODULE, |
220 | .ioctl = dvb_generic_ioctl, | 220 | .ioctl = dvb_generic_ioctl, |
221 | .open = dvb_generic_open, | 221 | .open = dvb_generic_open, |
diff --git a/drivers/misc/phantom.c b/drivers/misc/phantom.c index fa57b67593ae..90a95ce8dc34 100644 --- a/drivers/misc/phantom.c +++ b/drivers/misc/phantom.c | |||
@@ -271,7 +271,7 @@ static unsigned int phantom_poll(struct file *file, poll_table *wait) | |||
271 | return mask; | 271 | return mask; |
272 | } | 272 | } |
273 | 273 | ||
274 | static struct file_operations phantom_file_ops = { | 274 | static const struct file_operations phantom_file_ops = { |
275 | .open = phantom_open, | 275 | .open = phantom_open, |
276 | .release = phantom_release, | 276 | .release = phantom_release, |
277 | .unlocked_ioctl = phantom_ioctl, | 277 | .unlocked_ioctl = phantom_ioctl, |
diff --git a/drivers/misc/sgi-gru/grufile.c b/drivers/misc/sgi-gru/grufile.c index 300e7ba391a0..41c8fe2a928c 100644 --- a/drivers/misc/sgi-gru/grufile.c +++ b/drivers/misc/sgi-gru/grufile.c | |||
@@ -53,7 +53,6 @@ struct gru_stats_s gru_stats; | |||
53 | /* Guaranteed user available resources on each node */ | 53 | /* Guaranteed user available resources on each node */ |
54 | static int max_user_cbrs, max_user_dsr_bytes; | 54 | static int max_user_cbrs, max_user_dsr_bytes; |
55 | 55 | ||
56 | static struct file_operations gru_fops; | ||
57 | static struct miscdevice gru_miscdev; | 56 | static struct miscdevice gru_miscdev; |
58 | 57 | ||
59 | 58 | ||
@@ -426,7 +425,7 @@ static void __exit gru_exit(void) | |||
426 | gru_proc_exit(); | 425 | gru_proc_exit(); |
427 | } | 426 | } |
428 | 427 | ||
429 | static struct file_operations gru_fops = { | 428 | static const struct file_operations gru_fops = { |
430 | .owner = THIS_MODULE, | 429 | .owner = THIS_MODULE, |
431 | .unlocked_ioctl = gru_file_unlocked_ioctl, | 430 | .unlocked_ioctl = gru_file_unlocked_ioctl, |
432 | .mmap = gru_file_mmap, | 431 | .mmap = gru_file_mmap, |
diff --git a/drivers/mmc/core/debugfs.c b/drivers/mmc/core/debugfs.c index 610dbd1fcc82..96d10f40fb23 100644 --- a/drivers/mmc/core/debugfs.c +++ b/drivers/mmc/core/debugfs.c | |||
@@ -240,7 +240,7 @@ static int mmc_ext_csd_release(struct inode *inode, struct file *file) | |||
240 | return 0; | 240 | return 0; |
241 | } | 241 | } |
242 | 242 | ||
243 | static struct file_operations mmc_dbg_ext_csd_fops = { | 243 | static const struct file_operations mmc_dbg_ext_csd_fops = { |
244 | .open = mmc_ext_csd_open, | 244 | .open = mmc_ext_csd_open, |
245 | .read = mmc_ext_csd_read, | 245 | .read = mmc_ext_csd_read, |
246 | .release = mmc_ext_csd_release, | 246 | .release = mmc_ext_csd_release, |
diff --git a/drivers/mmc/core/sdio_cis.c b/drivers/mmc/core/sdio_cis.c index 6636354b48ce..e1035c895808 100644 --- a/drivers/mmc/core/sdio_cis.c +++ b/drivers/mmc/core/sdio_cis.c | |||
@@ -98,6 +98,22 @@ static const unsigned char speed_val[16] = | |||
98 | static const unsigned int speed_unit[8] = | 98 | static const unsigned int speed_unit[8] = |
99 | { 10000, 100000, 1000000, 10000000, 0, 0, 0, 0 }; | 99 | { 10000, 100000, 1000000, 10000000, 0, 0, 0, 0 }; |
100 | 100 | ||
101 | /* FUNCE tuples with these types get passed to SDIO drivers */ | ||
102 | static const unsigned char funce_type_whitelist[] = { | ||
103 | 4 /* CISTPL_FUNCE_LAN_NODE_ID used in Broadcom cards */ | ||
104 | }; | ||
105 | |||
106 | static int cistpl_funce_whitelisted(unsigned char type) | ||
107 | { | ||
108 | int i; | ||
109 | |||
110 | for (i = 0; i < ARRAY_SIZE(funce_type_whitelist); i++) { | ||
111 | if (funce_type_whitelist[i] == type) | ||
112 | return 1; | ||
113 | } | ||
114 | return 0; | ||
115 | } | ||
116 | |||
101 | static int cistpl_funce_common(struct mmc_card *card, | 117 | static int cistpl_funce_common(struct mmc_card *card, |
102 | const unsigned char *buf, unsigned size) | 118 | const unsigned char *buf, unsigned size) |
103 | { | 119 | { |
@@ -120,6 +136,10 @@ static int cistpl_funce_func(struct sdio_func *func, | |||
120 | unsigned vsn; | 136 | unsigned vsn; |
121 | unsigned min_size; | 137 | unsigned min_size; |
122 | 138 | ||
139 | /* let SDIO drivers take care of whitelisted FUNCE tuples */ | ||
140 | if (cistpl_funce_whitelisted(buf[0])) | ||
141 | return -EILSEQ; | ||
142 | |||
123 | vsn = func->card->cccr.sdio_vsn; | 143 | vsn = func->card->cccr.sdio_vsn; |
124 | min_size = (vsn == SDIO_SDIO_REV_1_00) ? 28 : 42; | 144 | min_size = (vsn == SDIO_SDIO_REV_1_00) ? 28 : 42; |
125 | 145 | ||
@@ -154,13 +174,12 @@ static int cistpl_funce(struct mmc_card *card, struct sdio_func *func, | |||
154 | else | 174 | else |
155 | ret = cistpl_funce_common(card, buf, size); | 175 | ret = cistpl_funce_common(card, buf, size); |
156 | 176 | ||
157 | if (ret) { | 177 | if (ret && ret != -EILSEQ) { |
158 | printk(KERN_ERR "%s: bad CISTPL_FUNCE size %u " | 178 | printk(KERN_ERR "%s: bad CISTPL_FUNCE size %u " |
159 | "type %u\n", mmc_hostname(card->host), size, buf[0]); | 179 | "type %u\n", mmc_hostname(card->host), size, buf[0]); |
160 | return ret; | ||
161 | } | 180 | } |
162 | 181 | ||
163 | return 0; | 182 | return ret; |
164 | } | 183 | } |
165 | 184 | ||
166 | typedef int (tpl_parse_t)(struct mmc_card *, struct sdio_func *, | 185 | typedef int (tpl_parse_t)(struct mmc_card *, struct sdio_func *, |
@@ -253,21 +272,12 @@ static int sdio_read_cis(struct mmc_card *card, struct sdio_func *func) | |||
253 | for (i = 0; i < ARRAY_SIZE(cis_tpl_list); i++) | 272 | for (i = 0; i < ARRAY_SIZE(cis_tpl_list); i++) |
254 | if (cis_tpl_list[i].code == tpl_code) | 273 | if (cis_tpl_list[i].code == tpl_code) |
255 | break; | 274 | break; |
256 | if (i >= ARRAY_SIZE(cis_tpl_list)) { | 275 | if (i < ARRAY_SIZE(cis_tpl_list)) { |
257 | /* this tuple is unknown to the core */ | ||
258 | this->next = NULL; | ||
259 | this->code = tpl_code; | ||
260 | this->size = tpl_link; | ||
261 | *prev = this; | ||
262 | prev = &this->next; | ||
263 | printk(KERN_DEBUG | ||
264 | "%s: queuing CIS tuple 0x%02x length %u\n", | ||
265 | mmc_hostname(card->host), tpl_code, tpl_link); | ||
266 | } else { | ||
267 | const struct cis_tpl *tpl = cis_tpl_list + i; | 276 | const struct cis_tpl *tpl = cis_tpl_list + i; |
268 | if (tpl_link < tpl->min_size) { | 277 | if (tpl_link < tpl->min_size) { |
269 | printk(KERN_ERR | 278 | printk(KERN_ERR |
270 | "%s: bad CIS tuple 0x%02x (length = %u, expected >= %u)\n", | 279 | "%s: bad CIS tuple 0x%02x" |
280 | " (length = %u, expected >= %u)\n", | ||
271 | mmc_hostname(card->host), | 281 | mmc_hostname(card->host), |
272 | tpl_code, tpl_link, tpl->min_size); | 282 | tpl_code, tpl_link, tpl->min_size); |
273 | ret = -EINVAL; | 283 | ret = -EINVAL; |
@@ -275,7 +285,30 @@ static int sdio_read_cis(struct mmc_card *card, struct sdio_func *func) | |||
275 | ret = tpl->parse(card, func, | 285 | ret = tpl->parse(card, func, |
276 | this->data, tpl_link); | 286 | this->data, tpl_link); |
277 | } | 287 | } |
278 | kfree(this); | 288 | /* |
289 | * We don't need the tuple anymore if it was | ||
290 | * successfully parsed by the SDIO core or if it is | ||
291 | * not going to be parsed by SDIO drivers. | ||
292 | */ | ||
293 | if (!ret || ret != -EILSEQ) | ||
294 | kfree(this); | ||
295 | } else { | ||
296 | /* unknown tuple */ | ||
297 | ret = -EILSEQ; | ||
298 | } | ||
299 | |||
300 | if (ret == -EILSEQ) { | ||
301 | /* this tuple is unknown to the core or whitelisted */ | ||
302 | this->next = NULL; | ||
303 | this->code = tpl_code; | ||
304 | this->size = tpl_link; | ||
305 | *prev = this; | ||
306 | prev = &this->next; | ||
307 | printk(KERN_DEBUG | ||
308 | "%s: queuing CIS tuple 0x%02x length %u\n", | ||
309 | mmc_hostname(card->host), tpl_code, tpl_link); | ||
310 | /* keep on analyzing tuples */ | ||
311 | ret = 0; | ||
279 | } | 312 | } |
280 | 313 | ||
281 | ptr += tpl_link; | 314 | ptr += tpl_link; |
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 7cb057f3f883..432ae8358c86 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig | |||
@@ -276,6 +276,47 @@ config MMC_S3C | |||
276 | 276 | ||
277 | If unsure, say N. | 277 | If unsure, say N. |
278 | 278 | ||
279 | config MMC_S3C_HW_SDIO_IRQ | ||
280 | bool "Hardware support for SDIO IRQ" | ||
281 | depends on MMC_S3C | ||
282 | help | ||
283 | Enable the hardware support for SDIO interrupts instead of using | ||
284 | the generic polling code. | ||
285 | |||
286 | choice | ||
287 | prompt "Samsung S3C SD/MMC transfer code" | ||
288 | depends on MMC_S3C | ||
289 | |||
290 | config MMC_S3C_PIO | ||
291 | bool "Use PIO transfers only" | ||
292 | help | ||
293 | Use PIO to transfer data between memory and the hardware. | ||
294 | |||
295 | PIO is slower than DMA as it requires CPU instructions to | ||
296 | move the data. This has been the traditional default for | ||
297 | the S3C MCI driver. | ||
298 | |||
299 | config MMC_S3C_DMA | ||
300 | bool "Use DMA transfers only (EXPERIMENTAL)" | ||
301 | depends on EXPERIMENTAL | ||
302 | help | ||
303 | Use DMA to transfer data between memory and the hardare. | ||
304 | |||
305 | Currently, the DMA support in this driver seems to not be | ||
306 | working properly and needs to be debugged before this | ||
307 | option is useful. | ||
308 | |||
309 | config MMC_S3C_PIODMA | ||
310 | bool "Support for both PIO and DMA (EXPERIMENTAL)" | ||
311 | help | ||
312 | Compile both the PIO and DMA transfer routines into the | ||
313 | driver and let the platform select at run-time which one | ||
314 | is best. | ||
315 | |||
316 | See notes for the DMA option. | ||
317 | |||
318 | endchoice | ||
319 | |||
279 | config MMC_SDRICOH_CS | 320 | config MMC_SDRICOH_CS |
280 | tristate "MMC/SD driver for Ricoh Bay1Controllers (EXPERIMENTAL)" | 321 | tristate "MMC/SD driver for Ricoh Bay1Controllers (EXPERIMENTAL)" |
281 | depends on EXPERIMENTAL && PCI && PCMCIA | 322 | depends on EXPERIMENTAL && PCI && PCMCIA |
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 3d1e5329da12..705a5894a6bb 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c | |||
@@ -678,7 +678,6 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) | |||
678 | writel(0, host->base + MMCIMASK1); | 678 | writel(0, host->base + MMCIMASK1); |
679 | writel(0xfff, host->base + MMCICLEAR); | 679 | writel(0xfff, host->base + MMCICLEAR); |
680 | 680 | ||
681 | #ifdef CONFIG_GPIOLIB | ||
682 | if (gpio_is_valid(plat->gpio_cd)) { | 681 | if (gpio_is_valid(plat->gpio_cd)) { |
683 | ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); | 682 | ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); |
684 | if (ret == 0) | 683 | if (ret == 0) |
@@ -697,7 +696,6 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) | |||
697 | else if (ret != -ENOSYS) | 696 | else if (ret != -ENOSYS) |
698 | goto err_gpio_wp; | 697 | goto err_gpio_wp; |
699 | } | 698 | } |
700 | #endif | ||
701 | 699 | ||
702 | ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); | 700 | ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); |
703 | if (ret) | 701 | if (ret) |
diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c index 8c08cd7efa7f..99b74a351020 100644 --- a/drivers/mmc/host/s3cmci.c +++ b/drivers/mmc/host/s3cmci.c | |||
@@ -17,6 +17,8 @@ | |||
17 | #include <linux/mmc/host.h> | 17 | #include <linux/mmc/host.h> |
18 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
19 | #include <linux/cpufreq.h> | 19 | #include <linux/cpufreq.h> |
20 | #include <linux/debugfs.h> | ||
21 | #include <linux/seq_file.h> | ||
20 | #include <linux/gpio.h> | 22 | #include <linux/gpio.h> |
21 | #include <linux/irq.h> | 23 | #include <linux/irq.h> |
22 | #include <linux/io.h> | 24 | #include <linux/io.h> |
@@ -58,8 +60,6 @@ static const int dbgmap_debug = dbg_err | dbg_debug; | |||
58 | dev_dbg(&host->pdev->dev, args); \ | 60 | dev_dbg(&host->pdev->dev, args); \ |
59 | } while (0) | 61 | } while (0) |
60 | 62 | ||
61 | #define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1) | ||
62 | |||
63 | static struct s3c2410_dma_client s3cmci_dma_client = { | 63 | static struct s3c2410_dma_client s3cmci_dma_client = { |
64 | .name = "s3c-mci", | 64 | .name = "s3c-mci", |
65 | }; | 65 | }; |
@@ -164,6 +164,40 @@ static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { } | |||
164 | 164 | ||
165 | #endif /* CONFIG_MMC_DEBUG */ | 165 | #endif /* CONFIG_MMC_DEBUG */ |
166 | 166 | ||
167 | /** | ||
168 | * s3cmci_host_usedma - return whether the host is using dma or pio | ||
169 | * @host: The host state | ||
170 | * | ||
171 | * Return true if the host is using DMA to transfer data, else false | ||
172 | * to use PIO mode. Will return static data depending on the driver | ||
173 | * configuration. | ||
174 | */ | ||
175 | static inline bool s3cmci_host_usedma(struct s3cmci_host *host) | ||
176 | { | ||
177 | #ifdef CONFIG_MMC_S3C_PIO | ||
178 | return false; | ||
179 | #elif defined(CONFIG_MMC_S3C_DMA) | ||
180 | return true; | ||
181 | #else | ||
182 | return host->dodma; | ||
183 | #endif | ||
184 | } | ||
185 | |||
186 | /** | ||
187 | * s3cmci_host_canpio - return true if host has pio code available | ||
188 | * | ||
189 | * Return true if the driver has been compiled with the PIO support code | ||
190 | * available. | ||
191 | */ | ||
192 | static inline bool s3cmci_host_canpio(void) | ||
193 | { | ||
194 | #ifdef CONFIG_MMC_S3C_PIO | ||
195 | return true; | ||
196 | #else | ||
197 | return false; | ||
198 | #endif | ||
199 | } | ||
200 | |||
167 | static inline u32 enable_imask(struct s3cmci_host *host, u32 imask) | 201 | static inline u32 enable_imask(struct s3cmci_host *host, u32 imask) |
168 | { | 202 | { |
169 | u32 newmask; | 203 | u32 newmask; |
@@ -190,7 +224,33 @@ static inline u32 disable_imask(struct s3cmci_host *host, u32 imask) | |||
190 | 224 | ||
191 | static inline void clear_imask(struct s3cmci_host *host) | 225 | static inline void clear_imask(struct s3cmci_host *host) |
192 | { | 226 | { |
193 | writel(0, host->base + host->sdiimsk); | 227 | u32 mask = readl(host->base + host->sdiimsk); |
228 | |||
229 | /* preserve the SDIO IRQ mask state */ | ||
230 | mask &= S3C2410_SDIIMSK_SDIOIRQ; | ||
231 | writel(mask, host->base + host->sdiimsk); | ||
232 | } | ||
233 | |||
234 | /** | ||
235 | * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled | ||
236 | * @host: The host to check. | ||
237 | * | ||
238 | * Test to see if the SDIO interrupt is being signalled in case the | ||
239 | * controller has failed to re-detect a card interrupt. Read GPE8 and | ||
240 | * see if it is low and if so, signal a SDIO interrupt. | ||
241 | * | ||
242 | * This is currently called if a request is finished (we assume that the | ||
243 | * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is | ||
244 | * already being indicated. | ||
245 | */ | ||
246 | static void s3cmci_check_sdio_irq(struct s3cmci_host *host) | ||
247 | { | ||
248 | if (host->sdio_irqen) { | ||
249 | if (gpio_get_value(S3C2410_GPE(8)) == 0) { | ||
250 | printk(KERN_DEBUG "%s: signalling irq\n", __func__); | ||
251 | mmc_signal_sdio_irq(host->mmc); | ||
252 | } | ||
253 | } | ||
194 | } | 254 | } |
195 | 255 | ||
196 | static inline int get_data_buffer(struct s3cmci_host *host, | 256 | static inline int get_data_buffer(struct s3cmci_host *host, |
@@ -238,6 +298,64 @@ static inline u32 fifo_free(struct s3cmci_host *host) | |||
238 | return 63 - fifostat; | 298 | return 63 - fifostat; |
239 | } | 299 | } |
240 | 300 | ||
301 | /** | ||
302 | * s3cmci_enable_irq - enable IRQ, after having disabled it. | ||
303 | * @host: The device state. | ||
304 | * @more: True if more IRQs are expected from transfer. | ||
305 | * | ||
306 | * Enable the main IRQ if needed after it has been disabled. | ||
307 | * | ||
308 | * The IRQ can be one of the following states: | ||
309 | * - disabled during IDLE | ||
310 | * - disabled whilst processing data | ||
311 | * - enabled during transfer | ||
312 | * - enabled whilst awaiting SDIO interrupt detection | ||
313 | */ | ||
314 | static void s3cmci_enable_irq(struct s3cmci_host *host, bool more) | ||
315 | { | ||
316 | unsigned long flags; | ||
317 | bool enable = false; | ||
318 | |||
319 | local_irq_save(flags); | ||
320 | |||
321 | host->irq_enabled = more; | ||
322 | host->irq_disabled = false; | ||
323 | |||
324 | enable = more | host->sdio_irqen; | ||
325 | |||
326 | if (host->irq_state != enable) { | ||
327 | host->irq_state = enable; | ||
328 | |||
329 | if (enable) | ||
330 | enable_irq(host->irq); | ||
331 | else | ||
332 | disable_irq(host->irq); | ||
333 | } | ||
334 | |||
335 | local_irq_restore(flags); | ||
336 | } | ||
337 | |||
338 | /** | ||
339 | * | ||
340 | */ | ||
341 | static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer) | ||
342 | { | ||
343 | unsigned long flags; | ||
344 | |||
345 | local_irq_save(flags); | ||
346 | |||
347 | //printk(KERN_DEBUG "%s: transfer %d\n", __func__, transfer); | ||
348 | |||
349 | host->irq_disabled = transfer; | ||
350 | |||
351 | if (transfer && host->irq_state) { | ||
352 | host->irq_state = false; | ||
353 | disable_irq(host->irq); | ||
354 | } | ||
355 | |||
356 | local_irq_restore(flags); | ||
357 | } | ||
358 | |||
241 | static void do_pio_read(struct s3cmci_host *host) | 359 | static void do_pio_read(struct s3cmci_host *host) |
242 | { | 360 | { |
243 | int res; | 361 | int res; |
@@ -374,8 +492,7 @@ static void pio_tasklet(unsigned long data) | |||
374 | { | 492 | { |
375 | struct s3cmci_host *host = (struct s3cmci_host *) data; | 493 | struct s3cmci_host *host = (struct s3cmci_host *) data; |
376 | 494 | ||
377 | 495 | s3cmci_disable_irq(host, true); | |
378 | disable_irq(host->irq); | ||
379 | 496 | ||
380 | if (host->pio_active == XFER_WRITE) | 497 | if (host->pio_active == XFER_WRITE) |
381 | do_pio_write(host); | 498 | do_pio_write(host); |
@@ -395,9 +512,10 @@ static void pio_tasklet(unsigned long data) | |||
395 | host->mrq->data->error = -EINVAL; | 512 | host->mrq->data->error = -EINVAL; |
396 | } | 513 | } |
397 | 514 | ||
515 | s3cmci_enable_irq(host, false); | ||
398 | finalize_request(host); | 516 | finalize_request(host); |
399 | } else | 517 | } else |
400 | enable_irq(host->irq); | 518 | s3cmci_enable_irq(host, true); |
401 | } | 519 | } |
402 | 520 | ||
403 | /* | 521 | /* |
@@ -432,17 +550,27 @@ static irqreturn_t s3cmci_irq(int irq, void *dev_id) | |||
432 | struct s3cmci_host *host = dev_id; | 550 | struct s3cmci_host *host = dev_id; |
433 | struct mmc_command *cmd; | 551 | struct mmc_command *cmd; |
434 | u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk; | 552 | u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk; |
435 | u32 mci_cclear, mci_dclear; | 553 | u32 mci_cclear = 0, mci_dclear; |
436 | unsigned long iflags; | 554 | unsigned long iflags; |
437 | 555 | ||
556 | mci_dsta = readl(host->base + S3C2410_SDIDSTA); | ||
557 | mci_imsk = readl(host->base + host->sdiimsk); | ||
558 | |||
559 | if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) { | ||
560 | if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) { | ||
561 | mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT; | ||
562 | writel(mci_dclear, host->base + S3C2410_SDIDSTA); | ||
563 | |||
564 | mmc_signal_sdio_irq(host->mmc); | ||
565 | return IRQ_HANDLED; | ||
566 | } | ||
567 | } | ||
568 | |||
438 | spin_lock_irqsave(&host->complete_lock, iflags); | 569 | spin_lock_irqsave(&host->complete_lock, iflags); |
439 | 570 | ||
440 | mci_csta = readl(host->base + S3C2410_SDICMDSTAT); | 571 | mci_csta = readl(host->base + S3C2410_SDICMDSTAT); |
441 | mci_dsta = readl(host->base + S3C2410_SDIDSTA); | ||
442 | mci_dcnt = readl(host->base + S3C2410_SDIDCNT); | 572 | mci_dcnt = readl(host->base + S3C2410_SDIDCNT); |
443 | mci_fsta = readl(host->base + S3C2410_SDIFSTA); | 573 | mci_fsta = readl(host->base + S3C2410_SDIFSTA); |
444 | mci_imsk = readl(host->base + host->sdiimsk); | ||
445 | mci_cclear = 0; | ||
446 | mci_dclear = 0; | 574 | mci_dclear = 0; |
447 | 575 | ||
448 | if ((host->complete_what == COMPLETION_NONE) || | 576 | if ((host->complete_what == COMPLETION_NONE) || |
@@ -466,7 +594,7 @@ static irqreturn_t s3cmci_irq(int irq, void *dev_id) | |||
466 | goto irq_out; | 594 | goto irq_out; |
467 | } | 595 | } |
468 | 596 | ||
469 | if (!host->dodma) { | 597 | if (!s3cmci_host_usedma(host)) { |
470 | if ((host->pio_active == XFER_WRITE) && | 598 | if ((host->pio_active == XFER_WRITE) && |
471 | (mci_fsta & S3C2410_SDIFSTA_TFDET)) { | 599 | (mci_fsta & S3C2410_SDIFSTA_TFDET)) { |
472 | 600 | ||
@@ -673,6 +801,7 @@ static void s3cmci_dma_done_callback(struct s3c2410_dma_chan *dma_ch, | |||
673 | dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n", | 801 | dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n", |
674 | size, mci_dsta, mci_dcnt); | 802 | size, mci_dsta, mci_dcnt); |
675 | 803 | ||
804 | host->dma_complete = 1; | ||
676 | host->complete_what = COMPLETION_FINALIZE; | 805 | host->complete_what = COMPLETION_FINALIZE; |
677 | 806 | ||
678 | out: | 807 | out: |
@@ -683,9 +812,9 @@ out: | |||
683 | fail_request: | 812 | fail_request: |
684 | host->mrq->data->error = -EINVAL; | 813 | host->mrq->data->error = -EINVAL; |
685 | host->complete_what = COMPLETION_FINALIZE; | 814 | host->complete_what = COMPLETION_FINALIZE; |
686 | writel(0, host->base + host->sdiimsk); | 815 | clear_imask(host); |
687 | goto out; | ||
688 | 816 | ||
817 | goto out; | ||
689 | } | 818 | } |
690 | 819 | ||
691 | static void finalize_request(struct s3cmci_host *host) | 820 | static void finalize_request(struct s3cmci_host *host) |
@@ -702,8 +831,9 @@ static void finalize_request(struct s3cmci_host *host) | |||
702 | 831 | ||
703 | if (cmd->data && (cmd->error == 0) && | 832 | if (cmd->data && (cmd->error == 0) && |
704 | (cmd->data->error == 0)) { | 833 | (cmd->data->error == 0)) { |
705 | if (host->dodma && (!host->dma_complete)) { | 834 | if (s3cmci_host_usedma(host) && (!host->dma_complete)) { |
706 | dbg(host, dbg_dma, "DMA Missing!\n"); | 835 | dbg(host, dbg_dma, "DMA Missing (%d)!\n", |
836 | host->dma_complete); | ||
707 | return; | 837 | return; |
708 | } | 838 | } |
709 | } | 839 | } |
@@ -728,7 +858,7 @@ static void finalize_request(struct s3cmci_host *host) | |||
728 | writel(0, host->base + S3C2410_SDICMDARG); | 858 | writel(0, host->base + S3C2410_SDICMDARG); |
729 | writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON); | 859 | writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON); |
730 | writel(0, host->base + S3C2410_SDICMDCON); | 860 | writel(0, host->base + S3C2410_SDICMDCON); |
731 | writel(0, host->base + host->sdiimsk); | 861 | clear_imask(host); |
732 | 862 | ||
733 | if (cmd->data && cmd->error) | 863 | if (cmd->data && cmd->error) |
734 | cmd->data->error = cmd->error; | 864 | cmd->data->error = cmd->error; |
@@ -754,7 +884,7 @@ static void finalize_request(struct s3cmci_host *host) | |||
754 | /* If we had an error while transfering data we flush the | 884 | /* If we had an error while transfering data we flush the |
755 | * DMA channel and the fifo to clear out any garbage. */ | 885 | * DMA channel and the fifo to clear out any garbage. */ |
756 | if (mrq->data->error != 0) { | 886 | if (mrq->data->error != 0) { |
757 | if (host->dodma) | 887 | if (s3cmci_host_usedma(host)) |
758 | s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH); | 888 | s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH); |
759 | 889 | ||
760 | if (host->is2440) { | 890 | if (host->is2440) { |
@@ -776,6 +906,8 @@ static void finalize_request(struct s3cmci_host *host) | |||
776 | request_done: | 906 | request_done: |
777 | host->complete_what = COMPLETION_NONE; | 907 | host->complete_what = COMPLETION_NONE; |
778 | host->mrq = NULL; | 908 | host->mrq = NULL; |
909 | |||
910 | s3cmci_check_sdio_irq(host); | ||
779 | mmc_request_done(host->mmc, mrq); | 911 | mmc_request_done(host->mmc, mrq); |
780 | } | 912 | } |
781 | 913 | ||
@@ -872,7 +1004,7 @@ static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data) | |||
872 | 1004 | ||
873 | dcon = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK; | 1005 | dcon = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK; |
874 | 1006 | ||
875 | if (host->dodma) | 1007 | if (s3cmci_host_usedma(host)) |
876 | dcon |= S3C2410_SDIDCON_DMAEN; | 1008 | dcon |= S3C2410_SDIDCON_DMAEN; |
877 | 1009 | ||
878 | if (host->bus_width == MMC_BUS_WIDTH_4) | 1010 | if (host->bus_width == MMC_BUS_WIDTH_4) |
@@ -950,7 +1082,7 @@ static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data) | |||
950 | static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data) | 1082 | static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data) |
951 | { | 1083 | { |
952 | int dma_len, i; | 1084 | int dma_len, i; |
953 | int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0; | 1085 | int rw = data->flags & MMC_DATA_WRITE; |
954 | 1086 | ||
955 | BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR); | 1087 | BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR); |
956 | 1088 | ||
@@ -958,7 +1090,7 @@ static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data) | |||
958 | s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH); | 1090 | s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH); |
959 | 1091 | ||
960 | dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, | 1092 | dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, |
961 | (rw) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | 1093 | rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
962 | 1094 | ||
963 | if (dma_len == 0) | 1095 | if (dma_len == 0) |
964 | return -ENOMEM; | 1096 | return -ENOMEM; |
@@ -969,11 +1101,11 @@ static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data) | |||
969 | for (i = 0; i < dma_len; i++) { | 1101 | for (i = 0; i < dma_len; i++) { |
970 | int res; | 1102 | int res; |
971 | 1103 | ||
972 | dbg(host, dbg_dma, "enqueue %i:%u@%u\n", i, | 1104 | dbg(host, dbg_dma, "enqueue %i: %08x@%u\n", i, |
973 | sg_dma_address(&data->sg[i]), | 1105 | sg_dma_address(&data->sg[i]), |
974 | sg_dma_len(&data->sg[i])); | 1106 | sg_dma_len(&data->sg[i])); |
975 | 1107 | ||
976 | res = s3c2410_dma_enqueue(host->dma, (void *) host, | 1108 | res = s3c2410_dma_enqueue(host->dma, host, |
977 | sg_dma_address(&data->sg[i]), | 1109 | sg_dma_address(&data->sg[i]), |
978 | sg_dma_len(&data->sg[i])); | 1110 | sg_dma_len(&data->sg[i])); |
979 | 1111 | ||
@@ -1018,7 +1150,7 @@ static void s3cmci_send_request(struct mmc_host *mmc) | |||
1018 | return; | 1150 | return; |
1019 | } | 1151 | } |
1020 | 1152 | ||
1021 | if (host->dodma) | 1153 | if (s3cmci_host_usedma(host)) |
1022 | res = s3cmci_prepare_dma(host, cmd->data); | 1154 | res = s3cmci_prepare_dma(host, cmd->data); |
1023 | else | 1155 | else |
1024 | res = s3cmci_prepare_pio(host, cmd->data); | 1156 | res = s3cmci_prepare_pio(host, cmd->data); |
@@ -1037,7 +1169,7 @@ static void s3cmci_send_request(struct mmc_host *mmc) | |||
1037 | s3cmci_send_command(host, cmd); | 1169 | s3cmci_send_command(host, cmd); |
1038 | 1170 | ||
1039 | /* Enable Interrupt */ | 1171 | /* Enable Interrupt */ |
1040 | enable_irq(host->irq); | 1172 | s3cmci_enable_irq(host, true); |
1041 | } | 1173 | } |
1042 | 1174 | ||
1043 | static int s3cmci_card_present(struct mmc_host *mmc) | 1175 | static int s3cmci_card_present(struct mmc_host *mmc) |
@@ -1049,7 +1181,7 @@ static int s3cmci_card_present(struct mmc_host *mmc) | |||
1049 | if (pdata->gpio_detect == 0) | 1181 | if (pdata->gpio_detect == 0) |
1050 | return -ENOSYS; | 1182 | return -ENOSYS; |
1051 | 1183 | ||
1052 | ret = s3c2410_gpio_getpin(pdata->gpio_detect) ? 0 : 1; | 1184 | ret = gpio_get_value(pdata->gpio_detect) ? 0 : 1; |
1053 | return ret ^ pdata->detect_invert; | 1185 | return ret ^ pdata->detect_invert; |
1054 | } | 1186 | } |
1055 | 1187 | ||
@@ -1104,12 +1236,12 @@ static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |||
1104 | switch (ios->power_mode) { | 1236 | switch (ios->power_mode) { |
1105 | case MMC_POWER_ON: | 1237 | case MMC_POWER_ON: |
1106 | case MMC_POWER_UP: | 1238 | case MMC_POWER_UP: |
1107 | s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPE5_SDCLK); | 1239 | s3c2410_gpio_cfgpin(S3C2410_GPE(5), S3C2410_GPE5_SDCLK); |
1108 | s3c2410_gpio_cfgpin(S3C2410_GPE6, S3C2410_GPE6_SDCMD); | 1240 | s3c2410_gpio_cfgpin(S3C2410_GPE(6), S3C2410_GPE6_SDCMD); |
1109 | s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2410_GPE7_SDDAT0); | 1241 | s3c2410_gpio_cfgpin(S3C2410_GPE(7), S3C2410_GPE7_SDDAT0); |
1110 | s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1); | 1242 | s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1); |
1111 | s3c2410_gpio_cfgpin(S3C2410_GPE9, S3C2410_GPE9_SDDAT2); | 1243 | s3c2410_gpio_cfgpin(S3C2410_GPE(9), S3C2410_GPE9_SDDAT2); |
1112 | s3c2410_gpio_cfgpin(S3C2410_GPE10, S3C2410_GPE10_SDDAT3); | 1244 | s3c2410_gpio_cfgpin(S3C2410_GPE(10), S3C2410_GPE10_SDDAT3); |
1113 | 1245 | ||
1114 | if (host->pdata->set_power) | 1246 | if (host->pdata->set_power) |
1115 | host->pdata->set_power(ios->power_mode, ios->vdd); | 1247 | host->pdata->set_power(ios->power_mode, ios->vdd); |
@@ -1121,8 +1253,7 @@ static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |||
1121 | 1253 | ||
1122 | case MMC_POWER_OFF: | 1254 | case MMC_POWER_OFF: |
1123 | default: | 1255 | default: |
1124 | s3c2410_gpio_setpin(S3C2410_GPE5, 0); | 1256 | gpio_direction_output(S3C2410_GPE(5), 0); |
1125 | s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPIO_OUTPUT); | ||
1126 | 1257 | ||
1127 | if (host->is2440) | 1258 | if (host->is2440) |
1128 | mci_con |= S3C2440_SDICON_SDRESET; | 1259 | mci_con |= S3C2440_SDICON_SDRESET; |
@@ -1168,7 +1299,7 @@ static int s3cmci_get_ro(struct mmc_host *mmc) | |||
1168 | struct s3c24xx_mci_pdata *pdata = host->pdata; | 1299 | struct s3c24xx_mci_pdata *pdata = host->pdata; |
1169 | int ret; | 1300 | int ret; |
1170 | 1301 | ||
1171 | if (pdata->gpio_wprotect == 0) | 1302 | if (pdata->no_wprotect) |
1172 | return 0; | 1303 | return 0; |
1173 | 1304 | ||
1174 | ret = s3c2410_gpio_getpin(pdata->gpio_wprotect); | 1305 | ret = s3c2410_gpio_getpin(pdata->gpio_wprotect); |
@@ -1179,11 +1310,52 @@ static int s3cmci_get_ro(struct mmc_host *mmc) | |||
1179 | return ret; | 1310 | return ret; |
1180 | } | 1311 | } |
1181 | 1312 | ||
1313 | static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable) | ||
1314 | { | ||
1315 | struct s3cmci_host *host = mmc_priv(mmc); | ||
1316 | unsigned long flags; | ||
1317 | u32 con; | ||
1318 | |||
1319 | local_irq_save(flags); | ||
1320 | |||
1321 | con = readl(host->base + S3C2410_SDICON); | ||
1322 | host->sdio_irqen = enable; | ||
1323 | |||
1324 | if (enable == host->sdio_irqen) | ||
1325 | goto same_state; | ||
1326 | |||
1327 | if (enable) { | ||
1328 | con |= S3C2410_SDICON_SDIOIRQ; | ||
1329 | enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ); | ||
1330 | |||
1331 | if (!host->irq_state && !host->irq_disabled) { | ||
1332 | host->irq_state = true; | ||
1333 | enable_irq(host->irq); | ||
1334 | } | ||
1335 | } else { | ||
1336 | disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ); | ||
1337 | con &= ~S3C2410_SDICON_SDIOIRQ; | ||
1338 | |||
1339 | if (!host->irq_enabled && host->irq_state) { | ||
1340 | disable_irq_nosync(host->irq); | ||
1341 | host->irq_state = false; | ||
1342 | } | ||
1343 | } | ||
1344 | |||
1345 | writel(con, host->base + S3C2410_SDICON); | ||
1346 | |||
1347 | same_state: | ||
1348 | local_irq_restore(flags); | ||
1349 | |||
1350 | s3cmci_check_sdio_irq(host); | ||
1351 | } | ||
1352 | |||
1182 | static struct mmc_host_ops s3cmci_ops = { | 1353 | static struct mmc_host_ops s3cmci_ops = { |
1183 | .request = s3cmci_request, | 1354 | .request = s3cmci_request, |
1184 | .set_ios = s3cmci_set_ios, | 1355 | .set_ios = s3cmci_set_ios, |
1185 | .get_ro = s3cmci_get_ro, | 1356 | .get_ro = s3cmci_get_ro, |
1186 | .get_cd = s3cmci_card_present, | 1357 | .get_cd = s3cmci_card_present, |
1358 | .enable_sdio_irq = s3cmci_enable_sdio_irq, | ||
1187 | }; | 1359 | }; |
1188 | 1360 | ||
1189 | static struct s3c24xx_mci_pdata s3cmci_def_pdata = { | 1361 | static struct s3c24xx_mci_pdata s3cmci_def_pdata = { |
@@ -1246,11 +1418,140 @@ static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host) | |||
1246 | } | 1418 | } |
1247 | #endif | 1419 | #endif |
1248 | 1420 | ||
1249 | static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440) | 1421 | |
1422 | #ifdef CONFIG_DEBUG_FS | ||
1423 | |||
1424 | static int s3cmci_state_show(struct seq_file *seq, void *v) | ||
1425 | { | ||
1426 | struct s3cmci_host *host = seq->private; | ||
1427 | |||
1428 | seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base); | ||
1429 | seq_printf(seq, "Clock rate = %ld\n", host->clk_rate); | ||
1430 | seq_printf(seq, "Prescale = %d\n", host->prescaler); | ||
1431 | seq_printf(seq, "is2440 = %d\n", host->is2440); | ||
1432 | seq_printf(seq, "IRQ = %d\n", host->irq); | ||
1433 | seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled); | ||
1434 | seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled); | ||
1435 | seq_printf(seq, "IRQ state = %d\n", host->irq_state); | ||
1436 | seq_printf(seq, "CD IRQ = %d\n", host->irq_cd); | ||
1437 | seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host)); | ||
1438 | seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk); | ||
1439 | seq_printf(seq, "SDIDATA at %d\n", host->sdidata); | ||
1440 | |||
1441 | return 0; | ||
1442 | } | ||
1443 | |||
1444 | static int s3cmci_state_open(struct inode *inode, struct file *file) | ||
1445 | { | ||
1446 | return single_open(file, s3cmci_state_show, inode->i_private); | ||
1447 | } | ||
1448 | |||
1449 | static const struct file_operations s3cmci_fops_state = { | ||
1450 | .owner = THIS_MODULE, | ||
1451 | .open = s3cmci_state_open, | ||
1452 | .read = seq_read, | ||
1453 | .llseek = seq_lseek, | ||
1454 | .release = single_release, | ||
1455 | }; | ||
1456 | |||
1457 | #define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r } | ||
1458 | |||
1459 | struct s3cmci_reg { | ||
1460 | unsigned short addr; | ||
1461 | unsigned char *name; | ||
1462 | } debug_regs[] = { | ||
1463 | DBG_REG(CON), | ||
1464 | DBG_REG(PRE), | ||
1465 | DBG_REG(CMDARG), | ||
1466 | DBG_REG(CMDCON), | ||
1467 | DBG_REG(CMDSTAT), | ||
1468 | DBG_REG(RSP0), | ||
1469 | DBG_REG(RSP1), | ||
1470 | DBG_REG(RSP2), | ||
1471 | DBG_REG(RSP3), | ||
1472 | DBG_REG(TIMER), | ||
1473 | DBG_REG(BSIZE), | ||
1474 | DBG_REG(DCON), | ||
1475 | DBG_REG(DCNT), | ||
1476 | DBG_REG(DSTA), | ||
1477 | DBG_REG(FSTA), | ||
1478 | {} | ||
1479 | }; | ||
1480 | |||
1481 | static int s3cmci_regs_show(struct seq_file *seq, void *v) | ||
1482 | { | ||
1483 | struct s3cmci_host *host = seq->private; | ||
1484 | struct s3cmci_reg *rptr = debug_regs; | ||
1485 | |||
1486 | for (; rptr->name; rptr++) | ||
1487 | seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name, | ||
1488 | readl(host->base + rptr->addr)); | ||
1489 | |||
1490 | seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk)); | ||
1491 | |||
1492 | return 0; | ||
1493 | } | ||
1494 | |||
1495 | static int s3cmci_regs_open(struct inode *inode, struct file *file) | ||
1496 | { | ||
1497 | return single_open(file, s3cmci_regs_show, inode->i_private); | ||
1498 | } | ||
1499 | |||
1500 | static const struct file_operations s3cmci_fops_regs = { | ||
1501 | .owner = THIS_MODULE, | ||
1502 | .open = s3cmci_regs_open, | ||
1503 | .read = seq_read, | ||
1504 | .llseek = seq_lseek, | ||
1505 | .release = single_release, | ||
1506 | }; | ||
1507 | |||
1508 | static void s3cmci_debugfs_attach(struct s3cmci_host *host) | ||
1509 | { | ||
1510 | struct device *dev = &host->pdev->dev; | ||
1511 | |||
1512 | host->debug_root = debugfs_create_dir(dev_name(dev), NULL); | ||
1513 | if (IS_ERR(host->debug_root)) { | ||
1514 | dev_err(dev, "failed to create debugfs root\n"); | ||
1515 | return; | ||
1516 | } | ||
1517 | |||
1518 | host->debug_state = debugfs_create_file("state", 0444, | ||
1519 | host->debug_root, host, | ||
1520 | &s3cmci_fops_state); | ||
1521 | |||
1522 | if (IS_ERR(host->debug_state)) | ||
1523 | dev_err(dev, "failed to create debug state file\n"); | ||
1524 | |||
1525 | host->debug_regs = debugfs_create_file("regs", 0444, | ||
1526 | host->debug_root, host, | ||
1527 | &s3cmci_fops_regs); | ||
1528 | |||
1529 | if (IS_ERR(host->debug_regs)) | ||
1530 | dev_err(dev, "failed to create debug regs file\n"); | ||
1531 | } | ||
1532 | |||
1533 | static void s3cmci_debugfs_remove(struct s3cmci_host *host) | ||
1534 | { | ||
1535 | debugfs_remove(host->debug_regs); | ||
1536 | debugfs_remove(host->debug_state); | ||
1537 | debugfs_remove(host->debug_root); | ||
1538 | } | ||
1539 | |||
1540 | #else | ||
1541 | static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { } | ||
1542 | static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { } | ||
1543 | |||
1544 | #endif /* CONFIG_DEBUG_FS */ | ||
1545 | |||
1546 | static int __devinit s3cmci_probe(struct platform_device *pdev) | ||
1250 | { | 1547 | { |
1251 | struct s3cmci_host *host; | 1548 | struct s3cmci_host *host; |
1252 | struct mmc_host *mmc; | 1549 | struct mmc_host *mmc; |
1253 | int ret; | 1550 | int ret; |
1551 | int is2440; | ||
1552 | int i; | ||
1553 | |||
1554 | is2440 = platform_get_device_id(pdev)->driver_data; | ||
1254 | 1555 | ||
1255 | mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev); | 1556 | mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev); |
1256 | if (!mmc) { | 1557 | if (!mmc) { |
@@ -1258,6 +1559,18 @@ static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440) | |||
1258 | goto probe_out; | 1559 | goto probe_out; |
1259 | } | 1560 | } |
1260 | 1561 | ||
1562 | for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) { | ||
1563 | ret = gpio_request(i, dev_name(&pdev->dev)); | ||
1564 | if (ret) { | ||
1565 | dev_err(&pdev->dev, "failed to get gpio %d\n", i); | ||
1566 | |||
1567 | for (i--; i >= S3C2410_GPE(5); i--) | ||
1568 | gpio_free(i); | ||
1569 | |||
1570 | goto probe_free_host; | ||
1571 | } | ||
1572 | } | ||
1573 | |||
1261 | host = mmc_priv(mmc); | 1574 | host = mmc_priv(mmc); |
1262 | host->mmc = mmc; | 1575 | host->mmc = mmc; |
1263 | host->pdev = pdev; | 1576 | host->pdev = pdev; |
@@ -1282,11 +1595,12 @@ static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440) | |||
1282 | host->clk_div = 2; | 1595 | host->clk_div = 2; |
1283 | } | 1596 | } |
1284 | 1597 | ||
1285 | host->dodma = 0; | ||
1286 | host->complete_what = COMPLETION_NONE; | 1598 | host->complete_what = COMPLETION_NONE; |
1287 | host->pio_active = XFER_NONE; | 1599 | host->pio_active = XFER_NONE; |
1288 | 1600 | ||
1289 | host->dma = S3CMCI_DMA; | 1601 | #ifdef CONFIG_MMC_S3C_PIODMA |
1602 | host->dodma = host->pdata->dma; | ||
1603 | #endif | ||
1290 | 1604 | ||
1291 | host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 1605 | host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1292 | if (!host->mem) { | 1606 | if (!host->mem) { |
@@ -1294,19 +1608,19 @@ static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440) | |||
1294 | "failed to get io memory region resouce.\n"); | 1608 | "failed to get io memory region resouce.\n"); |
1295 | 1609 | ||
1296 | ret = -ENOENT; | 1610 | ret = -ENOENT; |
1297 | goto probe_free_host; | 1611 | goto probe_free_gpio; |
1298 | } | 1612 | } |
1299 | 1613 | ||
1300 | host->mem = request_mem_region(host->mem->start, | 1614 | host->mem = request_mem_region(host->mem->start, |
1301 | RESSIZE(host->mem), pdev->name); | 1615 | resource_size(host->mem), pdev->name); |
1302 | 1616 | ||
1303 | if (!host->mem) { | 1617 | if (!host->mem) { |
1304 | dev_err(&pdev->dev, "failed to request io memory region.\n"); | 1618 | dev_err(&pdev->dev, "failed to request io memory region.\n"); |
1305 | ret = -ENOENT; | 1619 | ret = -ENOENT; |
1306 | goto probe_free_host; | 1620 | goto probe_free_gpio; |
1307 | } | 1621 | } |
1308 | 1622 | ||
1309 | host->base = ioremap(host->mem->start, RESSIZE(host->mem)); | 1623 | host->base = ioremap(host->mem->start, resource_size(host->mem)); |
1310 | if (!host->base) { | 1624 | if (!host->base) { |
1311 | dev_err(&pdev->dev, "failed to ioremap() io memory region.\n"); | 1625 | dev_err(&pdev->dev, "failed to ioremap() io memory region.\n"); |
1312 | ret = -EINVAL; | 1626 | ret = -EINVAL; |
@@ -1331,31 +1645,60 @@ static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440) | |||
1331 | * ensure we don't lock the system with un-serviceable requests. */ | 1645 | * ensure we don't lock the system with un-serviceable requests. */ |
1332 | 1646 | ||
1333 | disable_irq(host->irq); | 1647 | disable_irq(host->irq); |
1648 | host->irq_state = false; | ||
1334 | 1649 | ||
1335 | host->irq_cd = s3c2410_gpio_getirq(host->pdata->gpio_detect); | 1650 | if (!host->pdata->no_detect) { |
1336 | 1651 | ret = gpio_request(host->pdata->gpio_detect, "s3cmci detect"); | |
1337 | if (host->irq_cd >= 0) { | 1652 | if (ret) { |
1338 | if (request_irq(host->irq_cd, s3cmci_irq_cd, | 1653 | dev_err(&pdev->dev, "failed to get detect gpio\n"); |
1339 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, | ||
1340 | DRIVER_NAME, host)) { | ||
1341 | dev_err(&pdev->dev, "can't get card detect irq.\n"); | ||
1342 | ret = -ENOENT; | ||
1343 | goto probe_free_irq; | 1654 | goto probe_free_irq; |
1344 | } | 1655 | } |
1345 | } else { | 1656 | |
1346 | dev_warn(&pdev->dev, "host detect has no irq available\n"); | 1657 | host->irq_cd = s3c2410_gpio_getirq(host->pdata->gpio_detect); |
1347 | s3c2410_gpio_cfgpin(host->pdata->gpio_detect, | 1658 | |
1348 | S3C2410_GPIO_INPUT); | 1659 | if (host->irq_cd >= 0) { |
1660 | if (request_irq(host->irq_cd, s3cmci_irq_cd, | ||
1661 | IRQF_TRIGGER_RISING | | ||
1662 | IRQF_TRIGGER_FALLING, | ||
1663 | DRIVER_NAME, host)) { | ||
1664 | dev_err(&pdev->dev, | ||
1665 | "can't get card detect irq.\n"); | ||
1666 | ret = -ENOENT; | ||
1667 | goto probe_free_gpio_cd; | ||
1668 | } | ||
1669 | } else { | ||
1670 | dev_warn(&pdev->dev, | ||
1671 | "host detect has no irq available\n"); | ||
1672 | gpio_direction_input(host->pdata->gpio_detect); | ||
1673 | } | ||
1674 | } else | ||
1675 | host->irq_cd = -1; | ||
1676 | |||
1677 | if (!host->pdata->no_wprotect) { | ||
1678 | ret = gpio_request(host->pdata->gpio_wprotect, "s3cmci wp"); | ||
1679 | if (ret) { | ||
1680 | dev_err(&pdev->dev, "failed to get writeprotect\n"); | ||
1681 | goto probe_free_irq_cd; | ||
1682 | } | ||
1683 | |||
1684 | gpio_direction_input(host->pdata->gpio_wprotect); | ||
1349 | } | 1685 | } |
1350 | 1686 | ||
1351 | if (host->pdata->gpio_wprotect) | 1687 | /* depending on the dma state, get a dma channel to use. */ |
1352 | s3c2410_gpio_cfgpin(host->pdata->gpio_wprotect, | ||
1353 | S3C2410_GPIO_INPUT); | ||
1354 | 1688 | ||
1355 | if (s3c2410_dma_request(S3CMCI_DMA, &s3cmci_dma_client, NULL) < 0) { | 1689 | if (s3cmci_host_usedma(host)) { |
1356 | dev_err(&pdev->dev, "unable to get DMA channel.\n"); | 1690 | host->dma = s3c2410_dma_request(DMACH_SDI, &s3cmci_dma_client, |
1357 | ret = -EBUSY; | 1691 | host); |
1358 | goto probe_free_irq_cd; | 1692 | if (host->dma < 0) { |
1693 | dev_err(&pdev->dev, "cannot get DMA channel.\n"); | ||
1694 | if (!s3cmci_host_canpio()) { | ||
1695 | ret = -EBUSY; | ||
1696 | goto probe_free_gpio_wp; | ||
1697 | } else { | ||
1698 | dev_warn(&pdev->dev, "falling back to PIO.\n"); | ||
1699 | host->dodma = 0; | ||
1700 | } | ||
1701 | } | ||
1359 | } | 1702 | } |
1360 | 1703 | ||
1361 | host->clk = clk_get(&pdev->dev, "sdi"); | 1704 | host->clk = clk_get(&pdev->dev, "sdi"); |
@@ -1363,7 +1706,7 @@ static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440) | |||
1363 | dev_err(&pdev->dev, "failed to find clock source.\n"); | 1706 | dev_err(&pdev->dev, "failed to find clock source.\n"); |
1364 | ret = PTR_ERR(host->clk); | 1707 | ret = PTR_ERR(host->clk); |
1365 | host->clk = NULL; | 1708 | host->clk = NULL; |
1366 | goto probe_free_host; | 1709 | goto probe_free_dma; |
1367 | } | 1710 | } |
1368 | 1711 | ||
1369 | ret = clk_enable(host->clk); | 1712 | ret = clk_enable(host->clk); |
@@ -1376,7 +1719,11 @@ static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440) | |||
1376 | 1719 | ||
1377 | mmc->ops = &s3cmci_ops; | 1720 | mmc->ops = &s3cmci_ops; |
1378 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | 1721 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; |
1722 | #ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ | ||
1723 | mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; | ||
1724 | #else | ||
1379 | mmc->caps = MMC_CAP_4_BIT_DATA; | 1725 | mmc->caps = MMC_CAP_4_BIT_DATA; |
1726 | #endif | ||
1380 | mmc->f_min = host->clk_rate / (host->clk_div * 256); | 1727 | mmc->f_min = host->clk_rate / (host->clk_div * 256); |
1381 | mmc->f_max = host->clk_rate / host->clk_div; | 1728 | mmc->f_max = host->clk_rate / host->clk_div; |
1382 | 1729 | ||
@@ -1408,8 +1755,12 @@ static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440) | |||
1408 | goto free_cpufreq; | 1755 | goto free_cpufreq; |
1409 | } | 1756 | } |
1410 | 1757 | ||
1758 | s3cmci_debugfs_attach(host); | ||
1759 | |||
1411 | platform_set_drvdata(pdev, mmc); | 1760 | platform_set_drvdata(pdev, mmc); |
1412 | dev_info(&pdev->dev, "initialisation done.\n"); | 1761 | dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc), |
1762 | s3cmci_host_usedma(host) ? "dma" : "pio", | ||
1763 | mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw"); | ||
1413 | 1764 | ||
1414 | return 0; | 1765 | return 0; |
1415 | 1766 | ||
@@ -1422,6 +1773,18 @@ static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440) | |||
1422 | clk_free: | 1773 | clk_free: |
1423 | clk_put(host->clk); | 1774 | clk_put(host->clk); |
1424 | 1775 | ||
1776 | probe_free_dma: | ||
1777 | if (s3cmci_host_usedma(host)) | ||
1778 | s3c2410_dma_free(host->dma, &s3cmci_dma_client); | ||
1779 | |||
1780 | probe_free_gpio_wp: | ||
1781 | if (!host->pdata->no_wprotect) | ||
1782 | gpio_free(host->pdata->gpio_wprotect); | ||
1783 | |||
1784 | probe_free_gpio_cd: | ||
1785 | if (!host->pdata->no_detect) | ||
1786 | gpio_free(host->pdata->gpio_detect); | ||
1787 | |||
1425 | probe_free_irq_cd: | 1788 | probe_free_irq_cd: |
1426 | if (host->irq_cd >= 0) | 1789 | if (host->irq_cd >= 0) |
1427 | free_irq(host->irq_cd, host); | 1790 | free_irq(host->irq_cd, host); |
@@ -1433,10 +1796,15 @@ static int __devinit s3cmci_probe(struct platform_device *pdev, int is2440) | |||
1433 | iounmap(host->base); | 1796 | iounmap(host->base); |
1434 | 1797 | ||
1435 | probe_free_mem_region: | 1798 | probe_free_mem_region: |
1436 | release_mem_region(host->mem->start, RESSIZE(host->mem)); | 1799 | release_mem_region(host->mem->start, resource_size(host->mem)); |
1800 | |||
1801 | probe_free_gpio: | ||
1802 | for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) | ||
1803 | gpio_free(i); | ||
1437 | 1804 | ||
1438 | probe_free_host: | 1805 | probe_free_host: |
1439 | mmc_free_host(mmc); | 1806 | mmc_free_host(mmc); |
1807 | |||
1440 | probe_out: | 1808 | probe_out: |
1441 | return ret; | 1809 | return ret; |
1442 | } | 1810 | } |
@@ -1449,6 +1817,7 @@ static void s3cmci_shutdown(struct platform_device *pdev) | |||
1449 | if (host->irq_cd >= 0) | 1817 | if (host->irq_cd >= 0) |
1450 | free_irq(host->irq_cd, host); | 1818 | free_irq(host->irq_cd, host); |
1451 | 1819 | ||
1820 | s3cmci_debugfs_remove(host); | ||
1452 | s3cmci_cpufreq_deregister(host); | 1821 | s3cmci_cpufreq_deregister(host); |
1453 | mmc_remove_host(mmc); | 1822 | mmc_remove_host(mmc); |
1454 | clk_disable(host->clk); | 1823 | clk_disable(host->clk); |
@@ -1458,104 +1827,102 @@ static int __devexit s3cmci_remove(struct platform_device *pdev) | |||
1458 | { | 1827 | { |
1459 | struct mmc_host *mmc = platform_get_drvdata(pdev); | 1828 | struct mmc_host *mmc = platform_get_drvdata(pdev); |
1460 | struct s3cmci_host *host = mmc_priv(mmc); | 1829 | struct s3cmci_host *host = mmc_priv(mmc); |
1830 | struct s3c24xx_mci_pdata *pd = host->pdata; | ||
1831 | int i; | ||
1461 | 1832 | ||
1462 | s3cmci_shutdown(pdev); | 1833 | s3cmci_shutdown(pdev); |
1463 | 1834 | ||
1464 | clk_put(host->clk); | 1835 | clk_put(host->clk); |
1465 | 1836 | ||
1466 | tasklet_disable(&host->pio_tasklet); | 1837 | tasklet_disable(&host->pio_tasklet); |
1467 | s3c2410_dma_free(S3CMCI_DMA, &s3cmci_dma_client); | 1838 | |
1839 | if (s3cmci_host_usedma(host)) | ||
1840 | s3c2410_dma_free(host->dma, &s3cmci_dma_client); | ||
1468 | 1841 | ||
1469 | free_irq(host->irq, host); | 1842 | free_irq(host->irq, host); |
1470 | 1843 | ||
1844 | if (!pd->no_wprotect) | ||
1845 | gpio_free(pd->gpio_wprotect); | ||
1846 | |||
1847 | if (!pd->no_detect) | ||
1848 | gpio_free(pd->gpio_detect); | ||
1849 | |||
1850 | for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) | ||
1851 | gpio_free(i); | ||
1852 | |||
1853 | |||
1471 | iounmap(host->base); | 1854 | iounmap(host->base); |
1472 | release_mem_region(host->mem->start, RESSIZE(host->mem)); | 1855 | release_mem_region(host->mem->start, resource_size(host->mem)); |
1473 | 1856 | ||
1474 | mmc_free_host(mmc); | 1857 | mmc_free_host(mmc); |
1475 | return 0; | 1858 | return 0; |
1476 | } | 1859 | } |
1477 | 1860 | ||
1478 | static int __devinit s3cmci_2410_probe(struct platform_device *dev) | 1861 | static struct platform_device_id s3cmci_driver_ids[] = { |
1479 | { | 1862 | { |
1480 | return s3cmci_probe(dev, 0); | 1863 | .name = "s3c2410-sdi", |
1481 | } | 1864 | .driver_data = 0, |
1865 | }, { | ||
1866 | .name = "s3c2412-sdi", | ||
1867 | .driver_data = 1, | ||
1868 | }, { | ||
1869 | .name = "s3c2440-sdi", | ||
1870 | .driver_data = 1, | ||
1871 | }, | ||
1872 | { } | ||
1873 | }; | ||
1482 | 1874 | ||
1483 | static int __devinit s3cmci_2412_probe(struct platform_device *dev) | 1875 | MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids); |
1484 | { | ||
1485 | return s3cmci_probe(dev, 1); | ||
1486 | } | ||
1487 | 1876 | ||
1488 | static int __devinit s3cmci_2440_probe(struct platform_device *dev) | ||
1489 | { | ||
1490 | return s3cmci_probe(dev, 1); | ||
1491 | } | ||
1492 | 1877 | ||
1493 | #ifdef CONFIG_PM | 1878 | #ifdef CONFIG_PM |
1494 | 1879 | ||
1495 | static int s3cmci_suspend(struct platform_device *dev, pm_message_t state) | 1880 | static int s3cmci_suspend(struct device *dev) |
1496 | { | 1881 | { |
1497 | struct mmc_host *mmc = platform_get_drvdata(dev); | 1882 | struct mmc_host *mmc = platform_get_drvdata(to_platform_device(dev)); |
1883 | struct pm_message event = { PM_EVENT_SUSPEND }; | ||
1498 | 1884 | ||
1499 | return mmc_suspend_host(mmc, state); | 1885 | return mmc_suspend_host(mmc, event); |
1500 | } | 1886 | } |
1501 | 1887 | ||
1502 | static int s3cmci_resume(struct platform_device *dev) | 1888 | static int s3cmci_resume(struct device *dev) |
1503 | { | 1889 | { |
1504 | struct mmc_host *mmc = platform_get_drvdata(dev); | 1890 | struct mmc_host *mmc = platform_get_drvdata(to_platform_device(dev)); |
1505 | 1891 | ||
1506 | return mmc_resume_host(mmc); | 1892 | return mmc_resume_host(mmc); |
1507 | } | 1893 | } |
1508 | 1894 | ||
1509 | #else /* CONFIG_PM */ | 1895 | static struct dev_pm_ops s3cmci_pm = { |
1510 | #define s3cmci_suspend NULL | ||
1511 | #define s3cmci_resume NULL | ||
1512 | #endif /* CONFIG_PM */ | ||
1513 | |||
1514 | |||
1515 | static struct platform_driver s3cmci_2410_driver = { | ||
1516 | .driver.name = "s3c2410-sdi", | ||
1517 | .driver.owner = THIS_MODULE, | ||
1518 | .probe = s3cmci_2410_probe, | ||
1519 | .remove = __devexit_p(s3cmci_remove), | ||
1520 | .shutdown = s3cmci_shutdown, | ||
1521 | .suspend = s3cmci_suspend, | 1896 | .suspend = s3cmci_suspend, |
1522 | .resume = s3cmci_resume, | 1897 | .resume = s3cmci_resume, |
1523 | }; | 1898 | }; |
1524 | 1899 | ||
1525 | static struct platform_driver s3cmci_2412_driver = { | 1900 | #define s3cmci_pm_ops &s3cmci_pm |
1526 | .driver.name = "s3c2412-sdi", | 1901 | #else /* CONFIG_PM */ |
1527 | .driver.owner = THIS_MODULE, | 1902 | #define s3cmci_pm_ops NULL |
1528 | .probe = s3cmci_2412_probe, | 1903 | #endif /* CONFIG_PM */ |
1529 | .remove = __devexit_p(s3cmci_remove), | ||
1530 | .shutdown = s3cmci_shutdown, | ||
1531 | .suspend = s3cmci_suspend, | ||
1532 | .resume = s3cmci_resume, | ||
1533 | }; | ||
1534 | 1904 | ||
1535 | static struct platform_driver s3cmci_2440_driver = { | 1905 | |
1536 | .driver.name = "s3c2440-sdi", | 1906 | static struct platform_driver s3cmci_driver = { |
1537 | .driver.owner = THIS_MODULE, | 1907 | .driver = { |
1538 | .probe = s3cmci_2440_probe, | 1908 | .name = "s3c-sdi", |
1909 | .owner = THIS_MODULE, | ||
1910 | .pm = s3cmci_pm_ops, | ||
1911 | }, | ||
1912 | .id_table = s3cmci_driver_ids, | ||
1913 | .probe = s3cmci_probe, | ||
1539 | .remove = __devexit_p(s3cmci_remove), | 1914 | .remove = __devexit_p(s3cmci_remove), |
1540 | .shutdown = s3cmci_shutdown, | 1915 | .shutdown = s3cmci_shutdown, |
1541 | .suspend = s3cmci_suspend, | ||
1542 | .resume = s3cmci_resume, | ||
1543 | }; | 1916 | }; |
1544 | 1917 | ||
1545 | |||
1546 | static int __init s3cmci_init(void) | 1918 | static int __init s3cmci_init(void) |
1547 | { | 1919 | { |
1548 | platform_driver_register(&s3cmci_2410_driver); | 1920 | return platform_driver_register(&s3cmci_driver); |
1549 | platform_driver_register(&s3cmci_2412_driver); | ||
1550 | platform_driver_register(&s3cmci_2440_driver); | ||
1551 | return 0; | ||
1552 | } | 1921 | } |
1553 | 1922 | ||
1554 | static void __exit s3cmci_exit(void) | 1923 | static void __exit s3cmci_exit(void) |
1555 | { | 1924 | { |
1556 | platform_driver_unregister(&s3cmci_2410_driver); | 1925 | platform_driver_unregister(&s3cmci_driver); |
1557 | platform_driver_unregister(&s3cmci_2412_driver); | ||
1558 | platform_driver_unregister(&s3cmci_2440_driver); | ||
1559 | } | 1926 | } |
1560 | 1927 | ||
1561 | module_init(s3cmci_init); | 1928 | module_init(s3cmci_init); |
@@ -1564,6 +1931,3 @@ module_exit(s3cmci_exit); | |||
1564 | MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver"); | 1931 | MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver"); |
1565 | MODULE_LICENSE("GPL v2"); | 1932 | MODULE_LICENSE("GPL v2"); |
1566 | MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>"); | 1933 | MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>"); |
1567 | MODULE_ALIAS("platform:s3c2410-sdi"); | ||
1568 | MODULE_ALIAS("platform:s3c2412-sdi"); | ||
1569 | MODULE_ALIAS("platform:s3c2440-sdi"); | ||
diff --git a/drivers/mmc/host/s3cmci.h b/drivers/mmc/host/s3cmci.h index ca1ba3d58cfd..c76b53dbeb61 100644 --- a/drivers/mmc/host/s3cmci.h +++ b/drivers/mmc/host/s3cmci.h | |||
@@ -8,9 +8,6 @@ | |||
8 | * published by the Free Software Foundation. | 8 | * published by the Free Software Foundation. |
9 | */ | 9 | */ |
10 | 10 | ||
11 | /* FIXME: DMA Resource management ?! */ | ||
12 | #define S3CMCI_DMA 0 | ||
13 | |||
14 | enum s3cmci_waitfor { | 11 | enum s3cmci_waitfor { |
15 | COMPLETION_NONE, | 12 | COMPLETION_NONE, |
16 | COMPLETION_FINALIZE, | 13 | COMPLETION_FINALIZE, |
@@ -42,6 +39,11 @@ struct s3cmci_host { | |||
42 | int dodma; | 39 | int dodma; |
43 | int dmatogo; | 40 | int dmatogo; |
44 | 41 | ||
42 | bool irq_disabled; | ||
43 | bool irq_enabled; | ||
44 | bool irq_state; | ||
45 | int sdio_irqen; | ||
46 | |||
45 | struct mmc_request *mrq; | 47 | struct mmc_request *mrq; |
46 | int cmd_is_stop; | 48 | int cmd_is_stop; |
47 | 49 | ||
@@ -68,6 +70,12 @@ struct s3cmci_host { | |||
68 | unsigned int ccnt, dcnt; | 70 | unsigned int ccnt, dcnt; |
69 | struct tasklet_struct pio_tasklet; | 71 | struct tasklet_struct pio_tasklet; |
70 | 72 | ||
73 | #ifdef CONFIG_DEBUG_FS | ||
74 | struct dentry *debug_root; | ||
75 | struct dentry *debug_state; | ||
76 | struct dentry *debug_regs; | ||
77 | #endif | ||
78 | |||
71 | #ifdef CONFIG_CPU_FREQ | 79 | #ifdef CONFIG_CPU_FREQ |
72 | struct notifier_block freq_transition; | 80 | struct notifier_block freq_transition; |
73 | #endif | 81 | #endif |
diff --git a/drivers/net/3c59x.c b/drivers/net/3c59x.c index b9eeadf01b74..975e25b19ebe 100644 --- a/drivers/net/3c59x.c +++ b/drivers/net/3c59x.c | |||
@@ -805,52 +805,54 @@ static void poll_vortex(struct net_device *dev) | |||
805 | 805 | ||
806 | #ifdef CONFIG_PM | 806 | #ifdef CONFIG_PM |
807 | 807 | ||
808 | static int vortex_suspend(struct pci_dev *pdev, pm_message_t state) | 808 | static int vortex_suspend(struct device *dev) |
809 | { | 809 | { |
810 | struct net_device *dev = pci_get_drvdata(pdev); | 810 | struct pci_dev *pdev = to_pci_dev(dev); |
811 | struct net_device *ndev = pci_get_drvdata(pdev); | ||
812 | |||
813 | if (!ndev || !netif_running(ndev)) | ||
814 | return 0; | ||
815 | |||
816 | netif_device_detach(ndev); | ||
817 | vortex_down(ndev, 1); | ||
811 | 818 | ||
812 | if (dev && netdev_priv(dev)) { | ||
813 | if (netif_running(dev)) { | ||
814 | netif_device_detach(dev); | ||
815 | vortex_down(dev, 1); | ||
816 | disable_irq(dev->irq); | ||
817 | } | ||
818 | pci_save_state(pdev); | ||
819 | pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); | ||
820 | pci_disable_device(pdev); | ||
821 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | ||
822 | } | ||
823 | return 0; | 819 | return 0; |
824 | } | 820 | } |
825 | 821 | ||
826 | static int vortex_resume(struct pci_dev *pdev) | 822 | static int vortex_resume(struct device *dev) |
827 | { | 823 | { |
828 | struct net_device *dev = pci_get_drvdata(pdev); | 824 | struct pci_dev *pdev = to_pci_dev(dev); |
829 | struct vortex_private *vp = netdev_priv(dev); | 825 | struct net_device *ndev = pci_get_drvdata(pdev); |
830 | int err; | 826 | int err; |
831 | 827 | ||
832 | if (dev && vp) { | 828 | if (!ndev || !netif_running(ndev)) |
833 | pci_set_power_state(pdev, PCI_D0); | 829 | return 0; |
834 | pci_restore_state(pdev); | 830 | |
835 | err = pci_enable_device(pdev); | 831 | err = vortex_up(ndev); |
836 | if (err) { | 832 | if (err) |
837 | pr_warning("%s: Could not enable device\n", | 833 | return err; |
838 | dev->name); | 834 | |
839 | return err; | 835 | netif_device_attach(ndev); |
840 | } | 836 | |
841 | pci_set_master(pdev); | ||
842 | if (netif_running(dev)) { | ||
843 | err = vortex_up(dev); | ||
844 | if (err) | ||
845 | return err; | ||
846 | enable_irq(dev->irq); | ||
847 | netif_device_attach(dev); | ||
848 | } | ||
849 | } | ||
850 | return 0; | 837 | return 0; |
851 | } | 838 | } |
852 | 839 | ||
853 | #endif /* CONFIG_PM */ | 840 | static struct dev_pm_ops vortex_pm_ops = { |
841 | .suspend = vortex_suspend, | ||
842 | .resume = vortex_resume, | ||
843 | .freeze = vortex_suspend, | ||
844 | .thaw = vortex_resume, | ||
845 | .poweroff = vortex_suspend, | ||
846 | .restore = vortex_resume, | ||
847 | }; | ||
848 | |||
849 | #define VORTEX_PM_OPS (&vortex_pm_ops) | ||
850 | |||
851 | #else /* !CONFIG_PM */ | ||
852 | |||
853 | #define VORTEX_PM_OPS NULL | ||
854 | |||
855 | #endif /* !CONFIG_PM */ | ||
854 | 856 | ||
855 | #ifdef CONFIG_EISA | 857 | #ifdef CONFIG_EISA |
856 | static struct eisa_device_id vortex_eisa_ids[] = { | 858 | static struct eisa_device_id vortex_eisa_ids[] = { |
@@ -3199,10 +3201,7 @@ static struct pci_driver vortex_driver = { | |||
3199 | .probe = vortex_init_one, | 3201 | .probe = vortex_init_one, |
3200 | .remove = __devexit_p(vortex_remove_one), | 3202 | .remove = __devexit_p(vortex_remove_one), |
3201 | .id_table = vortex_pci_tbl, | 3203 | .id_table = vortex_pci_tbl, |
3202 | #ifdef CONFIG_PM | 3204 | .driver.pm = VORTEX_PM_OPS, |
3203 | .suspend = vortex_suspend, | ||
3204 | .resume = vortex_resume, | ||
3205 | #endif | ||
3206 | }; | 3205 | }; |
3207 | 3206 | ||
3208 | 3207 | ||
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 2bea67c134f0..712776089b46 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig | |||
@@ -1738,6 +1738,13 @@ config KS8851 | |||
1738 | help | 1738 | help |
1739 | SPI driver for Micrel KS8851 SPI attached network chip. | 1739 | SPI driver for Micrel KS8851 SPI attached network chip. |
1740 | 1740 | ||
1741 | config KS8851_MLL | ||
1742 | tristate "Micrel KS8851 MLL" | ||
1743 | depends on HAS_IOMEM | ||
1744 | help | ||
1745 | This platform driver is for Micrel KS8851 Address/data bus | ||
1746 | multiplexed network chip. | ||
1747 | |||
1741 | config VIA_RHINE | 1748 | config VIA_RHINE |
1742 | tristate "VIA Rhine support" | 1749 | tristate "VIA Rhine support" |
1743 | depends on NET_PCI && PCI | 1750 | depends on NET_PCI && PCI |
diff --git a/drivers/net/Makefile b/drivers/net/Makefile index ae8cd30f13d6..d866b8cf65d1 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile | |||
@@ -89,6 +89,7 @@ obj-$(CONFIG_SKY2) += sky2.o | |||
89 | obj-$(CONFIG_SKFP) += skfp/ | 89 | obj-$(CONFIG_SKFP) += skfp/ |
90 | obj-$(CONFIG_KS8842) += ks8842.o | 90 | obj-$(CONFIG_KS8842) += ks8842.o |
91 | obj-$(CONFIG_KS8851) += ks8851.o | 91 | obj-$(CONFIG_KS8851) += ks8851.o |
92 | obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o | ||
92 | obj-$(CONFIG_VIA_RHINE) += via-rhine.o | 93 | obj-$(CONFIG_VIA_RHINE) += via-rhine.o |
93 | obj-$(CONFIG_VIA_VELOCITY) += via-velocity.o | 94 | obj-$(CONFIG_VIA_VELOCITY) += via-velocity.o |
94 | obj-$(CONFIG_ADAPTEC_STARFIRE) += starfire.o | 95 | obj-$(CONFIG_ADAPTEC_STARFIRE) += starfire.o |
diff --git a/drivers/net/bcm63xx_enet.c b/drivers/net/bcm63xx_enet.c index 09d270913c50..ba29dc319b34 100644 --- a/drivers/net/bcm63xx_enet.c +++ b/drivers/net/bcm63xx_enet.c | |||
@@ -90,7 +90,7 @@ static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data) | |||
90 | if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII) | 90 | if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII) |
91 | break; | 91 | break; |
92 | udelay(1); | 92 | udelay(1); |
93 | } while (limit-- >= 0); | 93 | } while (limit-- > 0); |
94 | 94 | ||
95 | return (limit < 0) ? 1 : 0; | 95 | return (limit < 0) ? 1 : 0; |
96 | } | 96 | } |
diff --git a/drivers/net/benet/be.h b/drivers/net/benet/be.h index 684c6fe24c8d..a80da0e14a52 100644 --- a/drivers/net/benet/be.h +++ b/drivers/net/benet/be.h | |||
@@ -258,6 +258,7 @@ struct be_adapter { | |||
258 | bool link_up; | 258 | bool link_up; |
259 | u32 port_num; | 259 | u32 port_num; |
260 | bool promiscuous; | 260 | bool promiscuous; |
261 | u32 cap; | ||
261 | }; | 262 | }; |
262 | 263 | ||
263 | extern const struct ethtool_ops be_ethtool_ops; | 264 | extern const struct ethtool_ops be_ethtool_ops; |
diff --git a/drivers/net/benet/be_cmds.c b/drivers/net/benet/be_cmds.c index 3dd76c4170bf..79d35d122c08 100644 --- a/drivers/net/benet/be_cmds.c +++ b/drivers/net/benet/be_cmds.c | |||
@@ -1068,7 +1068,7 @@ int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc) | |||
1068 | } | 1068 | } |
1069 | 1069 | ||
1070 | /* Uses mbox */ | 1070 | /* Uses mbox */ |
1071 | int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num) | 1071 | int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, u32 *cap) |
1072 | { | 1072 | { |
1073 | struct be_mcc_wrb *wrb; | 1073 | struct be_mcc_wrb *wrb; |
1074 | struct be_cmd_req_query_fw_cfg *req; | 1074 | struct be_cmd_req_query_fw_cfg *req; |
@@ -1088,6 +1088,7 @@ int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num) | |||
1088 | if (!status) { | 1088 | if (!status) { |
1089 | struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb); | 1089 | struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb); |
1090 | *port_num = le32_to_cpu(resp->phys_port); | 1090 | *port_num = le32_to_cpu(resp->phys_port); |
1091 | *cap = le32_to_cpu(resp->function_cap); | ||
1091 | } | 1092 | } |
1092 | 1093 | ||
1093 | spin_unlock(&adapter->mbox_lock); | 1094 | spin_unlock(&adapter->mbox_lock); |
diff --git a/drivers/net/benet/be_cmds.h b/drivers/net/benet/be_cmds.h index 93e432f3d926..8b4c2cb9ad62 100644 --- a/drivers/net/benet/be_cmds.h +++ b/drivers/net/benet/be_cmds.h | |||
@@ -760,7 +760,8 @@ extern int be_cmd_set_flow_control(struct be_adapter *adapter, | |||
760 | u32 tx_fc, u32 rx_fc); | 760 | u32 tx_fc, u32 rx_fc); |
761 | extern int be_cmd_get_flow_control(struct be_adapter *adapter, | 761 | extern int be_cmd_get_flow_control(struct be_adapter *adapter, |
762 | u32 *tx_fc, u32 *rx_fc); | 762 | u32 *tx_fc, u32 *rx_fc); |
763 | extern int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num); | 763 | extern int be_cmd_query_fw_cfg(struct be_adapter *adapter, |
764 | u32 *port_num, u32 *cap); | ||
764 | extern int be_cmd_reset_function(struct be_adapter *adapter); | 765 | extern int be_cmd_reset_function(struct be_adapter *adapter); |
765 | extern int be_process_mcc(struct be_adapter *adapter); | 766 | extern int be_process_mcc(struct be_adapter *adapter); |
766 | extern int be_cmd_write_flashrom(struct be_adapter *adapter, | 767 | extern int be_cmd_write_flashrom(struct be_adapter *adapter, |
diff --git a/drivers/net/benet/be_main.c b/drivers/net/benet/be_main.c index 409cf0595903..2f9b50156e0c 100644 --- a/drivers/net/benet/be_main.c +++ b/drivers/net/benet/be_main.c | |||
@@ -747,9 +747,16 @@ static void be_rx_compl_process(struct be_adapter *adapter, | |||
747 | struct be_eth_rx_compl *rxcp) | 747 | struct be_eth_rx_compl *rxcp) |
748 | { | 748 | { |
749 | struct sk_buff *skb; | 749 | struct sk_buff *skb; |
750 | u32 vtp, vid; | 750 | u32 vlanf, vid; |
751 | u8 vtm; | ||
751 | 752 | ||
752 | vtp = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp); | 753 | vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp); |
754 | vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp); | ||
755 | |||
756 | /* vlanf could be wrongly set in some cards. | ||
757 | * ignore if vtm is not set */ | ||
758 | if ((adapter->cap == 0x400) && !vtm) | ||
759 | vlanf = 0; | ||
753 | 760 | ||
754 | skb = netdev_alloc_skb(adapter->netdev, BE_HDR_LEN + NET_IP_ALIGN); | 761 | skb = netdev_alloc_skb(adapter->netdev, BE_HDR_LEN + NET_IP_ALIGN); |
755 | if (!skb) { | 762 | if (!skb) { |
@@ -772,7 +779,7 @@ static void be_rx_compl_process(struct be_adapter *adapter, | |||
772 | skb->protocol = eth_type_trans(skb, adapter->netdev); | 779 | skb->protocol = eth_type_trans(skb, adapter->netdev); |
773 | skb->dev = adapter->netdev; | 780 | skb->dev = adapter->netdev; |
774 | 781 | ||
775 | if (vtp) { | 782 | if (vlanf) { |
776 | if (!adapter->vlan_grp || adapter->num_vlans == 0) { | 783 | if (!adapter->vlan_grp || adapter->num_vlans == 0) { |
777 | kfree_skb(skb); | 784 | kfree_skb(skb); |
778 | return; | 785 | return; |
@@ -797,11 +804,18 @@ static void be_rx_compl_process_gro(struct be_adapter *adapter, | |||
797 | struct be_eq_obj *eq_obj = &adapter->rx_eq; | 804 | struct be_eq_obj *eq_obj = &adapter->rx_eq; |
798 | u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len; | 805 | u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len; |
799 | u16 i, rxq_idx = 0, vid, j; | 806 | u16 i, rxq_idx = 0, vid, j; |
807 | u8 vtm; | ||
800 | 808 | ||
801 | num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp); | 809 | num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp); |
802 | pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp); | 810 | pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp); |
803 | vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp); | 811 | vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp); |
804 | rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp); | 812 | rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp); |
813 | vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp); | ||
814 | |||
815 | /* vlanf could be wrongly set in some cards. | ||
816 | * ignore if vtm is not set */ | ||
817 | if ((adapter->cap == 0x400) && !vtm) | ||
818 | vlanf = 0; | ||
805 | 819 | ||
806 | skb = napi_get_frags(&eq_obj->napi); | 820 | skb = napi_get_frags(&eq_obj->napi); |
807 | if (!skb) { | 821 | if (!skb) { |
@@ -2045,7 +2059,8 @@ static int be_hw_up(struct be_adapter *adapter) | |||
2045 | if (status) | 2059 | if (status) |
2046 | return status; | 2060 | return status; |
2047 | 2061 | ||
2048 | status = be_cmd_query_fw_cfg(adapter, &adapter->port_num); | 2062 | status = be_cmd_query_fw_cfg(adapter, |
2063 | &adapter->port_num, &adapter->cap); | ||
2049 | return status; | 2064 | return status; |
2050 | } | 2065 | } |
2051 | 2066 | ||
diff --git a/drivers/net/bonding/bond_sysfs.c b/drivers/net/bonding/bond_sysfs.c index 6044e12ff9fc..ff449de6f3c0 100644 --- a/drivers/net/bonding/bond_sysfs.c +++ b/drivers/net/bonding/bond_sysfs.c | |||
@@ -1182,6 +1182,7 @@ static ssize_t bonding_store_primary(struct device *d, | |||
1182 | ": %s: Setting %s as primary slave.\n", | 1182 | ": %s: Setting %s as primary slave.\n", |
1183 | bond->dev->name, slave->dev->name); | 1183 | bond->dev->name, slave->dev->name); |
1184 | bond->primary_slave = slave; | 1184 | bond->primary_slave = slave; |
1185 | strcpy(bond->params.primary, slave->dev->name); | ||
1185 | bond_select_active_slave(bond); | 1186 | bond_select_active_slave(bond); |
1186 | goto out; | 1187 | goto out; |
1187 | } | 1188 | } |
diff --git a/drivers/net/cnic.c b/drivers/net/cnic.c index 211c8e9182fc..46c87ec7960c 100644 --- a/drivers/net/cnic.c +++ b/drivers/net/cnic.c | |||
@@ -2733,7 +2733,8 @@ static int cnic_netdev_event(struct notifier_block *this, unsigned long event, | |||
2733 | cnic_ulp_init(dev); | 2733 | cnic_ulp_init(dev); |
2734 | else if (event == NETDEV_UNREGISTER) | 2734 | else if (event == NETDEV_UNREGISTER) |
2735 | cnic_ulp_exit(dev); | 2735 | cnic_ulp_exit(dev); |
2736 | else if (event == NETDEV_UP) { | 2736 | |
2737 | if (event == NETDEV_UP) { | ||
2737 | if (cnic_register_netdev(dev) != 0) { | 2738 | if (cnic_register_netdev(dev) != 0) { |
2738 | cnic_put(dev); | 2739 | cnic_put(dev); |
2739 | goto done; | 2740 | goto done; |
diff --git a/drivers/net/cnic_if.h b/drivers/net/cnic_if.h index a49235739eef..d8b09efdcb52 100644 --- a/drivers/net/cnic_if.h +++ b/drivers/net/cnic_if.h | |||
@@ -12,8 +12,8 @@ | |||
12 | #ifndef CNIC_IF_H | 12 | #ifndef CNIC_IF_H |
13 | #define CNIC_IF_H | 13 | #define CNIC_IF_H |
14 | 14 | ||
15 | #define CNIC_MODULE_VERSION "2.0.0" | 15 | #define CNIC_MODULE_VERSION "2.0.1" |
16 | #define CNIC_MODULE_RELDATE "May 21, 2009" | 16 | #define CNIC_MODULE_RELDATE "Oct 01, 2009" |
17 | 17 | ||
18 | #define CNIC_ULP_RDMA 0 | 18 | #define CNIC_ULP_RDMA 0 |
19 | #define CNIC_ULP_ISCSI 1 | 19 | #define CNIC_ULP_ISCSI 1 |
diff --git a/drivers/net/e1000/e1000.h b/drivers/net/e1000/e1000.h index 1a4f89c66a26..42e2b7e21c29 100644 --- a/drivers/net/e1000/e1000.h +++ b/drivers/net/e1000/e1000.h | |||
@@ -149,7 +149,6 @@ do { \ | |||
149 | 149 | ||
150 | #define AUTO_ALL_MODES 0 | 150 | #define AUTO_ALL_MODES 0 |
151 | #define E1000_EEPROM_82544_APM 0x0004 | 151 | #define E1000_EEPROM_82544_APM 0x0004 |
152 | #define E1000_EEPROM_ICH8_APME 0x0004 | ||
153 | #define E1000_EEPROM_APME 0x0400 | 152 | #define E1000_EEPROM_APME 0x0400 |
154 | 153 | ||
155 | #ifndef E1000_MASTER_SLAVE | 154 | #ifndef E1000_MASTER_SLAVE |
@@ -293,7 +292,6 @@ struct e1000_adapter { | |||
293 | 292 | ||
294 | u64 hw_csum_err; | 293 | u64 hw_csum_err; |
295 | u64 hw_csum_good; | 294 | u64 hw_csum_good; |
296 | u64 rx_hdr_split; | ||
297 | u32 alloc_rx_buff_failed; | 295 | u32 alloc_rx_buff_failed; |
298 | u32 rx_int_delay; | 296 | u32 rx_int_delay; |
299 | u32 rx_abs_int_delay; | 297 | u32 rx_abs_int_delay; |
@@ -317,7 +315,6 @@ struct e1000_adapter { | |||
317 | struct e1000_rx_ring test_rx_ring; | 315 | struct e1000_rx_ring test_rx_ring; |
318 | 316 | ||
319 | int msg_enable; | 317 | int msg_enable; |
320 | bool have_msi; | ||
321 | 318 | ||
322 | /* to not mess up cache alignment, always add to the bottom */ | 319 | /* to not mess up cache alignment, always add to the bottom */ |
323 | bool tso_force; | 320 | bool tso_force; |
diff --git a/drivers/net/e1000/e1000_ethtool.c b/drivers/net/e1000/e1000_ethtool.c index 27f996a2010f..490b2b7cd3ab 100644 --- a/drivers/net/e1000/e1000_ethtool.c +++ b/drivers/net/e1000/e1000_ethtool.c | |||
@@ -82,7 +82,6 @@ static const struct e1000_stats e1000_gstrings_stats[] = { | |||
82 | { "rx_long_byte_count", E1000_STAT(stats.gorcl) }, | 82 | { "rx_long_byte_count", E1000_STAT(stats.gorcl) }, |
83 | { "rx_csum_offload_good", E1000_STAT(hw_csum_good) }, | 83 | { "rx_csum_offload_good", E1000_STAT(hw_csum_good) }, |
84 | { "rx_csum_offload_errors", E1000_STAT(hw_csum_err) }, | 84 | { "rx_csum_offload_errors", E1000_STAT(hw_csum_err) }, |
85 | { "rx_header_split", E1000_STAT(rx_hdr_split) }, | ||
86 | { "alloc_rx_buff_failed", E1000_STAT(alloc_rx_buff_failed) }, | 85 | { "alloc_rx_buff_failed", E1000_STAT(alloc_rx_buff_failed) }, |
87 | { "tx_smbus", E1000_STAT(stats.mgptc) }, | 86 | { "tx_smbus", E1000_STAT(stats.mgptc) }, |
88 | { "rx_smbus", E1000_STAT(stats.mgprc) }, | 87 | { "rx_smbus", E1000_STAT(stats.mgprc) }, |
@@ -114,8 +113,6 @@ static int e1000_get_settings(struct net_device *netdev, | |||
114 | SUPPORTED_1000baseT_Full| | 113 | SUPPORTED_1000baseT_Full| |
115 | SUPPORTED_Autoneg | | 114 | SUPPORTED_Autoneg | |
116 | SUPPORTED_TP); | 115 | SUPPORTED_TP); |
117 | if (hw->phy_type == e1000_phy_ife) | ||
118 | ecmd->supported &= ~SUPPORTED_1000baseT_Full; | ||
119 | ecmd->advertising = ADVERTISED_TP; | 116 | ecmd->advertising = ADVERTISED_TP; |
120 | 117 | ||
121 | if (hw->autoneg == 1) { | 118 | if (hw->autoneg == 1) { |
@@ -178,14 +175,6 @@ static int e1000_set_settings(struct net_device *netdev, | |||
178 | struct e1000_adapter *adapter = netdev_priv(netdev); | 175 | struct e1000_adapter *adapter = netdev_priv(netdev); |
179 | struct e1000_hw *hw = &adapter->hw; | 176 | struct e1000_hw *hw = &adapter->hw; |
180 | 177 | ||
181 | /* When SoL/IDER sessions are active, autoneg/speed/duplex | ||
182 | * cannot be changed */ | ||
183 | if (e1000_check_phy_reset_block(hw)) { | ||
184 | DPRINTK(DRV, ERR, "Cannot change link characteristics " | ||
185 | "when SoL/IDER is active.\n"); | ||
186 | return -EINVAL; | ||
187 | } | ||
188 | |||
189 | while (test_and_set_bit(__E1000_RESETTING, &adapter->flags)) | 178 | while (test_and_set_bit(__E1000_RESETTING, &adapter->flags)) |
190 | msleep(1); | 179 | msleep(1); |
191 | 180 | ||
@@ -330,10 +319,7 @@ static int e1000_set_tso(struct net_device *netdev, u32 data) | |||
330 | else | 319 | else |
331 | netdev->features &= ~NETIF_F_TSO; | 320 | netdev->features &= ~NETIF_F_TSO; |
332 | 321 | ||
333 | if (data && (adapter->hw.mac_type > e1000_82547_rev_2)) | 322 | netdev->features &= ~NETIF_F_TSO6; |
334 | netdev->features |= NETIF_F_TSO6; | ||
335 | else | ||
336 | netdev->features &= ~NETIF_F_TSO6; | ||
337 | 323 | ||
338 | DPRINTK(PROBE, INFO, "TSO is %s\n", data ? "Enabled" : "Disabled"); | 324 | DPRINTK(PROBE, INFO, "TSO is %s\n", data ? "Enabled" : "Disabled"); |
339 | adapter->tso_force = true; | 325 | adapter->tso_force = true; |
@@ -441,7 +427,6 @@ static void e1000_get_regs(struct net_device *netdev, struct ethtool_regs *regs, | |||
441 | regs_buff[24] = (u32)phy_data; /* phy local receiver status */ | 427 | regs_buff[24] = (u32)phy_data; /* phy local receiver status */ |
442 | regs_buff[25] = regs_buff[24]; /* phy remote receiver status */ | 428 | regs_buff[25] = regs_buff[24]; /* phy remote receiver status */ |
443 | if (hw->mac_type >= e1000_82540 && | 429 | if (hw->mac_type >= e1000_82540 && |
444 | hw->mac_type < e1000_82571 && | ||
445 | hw->media_type == e1000_media_type_copper) { | 430 | hw->media_type == e1000_media_type_copper) { |
446 | regs_buff[26] = er32(MANC); | 431 | regs_buff[26] = er32(MANC); |
447 | } | 432 | } |
@@ -554,10 +539,8 @@ static int e1000_set_eeprom(struct net_device *netdev, | |||
554 | ret_val = e1000_write_eeprom(hw, first_word, | 539 | ret_val = e1000_write_eeprom(hw, first_word, |
555 | last_word - first_word + 1, eeprom_buff); | 540 | last_word - first_word + 1, eeprom_buff); |
556 | 541 | ||
557 | /* Update the checksum over the first part of the EEPROM if needed | 542 | /* Update the checksum over the first part of the EEPROM if needed */ |
558 | * and flush shadow RAM for 82573 conrollers */ | 543 | if ((ret_val == 0) && (first_word <= EEPROM_CHECKSUM_REG)) |
559 | if ((ret_val == 0) && ((first_word <= EEPROM_CHECKSUM_REG) || | ||
560 | (hw->mac_type == e1000_82573))) | ||
561 | e1000_update_eeprom_checksum(hw); | 544 | e1000_update_eeprom_checksum(hw); |
562 | 545 | ||
563 | kfree(eeprom_buff); | 546 | kfree(eeprom_buff); |
@@ -568,31 +551,12 @@ static void e1000_get_drvinfo(struct net_device *netdev, | |||
568 | struct ethtool_drvinfo *drvinfo) | 551 | struct ethtool_drvinfo *drvinfo) |
569 | { | 552 | { |
570 | struct e1000_adapter *adapter = netdev_priv(netdev); | 553 | struct e1000_adapter *adapter = netdev_priv(netdev); |
571 | struct e1000_hw *hw = &adapter->hw; | ||
572 | char firmware_version[32]; | 554 | char firmware_version[32]; |
573 | u16 eeprom_data; | ||
574 | 555 | ||
575 | strncpy(drvinfo->driver, e1000_driver_name, 32); | 556 | strncpy(drvinfo->driver, e1000_driver_name, 32); |
576 | strncpy(drvinfo->version, e1000_driver_version, 32); | 557 | strncpy(drvinfo->version, e1000_driver_version, 32); |
577 | 558 | ||
578 | /* EEPROM image version # is reported as firmware version # for | 559 | sprintf(firmware_version, "N/A"); |
579 | * 8257{1|2|3} controllers */ | ||
580 | e1000_read_eeprom(hw, 5, 1, &eeprom_data); | ||
581 | switch (hw->mac_type) { | ||
582 | case e1000_82571: | ||
583 | case e1000_82572: | ||
584 | case e1000_82573: | ||
585 | case e1000_80003es2lan: | ||
586 | case e1000_ich8lan: | ||
587 | sprintf(firmware_version, "%d.%d-%d", | ||
588 | (eeprom_data & 0xF000) >> 12, | ||
589 | (eeprom_data & 0x0FF0) >> 4, | ||
590 | eeprom_data & 0x000F); | ||
591 | break; | ||
592 | default: | ||
593 | sprintf(firmware_version, "N/A"); | ||
594 | } | ||
595 | |||
596 | strncpy(drvinfo->fw_version, firmware_version, 32); | 560 | strncpy(drvinfo->fw_version, firmware_version, 32); |
597 | strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32); | 561 | strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32); |
598 | drvinfo->regdump_len = e1000_get_regs_len(netdev); | 562 | drvinfo->regdump_len = e1000_get_regs_len(netdev); |
@@ -781,21 +745,9 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data) | |||
781 | /* The status register is Read Only, so a write should fail. | 745 | /* The status register is Read Only, so a write should fail. |
782 | * Some bits that get toggled are ignored. | 746 | * Some bits that get toggled are ignored. |
783 | */ | 747 | */ |
784 | switch (hw->mac_type) { | 748 | |
785 | /* there are several bits on newer hardware that are r/w */ | 749 | /* there are several bits on newer hardware that are r/w */ |
786 | case e1000_82571: | 750 | toggle = 0xFFFFF833; |
787 | case e1000_82572: | ||
788 | case e1000_80003es2lan: | ||
789 | toggle = 0x7FFFF3FF; | ||
790 | break; | ||
791 | case e1000_82573: | ||
792 | case e1000_ich8lan: | ||
793 | toggle = 0x7FFFF033; | ||
794 | break; | ||
795 | default: | ||
796 | toggle = 0xFFFFF833; | ||
797 | break; | ||
798 | } | ||
799 | 751 | ||
800 | before = er32(STATUS); | 752 | before = er32(STATUS); |
801 | value = (er32(STATUS) & toggle); | 753 | value = (er32(STATUS) & toggle); |
@@ -810,12 +762,10 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data) | |||
810 | /* restore previous status */ | 762 | /* restore previous status */ |
811 | ew32(STATUS, before); | 763 | ew32(STATUS, before); |
812 | 764 | ||
813 | if (hw->mac_type != e1000_ich8lan) { | 765 | REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF); |
814 | REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF); | 766 | REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF); |
815 | REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF); | 767 | REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF); |
816 | REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF); | 768 | REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF); |
817 | REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF); | ||
818 | } | ||
819 | 769 | ||
820 | REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF); | 770 | REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF); |
821 | REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF); | 771 | REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF); |
@@ -830,8 +780,7 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data) | |||
830 | 780 | ||
831 | REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000); | 781 | REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000); |
832 | 782 | ||
833 | before = (hw->mac_type == e1000_ich8lan ? | 783 | before = 0x06DFB3FE; |
834 | 0x06C3B33E : 0x06DFB3FE); | ||
835 | REG_SET_AND_CHECK(RCTL, before, 0x003FFFFB); | 784 | REG_SET_AND_CHECK(RCTL, before, 0x003FFFFB); |
836 | REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000); | 785 | REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000); |
837 | 786 | ||
@@ -839,12 +788,10 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data) | |||
839 | 788 | ||
840 | REG_SET_AND_CHECK(RCTL, before, 0xFFFFFFFF); | 789 | REG_SET_AND_CHECK(RCTL, before, 0xFFFFFFFF); |
841 | REG_PATTERN_TEST(RDBAL, 0xFFFFFFF0, 0xFFFFFFFF); | 790 | REG_PATTERN_TEST(RDBAL, 0xFFFFFFF0, 0xFFFFFFFF); |
842 | if (hw->mac_type != e1000_ich8lan) | 791 | REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF); |
843 | REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF); | ||
844 | REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF); | 792 | REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF); |
845 | REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF); | 793 | REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF); |
846 | value = (hw->mac_type == e1000_ich8lan ? | 794 | value = E1000_RAR_ENTRIES; |
847 | E1000_RAR_ENTRIES_ICH8LAN : E1000_RAR_ENTRIES); | ||
848 | for (i = 0; i < value; i++) { | 795 | for (i = 0; i < value; i++) { |
849 | REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF, | 796 | REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF, |
850 | 0xFFFFFFFF); | 797 | 0xFFFFFFFF); |
@@ -859,8 +806,7 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data) | |||
859 | 806 | ||
860 | } | 807 | } |
861 | 808 | ||
862 | value = (hw->mac_type == e1000_ich8lan ? | 809 | value = E1000_MC_TBL_SIZE; |
863 | E1000_MC_TBL_SIZE_ICH8LAN : E1000_MC_TBL_SIZE); | ||
864 | for (i = 0; i < value; i++) | 810 | for (i = 0; i < value; i++) |
865 | REG_PATTERN_TEST(MTA + (i << 2), 0xFFFFFFFF, 0xFFFFFFFF); | 811 | REG_PATTERN_TEST(MTA + (i << 2), 0xFFFFFFFF, 0xFFFFFFFF); |
866 | 812 | ||
@@ -933,9 +879,6 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data) | |||
933 | /* Test each interrupt */ | 879 | /* Test each interrupt */ |
934 | for (; i < 10; i++) { | 880 | for (; i < 10; i++) { |
935 | 881 | ||
936 | if (hw->mac_type == e1000_ich8lan && i == 8) | ||
937 | continue; | ||
938 | |||
939 | /* Interrupt to test */ | 882 | /* Interrupt to test */ |
940 | mask = 1 << i; | 883 | mask = 1 << i; |
941 | 884 | ||
@@ -1289,35 +1232,20 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter) | |||
1289 | e1000_write_phy_reg(hw, PHY_CTRL, 0x9140); | 1232 | e1000_write_phy_reg(hw, PHY_CTRL, 0x9140); |
1290 | /* autoneg off */ | 1233 | /* autoneg off */ |
1291 | e1000_write_phy_reg(hw, PHY_CTRL, 0x8140); | 1234 | e1000_write_phy_reg(hw, PHY_CTRL, 0x8140); |
1292 | } else if (hw->phy_type == e1000_phy_gg82563) | 1235 | } |
1293 | e1000_write_phy_reg(hw, | ||
1294 | GG82563_PHY_KMRN_MODE_CTRL, | ||
1295 | 0x1CC); | ||
1296 | 1236 | ||
1297 | ctrl_reg = er32(CTRL); | 1237 | ctrl_reg = er32(CTRL); |
1298 | 1238 | ||
1299 | if (hw->phy_type == e1000_phy_ife) { | 1239 | /* force 1000, set loopback */ |
1300 | /* force 100, set loopback */ | 1240 | e1000_write_phy_reg(hw, PHY_CTRL, 0x4140); |
1301 | e1000_write_phy_reg(hw, PHY_CTRL, 0x6100); | ||
1302 | 1241 | ||
1303 | /* Now set up the MAC to the same speed/duplex as the PHY. */ | 1242 | /* Now set up the MAC to the same speed/duplex as the PHY. */ |
1304 | ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ | 1243 | ctrl_reg = er32(CTRL); |
1305 | ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ | 1244 | ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ |
1306 | E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ | 1245 | ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ |
1307 | E1000_CTRL_SPD_100 |/* Force Speed to 100 */ | 1246 | E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ |
1308 | E1000_CTRL_FD); /* Force Duplex to FULL */ | 1247 | E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ |
1309 | } else { | 1248 | E1000_CTRL_FD); /* Force Duplex to FULL */ |
1310 | /* force 1000, set loopback */ | ||
1311 | e1000_write_phy_reg(hw, PHY_CTRL, 0x4140); | ||
1312 | |||
1313 | /* Now set up the MAC to the same speed/duplex as the PHY. */ | ||
1314 | ctrl_reg = er32(CTRL); | ||
1315 | ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ | ||
1316 | ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ | ||
1317 | E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ | ||
1318 | E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ | ||
1319 | E1000_CTRL_FD); /* Force Duplex to FULL */ | ||
1320 | } | ||
1321 | 1249 | ||
1322 | if (hw->media_type == e1000_media_type_copper && | 1250 | if (hw->media_type == e1000_media_type_copper && |
1323 | hw->phy_type == e1000_phy_m88) | 1251 | hw->phy_type == e1000_phy_m88) |
@@ -1373,14 +1301,8 @@ static int e1000_set_phy_loopback(struct e1000_adapter *adapter) | |||
1373 | case e1000_82541_rev_2: | 1301 | case e1000_82541_rev_2: |
1374 | case e1000_82547: | 1302 | case e1000_82547: |
1375 | case e1000_82547_rev_2: | 1303 | case e1000_82547_rev_2: |
1376 | case e1000_82571: | ||
1377 | case e1000_82572: | ||
1378 | case e1000_82573: | ||
1379 | case e1000_80003es2lan: | ||
1380 | case e1000_ich8lan: | ||
1381 | return e1000_integrated_phy_loopback(adapter); | 1304 | return e1000_integrated_phy_loopback(adapter); |
1382 | break; | 1305 | break; |
1383 | |||
1384 | default: | 1306 | default: |
1385 | /* Default PHY loopback work is to read the MII | 1307 | /* Default PHY loopback work is to read the MII |
1386 | * control register and assert bit 14 (loopback mode). | 1308 | * control register and assert bit 14 (loopback mode). |
@@ -1409,14 +1331,6 @@ static int e1000_setup_loopback_test(struct e1000_adapter *adapter) | |||
1409 | case e1000_82546_rev_3: | 1331 | case e1000_82546_rev_3: |
1410 | return e1000_set_phy_loopback(adapter); | 1332 | return e1000_set_phy_loopback(adapter); |
1411 | break; | 1333 | break; |
1412 | case e1000_82571: | ||
1413 | case e1000_82572: | ||
1414 | #define E1000_SERDES_LB_ON 0x410 | ||
1415 | e1000_set_phy_loopback(adapter); | ||
1416 | ew32(SCTL, E1000_SERDES_LB_ON); | ||
1417 | msleep(10); | ||
1418 | return 0; | ||
1419 | break; | ||
1420 | default: | 1334 | default: |
1421 | rctl = er32(RCTL); | 1335 | rctl = er32(RCTL); |
1422 | rctl |= E1000_RCTL_LBM_TCVR; | 1336 | rctl |= E1000_RCTL_LBM_TCVR; |
@@ -1440,26 +1354,12 @@ static void e1000_loopback_cleanup(struct e1000_adapter *adapter) | |||
1440 | ew32(RCTL, rctl); | 1354 | ew32(RCTL, rctl); |
1441 | 1355 | ||
1442 | switch (hw->mac_type) { | 1356 | switch (hw->mac_type) { |
1443 | case e1000_82571: | ||
1444 | case e1000_82572: | ||
1445 | if (hw->media_type == e1000_media_type_fiber || | ||
1446 | hw->media_type == e1000_media_type_internal_serdes) { | ||
1447 | #define E1000_SERDES_LB_OFF 0x400 | ||
1448 | ew32(SCTL, E1000_SERDES_LB_OFF); | ||
1449 | msleep(10); | ||
1450 | break; | ||
1451 | } | ||
1452 | /* Fall Through */ | ||
1453 | case e1000_82545: | 1357 | case e1000_82545: |
1454 | case e1000_82546: | 1358 | case e1000_82546: |
1455 | case e1000_82545_rev_3: | 1359 | case e1000_82545_rev_3: |
1456 | case e1000_82546_rev_3: | 1360 | case e1000_82546_rev_3: |
1457 | default: | 1361 | default: |
1458 | hw->autoneg = true; | 1362 | hw->autoneg = true; |
1459 | if (hw->phy_type == e1000_phy_gg82563) | ||
1460 | e1000_write_phy_reg(hw, | ||
1461 | GG82563_PHY_KMRN_MODE_CTRL, | ||
1462 | 0x180); | ||
1463 | e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); | 1363 | e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); |
1464 | if (phy_reg & MII_CR_LOOPBACK) { | 1364 | if (phy_reg & MII_CR_LOOPBACK) { |
1465 | phy_reg &= ~MII_CR_LOOPBACK; | 1365 | phy_reg &= ~MII_CR_LOOPBACK; |
@@ -1560,17 +1460,6 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter) | |||
1560 | 1460 | ||
1561 | static int e1000_loopback_test(struct e1000_adapter *adapter, u64 *data) | 1461 | static int e1000_loopback_test(struct e1000_adapter *adapter, u64 *data) |
1562 | { | 1462 | { |
1563 | struct e1000_hw *hw = &adapter->hw; | ||
1564 | |||
1565 | /* PHY loopback cannot be performed if SoL/IDER | ||
1566 | * sessions are active */ | ||
1567 | if (e1000_check_phy_reset_block(hw)) { | ||
1568 | DPRINTK(DRV, ERR, "Cannot do PHY loopback test " | ||
1569 | "when SoL/IDER is active.\n"); | ||
1570 | *data = 0; | ||
1571 | goto out; | ||
1572 | } | ||
1573 | |||
1574 | *data = e1000_setup_desc_rings(adapter); | 1463 | *data = e1000_setup_desc_rings(adapter); |
1575 | if (*data) | 1464 | if (*data) |
1576 | goto out; | 1465 | goto out; |
@@ -1592,13 +1481,13 @@ static int e1000_link_test(struct e1000_adapter *adapter, u64 *data) | |||
1592 | *data = 0; | 1481 | *data = 0; |
1593 | if (hw->media_type == e1000_media_type_internal_serdes) { | 1482 | if (hw->media_type == e1000_media_type_internal_serdes) { |
1594 | int i = 0; | 1483 | int i = 0; |
1595 | hw->serdes_link_down = true; | 1484 | hw->serdes_has_link = false; |
1596 | 1485 | ||
1597 | /* On some blade server designs, link establishment | 1486 | /* On some blade server designs, link establishment |
1598 | * could take as long as 2-3 minutes */ | 1487 | * could take as long as 2-3 minutes */ |
1599 | do { | 1488 | do { |
1600 | e1000_check_for_link(hw); | 1489 | e1000_check_for_link(hw); |
1601 | if (!hw->serdes_link_down) | 1490 | if (hw->serdes_has_link) |
1602 | return *data; | 1491 | return *data; |
1603 | msleep(20); | 1492 | msleep(20); |
1604 | } while (i++ < 3750); | 1493 | } while (i++ < 3750); |
@@ -1716,15 +1605,11 @@ static int e1000_wol_exclusion(struct e1000_adapter *adapter, | |||
1716 | case E1000_DEV_ID_82545EM_COPPER: | 1605 | case E1000_DEV_ID_82545EM_COPPER: |
1717 | case E1000_DEV_ID_82546GB_QUAD_COPPER: | 1606 | case E1000_DEV_ID_82546GB_QUAD_COPPER: |
1718 | case E1000_DEV_ID_82546GB_PCIE: | 1607 | case E1000_DEV_ID_82546GB_PCIE: |
1719 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | ||
1720 | /* these don't support WoL at all */ | 1608 | /* these don't support WoL at all */ |
1721 | wol->supported = 0; | 1609 | wol->supported = 0; |
1722 | break; | 1610 | break; |
1723 | case E1000_DEV_ID_82546EB_FIBER: | 1611 | case E1000_DEV_ID_82546EB_FIBER: |
1724 | case E1000_DEV_ID_82546GB_FIBER: | 1612 | case E1000_DEV_ID_82546GB_FIBER: |
1725 | case E1000_DEV_ID_82571EB_FIBER: | ||
1726 | case E1000_DEV_ID_82571EB_SERDES: | ||
1727 | case E1000_DEV_ID_82571EB_COPPER: | ||
1728 | /* Wake events not supported on port B */ | 1613 | /* Wake events not supported on port B */ |
1729 | if (er32(STATUS) & E1000_STATUS_FUNC_1) { | 1614 | if (er32(STATUS) & E1000_STATUS_FUNC_1) { |
1730 | wol->supported = 0; | 1615 | wol->supported = 0; |
@@ -1733,10 +1618,6 @@ static int e1000_wol_exclusion(struct e1000_adapter *adapter, | |||
1733 | /* return success for non excluded adapter ports */ | 1618 | /* return success for non excluded adapter ports */ |
1734 | retval = 0; | 1619 | retval = 0; |
1735 | break; | 1620 | break; |
1736 | case E1000_DEV_ID_82571EB_QUAD_COPPER: | ||
1737 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | ||
1738 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: | ||
1739 | case E1000_DEV_ID_82571PT_QUAD_COPPER: | ||
1740 | case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: | 1621 | case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: |
1741 | /* quad port adapters only support WoL on port A */ | 1622 | /* quad port adapters only support WoL on port A */ |
1742 | if (!adapter->quad_port_a) { | 1623 | if (!adapter->quad_port_a) { |
@@ -1872,30 +1753,15 @@ static int e1000_phys_id(struct net_device *netdev, u32 data) | |||
1872 | if (!data) | 1753 | if (!data) |
1873 | data = INT_MAX; | 1754 | data = INT_MAX; |
1874 | 1755 | ||
1875 | if (hw->mac_type < e1000_82571) { | 1756 | if (!adapter->blink_timer.function) { |
1876 | if (!adapter->blink_timer.function) { | 1757 | init_timer(&adapter->blink_timer); |
1877 | init_timer(&adapter->blink_timer); | 1758 | adapter->blink_timer.function = e1000_led_blink_callback; |
1878 | adapter->blink_timer.function = e1000_led_blink_callback; | 1759 | adapter->blink_timer.data = (unsigned long)adapter; |
1879 | adapter->blink_timer.data = (unsigned long)adapter; | ||
1880 | } | ||
1881 | e1000_setup_led(hw); | ||
1882 | mod_timer(&adapter->blink_timer, jiffies); | ||
1883 | msleep_interruptible(data * 1000); | ||
1884 | del_timer_sync(&adapter->blink_timer); | ||
1885 | } else if (hw->phy_type == e1000_phy_ife) { | ||
1886 | if (!adapter->blink_timer.function) { | ||
1887 | init_timer(&adapter->blink_timer); | ||
1888 | adapter->blink_timer.function = e1000_led_blink_callback; | ||
1889 | adapter->blink_timer.data = (unsigned long)adapter; | ||
1890 | } | ||
1891 | mod_timer(&adapter->blink_timer, jiffies); | ||
1892 | msleep_interruptible(data * 1000); | ||
1893 | del_timer_sync(&adapter->blink_timer); | ||
1894 | e1000_write_phy_reg(&(adapter->hw), IFE_PHY_SPECIAL_CONTROL_LED, 0); | ||
1895 | } else { | ||
1896 | e1000_blink_led_start(hw); | ||
1897 | msleep_interruptible(data * 1000); | ||
1898 | } | 1760 | } |
1761 | e1000_setup_led(hw); | ||
1762 | mod_timer(&adapter->blink_timer, jiffies); | ||
1763 | msleep_interruptible(data * 1000); | ||
1764 | del_timer_sync(&adapter->blink_timer); | ||
1899 | 1765 | ||
1900 | e1000_led_off(hw); | 1766 | e1000_led_off(hw); |
1901 | clear_bit(E1000_LED_ON, &adapter->led_status); | 1767 | clear_bit(E1000_LED_ON, &adapter->led_status); |
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c index 45ac225a7aaa..8d7d87f12827 100644 --- a/drivers/net/e1000/e1000_hw.c +++ b/drivers/net/e1000/e1000_hw.c | |||
@@ -24,88 +24,34 @@ | |||
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | 24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | 25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
26 | 26 | ||
27 | *******************************************************************************/ | 27 | */ |
28 | 28 | ||
29 | /* e1000_hw.c | 29 | /* e1000_hw.c |
30 | * Shared functions for accessing and configuring the MAC | 30 | * Shared functions for accessing and configuring the MAC |
31 | */ | 31 | */ |
32 | 32 | ||
33 | |||
34 | #include "e1000_hw.h" | 33 | #include "e1000_hw.h" |
35 | 34 | ||
36 | static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask); | ||
37 | static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask); | ||
38 | static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data); | ||
39 | static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data); | ||
40 | static s32 e1000_get_software_semaphore(struct e1000_hw *hw); | ||
41 | static void e1000_release_software_semaphore(struct e1000_hw *hw); | ||
42 | |||
43 | static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw); | ||
44 | static s32 e1000_check_downshift(struct e1000_hw *hw); | 35 | static s32 e1000_check_downshift(struct e1000_hw *hw); |
45 | static s32 e1000_check_polarity(struct e1000_hw *hw, | 36 | static s32 e1000_check_polarity(struct e1000_hw *hw, |
46 | e1000_rev_polarity *polarity); | 37 | e1000_rev_polarity *polarity); |
47 | static void e1000_clear_hw_cntrs(struct e1000_hw *hw); | 38 | static void e1000_clear_hw_cntrs(struct e1000_hw *hw); |
48 | static void e1000_clear_vfta(struct e1000_hw *hw); | 39 | static void e1000_clear_vfta(struct e1000_hw *hw); |
49 | static s32 e1000_commit_shadow_ram(struct e1000_hw *hw); | ||
50 | static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, | 40 | static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, |
51 | bool link_up); | 41 | bool link_up); |
52 | static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw); | 42 | static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw); |
53 | static s32 e1000_detect_gig_phy(struct e1000_hw *hw); | 43 | static s32 e1000_detect_gig_phy(struct e1000_hw *hw); |
54 | static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank); | ||
55 | static s32 e1000_get_auto_rd_done(struct e1000_hw *hw); | 44 | static s32 e1000_get_auto_rd_done(struct e1000_hw *hw); |
56 | static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, | 45 | static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, |
57 | u16 *max_length); | 46 | u16 *max_length); |
58 | static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); | ||
59 | static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); | 47 | static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); |
60 | static s32 e1000_get_software_flag(struct e1000_hw *hw); | ||
61 | static s32 e1000_ich8_cycle_init(struct e1000_hw *hw); | ||
62 | static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout); | ||
63 | static s32 e1000_id_led_init(struct e1000_hw *hw); | 48 | static s32 e1000_id_led_init(struct e1000_hw *hw); |
64 | static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, | ||
65 | u32 cnf_base_addr, | ||
66 | u32 cnf_size); | ||
67 | static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw); | ||
68 | static void e1000_init_rx_addrs(struct e1000_hw *hw); | 49 | static void e1000_init_rx_addrs(struct e1000_hw *hw); |
69 | static void e1000_initialize_hardware_bits(struct e1000_hw *hw); | ||
70 | static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); | ||
71 | static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw); | ||
72 | static s32 e1000_mng_enable_host_if(struct e1000_hw *hw); | ||
73 | static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length, | ||
74 | u16 offset, u8 *sum); | ||
75 | static s32 e1000_mng_write_cmd_header(struct e1000_hw* hw, | ||
76 | struct e1000_host_mng_command_header | ||
77 | *hdr); | ||
78 | static s32 e1000_mng_write_commit(struct e1000_hw *hw); | ||
79 | static s32 e1000_phy_ife_get_info(struct e1000_hw *hw, | ||
80 | struct e1000_phy_info *phy_info); | ||
81 | static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, | 50 | static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, |
82 | struct e1000_phy_info *phy_info); | 51 | struct e1000_phy_info *phy_info); |
83 | static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words, | ||
84 | u16 *data); | ||
85 | static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words, | ||
86 | u16 *data); | ||
87 | static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); | ||
88 | static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, | 52 | static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, |
89 | struct e1000_phy_info *phy_info); | 53 | struct e1000_phy_info *phy_info); |
90 | static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); | ||
91 | static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data); | ||
92 | static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, | ||
93 | u8 byte); | ||
94 | static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte); | ||
95 | static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data); | ||
96 | static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size, | ||
97 | u16 *data); | ||
98 | static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size, | ||
99 | u16 data); | ||
100 | static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, | ||
101 | u16 *data); | ||
102 | static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, | ||
103 | u16 *data); | ||
104 | static void e1000_release_software_flag(struct e1000_hw *hw); | ||
105 | static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); | 54 | static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); |
106 | static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); | ||
107 | static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop); | ||
108 | static void e1000_set_pci_express_master_disable(struct e1000_hw *hw); | ||
109 | static s32 e1000_wait_autoneg(struct e1000_hw *hw); | 55 | static s32 e1000_wait_autoneg(struct e1000_hw *hw); |
110 | static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value); | 56 | static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value); |
111 | static s32 e1000_set_phy_type(struct e1000_hw *hw); | 57 | static s32 e1000_set_phy_type(struct e1000_hw *hw); |
@@ -117,12 +63,11 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); | |||
117 | static s32 e1000_config_mac_to_phy(struct e1000_hw *hw); | 63 | static s32 e1000_config_mac_to_phy(struct e1000_hw *hw); |
118 | static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl); | 64 | static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl); |
119 | static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl); | 65 | static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl); |
120 | static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, | 66 | static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count); |
121 | u16 count); | ||
122 | static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw); | 67 | static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw); |
123 | static s32 e1000_phy_reset_dsp(struct e1000_hw *hw); | 68 | static s32 e1000_phy_reset_dsp(struct e1000_hw *hw); |
124 | static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, | 69 | static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, |
125 | u16 words, u16 *data); | 70 | u16 words, u16 *data); |
126 | static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, | 71 | static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, |
127 | u16 words, u16 *data); | 72 | u16 words, u16 *data); |
128 | static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw); | 73 | static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw); |
@@ -131,7 +76,7 @@ static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd); | |||
131 | static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count); | 76 | static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count); |
132 | static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, | 77 | static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, |
133 | u16 phy_data); | 78 | u16 phy_data); |
134 | static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw,u32 reg_addr, | 79 | static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, |
135 | u16 *phy_data); | 80 | u16 *phy_data); |
136 | static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count); | 81 | static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count); |
137 | static s32 e1000_acquire_eeprom(struct e1000_hw *hw); | 82 | static s32 e1000_acquire_eeprom(struct e1000_hw *hw); |
@@ -140,188 +85,164 @@ static void e1000_standby_eeprom(struct e1000_hw *hw); | |||
140 | static s32 e1000_set_vco_speed(struct e1000_hw *hw); | 85 | static s32 e1000_set_vco_speed(struct e1000_hw *hw); |
141 | static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw); | 86 | static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw); |
142 | static s32 e1000_set_phy_mode(struct e1000_hw *hw); | 87 | static s32 e1000_set_phy_mode(struct e1000_hw *hw); |
143 | static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer); | 88 | static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, |
144 | static u8 e1000_calculate_mng_checksum(char *buffer, u32 length); | 89 | u16 *data); |
145 | static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex); | 90 | static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, |
146 | static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw); | 91 | u16 *data); |
147 | static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); | ||
148 | static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); | ||
149 | 92 | ||
150 | /* IGP cable length table */ | 93 | /* IGP cable length table */ |
151 | static const | 94 | static const |
152 | u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = | 95 | u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = { |
153 | { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, | 96 | 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, |
154 | 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, | 97 | 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, |
155 | 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, | 98 | 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, |
156 | 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, | 99 | 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, |
157 | 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, | 100 | 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, |
158 | 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, | 101 | 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, |
159 | 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, | 102 | 100, |
160 | 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; | 103 | 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, |
161 | 104 | 110, 110, | |
162 | static const | 105 | 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, |
163 | u16 e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = | 106 | 120, 120 |
164 | { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, | 107 | }; |
165 | 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, | ||
166 | 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, | ||
167 | 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, | ||
168 | 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, | ||
169 | 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, | ||
170 | 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, | ||
171 | 104, 109, 114, 118, 121, 124}; | ||
172 | 108 | ||
173 | static DEFINE_SPINLOCK(e1000_eeprom_lock); | 109 | static DEFINE_SPINLOCK(e1000_eeprom_lock); |
174 | 110 | ||
175 | /****************************************************************************** | 111 | /** |
176 | * Set the phy type member in the hw struct. | 112 | * e1000_set_phy_type - Set the phy type member in the hw struct. |
177 | * | 113 | * @hw: Struct containing variables accessed by shared code |
178 | * hw - Struct containing variables accessed by shared code | 114 | */ |
179 | *****************************************************************************/ | ||
180 | static s32 e1000_set_phy_type(struct e1000_hw *hw) | 115 | static s32 e1000_set_phy_type(struct e1000_hw *hw) |
181 | { | 116 | { |
182 | DEBUGFUNC("e1000_set_phy_type"); | 117 | DEBUGFUNC("e1000_set_phy_type"); |
183 | |||
184 | if (hw->mac_type == e1000_undefined) | ||
185 | return -E1000_ERR_PHY_TYPE; | ||
186 | |||
187 | switch (hw->phy_id) { | ||
188 | case M88E1000_E_PHY_ID: | ||
189 | case M88E1000_I_PHY_ID: | ||
190 | case M88E1011_I_PHY_ID: | ||
191 | case M88E1111_I_PHY_ID: | ||
192 | hw->phy_type = e1000_phy_m88; | ||
193 | break; | ||
194 | case IGP01E1000_I_PHY_ID: | ||
195 | if (hw->mac_type == e1000_82541 || | ||
196 | hw->mac_type == e1000_82541_rev_2 || | ||
197 | hw->mac_type == e1000_82547 || | ||
198 | hw->mac_type == e1000_82547_rev_2) { | ||
199 | hw->phy_type = e1000_phy_igp; | ||
200 | break; | ||
201 | } | ||
202 | case IGP03E1000_E_PHY_ID: | ||
203 | hw->phy_type = e1000_phy_igp_3; | ||
204 | break; | ||
205 | case IFE_E_PHY_ID: | ||
206 | case IFE_PLUS_E_PHY_ID: | ||
207 | case IFE_C_E_PHY_ID: | ||
208 | hw->phy_type = e1000_phy_ife; | ||
209 | break; | ||
210 | case GG82563_E_PHY_ID: | ||
211 | if (hw->mac_type == e1000_80003es2lan) { | ||
212 | hw->phy_type = e1000_phy_gg82563; | ||
213 | break; | ||
214 | } | ||
215 | /* Fall Through */ | ||
216 | default: | ||
217 | /* Should never have loaded on this device */ | ||
218 | hw->phy_type = e1000_phy_undefined; | ||
219 | return -E1000_ERR_PHY_TYPE; | ||
220 | } | ||
221 | |||
222 | return E1000_SUCCESS; | ||
223 | } | ||
224 | |||
225 | /****************************************************************************** | ||
226 | * IGP phy init script - initializes the GbE PHY | ||
227 | * | ||
228 | * hw - Struct containing variables accessed by shared code | ||
229 | *****************************************************************************/ | ||
230 | static void e1000_phy_init_script(struct e1000_hw *hw) | ||
231 | { | ||
232 | u32 ret_val; | ||
233 | u16 phy_saved_data; | ||
234 | |||
235 | DEBUGFUNC("e1000_phy_init_script"); | ||
236 | |||
237 | if (hw->phy_init_script) { | ||
238 | msleep(20); | ||
239 | |||
240 | /* Save off the current value of register 0x2F5B to be restored at | ||
241 | * the end of this routine. */ | ||
242 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); | ||
243 | |||
244 | /* Disabled the PHY transmitter */ | ||
245 | e1000_write_phy_reg(hw, 0x2F5B, 0x0003); | ||
246 | 118 | ||
247 | msleep(20); | 119 | if (hw->mac_type == e1000_undefined) |
120 | return -E1000_ERR_PHY_TYPE; | ||
248 | 121 | ||
249 | e1000_write_phy_reg(hw,0x0000,0x0140); | 122 | switch (hw->phy_id) { |
250 | 123 | case M88E1000_E_PHY_ID: | |
251 | msleep(5); | 124 | case M88E1000_I_PHY_ID: |
252 | 125 | case M88E1011_I_PHY_ID: | |
253 | switch (hw->mac_type) { | 126 | case M88E1111_I_PHY_ID: |
254 | case e1000_82541: | 127 | hw->phy_type = e1000_phy_m88; |
255 | case e1000_82547: | 128 | break; |
256 | e1000_write_phy_reg(hw, 0x1F95, 0x0001); | 129 | case IGP01E1000_I_PHY_ID: |
257 | 130 | if (hw->mac_type == e1000_82541 || | |
258 | e1000_write_phy_reg(hw, 0x1F71, 0xBD21); | 131 | hw->mac_type == e1000_82541_rev_2 || |
259 | 132 | hw->mac_type == e1000_82547 || | |
260 | e1000_write_phy_reg(hw, 0x1F79, 0x0018); | 133 | hw->mac_type == e1000_82547_rev_2) { |
261 | 134 | hw->phy_type = e1000_phy_igp; | |
262 | e1000_write_phy_reg(hw, 0x1F30, 0x1600); | 135 | break; |
263 | 136 | } | |
264 | e1000_write_phy_reg(hw, 0x1F31, 0x0014); | 137 | default: |
265 | 138 | /* Should never have loaded on this device */ | |
266 | e1000_write_phy_reg(hw, 0x1F32, 0x161C); | 139 | hw->phy_type = e1000_phy_undefined; |
267 | 140 | return -E1000_ERR_PHY_TYPE; | |
268 | e1000_write_phy_reg(hw, 0x1F94, 0x0003); | 141 | } |
269 | |||
270 | e1000_write_phy_reg(hw, 0x1F96, 0x003F); | ||
271 | |||
272 | e1000_write_phy_reg(hw, 0x2010, 0x0008); | ||
273 | break; | ||
274 | |||
275 | case e1000_82541_rev_2: | ||
276 | case e1000_82547_rev_2: | ||
277 | e1000_write_phy_reg(hw, 0x1F73, 0x0099); | ||
278 | break; | ||
279 | default: | ||
280 | break; | ||
281 | } | ||
282 | |||
283 | e1000_write_phy_reg(hw, 0x0000, 0x3300); | ||
284 | |||
285 | msleep(20); | ||
286 | |||
287 | /* Now enable the transmitter */ | ||
288 | e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | ||
289 | |||
290 | if (hw->mac_type == e1000_82547) { | ||
291 | u16 fused, fine, coarse; | ||
292 | |||
293 | /* Move to analog registers page */ | ||
294 | e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); | ||
295 | |||
296 | if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { | ||
297 | e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); | ||
298 | 142 | ||
299 | fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; | 143 | return E1000_SUCCESS; |
300 | coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; | 144 | } |
301 | 145 | ||
302 | if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { | 146 | /** |
303 | coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; | 147 | * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY |
304 | fine -= IGP01E1000_ANALOG_FUSE_FINE_1; | 148 | * @hw: Struct containing variables accessed by shared code |
305 | } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) | 149 | */ |
306 | fine -= IGP01E1000_ANALOG_FUSE_FINE_10; | 150 | static void e1000_phy_init_script(struct e1000_hw *hw) |
151 | { | ||
152 | u32 ret_val; | ||
153 | u16 phy_saved_data; | ||
154 | |||
155 | DEBUGFUNC("e1000_phy_init_script"); | ||
156 | |||
157 | if (hw->phy_init_script) { | ||
158 | msleep(20); | ||
159 | |||
160 | /* Save off the current value of register 0x2F5B to be restored at | ||
161 | * the end of this routine. */ | ||
162 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); | ||
163 | |||
164 | /* Disabled the PHY transmitter */ | ||
165 | e1000_write_phy_reg(hw, 0x2F5B, 0x0003); | ||
166 | msleep(20); | ||
167 | |||
168 | e1000_write_phy_reg(hw, 0x0000, 0x0140); | ||
169 | msleep(5); | ||
170 | |||
171 | switch (hw->mac_type) { | ||
172 | case e1000_82541: | ||
173 | case e1000_82547: | ||
174 | e1000_write_phy_reg(hw, 0x1F95, 0x0001); | ||
175 | e1000_write_phy_reg(hw, 0x1F71, 0xBD21); | ||
176 | e1000_write_phy_reg(hw, 0x1F79, 0x0018); | ||
177 | e1000_write_phy_reg(hw, 0x1F30, 0x1600); | ||
178 | e1000_write_phy_reg(hw, 0x1F31, 0x0014); | ||
179 | e1000_write_phy_reg(hw, 0x1F32, 0x161C); | ||
180 | e1000_write_phy_reg(hw, 0x1F94, 0x0003); | ||
181 | e1000_write_phy_reg(hw, 0x1F96, 0x003F); | ||
182 | e1000_write_phy_reg(hw, 0x2010, 0x0008); | ||
183 | break; | ||
307 | 184 | ||
308 | fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | | 185 | case e1000_82541_rev_2: |
309 | (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | | 186 | case e1000_82547_rev_2: |
310 | (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); | 187 | e1000_write_phy_reg(hw, 0x1F73, 0x0099); |
188 | break; | ||
189 | default: | ||
190 | break; | ||
191 | } | ||
311 | 192 | ||
312 | e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused); | 193 | e1000_write_phy_reg(hw, 0x0000, 0x3300); |
313 | e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, | 194 | msleep(20); |
314 | IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); | 195 | |
315 | } | 196 | /* Now enable the transmitter */ |
316 | } | 197 | e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
317 | } | 198 | |
199 | if (hw->mac_type == e1000_82547) { | ||
200 | u16 fused, fine, coarse; | ||
201 | |||
202 | /* Move to analog registers page */ | ||
203 | e1000_read_phy_reg(hw, | ||
204 | IGP01E1000_ANALOG_SPARE_FUSE_STATUS, | ||
205 | &fused); | ||
206 | |||
207 | if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { | ||
208 | e1000_read_phy_reg(hw, | ||
209 | IGP01E1000_ANALOG_FUSE_STATUS, | ||
210 | &fused); | ||
211 | |||
212 | fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; | ||
213 | coarse = | ||
214 | fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; | ||
215 | |||
216 | if (coarse > | ||
217 | IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { | ||
218 | coarse -= | ||
219 | IGP01E1000_ANALOG_FUSE_COARSE_10; | ||
220 | fine -= IGP01E1000_ANALOG_FUSE_FINE_1; | ||
221 | } else if (coarse == | ||
222 | IGP01E1000_ANALOG_FUSE_COARSE_THRESH) | ||
223 | fine -= IGP01E1000_ANALOG_FUSE_FINE_10; | ||
224 | |||
225 | fused = | ||
226 | (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | | ||
227 | (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | | ||
228 | (coarse & | ||
229 | IGP01E1000_ANALOG_FUSE_COARSE_MASK); | ||
230 | |||
231 | e1000_write_phy_reg(hw, | ||
232 | IGP01E1000_ANALOG_FUSE_CONTROL, | ||
233 | fused); | ||
234 | e1000_write_phy_reg(hw, | ||
235 | IGP01E1000_ANALOG_FUSE_BYPASS, | ||
236 | IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); | ||
237 | } | ||
238 | } | ||
239 | } | ||
318 | } | 240 | } |
319 | 241 | ||
320 | /****************************************************************************** | 242 | /** |
321 | * Set the mac type member in the hw struct. | 243 | * e1000_set_mac_type - Set the mac type member in the hw struct. |
322 | * | 244 | * @hw: Struct containing variables accessed by shared code |
323 | * hw - Struct containing variables accessed by shared code | 245 | */ |
324 | *****************************************************************************/ | ||
325 | s32 e1000_set_mac_type(struct e1000_hw *hw) | 246 | s32 e1000_set_mac_type(struct e1000_hw *hw) |
326 | { | 247 | { |
327 | DEBUGFUNC("e1000_set_mac_type"); | 248 | DEBUGFUNC("e1000_set_mac_type"); |
@@ -397,61 +318,12 @@ s32 e1000_set_mac_type(struct e1000_hw *hw) | |||
397 | case E1000_DEV_ID_82547GI: | 318 | case E1000_DEV_ID_82547GI: |
398 | hw->mac_type = e1000_82547_rev_2; | 319 | hw->mac_type = e1000_82547_rev_2; |
399 | break; | 320 | break; |
400 | case E1000_DEV_ID_82571EB_COPPER: | ||
401 | case E1000_DEV_ID_82571EB_FIBER: | ||
402 | case E1000_DEV_ID_82571EB_SERDES: | ||
403 | case E1000_DEV_ID_82571EB_SERDES_DUAL: | ||
404 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | ||
405 | case E1000_DEV_ID_82571EB_QUAD_COPPER: | ||
406 | case E1000_DEV_ID_82571PT_QUAD_COPPER: | ||
407 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | ||
408 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: | ||
409 | hw->mac_type = e1000_82571; | ||
410 | break; | ||
411 | case E1000_DEV_ID_82572EI_COPPER: | ||
412 | case E1000_DEV_ID_82572EI_FIBER: | ||
413 | case E1000_DEV_ID_82572EI_SERDES: | ||
414 | case E1000_DEV_ID_82572EI: | ||
415 | hw->mac_type = e1000_82572; | ||
416 | break; | ||
417 | case E1000_DEV_ID_82573E: | ||
418 | case E1000_DEV_ID_82573E_IAMT: | ||
419 | case E1000_DEV_ID_82573L: | ||
420 | hw->mac_type = e1000_82573; | ||
421 | break; | ||
422 | case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: | ||
423 | case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: | ||
424 | case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: | ||
425 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: | ||
426 | hw->mac_type = e1000_80003es2lan; | ||
427 | break; | ||
428 | case E1000_DEV_ID_ICH8_IGP_M_AMT: | ||
429 | case E1000_DEV_ID_ICH8_IGP_AMT: | ||
430 | case E1000_DEV_ID_ICH8_IGP_C: | ||
431 | case E1000_DEV_ID_ICH8_IFE: | ||
432 | case E1000_DEV_ID_ICH8_IFE_GT: | ||
433 | case E1000_DEV_ID_ICH8_IFE_G: | ||
434 | case E1000_DEV_ID_ICH8_IGP_M: | ||
435 | hw->mac_type = e1000_ich8lan; | ||
436 | break; | ||
437 | default: | 321 | default: |
438 | /* Should never have loaded on this device */ | 322 | /* Should never have loaded on this device */ |
439 | return -E1000_ERR_MAC_TYPE; | 323 | return -E1000_ERR_MAC_TYPE; |
440 | } | 324 | } |
441 | 325 | ||
442 | switch (hw->mac_type) { | 326 | switch (hw->mac_type) { |
443 | case e1000_ich8lan: | ||
444 | hw->swfwhw_semaphore_present = true; | ||
445 | hw->asf_firmware_present = true; | ||
446 | break; | ||
447 | case e1000_80003es2lan: | ||
448 | hw->swfw_sync_present = true; | ||
449 | /* fall through */ | ||
450 | case e1000_82571: | ||
451 | case e1000_82572: | ||
452 | case e1000_82573: | ||
453 | hw->eeprom_semaphore_present = true; | ||
454 | /* fall through */ | ||
455 | case e1000_82541: | 327 | case e1000_82541: |
456 | case e1000_82547: | 328 | case e1000_82547: |
457 | case e1000_82541_rev_2: | 329 | case e1000_82541_rev_2: |
@@ -468,6058 +340,4500 @@ s32 e1000_set_mac_type(struct e1000_hw *hw) | |||
468 | if (hw->mac_type == e1000_82543) | 340 | if (hw->mac_type == e1000_82543) |
469 | hw->bad_tx_carr_stats_fd = true; | 341 | hw->bad_tx_carr_stats_fd = true; |
470 | 342 | ||
471 | /* capable of receiving management packets to the host */ | ||
472 | if (hw->mac_type >= e1000_82571) | ||
473 | hw->has_manc2h = true; | ||
474 | |||
475 | /* In rare occasions, ESB2 systems would end up started without | ||
476 | * the RX unit being turned on. | ||
477 | */ | ||
478 | if (hw->mac_type == e1000_80003es2lan) | ||
479 | hw->rx_needs_kicking = true; | ||
480 | |||
481 | if (hw->mac_type > e1000_82544) | 343 | if (hw->mac_type > e1000_82544) |
482 | hw->has_smbus = true; | 344 | hw->has_smbus = true; |
483 | 345 | ||
484 | return E1000_SUCCESS; | 346 | return E1000_SUCCESS; |
485 | } | 347 | } |
486 | 348 | ||
487 | /***************************************************************************** | 349 | /** |
488 | * Set media type and TBI compatibility. | 350 | * e1000_set_media_type - Set media type and TBI compatibility. |
489 | * | 351 | * @hw: Struct containing variables accessed by shared code |
490 | * hw - Struct containing variables accessed by shared code | 352 | */ |
491 | * **************************************************************************/ | ||
492 | void e1000_set_media_type(struct e1000_hw *hw) | 353 | void e1000_set_media_type(struct e1000_hw *hw) |
493 | { | 354 | { |
494 | u32 status; | 355 | u32 status; |
495 | 356 | ||
496 | DEBUGFUNC("e1000_set_media_type"); | 357 | DEBUGFUNC("e1000_set_media_type"); |
497 | 358 | ||
498 | if (hw->mac_type != e1000_82543) { | 359 | if (hw->mac_type != e1000_82543) { |
499 | /* tbi_compatibility is only valid on 82543 */ | 360 | /* tbi_compatibility is only valid on 82543 */ |
500 | hw->tbi_compatibility_en = false; | 361 | hw->tbi_compatibility_en = false; |
501 | } | 362 | } |
502 | 363 | ||
503 | switch (hw->device_id) { | 364 | switch (hw->device_id) { |
504 | case E1000_DEV_ID_82545GM_SERDES: | 365 | case E1000_DEV_ID_82545GM_SERDES: |
505 | case E1000_DEV_ID_82546GB_SERDES: | 366 | case E1000_DEV_ID_82546GB_SERDES: |
506 | case E1000_DEV_ID_82571EB_SERDES: | 367 | hw->media_type = e1000_media_type_internal_serdes; |
507 | case E1000_DEV_ID_82571EB_SERDES_DUAL: | 368 | break; |
508 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | 369 | default: |
509 | case E1000_DEV_ID_82572EI_SERDES: | 370 | switch (hw->mac_type) { |
510 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: | 371 | case e1000_82542_rev2_0: |
511 | hw->media_type = e1000_media_type_internal_serdes; | 372 | case e1000_82542_rev2_1: |
512 | break; | 373 | hw->media_type = e1000_media_type_fiber; |
513 | default: | 374 | break; |
514 | switch (hw->mac_type) { | 375 | default: |
515 | case e1000_82542_rev2_0: | 376 | status = er32(STATUS); |
516 | case e1000_82542_rev2_1: | 377 | if (status & E1000_STATUS_TBIMODE) { |
517 | hw->media_type = e1000_media_type_fiber; | 378 | hw->media_type = e1000_media_type_fiber; |
518 | break; | 379 | /* tbi_compatibility not valid on fiber */ |
519 | case e1000_ich8lan: | 380 | hw->tbi_compatibility_en = false; |
520 | case e1000_82573: | 381 | } else { |
521 | /* The STATUS_TBIMODE bit is reserved or reused for the this | 382 | hw->media_type = e1000_media_type_copper; |
522 | * device. | 383 | } |
523 | */ | 384 | break; |
524 | hw->media_type = e1000_media_type_copper; | 385 | } |
525 | break; | 386 | } |
526 | default: | ||
527 | status = er32(STATUS); | ||
528 | if (status & E1000_STATUS_TBIMODE) { | ||
529 | hw->media_type = e1000_media_type_fiber; | ||
530 | /* tbi_compatibility not valid on fiber */ | ||
531 | hw->tbi_compatibility_en = false; | ||
532 | } else { | ||
533 | hw->media_type = e1000_media_type_copper; | ||
534 | } | ||
535 | break; | ||
536 | } | ||
537 | } | ||
538 | } | 387 | } |
539 | 388 | ||
540 | /****************************************************************************** | 389 | /** |
541 | * Reset the transmit and receive units; mask and clear all interrupts. | 390 | * e1000_reset_hw: reset the hardware completely |
391 | * @hw: Struct containing variables accessed by shared code | ||
542 | * | 392 | * |
543 | * hw - Struct containing variables accessed by shared code | 393 | * Reset the transmit and receive units; mask and clear all interrupts. |
544 | *****************************************************************************/ | 394 | */ |
545 | s32 e1000_reset_hw(struct e1000_hw *hw) | 395 | s32 e1000_reset_hw(struct e1000_hw *hw) |
546 | { | 396 | { |
547 | u32 ctrl; | 397 | u32 ctrl; |
548 | u32 ctrl_ext; | 398 | u32 ctrl_ext; |
549 | u32 icr; | 399 | u32 icr; |
550 | u32 manc; | 400 | u32 manc; |
551 | u32 led_ctrl; | 401 | u32 led_ctrl; |
552 | u32 timeout; | 402 | s32 ret_val; |
553 | u32 extcnf_ctrl; | ||
554 | s32 ret_val; | ||
555 | |||
556 | DEBUGFUNC("e1000_reset_hw"); | ||
557 | |||
558 | /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ | ||
559 | if (hw->mac_type == e1000_82542_rev2_0) { | ||
560 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); | ||
561 | e1000_pci_clear_mwi(hw); | ||
562 | } | ||
563 | |||
564 | if (hw->bus_type == e1000_bus_type_pci_express) { | ||
565 | /* Prevent the PCI-E bus from sticking if there is no TLP connection | ||
566 | * on the last TLP read/write transaction when MAC is reset. | ||
567 | */ | ||
568 | if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) { | ||
569 | DEBUGOUT("PCI-E Master disable polling has failed.\n"); | ||
570 | } | ||
571 | } | ||
572 | |||
573 | /* Clear interrupt mask to stop board from generating interrupts */ | ||
574 | DEBUGOUT("Masking off all interrupts\n"); | ||
575 | ew32(IMC, 0xffffffff); | ||
576 | |||
577 | /* Disable the Transmit and Receive units. Then delay to allow | ||
578 | * any pending transactions to complete before we hit the MAC with | ||
579 | * the global reset. | ||
580 | */ | ||
581 | ew32(RCTL, 0); | ||
582 | ew32(TCTL, E1000_TCTL_PSP); | ||
583 | E1000_WRITE_FLUSH(); | ||
584 | |||
585 | /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ | ||
586 | hw->tbi_compatibility_on = false; | ||
587 | |||
588 | /* Delay to allow any outstanding PCI transactions to complete before | ||
589 | * resetting the device | ||
590 | */ | ||
591 | msleep(10); | ||
592 | |||
593 | ctrl = er32(CTRL); | ||
594 | |||
595 | /* Must reset the PHY before resetting the MAC */ | ||
596 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { | ||
597 | ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST)); | ||
598 | msleep(5); | ||
599 | } | ||
600 | |||
601 | /* Must acquire the MDIO ownership before MAC reset. | ||
602 | * Ownership defaults to firmware after a reset. */ | ||
603 | if (hw->mac_type == e1000_82573) { | ||
604 | timeout = 10; | ||
605 | |||
606 | extcnf_ctrl = er32(EXTCNF_CTRL); | ||
607 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | ||
608 | |||
609 | do { | ||
610 | ew32(EXTCNF_CTRL, extcnf_ctrl); | ||
611 | extcnf_ctrl = er32(EXTCNF_CTRL); | ||
612 | |||
613 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) | ||
614 | break; | ||
615 | else | ||
616 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | ||
617 | |||
618 | msleep(2); | ||
619 | timeout--; | ||
620 | } while (timeout); | ||
621 | } | ||
622 | |||
623 | /* Workaround for ICH8 bit corruption issue in FIFO memory */ | ||
624 | if (hw->mac_type == e1000_ich8lan) { | ||
625 | /* Set Tx and Rx buffer allocation to 8k apiece. */ | ||
626 | ew32(PBA, E1000_PBA_8K); | ||
627 | /* Set Packet Buffer Size to 16k. */ | ||
628 | ew32(PBS, E1000_PBS_16K); | ||
629 | } | ||
630 | |||
631 | /* Issue a global reset to the MAC. This will reset the chip's | ||
632 | * transmit, receive, DMA, and link units. It will not effect | ||
633 | * the current PCI configuration. The global reset bit is self- | ||
634 | * clearing, and should clear within a microsecond. | ||
635 | */ | ||
636 | DEBUGOUT("Issuing a global reset to MAC\n"); | ||
637 | |||
638 | switch (hw->mac_type) { | ||
639 | case e1000_82544: | ||
640 | case e1000_82540: | ||
641 | case e1000_82545: | ||
642 | case e1000_82546: | ||
643 | case e1000_82541: | ||
644 | case e1000_82541_rev_2: | ||
645 | /* These controllers can't ack the 64-bit write when issuing the | ||
646 | * reset, so use IO-mapping as a workaround to issue the reset */ | ||
647 | E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); | ||
648 | break; | ||
649 | case e1000_82545_rev_3: | ||
650 | case e1000_82546_rev_3: | ||
651 | /* Reset is performed on a shadow of the control register */ | ||
652 | ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST)); | ||
653 | break; | ||
654 | case e1000_ich8lan: | ||
655 | if (!hw->phy_reset_disable && | ||
656 | e1000_check_phy_reset_block(hw) == E1000_SUCCESS) { | ||
657 | /* e1000_ich8lan PHY HW reset requires MAC CORE reset | ||
658 | * at the same time to make sure the interface between | ||
659 | * MAC and the external PHY is reset. | ||
660 | */ | ||
661 | ctrl |= E1000_CTRL_PHY_RST; | ||
662 | } | ||
663 | |||
664 | e1000_get_software_flag(hw); | ||
665 | ew32(CTRL, (ctrl | E1000_CTRL_RST)); | ||
666 | msleep(5); | ||
667 | break; | ||
668 | default: | ||
669 | ew32(CTRL, (ctrl | E1000_CTRL_RST)); | ||
670 | break; | ||
671 | } | ||
672 | |||
673 | /* After MAC reset, force reload of EEPROM to restore power-on settings to | ||
674 | * device. Later controllers reload the EEPROM automatically, so just wait | ||
675 | * for reload to complete. | ||
676 | */ | ||
677 | switch (hw->mac_type) { | ||
678 | case e1000_82542_rev2_0: | ||
679 | case e1000_82542_rev2_1: | ||
680 | case e1000_82543: | ||
681 | case e1000_82544: | ||
682 | /* Wait for reset to complete */ | ||
683 | udelay(10); | ||
684 | ctrl_ext = er32(CTRL_EXT); | ||
685 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | ||
686 | ew32(CTRL_EXT, ctrl_ext); | ||
687 | E1000_WRITE_FLUSH(); | ||
688 | /* Wait for EEPROM reload */ | ||
689 | msleep(2); | ||
690 | break; | ||
691 | case e1000_82541: | ||
692 | case e1000_82541_rev_2: | ||
693 | case e1000_82547: | ||
694 | case e1000_82547_rev_2: | ||
695 | /* Wait for EEPROM reload */ | ||
696 | msleep(20); | ||
697 | break; | ||
698 | case e1000_82573: | ||
699 | if (!e1000_is_onboard_nvm_eeprom(hw)) { | ||
700 | udelay(10); | ||
701 | ctrl_ext = er32(CTRL_EXT); | ||
702 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | ||
703 | ew32(CTRL_EXT, ctrl_ext); | ||
704 | E1000_WRITE_FLUSH(); | ||
705 | } | ||
706 | /* fall through */ | ||
707 | default: | ||
708 | /* Auto read done will delay 5ms or poll based on mac type */ | ||
709 | ret_val = e1000_get_auto_rd_done(hw); | ||
710 | if (ret_val) | ||
711 | return ret_val; | ||
712 | break; | ||
713 | } | ||
714 | |||
715 | /* Disable HW ARPs on ASF enabled adapters */ | ||
716 | if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { | ||
717 | manc = er32(MANC); | ||
718 | manc &= ~(E1000_MANC_ARP_EN); | ||
719 | ew32(MANC, manc); | ||
720 | } | ||
721 | |||
722 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { | ||
723 | e1000_phy_init_script(hw); | ||
724 | |||
725 | /* Configure activity LED after PHY reset */ | ||
726 | led_ctrl = er32(LEDCTL); | ||
727 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | ||
728 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | ||
729 | ew32(LEDCTL, led_ctrl); | ||
730 | } | ||
731 | |||
732 | /* Clear interrupt mask to stop board from generating interrupts */ | ||
733 | DEBUGOUT("Masking off all interrupts\n"); | ||
734 | ew32(IMC, 0xffffffff); | ||
735 | |||
736 | /* Clear any pending interrupt events. */ | ||
737 | icr = er32(ICR); | ||
738 | |||
739 | /* If MWI was previously enabled, reenable it. */ | ||
740 | if (hw->mac_type == e1000_82542_rev2_0) { | ||
741 | if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) | ||
742 | e1000_pci_set_mwi(hw); | ||
743 | } | ||
744 | |||
745 | if (hw->mac_type == e1000_ich8lan) { | ||
746 | u32 kab = er32(KABGTXD); | ||
747 | kab |= E1000_KABGTXD_BGSQLBIAS; | ||
748 | ew32(KABGTXD, kab); | ||
749 | } | ||
750 | |||
751 | return E1000_SUCCESS; | ||
752 | } | ||
753 | 403 | ||
754 | /****************************************************************************** | 404 | DEBUGFUNC("e1000_reset_hw"); |
755 | * | 405 | |
756 | * Initialize a number of hardware-dependent bits | 406 | /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ |
757 | * | 407 | if (hw->mac_type == e1000_82542_rev2_0) { |
758 | * hw: Struct containing variables accessed by shared code | 408 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); |
759 | * | 409 | e1000_pci_clear_mwi(hw); |
760 | * This function contains hardware limitation workarounds for PCI-E adapters | 410 | } |
761 | * | 411 | |
762 | *****************************************************************************/ | 412 | /* Clear interrupt mask to stop board from generating interrupts */ |
763 | static void e1000_initialize_hardware_bits(struct e1000_hw *hw) | 413 | DEBUGOUT("Masking off all interrupts\n"); |
764 | { | 414 | ew32(IMC, 0xffffffff); |
765 | if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) { | 415 | |
766 | /* Settings common to all PCI-express silicon */ | 416 | /* Disable the Transmit and Receive units. Then delay to allow |
767 | u32 reg_ctrl, reg_ctrl_ext; | 417 | * any pending transactions to complete before we hit the MAC with |
768 | u32 reg_tarc0, reg_tarc1; | 418 | * the global reset. |
769 | u32 reg_tctl; | 419 | */ |
770 | u32 reg_txdctl, reg_txdctl1; | 420 | ew32(RCTL, 0); |
771 | 421 | ew32(TCTL, E1000_TCTL_PSP); | |
772 | /* link autonegotiation/sync workarounds */ | 422 | E1000_WRITE_FLUSH(); |
773 | reg_tarc0 = er32(TARC0); | 423 | |
774 | reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); | 424 | /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ |
775 | 425 | hw->tbi_compatibility_on = false; | |
776 | /* Enable not-done TX descriptor counting */ | 426 | |
777 | reg_txdctl = er32(TXDCTL); | 427 | /* Delay to allow any outstanding PCI transactions to complete before |
778 | reg_txdctl |= E1000_TXDCTL_COUNT_DESC; | 428 | * resetting the device |
779 | ew32(TXDCTL, reg_txdctl); | 429 | */ |
780 | reg_txdctl1 = er32(TXDCTL1); | 430 | msleep(10); |
781 | reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; | 431 | |
782 | ew32(TXDCTL1, reg_txdctl1); | 432 | ctrl = er32(CTRL); |
783 | 433 | ||
784 | switch (hw->mac_type) { | 434 | /* Must reset the PHY before resetting the MAC */ |
785 | case e1000_82571: | 435 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
786 | case e1000_82572: | 436 | ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST)); |
787 | /* Clear PHY TX compatible mode bits */ | 437 | msleep(5); |
788 | reg_tarc1 = er32(TARC1); | 438 | } |
789 | reg_tarc1 &= ~((1 << 30)|(1 << 29)); | 439 | |
790 | 440 | /* Issue a global reset to the MAC. This will reset the chip's | |
791 | /* link autonegotiation/sync workarounds */ | 441 | * transmit, receive, DMA, and link units. It will not effect |
792 | reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); | 442 | * the current PCI configuration. The global reset bit is self- |
793 | 443 | * clearing, and should clear within a microsecond. | |
794 | /* TX ring control fixes */ | 444 | */ |
795 | reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); | 445 | DEBUGOUT("Issuing a global reset to MAC\n"); |
796 | 446 | ||
797 | /* Multiple read bit is reversed polarity */ | 447 | switch (hw->mac_type) { |
798 | reg_tctl = er32(TCTL); | 448 | case e1000_82544: |
799 | if (reg_tctl & E1000_TCTL_MULR) | 449 | case e1000_82540: |
800 | reg_tarc1 &= ~(1 << 28); | 450 | case e1000_82545: |
801 | else | 451 | case e1000_82546: |
802 | reg_tarc1 |= (1 << 28); | 452 | case e1000_82541: |
803 | 453 | case e1000_82541_rev_2: | |
804 | ew32(TARC1, reg_tarc1); | 454 | /* These controllers can't ack the 64-bit write when issuing the |
805 | break; | 455 | * reset, so use IO-mapping as a workaround to issue the reset */ |
806 | case e1000_82573: | 456 | E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
807 | reg_ctrl_ext = er32(CTRL_EXT); | 457 | break; |
808 | reg_ctrl_ext &= ~(1 << 23); | 458 | case e1000_82545_rev_3: |
809 | reg_ctrl_ext |= (1 << 22); | 459 | case e1000_82546_rev_3: |
810 | 460 | /* Reset is performed on a shadow of the control register */ | |
811 | /* TX byte count fix */ | 461 | ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST)); |
812 | reg_ctrl = er32(CTRL); | 462 | break; |
813 | reg_ctrl &= ~(1 << 29); | 463 | default: |
814 | 464 | ew32(CTRL, (ctrl | E1000_CTRL_RST)); | |
815 | ew32(CTRL_EXT, reg_ctrl_ext); | 465 | break; |
816 | ew32(CTRL, reg_ctrl); | 466 | } |
817 | break; | 467 | |
818 | case e1000_80003es2lan: | 468 | /* After MAC reset, force reload of EEPROM to restore power-on settings to |
819 | /* improve small packet performace for fiber/serdes */ | 469 | * device. Later controllers reload the EEPROM automatically, so just wait |
820 | if ((hw->media_type == e1000_media_type_fiber) || | 470 | * for reload to complete. |
821 | (hw->media_type == e1000_media_type_internal_serdes)) { | 471 | */ |
822 | reg_tarc0 &= ~(1 << 20); | 472 | switch (hw->mac_type) { |
823 | } | 473 | case e1000_82542_rev2_0: |
824 | 474 | case e1000_82542_rev2_1: | |
825 | /* Multiple read bit is reversed polarity */ | 475 | case e1000_82543: |
826 | reg_tctl = er32(TCTL); | 476 | case e1000_82544: |
827 | reg_tarc1 = er32(TARC1); | 477 | /* Wait for reset to complete */ |
828 | if (reg_tctl & E1000_TCTL_MULR) | 478 | udelay(10); |
829 | reg_tarc1 &= ~(1 << 28); | 479 | ctrl_ext = er32(CTRL_EXT); |
830 | else | 480 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
831 | reg_tarc1 |= (1 << 28); | 481 | ew32(CTRL_EXT, ctrl_ext); |
832 | 482 | E1000_WRITE_FLUSH(); | |
833 | ew32(TARC1, reg_tarc1); | 483 | /* Wait for EEPROM reload */ |
834 | break; | 484 | msleep(2); |
835 | case e1000_ich8lan: | 485 | break; |
836 | /* Reduce concurrent DMA requests to 3 from 4 */ | 486 | case e1000_82541: |
837 | if ((hw->revision_id < 3) || | 487 | case e1000_82541_rev_2: |
838 | ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && | 488 | case e1000_82547: |
839 | (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) | 489 | case e1000_82547_rev_2: |
840 | reg_tarc0 |= ((1 << 29)|(1 << 28)); | 490 | /* Wait for EEPROM reload */ |
841 | 491 | msleep(20); | |
842 | reg_ctrl_ext = er32(CTRL_EXT); | 492 | break; |
843 | reg_ctrl_ext |= (1 << 22); | 493 | default: |
844 | ew32(CTRL_EXT, reg_ctrl_ext); | 494 | /* Auto read done will delay 5ms or poll based on mac type */ |
845 | 495 | ret_val = e1000_get_auto_rd_done(hw); | |
846 | /* workaround TX hang with TSO=on */ | 496 | if (ret_val) |
847 | reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); | 497 | return ret_val; |
848 | 498 | break; | |
849 | /* Multiple read bit is reversed polarity */ | 499 | } |
850 | reg_tctl = er32(TCTL); | 500 | |
851 | reg_tarc1 = er32(TARC1); | 501 | /* Disable HW ARPs on ASF enabled adapters */ |
852 | if (reg_tctl & E1000_TCTL_MULR) | 502 | if (hw->mac_type >= e1000_82540) { |
853 | reg_tarc1 &= ~(1 << 28); | 503 | manc = er32(MANC); |
854 | else | 504 | manc &= ~(E1000_MANC_ARP_EN); |
855 | reg_tarc1 |= (1 << 28); | 505 | ew32(MANC, manc); |
856 | 506 | } | |
857 | /* workaround TX hang with TSO=on */ | 507 | |
858 | reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); | 508 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
859 | 509 | e1000_phy_init_script(hw); | |
860 | ew32(TARC1, reg_tarc1); | 510 | |
861 | break; | 511 | /* Configure activity LED after PHY reset */ |
862 | default: | 512 | led_ctrl = er32(LEDCTL); |
863 | break; | 513 | led_ctrl &= IGP_ACTIVITY_LED_MASK; |
864 | } | 514 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
865 | 515 | ew32(LEDCTL, led_ctrl); | |
866 | ew32(TARC0, reg_tarc0); | 516 | } |
867 | } | 517 | |
518 | /* Clear interrupt mask to stop board from generating interrupts */ | ||
519 | DEBUGOUT("Masking off all interrupts\n"); | ||
520 | ew32(IMC, 0xffffffff); | ||
521 | |||
522 | /* Clear any pending interrupt events. */ | ||
523 | icr = er32(ICR); | ||
524 | |||
525 | /* If MWI was previously enabled, reenable it. */ | ||
526 | if (hw->mac_type == e1000_82542_rev2_0) { | ||
527 | if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) | ||
528 | e1000_pci_set_mwi(hw); | ||
529 | } | ||
530 | |||
531 | return E1000_SUCCESS; | ||
868 | } | 532 | } |
869 | 533 | ||
870 | /****************************************************************************** | 534 | /** |
871 | * Performs basic configuration of the adapter. | 535 | * e1000_init_hw: Performs basic configuration of the adapter. |
872 | * | 536 | * @hw: Struct containing variables accessed by shared code |
873 | * hw - Struct containing variables accessed by shared code | ||
874 | * | 537 | * |
875 | * Assumes that the controller has previously been reset and is in a | 538 | * Assumes that the controller has previously been reset and is in a |
876 | * post-reset uninitialized state. Initializes the receive address registers, | 539 | * post-reset uninitialized state. Initializes the receive address registers, |
877 | * multicast table, and VLAN filter table. Calls routines to setup link | 540 | * multicast table, and VLAN filter table. Calls routines to setup link |
878 | * configuration and flow control settings. Clears all on-chip counters. Leaves | 541 | * configuration and flow control settings. Clears all on-chip counters. Leaves |
879 | * the transmit and receive units disabled and uninitialized. | 542 | * the transmit and receive units disabled and uninitialized. |
880 | *****************************************************************************/ | 543 | */ |
881 | s32 e1000_init_hw(struct e1000_hw *hw) | 544 | s32 e1000_init_hw(struct e1000_hw *hw) |
882 | { | 545 | { |
883 | u32 ctrl; | 546 | u32 ctrl; |
884 | u32 i; | 547 | u32 i; |
885 | s32 ret_val; | 548 | s32 ret_val; |
886 | u32 mta_size; | 549 | u32 mta_size; |
887 | u32 reg_data; | 550 | u32 ctrl_ext; |
888 | u32 ctrl_ext; | 551 | |
889 | 552 | DEBUGFUNC("e1000_init_hw"); | |
890 | DEBUGFUNC("e1000_init_hw"); | 553 | |
891 | 554 | /* Initialize Identification LED */ | |
892 | /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ | 555 | ret_val = e1000_id_led_init(hw); |
893 | if ((hw->mac_type == e1000_ich8lan) && | 556 | if (ret_val) { |
894 | ((hw->revision_id < 3) || | 557 | DEBUGOUT("Error Initializing Identification LED\n"); |
895 | ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && | 558 | return ret_val; |
896 | (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { | 559 | } |
897 | reg_data = er32(STATUS); | 560 | |
898 | reg_data &= ~0x80000000; | 561 | /* Set the media type and TBI compatibility */ |
899 | ew32(STATUS, reg_data); | 562 | e1000_set_media_type(hw); |
900 | } | 563 | |
901 | 564 | /* Disabling VLAN filtering. */ | |
902 | /* Initialize Identification LED */ | 565 | DEBUGOUT("Initializing the IEEE VLAN\n"); |
903 | ret_val = e1000_id_led_init(hw); | 566 | if (hw->mac_type < e1000_82545_rev_3) |
904 | if (ret_val) { | 567 | ew32(VET, 0); |
905 | DEBUGOUT("Error Initializing Identification LED\n"); | 568 | e1000_clear_vfta(hw); |
906 | return ret_val; | 569 | |
907 | } | 570 | /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ |
908 | 571 | if (hw->mac_type == e1000_82542_rev2_0) { | |
909 | /* Set the media type and TBI compatibility */ | 572 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); |
910 | e1000_set_media_type(hw); | 573 | e1000_pci_clear_mwi(hw); |
911 | 574 | ew32(RCTL, E1000_RCTL_RST); | |
912 | /* Must be called after e1000_set_media_type because media_type is used */ | 575 | E1000_WRITE_FLUSH(); |
913 | e1000_initialize_hardware_bits(hw); | 576 | msleep(5); |
914 | 577 | } | |
915 | /* Disabling VLAN filtering. */ | 578 | |
916 | DEBUGOUT("Initializing the IEEE VLAN\n"); | 579 | /* Setup the receive address. This involves initializing all of the Receive |
917 | /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ | 580 | * Address Registers (RARs 0 - 15). |
918 | if (hw->mac_type != e1000_ich8lan) { | 581 | */ |
919 | if (hw->mac_type < e1000_82545_rev_3) | 582 | e1000_init_rx_addrs(hw); |
920 | ew32(VET, 0); | 583 | |
921 | e1000_clear_vfta(hw); | 584 | /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ |
922 | } | 585 | if (hw->mac_type == e1000_82542_rev2_0) { |
923 | 586 | ew32(RCTL, 0); | |
924 | /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ | 587 | E1000_WRITE_FLUSH(); |
925 | if (hw->mac_type == e1000_82542_rev2_0) { | 588 | msleep(1); |
926 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); | 589 | if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) |
927 | e1000_pci_clear_mwi(hw); | 590 | e1000_pci_set_mwi(hw); |
928 | ew32(RCTL, E1000_RCTL_RST); | 591 | } |
929 | E1000_WRITE_FLUSH(); | 592 | |
930 | msleep(5); | 593 | /* Zero out the Multicast HASH table */ |
931 | } | 594 | DEBUGOUT("Zeroing the MTA\n"); |
932 | 595 | mta_size = E1000_MC_TBL_SIZE; | |
933 | /* Setup the receive address. This involves initializing all of the Receive | 596 | for (i = 0; i < mta_size; i++) { |
934 | * Address Registers (RARs 0 - 15). | 597 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
935 | */ | 598 | /* use write flush to prevent Memory Write Block (MWB) from |
936 | e1000_init_rx_addrs(hw); | 599 | * occurring when accessing our register space */ |
937 | 600 | E1000_WRITE_FLUSH(); | |
938 | /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ | 601 | } |
939 | if (hw->mac_type == e1000_82542_rev2_0) { | 602 | |
940 | ew32(RCTL, 0); | 603 | /* Set the PCI priority bit correctly in the CTRL register. This |
941 | E1000_WRITE_FLUSH(); | 604 | * determines if the adapter gives priority to receives, or if it |
942 | msleep(1); | 605 | * gives equal priority to transmits and receives. Valid only on |
943 | if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) | 606 | * 82542 and 82543 silicon. |
944 | e1000_pci_set_mwi(hw); | 607 | */ |
945 | } | 608 | if (hw->dma_fairness && hw->mac_type <= e1000_82543) { |
946 | 609 | ctrl = er32(CTRL); | |
947 | /* Zero out the Multicast HASH table */ | 610 | ew32(CTRL, ctrl | E1000_CTRL_PRIOR); |
948 | DEBUGOUT("Zeroing the MTA\n"); | 611 | } |
949 | mta_size = E1000_MC_TBL_SIZE; | 612 | |
950 | if (hw->mac_type == e1000_ich8lan) | 613 | switch (hw->mac_type) { |
951 | mta_size = E1000_MC_TBL_SIZE_ICH8LAN; | 614 | case e1000_82545_rev_3: |
952 | for (i = 0; i < mta_size; i++) { | 615 | case e1000_82546_rev_3: |
953 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); | 616 | break; |
954 | /* use write flush to prevent Memory Write Block (MWB) from | 617 | default: |
955 | * occuring when accessing our register space */ | 618 | /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ |
956 | E1000_WRITE_FLUSH(); | 619 | if (hw->bus_type == e1000_bus_type_pcix |
957 | } | 620 | && e1000_pcix_get_mmrbc(hw) > 2048) |
958 | 621 | e1000_pcix_set_mmrbc(hw, 2048); | |
959 | /* Set the PCI priority bit correctly in the CTRL register. This | 622 | break; |
960 | * determines if the adapter gives priority to receives, or if it | 623 | } |
961 | * gives equal priority to transmits and receives. Valid only on | 624 | |
962 | * 82542 and 82543 silicon. | 625 | /* Call a subroutine to configure the link and setup flow control. */ |
963 | */ | 626 | ret_val = e1000_setup_link(hw); |
964 | if (hw->dma_fairness && hw->mac_type <= e1000_82543) { | 627 | |
965 | ctrl = er32(CTRL); | 628 | /* Set the transmit descriptor write-back policy */ |
966 | ew32(CTRL, ctrl | E1000_CTRL_PRIOR); | 629 | if (hw->mac_type > e1000_82544) { |
967 | } | 630 | ctrl = er32(TXDCTL); |
968 | 631 | ctrl = | |
969 | switch (hw->mac_type) { | 632 | (ctrl & ~E1000_TXDCTL_WTHRESH) | |
970 | case e1000_82545_rev_3: | 633 | E1000_TXDCTL_FULL_TX_DESC_WB; |
971 | case e1000_82546_rev_3: | 634 | ew32(TXDCTL, ctrl); |
972 | break; | 635 | } |
973 | default: | 636 | |
974 | /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ | 637 | /* Clear all of the statistics registers (clear on read). It is |
975 | if (hw->bus_type == e1000_bus_type_pcix && e1000_pcix_get_mmrbc(hw) > 2048) | 638 | * important that we do this after we have tried to establish link |
976 | e1000_pcix_set_mmrbc(hw, 2048); | 639 | * because the symbol error count will increment wildly if there |
977 | break; | 640 | * is no link. |
978 | } | 641 | */ |
979 | 642 | e1000_clear_hw_cntrs(hw); | |
980 | /* More time needed for PHY to initialize */ | 643 | |
981 | if (hw->mac_type == e1000_ich8lan) | 644 | if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || |
982 | msleep(15); | 645 | hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { |
983 | 646 | ctrl_ext = er32(CTRL_EXT); | |
984 | /* Call a subroutine to configure the link and setup flow control. */ | 647 | /* Relaxed ordering must be disabled to avoid a parity |
985 | ret_val = e1000_setup_link(hw); | 648 | * error crash in a PCI slot. */ |
986 | 649 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; | |
987 | /* Set the transmit descriptor write-back policy */ | 650 | ew32(CTRL_EXT, ctrl_ext); |
988 | if (hw->mac_type > e1000_82544) { | 651 | } |
989 | ctrl = er32(TXDCTL); | 652 | |
990 | ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; | 653 | return ret_val; |
991 | ew32(TXDCTL, ctrl); | ||
992 | } | ||
993 | |||
994 | if (hw->mac_type == e1000_82573) { | ||
995 | e1000_enable_tx_pkt_filtering(hw); | ||
996 | } | ||
997 | |||
998 | switch (hw->mac_type) { | ||
999 | default: | ||
1000 | break; | ||
1001 | case e1000_80003es2lan: | ||
1002 | /* Enable retransmit on late collisions */ | ||
1003 | reg_data = er32(TCTL); | ||
1004 | reg_data |= E1000_TCTL_RTLC; | ||
1005 | ew32(TCTL, reg_data); | ||
1006 | |||
1007 | /* Configure Gigabit Carry Extend Padding */ | ||
1008 | reg_data = er32(TCTL_EXT); | ||
1009 | reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; | ||
1010 | reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; | ||
1011 | ew32(TCTL_EXT, reg_data); | ||
1012 | |||
1013 | /* Configure Transmit Inter-Packet Gap */ | ||
1014 | reg_data = er32(TIPG); | ||
1015 | reg_data &= ~E1000_TIPG_IPGT_MASK; | ||
1016 | reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; | ||
1017 | ew32(TIPG, reg_data); | ||
1018 | |||
1019 | reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); | ||
1020 | reg_data &= ~0x00100000; | ||
1021 | E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); | ||
1022 | /* Fall through */ | ||
1023 | case e1000_82571: | ||
1024 | case e1000_82572: | ||
1025 | case e1000_ich8lan: | ||
1026 | ctrl = er32(TXDCTL1); | ||
1027 | ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; | ||
1028 | ew32(TXDCTL1, ctrl); | ||
1029 | break; | ||
1030 | } | ||
1031 | |||
1032 | |||
1033 | if (hw->mac_type == e1000_82573) { | ||
1034 | u32 gcr = er32(GCR); | ||
1035 | gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; | ||
1036 | ew32(GCR, gcr); | ||
1037 | } | ||
1038 | |||
1039 | /* Clear all of the statistics registers (clear on read). It is | ||
1040 | * important that we do this after we have tried to establish link | ||
1041 | * because the symbol error count will increment wildly if there | ||
1042 | * is no link. | ||
1043 | */ | ||
1044 | e1000_clear_hw_cntrs(hw); | ||
1045 | |||
1046 | /* ICH8 No-snoop bits are opposite polarity. | ||
1047 | * Set to snoop by default after reset. */ | ||
1048 | if (hw->mac_type == e1000_ich8lan) | ||
1049 | e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); | ||
1050 | |||
1051 | if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || | ||
1052 | hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { | ||
1053 | ctrl_ext = er32(CTRL_EXT); | ||
1054 | /* Relaxed ordering must be disabled to avoid a parity | ||
1055 | * error crash in a PCI slot. */ | ||
1056 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; | ||
1057 | ew32(CTRL_EXT, ctrl_ext); | ||
1058 | } | ||
1059 | |||
1060 | return ret_val; | ||
1061 | } | 654 | } |
1062 | 655 | ||
1063 | /****************************************************************************** | 656 | /** |
1064 | * Adjust SERDES output amplitude based on EEPROM setting. | 657 | * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting. |
1065 | * | 658 | * @hw: Struct containing variables accessed by shared code. |
1066 | * hw - Struct containing variables accessed by shared code. | 659 | */ |
1067 | *****************************************************************************/ | ||
1068 | static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw) | 660 | static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw) |
1069 | { | 661 | { |
1070 | u16 eeprom_data; | 662 | u16 eeprom_data; |
1071 | s32 ret_val; | 663 | s32 ret_val; |
1072 | 664 | ||
1073 | DEBUGFUNC("e1000_adjust_serdes_amplitude"); | 665 | DEBUGFUNC("e1000_adjust_serdes_amplitude"); |
1074 | 666 | ||
1075 | if (hw->media_type != e1000_media_type_internal_serdes) | 667 | if (hw->media_type != e1000_media_type_internal_serdes) |
1076 | return E1000_SUCCESS; | 668 | return E1000_SUCCESS; |
1077 | 669 | ||
1078 | switch (hw->mac_type) { | 670 | switch (hw->mac_type) { |
1079 | case e1000_82545_rev_3: | 671 | case e1000_82545_rev_3: |
1080 | case e1000_82546_rev_3: | 672 | case e1000_82546_rev_3: |
1081 | break; | 673 | break; |
1082 | default: | 674 | default: |
1083 | return E1000_SUCCESS; | 675 | return E1000_SUCCESS; |
1084 | } | 676 | } |
1085 | 677 | ||
1086 | ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); | 678 | ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, |
1087 | if (ret_val) { | 679 | &eeprom_data); |
1088 | return ret_val; | 680 | if (ret_val) { |
1089 | } | 681 | return ret_val; |
1090 | 682 | } | |
1091 | if (eeprom_data != EEPROM_RESERVED_WORD) { | 683 | |
1092 | /* Adjust SERDES output amplitude only. */ | 684 | if (eeprom_data != EEPROM_RESERVED_WORD) { |
1093 | eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; | 685 | /* Adjust SERDES output amplitude only. */ |
1094 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); | 686 | eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; |
1095 | if (ret_val) | 687 | ret_val = |
1096 | return ret_val; | 688 | e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); |
1097 | } | 689 | if (ret_val) |
1098 | 690 | return ret_val; | |
1099 | return E1000_SUCCESS; | 691 | } |
692 | |||
693 | return E1000_SUCCESS; | ||
1100 | } | 694 | } |
1101 | 695 | ||
1102 | /****************************************************************************** | 696 | /** |
1103 | * Configures flow control and link settings. | 697 | * e1000_setup_link - Configures flow control and link settings. |
1104 | * | 698 | * @hw: Struct containing variables accessed by shared code |
1105 | * hw - Struct containing variables accessed by shared code | ||
1106 | * | 699 | * |
1107 | * Determines which flow control settings to use. Calls the apropriate media- | 700 | * Determines which flow control settings to use. Calls the appropriate media- |
1108 | * specific link configuration function. Configures the flow control settings. | 701 | * specific link configuration function. Configures the flow control settings. |
1109 | * Assuming the adapter has a valid link partner, a valid link should be | 702 | * Assuming the adapter has a valid link partner, a valid link should be |
1110 | * established. Assumes the hardware has previously been reset and the | 703 | * established. Assumes the hardware has previously been reset and the |
1111 | * transmitter and receiver are not enabled. | 704 | * transmitter and receiver are not enabled. |
1112 | *****************************************************************************/ | 705 | */ |
1113 | s32 e1000_setup_link(struct e1000_hw *hw) | 706 | s32 e1000_setup_link(struct e1000_hw *hw) |
1114 | { | 707 | { |
1115 | u32 ctrl_ext; | 708 | u32 ctrl_ext; |
1116 | s32 ret_val; | 709 | s32 ret_val; |
1117 | u16 eeprom_data; | 710 | u16 eeprom_data; |
1118 | 711 | ||
1119 | DEBUGFUNC("e1000_setup_link"); | 712 | DEBUGFUNC("e1000_setup_link"); |
1120 | 713 | ||
1121 | /* In the case of the phy reset being blocked, we already have a link. | 714 | /* Read and store word 0x0F of the EEPROM. This word contains bits |
1122 | * We do not have to set it up again. */ | 715 | * that determine the hardware's default PAUSE (flow control) mode, |
1123 | if (e1000_check_phy_reset_block(hw)) | 716 | * a bit that determines whether the HW defaults to enabling or |
1124 | return E1000_SUCCESS; | 717 | * disabling auto-negotiation, and the direction of the |
1125 | 718 | * SW defined pins. If there is no SW over-ride of the flow | |
1126 | /* Read and store word 0x0F of the EEPROM. This word contains bits | 719 | * control setting, then the variable hw->fc will |
1127 | * that determine the hardware's default PAUSE (flow control) mode, | 720 | * be initialized based on a value in the EEPROM. |
1128 | * a bit that determines whether the HW defaults to enabling or | 721 | */ |
1129 | * disabling auto-negotiation, and the direction of the | 722 | if (hw->fc == E1000_FC_DEFAULT) { |
1130 | * SW defined pins. If there is no SW over-ride of the flow | 723 | ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, |
1131 | * control setting, then the variable hw->fc will | 724 | 1, &eeprom_data); |
1132 | * be initialized based on a value in the EEPROM. | 725 | if (ret_val) { |
1133 | */ | 726 | DEBUGOUT("EEPROM Read Error\n"); |
1134 | if (hw->fc == E1000_FC_DEFAULT) { | 727 | return -E1000_ERR_EEPROM; |
1135 | switch (hw->mac_type) { | 728 | } |
1136 | case e1000_ich8lan: | 729 | if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) |
1137 | case e1000_82573: | 730 | hw->fc = E1000_FC_NONE; |
1138 | hw->fc = E1000_FC_FULL; | 731 | else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == |
1139 | break; | 732 | EEPROM_WORD0F_ASM_DIR) |
1140 | default: | 733 | hw->fc = E1000_FC_TX_PAUSE; |
1141 | ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, | 734 | else |
1142 | 1, &eeprom_data); | 735 | hw->fc = E1000_FC_FULL; |
1143 | if (ret_val) { | 736 | } |
1144 | DEBUGOUT("EEPROM Read Error\n"); | 737 | |
1145 | return -E1000_ERR_EEPROM; | 738 | /* We want to save off the original Flow Control configuration just |
1146 | } | 739 | * in case we get disconnected and then reconnected into a different |
1147 | if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) | 740 | * hub or switch with different Flow Control capabilities. |
1148 | hw->fc = E1000_FC_NONE; | 741 | */ |
1149 | else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == | 742 | if (hw->mac_type == e1000_82542_rev2_0) |
1150 | EEPROM_WORD0F_ASM_DIR) | 743 | hw->fc &= (~E1000_FC_TX_PAUSE); |
1151 | hw->fc = E1000_FC_TX_PAUSE; | 744 | |
1152 | else | 745 | if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) |
1153 | hw->fc = E1000_FC_FULL; | 746 | hw->fc &= (~E1000_FC_RX_PAUSE); |
1154 | break; | 747 | |
1155 | } | 748 | hw->original_fc = hw->fc; |
1156 | } | 749 | |
1157 | 750 | DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); | |
1158 | /* We want to save off the original Flow Control configuration just | 751 | |
1159 | * in case we get disconnected and then reconnected into a different | 752 | /* Take the 4 bits from EEPROM word 0x0F that determine the initial |
1160 | * hub or switch with different Flow Control capabilities. | 753 | * polarity value for the SW controlled pins, and setup the |
1161 | */ | 754 | * Extended Device Control reg with that info. |
1162 | if (hw->mac_type == e1000_82542_rev2_0) | 755 | * This is needed because one of the SW controlled pins is used for |
1163 | hw->fc &= (~E1000_FC_TX_PAUSE); | 756 | * signal detection. So this should be done before e1000_setup_pcs_link() |
1164 | 757 | * or e1000_phy_setup() is called. | |
1165 | if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) | 758 | */ |
1166 | hw->fc &= (~E1000_FC_RX_PAUSE); | 759 | if (hw->mac_type == e1000_82543) { |
1167 | 760 | ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, | |
1168 | hw->original_fc = hw->fc; | 761 | 1, &eeprom_data); |
1169 | 762 | if (ret_val) { | |
1170 | DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); | 763 | DEBUGOUT("EEPROM Read Error\n"); |
1171 | 764 | return -E1000_ERR_EEPROM; | |
1172 | /* Take the 4 bits from EEPROM word 0x0F that determine the initial | 765 | } |
1173 | * polarity value for the SW controlled pins, and setup the | 766 | ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << |
1174 | * Extended Device Control reg with that info. | 767 | SWDPIO__EXT_SHIFT); |
1175 | * This is needed because one of the SW controlled pins is used for | 768 | ew32(CTRL_EXT, ctrl_ext); |
1176 | * signal detection. So this should be done before e1000_setup_pcs_link() | 769 | } |
1177 | * or e1000_phy_setup() is called. | 770 | |
1178 | */ | 771 | /* Call the necessary subroutine to configure the link. */ |
1179 | if (hw->mac_type == e1000_82543) { | 772 | ret_val = (hw->media_type == e1000_media_type_copper) ? |
1180 | ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, | 773 | e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw); |
1181 | 1, &eeprom_data); | 774 | |
1182 | if (ret_val) { | 775 | /* Initialize the flow control address, type, and PAUSE timer |
1183 | DEBUGOUT("EEPROM Read Error\n"); | 776 | * registers to their default values. This is done even if flow |
1184 | return -E1000_ERR_EEPROM; | 777 | * control is disabled, because it does not hurt anything to |
1185 | } | 778 | * initialize these registers. |
1186 | ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << | 779 | */ |
1187 | SWDPIO__EXT_SHIFT); | 780 | DEBUGOUT |
1188 | ew32(CTRL_EXT, ctrl_ext); | 781 | ("Initializing the Flow Control address, type and timer regs\n"); |
1189 | } | 782 | |
1190 | 783 | ew32(FCT, FLOW_CONTROL_TYPE); | |
1191 | /* Call the necessary subroutine to configure the link. */ | 784 | ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); |
1192 | ret_val = (hw->media_type == e1000_media_type_copper) ? | 785 | ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); |
1193 | e1000_setup_copper_link(hw) : | 786 | |
1194 | e1000_setup_fiber_serdes_link(hw); | 787 | ew32(FCTTV, hw->fc_pause_time); |
1195 | 788 | ||
1196 | /* Initialize the flow control address, type, and PAUSE timer | 789 | /* Set the flow control receive threshold registers. Normally, |
1197 | * registers to their default values. This is done even if flow | 790 | * these registers will be set to a default threshold that may be |
1198 | * control is disabled, because it does not hurt anything to | 791 | * adjusted later by the driver's runtime code. However, if the |
1199 | * initialize these registers. | 792 | * ability to transmit pause frames in not enabled, then these |
1200 | */ | 793 | * registers will be set to 0. |
1201 | DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); | 794 | */ |
1202 | 795 | if (!(hw->fc & E1000_FC_TX_PAUSE)) { | |
1203 | /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ | 796 | ew32(FCRTL, 0); |
1204 | if (hw->mac_type != e1000_ich8lan) { | 797 | ew32(FCRTH, 0); |
1205 | ew32(FCT, FLOW_CONTROL_TYPE); | 798 | } else { |
1206 | ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); | 799 | /* We need to set up the Receive Threshold high and low water marks |
1207 | ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); | 800 | * as well as (optionally) enabling the transmission of XON frames. |
1208 | } | 801 | */ |
1209 | 802 | if (hw->fc_send_xon) { | |
1210 | ew32(FCTTV, hw->fc_pause_time); | 803 | ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); |
1211 | 804 | ew32(FCRTH, hw->fc_high_water); | |
1212 | /* Set the flow control receive threshold registers. Normally, | 805 | } else { |
1213 | * these registers will be set to a default threshold that may be | 806 | ew32(FCRTL, hw->fc_low_water); |
1214 | * adjusted later by the driver's runtime code. However, if the | 807 | ew32(FCRTH, hw->fc_high_water); |
1215 | * ability to transmit pause frames in not enabled, then these | 808 | } |
1216 | * registers will be set to 0. | 809 | } |
1217 | */ | 810 | return ret_val; |
1218 | if (!(hw->fc & E1000_FC_TX_PAUSE)) { | ||
1219 | ew32(FCRTL, 0); | ||
1220 | ew32(FCRTH, 0); | ||
1221 | } else { | ||
1222 | /* We need to set up the Receive Threshold high and low water marks | ||
1223 | * as well as (optionally) enabling the transmission of XON frames. | ||
1224 | */ | ||
1225 | if (hw->fc_send_xon) { | ||
1226 | ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); | ||
1227 | ew32(FCRTH, hw->fc_high_water); | ||
1228 | } else { | ||
1229 | ew32(FCRTL, hw->fc_low_water); | ||
1230 | ew32(FCRTH, hw->fc_high_water); | ||
1231 | } | ||
1232 | } | ||
1233 | return ret_val; | ||
1234 | } | 811 | } |
1235 | 812 | ||
1236 | /****************************************************************************** | 813 | /** |
1237 | * Sets up link for a fiber based or serdes based adapter | 814 | * e1000_setup_fiber_serdes_link - prepare fiber or serdes link |
1238 | * | 815 | * @hw: Struct containing variables accessed by shared code |
1239 | * hw - Struct containing variables accessed by shared code | ||
1240 | * | 816 | * |
1241 | * Manipulates Physical Coding Sublayer functions in order to configure | 817 | * Manipulates Physical Coding Sublayer functions in order to configure |
1242 | * link. Assumes the hardware has been previously reset and the transmitter | 818 | * link. Assumes the hardware has been previously reset and the transmitter |
1243 | * and receiver are not enabled. | 819 | * and receiver are not enabled. |
1244 | *****************************************************************************/ | 820 | */ |
1245 | static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) | 821 | static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) |
1246 | { | 822 | { |
1247 | u32 ctrl; | 823 | u32 ctrl; |
1248 | u32 status; | 824 | u32 status; |
1249 | u32 txcw = 0; | 825 | u32 txcw = 0; |
1250 | u32 i; | 826 | u32 i; |
1251 | u32 signal = 0; | 827 | u32 signal = 0; |
1252 | s32 ret_val; | 828 | s32 ret_val; |
1253 | 829 | ||
1254 | DEBUGFUNC("e1000_setup_fiber_serdes_link"); | 830 | DEBUGFUNC("e1000_setup_fiber_serdes_link"); |
1255 | 831 | ||
1256 | /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists | 832 | /* On adapters with a MAC newer than 82544, SWDP 1 will be |
1257 | * until explicitly turned off or a power cycle is performed. A read to | 833 | * set when the optics detect a signal. On older adapters, it will be |
1258 | * the register does not indicate its status. Therefore, we ensure | 834 | * cleared when there is a signal. This applies to fiber media only. |
1259 | * loopback mode is disabled during initialization. | 835 | * If we're on serdes media, adjust the output amplitude to value |
1260 | */ | 836 | * set in the EEPROM. |
1261 | if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) | 837 | */ |
1262 | ew32(SCTL, E1000_DISABLE_SERDES_LOOPBACK); | 838 | ctrl = er32(CTRL); |
1263 | 839 | if (hw->media_type == e1000_media_type_fiber) | |
1264 | /* On adapters with a MAC newer than 82544, SWDP 1 will be | 840 | signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; |
1265 | * set when the optics detect a signal. On older adapters, it will be | 841 | |
1266 | * cleared when there is a signal. This applies to fiber media only. | 842 | ret_val = e1000_adjust_serdes_amplitude(hw); |
1267 | * If we're on serdes media, adjust the output amplitude to value | 843 | if (ret_val) |
1268 | * set in the EEPROM. | 844 | return ret_val; |
1269 | */ | 845 | |
1270 | ctrl = er32(CTRL); | 846 | /* Take the link out of reset */ |
1271 | if (hw->media_type == e1000_media_type_fiber) | 847 | ctrl &= ~(E1000_CTRL_LRST); |
1272 | signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; | 848 | |
1273 | 849 | /* Adjust VCO speed to improve BER performance */ | |
1274 | ret_val = e1000_adjust_serdes_amplitude(hw); | 850 | ret_val = e1000_set_vco_speed(hw); |
1275 | if (ret_val) | 851 | if (ret_val) |
1276 | return ret_val; | 852 | return ret_val; |
1277 | 853 | ||
1278 | /* Take the link out of reset */ | 854 | e1000_config_collision_dist(hw); |
1279 | ctrl &= ~(E1000_CTRL_LRST); | 855 | |
1280 | 856 | /* Check for a software override of the flow control settings, and setup | |
1281 | /* Adjust VCO speed to improve BER performance */ | 857 | * the device accordingly. If auto-negotiation is enabled, then software |
1282 | ret_val = e1000_set_vco_speed(hw); | 858 | * will have to set the "PAUSE" bits to the correct value in the Tranmsit |
1283 | if (ret_val) | 859 | * Config Word Register (TXCW) and re-start auto-negotiation. However, if |
1284 | return ret_val; | 860 | * auto-negotiation is disabled, then software will have to manually |
1285 | 861 | * configure the two flow control enable bits in the CTRL register. | |
1286 | e1000_config_collision_dist(hw); | 862 | * |
1287 | 863 | * The possible values of the "fc" parameter are: | |
1288 | /* Check for a software override of the flow control settings, and setup | 864 | * 0: Flow control is completely disabled |
1289 | * the device accordingly. If auto-negotiation is enabled, then software | 865 | * 1: Rx flow control is enabled (we can receive pause frames, but |
1290 | * will have to set the "PAUSE" bits to the correct value in the Tranmsit | 866 | * not send pause frames). |
1291 | * Config Word Register (TXCW) and re-start auto-negotiation. However, if | 867 | * 2: Tx flow control is enabled (we can send pause frames but we do |
1292 | * auto-negotiation is disabled, then software will have to manually | 868 | * not support receiving pause frames). |
1293 | * configure the two flow control enable bits in the CTRL register. | 869 | * 3: Both Rx and TX flow control (symmetric) are enabled. |
1294 | * | 870 | */ |
1295 | * The possible values of the "fc" parameter are: | 871 | switch (hw->fc) { |
1296 | * 0: Flow control is completely disabled | 872 | case E1000_FC_NONE: |
1297 | * 1: Rx flow control is enabled (we can receive pause frames, but | 873 | /* Flow control is completely disabled by a software over-ride. */ |
1298 | * not send pause frames). | 874 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); |
1299 | * 2: Tx flow control is enabled (we can send pause frames but we do | 875 | break; |
1300 | * not support receiving pause frames). | 876 | case E1000_FC_RX_PAUSE: |
1301 | * 3: Both Rx and TX flow control (symmetric) are enabled. | 877 | /* RX Flow control is enabled and TX Flow control is disabled by a |
1302 | */ | 878 | * software over-ride. Since there really isn't a way to advertise |
1303 | switch (hw->fc) { | 879 | * that we are capable of RX Pause ONLY, we will advertise that we |
1304 | case E1000_FC_NONE: | 880 | * support both symmetric and asymmetric RX PAUSE. Later, we will |
1305 | /* Flow control is completely disabled by a software over-ride. */ | 881 | * disable the adapter's ability to send PAUSE frames. |
1306 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); | 882 | */ |
1307 | break; | 883 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
1308 | case E1000_FC_RX_PAUSE: | 884 | break; |
1309 | /* RX Flow control is enabled and TX Flow control is disabled by a | 885 | case E1000_FC_TX_PAUSE: |
1310 | * software over-ride. Since there really isn't a way to advertise | 886 | /* TX Flow control is enabled, and RX Flow control is disabled, by a |
1311 | * that we are capable of RX Pause ONLY, we will advertise that we | 887 | * software over-ride. |
1312 | * support both symmetric and asymmetric RX PAUSE. Later, we will | 888 | */ |
1313 | * disable the adapter's ability to send PAUSE frames. | 889 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); |
1314 | */ | 890 | break; |
1315 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); | 891 | case E1000_FC_FULL: |
1316 | break; | 892 | /* Flow control (both RX and TX) is enabled by a software over-ride. */ |
1317 | case E1000_FC_TX_PAUSE: | 893 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
1318 | /* TX Flow control is enabled, and RX Flow control is disabled, by a | 894 | break; |
1319 | * software over-ride. | 895 | default: |
1320 | */ | 896 | DEBUGOUT("Flow control param set incorrectly\n"); |
1321 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); | 897 | return -E1000_ERR_CONFIG; |
1322 | break; | 898 | break; |
1323 | case E1000_FC_FULL: | 899 | } |
1324 | /* Flow control (both RX and TX) is enabled by a software over-ride. */ | 900 | |
1325 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); | 901 | /* Since auto-negotiation is enabled, take the link out of reset (the link |
1326 | break; | 902 | * will be in reset, because we previously reset the chip). This will |
1327 | default: | 903 | * restart auto-negotiation. If auto-negotiation is successful then the |
1328 | DEBUGOUT("Flow control param set incorrectly\n"); | 904 | * link-up status bit will be set and the flow control enable bits (RFCE |
1329 | return -E1000_ERR_CONFIG; | 905 | * and TFCE) will be set according to their negotiated value. |
1330 | break; | 906 | */ |
1331 | } | 907 | DEBUGOUT("Auto-negotiation enabled\n"); |
1332 | 908 | ||
1333 | /* Since auto-negotiation is enabled, take the link out of reset (the link | 909 | ew32(TXCW, txcw); |
1334 | * will be in reset, because we previously reset the chip). This will | 910 | ew32(CTRL, ctrl); |
1335 | * restart auto-negotiation. If auto-neogtiation is successful then the | 911 | E1000_WRITE_FLUSH(); |
1336 | * link-up status bit will be set and the flow control enable bits (RFCE | 912 | |
1337 | * and TFCE) will be set according to their negotiated value. | 913 | hw->txcw = txcw; |
1338 | */ | 914 | msleep(1); |
1339 | DEBUGOUT("Auto-negotiation enabled\n"); | 915 | |
1340 | 916 | /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" | |
1341 | ew32(TXCW, txcw); | 917 | * indication in the Device Status Register. Time-out if a link isn't |
1342 | ew32(CTRL, ctrl); | 918 | * seen in 500 milliseconds seconds (Auto-negotiation should complete in |
1343 | E1000_WRITE_FLUSH(); | 919 | * less than 500 milliseconds even if the other end is doing it in SW). |
1344 | 920 | * For internal serdes, we just assume a signal is present, then poll. | |
1345 | hw->txcw = txcw; | 921 | */ |
1346 | msleep(1); | 922 | if (hw->media_type == e1000_media_type_internal_serdes || |
1347 | 923 | (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) { | |
1348 | /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" | 924 | DEBUGOUT("Looking for Link\n"); |
1349 | * indication in the Device Status Register. Time-out if a link isn't | 925 | for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { |
1350 | * seen in 500 milliseconds seconds (Auto-negotiation should complete in | 926 | msleep(10); |
1351 | * less than 500 milliseconds even if the other end is doing it in SW). | 927 | status = er32(STATUS); |
1352 | * For internal serdes, we just assume a signal is present, then poll. | 928 | if (status & E1000_STATUS_LU) |
1353 | */ | 929 | break; |
1354 | if (hw->media_type == e1000_media_type_internal_serdes || | 930 | } |
1355 | (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) { | 931 | if (i == (LINK_UP_TIMEOUT / 10)) { |
1356 | DEBUGOUT("Looking for Link\n"); | 932 | DEBUGOUT("Never got a valid link from auto-neg!!!\n"); |
1357 | for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { | 933 | hw->autoneg_failed = 1; |
1358 | msleep(10); | 934 | /* AutoNeg failed to achieve a link, so we'll call |
1359 | status = er32(STATUS); | 935 | * e1000_check_for_link. This routine will force the link up if |
1360 | if (status & E1000_STATUS_LU) break; | 936 | * we detect a signal. This will allow us to communicate with |
1361 | } | 937 | * non-autonegotiating link partners. |
1362 | if (i == (LINK_UP_TIMEOUT / 10)) { | 938 | */ |
1363 | DEBUGOUT("Never got a valid link from auto-neg!!!\n"); | 939 | ret_val = e1000_check_for_link(hw); |
1364 | hw->autoneg_failed = 1; | 940 | if (ret_val) { |
1365 | /* AutoNeg failed to achieve a link, so we'll call | 941 | DEBUGOUT("Error while checking for link\n"); |
1366 | * e1000_check_for_link. This routine will force the link up if | 942 | return ret_val; |
1367 | * we detect a signal. This will allow us to communicate with | 943 | } |
1368 | * non-autonegotiating link partners. | 944 | hw->autoneg_failed = 0; |
1369 | */ | 945 | } else { |
1370 | ret_val = e1000_check_for_link(hw); | 946 | hw->autoneg_failed = 0; |
1371 | if (ret_val) { | 947 | DEBUGOUT("Valid Link Found\n"); |
1372 | DEBUGOUT("Error while checking for link\n"); | 948 | } |
1373 | return ret_val; | 949 | } else { |
1374 | } | 950 | DEBUGOUT("No Signal Detected\n"); |
1375 | hw->autoneg_failed = 0; | 951 | } |
1376 | } else { | 952 | return E1000_SUCCESS; |
1377 | hw->autoneg_failed = 0; | ||
1378 | DEBUGOUT("Valid Link Found\n"); | ||
1379 | } | ||
1380 | } else { | ||
1381 | DEBUGOUT("No Signal Detected\n"); | ||
1382 | } | ||
1383 | return E1000_SUCCESS; | ||
1384 | } | 953 | } |
1385 | 954 | ||
1386 | /****************************************************************************** | 955 | /** |
1387 | * Make sure we have a valid PHY and change PHY mode before link setup. | 956 | * e1000_copper_link_preconfig - early configuration for copper |
1388 | * | 957 | * @hw: Struct containing variables accessed by shared code |
1389 | * hw - Struct containing variables accessed by shared code | 958 | * |
1390 | ******************************************************************************/ | 959 | * Make sure we have a valid PHY and change PHY mode before link setup. |
960 | */ | ||
1391 | static s32 e1000_copper_link_preconfig(struct e1000_hw *hw) | 961 | static s32 e1000_copper_link_preconfig(struct e1000_hw *hw) |
1392 | { | 962 | { |
1393 | u32 ctrl; | 963 | u32 ctrl; |
1394 | s32 ret_val; | 964 | s32 ret_val; |
1395 | u16 phy_data; | 965 | u16 phy_data; |
1396 | |||
1397 | DEBUGFUNC("e1000_copper_link_preconfig"); | ||
1398 | |||
1399 | ctrl = er32(CTRL); | ||
1400 | /* With 82543, we need to force speed and duplex on the MAC equal to what | ||
1401 | * the PHY speed and duplex configuration is. In addition, we need to | ||
1402 | * perform a hardware reset on the PHY to take it out of reset. | ||
1403 | */ | ||
1404 | if (hw->mac_type > e1000_82543) { | ||
1405 | ctrl |= E1000_CTRL_SLU; | ||
1406 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | ||
1407 | ew32(CTRL, ctrl); | ||
1408 | } else { | ||
1409 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); | ||
1410 | ew32(CTRL, ctrl); | ||
1411 | ret_val = e1000_phy_hw_reset(hw); | ||
1412 | if (ret_val) | ||
1413 | return ret_val; | ||
1414 | } | ||
1415 | |||
1416 | /* Make sure we have a valid PHY */ | ||
1417 | ret_val = e1000_detect_gig_phy(hw); | ||
1418 | if (ret_val) { | ||
1419 | DEBUGOUT("Error, did not detect valid phy.\n"); | ||
1420 | return ret_val; | ||
1421 | } | ||
1422 | DEBUGOUT1("Phy ID = %x \n", hw->phy_id); | ||
1423 | |||
1424 | /* Set PHY to class A mode (if necessary) */ | ||
1425 | ret_val = e1000_set_phy_mode(hw); | ||
1426 | if (ret_val) | ||
1427 | return ret_val; | ||
1428 | |||
1429 | if ((hw->mac_type == e1000_82545_rev_3) || | ||
1430 | (hw->mac_type == e1000_82546_rev_3)) { | ||
1431 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | ||
1432 | phy_data |= 0x00000008; | ||
1433 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | ||
1434 | } | ||
1435 | |||
1436 | if (hw->mac_type <= e1000_82543 || | ||
1437 | hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || | ||
1438 | hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) | ||
1439 | hw->phy_reset_disable = false; | ||
1440 | |||
1441 | return E1000_SUCCESS; | ||
1442 | } | ||
1443 | 966 | ||
967 | DEBUGFUNC("e1000_copper_link_preconfig"); | ||
1444 | 968 | ||
1445 | /******************************************************************** | 969 | ctrl = er32(CTRL); |
1446 | * Copper link setup for e1000_phy_igp series. | 970 | /* With 82543, we need to force speed and duplex on the MAC equal to what |
1447 | * | 971 | * the PHY speed and duplex configuration is. In addition, we need to |
1448 | * hw - Struct containing variables accessed by shared code | 972 | * perform a hardware reset on the PHY to take it out of reset. |
1449 | *********************************************************************/ | 973 | */ |
1450 | static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw) | 974 | if (hw->mac_type > e1000_82543) { |
1451 | { | 975 | ctrl |= E1000_CTRL_SLU; |
1452 | u32 led_ctrl; | 976 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
1453 | s32 ret_val; | 977 | ew32(CTRL, ctrl); |
1454 | u16 phy_data; | 978 | } else { |
1455 | 979 | ctrl |= | |
1456 | DEBUGFUNC("e1000_copper_link_igp_setup"); | 980 | (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); |
1457 | 981 | ew32(CTRL, ctrl); | |
1458 | if (hw->phy_reset_disable) | 982 | ret_val = e1000_phy_hw_reset(hw); |
1459 | return E1000_SUCCESS; | 983 | if (ret_val) |
1460 | 984 | return ret_val; | |
1461 | ret_val = e1000_phy_reset(hw); | 985 | } |
1462 | if (ret_val) { | 986 | |
1463 | DEBUGOUT("Error Resetting the PHY\n"); | 987 | /* Make sure we have a valid PHY */ |
1464 | return ret_val; | 988 | ret_val = e1000_detect_gig_phy(hw); |
1465 | } | 989 | if (ret_val) { |
1466 | 990 | DEBUGOUT("Error, did not detect valid phy.\n"); | |
1467 | /* Wait 15ms for MAC to configure PHY from eeprom settings */ | 991 | return ret_val; |
1468 | msleep(15); | 992 | } |
1469 | if (hw->mac_type != e1000_ich8lan) { | 993 | DEBUGOUT1("Phy ID = %x \n", hw->phy_id); |
1470 | /* Configure activity LED after PHY reset */ | 994 | |
1471 | led_ctrl = er32(LEDCTL); | 995 | /* Set PHY to class A mode (if necessary) */ |
1472 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | 996 | ret_val = e1000_set_phy_mode(hw); |
1473 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | 997 | if (ret_val) |
1474 | ew32(LEDCTL, led_ctrl); | 998 | return ret_val; |
1475 | } | 999 | |
1476 | 1000 | if ((hw->mac_type == e1000_82545_rev_3) || | |
1477 | /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ | 1001 | (hw->mac_type == e1000_82546_rev_3)) { |
1478 | if (hw->phy_type == e1000_phy_igp) { | 1002 | ret_val = |
1479 | /* disable lplu d3 during driver init */ | 1003 | e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
1480 | ret_val = e1000_set_d3_lplu_state(hw, false); | 1004 | phy_data |= 0x00000008; |
1481 | if (ret_val) { | 1005 | ret_val = |
1482 | DEBUGOUT("Error Disabling LPLU D3\n"); | 1006 | e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
1483 | return ret_val; | 1007 | } |
1484 | } | 1008 | |
1485 | } | 1009 | if (hw->mac_type <= e1000_82543 || |
1486 | 1010 | hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || | |
1487 | /* disable lplu d0 during driver init */ | 1011 | hw->mac_type == e1000_82541_rev_2 |
1488 | ret_val = e1000_set_d0_lplu_state(hw, false); | 1012 | || hw->mac_type == e1000_82547_rev_2) |
1489 | if (ret_val) { | 1013 | hw->phy_reset_disable = false; |
1490 | DEBUGOUT("Error Disabling LPLU D0\n"); | 1014 | |
1491 | return ret_val; | 1015 | return E1000_SUCCESS; |
1492 | } | ||
1493 | /* Configure mdi-mdix settings */ | ||
1494 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); | ||
1495 | if (ret_val) | ||
1496 | return ret_val; | ||
1497 | |||
1498 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { | ||
1499 | hw->dsp_config_state = e1000_dsp_config_disabled; | ||
1500 | /* Force MDI for earlier revs of the IGP PHY */ | ||
1501 | phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX); | ||
1502 | hw->mdix = 1; | ||
1503 | |||
1504 | } else { | ||
1505 | hw->dsp_config_state = e1000_dsp_config_enabled; | ||
1506 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | ||
1507 | |||
1508 | switch (hw->mdix) { | ||
1509 | case 1: | ||
1510 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | ||
1511 | break; | ||
1512 | case 2: | ||
1513 | phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; | ||
1514 | break; | ||
1515 | case 0: | ||
1516 | default: | ||
1517 | phy_data |= IGP01E1000_PSCR_AUTO_MDIX; | ||
1518 | break; | ||
1519 | } | ||
1520 | } | ||
1521 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); | ||
1522 | if (ret_val) | ||
1523 | return ret_val; | ||
1524 | |||
1525 | /* set auto-master slave resolution settings */ | ||
1526 | if (hw->autoneg) { | ||
1527 | e1000_ms_type phy_ms_setting = hw->master_slave; | ||
1528 | |||
1529 | if (hw->ffe_config_state == e1000_ffe_config_active) | ||
1530 | hw->ffe_config_state = e1000_ffe_config_enabled; | ||
1531 | |||
1532 | if (hw->dsp_config_state == e1000_dsp_config_activated) | ||
1533 | hw->dsp_config_state = e1000_dsp_config_enabled; | ||
1534 | |||
1535 | /* when autonegotiation advertisment is only 1000Mbps then we | ||
1536 | * should disable SmartSpeed and enable Auto MasterSlave | ||
1537 | * resolution as hardware default. */ | ||
1538 | if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { | ||
1539 | /* Disable SmartSpeed */ | ||
1540 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | ||
1541 | &phy_data); | ||
1542 | if (ret_val) | ||
1543 | return ret_val; | ||
1544 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | ||
1545 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | ||
1546 | phy_data); | ||
1547 | if (ret_val) | ||
1548 | return ret_val; | ||
1549 | /* Set auto Master/Slave resolution process */ | ||
1550 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); | ||
1551 | if (ret_val) | ||
1552 | return ret_val; | ||
1553 | phy_data &= ~CR_1000T_MS_ENABLE; | ||
1554 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); | ||
1555 | if (ret_val) | ||
1556 | return ret_val; | ||
1557 | } | ||
1558 | |||
1559 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); | ||
1560 | if (ret_val) | ||
1561 | return ret_val; | ||
1562 | |||
1563 | /* load defaults for future use */ | ||
1564 | hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? | ||
1565 | ((phy_data & CR_1000T_MS_VALUE) ? | ||
1566 | e1000_ms_force_master : | ||
1567 | e1000_ms_force_slave) : | ||
1568 | e1000_ms_auto; | ||
1569 | |||
1570 | switch (phy_ms_setting) { | ||
1571 | case e1000_ms_force_master: | ||
1572 | phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); | ||
1573 | break; | ||
1574 | case e1000_ms_force_slave: | ||
1575 | phy_data |= CR_1000T_MS_ENABLE; | ||
1576 | phy_data &= ~(CR_1000T_MS_VALUE); | ||
1577 | break; | ||
1578 | case e1000_ms_auto: | ||
1579 | phy_data &= ~CR_1000T_MS_ENABLE; | ||
1580 | default: | ||
1581 | break; | ||
1582 | } | ||
1583 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); | ||
1584 | if (ret_val) | ||
1585 | return ret_val; | ||
1586 | } | ||
1587 | |||
1588 | return E1000_SUCCESS; | ||
1589 | } | 1016 | } |
1590 | 1017 | ||
1591 | /******************************************************************** | 1018 | /** |
1592 | * Copper link setup for e1000_phy_gg82563 series. | 1019 | * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series. |
1593 | * | 1020 | * @hw: Struct containing variables accessed by shared code |
1594 | * hw - Struct containing variables accessed by shared code | 1021 | */ |
1595 | *********************************************************************/ | 1022 | static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw) |
1596 | static s32 e1000_copper_link_ggp_setup(struct e1000_hw *hw) | ||
1597 | { | 1023 | { |
1598 | s32 ret_val; | 1024 | u32 led_ctrl; |
1599 | u16 phy_data; | 1025 | s32 ret_val; |
1600 | u32 reg_data; | 1026 | u16 phy_data; |
1601 | 1027 | ||
1602 | DEBUGFUNC("e1000_copper_link_ggp_setup"); | 1028 | DEBUGFUNC("e1000_copper_link_igp_setup"); |
1603 | 1029 | ||
1604 | if (!hw->phy_reset_disable) { | 1030 | if (hw->phy_reset_disable) |
1605 | 1031 | return E1000_SUCCESS; | |
1606 | /* Enable CRS on TX for half-duplex operation. */ | 1032 | |
1607 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, | 1033 | ret_val = e1000_phy_reset(hw); |
1608 | &phy_data); | 1034 | if (ret_val) { |
1609 | if (ret_val) | 1035 | DEBUGOUT("Error Resetting the PHY\n"); |
1610 | return ret_val; | 1036 | return ret_val; |
1611 | 1037 | } | |
1612 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | 1038 | |
1613 | /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ | 1039 | /* Wait 15ms for MAC to configure PHY from eeprom settings */ |
1614 | phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; | 1040 | msleep(15); |
1615 | 1041 | /* Configure activity LED after PHY reset */ | |
1616 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, | 1042 | led_ctrl = er32(LEDCTL); |
1617 | phy_data); | 1043 | led_ctrl &= IGP_ACTIVITY_LED_MASK; |
1618 | if (ret_val) | 1044 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
1619 | return ret_val; | 1045 | ew32(LEDCTL, led_ctrl); |
1620 | 1046 | ||
1621 | /* Options: | 1047 | /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ |
1622 | * MDI/MDI-X = 0 (default) | 1048 | if (hw->phy_type == e1000_phy_igp) { |
1623 | * 0 - Auto for all speeds | 1049 | /* disable lplu d3 during driver init */ |
1624 | * 1 - MDI mode | 1050 | ret_val = e1000_set_d3_lplu_state(hw, false); |
1625 | * 2 - MDI-X mode | 1051 | if (ret_val) { |
1626 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | 1052 | DEBUGOUT("Error Disabling LPLU D3\n"); |
1627 | */ | 1053 | return ret_val; |
1628 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data); | 1054 | } |
1629 | if (ret_val) | 1055 | } |
1630 | return ret_val; | 1056 | |
1631 | 1057 | /* Configure mdi-mdix settings */ | |
1632 | phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; | 1058 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
1633 | 1059 | if (ret_val) | |
1634 | switch (hw->mdix) { | 1060 | return ret_val; |
1635 | case 1: | 1061 | |
1636 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; | 1062 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
1637 | break; | 1063 | hw->dsp_config_state = e1000_dsp_config_disabled; |
1638 | case 2: | 1064 | /* Force MDI for earlier revs of the IGP PHY */ |
1639 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; | 1065 | phy_data &= |
1640 | break; | 1066 | ~(IGP01E1000_PSCR_AUTO_MDIX | |
1641 | case 0: | 1067 | IGP01E1000_PSCR_FORCE_MDI_MDIX); |
1642 | default: | 1068 | hw->mdix = 1; |
1643 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; | 1069 | |
1644 | break; | 1070 | } else { |
1645 | } | 1071 | hw->dsp_config_state = e1000_dsp_config_enabled; |
1646 | 1072 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
1647 | /* Options: | 1073 | |
1648 | * disable_polarity_correction = 0 (default) | 1074 | switch (hw->mdix) { |
1649 | * Automatic Correction for Reversed Cable Polarity | 1075 | case 1: |
1650 | * 0 - Disabled | 1076 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
1651 | * 1 - Enabled | 1077 | break; |
1652 | */ | 1078 | case 2: |
1653 | phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; | 1079 | phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; |
1654 | if (hw->disable_polarity_correction == 1) | 1080 | break; |
1655 | phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; | 1081 | case 0: |
1656 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); | 1082 | default: |
1657 | 1083 | phy_data |= IGP01E1000_PSCR_AUTO_MDIX; | |
1658 | if (ret_val) | 1084 | break; |
1659 | return ret_val; | 1085 | } |
1660 | 1086 | } | |
1661 | /* SW Reset the PHY so all changes take effect */ | 1087 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
1662 | ret_val = e1000_phy_reset(hw); | 1088 | if (ret_val) |
1663 | if (ret_val) { | 1089 | return ret_val; |
1664 | DEBUGOUT("Error Resetting the PHY\n"); | 1090 | |
1665 | return ret_val; | 1091 | /* set auto-master slave resolution settings */ |
1666 | } | 1092 | if (hw->autoneg) { |
1667 | } /* phy_reset_disable */ | 1093 | e1000_ms_type phy_ms_setting = hw->master_slave; |
1668 | 1094 | ||
1669 | if (hw->mac_type == e1000_80003es2lan) { | 1095 | if (hw->ffe_config_state == e1000_ffe_config_active) |
1670 | /* Bypass RX and TX FIFO's */ | 1096 | hw->ffe_config_state = e1000_ffe_config_enabled; |
1671 | ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, | 1097 | |
1672 | E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | | 1098 | if (hw->dsp_config_state == e1000_dsp_config_activated) |
1673 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); | 1099 | hw->dsp_config_state = e1000_dsp_config_enabled; |
1674 | if (ret_val) | 1100 | |
1675 | return ret_val; | 1101 | /* when autonegotiation advertisement is only 1000Mbps then we |
1676 | 1102 | * should disable SmartSpeed and enable Auto MasterSlave | |
1677 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data); | 1103 | * resolution as hardware default. */ |
1678 | if (ret_val) | 1104 | if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { |
1679 | return ret_val; | 1105 | /* Disable SmartSpeed */ |
1680 | 1106 | ret_val = | |
1681 | phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; | 1107 | e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
1682 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data); | 1108 | &phy_data); |
1683 | 1109 | if (ret_val) | |
1684 | if (ret_val) | 1110 | return ret_val; |
1685 | return ret_val; | 1111 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
1686 | 1112 | ret_val = | |
1687 | reg_data = er32(CTRL_EXT); | 1113 | e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
1688 | reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); | 1114 | phy_data); |
1689 | ew32(CTRL_EXT, reg_data); | 1115 | if (ret_val) |
1690 | 1116 | return ret_val; | |
1691 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, | 1117 | /* Set auto Master/Slave resolution process */ |
1692 | &phy_data); | 1118 | ret_val = |
1693 | if (ret_val) | 1119 | e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
1694 | return ret_val; | 1120 | if (ret_val) |
1695 | 1121 | return ret_val; | |
1696 | /* Do not init these registers when the HW is in IAMT mode, since the | 1122 | phy_data &= ~CR_1000T_MS_ENABLE; |
1697 | * firmware will have already initialized them. We only initialize | 1123 | ret_val = |
1698 | * them if the HW is not in IAMT mode. | 1124 | e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); |
1699 | */ | 1125 | if (ret_val) |
1700 | if (!e1000_check_mng_mode(hw)) { | 1126 | return ret_val; |
1701 | /* Enable Electrical Idle on the PHY */ | 1127 | } |
1702 | phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; | 1128 | |
1703 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, | 1129 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
1704 | phy_data); | 1130 | if (ret_val) |
1705 | if (ret_val) | 1131 | return ret_val; |
1706 | return ret_val; | 1132 | |
1707 | 1133 | /* load defaults for future use */ | |
1708 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, | 1134 | hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? |
1709 | &phy_data); | 1135 | ((phy_data & CR_1000T_MS_VALUE) ? |
1710 | if (ret_val) | 1136 | e1000_ms_force_master : |
1711 | return ret_val; | 1137 | e1000_ms_force_slave) : e1000_ms_auto; |
1712 | 1138 | ||
1713 | phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | 1139 | switch (phy_ms_setting) { |
1714 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, | 1140 | case e1000_ms_force_master: |
1715 | phy_data); | 1141 | phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); |
1716 | 1142 | break; | |
1717 | if (ret_val) | 1143 | case e1000_ms_force_slave: |
1718 | return ret_val; | 1144 | phy_data |= CR_1000T_MS_ENABLE; |
1719 | } | 1145 | phy_data &= ~(CR_1000T_MS_VALUE); |
1720 | 1146 | break; | |
1721 | /* Workaround: Disable padding in Kumeran interface in the MAC | 1147 | case e1000_ms_auto: |
1722 | * and in the PHY to avoid CRC errors. | 1148 | phy_data &= ~CR_1000T_MS_ENABLE; |
1723 | */ | 1149 | default: |
1724 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, | 1150 | break; |
1725 | &phy_data); | 1151 | } |
1726 | if (ret_val) | 1152 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); |
1727 | return ret_val; | 1153 | if (ret_val) |
1728 | phy_data |= GG82563_ICR_DIS_PADDING; | 1154 | return ret_val; |
1729 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, | 1155 | } |
1730 | phy_data); | 1156 | |
1731 | if (ret_val) | 1157 | return E1000_SUCCESS; |
1732 | return ret_val; | ||
1733 | } | ||
1734 | |||
1735 | return E1000_SUCCESS; | ||
1736 | } | 1158 | } |
1737 | 1159 | ||
1738 | /******************************************************************** | 1160 | /** |
1739 | * Copper link setup for e1000_phy_m88 series. | 1161 | * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series. |
1740 | * | 1162 | * @hw: Struct containing variables accessed by shared code |
1741 | * hw - Struct containing variables accessed by shared code | 1163 | */ |
1742 | *********************************************************************/ | ||
1743 | static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw) | 1164 | static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw) |
1744 | { | 1165 | { |
1745 | s32 ret_val; | 1166 | s32 ret_val; |
1746 | u16 phy_data; | 1167 | u16 phy_data; |
1747 | 1168 | ||
1748 | DEBUGFUNC("e1000_copper_link_mgp_setup"); | 1169 | DEBUGFUNC("e1000_copper_link_mgp_setup"); |
1749 | 1170 | ||
1750 | if (hw->phy_reset_disable) | 1171 | if (hw->phy_reset_disable) |
1751 | return E1000_SUCCESS; | 1172 | return E1000_SUCCESS; |
1752 | 1173 | ||
1753 | /* Enable CRS on TX. This must be set for half-duplex operation. */ | 1174 | /* Enable CRS on TX. This must be set for half-duplex operation. */ |
1754 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | 1175 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
1755 | if (ret_val) | 1176 | if (ret_val) |
1756 | return ret_val; | 1177 | return ret_val; |
1757 | 1178 | ||
1758 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | 1179 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
1759 | 1180 | ||
1760 | /* Options: | 1181 | /* Options: |
1761 | * MDI/MDI-X = 0 (default) | 1182 | * MDI/MDI-X = 0 (default) |
1762 | * 0 - Auto for all speeds | 1183 | * 0 - Auto for all speeds |
1763 | * 1 - MDI mode | 1184 | * 1 - MDI mode |
1764 | * 2 - MDI-X mode | 1185 | * 2 - MDI-X mode |
1765 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | 1186 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
1766 | */ | 1187 | */ |
1767 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | 1188 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
1768 | 1189 | ||
1769 | switch (hw->mdix) { | 1190 | switch (hw->mdix) { |
1770 | case 1: | 1191 | case 1: |
1771 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; | 1192 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; |
1772 | break; | 1193 | break; |
1773 | case 2: | 1194 | case 2: |
1774 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; | 1195 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; |
1775 | break; | 1196 | break; |
1776 | case 3: | 1197 | case 3: |
1777 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; | 1198 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; |
1778 | break; | 1199 | break; |
1779 | case 0: | 1200 | case 0: |
1780 | default: | 1201 | default: |
1781 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; | 1202 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; |
1782 | break; | 1203 | break; |
1783 | } | 1204 | } |
1784 | 1205 | ||
1785 | /* Options: | 1206 | /* Options: |
1786 | * disable_polarity_correction = 0 (default) | 1207 | * disable_polarity_correction = 0 (default) |
1787 | * Automatic Correction for Reversed Cable Polarity | 1208 | * Automatic Correction for Reversed Cable Polarity |
1788 | * 0 - Disabled | 1209 | * 0 - Disabled |
1789 | * 1 - Enabled | 1210 | * 1 - Enabled |
1790 | */ | 1211 | */ |
1791 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; | 1212 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; |
1792 | if (hw->disable_polarity_correction == 1) | 1213 | if (hw->disable_polarity_correction == 1) |
1793 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; | 1214 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; |
1794 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | 1215 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
1795 | if (ret_val) | 1216 | if (ret_val) |
1796 | return ret_val; | 1217 | return ret_val; |
1797 | 1218 | ||
1798 | if (hw->phy_revision < M88E1011_I_REV_4) { | 1219 | if (hw->phy_revision < M88E1011_I_REV_4) { |
1799 | /* Force TX_CLK in the Extended PHY Specific Control Register | 1220 | /* Force TX_CLK in the Extended PHY Specific Control Register |
1800 | * to 25MHz clock. | 1221 | * to 25MHz clock. |
1801 | */ | 1222 | */ |
1802 | ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); | 1223 | ret_val = |
1803 | if (ret_val) | 1224 | e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
1804 | return ret_val; | 1225 | &phy_data); |
1805 | 1226 | if (ret_val) | |
1806 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | 1227 | return ret_val; |
1807 | 1228 | ||
1808 | if ((hw->phy_revision == E1000_REVISION_2) && | 1229 | phy_data |= M88E1000_EPSCR_TX_CLK_25; |
1809 | (hw->phy_id == M88E1111_I_PHY_ID)) { | 1230 | |
1810 | /* Vidalia Phy, set the downshift counter to 5x */ | 1231 | if ((hw->phy_revision == E1000_REVISION_2) && |
1811 | phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); | 1232 | (hw->phy_id == M88E1111_I_PHY_ID)) { |
1812 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; | 1233 | /* Vidalia Phy, set the downshift counter to 5x */ |
1813 | ret_val = e1000_write_phy_reg(hw, | 1234 | phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); |
1814 | M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | 1235 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; |
1815 | if (ret_val) | 1236 | ret_val = e1000_write_phy_reg(hw, |
1816 | return ret_val; | 1237 | M88E1000_EXT_PHY_SPEC_CTRL, |
1817 | } else { | 1238 | phy_data); |
1818 | /* Configure Master and Slave downshift values */ | 1239 | if (ret_val) |
1819 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | | 1240 | return ret_val; |
1820 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); | 1241 | } else { |
1821 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | | 1242 | /* Configure Master and Slave downshift values */ |
1822 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); | 1243 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | |
1823 | ret_val = e1000_write_phy_reg(hw, | 1244 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); |
1824 | M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | 1245 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | |
1825 | if (ret_val) | 1246 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); |
1826 | return ret_val; | 1247 | ret_val = e1000_write_phy_reg(hw, |
1827 | } | 1248 | M88E1000_EXT_PHY_SPEC_CTRL, |
1828 | } | 1249 | phy_data); |
1829 | 1250 | if (ret_val) | |
1830 | /* SW Reset the PHY so all changes take effect */ | 1251 | return ret_val; |
1831 | ret_val = e1000_phy_reset(hw); | 1252 | } |
1832 | if (ret_val) { | 1253 | } |
1833 | DEBUGOUT("Error Resetting the PHY\n"); | 1254 | |
1834 | return ret_val; | 1255 | /* SW Reset the PHY so all changes take effect */ |
1835 | } | 1256 | ret_val = e1000_phy_reset(hw); |
1836 | 1257 | if (ret_val) { | |
1837 | return E1000_SUCCESS; | 1258 | DEBUGOUT("Error Resetting the PHY\n"); |
1259 | return ret_val; | ||
1260 | } | ||
1261 | |||
1262 | return E1000_SUCCESS; | ||
1838 | } | 1263 | } |
1839 | 1264 | ||
1840 | /******************************************************************** | 1265 | /** |
1841 | * Setup auto-negotiation and flow control advertisements, | 1266 | * e1000_copper_link_autoneg - setup auto-neg |
1842 | * and then perform auto-negotiation. | 1267 | * @hw: Struct containing variables accessed by shared code |
1843 | * | 1268 | * |
1844 | * hw - Struct containing variables accessed by shared code | 1269 | * Setup auto-negotiation and flow control advertisements, |
1845 | *********************************************************************/ | 1270 | * and then perform auto-negotiation. |
1271 | */ | ||
1846 | static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) | 1272 | static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) |
1847 | { | 1273 | { |
1848 | s32 ret_val; | 1274 | s32 ret_val; |
1849 | u16 phy_data; | 1275 | u16 phy_data; |
1850 | 1276 | ||
1851 | DEBUGFUNC("e1000_copper_link_autoneg"); | 1277 | DEBUGFUNC("e1000_copper_link_autoneg"); |
1852 | 1278 | ||
1853 | /* Perform some bounds checking on the hw->autoneg_advertised | 1279 | /* Perform some bounds checking on the hw->autoneg_advertised |
1854 | * parameter. If this variable is zero, then set it to the default. | 1280 | * parameter. If this variable is zero, then set it to the default. |
1855 | */ | 1281 | */ |
1856 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; | 1282 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; |
1857 | 1283 | ||
1858 | /* If autoneg_advertised is zero, we assume it was not defaulted | 1284 | /* If autoneg_advertised is zero, we assume it was not defaulted |
1859 | * by the calling code so we set to advertise full capability. | 1285 | * by the calling code so we set to advertise full capability. |
1860 | */ | 1286 | */ |
1861 | if (hw->autoneg_advertised == 0) | 1287 | if (hw->autoneg_advertised == 0) |
1862 | hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; | 1288 | hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
1863 | 1289 | ||
1864 | /* IFE phy only supports 10/100 */ | 1290 | DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); |
1865 | if (hw->phy_type == e1000_phy_ife) | 1291 | ret_val = e1000_phy_setup_autoneg(hw); |
1866 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; | 1292 | if (ret_val) { |
1867 | 1293 | DEBUGOUT("Error Setting up Auto-Negotiation\n"); | |
1868 | DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); | 1294 | return ret_val; |
1869 | ret_val = e1000_phy_setup_autoneg(hw); | 1295 | } |
1870 | if (ret_val) { | 1296 | DEBUGOUT("Restarting Auto-Neg\n"); |
1871 | DEBUGOUT("Error Setting up Auto-Negotiation\n"); | 1297 | |
1872 | return ret_val; | 1298 | /* Restart auto-negotiation by setting the Auto Neg Enable bit and |
1873 | } | 1299 | * the Auto Neg Restart bit in the PHY control register. |
1874 | DEBUGOUT("Restarting Auto-Neg\n"); | 1300 | */ |
1875 | 1301 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); | |
1876 | /* Restart auto-negotiation by setting the Auto Neg Enable bit and | 1302 | if (ret_val) |
1877 | * the Auto Neg Restart bit in the PHY control register. | 1303 | return ret_val; |
1878 | */ | 1304 | |
1879 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); | 1305 | phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); |
1880 | if (ret_val) | 1306 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); |
1881 | return ret_val; | 1307 | if (ret_val) |
1882 | 1308 | return ret_val; | |
1883 | phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); | 1309 | |
1884 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); | 1310 | /* Does the user want to wait for Auto-Neg to complete here, or |
1885 | if (ret_val) | 1311 | * check at a later time (for example, callback routine). |
1886 | return ret_val; | 1312 | */ |
1887 | 1313 | if (hw->wait_autoneg_complete) { | |
1888 | /* Does the user want to wait for Auto-Neg to complete here, or | 1314 | ret_val = e1000_wait_autoneg(hw); |
1889 | * check at a later time (for example, callback routine). | 1315 | if (ret_val) { |
1890 | */ | 1316 | DEBUGOUT |
1891 | if (hw->wait_autoneg_complete) { | 1317 | ("Error while waiting for autoneg to complete\n"); |
1892 | ret_val = e1000_wait_autoneg(hw); | 1318 | return ret_val; |
1893 | if (ret_val) { | 1319 | } |
1894 | DEBUGOUT("Error while waiting for autoneg to complete\n"); | 1320 | } |
1895 | return ret_val; | 1321 | |
1896 | } | 1322 | hw->get_link_status = true; |
1897 | } | 1323 | |
1898 | 1324 | return E1000_SUCCESS; | |
1899 | hw->get_link_status = true; | ||
1900 | |||
1901 | return E1000_SUCCESS; | ||
1902 | } | 1325 | } |
1903 | 1326 | ||
1904 | /****************************************************************************** | 1327 | /** |
1905 | * Config the MAC and the PHY after link is up. | 1328 | * e1000_copper_link_postconfig - post link setup |
1906 | * 1) Set up the MAC to the current PHY speed/duplex | 1329 | * @hw: Struct containing variables accessed by shared code |
1907 | * if we are on 82543. If we | 1330 | * |
1908 | * are on newer silicon, we only need to configure | 1331 | * Config the MAC and the PHY after link is up. |
1909 | * collision distance in the Transmit Control Register. | 1332 | * 1) Set up the MAC to the current PHY speed/duplex |
1910 | * 2) Set up flow control on the MAC to that established with | 1333 | * if we are on 82543. If we |
1911 | * the link partner. | 1334 | * are on newer silicon, we only need to configure |
1912 | * 3) Config DSP to improve Gigabit link quality for some PHY revisions. | 1335 | * collision distance in the Transmit Control Register. |
1913 | * | 1336 | * 2) Set up flow control on the MAC to that established with |
1914 | * hw - Struct containing variables accessed by shared code | 1337 | * the link partner. |
1915 | ******************************************************************************/ | 1338 | * 3) Config DSP to improve Gigabit link quality for some PHY revisions. |
1339 | */ | ||
1916 | static s32 e1000_copper_link_postconfig(struct e1000_hw *hw) | 1340 | static s32 e1000_copper_link_postconfig(struct e1000_hw *hw) |
1917 | { | 1341 | { |
1918 | s32 ret_val; | 1342 | s32 ret_val; |
1919 | DEBUGFUNC("e1000_copper_link_postconfig"); | 1343 | DEBUGFUNC("e1000_copper_link_postconfig"); |
1920 | 1344 | ||
1921 | if (hw->mac_type >= e1000_82544) { | 1345 | if (hw->mac_type >= e1000_82544) { |
1922 | e1000_config_collision_dist(hw); | 1346 | e1000_config_collision_dist(hw); |
1923 | } else { | 1347 | } else { |
1924 | ret_val = e1000_config_mac_to_phy(hw); | 1348 | ret_val = e1000_config_mac_to_phy(hw); |
1925 | if (ret_val) { | 1349 | if (ret_val) { |
1926 | DEBUGOUT("Error configuring MAC to PHY settings\n"); | 1350 | DEBUGOUT("Error configuring MAC to PHY settings\n"); |
1927 | return ret_val; | 1351 | return ret_val; |
1928 | } | 1352 | } |
1929 | } | 1353 | } |
1930 | ret_val = e1000_config_fc_after_link_up(hw); | 1354 | ret_val = e1000_config_fc_after_link_up(hw); |
1931 | if (ret_val) { | 1355 | if (ret_val) { |
1932 | DEBUGOUT("Error Configuring Flow Control\n"); | 1356 | DEBUGOUT("Error Configuring Flow Control\n"); |
1933 | return ret_val; | 1357 | return ret_val; |
1934 | } | 1358 | } |
1935 | 1359 | ||
1936 | /* Config DSP to improve Giga link quality */ | 1360 | /* Config DSP to improve Giga link quality */ |
1937 | if (hw->phy_type == e1000_phy_igp) { | 1361 | if (hw->phy_type == e1000_phy_igp) { |
1938 | ret_val = e1000_config_dsp_after_link_change(hw, true); | 1362 | ret_val = e1000_config_dsp_after_link_change(hw, true); |
1939 | if (ret_val) { | 1363 | if (ret_val) { |
1940 | DEBUGOUT("Error Configuring DSP after link up\n"); | 1364 | DEBUGOUT("Error Configuring DSP after link up\n"); |
1941 | return ret_val; | 1365 | return ret_val; |
1942 | } | 1366 | } |
1943 | } | 1367 | } |
1944 | 1368 | ||
1945 | return E1000_SUCCESS; | 1369 | return E1000_SUCCESS; |
1946 | } | 1370 | } |
1947 | 1371 | ||
1948 | /****************************************************************************** | 1372 | /** |
1949 | * Detects which PHY is present and setup the speed and duplex | 1373 | * e1000_setup_copper_link - phy/speed/duplex setting |
1950 | * | 1374 | * @hw: Struct containing variables accessed by shared code |
1951 | * hw - Struct containing variables accessed by shared code | 1375 | * |
1952 | ******************************************************************************/ | 1376 | * Detects which PHY is present and sets up the speed and duplex |
1377 | */ | ||
1953 | static s32 e1000_setup_copper_link(struct e1000_hw *hw) | 1378 | static s32 e1000_setup_copper_link(struct e1000_hw *hw) |
1954 | { | 1379 | { |
1955 | s32 ret_val; | 1380 | s32 ret_val; |
1956 | u16 i; | 1381 | u16 i; |
1957 | u16 phy_data; | 1382 | u16 phy_data; |
1958 | u16 reg_data = 0; | 1383 | |
1959 | 1384 | DEBUGFUNC("e1000_setup_copper_link"); | |
1960 | DEBUGFUNC("e1000_setup_copper_link"); | 1385 | |
1961 | 1386 | /* Check if it is a valid PHY and set PHY mode if necessary. */ | |
1962 | switch (hw->mac_type) { | 1387 | ret_val = e1000_copper_link_preconfig(hw); |
1963 | case e1000_80003es2lan: | 1388 | if (ret_val) |
1964 | case e1000_ich8lan: | 1389 | return ret_val; |
1965 | /* Set the mac to wait the maximum time between each | 1390 | |
1966 | * iteration and increase the max iterations when | 1391 | if (hw->phy_type == e1000_phy_igp) { |
1967 | * polling the phy; this fixes erroneous timeouts at 10Mbps. */ | 1392 | ret_val = e1000_copper_link_igp_setup(hw); |
1968 | ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); | 1393 | if (ret_val) |
1969 | if (ret_val) | 1394 | return ret_val; |
1970 | return ret_val; | 1395 | } else if (hw->phy_type == e1000_phy_m88) { |
1971 | ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); | 1396 | ret_val = e1000_copper_link_mgp_setup(hw); |
1972 | if (ret_val) | 1397 | if (ret_val) |
1973 | return ret_val; | 1398 | return ret_val; |
1974 | reg_data |= 0x3F; | 1399 | } |
1975 | ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); | 1400 | |
1976 | if (ret_val) | 1401 | if (hw->autoneg) { |
1977 | return ret_val; | 1402 | /* Setup autoneg and flow control advertisement |
1978 | default: | 1403 | * and perform autonegotiation */ |
1979 | break; | 1404 | ret_val = e1000_copper_link_autoneg(hw); |
1980 | } | 1405 | if (ret_val) |
1981 | 1406 | return ret_val; | |
1982 | /* Check if it is a valid PHY and set PHY mode if necessary. */ | 1407 | } else { |
1983 | ret_val = e1000_copper_link_preconfig(hw); | 1408 | /* PHY will be set to 10H, 10F, 100H,or 100F |
1984 | if (ret_val) | 1409 | * depending on value from forced_speed_duplex. */ |
1985 | return ret_val; | 1410 | DEBUGOUT("Forcing speed and duplex\n"); |
1986 | 1411 | ret_val = e1000_phy_force_speed_duplex(hw); | |
1987 | switch (hw->mac_type) { | 1412 | if (ret_val) { |
1988 | case e1000_80003es2lan: | 1413 | DEBUGOUT("Error Forcing Speed and Duplex\n"); |
1989 | /* Kumeran registers are written-only */ | 1414 | return ret_val; |
1990 | reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; | 1415 | } |
1991 | reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; | 1416 | } |
1992 | ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, | 1417 | |
1993 | reg_data); | 1418 | /* Check link status. Wait up to 100 microseconds for link to become |
1994 | if (ret_val) | 1419 | * valid. |
1995 | return ret_val; | 1420 | */ |
1996 | break; | 1421 | for (i = 0; i < 10; i++) { |
1997 | default: | 1422 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
1998 | break; | 1423 | if (ret_val) |
1999 | } | 1424 | return ret_val; |
2000 | 1425 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
2001 | if (hw->phy_type == e1000_phy_igp || | 1426 | if (ret_val) |
2002 | hw->phy_type == e1000_phy_igp_3 || | 1427 | return ret_val; |
2003 | hw->phy_type == e1000_phy_igp_2) { | 1428 | |
2004 | ret_val = e1000_copper_link_igp_setup(hw); | 1429 | if (phy_data & MII_SR_LINK_STATUS) { |
2005 | if (ret_val) | 1430 | /* Config the MAC and PHY after link is up */ |
2006 | return ret_val; | 1431 | ret_val = e1000_copper_link_postconfig(hw); |
2007 | } else if (hw->phy_type == e1000_phy_m88) { | 1432 | if (ret_val) |
2008 | ret_val = e1000_copper_link_mgp_setup(hw); | 1433 | return ret_val; |
2009 | if (ret_val) | 1434 | |
2010 | return ret_val; | 1435 | DEBUGOUT("Valid link established!!!\n"); |
2011 | } else if (hw->phy_type == e1000_phy_gg82563) { | 1436 | return E1000_SUCCESS; |
2012 | ret_val = e1000_copper_link_ggp_setup(hw); | 1437 | } |
2013 | if (ret_val) | 1438 | udelay(10); |
2014 | return ret_val; | 1439 | } |
2015 | } | 1440 | |
2016 | 1441 | DEBUGOUT("Unable to establish link!!!\n"); | |
2017 | if (hw->autoneg) { | 1442 | return E1000_SUCCESS; |
2018 | /* Setup autoneg and flow control advertisement | ||
2019 | * and perform autonegotiation */ | ||
2020 | ret_val = e1000_copper_link_autoneg(hw); | ||
2021 | if (ret_val) | ||
2022 | return ret_val; | ||
2023 | } else { | ||
2024 | /* PHY will be set to 10H, 10F, 100H,or 100F | ||
2025 | * depending on value from forced_speed_duplex. */ | ||
2026 | DEBUGOUT("Forcing speed and duplex\n"); | ||
2027 | ret_val = e1000_phy_force_speed_duplex(hw); | ||
2028 | if (ret_val) { | ||
2029 | DEBUGOUT("Error Forcing Speed and Duplex\n"); | ||
2030 | return ret_val; | ||
2031 | } | ||
2032 | } | ||
2033 | |||
2034 | /* Check link status. Wait up to 100 microseconds for link to become | ||
2035 | * valid. | ||
2036 | */ | ||
2037 | for (i = 0; i < 10; i++) { | ||
2038 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | ||
2039 | if (ret_val) | ||
2040 | return ret_val; | ||
2041 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | ||
2042 | if (ret_val) | ||
2043 | return ret_val; | ||
2044 | |||
2045 | if (phy_data & MII_SR_LINK_STATUS) { | ||
2046 | /* Config the MAC and PHY after link is up */ | ||
2047 | ret_val = e1000_copper_link_postconfig(hw); | ||
2048 | if (ret_val) | ||
2049 | return ret_val; | ||
2050 | |||
2051 | DEBUGOUT("Valid link established!!!\n"); | ||
2052 | return E1000_SUCCESS; | ||
2053 | } | ||
2054 | udelay(10); | ||
2055 | } | ||
2056 | |||
2057 | DEBUGOUT("Unable to establish link!!!\n"); | ||
2058 | return E1000_SUCCESS; | ||
2059 | } | 1443 | } |
2060 | 1444 | ||
2061 | /****************************************************************************** | 1445 | /** |
2062 | * Configure the MAC-to-PHY interface for 10/100Mbps | 1446 | * e1000_phy_setup_autoneg - phy settings |
2063 | * | 1447 | * @hw: Struct containing variables accessed by shared code |
2064 | * hw - Struct containing variables accessed by shared code | 1448 | * |
2065 | ******************************************************************************/ | 1449 | * Configures PHY autoneg and flow control advertisement settings |
2066 | static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex) | 1450 | */ |
1451 | s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) | ||
2067 | { | 1452 | { |
2068 | s32 ret_val = E1000_SUCCESS; | 1453 | s32 ret_val; |
2069 | u32 tipg; | 1454 | u16 mii_autoneg_adv_reg; |
2070 | u16 reg_data; | 1455 | u16 mii_1000t_ctrl_reg; |
2071 | 1456 | ||
2072 | DEBUGFUNC("e1000_configure_kmrn_for_10_100"); | 1457 | DEBUGFUNC("e1000_phy_setup_autoneg"); |
2073 | 1458 | ||
2074 | reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; | 1459 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ |
2075 | ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, | 1460 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); |
2076 | reg_data); | 1461 | if (ret_val) |
2077 | if (ret_val) | 1462 | return ret_val; |
2078 | return ret_val; | ||
2079 | 1463 | ||
2080 | /* Configure Transmit Inter-Packet Gap */ | 1464 | /* Read the MII 1000Base-T Control Register (Address 9). */ |
2081 | tipg = er32(TIPG); | 1465 | ret_val = |
2082 | tipg &= ~E1000_TIPG_IPGT_MASK; | 1466 | e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); |
2083 | tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; | 1467 | if (ret_val) |
2084 | ew32(TIPG, tipg); | 1468 | return ret_val; |
2085 | 1469 | ||
2086 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); | 1470 | /* Need to parse both autoneg_advertised and fc and set up |
1471 | * the appropriate PHY registers. First we will parse for | ||
1472 | * autoneg_advertised software override. Since we can advertise | ||
1473 | * a plethora of combinations, we need to check each bit | ||
1474 | * individually. | ||
1475 | */ | ||
2087 | 1476 | ||
2088 | if (ret_val) | 1477 | /* First we clear all the 10/100 mb speed bits in the Auto-Neg |
2089 | return ret_val; | 1478 | * Advertisement Register (Address 4) and the 1000 mb speed bits in |
1479 | * the 1000Base-T Control Register (Address 9). | ||
1480 | */ | ||
1481 | mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; | ||
1482 | mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; | ||
2090 | 1483 | ||
2091 | if (duplex == HALF_DUPLEX) | 1484 | DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); |
2092 | reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; | ||
2093 | else | ||
2094 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | ||
2095 | 1485 | ||
2096 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | 1486 | /* Do we want to advertise 10 Mb Half Duplex? */ |
1487 | if (hw->autoneg_advertised & ADVERTISE_10_HALF) { | ||
1488 | DEBUGOUT("Advertise 10mb Half duplex\n"); | ||
1489 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; | ||
1490 | } | ||
2097 | 1491 | ||
2098 | return ret_val; | 1492 | /* Do we want to advertise 10 Mb Full Duplex? */ |
2099 | } | 1493 | if (hw->autoneg_advertised & ADVERTISE_10_FULL) { |
1494 | DEBUGOUT("Advertise 10mb Full duplex\n"); | ||
1495 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; | ||
1496 | } | ||
2100 | 1497 | ||
2101 | static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw) | 1498 | /* Do we want to advertise 100 Mb Half Duplex? */ |
2102 | { | 1499 | if (hw->autoneg_advertised & ADVERTISE_100_HALF) { |
2103 | s32 ret_val = E1000_SUCCESS; | 1500 | DEBUGOUT("Advertise 100mb Half duplex\n"); |
2104 | u16 reg_data; | 1501 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; |
2105 | u32 tipg; | 1502 | } |
2106 | 1503 | ||
2107 | DEBUGFUNC("e1000_configure_kmrn_for_1000"); | 1504 | /* Do we want to advertise 100 Mb Full Duplex? */ |
1505 | if (hw->autoneg_advertised & ADVERTISE_100_FULL) { | ||
1506 | DEBUGOUT("Advertise 100mb Full duplex\n"); | ||
1507 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; | ||
1508 | } | ||
2108 | 1509 | ||
2109 | reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; | 1510 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ |
2110 | ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, | 1511 | if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { |
2111 | reg_data); | 1512 | DEBUGOUT |
2112 | if (ret_val) | 1513 | ("Advertise 1000mb Half duplex requested, request denied!\n"); |
2113 | return ret_val; | 1514 | } |
2114 | 1515 | ||
2115 | /* Configure Transmit Inter-Packet Gap */ | 1516 | /* Do we want to advertise 1000 Mb Full Duplex? */ |
2116 | tipg = er32(TIPG); | 1517 | if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { |
2117 | tipg &= ~E1000_TIPG_IPGT_MASK; | 1518 | DEBUGOUT("Advertise 1000mb Full duplex\n"); |
2118 | tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; | 1519 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; |
2119 | ew32(TIPG, tipg); | 1520 | } |
2120 | 1521 | ||
2121 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); | 1522 | /* Check for a software override of the flow control settings, and |
1523 | * setup the PHY advertisement registers accordingly. If | ||
1524 | * auto-negotiation is enabled, then software will have to set the | ||
1525 | * "PAUSE" bits to the correct value in the Auto-Negotiation | ||
1526 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. | ||
1527 | * | ||
1528 | * The possible values of the "fc" parameter are: | ||
1529 | * 0: Flow control is completely disabled | ||
1530 | * 1: Rx flow control is enabled (we can receive pause frames | ||
1531 | * but not send pause frames). | ||
1532 | * 2: Tx flow control is enabled (we can send pause frames | ||
1533 | * but we do not support receiving pause frames). | ||
1534 | * 3: Both Rx and TX flow control (symmetric) are enabled. | ||
1535 | * other: No software override. The flow control configuration | ||
1536 | * in the EEPROM is used. | ||
1537 | */ | ||
1538 | switch (hw->fc) { | ||
1539 | case E1000_FC_NONE: /* 0 */ | ||
1540 | /* Flow control (RX & TX) is completely disabled by a | ||
1541 | * software over-ride. | ||
1542 | */ | ||
1543 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | ||
1544 | break; | ||
1545 | case E1000_FC_RX_PAUSE: /* 1 */ | ||
1546 | /* RX Flow control is enabled, and TX Flow control is | ||
1547 | * disabled, by a software over-ride. | ||
1548 | */ | ||
1549 | /* Since there really isn't a way to advertise that we are | ||
1550 | * capable of RX Pause ONLY, we will advertise that we | ||
1551 | * support both symmetric and asymmetric RX PAUSE. Later | ||
1552 | * (in e1000_config_fc_after_link_up) we will disable the | ||
1553 | *hw's ability to send PAUSE frames. | ||
1554 | */ | ||
1555 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | ||
1556 | break; | ||
1557 | case E1000_FC_TX_PAUSE: /* 2 */ | ||
1558 | /* TX Flow control is enabled, and RX Flow control is | ||
1559 | * disabled, by a software over-ride. | ||
1560 | */ | ||
1561 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; | ||
1562 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; | ||
1563 | break; | ||
1564 | case E1000_FC_FULL: /* 3 */ | ||
1565 | /* Flow control (both RX and TX) is enabled by a software | ||
1566 | * over-ride. | ||
1567 | */ | ||
1568 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | ||
1569 | break; | ||
1570 | default: | ||
1571 | DEBUGOUT("Flow control param set incorrectly\n"); | ||
1572 | return -E1000_ERR_CONFIG; | ||
1573 | } | ||
2122 | 1574 | ||
2123 | if (ret_val) | 1575 | ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); |
2124 | return ret_val; | 1576 | if (ret_val) |
1577 | return ret_val; | ||
2125 | 1578 | ||
2126 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | 1579 | DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
2127 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | ||
2128 | 1580 | ||
2129 | return ret_val; | 1581 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); |
2130 | } | 1582 | if (ret_val) |
1583 | return ret_val; | ||
2131 | 1584 | ||
2132 | /****************************************************************************** | 1585 | return E1000_SUCCESS; |
2133 | * Configures PHY autoneg and flow control advertisement settings | ||
2134 | * | ||
2135 | * hw - Struct containing variables accessed by shared code | ||
2136 | ******************************************************************************/ | ||
2137 | s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) | ||
2138 | { | ||
2139 | s32 ret_val; | ||
2140 | u16 mii_autoneg_adv_reg; | ||
2141 | u16 mii_1000t_ctrl_reg; | ||
2142 | |||
2143 | DEBUGFUNC("e1000_phy_setup_autoneg"); | ||
2144 | |||
2145 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ | ||
2146 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); | ||
2147 | if (ret_val) | ||
2148 | return ret_val; | ||
2149 | |||
2150 | if (hw->phy_type != e1000_phy_ife) { | ||
2151 | /* Read the MII 1000Base-T Control Register (Address 9). */ | ||
2152 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); | ||
2153 | if (ret_val) | ||
2154 | return ret_val; | ||
2155 | } else | ||
2156 | mii_1000t_ctrl_reg=0; | ||
2157 | |||
2158 | /* Need to parse both autoneg_advertised and fc and set up | ||
2159 | * the appropriate PHY registers. First we will parse for | ||
2160 | * autoneg_advertised software override. Since we can advertise | ||
2161 | * a plethora of combinations, we need to check each bit | ||
2162 | * individually. | ||
2163 | */ | ||
2164 | |||
2165 | /* First we clear all the 10/100 mb speed bits in the Auto-Neg | ||
2166 | * Advertisement Register (Address 4) and the 1000 mb speed bits in | ||
2167 | * the 1000Base-T Control Register (Address 9). | ||
2168 | */ | ||
2169 | mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; | ||
2170 | mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; | ||
2171 | |||
2172 | DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); | ||
2173 | |||
2174 | /* Do we want to advertise 10 Mb Half Duplex? */ | ||
2175 | if (hw->autoneg_advertised & ADVERTISE_10_HALF) { | ||
2176 | DEBUGOUT("Advertise 10mb Half duplex\n"); | ||
2177 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; | ||
2178 | } | ||
2179 | |||
2180 | /* Do we want to advertise 10 Mb Full Duplex? */ | ||
2181 | if (hw->autoneg_advertised & ADVERTISE_10_FULL) { | ||
2182 | DEBUGOUT("Advertise 10mb Full duplex\n"); | ||
2183 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; | ||
2184 | } | ||
2185 | |||
2186 | /* Do we want to advertise 100 Mb Half Duplex? */ | ||
2187 | if (hw->autoneg_advertised & ADVERTISE_100_HALF) { | ||
2188 | DEBUGOUT("Advertise 100mb Half duplex\n"); | ||
2189 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; | ||
2190 | } | ||
2191 | |||
2192 | /* Do we want to advertise 100 Mb Full Duplex? */ | ||
2193 | if (hw->autoneg_advertised & ADVERTISE_100_FULL) { | ||
2194 | DEBUGOUT("Advertise 100mb Full duplex\n"); | ||
2195 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; | ||
2196 | } | ||
2197 | |||
2198 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ | ||
2199 | if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { | ||
2200 | DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); | ||
2201 | } | ||
2202 | |||
2203 | /* Do we want to advertise 1000 Mb Full Duplex? */ | ||
2204 | if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { | ||
2205 | DEBUGOUT("Advertise 1000mb Full duplex\n"); | ||
2206 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; | ||
2207 | if (hw->phy_type == e1000_phy_ife) { | ||
2208 | DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n"); | ||
2209 | } | ||
2210 | } | ||
2211 | |||
2212 | /* Check for a software override of the flow control settings, and | ||
2213 | * setup the PHY advertisement registers accordingly. If | ||
2214 | * auto-negotiation is enabled, then software will have to set the | ||
2215 | * "PAUSE" bits to the correct value in the Auto-Negotiation | ||
2216 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. | ||
2217 | * | ||
2218 | * The possible values of the "fc" parameter are: | ||
2219 | * 0: Flow control is completely disabled | ||
2220 | * 1: Rx flow control is enabled (we can receive pause frames | ||
2221 | * but not send pause frames). | ||
2222 | * 2: Tx flow control is enabled (we can send pause frames | ||
2223 | * but we do not support receiving pause frames). | ||
2224 | * 3: Both Rx and TX flow control (symmetric) are enabled. | ||
2225 | * other: No software override. The flow control configuration | ||
2226 | * in the EEPROM is used. | ||
2227 | */ | ||
2228 | switch (hw->fc) { | ||
2229 | case E1000_FC_NONE: /* 0 */ | ||
2230 | /* Flow control (RX & TX) is completely disabled by a | ||
2231 | * software over-ride. | ||
2232 | */ | ||
2233 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | ||
2234 | break; | ||
2235 | case E1000_FC_RX_PAUSE: /* 1 */ | ||
2236 | /* RX Flow control is enabled, and TX Flow control is | ||
2237 | * disabled, by a software over-ride. | ||
2238 | */ | ||
2239 | /* Since there really isn't a way to advertise that we are | ||
2240 | * capable of RX Pause ONLY, we will advertise that we | ||
2241 | * support both symmetric and asymmetric RX PAUSE. Later | ||
2242 | * (in e1000_config_fc_after_link_up) we will disable the | ||
2243 | *hw's ability to send PAUSE frames. | ||
2244 | */ | ||
2245 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | ||
2246 | break; | ||
2247 | case E1000_FC_TX_PAUSE: /* 2 */ | ||
2248 | /* TX Flow control is enabled, and RX Flow control is | ||
2249 | * disabled, by a software over-ride. | ||
2250 | */ | ||
2251 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; | ||
2252 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; | ||
2253 | break; | ||
2254 | case E1000_FC_FULL: /* 3 */ | ||
2255 | /* Flow control (both RX and TX) is enabled by a software | ||
2256 | * over-ride. | ||
2257 | */ | ||
2258 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | ||
2259 | break; | ||
2260 | default: | ||
2261 | DEBUGOUT("Flow control param set incorrectly\n"); | ||
2262 | return -E1000_ERR_CONFIG; | ||
2263 | } | ||
2264 | |||
2265 | ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); | ||
2266 | if (ret_val) | ||
2267 | return ret_val; | ||
2268 | |||
2269 | DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); | ||
2270 | |||
2271 | if (hw->phy_type != e1000_phy_ife) { | ||
2272 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); | ||
2273 | if (ret_val) | ||
2274 | return ret_val; | ||
2275 | } | ||
2276 | |||
2277 | return E1000_SUCCESS; | ||
2278 | } | 1586 | } |
2279 | 1587 | ||
2280 | /****************************************************************************** | 1588 | /** |
2281 | * Force PHY speed and duplex settings to hw->forced_speed_duplex | 1589 | * e1000_phy_force_speed_duplex - force link settings |
2282 | * | 1590 | * @hw: Struct containing variables accessed by shared code |
2283 | * hw - Struct containing variables accessed by shared code | 1591 | * |
2284 | ******************************************************************************/ | 1592 | * Force PHY speed and duplex settings to hw->forced_speed_duplex |
1593 | */ | ||
2285 | static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) | 1594 | static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) |
2286 | { | 1595 | { |
2287 | u32 ctrl; | 1596 | u32 ctrl; |
2288 | s32 ret_val; | 1597 | s32 ret_val; |
2289 | u16 mii_ctrl_reg; | 1598 | u16 mii_ctrl_reg; |
2290 | u16 mii_status_reg; | 1599 | u16 mii_status_reg; |
2291 | u16 phy_data; | 1600 | u16 phy_data; |
2292 | u16 i; | 1601 | u16 i; |
2293 | 1602 | ||
2294 | DEBUGFUNC("e1000_phy_force_speed_duplex"); | 1603 | DEBUGFUNC("e1000_phy_force_speed_duplex"); |
2295 | 1604 | ||
2296 | /* Turn off Flow control if we are forcing speed and duplex. */ | 1605 | /* Turn off Flow control if we are forcing speed and duplex. */ |
2297 | hw->fc = E1000_FC_NONE; | 1606 | hw->fc = E1000_FC_NONE; |
2298 | 1607 | ||
2299 | DEBUGOUT1("hw->fc = %d\n", hw->fc); | 1608 | DEBUGOUT1("hw->fc = %d\n", hw->fc); |
2300 | 1609 | ||
2301 | /* Read the Device Control Register. */ | 1610 | /* Read the Device Control Register. */ |
2302 | ctrl = er32(CTRL); | 1611 | ctrl = er32(CTRL); |
2303 | 1612 | ||
2304 | /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ | 1613 | /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ |
2305 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | 1614 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
2306 | ctrl &= ~(DEVICE_SPEED_MASK); | 1615 | ctrl &= ~(DEVICE_SPEED_MASK); |
2307 | 1616 | ||
2308 | /* Clear the Auto Speed Detect Enable bit. */ | 1617 | /* Clear the Auto Speed Detect Enable bit. */ |
2309 | ctrl &= ~E1000_CTRL_ASDE; | 1618 | ctrl &= ~E1000_CTRL_ASDE; |
2310 | 1619 | ||
2311 | /* Read the MII Control Register. */ | 1620 | /* Read the MII Control Register. */ |
2312 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); | 1621 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); |
2313 | if (ret_val) | 1622 | if (ret_val) |
2314 | return ret_val; | 1623 | return ret_val; |
2315 | 1624 | ||
2316 | /* We need to disable autoneg in order to force link and duplex. */ | 1625 | /* We need to disable autoneg in order to force link and duplex. */ |
2317 | 1626 | ||
2318 | mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; | 1627 | mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; |
2319 | 1628 | ||
2320 | /* Are we forcing Full or Half Duplex? */ | 1629 | /* Are we forcing Full or Half Duplex? */ |
2321 | if (hw->forced_speed_duplex == e1000_100_full || | 1630 | if (hw->forced_speed_duplex == e1000_100_full || |
2322 | hw->forced_speed_duplex == e1000_10_full) { | 1631 | hw->forced_speed_duplex == e1000_10_full) { |
2323 | /* We want to force full duplex so we SET the full duplex bits in the | 1632 | /* We want to force full duplex so we SET the full duplex bits in the |
2324 | * Device and MII Control Registers. | 1633 | * Device and MII Control Registers. |
2325 | */ | 1634 | */ |
2326 | ctrl |= E1000_CTRL_FD; | 1635 | ctrl |= E1000_CTRL_FD; |
2327 | mii_ctrl_reg |= MII_CR_FULL_DUPLEX; | 1636 | mii_ctrl_reg |= MII_CR_FULL_DUPLEX; |
2328 | DEBUGOUT("Full Duplex\n"); | 1637 | DEBUGOUT("Full Duplex\n"); |
2329 | } else { | 1638 | } else { |
2330 | /* We want to force half duplex so we CLEAR the full duplex bits in | 1639 | /* We want to force half duplex so we CLEAR the full duplex bits in |
2331 | * the Device and MII Control Registers. | 1640 | * the Device and MII Control Registers. |
2332 | */ | 1641 | */ |
2333 | ctrl &= ~E1000_CTRL_FD; | 1642 | ctrl &= ~E1000_CTRL_FD; |
2334 | mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; | 1643 | mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; |
2335 | DEBUGOUT("Half Duplex\n"); | 1644 | DEBUGOUT("Half Duplex\n"); |
2336 | } | 1645 | } |
2337 | 1646 | ||
2338 | /* Are we forcing 100Mbps??? */ | 1647 | /* Are we forcing 100Mbps??? */ |
2339 | if (hw->forced_speed_duplex == e1000_100_full || | 1648 | if (hw->forced_speed_duplex == e1000_100_full || |
2340 | hw->forced_speed_duplex == e1000_100_half) { | 1649 | hw->forced_speed_duplex == e1000_100_half) { |
2341 | /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ | 1650 | /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ |
2342 | ctrl |= E1000_CTRL_SPD_100; | 1651 | ctrl |= E1000_CTRL_SPD_100; |
2343 | mii_ctrl_reg |= MII_CR_SPEED_100; | 1652 | mii_ctrl_reg |= MII_CR_SPEED_100; |
2344 | mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); | 1653 | mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); |
2345 | DEBUGOUT("Forcing 100mb "); | 1654 | DEBUGOUT("Forcing 100mb "); |
2346 | } else { | 1655 | } else { |
2347 | /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ | 1656 | /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ |
2348 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); | 1657 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); |
2349 | mii_ctrl_reg |= MII_CR_SPEED_10; | 1658 | mii_ctrl_reg |= MII_CR_SPEED_10; |
2350 | mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); | 1659 | mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); |
2351 | DEBUGOUT("Forcing 10mb "); | 1660 | DEBUGOUT("Forcing 10mb "); |
2352 | } | 1661 | } |
2353 | 1662 | ||
2354 | e1000_config_collision_dist(hw); | 1663 | e1000_config_collision_dist(hw); |
2355 | 1664 | ||
2356 | /* Write the configured values back to the Device Control Reg. */ | 1665 | /* Write the configured values back to the Device Control Reg. */ |
2357 | ew32(CTRL, ctrl); | 1666 | ew32(CTRL, ctrl); |
2358 | 1667 | ||
2359 | if ((hw->phy_type == e1000_phy_m88) || | 1668 | if (hw->phy_type == e1000_phy_m88) { |
2360 | (hw->phy_type == e1000_phy_gg82563)) { | 1669 | ret_val = |
2361 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | 1670 | e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
2362 | if (ret_val) | 1671 | if (ret_val) |
2363 | return ret_val; | 1672 | return ret_val; |
2364 | 1673 | ||
2365 | /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI | 1674 | /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI |
2366 | * forced whenever speed are duplex are forced. | 1675 | * forced whenever speed are duplex are forced. |
2367 | */ | 1676 | */ |
2368 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | 1677 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
2369 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | 1678 | ret_val = |
2370 | if (ret_val) | 1679 | e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
2371 | return ret_val; | 1680 | if (ret_val) |
2372 | 1681 | return ret_val; | |
2373 | DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); | 1682 | |
2374 | 1683 | DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); | |
2375 | /* Need to reset the PHY or these changes will be ignored */ | 1684 | |
2376 | mii_ctrl_reg |= MII_CR_RESET; | 1685 | /* Need to reset the PHY or these changes will be ignored */ |
2377 | 1686 | mii_ctrl_reg |= MII_CR_RESET; | |
2378 | /* Disable MDI-X support for 10/100 */ | 1687 | |
2379 | } else if (hw->phy_type == e1000_phy_ife) { | 1688 | /* Disable MDI-X support for 10/100 */ |
2380 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); | 1689 | } else { |
2381 | if (ret_val) | 1690 | /* Clear Auto-Crossover to force MDI manually. IGP requires MDI |
2382 | return ret_val; | 1691 | * forced whenever speed or duplex are forced. |
2383 | 1692 | */ | |
2384 | phy_data &= ~IFE_PMC_AUTO_MDIX; | 1693 | ret_val = |
2385 | phy_data &= ~IFE_PMC_FORCE_MDIX; | 1694 | e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
2386 | 1695 | if (ret_val) | |
2387 | ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); | 1696 | return ret_val; |
2388 | if (ret_val) | 1697 | |
2389 | return ret_val; | 1698 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
2390 | 1699 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
2391 | } else { | 1700 | |
2392 | /* Clear Auto-Crossover to force MDI manually. IGP requires MDI | 1701 | ret_val = |
2393 | * forced whenever speed or duplex are forced. | 1702 | e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
2394 | */ | 1703 | if (ret_val) |
2395 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); | 1704 | return ret_val; |
2396 | if (ret_val) | 1705 | } |
2397 | return ret_val; | 1706 | |
2398 | 1707 | /* Write back the modified PHY MII control register. */ | |
2399 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | 1708 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); |
2400 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | 1709 | if (ret_val) |
2401 | 1710 | return ret_val; | |
2402 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); | 1711 | |
2403 | if (ret_val) | 1712 | udelay(1); |
2404 | return ret_val; | 1713 | |
2405 | } | 1714 | /* The wait_autoneg_complete flag may be a little misleading here. |
2406 | 1715 | * Since we are forcing speed and duplex, Auto-Neg is not enabled. | |
2407 | /* Write back the modified PHY MII control register. */ | 1716 | * But we do want to delay for a period while forcing only so we |
2408 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); | 1717 | * don't generate false No Link messages. So we will wait here |
2409 | if (ret_val) | 1718 | * only if the user has set wait_autoneg_complete to 1, which is |
2410 | return ret_val; | 1719 | * the default. |
2411 | 1720 | */ | |
2412 | udelay(1); | 1721 | if (hw->wait_autoneg_complete) { |
2413 | 1722 | /* We will wait for autoneg to complete. */ | |
2414 | /* The wait_autoneg_complete flag may be a little misleading here. | 1723 | DEBUGOUT("Waiting for forced speed/duplex link.\n"); |
2415 | * Since we are forcing speed and duplex, Auto-Neg is not enabled. | 1724 | mii_status_reg = 0; |
2416 | * But we do want to delay for a period while forcing only so we | 1725 | |
2417 | * don't generate false No Link messages. So we will wait here | 1726 | /* We will wait for autoneg to complete or 4.5 seconds to expire. */ |
2418 | * only if the user has set wait_autoneg_complete to 1, which is | 1727 | for (i = PHY_FORCE_TIME; i > 0; i--) { |
2419 | * the default. | 1728 | /* Read the MII Status Register and wait for Auto-Neg Complete bit |
2420 | */ | 1729 | * to be set. |
2421 | if (hw->wait_autoneg_complete) { | 1730 | */ |
2422 | /* We will wait for autoneg to complete. */ | 1731 | ret_val = |
2423 | DEBUGOUT("Waiting for forced speed/duplex link.\n"); | 1732 | e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
2424 | mii_status_reg = 0; | 1733 | if (ret_val) |
2425 | 1734 | return ret_val; | |
2426 | /* We will wait for autoneg to complete or 4.5 seconds to expire. */ | 1735 | |
2427 | for (i = PHY_FORCE_TIME; i > 0; i--) { | 1736 | ret_val = |
2428 | /* Read the MII Status Register and wait for Auto-Neg Complete bit | 1737 | e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
2429 | * to be set. | 1738 | if (ret_val) |
2430 | */ | 1739 | return ret_val; |
2431 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | 1740 | |
2432 | if (ret_val) | 1741 | if (mii_status_reg & MII_SR_LINK_STATUS) |
2433 | return ret_val; | 1742 | break; |
2434 | 1743 | msleep(100); | |
2435 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | 1744 | } |
2436 | if (ret_val) | 1745 | if ((i == 0) && (hw->phy_type == e1000_phy_m88)) { |
2437 | return ret_val; | 1746 | /* We didn't get link. Reset the DSP and wait again for link. */ |
2438 | 1747 | ret_val = e1000_phy_reset_dsp(hw); | |
2439 | if (mii_status_reg & MII_SR_LINK_STATUS) break; | 1748 | if (ret_val) { |
2440 | msleep(100); | 1749 | DEBUGOUT("Error Resetting PHY DSP\n"); |
2441 | } | 1750 | return ret_val; |
2442 | if ((i == 0) && | 1751 | } |
2443 | ((hw->phy_type == e1000_phy_m88) || | 1752 | } |
2444 | (hw->phy_type == e1000_phy_gg82563))) { | 1753 | /* This loop will early-out if the link condition has been met. */ |
2445 | /* We didn't get link. Reset the DSP and wait again for link. */ | 1754 | for (i = PHY_FORCE_TIME; i > 0; i--) { |
2446 | ret_val = e1000_phy_reset_dsp(hw); | 1755 | if (mii_status_reg & MII_SR_LINK_STATUS) |
2447 | if (ret_val) { | 1756 | break; |
2448 | DEBUGOUT("Error Resetting PHY DSP\n"); | 1757 | msleep(100); |
2449 | return ret_val; | 1758 | /* Read the MII Status Register and wait for Auto-Neg Complete bit |
2450 | } | 1759 | * to be set. |
2451 | } | 1760 | */ |
2452 | /* This loop will early-out if the link condition has been met. */ | 1761 | ret_val = |
2453 | for (i = PHY_FORCE_TIME; i > 0; i--) { | 1762 | e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
2454 | if (mii_status_reg & MII_SR_LINK_STATUS) break; | 1763 | if (ret_val) |
2455 | msleep(100); | 1764 | return ret_val; |
2456 | /* Read the MII Status Register and wait for Auto-Neg Complete bit | 1765 | |
2457 | * to be set. | 1766 | ret_val = |
2458 | */ | 1767 | e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
2459 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | 1768 | if (ret_val) |
2460 | if (ret_val) | 1769 | return ret_val; |
2461 | return ret_val; | 1770 | } |
2462 | 1771 | } | |
2463 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | 1772 | |
2464 | if (ret_val) | 1773 | if (hw->phy_type == e1000_phy_m88) { |
2465 | return ret_val; | 1774 | /* Because we reset the PHY above, we need to re-force TX_CLK in the |
2466 | } | 1775 | * Extended PHY Specific Control Register to 25MHz clock. This value |
2467 | } | 1776 | * defaults back to a 2.5MHz clock when the PHY is reset. |
2468 | 1777 | */ | |
2469 | if (hw->phy_type == e1000_phy_m88) { | 1778 | ret_val = |
2470 | /* Because we reset the PHY above, we need to re-force TX_CLK in the | 1779 | e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
2471 | * Extended PHY Specific Control Register to 25MHz clock. This value | 1780 | &phy_data); |
2472 | * defaults back to a 2.5MHz clock when the PHY is reset. | 1781 | if (ret_val) |
2473 | */ | 1782 | return ret_val; |
2474 | ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); | 1783 | |
2475 | if (ret_val) | 1784 | phy_data |= M88E1000_EPSCR_TX_CLK_25; |
2476 | return ret_val; | 1785 | ret_val = |
2477 | 1786 | e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, | |
2478 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | 1787 | phy_data); |
2479 | ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | 1788 | if (ret_val) |
2480 | if (ret_val) | 1789 | return ret_val; |
2481 | return ret_val; | 1790 | |
2482 | 1791 | /* In addition, because of the s/w reset above, we need to enable CRS on | |
2483 | /* In addition, because of the s/w reset above, we need to enable CRS on | 1792 | * TX. This must be set for both full and half duplex operation. |
2484 | * TX. This must be set for both full and half duplex operation. | 1793 | */ |
2485 | */ | 1794 | ret_val = |
2486 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | 1795 | e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
2487 | if (ret_val) | 1796 | if (ret_val) |
2488 | return ret_val; | 1797 | return ret_val; |
2489 | 1798 | ||
2490 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | 1799 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
2491 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | 1800 | ret_val = |
2492 | if (ret_val) | 1801 | e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
2493 | return ret_val; | 1802 | if (ret_val) |
2494 | 1803 | return ret_val; | |
2495 | if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && | 1804 | |
2496 | (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full || | 1805 | if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) |
2497 | hw->forced_speed_duplex == e1000_10_half)) { | 1806 | && (!hw->autoneg) |
2498 | ret_val = e1000_polarity_reversal_workaround(hw); | 1807 | && (hw->forced_speed_duplex == e1000_10_full |
2499 | if (ret_val) | 1808 | || hw->forced_speed_duplex == e1000_10_half)) { |
2500 | return ret_val; | 1809 | ret_val = e1000_polarity_reversal_workaround(hw); |
2501 | } | 1810 | if (ret_val) |
2502 | } else if (hw->phy_type == e1000_phy_gg82563) { | 1811 | return ret_val; |
2503 | /* The TX_CLK of the Extended PHY Specific Control Register defaults | 1812 | } |
2504 | * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if | 1813 | } |
2505 | * we're not in a forced 10/duplex configuration. */ | 1814 | return E1000_SUCCESS; |
2506 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); | ||
2507 | if (ret_val) | ||
2508 | return ret_val; | ||
2509 | |||
2510 | phy_data &= ~GG82563_MSCR_TX_CLK_MASK; | ||
2511 | if ((hw->forced_speed_duplex == e1000_10_full) || | ||
2512 | (hw->forced_speed_duplex == e1000_10_half)) | ||
2513 | phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; | ||
2514 | else | ||
2515 | phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; | ||
2516 | |||
2517 | /* Also due to the reset, we need to enable CRS on Tx. */ | ||
2518 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | ||
2519 | |||
2520 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); | ||
2521 | if (ret_val) | ||
2522 | return ret_val; | ||
2523 | } | ||
2524 | return E1000_SUCCESS; | ||
2525 | } | 1815 | } |
2526 | 1816 | ||
2527 | /****************************************************************************** | 1817 | /** |
2528 | * Sets the collision distance in the Transmit Control register | 1818 | * e1000_config_collision_dist - set collision distance register |
2529 | * | 1819 | * @hw: Struct containing variables accessed by shared code |
2530 | * hw - Struct containing variables accessed by shared code | 1820 | * |
2531 | * | 1821 | * Sets the collision distance in the Transmit Control register. |
2532 | * Link should have been established previously. Reads the speed and duplex | 1822 | * Link should have been established previously. Reads the speed and duplex |
2533 | * information from the Device Status register. | 1823 | * information from the Device Status register. |
2534 | ******************************************************************************/ | 1824 | */ |
2535 | void e1000_config_collision_dist(struct e1000_hw *hw) | 1825 | void e1000_config_collision_dist(struct e1000_hw *hw) |
2536 | { | 1826 | { |
2537 | u32 tctl, coll_dist; | 1827 | u32 tctl, coll_dist; |
2538 | 1828 | ||
2539 | DEBUGFUNC("e1000_config_collision_dist"); | 1829 | DEBUGFUNC("e1000_config_collision_dist"); |
2540 | 1830 | ||
2541 | if (hw->mac_type < e1000_82543) | 1831 | if (hw->mac_type < e1000_82543) |
2542 | coll_dist = E1000_COLLISION_DISTANCE_82542; | 1832 | coll_dist = E1000_COLLISION_DISTANCE_82542; |
2543 | else | 1833 | else |
2544 | coll_dist = E1000_COLLISION_DISTANCE; | 1834 | coll_dist = E1000_COLLISION_DISTANCE; |
2545 | 1835 | ||
2546 | tctl = er32(TCTL); | 1836 | tctl = er32(TCTL); |
2547 | 1837 | ||
2548 | tctl &= ~E1000_TCTL_COLD; | 1838 | tctl &= ~E1000_TCTL_COLD; |
2549 | tctl |= coll_dist << E1000_COLD_SHIFT; | 1839 | tctl |= coll_dist << E1000_COLD_SHIFT; |
2550 | 1840 | ||
2551 | ew32(TCTL, tctl); | 1841 | ew32(TCTL, tctl); |
2552 | E1000_WRITE_FLUSH(); | 1842 | E1000_WRITE_FLUSH(); |
2553 | } | 1843 | } |
2554 | 1844 | ||
2555 | /****************************************************************************** | 1845 | /** |
2556 | * Sets MAC speed and duplex settings to reflect the those in the PHY | 1846 | * e1000_config_mac_to_phy - sync phy and mac settings |
2557 | * | 1847 | * @hw: Struct containing variables accessed by shared code |
2558 | * hw - Struct containing variables accessed by shared code | 1848 | * @mii_reg: data to write to the MII control register |
2559 | * mii_reg - data to write to the MII control register | 1849 | * |
2560 | * | 1850 | * Sets MAC speed and duplex settings to reflect the those in the PHY |
2561 | * The contents of the PHY register containing the needed information need to | 1851 | * The contents of the PHY register containing the needed information need to |
2562 | * be passed in. | 1852 | * be passed in. |
2563 | ******************************************************************************/ | 1853 | */ |
2564 | static s32 e1000_config_mac_to_phy(struct e1000_hw *hw) | 1854 | static s32 e1000_config_mac_to_phy(struct e1000_hw *hw) |
2565 | { | 1855 | { |
2566 | u32 ctrl; | 1856 | u32 ctrl; |
2567 | s32 ret_val; | 1857 | s32 ret_val; |
2568 | u16 phy_data; | 1858 | u16 phy_data; |
2569 | 1859 | ||
2570 | DEBUGFUNC("e1000_config_mac_to_phy"); | 1860 | DEBUGFUNC("e1000_config_mac_to_phy"); |
2571 | 1861 | ||
2572 | /* 82544 or newer MAC, Auto Speed Detection takes care of | 1862 | /* 82544 or newer MAC, Auto Speed Detection takes care of |
2573 | * MAC speed/duplex configuration.*/ | 1863 | * MAC speed/duplex configuration.*/ |
2574 | if (hw->mac_type >= e1000_82544) | 1864 | if (hw->mac_type >= e1000_82544) |
2575 | return E1000_SUCCESS; | 1865 | return E1000_SUCCESS; |
2576 | 1866 | ||
2577 | /* Read the Device Control Register and set the bits to Force Speed | 1867 | /* Read the Device Control Register and set the bits to Force Speed |
2578 | * and Duplex. | 1868 | * and Duplex. |
2579 | */ | 1869 | */ |
2580 | ctrl = er32(CTRL); | 1870 | ctrl = er32(CTRL); |
2581 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | 1871 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
2582 | ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); | 1872 | ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); |
2583 | 1873 | ||
2584 | /* Set up duplex in the Device Control and Transmit Control | 1874 | /* Set up duplex in the Device Control and Transmit Control |
2585 | * registers depending on negotiated values. | 1875 | * registers depending on negotiated values. |
2586 | */ | 1876 | */ |
2587 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); | 1877 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
2588 | if (ret_val) | 1878 | if (ret_val) |
2589 | return ret_val; | 1879 | return ret_val; |
2590 | 1880 | ||
2591 | if (phy_data & M88E1000_PSSR_DPLX) | 1881 | if (phy_data & M88E1000_PSSR_DPLX) |
2592 | ctrl |= E1000_CTRL_FD; | 1882 | ctrl |= E1000_CTRL_FD; |
2593 | else | 1883 | else |
2594 | ctrl &= ~E1000_CTRL_FD; | 1884 | ctrl &= ~E1000_CTRL_FD; |
2595 | 1885 | ||
2596 | e1000_config_collision_dist(hw); | 1886 | e1000_config_collision_dist(hw); |
2597 | 1887 | ||
2598 | /* Set up speed in the Device Control register depending on | 1888 | /* Set up speed in the Device Control register depending on |
2599 | * negotiated values. | 1889 | * negotiated values. |
2600 | */ | 1890 | */ |
2601 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) | 1891 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) |
2602 | ctrl |= E1000_CTRL_SPD_1000; | 1892 | ctrl |= E1000_CTRL_SPD_1000; |
2603 | else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) | 1893 | else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) |
2604 | ctrl |= E1000_CTRL_SPD_100; | 1894 | ctrl |= E1000_CTRL_SPD_100; |
2605 | 1895 | ||
2606 | /* Write the configured values back to the Device Control Reg. */ | 1896 | /* Write the configured values back to the Device Control Reg. */ |
2607 | ew32(CTRL, ctrl); | 1897 | ew32(CTRL, ctrl); |
2608 | return E1000_SUCCESS; | 1898 | return E1000_SUCCESS; |
2609 | } | 1899 | } |
2610 | 1900 | ||
2611 | /****************************************************************************** | 1901 | /** |
2612 | * Forces the MAC's flow control settings. | 1902 | * e1000_force_mac_fc - force flow control settings |
2613 | * | 1903 | * @hw: Struct containing variables accessed by shared code |
2614 | * hw - Struct containing variables accessed by shared code | ||
2615 | * | 1904 | * |
1905 | * Forces the MAC's flow control settings. | ||
2616 | * Sets the TFCE and RFCE bits in the device control register to reflect | 1906 | * Sets the TFCE and RFCE bits in the device control register to reflect |
2617 | * the adapter settings. TFCE and RFCE need to be explicitly set by | 1907 | * the adapter settings. TFCE and RFCE need to be explicitly set by |
2618 | * software when a Copper PHY is used because autonegotiation is managed | 1908 | * software when a Copper PHY is used because autonegotiation is managed |
2619 | * by the PHY rather than the MAC. Software must also configure these | 1909 | * by the PHY rather than the MAC. Software must also configure these |
2620 | * bits when link is forced on a fiber connection. | 1910 | * bits when link is forced on a fiber connection. |
2621 | *****************************************************************************/ | 1911 | */ |
2622 | s32 e1000_force_mac_fc(struct e1000_hw *hw) | 1912 | s32 e1000_force_mac_fc(struct e1000_hw *hw) |
2623 | { | 1913 | { |
2624 | u32 ctrl; | 1914 | u32 ctrl; |
2625 | 1915 | ||
2626 | DEBUGFUNC("e1000_force_mac_fc"); | 1916 | DEBUGFUNC("e1000_force_mac_fc"); |
2627 | 1917 | ||
2628 | /* Get the current configuration of the Device Control Register */ | 1918 | /* Get the current configuration of the Device Control Register */ |
2629 | ctrl = er32(CTRL); | 1919 | ctrl = er32(CTRL); |
2630 | 1920 | ||
2631 | /* Because we didn't get link via the internal auto-negotiation | 1921 | /* Because we didn't get link via the internal auto-negotiation |
2632 | * mechanism (we either forced link or we got link via PHY | 1922 | * mechanism (we either forced link or we got link via PHY |
2633 | * auto-neg), we have to manually enable/disable transmit an | 1923 | * auto-neg), we have to manually enable/disable transmit an |
2634 | * receive flow control. | 1924 | * receive flow control. |
2635 | * | 1925 | * |
2636 | * The "Case" statement below enables/disable flow control | 1926 | * The "Case" statement below enables/disable flow control |
2637 | * according to the "hw->fc" parameter. | 1927 | * according to the "hw->fc" parameter. |
2638 | * | 1928 | * |
2639 | * The possible values of the "fc" parameter are: | 1929 | * The possible values of the "fc" parameter are: |
2640 | * 0: Flow control is completely disabled | 1930 | * 0: Flow control is completely disabled |
2641 | * 1: Rx flow control is enabled (we can receive pause | 1931 | * 1: Rx flow control is enabled (we can receive pause |
2642 | * frames but not send pause frames). | 1932 | * frames but not send pause frames). |
2643 | * 2: Tx flow control is enabled (we can send pause frames | 1933 | * 2: Tx flow control is enabled (we can send pause frames |
2644 | * frames but we do not receive pause frames). | 1934 | * frames but we do not receive pause frames). |
2645 | * 3: Both Rx and TX flow control (symmetric) is enabled. | 1935 | * 3: Both Rx and TX flow control (symmetric) is enabled. |
2646 | * other: No other values should be possible at this point. | 1936 | * other: No other values should be possible at this point. |
2647 | */ | 1937 | */ |
2648 | 1938 | ||
2649 | switch (hw->fc) { | 1939 | switch (hw->fc) { |
2650 | case E1000_FC_NONE: | 1940 | case E1000_FC_NONE: |
2651 | ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); | 1941 | ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); |
2652 | break; | 1942 | break; |
2653 | case E1000_FC_RX_PAUSE: | 1943 | case E1000_FC_RX_PAUSE: |
2654 | ctrl &= (~E1000_CTRL_TFCE); | 1944 | ctrl &= (~E1000_CTRL_TFCE); |
2655 | ctrl |= E1000_CTRL_RFCE; | 1945 | ctrl |= E1000_CTRL_RFCE; |
2656 | break; | 1946 | break; |
2657 | case E1000_FC_TX_PAUSE: | 1947 | case E1000_FC_TX_PAUSE: |
2658 | ctrl &= (~E1000_CTRL_RFCE); | 1948 | ctrl &= (~E1000_CTRL_RFCE); |
2659 | ctrl |= E1000_CTRL_TFCE; | 1949 | ctrl |= E1000_CTRL_TFCE; |
2660 | break; | 1950 | break; |
2661 | case E1000_FC_FULL: | 1951 | case E1000_FC_FULL: |
2662 | ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); | 1952 | ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); |
2663 | break; | 1953 | break; |
2664 | default: | 1954 | default: |
2665 | DEBUGOUT("Flow control param set incorrectly\n"); | 1955 | DEBUGOUT("Flow control param set incorrectly\n"); |
2666 | return -E1000_ERR_CONFIG; | 1956 | return -E1000_ERR_CONFIG; |
2667 | } | 1957 | } |
2668 | 1958 | ||
2669 | /* Disable TX Flow Control for 82542 (rev 2.0) */ | 1959 | /* Disable TX Flow Control for 82542 (rev 2.0) */ |
2670 | if (hw->mac_type == e1000_82542_rev2_0) | 1960 | if (hw->mac_type == e1000_82542_rev2_0) |
2671 | ctrl &= (~E1000_CTRL_TFCE); | 1961 | ctrl &= (~E1000_CTRL_TFCE); |
2672 | 1962 | ||
2673 | ew32(CTRL, ctrl); | 1963 | ew32(CTRL, ctrl); |
2674 | return E1000_SUCCESS; | 1964 | return E1000_SUCCESS; |
2675 | } | 1965 | } |
2676 | 1966 | ||
2677 | /****************************************************************************** | 1967 | /** |
2678 | * Configures flow control settings after link is established | 1968 | * e1000_config_fc_after_link_up - configure flow control after autoneg |
2679 | * | 1969 | * @hw: Struct containing variables accessed by shared code |
2680 | * hw - Struct containing variables accessed by shared code | ||
2681 | * | 1970 | * |
1971 | * Configures flow control settings after link is established | ||
2682 | * Should be called immediately after a valid link has been established. | 1972 | * Should be called immediately after a valid link has been established. |
2683 | * Forces MAC flow control settings if link was forced. When in MII/GMII mode | 1973 | * Forces MAC flow control settings if link was forced. When in MII/GMII mode |
2684 | * and autonegotiation is enabled, the MAC flow control settings will be set | 1974 | * and autonegotiation is enabled, the MAC flow control settings will be set |
2685 | * based on the flow control negotiated by the PHY. In TBI mode, the TFCE | 1975 | * based on the flow control negotiated by the PHY. In TBI mode, the TFCE |
2686 | * and RFCE bits will be automaticaly set to the negotiated flow control mode. | 1976 | * and RFCE bits will be automatically set to the negotiated flow control mode. |
2687 | *****************************************************************************/ | 1977 | */ |
2688 | static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) | 1978 | static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) |
2689 | { | 1979 | { |
2690 | s32 ret_val; | 1980 | s32 ret_val; |
2691 | u16 mii_status_reg; | 1981 | u16 mii_status_reg; |
2692 | u16 mii_nway_adv_reg; | 1982 | u16 mii_nway_adv_reg; |
2693 | u16 mii_nway_lp_ability_reg; | 1983 | u16 mii_nway_lp_ability_reg; |
2694 | u16 speed; | 1984 | u16 speed; |
2695 | u16 duplex; | 1985 | u16 duplex; |
2696 | 1986 | ||
2697 | DEBUGFUNC("e1000_config_fc_after_link_up"); | 1987 | DEBUGFUNC("e1000_config_fc_after_link_up"); |
2698 | 1988 | ||
2699 | /* Check for the case where we have fiber media and auto-neg failed | 1989 | /* Check for the case where we have fiber media and auto-neg failed |
2700 | * so we had to force link. In this case, we need to force the | 1990 | * so we had to force link. In this case, we need to force the |
2701 | * configuration of the MAC to match the "fc" parameter. | 1991 | * configuration of the MAC to match the "fc" parameter. |
2702 | */ | 1992 | */ |
2703 | if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) || | 1993 | if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) |
2704 | ((hw->media_type == e1000_media_type_internal_serdes) && | 1994 | || ((hw->media_type == e1000_media_type_internal_serdes) |
2705 | (hw->autoneg_failed)) || | 1995 | && (hw->autoneg_failed)) |
2706 | ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) { | 1996 | || ((hw->media_type == e1000_media_type_copper) |
2707 | ret_val = e1000_force_mac_fc(hw); | 1997 | && (!hw->autoneg))) { |
2708 | if (ret_val) { | 1998 | ret_val = e1000_force_mac_fc(hw); |
2709 | DEBUGOUT("Error forcing flow control settings\n"); | 1999 | if (ret_val) { |
2710 | return ret_val; | 2000 | DEBUGOUT("Error forcing flow control settings\n"); |
2711 | } | 2001 | return ret_val; |
2712 | } | 2002 | } |
2713 | 2003 | } | |
2714 | /* Check for the case where we have copper media and auto-neg is | 2004 | |
2715 | * enabled. In this case, we need to check and see if Auto-Neg | 2005 | /* Check for the case where we have copper media and auto-neg is |
2716 | * has completed, and if so, how the PHY and link partner has | 2006 | * enabled. In this case, we need to check and see if Auto-Neg |
2717 | * flow control configured. | 2007 | * has completed, and if so, how the PHY and link partner has |
2718 | */ | 2008 | * flow control configured. |
2719 | if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { | 2009 | */ |
2720 | /* Read the MII Status Register and check to see if AutoNeg | 2010 | if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { |
2721 | * has completed. We read this twice because this reg has | 2011 | /* Read the MII Status Register and check to see if AutoNeg |
2722 | * some "sticky" (latched) bits. | 2012 | * has completed. We read this twice because this reg has |
2723 | */ | 2013 | * some "sticky" (latched) bits. |
2724 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | 2014 | */ |
2725 | if (ret_val) | 2015 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
2726 | return ret_val; | 2016 | if (ret_val) |
2727 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | 2017 | return ret_val; |
2728 | if (ret_val) | 2018 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
2729 | return ret_val; | 2019 | if (ret_val) |
2730 | 2020 | return ret_val; | |
2731 | if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { | 2021 | |
2732 | /* The AutoNeg process has completed, so we now need to | 2022 | if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { |
2733 | * read both the Auto Negotiation Advertisement Register | 2023 | /* The AutoNeg process has completed, so we now need to |
2734 | * (Address 4) and the Auto_Negotiation Base Page Ability | 2024 | * read both the Auto Negotiation Advertisement Register |
2735 | * Register (Address 5) to determine how flow control was | 2025 | * (Address 4) and the Auto_Negotiation Base Page Ability |
2736 | * negotiated. | 2026 | * Register (Address 5) to determine how flow control was |
2737 | */ | 2027 | * negotiated. |
2738 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, | 2028 | */ |
2739 | &mii_nway_adv_reg); | 2029 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, |
2740 | if (ret_val) | 2030 | &mii_nway_adv_reg); |
2741 | return ret_val; | 2031 | if (ret_val) |
2742 | ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, | 2032 | return ret_val; |
2743 | &mii_nway_lp_ability_reg); | 2033 | ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, |
2744 | if (ret_val) | 2034 | &mii_nway_lp_ability_reg); |
2745 | return ret_val; | 2035 | if (ret_val) |
2746 | 2036 | return ret_val; | |
2747 | /* Two bits in the Auto Negotiation Advertisement Register | 2037 | |
2748 | * (Address 4) and two bits in the Auto Negotiation Base | 2038 | /* Two bits in the Auto Negotiation Advertisement Register |
2749 | * Page Ability Register (Address 5) determine flow control | 2039 | * (Address 4) and two bits in the Auto Negotiation Base |
2750 | * for both the PHY and the link partner. The following | 2040 | * Page Ability Register (Address 5) determine flow control |
2751 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, | 2041 | * for both the PHY and the link partner. The following |
2752 | * 1999, describes these PAUSE resolution bits and how flow | 2042 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, |
2753 | * control is determined based upon these settings. | 2043 | * 1999, describes these PAUSE resolution bits and how flow |
2754 | * NOTE: DC = Don't Care | 2044 | * control is determined based upon these settings. |
2755 | * | 2045 | * NOTE: DC = Don't Care |
2756 | * LOCAL DEVICE | LINK PARTNER | 2046 | * |
2757 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution | 2047 | * LOCAL DEVICE | LINK PARTNER |
2758 | *-------|---------|-------|---------|-------------------- | 2048 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution |
2759 | * 0 | 0 | DC | DC | E1000_FC_NONE | 2049 | *-------|---------|-------|---------|-------------------- |
2760 | * 0 | 1 | 0 | DC | E1000_FC_NONE | 2050 | * 0 | 0 | DC | DC | E1000_FC_NONE |
2761 | * 0 | 1 | 1 | 0 | E1000_FC_NONE | 2051 | * 0 | 1 | 0 | DC | E1000_FC_NONE |
2762 | * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE | 2052 | * 0 | 1 | 1 | 0 | E1000_FC_NONE |
2763 | * 1 | 0 | 0 | DC | E1000_FC_NONE | 2053 | * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE |
2764 | * 1 | DC | 1 | DC | E1000_FC_FULL | 2054 | * 1 | 0 | 0 | DC | E1000_FC_NONE |
2765 | * 1 | 1 | 0 | 0 | E1000_FC_NONE | 2055 | * 1 | DC | 1 | DC | E1000_FC_FULL |
2766 | * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE | 2056 | * 1 | 1 | 0 | 0 | E1000_FC_NONE |
2767 | * | 2057 | * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE |
2768 | */ | 2058 | * |
2769 | /* Are both PAUSE bits set to 1? If so, this implies | 2059 | */ |
2770 | * Symmetric Flow Control is enabled at both ends. The | 2060 | /* Are both PAUSE bits set to 1? If so, this implies |
2771 | * ASM_DIR bits are irrelevant per the spec. | 2061 | * Symmetric Flow Control is enabled at both ends. The |
2772 | * | 2062 | * ASM_DIR bits are irrelevant per the spec. |
2773 | * For Symmetric Flow Control: | 2063 | * |
2774 | * | 2064 | * For Symmetric Flow Control: |
2775 | * LOCAL DEVICE | LINK PARTNER | 2065 | * |
2776 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | 2066 | * LOCAL DEVICE | LINK PARTNER |
2777 | *-------|---------|-------|---------|-------------------- | 2067 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
2778 | * 1 | DC | 1 | DC | E1000_FC_FULL | 2068 | *-------|---------|-------|---------|-------------------- |
2779 | * | 2069 | * 1 | DC | 1 | DC | E1000_FC_FULL |
2780 | */ | 2070 | * |
2781 | if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && | 2071 | */ |
2782 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { | 2072 | if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
2783 | /* Now we need to check if the user selected RX ONLY | 2073 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { |
2784 | * of pause frames. In this case, we had to advertise | 2074 | /* Now we need to check if the user selected RX ONLY |
2785 | * FULL flow control because we could not advertise RX | 2075 | * of pause frames. In this case, we had to advertise |
2786 | * ONLY. Hence, we must now check to see if we need to | 2076 | * FULL flow control because we could not advertise RX |
2787 | * turn OFF the TRANSMISSION of PAUSE frames. | 2077 | * ONLY. Hence, we must now check to see if we need to |
2788 | */ | 2078 | * turn OFF the TRANSMISSION of PAUSE frames. |
2789 | if (hw->original_fc == E1000_FC_FULL) { | 2079 | */ |
2790 | hw->fc = E1000_FC_FULL; | 2080 | if (hw->original_fc == E1000_FC_FULL) { |
2791 | DEBUGOUT("Flow Control = FULL.\n"); | 2081 | hw->fc = E1000_FC_FULL; |
2792 | } else { | 2082 | DEBUGOUT("Flow Control = FULL.\n"); |
2793 | hw->fc = E1000_FC_RX_PAUSE; | 2083 | } else { |
2794 | DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); | 2084 | hw->fc = E1000_FC_RX_PAUSE; |
2795 | } | 2085 | DEBUGOUT |
2796 | } | 2086 | ("Flow Control = RX PAUSE frames only.\n"); |
2797 | /* For receiving PAUSE frames ONLY. | 2087 | } |
2798 | * | 2088 | } |
2799 | * LOCAL DEVICE | LINK PARTNER | 2089 | /* For receiving PAUSE frames ONLY. |
2800 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | 2090 | * |
2801 | *-------|---------|-------|---------|-------------------- | 2091 | * LOCAL DEVICE | LINK PARTNER |
2802 | * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE | 2092 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
2803 | * | 2093 | *-------|---------|-------|---------|-------------------- |
2804 | */ | 2094 | * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE |
2805 | else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && | 2095 | * |
2806 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && | 2096 | */ |
2807 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && | 2097 | else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && |
2808 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { | 2098 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
2809 | hw->fc = E1000_FC_TX_PAUSE; | 2099 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
2810 | DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); | 2100 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) |
2811 | } | 2101 | { |
2812 | /* For transmitting PAUSE frames ONLY. | 2102 | hw->fc = E1000_FC_TX_PAUSE; |
2813 | * | 2103 | DEBUGOUT |
2814 | * LOCAL DEVICE | LINK PARTNER | 2104 | ("Flow Control = TX PAUSE frames only.\n"); |
2815 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | 2105 | } |
2816 | *-------|---------|-------|---------|-------------------- | 2106 | /* For transmitting PAUSE frames ONLY. |
2817 | * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE | 2107 | * |
2818 | * | 2108 | * LOCAL DEVICE | LINK PARTNER |
2819 | */ | 2109 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
2820 | else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && | 2110 | *-------|---------|-------|---------|-------------------- |
2821 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && | 2111 | * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE |
2822 | !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && | 2112 | * |
2823 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { | 2113 | */ |
2824 | hw->fc = E1000_FC_RX_PAUSE; | 2114 | else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
2825 | DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); | 2115 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
2826 | } | 2116 | !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
2827 | /* Per the IEEE spec, at this point flow control should be | 2117 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) |
2828 | * disabled. However, we want to consider that we could | 2118 | { |
2829 | * be connected to a legacy switch that doesn't advertise | 2119 | hw->fc = E1000_FC_RX_PAUSE; |
2830 | * desired flow control, but can be forced on the link | 2120 | DEBUGOUT |
2831 | * partner. So if we advertised no flow control, that is | 2121 | ("Flow Control = RX PAUSE frames only.\n"); |
2832 | * what we will resolve to. If we advertised some kind of | 2122 | } |
2833 | * receive capability (Rx Pause Only or Full Flow Control) | 2123 | /* Per the IEEE spec, at this point flow control should be |
2834 | * and the link partner advertised none, we will configure | 2124 | * disabled. However, we want to consider that we could |
2835 | * ourselves to enable Rx Flow Control only. We can do | 2125 | * be connected to a legacy switch that doesn't advertise |
2836 | * this safely for two reasons: If the link partner really | 2126 | * desired flow control, but can be forced on the link |
2837 | * didn't want flow control enabled, and we enable Rx, no | 2127 | * partner. So if we advertised no flow control, that is |
2838 | * harm done since we won't be receiving any PAUSE frames | 2128 | * what we will resolve to. If we advertised some kind of |
2839 | * anyway. If the intent on the link partner was to have | 2129 | * receive capability (Rx Pause Only or Full Flow Control) |
2840 | * flow control enabled, then by us enabling RX only, we | 2130 | * and the link partner advertised none, we will configure |
2841 | * can at least receive pause frames and process them. | 2131 | * ourselves to enable Rx Flow Control only. We can do |
2842 | * This is a good idea because in most cases, since we are | 2132 | * this safely for two reasons: If the link partner really |
2843 | * predominantly a server NIC, more times than not we will | 2133 | * didn't want flow control enabled, and we enable Rx, no |
2844 | * be asked to delay transmission of packets than asking | 2134 | * harm done since we won't be receiving any PAUSE frames |
2845 | * our link partner to pause transmission of frames. | 2135 | * anyway. If the intent on the link partner was to have |
2846 | */ | 2136 | * flow control enabled, then by us enabling RX only, we |
2847 | else if ((hw->original_fc == E1000_FC_NONE || | 2137 | * can at least receive pause frames and process them. |
2848 | hw->original_fc == E1000_FC_TX_PAUSE) || | 2138 | * This is a good idea because in most cases, since we are |
2849 | hw->fc_strict_ieee) { | 2139 | * predominantly a server NIC, more times than not we will |
2850 | hw->fc = E1000_FC_NONE; | 2140 | * be asked to delay transmission of packets than asking |
2851 | DEBUGOUT("Flow Control = NONE.\n"); | 2141 | * our link partner to pause transmission of frames. |
2852 | } else { | 2142 | */ |
2853 | hw->fc = E1000_FC_RX_PAUSE; | 2143 | else if ((hw->original_fc == E1000_FC_NONE || |
2854 | DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); | 2144 | hw->original_fc == E1000_FC_TX_PAUSE) || |
2855 | } | 2145 | hw->fc_strict_ieee) { |
2856 | 2146 | hw->fc = E1000_FC_NONE; | |
2857 | /* Now we need to do one last check... If we auto- | 2147 | DEBUGOUT("Flow Control = NONE.\n"); |
2858 | * negotiated to HALF DUPLEX, flow control should not be | 2148 | } else { |
2859 | * enabled per IEEE 802.3 spec. | 2149 | hw->fc = E1000_FC_RX_PAUSE; |
2860 | */ | 2150 | DEBUGOUT |
2861 | ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); | 2151 | ("Flow Control = RX PAUSE frames only.\n"); |
2862 | if (ret_val) { | 2152 | } |
2863 | DEBUGOUT("Error getting link speed and duplex\n"); | 2153 | |
2864 | return ret_val; | 2154 | /* Now we need to do one last check... If we auto- |
2865 | } | 2155 | * negotiated to HALF DUPLEX, flow control should not be |
2866 | 2156 | * enabled per IEEE 802.3 spec. | |
2867 | if (duplex == HALF_DUPLEX) | 2157 | */ |
2868 | hw->fc = E1000_FC_NONE; | 2158 | ret_val = |
2869 | 2159 | e1000_get_speed_and_duplex(hw, &speed, &duplex); | |
2870 | /* Now we call a subroutine to actually force the MAC | 2160 | if (ret_val) { |
2871 | * controller to use the correct flow control settings. | 2161 | DEBUGOUT |
2872 | */ | 2162 | ("Error getting link speed and duplex\n"); |
2873 | ret_val = e1000_force_mac_fc(hw); | 2163 | return ret_val; |
2874 | if (ret_val) { | 2164 | } |
2875 | DEBUGOUT("Error forcing flow control settings\n"); | 2165 | |
2876 | return ret_val; | 2166 | if (duplex == HALF_DUPLEX) |
2877 | } | 2167 | hw->fc = E1000_FC_NONE; |
2878 | } else { | 2168 | |
2879 | DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); | 2169 | /* Now we call a subroutine to actually force the MAC |
2880 | } | 2170 | * controller to use the correct flow control settings. |
2881 | } | 2171 | */ |
2882 | return E1000_SUCCESS; | 2172 | ret_val = e1000_force_mac_fc(hw); |
2173 | if (ret_val) { | ||
2174 | DEBUGOUT | ||
2175 | ("Error forcing flow control settings\n"); | ||
2176 | return ret_val; | ||
2177 | } | ||
2178 | } else { | ||
2179 | DEBUGOUT | ||
2180 | ("Copper PHY and Auto Neg has not completed.\n"); | ||
2181 | } | ||
2182 | } | ||
2183 | return E1000_SUCCESS; | ||
2883 | } | 2184 | } |
2884 | 2185 | ||
2885 | /****************************************************************************** | 2186 | /** |
2886 | * Checks to see if the link status of the hardware has changed. | 2187 | * e1000_check_for_serdes_link_generic - Check for link (Serdes) |
2188 | * @hw: pointer to the HW structure | ||
2887 | * | 2189 | * |
2888 | * hw - Struct containing variables accessed by shared code | 2190 | * Checks for link up on the hardware. If link is not up and we have |
2191 | * a signal, then we need to force link up. | ||
2192 | */ | ||
2193 | static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) | ||
2194 | { | ||
2195 | u32 rxcw; | ||
2196 | u32 ctrl; | ||
2197 | u32 status; | ||
2198 | s32 ret_val = E1000_SUCCESS; | ||
2199 | |||
2200 | DEBUGFUNC("e1000_check_for_serdes_link_generic"); | ||
2201 | |||
2202 | ctrl = er32(CTRL); | ||
2203 | status = er32(STATUS); | ||
2204 | rxcw = er32(RXCW); | ||
2205 | |||
2206 | /* | ||
2207 | * If we don't have link (auto-negotiation failed or link partner | ||
2208 | * cannot auto-negotiate), and our link partner is not trying to | ||
2209 | * auto-negotiate with us (we are receiving idles or data), | ||
2210 | * we need to force link up. We also need to give auto-negotiation | ||
2211 | * time to complete. | ||
2212 | */ | ||
2213 | /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ | ||
2214 | if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { | ||
2215 | if (hw->autoneg_failed == 0) { | ||
2216 | hw->autoneg_failed = 1; | ||
2217 | goto out; | ||
2218 | } | ||
2219 | DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); | ||
2220 | |||
2221 | /* Disable auto-negotiation in the TXCW register */ | ||
2222 | ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE)); | ||
2223 | |||
2224 | /* Force link-up and also force full-duplex. */ | ||
2225 | ctrl = er32(CTRL); | ||
2226 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); | ||
2227 | ew32(CTRL, ctrl); | ||
2228 | |||
2229 | /* Configure Flow Control after forcing link up. */ | ||
2230 | ret_val = e1000_config_fc_after_link_up(hw); | ||
2231 | if (ret_val) { | ||
2232 | DEBUGOUT("Error configuring flow control\n"); | ||
2233 | goto out; | ||
2234 | } | ||
2235 | } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { | ||
2236 | /* | ||
2237 | * If we are forcing link and we are receiving /C/ ordered | ||
2238 | * sets, re-enable auto-negotiation in the TXCW register | ||
2239 | * and disable forced link in the Device Control register | ||
2240 | * in an attempt to auto-negotiate with our link partner. | ||
2241 | */ | ||
2242 | DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); | ||
2243 | ew32(TXCW, hw->txcw); | ||
2244 | ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); | ||
2245 | |||
2246 | hw->serdes_has_link = true; | ||
2247 | } else if (!(E1000_TXCW_ANE & er32(TXCW))) { | ||
2248 | /* | ||
2249 | * If we force link for non-auto-negotiation switch, check | ||
2250 | * link status based on MAC synchronization for internal | ||
2251 | * serdes media type. | ||
2252 | */ | ||
2253 | /* SYNCH bit and IV bit are sticky. */ | ||
2254 | udelay(10); | ||
2255 | rxcw = er32(RXCW); | ||
2256 | if (rxcw & E1000_RXCW_SYNCH) { | ||
2257 | if (!(rxcw & E1000_RXCW_IV)) { | ||
2258 | hw->serdes_has_link = true; | ||
2259 | DEBUGOUT("SERDES: Link up - forced.\n"); | ||
2260 | } | ||
2261 | } else { | ||
2262 | hw->serdes_has_link = false; | ||
2263 | DEBUGOUT("SERDES: Link down - force failed.\n"); | ||
2264 | } | ||
2265 | } | ||
2266 | |||
2267 | if (E1000_TXCW_ANE & er32(TXCW)) { | ||
2268 | status = er32(STATUS); | ||
2269 | if (status & E1000_STATUS_LU) { | ||
2270 | /* SYNCH bit and IV bit are sticky, so reread rxcw. */ | ||
2271 | udelay(10); | ||
2272 | rxcw = er32(RXCW); | ||
2273 | if (rxcw & E1000_RXCW_SYNCH) { | ||
2274 | if (!(rxcw & E1000_RXCW_IV)) { | ||
2275 | hw->serdes_has_link = true; | ||
2276 | DEBUGOUT("SERDES: Link up - autoneg " | ||
2277 | "completed successfully.\n"); | ||
2278 | } else { | ||
2279 | hw->serdes_has_link = false; | ||
2280 | DEBUGOUT("SERDES: Link down - invalid" | ||
2281 | "codewords detected in autoneg.\n"); | ||
2282 | } | ||
2283 | } else { | ||
2284 | hw->serdes_has_link = false; | ||
2285 | DEBUGOUT("SERDES: Link down - no sync.\n"); | ||
2286 | } | ||
2287 | } else { | ||
2288 | hw->serdes_has_link = false; | ||
2289 | DEBUGOUT("SERDES: Link down - autoneg failed\n"); | ||
2290 | } | ||
2291 | } | ||
2292 | |||
2293 | out: | ||
2294 | return ret_val; | ||
2295 | } | ||
2296 | |||
2297 | /** | ||
2298 | * e1000_check_for_link | ||
2299 | * @hw: Struct containing variables accessed by shared code | ||
2889 | * | 2300 | * |
2301 | * Checks to see if the link status of the hardware has changed. | ||
2890 | * Called by any function that needs to check the link status of the adapter. | 2302 | * Called by any function that needs to check the link status of the adapter. |
2891 | *****************************************************************************/ | 2303 | */ |
2892 | s32 e1000_check_for_link(struct e1000_hw *hw) | 2304 | s32 e1000_check_for_link(struct e1000_hw *hw) |
2893 | { | 2305 | { |
2894 | u32 rxcw = 0; | 2306 | u32 rxcw = 0; |
2895 | u32 ctrl; | 2307 | u32 ctrl; |
2896 | u32 status; | 2308 | u32 status; |
2897 | u32 rctl; | 2309 | u32 rctl; |
2898 | u32 icr; | 2310 | u32 icr; |
2899 | u32 signal = 0; | 2311 | u32 signal = 0; |
2900 | s32 ret_val; | 2312 | s32 ret_val; |
2901 | u16 phy_data; | 2313 | u16 phy_data; |
2902 | 2314 | ||
2903 | DEBUGFUNC("e1000_check_for_link"); | 2315 | DEBUGFUNC("e1000_check_for_link"); |
2904 | 2316 | ||
2905 | ctrl = er32(CTRL); | 2317 | ctrl = er32(CTRL); |
2906 | status = er32(STATUS); | 2318 | status = er32(STATUS); |
2907 | 2319 | ||
2908 | /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be | 2320 | /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be |
2909 | * set when the optics detect a signal. On older adapters, it will be | 2321 | * set when the optics detect a signal. On older adapters, it will be |
2910 | * cleared when there is a signal. This applies to fiber media only. | 2322 | * cleared when there is a signal. This applies to fiber media only. |
2911 | */ | 2323 | */ |
2912 | if ((hw->media_type == e1000_media_type_fiber) || | 2324 | if ((hw->media_type == e1000_media_type_fiber) || |
2913 | (hw->media_type == e1000_media_type_internal_serdes)) { | 2325 | (hw->media_type == e1000_media_type_internal_serdes)) { |
2914 | rxcw = er32(RXCW); | 2326 | rxcw = er32(RXCW); |
2915 | 2327 | ||
2916 | if (hw->media_type == e1000_media_type_fiber) { | 2328 | if (hw->media_type == e1000_media_type_fiber) { |
2917 | signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; | 2329 | signal = |
2918 | if (status & E1000_STATUS_LU) | 2330 | (hw->mac_type > |
2919 | hw->get_link_status = false; | 2331 | e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; |
2920 | } | 2332 | if (status & E1000_STATUS_LU) |
2921 | } | 2333 | hw->get_link_status = false; |
2922 | 2334 | } | |
2923 | /* If we have a copper PHY then we only want to go out to the PHY | 2335 | } |
2924 | * registers to see if Auto-Neg has completed and/or if our link | 2336 | |
2925 | * status has changed. The get_link_status flag will be set if we | 2337 | /* If we have a copper PHY then we only want to go out to the PHY |
2926 | * receive a Link Status Change interrupt or we have Rx Sequence | 2338 | * registers to see if Auto-Neg has completed and/or if our link |
2927 | * Errors. | 2339 | * status has changed. The get_link_status flag will be set if we |
2928 | */ | 2340 | * receive a Link Status Change interrupt or we have Rx Sequence |
2929 | if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { | 2341 | * Errors. |
2930 | /* First we want to see if the MII Status Register reports | 2342 | */ |
2931 | * link. If so, then we want to get the current speed/duplex | 2343 | if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { |
2932 | * of the PHY. | 2344 | /* First we want to see if the MII Status Register reports |
2933 | * Read the register twice since the link bit is sticky. | 2345 | * link. If so, then we want to get the current speed/duplex |
2934 | */ | 2346 | * of the PHY. |
2935 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | 2347 | * Read the register twice since the link bit is sticky. |
2936 | if (ret_val) | 2348 | */ |
2937 | return ret_val; | 2349 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
2938 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | 2350 | if (ret_val) |
2939 | if (ret_val) | 2351 | return ret_val; |
2940 | return ret_val; | 2352 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
2941 | 2353 | if (ret_val) | |
2942 | if (phy_data & MII_SR_LINK_STATUS) { | 2354 | return ret_val; |
2943 | hw->get_link_status = false; | 2355 | |
2944 | /* Check if there was DownShift, must be checked immediately after | 2356 | if (phy_data & MII_SR_LINK_STATUS) { |
2945 | * link-up */ | 2357 | hw->get_link_status = false; |
2946 | e1000_check_downshift(hw); | 2358 | /* Check if there was DownShift, must be checked immediately after |
2947 | 2359 | * link-up */ | |
2948 | /* If we are on 82544 or 82543 silicon and speed/duplex | 2360 | e1000_check_downshift(hw); |
2949 | * are forced to 10H or 10F, then we will implement the polarity | 2361 | |
2950 | * reversal workaround. We disable interrupts first, and upon | 2362 | /* If we are on 82544 or 82543 silicon and speed/duplex |
2951 | * returning, place the devices interrupt state to its previous | 2363 | * are forced to 10H or 10F, then we will implement the polarity |
2952 | * value except for the link status change interrupt which will | 2364 | * reversal workaround. We disable interrupts first, and upon |
2953 | * happen due to the execution of this workaround. | 2365 | * returning, place the devices interrupt state to its previous |
2954 | */ | 2366 | * value except for the link status change interrupt which will |
2955 | 2367 | * happen due to the execution of this workaround. | |
2956 | if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && | 2368 | */ |
2957 | (!hw->autoneg) && | 2369 | |
2958 | (hw->forced_speed_duplex == e1000_10_full || | 2370 | if ((hw->mac_type == e1000_82544 |
2959 | hw->forced_speed_duplex == e1000_10_half)) { | 2371 | || hw->mac_type == e1000_82543) && (!hw->autoneg) |
2960 | ew32(IMC, 0xffffffff); | 2372 | && (hw->forced_speed_duplex == e1000_10_full |
2961 | ret_val = e1000_polarity_reversal_workaround(hw); | 2373 | || hw->forced_speed_duplex == e1000_10_half)) { |
2962 | icr = er32(ICR); | 2374 | ew32(IMC, 0xffffffff); |
2963 | ew32(ICS, (icr & ~E1000_ICS_LSC)); | 2375 | ret_val = |
2964 | ew32(IMS, IMS_ENABLE_MASK); | 2376 | e1000_polarity_reversal_workaround(hw); |
2965 | } | 2377 | icr = er32(ICR); |
2966 | 2378 | ew32(ICS, (icr & ~E1000_ICS_LSC)); | |
2967 | } else { | 2379 | ew32(IMS, IMS_ENABLE_MASK); |
2968 | /* No link detected */ | 2380 | } |
2969 | e1000_config_dsp_after_link_change(hw, false); | 2381 | |
2970 | return 0; | 2382 | } else { |
2971 | } | 2383 | /* No link detected */ |
2972 | 2384 | e1000_config_dsp_after_link_change(hw, false); | |
2973 | /* If we are forcing speed/duplex, then we simply return since | 2385 | return 0; |
2974 | * we have already determined whether we have link or not. | 2386 | } |
2975 | */ | 2387 | |
2976 | if (!hw->autoneg) return -E1000_ERR_CONFIG; | 2388 | /* If we are forcing speed/duplex, then we simply return since |
2977 | 2389 | * we have already determined whether we have link or not. | |
2978 | /* optimize the dsp settings for the igp phy */ | 2390 | */ |
2979 | e1000_config_dsp_after_link_change(hw, true); | 2391 | if (!hw->autoneg) |
2980 | 2392 | return -E1000_ERR_CONFIG; | |
2981 | /* We have a M88E1000 PHY and Auto-Neg is enabled. If we | 2393 | |
2982 | * have Si on board that is 82544 or newer, Auto | 2394 | /* optimize the dsp settings for the igp phy */ |
2983 | * Speed Detection takes care of MAC speed/duplex | 2395 | e1000_config_dsp_after_link_change(hw, true); |
2984 | * configuration. So we only need to configure Collision | 2396 | |
2985 | * Distance in the MAC. Otherwise, we need to force | 2397 | /* We have a M88E1000 PHY and Auto-Neg is enabled. If we |
2986 | * speed/duplex on the MAC to the current PHY speed/duplex | 2398 | * have Si on board that is 82544 or newer, Auto |
2987 | * settings. | 2399 | * Speed Detection takes care of MAC speed/duplex |
2988 | */ | 2400 | * configuration. So we only need to configure Collision |
2989 | if (hw->mac_type >= e1000_82544) | 2401 | * Distance in the MAC. Otherwise, we need to force |
2990 | e1000_config_collision_dist(hw); | 2402 | * speed/duplex on the MAC to the current PHY speed/duplex |
2991 | else { | 2403 | * settings. |
2992 | ret_val = e1000_config_mac_to_phy(hw); | 2404 | */ |
2993 | if (ret_val) { | 2405 | if (hw->mac_type >= e1000_82544) |
2994 | DEBUGOUT("Error configuring MAC to PHY settings\n"); | 2406 | e1000_config_collision_dist(hw); |
2995 | return ret_val; | 2407 | else { |
2996 | } | 2408 | ret_val = e1000_config_mac_to_phy(hw); |
2997 | } | 2409 | if (ret_val) { |
2998 | 2410 | DEBUGOUT | |
2999 | /* Configure Flow Control now that Auto-Neg has completed. First, we | 2411 | ("Error configuring MAC to PHY settings\n"); |
3000 | * need to restore the desired flow control settings because we may | 2412 | return ret_val; |
3001 | * have had to re-autoneg with a different link partner. | 2413 | } |
3002 | */ | 2414 | } |
3003 | ret_val = e1000_config_fc_after_link_up(hw); | 2415 | |
3004 | if (ret_val) { | 2416 | /* Configure Flow Control now that Auto-Neg has completed. First, we |
3005 | DEBUGOUT("Error configuring flow control\n"); | 2417 | * need to restore the desired flow control settings because we may |
3006 | return ret_val; | 2418 | * have had to re-autoneg with a different link partner. |
3007 | } | 2419 | */ |
3008 | 2420 | ret_val = e1000_config_fc_after_link_up(hw); | |
3009 | /* At this point we know that we are on copper and we have | 2421 | if (ret_val) { |
3010 | * auto-negotiated link. These are conditions for checking the link | 2422 | DEBUGOUT("Error configuring flow control\n"); |
3011 | * partner capability register. We use the link speed to determine if | 2423 | return ret_val; |
3012 | * TBI compatibility needs to be turned on or off. If the link is not | 2424 | } |
3013 | * at gigabit speed, then TBI compatibility is not needed. If we are | 2425 | |
3014 | * at gigabit speed, we turn on TBI compatibility. | 2426 | /* At this point we know that we are on copper and we have |
3015 | */ | 2427 | * auto-negotiated link. These are conditions for checking the link |
3016 | if (hw->tbi_compatibility_en) { | 2428 | * partner capability register. We use the link speed to determine if |
3017 | u16 speed, duplex; | 2429 | * TBI compatibility needs to be turned on or off. If the link is not |
3018 | ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); | 2430 | * at gigabit speed, then TBI compatibility is not needed. If we are |
3019 | if (ret_val) { | 2431 | * at gigabit speed, we turn on TBI compatibility. |
3020 | DEBUGOUT("Error getting link speed and duplex\n"); | 2432 | */ |
3021 | return ret_val; | 2433 | if (hw->tbi_compatibility_en) { |
3022 | } | 2434 | u16 speed, duplex; |
3023 | if (speed != SPEED_1000) { | 2435 | ret_val = |
3024 | /* If link speed is not set to gigabit speed, we do not need | 2436 | e1000_get_speed_and_duplex(hw, &speed, &duplex); |
3025 | * to enable TBI compatibility. | 2437 | if (ret_val) { |
3026 | */ | 2438 | DEBUGOUT |
3027 | if (hw->tbi_compatibility_on) { | 2439 | ("Error getting link speed and duplex\n"); |
3028 | /* If we previously were in the mode, turn it off. */ | 2440 | return ret_val; |
3029 | rctl = er32(RCTL); | 2441 | } |
3030 | rctl &= ~E1000_RCTL_SBP; | 2442 | if (speed != SPEED_1000) { |
3031 | ew32(RCTL, rctl); | 2443 | /* If link speed is not set to gigabit speed, we do not need |
3032 | hw->tbi_compatibility_on = false; | 2444 | * to enable TBI compatibility. |
3033 | } | 2445 | */ |
3034 | } else { | 2446 | if (hw->tbi_compatibility_on) { |
3035 | /* If TBI compatibility is was previously off, turn it on. For | 2447 | /* If we previously were in the mode, turn it off. */ |
3036 | * compatibility with a TBI link partner, we will store bad | 2448 | rctl = er32(RCTL); |
3037 | * packets. Some frames have an additional byte on the end and | 2449 | rctl &= ~E1000_RCTL_SBP; |
3038 | * will look like CRC errors to the hardware. | 2450 | ew32(RCTL, rctl); |
3039 | */ | 2451 | hw->tbi_compatibility_on = false; |
3040 | if (!hw->tbi_compatibility_on) { | 2452 | } |
3041 | hw->tbi_compatibility_on = true; | 2453 | } else { |
3042 | rctl = er32(RCTL); | 2454 | /* If TBI compatibility is was previously off, turn it on. For |
3043 | rctl |= E1000_RCTL_SBP; | 2455 | * compatibility with a TBI link partner, we will store bad |
3044 | ew32(RCTL, rctl); | 2456 | * packets. Some frames have an additional byte on the end and |
3045 | } | 2457 | * will look like CRC errors to to the hardware. |
3046 | } | 2458 | */ |
3047 | } | 2459 | if (!hw->tbi_compatibility_on) { |
3048 | } | 2460 | hw->tbi_compatibility_on = true; |
3049 | /* If we don't have link (auto-negotiation failed or link partner cannot | 2461 | rctl = er32(RCTL); |
3050 | * auto-negotiate), the cable is plugged in (we have signal), and our | 2462 | rctl |= E1000_RCTL_SBP; |
3051 | * link partner is not trying to auto-negotiate with us (we are receiving | 2463 | ew32(RCTL, rctl); |
3052 | * idles or data), we need to force link up. We also need to give | 2464 | } |
3053 | * auto-negotiation time to complete, in case the cable was just plugged | 2465 | } |
3054 | * in. The autoneg_failed flag does this. | 2466 | } |
3055 | */ | 2467 | } |
3056 | else if ((((hw->media_type == e1000_media_type_fiber) && | 2468 | |
3057 | ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || | 2469 | if ((hw->media_type == e1000_media_type_fiber) || |
3058 | (hw->media_type == e1000_media_type_internal_serdes)) && | 2470 | (hw->media_type == e1000_media_type_internal_serdes)) |
3059 | (!(status & E1000_STATUS_LU)) && | 2471 | e1000_check_for_serdes_link_generic(hw); |
3060 | (!(rxcw & E1000_RXCW_C))) { | 2472 | |
3061 | if (hw->autoneg_failed == 0) { | 2473 | return E1000_SUCCESS; |
3062 | hw->autoneg_failed = 1; | ||
3063 | return 0; | ||
3064 | } | ||
3065 | DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); | ||
3066 | |||
3067 | /* Disable auto-negotiation in the TXCW register */ | ||
3068 | ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE)); | ||
3069 | |||
3070 | /* Force link-up and also force full-duplex. */ | ||
3071 | ctrl = er32(CTRL); | ||
3072 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); | ||
3073 | ew32(CTRL, ctrl); | ||
3074 | |||
3075 | /* Configure Flow Control after forcing link up. */ | ||
3076 | ret_val = e1000_config_fc_after_link_up(hw); | ||
3077 | if (ret_val) { | ||
3078 | DEBUGOUT("Error configuring flow control\n"); | ||
3079 | return ret_val; | ||
3080 | } | ||
3081 | } | ||
3082 | /* If we are forcing link and we are receiving /C/ ordered sets, re-enable | ||
3083 | * auto-negotiation in the TXCW register and disable forced link in the | ||
3084 | * Device Control register in an attempt to auto-negotiate with our link | ||
3085 | * partner. | ||
3086 | */ | ||
3087 | else if (((hw->media_type == e1000_media_type_fiber) || | ||
3088 | (hw->media_type == e1000_media_type_internal_serdes)) && | ||
3089 | (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { | ||
3090 | DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); | ||
3091 | ew32(TXCW, hw->txcw); | ||
3092 | ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); | ||
3093 | |||
3094 | hw->serdes_link_down = false; | ||
3095 | } | ||
3096 | /* If we force link for non-auto-negotiation switch, check link status | ||
3097 | * based on MAC synchronization for internal serdes media type. | ||
3098 | */ | ||
3099 | else if ((hw->media_type == e1000_media_type_internal_serdes) && | ||
3100 | !(E1000_TXCW_ANE & er32(TXCW))) { | ||
3101 | /* SYNCH bit and IV bit are sticky. */ | ||
3102 | udelay(10); | ||
3103 | if (E1000_RXCW_SYNCH & er32(RXCW)) { | ||
3104 | if (!(rxcw & E1000_RXCW_IV)) { | ||
3105 | hw->serdes_link_down = false; | ||
3106 | DEBUGOUT("SERDES: Link is up.\n"); | ||
3107 | } | ||
3108 | } else { | ||
3109 | hw->serdes_link_down = true; | ||
3110 | DEBUGOUT("SERDES: Link is down.\n"); | ||
3111 | } | ||
3112 | } | ||
3113 | if ((hw->media_type == e1000_media_type_internal_serdes) && | ||
3114 | (E1000_TXCW_ANE & er32(TXCW))) { | ||
3115 | hw->serdes_link_down = !(E1000_STATUS_LU & er32(STATUS)); | ||
3116 | } | ||
3117 | return E1000_SUCCESS; | ||
3118 | } | 2474 | } |
3119 | 2475 | ||
3120 | /****************************************************************************** | 2476 | /** |
2477 | * e1000_get_speed_and_duplex | ||
2478 | * @hw: Struct containing variables accessed by shared code | ||
2479 | * @speed: Speed of the connection | ||
2480 | * @duplex: Duplex setting of the connection | ||
2481 | |||
3121 | * Detects the current speed and duplex settings of the hardware. | 2482 | * Detects the current speed and duplex settings of the hardware. |
3122 | * | 2483 | */ |
3123 | * hw - Struct containing variables accessed by shared code | ||
3124 | * speed - Speed of the connection | ||
3125 | * duplex - Duplex setting of the connection | ||
3126 | *****************************************************************************/ | ||
3127 | s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex) | 2484 | s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex) |
3128 | { | 2485 | { |
3129 | u32 status; | 2486 | u32 status; |
3130 | s32 ret_val; | 2487 | s32 ret_val; |
3131 | u16 phy_data; | 2488 | u16 phy_data; |
3132 | 2489 | ||
3133 | DEBUGFUNC("e1000_get_speed_and_duplex"); | 2490 | DEBUGFUNC("e1000_get_speed_and_duplex"); |
3134 | 2491 | ||
3135 | if (hw->mac_type >= e1000_82543) { | 2492 | if (hw->mac_type >= e1000_82543) { |
3136 | status = er32(STATUS); | 2493 | status = er32(STATUS); |
3137 | if (status & E1000_STATUS_SPEED_1000) { | 2494 | if (status & E1000_STATUS_SPEED_1000) { |
3138 | *speed = SPEED_1000; | 2495 | *speed = SPEED_1000; |
3139 | DEBUGOUT("1000 Mbs, "); | 2496 | DEBUGOUT("1000 Mbs, "); |
3140 | } else if (status & E1000_STATUS_SPEED_100) { | 2497 | } else if (status & E1000_STATUS_SPEED_100) { |
3141 | *speed = SPEED_100; | 2498 | *speed = SPEED_100; |
3142 | DEBUGOUT("100 Mbs, "); | 2499 | DEBUGOUT("100 Mbs, "); |
3143 | } else { | 2500 | } else { |
3144 | *speed = SPEED_10; | 2501 | *speed = SPEED_10; |
3145 | DEBUGOUT("10 Mbs, "); | 2502 | DEBUGOUT("10 Mbs, "); |
3146 | } | 2503 | } |
3147 | 2504 | ||
3148 | if (status & E1000_STATUS_FD) { | 2505 | if (status & E1000_STATUS_FD) { |
3149 | *duplex = FULL_DUPLEX; | 2506 | *duplex = FULL_DUPLEX; |
3150 | DEBUGOUT("Full Duplex\n"); | 2507 | DEBUGOUT("Full Duplex\n"); |
3151 | } else { | 2508 | } else { |
3152 | *duplex = HALF_DUPLEX; | 2509 | *duplex = HALF_DUPLEX; |
3153 | DEBUGOUT(" Half Duplex\n"); | 2510 | DEBUGOUT(" Half Duplex\n"); |
3154 | } | 2511 | } |
3155 | } else { | 2512 | } else { |
3156 | DEBUGOUT("1000 Mbs, Full Duplex\n"); | 2513 | DEBUGOUT("1000 Mbs, Full Duplex\n"); |
3157 | *speed = SPEED_1000; | 2514 | *speed = SPEED_1000; |
3158 | *duplex = FULL_DUPLEX; | 2515 | *duplex = FULL_DUPLEX; |
3159 | } | 2516 | } |
3160 | 2517 | ||
3161 | /* IGP01 PHY may advertise full duplex operation after speed downgrade even | 2518 | /* IGP01 PHY may advertise full duplex operation after speed downgrade even |
3162 | * if it is operating at half duplex. Here we set the duplex settings to | 2519 | * if it is operating at half duplex. Here we set the duplex settings to |
3163 | * match the duplex in the link partner's capabilities. | 2520 | * match the duplex in the link partner's capabilities. |
3164 | */ | 2521 | */ |
3165 | if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { | 2522 | if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { |
3166 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); | 2523 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); |
3167 | if (ret_val) | 2524 | if (ret_val) |
3168 | return ret_val; | 2525 | return ret_val; |
3169 | 2526 | ||
3170 | if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) | 2527 | if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) |
3171 | *duplex = HALF_DUPLEX; | 2528 | *duplex = HALF_DUPLEX; |
3172 | else { | 2529 | else { |
3173 | ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); | 2530 | ret_val = |
3174 | if (ret_val) | 2531 | e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); |
3175 | return ret_val; | 2532 | if (ret_val) |
3176 | if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || | 2533 | return ret_val; |
3177 | (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) | 2534 | if ((*speed == SPEED_100 |
3178 | *duplex = HALF_DUPLEX; | 2535 | && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) |
3179 | } | 2536 | || (*speed == SPEED_10 |
3180 | } | 2537 | && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) |
3181 | 2538 | *duplex = HALF_DUPLEX; | |
3182 | if ((hw->mac_type == e1000_80003es2lan) && | 2539 | } |
3183 | (hw->media_type == e1000_media_type_copper)) { | 2540 | } |
3184 | if (*speed == SPEED_1000) | 2541 | |
3185 | ret_val = e1000_configure_kmrn_for_1000(hw); | 2542 | return E1000_SUCCESS; |
3186 | else | ||
3187 | ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); | ||
3188 | if (ret_val) | ||
3189 | return ret_val; | ||
3190 | } | ||
3191 | |||
3192 | if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { | ||
3193 | ret_val = e1000_kumeran_lock_loss_workaround(hw); | ||
3194 | if (ret_val) | ||
3195 | return ret_val; | ||
3196 | } | ||
3197 | |||
3198 | return E1000_SUCCESS; | ||
3199 | } | 2543 | } |
3200 | 2544 | ||
3201 | /****************************************************************************** | 2545 | /** |
3202 | * Blocks until autoneg completes or times out (~4.5 seconds) | 2546 | * e1000_wait_autoneg |
3203 | * | 2547 | * @hw: Struct containing variables accessed by shared code |
3204 | * hw - Struct containing variables accessed by shared code | 2548 | * |
3205 | ******************************************************************************/ | 2549 | * Blocks until autoneg completes or times out (~4.5 seconds) |
2550 | */ | ||
3206 | static s32 e1000_wait_autoneg(struct e1000_hw *hw) | 2551 | static s32 e1000_wait_autoneg(struct e1000_hw *hw) |
3207 | { | 2552 | { |
3208 | s32 ret_val; | 2553 | s32 ret_val; |
3209 | u16 i; | 2554 | u16 i; |
3210 | u16 phy_data; | 2555 | u16 phy_data; |
3211 | 2556 | ||
3212 | DEBUGFUNC("e1000_wait_autoneg"); | 2557 | DEBUGFUNC("e1000_wait_autoneg"); |
3213 | DEBUGOUT("Waiting for Auto-Neg to complete.\n"); | 2558 | DEBUGOUT("Waiting for Auto-Neg to complete.\n"); |
3214 | 2559 | ||
3215 | /* We will wait for autoneg to complete or 4.5 seconds to expire. */ | 2560 | /* We will wait for autoneg to complete or 4.5 seconds to expire. */ |
3216 | for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { | 2561 | for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { |
3217 | /* Read the MII Status Register and wait for Auto-Neg | 2562 | /* Read the MII Status Register and wait for Auto-Neg |
3218 | * Complete bit to be set. | 2563 | * Complete bit to be set. |
3219 | */ | 2564 | */ |
3220 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | 2565 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
3221 | if (ret_val) | 2566 | if (ret_val) |
3222 | return ret_val; | 2567 | return ret_val; |
3223 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | 2568 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
3224 | if (ret_val) | 2569 | if (ret_val) |
3225 | return ret_val; | 2570 | return ret_val; |
3226 | if (phy_data & MII_SR_AUTONEG_COMPLETE) { | 2571 | if (phy_data & MII_SR_AUTONEG_COMPLETE) { |
3227 | return E1000_SUCCESS; | 2572 | return E1000_SUCCESS; |
3228 | } | 2573 | } |
3229 | msleep(100); | 2574 | msleep(100); |
3230 | } | 2575 | } |
3231 | return E1000_SUCCESS; | 2576 | return E1000_SUCCESS; |
3232 | } | 2577 | } |
3233 | 2578 | ||
3234 | /****************************************************************************** | 2579 | /** |
3235 | * Raises the Management Data Clock | 2580 | * e1000_raise_mdi_clk - Raises the Management Data Clock |
3236 | * | 2581 | * @hw: Struct containing variables accessed by shared code |
3237 | * hw - Struct containing variables accessed by shared code | 2582 | * @ctrl: Device control register's current value |
3238 | * ctrl - Device control register's current value | 2583 | */ |
3239 | ******************************************************************************/ | ||
3240 | static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl) | 2584 | static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl) |
3241 | { | 2585 | { |
3242 | /* Raise the clock input to the Management Data Clock (by setting the MDC | 2586 | /* Raise the clock input to the Management Data Clock (by setting the MDC |
3243 | * bit), and then delay 10 microseconds. | 2587 | * bit), and then delay 10 microseconds. |
3244 | */ | 2588 | */ |
3245 | ew32(CTRL, (*ctrl | E1000_CTRL_MDC)); | 2589 | ew32(CTRL, (*ctrl | E1000_CTRL_MDC)); |
3246 | E1000_WRITE_FLUSH(); | 2590 | E1000_WRITE_FLUSH(); |
3247 | udelay(10); | 2591 | udelay(10); |
3248 | } | 2592 | } |
3249 | 2593 | ||
3250 | /****************************************************************************** | 2594 | /** |
3251 | * Lowers the Management Data Clock | 2595 | * e1000_lower_mdi_clk - Lowers the Management Data Clock |
3252 | * | 2596 | * @hw: Struct containing variables accessed by shared code |
3253 | * hw - Struct containing variables accessed by shared code | 2597 | * @ctrl: Device control register's current value |
3254 | * ctrl - Device control register's current value | 2598 | */ |
3255 | ******************************************************************************/ | ||
3256 | static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl) | 2599 | static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl) |
3257 | { | 2600 | { |
3258 | /* Lower the clock input to the Management Data Clock (by clearing the MDC | 2601 | /* Lower the clock input to the Management Data Clock (by clearing the MDC |
3259 | * bit), and then delay 10 microseconds. | 2602 | * bit), and then delay 10 microseconds. |
3260 | */ | 2603 | */ |
3261 | ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC)); | 2604 | ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC)); |
3262 | E1000_WRITE_FLUSH(); | 2605 | E1000_WRITE_FLUSH(); |
3263 | udelay(10); | 2606 | udelay(10); |
3264 | } | 2607 | } |
3265 | 2608 | ||
3266 | /****************************************************************************** | 2609 | /** |
3267 | * Shifts data bits out to the PHY | 2610 | * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY |
3268 | * | 2611 | * @hw: Struct containing variables accessed by shared code |
3269 | * hw - Struct containing variables accessed by shared code | 2612 | * @data: Data to send out to the PHY |
3270 | * data - Data to send out to the PHY | 2613 | * @count: Number of bits to shift out |
3271 | * count - Number of bits to shift out | 2614 | * |
3272 | * | 2615 | * Bits are shifted out in MSB to LSB order. |
3273 | * Bits are shifted out in MSB to LSB order. | 2616 | */ |
3274 | ******************************************************************************/ | ||
3275 | static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count) | 2617 | static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count) |
3276 | { | 2618 | { |
3277 | u32 ctrl; | 2619 | u32 ctrl; |
3278 | u32 mask; | 2620 | u32 mask; |
3279 | |||
3280 | /* We need to shift "count" number of bits out to the PHY. So, the value | ||
3281 | * in the "data" parameter will be shifted out to the PHY one bit at a | ||
3282 | * time. In order to do this, "data" must be broken down into bits. | ||
3283 | */ | ||
3284 | mask = 0x01; | ||
3285 | mask <<= (count - 1); | ||
3286 | |||
3287 | ctrl = er32(CTRL); | ||
3288 | |||
3289 | /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ | ||
3290 | ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); | ||
3291 | |||
3292 | while (mask) { | ||
3293 | /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and | ||
3294 | * then raising and lowering the Management Data Clock. A "0" is | ||
3295 | * shifted out to the PHY by setting the MDIO bit to "0" and then | ||
3296 | * raising and lowering the clock. | ||
3297 | */ | ||
3298 | if (data & mask) | ||
3299 | ctrl |= E1000_CTRL_MDIO; | ||
3300 | else | ||
3301 | ctrl &= ~E1000_CTRL_MDIO; | ||
3302 | |||
3303 | ew32(CTRL, ctrl); | ||
3304 | E1000_WRITE_FLUSH(); | ||
3305 | |||
3306 | udelay(10); | ||
3307 | |||
3308 | e1000_raise_mdi_clk(hw, &ctrl); | ||
3309 | e1000_lower_mdi_clk(hw, &ctrl); | ||
3310 | |||
3311 | mask = mask >> 1; | ||
3312 | } | ||
3313 | } | ||
3314 | |||
3315 | /****************************************************************************** | ||
3316 | * Shifts data bits in from the PHY | ||
3317 | * | ||
3318 | * hw - Struct containing variables accessed by shared code | ||
3319 | * | ||
3320 | * Bits are shifted in in MSB to LSB order. | ||
3321 | ******************************************************************************/ | ||
3322 | static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw) | ||
3323 | { | ||
3324 | u32 ctrl; | ||
3325 | u16 data = 0; | ||
3326 | u8 i; | ||
3327 | |||
3328 | /* In order to read a register from the PHY, we need to shift in a total | ||
3329 | * of 18 bits from the PHY. The first two bit (turnaround) times are used | ||
3330 | * to avoid contention on the MDIO pin when a read operation is performed. | ||
3331 | * These two bits are ignored by us and thrown away. Bits are "shifted in" | ||
3332 | * by raising the input to the Management Data Clock (setting the MDC bit), | ||
3333 | * and then reading the value of the MDIO bit. | ||
3334 | */ | ||
3335 | ctrl = er32(CTRL); | ||
3336 | |||
3337 | /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ | ||
3338 | ctrl &= ~E1000_CTRL_MDIO_DIR; | ||
3339 | ctrl &= ~E1000_CTRL_MDIO; | ||
3340 | |||
3341 | ew32(CTRL, ctrl); | ||
3342 | E1000_WRITE_FLUSH(); | ||
3343 | |||
3344 | /* Raise and Lower the clock before reading in the data. This accounts for | ||
3345 | * the turnaround bits. The first clock occurred when we clocked out the | ||
3346 | * last bit of the Register Address. | ||
3347 | */ | ||
3348 | e1000_raise_mdi_clk(hw, &ctrl); | ||
3349 | e1000_lower_mdi_clk(hw, &ctrl); | ||
3350 | |||
3351 | for (data = 0, i = 0; i < 16; i++) { | ||
3352 | data = data << 1; | ||
3353 | e1000_raise_mdi_clk(hw, &ctrl); | ||
3354 | ctrl = er32(CTRL); | ||
3355 | /* Check to see if we shifted in a "1". */ | ||
3356 | if (ctrl & E1000_CTRL_MDIO) | ||
3357 | data |= 1; | ||
3358 | e1000_lower_mdi_clk(hw, &ctrl); | ||
3359 | } | ||
3360 | |||
3361 | e1000_raise_mdi_clk(hw, &ctrl); | ||
3362 | e1000_lower_mdi_clk(hw, &ctrl); | ||
3363 | |||
3364 | return data; | ||
3365 | } | ||
3366 | |||
3367 | static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask) | ||
3368 | { | ||
3369 | u32 swfw_sync = 0; | ||
3370 | u32 swmask = mask; | ||
3371 | u32 fwmask = mask << 16; | ||
3372 | s32 timeout = 200; | ||
3373 | 2621 | ||
3374 | DEBUGFUNC("e1000_swfw_sync_acquire"); | 2622 | /* We need to shift "count" number of bits out to the PHY. So, the value |
3375 | 2623 | * in the "data" parameter will be shifted out to the PHY one bit at a | |
3376 | if (hw->swfwhw_semaphore_present) | 2624 | * time. In order to do this, "data" must be broken down into bits. |
3377 | return e1000_get_software_flag(hw); | 2625 | */ |
2626 | mask = 0x01; | ||
2627 | mask <<= (count - 1); | ||
3378 | 2628 | ||
3379 | if (!hw->swfw_sync_present) | 2629 | ctrl = er32(CTRL); |
3380 | return e1000_get_hw_eeprom_semaphore(hw); | ||
3381 | 2630 | ||
3382 | while (timeout) { | 2631 | /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ |
3383 | if (e1000_get_hw_eeprom_semaphore(hw)) | 2632 | ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); |
3384 | return -E1000_ERR_SWFW_SYNC; | ||
3385 | 2633 | ||
3386 | swfw_sync = er32(SW_FW_SYNC); | 2634 | while (mask) { |
3387 | if (!(swfw_sync & (fwmask | swmask))) { | 2635 | /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and |
3388 | break; | 2636 | * then raising and lowering the Management Data Clock. A "0" is |
3389 | } | 2637 | * shifted out to the PHY by setting the MDIO bit to "0" and then |
2638 | * raising and lowering the clock. | ||
2639 | */ | ||
2640 | if (data & mask) | ||
2641 | ctrl |= E1000_CTRL_MDIO; | ||
2642 | else | ||
2643 | ctrl &= ~E1000_CTRL_MDIO; | ||
3390 | 2644 | ||
3391 | /* firmware currently using resource (fwmask) */ | 2645 | ew32(CTRL, ctrl); |
3392 | /* or other software thread currently using resource (swmask) */ | 2646 | E1000_WRITE_FLUSH(); |
3393 | e1000_put_hw_eeprom_semaphore(hw); | ||
3394 | mdelay(5); | ||
3395 | timeout--; | ||
3396 | } | ||
3397 | 2647 | ||
3398 | if (!timeout) { | 2648 | udelay(10); |
3399 | DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); | ||
3400 | return -E1000_ERR_SWFW_SYNC; | ||
3401 | } | ||
3402 | 2649 | ||
3403 | swfw_sync |= swmask; | 2650 | e1000_raise_mdi_clk(hw, &ctrl); |
3404 | ew32(SW_FW_SYNC, swfw_sync); | 2651 | e1000_lower_mdi_clk(hw, &ctrl); |
3405 | 2652 | ||
3406 | e1000_put_hw_eeprom_semaphore(hw); | 2653 | mask = mask >> 1; |
3407 | return E1000_SUCCESS; | 2654 | } |
3408 | } | 2655 | } |
3409 | 2656 | ||
3410 | static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask) | 2657 | /** |
2658 | * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY | ||
2659 | * @hw: Struct containing variables accessed by shared code | ||
2660 | * | ||
2661 | * Bits are shifted in in MSB to LSB order. | ||
2662 | */ | ||
2663 | static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw) | ||
3411 | { | 2664 | { |
3412 | u32 swfw_sync; | 2665 | u32 ctrl; |
3413 | u32 swmask = mask; | 2666 | u16 data = 0; |
2667 | u8 i; | ||
3414 | 2668 | ||
3415 | DEBUGFUNC("e1000_swfw_sync_release"); | 2669 | /* In order to read a register from the PHY, we need to shift in a total |
2670 | * of 18 bits from the PHY. The first two bit (turnaround) times are used | ||
2671 | * to avoid contention on the MDIO pin when a read operation is performed. | ||
2672 | * These two bits are ignored by us and thrown away. Bits are "shifted in" | ||
2673 | * by raising the input to the Management Data Clock (setting the MDC bit), | ||
2674 | * and then reading the value of the MDIO bit. | ||
2675 | */ | ||
2676 | ctrl = er32(CTRL); | ||
3416 | 2677 | ||
3417 | if (hw->swfwhw_semaphore_present) { | 2678 | /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ |
3418 | e1000_release_software_flag(hw); | 2679 | ctrl &= ~E1000_CTRL_MDIO_DIR; |
3419 | return; | 2680 | ctrl &= ~E1000_CTRL_MDIO; |
3420 | } | ||
3421 | 2681 | ||
3422 | if (!hw->swfw_sync_present) { | 2682 | ew32(CTRL, ctrl); |
3423 | e1000_put_hw_eeprom_semaphore(hw); | 2683 | E1000_WRITE_FLUSH(); |
3424 | return; | ||
3425 | } | ||
3426 | 2684 | ||
3427 | /* if (e1000_get_hw_eeprom_semaphore(hw)) | 2685 | /* Raise and Lower the clock before reading in the data. This accounts for |
3428 | * return -E1000_ERR_SWFW_SYNC; */ | 2686 | * the turnaround bits. The first clock occurred when we clocked out the |
3429 | while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); | 2687 | * last bit of the Register Address. |
3430 | /* empty */ | 2688 | */ |
2689 | e1000_raise_mdi_clk(hw, &ctrl); | ||
2690 | e1000_lower_mdi_clk(hw, &ctrl); | ||
2691 | |||
2692 | for (data = 0, i = 0; i < 16; i++) { | ||
2693 | data = data << 1; | ||
2694 | e1000_raise_mdi_clk(hw, &ctrl); | ||
2695 | ctrl = er32(CTRL); | ||
2696 | /* Check to see if we shifted in a "1". */ | ||
2697 | if (ctrl & E1000_CTRL_MDIO) | ||
2698 | data |= 1; | ||
2699 | e1000_lower_mdi_clk(hw, &ctrl); | ||
2700 | } | ||
3431 | 2701 | ||
3432 | swfw_sync = er32(SW_FW_SYNC); | 2702 | e1000_raise_mdi_clk(hw, &ctrl); |
3433 | swfw_sync &= ~swmask; | 2703 | e1000_lower_mdi_clk(hw, &ctrl); |
3434 | ew32(SW_FW_SYNC, swfw_sync); | ||
3435 | 2704 | ||
3436 | e1000_put_hw_eeprom_semaphore(hw); | 2705 | return data; |
3437 | } | 2706 | } |
3438 | 2707 | ||
3439 | /***************************************************************************** | 2708 | |
3440 | * Reads the value from a PHY register, if the value is on a specific non zero | 2709 | /** |
3441 | * page, sets the page first. | 2710 | * e1000_read_phy_reg - read a phy register |
3442 | * hw - Struct containing variables accessed by shared code | 2711 | * @hw: Struct containing variables accessed by shared code |
3443 | * reg_addr - address of the PHY register to read | 2712 | * @reg_addr: address of the PHY register to read |
3444 | ******************************************************************************/ | 2713 | * |
2714 | * Reads the value from a PHY register, if the value is on a specific non zero | ||
2715 | * page, sets the page first. | ||
2716 | */ | ||
3445 | s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data) | 2717 | s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data) |
3446 | { | 2718 | { |
3447 | u32 ret_val; | 2719 | u32 ret_val; |
3448 | u16 swfw; | 2720 | |
3449 | 2721 | DEBUGFUNC("e1000_read_phy_reg"); | |
3450 | DEBUGFUNC("e1000_read_phy_reg"); | 2722 | |
3451 | 2723 | if ((hw->phy_type == e1000_phy_igp) && | |
3452 | if ((hw->mac_type == e1000_80003es2lan) && | 2724 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
3453 | (er32(STATUS) & E1000_STATUS_FUNC_1)) { | 2725 | ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, |
3454 | swfw = E1000_SWFW_PHY1_SM; | 2726 | (u16) reg_addr); |
3455 | } else { | 2727 | if (ret_val) |
3456 | swfw = E1000_SWFW_PHY0_SM; | 2728 | return ret_val; |
3457 | } | 2729 | } |
3458 | if (e1000_swfw_sync_acquire(hw, swfw)) | 2730 | |
3459 | return -E1000_ERR_SWFW_SYNC; | 2731 | ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, |
3460 | 2732 | phy_data); | |
3461 | if ((hw->phy_type == e1000_phy_igp || | 2733 | |
3462 | hw->phy_type == e1000_phy_igp_3 || | 2734 | return ret_val; |
3463 | hw->phy_type == e1000_phy_igp_2) && | ||
3464 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { | ||
3465 | ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, | ||
3466 | (u16)reg_addr); | ||
3467 | if (ret_val) { | ||
3468 | e1000_swfw_sync_release(hw, swfw); | ||
3469 | return ret_val; | ||
3470 | } | ||
3471 | } else if (hw->phy_type == e1000_phy_gg82563) { | ||
3472 | if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || | ||
3473 | (hw->mac_type == e1000_80003es2lan)) { | ||
3474 | /* Select Configuration Page */ | ||
3475 | if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { | ||
3476 | ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, | ||
3477 | (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT)); | ||
3478 | } else { | ||
3479 | /* Use Alternative Page Select register to access | ||
3480 | * registers 30 and 31 | ||
3481 | */ | ||
3482 | ret_val = e1000_write_phy_reg_ex(hw, | ||
3483 | GG82563_PHY_PAGE_SELECT_ALT, | ||
3484 | (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT)); | ||
3485 | } | ||
3486 | |||
3487 | if (ret_val) { | ||
3488 | e1000_swfw_sync_release(hw, swfw); | ||
3489 | return ret_val; | ||
3490 | } | ||
3491 | } | ||
3492 | } | ||
3493 | |||
3494 | ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, | ||
3495 | phy_data); | ||
3496 | |||
3497 | e1000_swfw_sync_release(hw, swfw); | ||
3498 | return ret_val; | ||
3499 | } | 2735 | } |
3500 | 2736 | ||
3501 | static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, | 2737 | static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, |
3502 | u16 *phy_data) | 2738 | u16 *phy_data) |
3503 | { | 2739 | { |
3504 | u32 i; | 2740 | u32 i; |
3505 | u32 mdic = 0; | 2741 | u32 mdic = 0; |
3506 | const u32 phy_addr = 1; | 2742 | const u32 phy_addr = 1; |
3507 | 2743 | ||
3508 | DEBUGFUNC("e1000_read_phy_reg_ex"); | 2744 | DEBUGFUNC("e1000_read_phy_reg_ex"); |
3509 | 2745 | ||
3510 | if (reg_addr > MAX_PHY_REG_ADDRESS) { | 2746 | if (reg_addr > MAX_PHY_REG_ADDRESS) { |
3511 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); | 2747 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); |
3512 | return -E1000_ERR_PARAM; | 2748 | return -E1000_ERR_PARAM; |
3513 | } | 2749 | } |
3514 | 2750 | ||
3515 | if (hw->mac_type > e1000_82543) { | 2751 | if (hw->mac_type > e1000_82543) { |
3516 | /* Set up Op-code, Phy Address, and register address in the MDI | 2752 | /* Set up Op-code, Phy Address, and register address in the MDI |
3517 | * Control register. The MAC will take care of interfacing with the | 2753 | * Control register. The MAC will take care of interfacing with the |
3518 | * PHY to retrieve the desired data. | 2754 | * PHY to retrieve the desired data. |
3519 | */ | 2755 | */ |
3520 | mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | | 2756 | mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | |
3521 | (phy_addr << E1000_MDIC_PHY_SHIFT) | | 2757 | (phy_addr << E1000_MDIC_PHY_SHIFT) | |
3522 | (E1000_MDIC_OP_READ)); | 2758 | (E1000_MDIC_OP_READ)); |
3523 | 2759 | ||
3524 | ew32(MDIC, mdic); | 2760 | ew32(MDIC, mdic); |
3525 | 2761 | ||
3526 | /* Poll the ready bit to see if the MDI read completed */ | 2762 | /* Poll the ready bit to see if the MDI read completed */ |
3527 | for (i = 0; i < 64; i++) { | 2763 | for (i = 0; i < 64; i++) { |
3528 | udelay(50); | 2764 | udelay(50); |
3529 | mdic = er32(MDIC); | 2765 | mdic = er32(MDIC); |
3530 | if (mdic & E1000_MDIC_READY) break; | 2766 | if (mdic & E1000_MDIC_READY) |
3531 | } | 2767 | break; |
3532 | if (!(mdic & E1000_MDIC_READY)) { | 2768 | } |
3533 | DEBUGOUT("MDI Read did not complete\n"); | 2769 | if (!(mdic & E1000_MDIC_READY)) { |
3534 | return -E1000_ERR_PHY; | 2770 | DEBUGOUT("MDI Read did not complete\n"); |
3535 | } | 2771 | return -E1000_ERR_PHY; |
3536 | if (mdic & E1000_MDIC_ERROR) { | 2772 | } |
3537 | DEBUGOUT("MDI Error\n"); | 2773 | if (mdic & E1000_MDIC_ERROR) { |
3538 | return -E1000_ERR_PHY; | 2774 | DEBUGOUT("MDI Error\n"); |
3539 | } | 2775 | return -E1000_ERR_PHY; |
3540 | *phy_data = (u16)mdic; | 2776 | } |
3541 | } else { | 2777 | *phy_data = (u16) mdic; |
3542 | /* We must first send a preamble through the MDIO pin to signal the | 2778 | } else { |
3543 | * beginning of an MII instruction. This is done by sending 32 | 2779 | /* We must first send a preamble through the MDIO pin to signal the |
3544 | * consecutive "1" bits. | 2780 | * beginning of an MII instruction. This is done by sending 32 |
3545 | */ | 2781 | * consecutive "1" bits. |
3546 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); | 2782 | */ |
3547 | 2783 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); | |
3548 | /* Now combine the next few fields that are required for a read | 2784 | |
3549 | * operation. We use this method instead of calling the | 2785 | /* Now combine the next few fields that are required for a read |
3550 | * e1000_shift_out_mdi_bits routine five different times. The format of | 2786 | * operation. We use this method instead of calling the |
3551 | * a MII read instruction consists of a shift out of 14 bits and is | 2787 | * e1000_shift_out_mdi_bits routine five different times. The format of |
3552 | * defined as follows: | 2788 | * a MII read instruction consists of a shift out of 14 bits and is |
3553 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> | 2789 | * defined as follows: |
3554 | * followed by a shift in of 18 bits. This first two bits shifted in | 2790 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> |
3555 | * are TurnAround bits used to avoid contention on the MDIO pin when a | 2791 | * followed by a shift in of 18 bits. This first two bits shifted in |
3556 | * READ operation is performed. These two bits are thrown away | 2792 | * are TurnAround bits used to avoid contention on the MDIO pin when a |
3557 | * followed by a shift in of 16 bits which contains the desired data. | 2793 | * READ operation is performed. These two bits are thrown away |
3558 | */ | 2794 | * followed by a shift in of 16 bits which contains the desired data. |
3559 | mdic = ((reg_addr) | (phy_addr << 5) | | 2795 | */ |
3560 | (PHY_OP_READ << 10) | (PHY_SOF << 12)); | 2796 | mdic = ((reg_addr) | (phy_addr << 5) | |
3561 | 2797 | (PHY_OP_READ << 10) | (PHY_SOF << 12)); | |
3562 | e1000_shift_out_mdi_bits(hw, mdic, 14); | 2798 | |
3563 | 2799 | e1000_shift_out_mdi_bits(hw, mdic, 14); | |
3564 | /* Now that we've shifted out the read command to the MII, we need to | 2800 | |
3565 | * "shift in" the 16-bit value (18 total bits) of the requested PHY | 2801 | /* Now that we've shifted out the read command to the MII, we need to |
3566 | * register address. | 2802 | * "shift in" the 16-bit value (18 total bits) of the requested PHY |
3567 | */ | 2803 | * register address. |
3568 | *phy_data = e1000_shift_in_mdi_bits(hw); | 2804 | */ |
3569 | } | 2805 | *phy_data = e1000_shift_in_mdi_bits(hw); |
3570 | return E1000_SUCCESS; | 2806 | } |
2807 | return E1000_SUCCESS; | ||
3571 | } | 2808 | } |
3572 | 2809 | ||
3573 | /****************************************************************************** | 2810 | /** |
3574 | * Writes a value to a PHY register | 2811 | * e1000_write_phy_reg - write a phy register |
3575 | * | 2812 | * |
3576 | * hw - Struct containing variables accessed by shared code | 2813 | * @hw: Struct containing variables accessed by shared code |
3577 | * reg_addr - address of the PHY register to write | 2814 | * @reg_addr: address of the PHY register to write |
3578 | * data - data to write to the PHY | 2815 | * @data: data to write to the PHY |
3579 | ******************************************************************************/ | 2816 | |
2817 | * Writes a value to a PHY register | ||
2818 | */ | ||
3580 | s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data) | 2819 | s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data) |
3581 | { | 2820 | { |
3582 | u32 ret_val; | 2821 | u32 ret_val; |
3583 | u16 swfw; | 2822 | |
3584 | 2823 | DEBUGFUNC("e1000_write_phy_reg"); | |
3585 | DEBUGFUNC("e1000_write_phy_reg"); | 2824 | |
3586 | 2825 | if ((hw->phy_type == e1000_phy_igp) && | |
3587 | if ((hw->mac_type == e1000_80003es2lan) && | 2826 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
3588 | (er32(STATUS) & E1000_STATUS_FUNC_1)) { | 2827 | ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, |
3589 | swfw = E1000_SWFW_PHY1_SM; | 2828 | (u16) reg_addr); |
3590 | } else { | 2829 | if (ret_val) |
3591 | swfw = E1000_SWFW_PHY0_SM; | 2830 | return ret_val; |
3592 | } | 2831 | } |
3593 | if (e1000_swfw_sync_acquire(hw, swfw)) | 2832 | |
3594 | return -E1000_ERR_SWFW_SYNC; | 2833 | ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, |
3595 | 2834 | phy_data); | |
3596 | if ((hw->phy_type == e1000_phy_igp || | 2835 | |
3597 | hw->phy_type == e1000_phy_igp_3 || | 2836 | return ret_val; |
3598 | hw->phy_type == e1000_phy_igp_2) && | ||
3599 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { | ||
3600 | ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, | ||
3601 | (u16)reg_addr); | ||
3602 | if (ret_val) { | ||
3603 | e1000_swfw_sync_release(hw, swfw); | ||
3604 | return ret_val; | ||
3605 | } | ||
3606 | } else if (hw->phy_type == e1000_phy_gg82563) { | ||
3607 | if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || | ||
3608 | (hw->mac_type == e1000_80003es2lan)) { | ||
3609 | /* Select Configuration Page */ | ||
3610 | if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { | ||
3611 | ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, | ||
3612 | (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT)); | ||
3613 | } else { | ||
3614 | /* Use Alternative Page Select register to access | ||
3615 | * registers 30 and 31 | ||
3616 | */ | ||
3617 | ret_val = e1000_write_phy_reg_ex(hw, | ||
3618 | GG82563_PHY_PAGE_SELECT_ALT, | ||
3619 | (u16)((u16)reg_addr >> GG82563_PAGE_SHIFT)); | ||
3620 | } | ||
3621 | |||
3622 | if (ret_val) { | ||
3623 | e1000_swfw_sync_release(hw, swfw); | ||
3624 | return ret_val; | ||
3625 | } | ||
3626 | } | ||
3627 | } | ||
3628 | |||
3629 | ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, | ||
3630 | phy_data); | ||
3631 | |||
3632 | e1000_swfw_sync_release(hw, swfw); | ||
3633 | return ret_val; | ||
3634 | } | 2837 | } |
3635 | 2838 | ||
3636 | static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, | 2839 | static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, |
3637 | u16 phy_data) | 2840 | u16 phy_data) |
3638 | { | 2841 | { |
3639 | u32 i; | 2842 | u32 i; |
3640 | u32 mdic = 0; | 2843 | u32 mdic = 0; |
3641 | const u32 phy_addr = 1; | 2844 | const u32 phy_addr = 1; |
3642 | |||
3643 | DEBUGFUNC("e1000_write_phy_reg_ex"); | ||
3644 | |||
3645 | if (reg_addr > MAX_PHY_REG_ADDRESS) { | ||
3646 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); | ||
3647 | return -E1000_ERR_PARAM; | ||
3648 | } | ||
3649 | |||
3650 | if (hw->mac_type > e1000_82543) { | ||
3651 | /* Set up Op-code, Phy Address, register address, and data intended | ||
3652 | * for the PHY register in the MDI Control register. The MAC will take | ||
3653 | * care of interfacing with the PHY to send the desired data. | ||
3654 | */ | ||
3655 | mdic = (((u32)phy_data) | | ||
3656 | (reg_addr << E1000_MDIC_REG_SHIFT) | | ||
3657 | (phy_addr << E1000_MDIC_PHY_SHIFT) | | ||
3658 | (E1000_MDIC_OP_WRITE)); | ||
3659 | |||
3660 | ew32(MDIC, mdic); | ||
3661 | |||
3662 | /* Poll the ready bit to see if the MDI read completed */ | ||
3663 | for (i = 0; i < 641; i++) { | ||
3664 | udelay(5); | ||
3665 | mdic = er32(MDIC); | ||
3666 | if (mdic & E1000_MDIC_READY) break; | ||
3667 | } | ||
3668 | if (!(mdic & E1000_MDIC_READY)) { | ||
3669 | DEBUGOUT("MDI Write did not complete\n"); | ||
3670 | return -E1000_ERR_PHY; | ||
3671 | } | ||
3672 | } else { | ||
3673 | /* We'll need to use the SW defined pins to shift the write command | ||
3674 | * out to the PHY. We first send a preamble to the PHY to signal the | ||
3675 | * beginning of the MII instruction. This is done by sending 32 | ||
3676 | * consecutive "1" bits. | ||
3677 | */ | ||
3678 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); | ||
3679 | |||
3680 | /* Now combine the remaining required fields that will indicate a | ||
3681 | * write operation. We use this method instead of calling the | ||
3682 | * e1000_shift_out_mdi_bits routine for each field in the command. The | ||
3683 | * format of a MII write instruction is as follows: | ||
3684 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. | ||
3685 | */ | ||
3686 | mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | | ||
3687 | (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); | ||
3688 | mdic <<= 16; | ||
3689 | mdic |= (u32)phy_data; | ||
3690 | |||
3691 | e1000_shift_out_mdi_bits(hw, mdic, 32); | ||
3692 | } | ||
3693 | |||
3694 | return E1000_SUCCESS; | ||
3695 | } | ||
3696 | 2845 | ||
3697 | static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data) | 2846 | DEBUGFUNC("e1000_write_phy_reg_ex"); |
3698 | { | ||
3699 | u32 reg_val; | ||
3700 | u16 swfw; | ||
3701 | DEBUGFUNC("e1000_read_kmrn_reg"); | ||
3702 | |||
3703 | if ((hw->mac_type == e1000_80003es2lan) && | ||
3704 | (er32(STATUS) & E1000_STATUS_FUNC_1)) { | ||
3705 | swfw = E1000_SWFW_PHY1_SM; | ||
3706 | } else { | ||
3707 | swfw = E1000_SWFW_PHY0_SM; | ||
3708 | } | ||
3709 | if (e1000_swfw_sync_acquire(hw, swfw)) | ||
3710 | return -E1000_ERR_SWFW_SYNC; | ||
3711 | |||
3712 | /* Write register address */ | ||
3713 | reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & | ||
3714 | E1000_KUMCTRLSTA_OFFSET) | | ||
3715 | E1000_KUMCTRLSTA_REN; | ||
3716 | ew32(KUMCTRLSTA, reg_val); | ||
3717 | udelay(2); | ||
3718 | |||
3719 | /* Read the data returned */ | ||
3720 | reg_val = er32(KUMCTRLSTA); | ||
3721 | *data = (u16)reg_val; | ||
3722 | |||
3723 | e1000_swfw_sync_release(hw, swfw); | ||
3724 | return E1000_SUCCESS; | ||
3725 | } | ||
3726 | 2847 | ||
3727 | static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data) | 2848 | if (reg_addr > MAX_PHY_REG_ADDRESS) { |
3728 | { | 2849 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); |
3729 | u32 reg_val; | 2850 | return -E1000_ERR_PARAM; |
3730 | u16 swfw; | 2851 | } |
3731 | DEBUGFUNC("e1000_write_kmrn_reg"); | 2852 | |
3732 | 2853 | if (hw->mac_type > e1000_82543) { | |
3733 | if ((hw->mac_type == e1000_80003es2lan) && | 2854 | /* Set up Op-code, Phy Address, register address, and data intended |
3734 | (er32(STATUS) & E1000_STATUS_FUNC_1)) { | 2855 | * for the PHY register in the MDI Control register. The MAC will take |
3735 | swfw = E1000_SWFW_PHY1_SM; | 2856 | * care of interfacing with the PHY to send the desired data. |
3736 | } else { | 2857 | */ |
3737 | swfw = E1000_SWFW_PHY0_SM; | 2858 | mdic = (((u32) phy_data) | |
3738 | } | 2859 | (reg_addr << E1000_MDIC_REG_SHIFT) | |
3739 | if (e1000_swfw_sync_acquire(hw, swfw)) | 2860 | (phy_addr << E1000_MDIC_PHY_SHIFT) | |
3740 | return -E1000_ERR_SWFW_SYNC; | 2861 | (E1000_MDIC_OP_WRITE)); |
3741 | 2862 | ||
3742 | reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & | 2863 | ew32(MDIC, mdic); |
3743 | E1000_KUMCTRLSTA_OFFSET) | data; | 2864 | |
3744 | ew32(KUMCTRLSTA, reg_val); | 2865 | /* Poll the ready bit to see if the MDI read completed */ |
3745 | udelay(2); | 2866 | for (i = 0; i < 641; i++) { |
3746 | 2867 | udelay(5); | |
3747 | e1000_swfw_sync_release(hw, swfw); | 2868 | mdic = er32(MDIC); |
3748 | return E1000_SUCCESS; | 2869 | if (mdic & E1000_MDIC_READY) |
2870 | break; | ||
2871 | } | ||
2872 | if (!(mdic & E1000_MDIC_READY)) { | ||
2873 | DEBUGOUT("MDI Write did not complete\n"); | ||
2874 | return -E1000_ERR_PHY; | ||
2875 | } | ||
2876 | } else { | ||
2877 | /* We'll need to use the SW defined pins to shift the write command | ||
2878 | * out to the PHY. We first send a preamble to the PHY to signal the | ||
2879 | * beginning of the MII instruction. This is done by sending 32 | ||
2880 | * consecutive "1" bits. | ||
2881 | */ | ||
2882 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); | ||
2883 | |||
2884 | /* Now combine the remaining required fields that will indicate a | ||
2885 | * write operation. We use this method instead of calling the | ||
2886 | * e1000_shift_out_mdi_bits routine for each field in the command. The | ||
2887 | * format of a MII write instruction is as follows: | ||
2888 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. | ||
2889 | */ | ||
2890 | mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | | ||
2891 | (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); | ||
2892 | mdic <<= 16; | ||
2893 | mdic |= (u32) phy_data; | ||
2894 | |||
2895 | e1000_shift_out_mdi_bits(hw, mdic, 32); | ||
2896 | } | ||
2897 | |||
2898 | return E1000_SUCCESS; | ||
3749 | } | 2899 | } |
3750 | 2900 | ||
3751 | /****************************************************************************** | 2901 | /** |
3752 | * Returns the PHY to the power-on reset state | 2902 | * e1000_phy_hw_reset - reset the phy, hardware style |
3753 | * | 2903 | * @hw: Struct containing variables accessed by shared code |
3754 | * hw - Struct containing variables accessed by shared code | 2904 | * |
3755 | ******************************************************************************/ | 2905 | * Returns the PHY to the power-on reset state |
2906 | */ | ||
3756 | s32 e1000_phy_hw_reset(struct e1000_hw *hw) | 2907 | s32 e1000_phy_hw_reset(struct e1000_hw *hw) |
3757 | { | 2908 | { |
3758 | u32 ctrl, ctrl_ext; | 2909 | u32 ctrl, ctrl_ext; |
3759 | u32 led_ctrl; | 2910 | u32 led_ctrl; |
3760 | s32 ret_val; | 2911 | s32 ret_val; |
3761 | u16 swfw; | 2912 | |
3762 | 2913 | DEBUGFUNC("e1000_phy_hw_reset"); | |
3763 | DEBUGFUNC("e1000_phy_hw_reset"); | 2914 | |
3764 | 2915 | DEBUGOUT("Resetting Phy...\n"); | |
3765 | /* In the case of the phy reset being blocked, it's not an error, we | 2916 | |
3766 | * simply return success without performing the reset. */ | 2917 | if (hw->mac_type > e1000_82543) { |
3767 | ret_val = e1000_check_phy_reset_block(hw); | 2918 | /* Read the device control register and assert the E1000_CTRL_PHY_RST |
3768 | if (ret_val) | 2919 | * bit. Then, take it out of reset. |
3769 | return E1000_SUCCESS; | 2920 | * For e1000 hardware, we delay for 10ms between the assert |
3770 | 2921 | * and deassert. | |
3771 | DEBUGOUT("Resetting Phy...\n"); | 2922 | */ |
3772 | 2923 | ctrl = er32(CTRL); | |
3773 | if (hw->mac_type > e1000_82543) { | 2924 | ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); |
3774 | if ((hw->mac_type == e1000_80003es2lan) && | 2925 | E1000_WRITE_FLUSH(); |
3775 | (er32(STATUS) & E1000_STATUS_FUNC_1)) { | 2926 | |
3776 | swfw = E1000_SWFW_PHY1_SM; | 2927 | msleep(10); |
3777 | } else { | 2928 | |
3778 | swfw = E1000_SWFW_PHY0_SM; | 2929 | ew32(CTRL, ctrl); |
3779 | } | 2930 | E1000_WRITE_FLUSH(); |
3780 | if (e1000_swfw_sync_acquire(hw, swfw)) { | 2931 | |
3781 | DEBUGOUT("Unable to acquire swfw sync\n"); | 2932 | } else { |
3782 | return -E1000_ERR_SWFW_SYNC; | 2933 | /* Read the Extended Device Control Register, assert the PHY_RESET_DIR |
3783 | } | 2934 | * bit to put the PHY into reset. Then, take it out of reset. |
3784 | /* Read the device control register and assert the E1000_CTRL_PHY_RST | 2935 | */ |
3785 | * bit. Then, take it out of reset. | 2936 | ctrl_ext = er32(CTRL_EXT); |
3786 | * For pre-e1000_82571 hardware, we delay for 10ms between the assert | 2937 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; |
3787 | * and deassert. For e1000_82571 hardware and later, we instead delay | 2938 | ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; |
3788 | * for 50us between and 10ms after the deassertion. | 2939 | ew32(CTRL_EXT, ctrl_ext); |
3789 | */ | 2940 | E1000_WRITE_FLUSH(); |
3790 | ctrl = er32(CTRL); | 2941 | msleep(10); |
3791 | ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); | 2942 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; |
3792 | E1000_WRITE_FLUSH(); | 2943 | ew32(CTRL_EXT, ctrl_ext); |
3793 | 2944 | E1000_WRITE_FLUSH(); | |
3794 | if (hw->mac_type < e1000_82571) | 2945 | } |
3795 | msleep(10); | 2946 | udelay(150); |
3796 | else | 2947 | |
3797 | udelay(100); | 2948 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
3798 | 2949 | /* Configure activity LED after PHY reset */ | |
3799 | ew32(CTRL, ctrl); | 2950 | led_ctrl = er32(LEDCTL); |
3800 | E1000_WRITE_FLUSH(); | 2951 | led_ctrl &= IGP_ACTIVITY_LED_MASK; |
3801 | 2952 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
3802 | if (hw->mac_type >= e1000_82571) | 2953 | ew32(LEDCTL, led_ctrl); |
3803 | mdelay(10); | 2954 | } |
3804 | 2955 | ||
3805 | e1000_swfw_sync_release(hw, swfw); | 2956 | /* Wait for FW to finish PHY configuration. */ |
3806 | } else { | 2957 | ret_val = e1000_get_phy_cfg_done(hw); |
3807 | /* Read the Extended Device Control Register, assert the PHY_RESET_DIR | 2958 | if (ret_val != E1000_SUCCESS) |
3808 | * bit to put the PHY into reset. Then, take it out of reset. | 2959 | return ret_val; |
3809 | */ | 2960 | |
3810 | ctrl_ext = er32(CTRL_EXT); | 2961 | return ret_val; |
3811 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; | ||
3812 | ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; | ||
3813 | ew32(CTRL_EXT, ctrl_ext); | ||
3814 | E1000_WRITE_FLUSH(); | ||
3815 | msleep(10); | ||
3816 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; | ||
3817 | ew32(CTRL_EXT, ctrl_ext); | ||
3818 | E1000_WRITE_FLUSH(); | ||
3819 | } | ||
3820 | udelay(150); | ||
3821 | |||
3822 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { | ||
3823 | /* Configure activity LED after PHY reset */ | ||
3824 | led_ctrl = er32(LEDCTL); | ||
3825 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | ||
3826 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | ||
3827 | ew32(LEDCTL, led_ctrl); | ||
3828 | } | ||
3829 | |||
3830 | /* Wait for FW to finish PHY configuration. */ | ||
3831 | ret_val = e1000_get_phy_cfg_done(hw); | ||
3832 | if (ret_val != E1000_SUCCESS) | ||
3833 | return ret_val; | ||
3834 | e1000_release_software_semaphore(hw); | ||
3835 | |||
3836 | if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3)) | ||
3837 | ret_val = e1000_init_lcd_from_nvm(hw); | ||
3838 | |||
3839 | return ret_val; | ||
3840 | } | 2962 | } |
3841 | 2963 | ||
3842 | /****************************************************************************** | 2964 | /** |
3843 | * Resets the PHY | 2965 | * e1000_phy_reset - reset the phy to commit settings |
3844 | * | 2966 | * @hw: Struct containing variables accessed by shared code |
3845 | * hw - Struct containing variables accessed by shared code | 2967 | * |
3846 | * | 2968 | * Resets the PHY |
3847 | * Sets bit 15 of the MII Control register | 2969 | * Sets bit 15 of the MII Control register |
3848 | ******************************************************************************/ | 2970 | */ |
3849 | s32 e1000_phy_reset(struct e1000_hw *hw) | 2971 | s32 e1000_phy_reset(struct e1000_hw *hw) |
3850 | { | 2972 | { |
3851 | s32 ret_val; | 2973 | s32 ret_val; |
3852 | u16 phy_data; | 2974 | u16 phy_data; |
3853 | |||
3854 | DEBUGFUNC("e1000_phy_reset"); | ||
3855 | |||
3856 | /* In the case of the phy reset being blocked, it's not an error, we | ||
3857 | * simply return success without performing the reset. */ | ||
3858 | ret_val = e1000_check_phy_reset_block(hw); | ||
3859 | if (ret_val) | ||
3860 | return E1000_SUCCESS; | ||
3861 | |||
3862 | switch (hw->phy_type) { | ||
3863 | case e1000_phy_igp: | ||
3864 | case e1000_phy_igp_2: | ||
3865 | case e1000_phy_igp_3: | ||
3866 | case e1000_phy_ife: | ||
3867 | ret_val = e1000_phy_hw_reset(hw); | ||
3868 | if (ret_val) | ||
3869 | return ret_val; | ||
3870 | break; | ||
3871 | default: | ||
3872 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); | ||
3873 | if (ret_val) | ||
3874 | return ret_val; | ||
3875 | |||
3876 | phy_data |= MII_CR_RESET; | ||
3877 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); | ||
3878 | if (ret_val) | ||
3879 | return ret_val; | ||
3880 | |||
3881 | udelay(1); | ||
3882 | break; | ||
3883 | } | ||
3884 | |||
3885 | if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) | ||
3886 | e1000_phy_init_script(hw); | ||
3887 | |||
3888 | return E1000_SUCCESS; | ||
3889 | } | ||
3890 | 2975 | ||
3891 | /****************************************************************************** | 2976 | DEBUGFUNC("e1000_phy_reset"); |
3892 | * Work-around for 82566 power-down: on D3 entry- | ||
3893 | * 1) disable gigabit link | ||
3894 | * 2) write VR power-down enable | ||
3895 | * 3) read it back | ||
3896 | * if successful continue, else issue LCD reset and repeat | ||
3897 | * | ||
3898 | * hw - struct containing variables accessed by shared code | ||
3899 | ******************************************************************************/ | ||
3900 | void e1000_phy_powerdown_workaround(struct e1000_hw *hw) | ||
3901 | { | ||
3902 | s32 reg; | ||
3903 | u16 phy_data; | ||
3904 | s32 retry = 0; | ||
3905 | 2977 | ||
3906 | DEBUGFUNC("e1000_phy_powerdown_workaround"); | 2978 | switch (hw->phy_type) { |
2979 | case e1000_phy_igp: | ||
2980 | ret_val = e1000_phy_hw_reset(hw); | ||
2981 | if (ret_val) | ||
2982 | return ret_val; | ||
2983 | break; | ||
2984 | default: | ||
2985 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); | ||
2986 | if (ret_val) | ||
2987 | return ret_val; | ||
3907 | 2988 | ||
3908 | if (hw->phy_type != e1000_phy_igp_3) | 2989 | phy_data |= MII_CR_RESET; |
3909 | return; | 2990 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); |
2991 | if (ret_val) | ||
2992 | return ret_val; | ||
3910 | 2993 | ||
3911 | do { | 2994 | udelay(1); |
3912 | /* Disable link */ | 2995 | break; |
3913 | reg = er32(PHY_CTRL); | 2996 | } |
3914 | ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | | ||
3915 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); | ||
3916 | 2997 | ||
3917 | /* Write VR power-down enable - bits 9:8 should be 10b */ | 2998 | if (hw->phy_type == e1000_phy_igp) |
3918 | e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); | 2999 | e1000_phy_init_script(hw); |
3919 | phy_data |= (1 << 9); | ||
3920 | phy_data &= ~(1 << 8); | ||
3921 | e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data); | ||
3922 | 3000 | ||
3923 | /* Read it back and test */ | 3001 | return E1000_SUCCESS; |
3924 | e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); | 3002 | } |
3925 | if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry) | ||
3926 | break; | ||
3927 | 3003 | ||
3928 | /* Issue PHY reset and repeat at most one more time */ | 3004 | /** |
3929 | reg = er32(CTRL); | 3005 | * e1000_detect_gig_phy - check the phy type |
3930 | ew32(CTRL, reg | E1000_CTRL_PHY_RST); | 3006 | * @hw: Struct containing variables accessed by shared code |
3931 | retry++; | 3007 | * |
3932 | } while (retry); | 3008 | * Probes the expected PHY address for known PHY IDs |
3009 | */ | ||
3010 | static s32 e1000_detect_gig_phy(struct e1000_hw *hw) | ||
3011 | { | ||
3012 | s32 phy_init_status, ret_val; | ||
3013 | u16 phy_id_high, phy_id_low; | ||
3014 | bool match = false; | ||
3933 | 3015 | ||
3934 | return; | 3016 | DEBUGFUNC("e1000_detect_gig_phy"); |
3935 | 3017 | ||
3936 | } | 3018 | if (hw->phy_id != 0) |
3019 | return E1000_SUCCESS; | ||
3937 | 3020 | ||
3938 | /****************************************************************************** | 3021 | /* Read the PHY ID Registers to identify which PHY is onboard. */ |
3939 | * Work-around for 82566 Kumeran PCS lock loss: | 3022 | ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); |
3940 | * On link status change (i.e. PCI reset, speed change) and link is up and | 3023 | if (ret_val) |
3941 | * speed is gigabit- | 3024 | return ret_val; |
3942 | * 0) if workaround is optionally disabled do nothing | ||
3943 | * 1) wait 1ms for Kumeran link to come up | ||
3944 | * 2) check Kumeran Diagnostic register PCS lock loss bit | ||
3945 | * 3) if not set the link is locked (all is good), otherwise... | ||
3946 | * 4) reset the PHY | ||
3947 | * 5) repeat up to 10 times | ||
3948 | * Note: this is only called for IGP3 copper when speed is 1gb. | ||
3949 | * | ||
3950 | * hw - struct containing variables accessed by shared code | ||
3951 | ******************************************************************************/ | ||
3952 | static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw) | ||
3953 | { | ||
3954 | s32 ret_val; | ||
3955 | s32 reg; | ||
3956 | s32 cnt; | ||
3957 | u16 phy_data; | ||
3958 | |||
3959 | if (hw->kmrn_lock_loss_workaround_disabled) | ||
3960 | return E1000_SUCCESS; | ||
3961 | |||
3962 | /* Make sure link is up before proceeding. If not just return. | ||
3963 | * Attempting this while link is negotiating fouled up link | ||
3964 | * stability */ | ||
3965 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | ||
3966 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | ||
3967 | |||
3968 | if (phy_data & MII_SR_LINK_STATUS) { | ||
3969 | for (cnt = 0; cnt < 10; cnt++) { | ||
3970 | /* read once to clear */ | ||
3971 | ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); | ||
3972 | if (ret_val) | ||
3973 | return ret_val; | ||
3974 | /* and again to get new status */ | ||
3975 | ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); | ||
3976 | if (ret_val) | ||
3977 | return ret_val; | ||
3978 | |||
3979 | /* check for PCS lock */ | ||
3980 | if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) | ||
3981 | return E1000_SUCCESS; | ||
3982 | |||
3983 | /* Issue PHY reset */ | ||
3984 | e1000_phy_hw_reset(hw); | ||
3985 | mdelay(5); | ||
3986 | } | ||
3987 | /* Disable GigE link negotiation */ | ||
3988 | reg = er32(PHY_CTRL); | ||
3989 | ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | | ||
3990 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); | ||
3991 | |||
3992 | /* unable to acquire PCS lock */ | ||
3993 | return E1000_ERR_PHY; | ||
3994 | } | ||
3995 | |||
3996 | return E1000_SUCCESS; | ||
3997 | } | ||
3998 | 3025 | ||
3999 | /****************************************************************************** | 3026 | hw->phy_id = (u32) (phy_id_high << 16); |
4000 | * Probes the expected PHY address for known PHY IDs | 3027 | udelay(20); |
4001 | * | 3028 | ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); |
4002 | * hw - Struct containing variables accessed by shared code | 3029 | if (ret_val) |
4003 | ******************************************************************************/ | 3030 | return ret_val; |
4004 | static s32 e1000_detect_gig_phy(struct e1000_hw *hw) | 3031 | |
4005 | { | 3032 | hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK); |
4006 | s32 phy_init_status, ret_val; | 3033 | hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK; |
4007 | u16 phy_id_high, phy_id_low; | 3034 | |
4008 | bool match = false; | 3035 | switch (hw->mac_type) { |
4009 | 3036 | case e1000_82543: | |
4010 | DEBUGFUNC("e1000_detect_gig_phy"); | 3037 | if (hw->phy_id == M88E1000_E_PHY_ID) |
4011 | 3038 | match = true; | |
4012 | if (hw->phy_id != 0) | 3039 | break; |
4013 | return E1000_SUCCESS; | 3040 | case e1000_82544: |
4014 | 3041 | if (hw->phy_id == M88E1000_I_PHY_ID) | |
4015 | /* The 82571 firmware may still be configuring the PHY. In this | 3042 | match = true; |
4016 | * case, we cannot access the PHY until the configuration is done. So | 3043 | break; |
4017 | * we explicitly set the PHY values. */ | 3044 | case e1000_82540: |
4018 | if (hw->mac_type == e1000_82571 || | 3045 | case e1000_82545: |
4019 | hw->mac_type == e1000_82572) { | 3046 | case e1000_82545_rev_3: |
4020 | hw->phy_id = IGP01E1000_I_PHY_ID; | 3047 | case e1000_82546: |
4021 | hw->phy_type = e1000_phy_igp_2; | 3048 | case e1000_82546_rev_3: |
4022 | return E1000_SUCCESS; | 3049 | if (hw->phy_id == M88E1011_I_PHY_ID) |
4023 | } | 3050 | match = true; |
4024 | 3051 | break; | |
4025 | /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work- | 3052 | case e1000_82541: |
4026 | * around that forces PHY page 0 to be set or the reads fail. The rest of | 3053 | case e1000_82541_rev_2: |
4027 | * the code in this routine uses e1000_read_phy_reg to read the PHY ID. | 3054 | case e1000_82547: |
4028 | * So for ESB-2 we need to have this set so our reads won't fail. If the | 3055 | case e1000_82547_rev_2: |
4029 | * attached PHY is not a e1000_phy_gg82563, the routines below will figure | 3056 | if (hw->phy_id == IGP01E1000_I_PHY_ID) |
4030 | * this out as well. */ | 3057 | match = true; |
4031 | if (hw->mac_type == e1000_80003es2lan) | 3058 | break; |
4032 | hw->phy_type = e1000_phy_gg82563; | 3059 | default: |
4033 | 3060 | DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); | |
4034 | /* Read the PHY ID Registers to identify which PHY is onboard. */ | 3061 | return -E1000_ERR_CONFIG; |
4035 | ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); | 3062 | } |
4036 | if (ret_val) | 3063 | phy_init_status = e1000_set_phy_type(hw); |
4037 | return ret_val; | 3064 | |
4038 | 3065 | if ((match) && (phy_init_status == E1000_SUCCESS)) { | |
4039 | hw->phy_id = (u32)(phy_id_high << 16); | 3066 | DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); |
4040 | udelay(20); | 3067 | return E1000_SUCCESS; |
4041 | ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); | 3068 | } |
4042 | if (ret_val) | 3069 | DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); |
4043 | return ret_val; | 3070 | return -E1000_ERR_PHY; |
4044 | |||
4045 | hw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK); | ||
4046 | hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK; | ||
4047 | |||
4048 | switch (hw->mac_type) { | ||
4049 | case e1000_82543: | ||
4050 | if (hw->phy_id == M88E1000_E_PHY_ID) match = true; | ||
4051 | break; | ||
4052 | case e1000_82544: | ||
4053 | if (hw->phy_id == M88E1000_I_PHY_ID) match = true; | ||
4054 | break; | ||
4055 | case e1000_82540: | ||
4056 | case e1000_82545: | ||
4057 | case e1000_82545_rev_3: | ||
4058 | case e1000_82546: | ||
4059 | case e1000_82546_rev_3: | ||
4060 | if (hw->phy_id == M88E1011_I_PHY_ID) match = true; | ||
4061 | break; | ||
4062 | case e1000_82541: | ||
4063 | case e1000_82541_rev_2: | ||
4064 | case e1000_82547: | ||
4065 | case e1000_82547_rev_2: | ||
4066 | if (hw->phy_id == IGP01E1000_I_PHY_ID) match = true; | ||
4067 | break; | ||
4068 | case e1000_82573: | ||
4069 | if (hw->phy_id == M88E1111_I_PHY_ID) match = true; | ||
4070 | break; | ||
4071 | case e1000_80003es2lan: | ||
4072 | if (hw->phy_id == GG82563_E_PHY_ID) match = true; | ||
4073 | break; | ||
4074 | case e1000_ich8lan: | ||
4075 | if (hw->phy_id == IGP03E1000_E_PHY_ID) match = true; | ||
4076 | if (hw->phy_id == IFE_E_PHY_ID) match = true; | ||
4077 | if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = true; | ||
4078 | if (hw->phy_id == IFE_C_E_PHY_ID) match = true; | ||
4079 | break; | ||
4080 | default: | ||
4081 | DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); | ||
4082 | return -E1000_ERR_CONFIG; | ||
4083 | } | ||
4084 | phy_init_status = e1000_set_phy_type(hw); | ||
4085 | |||
4086 | if ((match) && (phy_init_status == E1000_SUCCESS)) { | ||
4087 | DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); | ||
4088 | return E1000_SUCCESS; | ||
4089 | } | ||
4090 | DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); | ||
4091 | return -E1000_ERR_PHY; | ||
4092 | } | 3071 | } |
4093 | 3072 | ||
4094 | /****************************************************************************** | 3073 | /** |
4095 | * Resets the PHY's DSP | 3074 | * e1000_phy_reset_dsp - reset DSP |
4096 | * | 3075 | * @hw: Struct containing variables accessed by shared code |
4097 | * hw - Struct containing variables accessed by shared code | 3076 | * |
4098 | ******************************************************************************/ | 3077 | * Resets the PHY's DSP |
3078 | */ | ||
4099 | static s32 e1000_phy_reset_dsp(struct e1000_hw *hw) | 3079 | static s32 e1000_phy_reset_dsp(struct e1000_hw *hw) |
4100 | { | 3080 | { |
4101 | s32 ret_val; | 3081 | s32 ret_val; |
4102 | DEBUGFUNC("e1000_phy_reset_dsp"); | 3082 | DEBUGFUNC("e1000_phy_reset_dsp"); |
4103 | 3083 | ||
4104 | do { | 3084 | do { |
4105 | if (hw->phy_type != e1000_phy_gg82563) { | 3085 | ret_val = e1000_write_phy_reg(hw, 29, 0x001d); |
4106 | ret_val = e1000_write_phy_reg(hw, 29, 0x001d); | 3086 | if (ret_val) |
4107 | if (ret_val) break; | 3087 | break; |
4108 | } | 3088 | ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); |
4109 | ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); | 3089 | if (ret_val) |
4110 | if (ret_val) break; | 3090 | break; |
4111 | ret_val = e1000_write_phy_reg(hw, 30, 0x0000); | 3091 | ret_val = e1000_write_phy_reg(hw, 30, 0x0000); |
4112 | if (ret_val) break; | 3092 | if (ret_val) |
4113 | ret_val = E1000_SUCCESS; | 3093 | break; |
4114 | } while (0); | 3094 | ret_val = E1000_SUCCESS; |
4115 | 3095 | } while (0); | |
4116 | return ret_val; | 3096 | |
3097 | return ret_val; | ||
4117 | } | 3098 | } |
4118 | 3099 | ||
4119 | /****************************************************************************** | 3100 | /** |
4120 | * Get PHY information from various PHY registers for igp PHY only. | 3101 | * e1000_phy_igp_get_info - get igp specific registers |
4121 | * | 3102 | * @hw: Struct containing variables accessed by shared code |
4122 | * hw - Struct containing variables accessed by shared code | 3103 | * @phy_info: PHY information structure |
4123 | * phy_info - PHY information structure | 3104 | * |
4124 | ******************************************************************************/ | 3105 | * Get PHY information from various PHY registers for igp PHY only. |
3106 | */ | ||
4125 | static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, | 3107 | static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, |
4126 | struct e1000_phy_info *phy_info) | 3108 | struct e1000_phy_info *phy_info) |
4127 | { | 3109 | { |
4128 | s32 ret_val; | 3110 | s32 ret_val; |
4129 | u16 phy_data, min_length, max_length, average; | 3111 | u16 phy_data, min_length, max_length, average; |
4130 | e1000_rev_polarity polarity; | 3112 | e1000_rev_polarity polarity; |
4131 | 3113 | ||
4132 | DEBUGFUNC("e1000_phy_igp_get_info"); | 3114 | DEBUGFUNC("e1000_phy_igp_get_info"); |
4133 | 3115 | ||
4134 | /* The downshift status is checked only once, after link is established, | 3116 | /* The downshift status is checked only once, after link is established, |
4135 | * and it stored in the hw->speed_downgraded parameter. */ | 3117 | * and it stored in the hw->speed_downgraded parameter. */ |
4136 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; | 3118 | phy_info->downshift = (e1000_downshift) hw->speed_downgraded; |
4137 | 3119 | ||
4138 | /* IGP01E1000 does not need to support it. */ | 3120 | /* IGP01E1000 does not need to support it. */ |
4139 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; | 3121 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; |
4140 | 3122 | ||
4141 | /* IGP01E1000 always correct polarity reversal */ | 3123 | /* IGP01E1000 always correct polarity reversal */ |
4142 | phy_info->polarity_correction = e1000_polarity_reversal_enabled; | 3124 | phy_info->polarity_correction = e1000_polarity_reversal_enabled; |
4143 | 3125 | ||
4144 | /* Check polarity status */ | 3126 | /* Check polarity status */ |
4145 | ret_val = e1000_check_polarity(hw, &polarity); | 3127 | ret_val = e1000_check_polarity(hw, &polarity); |
4146 | if (ret_val) | 3128 | if (ret_val) |
4147 | return ret_val; | 3129 | return ret_val; |
4148 | 3130 | ||
4149 | phy_info->cable_polarity = polarity; | 3131 | phy_info->cable_polarity = polarity; |
4150 | 3132 | ||
4151 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); | 3133 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); |
4152 | if (ret_val) | 3134 | if (ret_val) |
4153 | return ret_val; | 3135 | return ret_val; |
4154 | 3136 | ||
4155 | phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >> | 3137 | phy_info->mdix_mode = |
4156 | IGP01E1000_PSSR_MDIX_SHIFT); | 3138 | (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >> |
4157 | 3139 | IGP01E1000_PSSR_MDIX_SHIFT); | |
4158 | if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == | 3140 | |
4159 | IGP01E1000_PSSR_SPEED_1000MBPS) { | 3141 | if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == |
4160 | /* Local/Remote Receiver Information are only valid at 1000 Mbps */ | 3142 | IGP01E1000_PSSR_SPEED_1000MBPS) { |
4161 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); | 3143 | /* Local/Remote Receiver Information are only valid at 1000 Mbps */ |
4162 | if (ret_val) | 3144 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); |
4163 | return ret_val; | 3145 | if (ret_val) |
4164 | 3146 | return ret_val; | |
4165 | phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> | 3147 | |
4166 | SR_1000T_LOCAL_RX_STATUS_SHIFT) ? | 3148 | phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> |
4167 | e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; | 3149 | SR_1000T_LOCAL_RX_STATUS_SHIFT) ? |
4168 | phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> | 3150 | e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
4169 | SR_1000T_REMOTE_RX_STATUS_SHIFT) ? | 3151 | phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> |
4170 | e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; | 3152 | SR_1000T_REMOTE_RX_STATUS_SHIFT) ? |
4171 | 3153 | e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; | |
4172 | /* Get cable length */ | 3154 | |
4173 | ret_val = e1000_get_cable_length(hw, &min_length, &max_length); | 3155 | /* Get cable length */ |
4174 | if (ret_val) | 3156 | ret_val = e1000_get_cable_length(hw, &min_length, &max_length); |
4175 | return ret_val; | 3157 | if (ret_val) |
4176 | 3158 | return ret_val; | |
4177 | /* Translate to old method */ | 3159 | |
4178 | average = (max_length + min_length) / 2; | 3160 | /* Translate to old method */ |
4179 | 3161 | average = (max_length + min_length) / 2; | |
4180 | if (average <= e1000_igp_cable_length_50) | 3162 | |
4181 | phy_info->cable_length = e1000_cable_length_50; | 3163 | if (average <= e1000_igp_cable_length_50) |
4182 | else if (average <= e1000_igp_cable_length_80) | 3164 | phy_info->cable_length = e1000_cable_length_50; |
4183 | phy_info->cable_length = e1000_cable_length_50_80; | 3165 | else if (average <= e1000_igp_cable_length_80) |
4184 | else if (average <= e1000_igp_cable_length_110) | 3166 | phy_info->cable_length = e1000_cable_length_50_80; |
4185 | phy_info->cable_length = e1000_cable_length_80_110; | 3167 | else if (average <= e1000_igp_cable_length_110) |
4186 | else if (average <= e1000_igp_cable_length_140) | 3168 | phy_info->cable_length = e1000_cable_length_80_110; |
4187 | phy_info->cable_length = e1000_cable_length_110_140; | 3169 | else if (average <= e1000_igp_cable_length_140) |
4188 | else | 3170 | phy_info->cable_length = e1000_cable_length_110_140; |
4189 | phy_info->cable_length = e1000_cable_length_140; | 3171 | else |
4190 | } | 3172 | phy_info->cable_length = e1000_cable_length_140; |
4191 | 3173 | } | |
4192 | return E1000_SUCCESS; | ||
4193 | } | ||
4194 | 3174 | ||
4195 | /****************************************************************************** | 3175 | return E1000_SUCCESS; |
4196 | * Get PHY information from various PHY registers for ife PHY only. | ||
4197 | * | ||
4198 | * hw - Struct containing variables accessed by shared code | ||
4199 | * phy_info - PHY information structure | ||
4200 | ******************************************************************************/ | ||
4201 | static s32 e1000_phy_ife_get_info(struct e1000_hw *hw, | ||
4202 | struct e1000_phy_info *phy_info) | ||
4203 | { | ||
4204 | s32 ret_val; | ||
4205 | u16 phy_data; | ||
4206 | e1000_rev_polarity polarity; | ||
4207 | |||
4208 | DEBUGFUNC("e1000_phy_ife_get_info"); | ||
4209 | |||
4210 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; | ||
4211 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; | ||
4212 | |||
4213 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data); | ||
4214 | if (ret_val) | ||
4215 | return ret_val; | ||
4216 | phy_info->polarity_correction = | ||
4217 | ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >> | ||
4218 | IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ? | ||
4219 | e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; | ||
4220 | |||
4221 | if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) { | ||
4222 | ret_val = e1000_check_polarity(hw, &polarity); | ||
4223 | if (ret_val) | ||
4224 | return ret_val; | ||
4225 | } else { | ||
4226 | /* Polarity is forced. */ | ||
4227 | polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >> | ||
4228 | IFE_PSC_FORCE_POLARITY_SHIFT) ? | ||
4229 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; | ||
4230 | } | ||
4231 | phy_info->cable_polarity = polarity; | ||
4232 | |||
4233 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); | ||
4234 | if (ret_val) | ||
4235 | return ret_val; | ||
4236 | |||
4237 | phy_info->mdix_mode = (e1000_auto_x_mode) | ||
4238 | ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >> | ||
4239 | IFE_PMC_MDIX_MODE_SHIFT); | ||
4240 | |||
4241 | return E1000_SUCCESS; | ||
4242 | } | 3176 | } |
4243 | 3177 | ||
4244 | /****************************************************************************** | 3178 | /** |
4245 | * Get PHY information from various PHY registers fot m88 PHY only. | 3179 | * e1000_phy_m88_get_info - get m88 specific registers |
4246 | * | 3180 | * @hw: Struct containing variables accessed by shared code |
4247 | * hw - Struct containing variables accessed by shared code | 3181 | * @phy_info: PHY information structure |
4248 | * phy_info - PHY information structure | 3182 | * |
4249 | ******************************************************************************/ | 3183 | * Get PHY information from various PHY registers for m88 PHY only. |
3184 | */ | ||
4250 | static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, | 3185 | static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, |
4251 | struct e1000_phy_info *phy_info) | 3186 | struct e1000_phy_info *phy_info) |
4252 | { | 3187 | { |
4253 | s32 ret_val; | 3188 | s32 ret_val; |
4254 | u16 phy_data; | 3189 | u16 phy_data; |
4255 | e1000_rev_polarity polarity; | 3190 | e1000_rev_polarity polarity; |
4256 | 3191 | ||
4257 | DEBUGFUNC("e1000_phy_m88_get_info"); | 3192 | DEBUGFUNC("e1000_phy_m88_get_info"); |
4258 | 3193 | ||
4259 | /* The downshift status is checked only once, after link is established, | 3194 | /* The downshift status is checked only once, after link is established, |
4260 | * and it stored in the hw->speed_downgraded parameter. */ | 3195 | * and it stored in the hw->speed_downgraded parameter. */ |
4261 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; | 3196 | phy_info->downshift = (e1000_downshift) hw->speed_downgraded; |
4262 | 3197 | ||
4263 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | 3198 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
4264 | if (ret_val) | 3199 | if (ret_val) |
4265 | return ret_val; | 3200 | return ret_val; |
4266 | 3201 | ||
4267 | phy_info->extended_10bt_distance = | 3202 | phy_info->extended_10bt_distance = |
4268 | ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> | 3203 | ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> |
4269 | M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? | 3204 | M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? |
4270 | e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal; | 3205 | e1000_10bt_ext_dist_enable_lower : |
4271 | 3206 | e1000_10bt_ext_dist_enable_normal; | |
4272 | phy_info->polarity_correction = | 3207 | |
4273 | ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> | 3208 | phy_info->polarity_correction = |
4274 | M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? | 3209 | ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> |
4275 | e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; | 3210 | M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? |
4276 | 3211 | e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; | |
4277 | /* Check polarity status */ | 3212 | |
4278 | ret_val = e1000_check_polarity(hw, &polarity); | 3213 | /* Check polarity status */ |
4279 | if (ret_val) | 3214 | ret_val = e1000_check_polarity(hw, &polarity); |
4280 | return ret_val; | 3215 | if (ret_val) |
4281 | phy_info->cable_polarity = polarity; | 3216 | return ret_val; |
4282 | 3217 | phy_info->cable_polarity = polarity; | |
4283 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); | 3218 | |
4284 | if (ret_val) | 3219 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
4285 | return ret_val; | 3220 | if (ret_val) |
4286 | 3221 | return ret_val; | |
4287 | phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >> | 3222 | |
4288 | M88E1000_PSSR_MDIX_SHIFT); | 3223 | phy_info->mdix_mode = |
4289 | 3224 | (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >> | |
4290 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { | 3225 | M88E1000_PSSR_MDIX_SHIFT); |
4291 | /* Cable Length Estimation and Local/Remote Receiver Information | 3226 | |
4292 | * are only valid at 1000 Mbps. | 3227 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { |
4293 | */ | 3228 | /* Cable Length Estimation and Local/Remote Receiver Information |
4294 | if (hw->phy_type != e1000_phy_gg82563) { | 3229 | * are only valid at 1000 Mbps. |
4295 | phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> | 3230 | */ |
4296 | M88E1000_PSSR_CABLE_LENGTH_SHIFT); | 3231 | phy_info->cable_length = |
4297 | } else { | 3232 | (e1000_cable_length) ((phy_data & |
4298 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, | 3233 | M88E1000_PSSR_CABLE_LENGTH) >> |
4299 | &phy_data); | 3234 | M88E1000_PSSR_CABLE_LENGTH_SHIFT); |
4300 | if (ret_val) | 3235 | |
4301 | return ret_val; | 3236 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); |
4302 | 3237 | if (ret_val) | |
4303 | phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH); | 3238 | return ret_val; |
4304 | } | 3239 | |
4305 | 3240 | phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> | |
4306 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); | 3241 | SR_1000T_LOCAL_RX_STATUS_SHIFT) ? |
4307 | if (ret_val) | 3242 | e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
4308 | return ret_val; | 3243 | phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> |
4309 | 3244 | SR_1000T_REMOTE_RX_STATUS_SHIFT) ? | |
4310 | phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> | 3245 | e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
4311 | SR_1000T_LOCAL_RX_STATUS_SHIFT) ? | 3246 | |
4312 | e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; | 3247 | } |
4313 | phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> | 3248 | |
4314 | SR_1000T_REMOTE_RX_STATUS_SHIFT) ? | 3249 | return E1000_SUCCESS; |
4315 | e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; | ||
4316 | |||
4317 | } | ||
4318 | |||
4319 | return E1000_SUCCESS; | ||
4320 | } | 3250 | } |
4321 | 3251 | ||
4322 | /****************************************************************************** | 3252 | /** |
4323 | * Get PHY information from various PHY registers | 3253 | * e1000_phy_get_info - request phy info |
4324 | * | 3254 | * @hw: Struct containing variables accessed by shared code |
4325 | * hw - Struct containing variables accessed by shared code | 3255 | * @phy_info: PHY information structure |
4326 | * phy_info - PHY information structure | 3256 | * |
4327 | ******************************************************************************/ | 3257 | * Get PHY information from various PHY registers |
3258 | */ | ||
4328 | s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info) | 3259 | s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info) |
4329 | { | 3260 | { |
4330 | s32 ret_val; | 3261 | s32 ret_val; |
4331 | u16 phy_data; | 3262 | u16 phy_data; |
4332 | 3263 | ||
4333 | DEBUGFUNC("e1000_phy_get_info"); | 3264 | DEBUGFUNC("e1000_phy_get_info"); |
4334 | 3265 | ||
4335 | phy_info->cable_length = e1000_cable_length_undefined; | 3266 | phy_info->cable_length = e1000_cable_length_undefined; |
4336 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; | 3267 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; |
4337 | phy_info->cable_polarity = e1000_rev_polarity_undefined; | 3268 | phy_info->cable_polarity = e1000_rev_polarity_undefined; |
4338 | phy_info->downshift = e1000_downshift_undefined; | 3269 | phy_info->downshift = e1000_downshift_undefined; |
4339 | phy_info->polarity_correction = e1000_polarity_reversal_undefined; | 3270 | phy_info->polarity_correction = e1000_polarity_reversal_undefined; |
4340 | phy_info->mdix_mode = e1000_auto_x_mode_undefined; | 3271 | phy_info->mdix_mode = e1000_auto_x_mode_undefined; |
4341 | phy_info->local_rx = e1000_1000t_rx_status_undefined; | 3272 | phy_info->local_rx = e1000_1000t_rx_status_undefined; |
4342 | phy_info->remote_rx = e1000_1000t_rx_status_undefined; | 3273 | phy_info->remote_rx = e1000_1000t_rx_status_undefined; |
4343 | 3274 | ||
4344 | if (hw->media_type != e1000_media_type_copper) { | 3275 | if (hw->media_type != e1000_media_type_copper) { |
4345 | DEBUGOUT("PHY info is only valid for copper media\n"); | 3276 | DEBUGOUT("PHY info is only valid for copper media\n"); |
4346 | return -E1000_ERR_CONFIG; | 3277 | return -E1000_ERR_CONFIG; |
4347 | } | 3278 | } |
4348 | 3279 | ||
4349 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | 3280 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
4350 | if (ret_val) | 3281 | if (ret_val) |
4351 | return ret_val; | 3282 | return ret_val; |
4352 | 3283 | ||
4353 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | 3284 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
4354 | if (ret_val) | 3285 | if (ret_val) |
4355 | return ret_val; | 3286 | return ret_val; |
4356 | 3287 | ||
4357 | if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { | 3288 | if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { |
4358 | DEBUGOUT("PHY info is only valid if link is up\n"); | 3289 | DEBUGOUT("PHY info is only valid if link is up\n"); |
4359 | return -E1000_ERR_CONFIG; | 3290 | return -E1000_ERR_CONFIG; |
4360 | } | 3291 | } |
4361 | 3292 | ||
4362 | if (hw->phy_type == e1000_phy_igp || | 3293 | if (hw->phy_type == e1000_phy_igp) |
4363 | hw->phy_type == e1000_phy_igp_3 || | 3294 | return e1000_phy_igp_get_info(hw, phy_info); |
4364 | hw->phy_type == e1000_phy_igp_2) | 3295 | else |
4365 | return e1000_phy_igp_get_info(hw, phy_info); | 3296 | return e1000_phy_m88_get_info(hw, phy_info); |
4366 | else if (hw->phy_type == e1000_phy_ife) | ||
4367 | return e1000_phy_ife_get_info(hw, phy_info); | ||
4368 | else | ||
4369 | return e1000_phy_m88_get_info(hw, phy_info); | ||
4370 | } | 3297 | } |
4371 | 3298 | ||
4372 | s32 e1000_validate_mdi_setting(struct e1000_hw *hw) | 3299 | s32 e1000_validate_mdi_setting(struct e1000_hw *hw) |
4373 | { | 3300 | { |
4374 | DEBUGFUNC("e1000_validate_mdi_settings"); | 3301 | DEBUGFUNC("e1000_validate_mdi_settings"); |
4375 | |||
4376 | if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { | ||
4377 | DEBUGOUT("Invalid MDI setting detected\n"); | ||
4378 | hw->mdix = 1; | ||
4379 | return -E1000_ERR_CONFIG; | ||
4380 | } | ||
4381 | return E1000_SUCCESS; | ||
4382 | } | ||
4383 | 3302 | ||
3303 | if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { | ||
3304 | DEBUGOUT("Invalid MDI setting detected\n"); | ||
3305 | hw->mdix = 1; | ||
3306 | return -E1000_ERR_CONFIG; | ||
3307 | } | ||
3308 | return E1000_SUCCESS; | ||
3309 | } | ||
4384 | 3310 | ||
4385 | /****************************************************************************** | 3311 | /** |
4386 | * Sets up eeprom variables in the hw struct. Must be called after mac_type | 3312 | * e1000_init_eeprom_params - initialize sw eeprom vars |
4387 | * is configured. Additionally, if this is ICH8, the flash controller GbE | 3313 | * @hw: Struct containing variables accessed by shared code |
4388 | * registers must be mapped, or this will crash. | ||
4389 | * | 3314 | * |
4390 | * hw - Struct containing variables accessed by shared code | 3315 | * Sets up eeprom variables in the hw struct. Must be called after mac_type |
4391 | *****************************************************************************/ | 3316 | * is configured. |
3317 | */ | ||
4392 | s32 e1000_init_eeprom_params(struct e1000_hw *hw) | 3318 | s32 e1000_init_eeprom_params(struct e1000_hw *hw) |
4393 | { | 3319 | { |
4394 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | 3320 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
4395 | u32 eecd = er32(EECD); | 3321 | u32 eecd = er32(EECD); |
4396 | s32 ret_val = E1000_SUCCESS; | 3322 | s32 ret_val = E1000_SUCCESS; |
4397 | u16 eeprom_size; | 3323 | u16 eeprom_size; |
4398 | 3324 | ||
4399 | DEBUGFUNC("e1000_init_eeprom_params"); | 3325 | DEBUGFUNC("e1000_init_eeprom_params"); |
4400 | 3326 | ||
4401 | switch (hw->mac_type) { | 3327 | switch (hw->mac_type) { |
4402 | case e1000_82542_rev2_0: | 3328 | case e1000_82542_rev2_0: |
4403 | case e1000_82542_rev2_1: | 3329 | case e1000_82542_rev2_1: |
4404 | case e1000_82543: | 3330 | case e1000_82543: |
4405 | case e1000_82544: | 3331 | case e1000_82544: |
4406 | eeprom->type = e1000_eeprom_microwire; | 3332 | eeprom->type = e1000_eeprom_microwire; |
4407 | eeprom->word_size = 64; | 3333 | eeprom->word_size = 64; |
4408 | eeprom->opcode_bits = 3; | 3334 | eeprom->opcode_bits = 3; |
4409 | eeprom->address_bits = 6; | 3335 | eeprom->address_bits = 6; |
4410 | eeprom->delay_usec = 50; | 3336 | eeprom->delay_usec = 50; |
4411 | eeprom->use_eerd = false; | 3337 | break; |
4412 | eeprom->use_eewr = false; | 3338 | case e1000_82540: |
4413 | break; | 3339 | case e1000_82545: |
4414 | case e1000_82540: | 3340 | case e1000_82545_rev_3: |
4415 | case e1000_82545: | 3341 | case e1000_82546: |
4416 | case e1000_82545_rev_3: | 3342 | case e1000_82546_rev_3: |
4417 | case e1000_82546: | 3343 | eeprom->type = e1000_eeprom_microwire; |
4418 | case e1000_82546_rev_3: | 3344 | eeprom->opcode_bits = 3; |
4419 | eeprom->type = e1000_eeprom_microwire; | 3345 | eeprom->delay_usec = 50; |
4420 | eeprom->opcode_bits = 3; | 3346 | if (eecd & E1000_EECD_SIZE) { |
4421 | eeprom->delay_usec = 50; | 3347 | eeprom->word_size = 256; |
4422 | if (eecd & E1000_EECD_SIZE) { | 3348 | eeprom->address_bits = 8; |
4423 | eeprom->word_size = 256; | 3349 | } else { |
4424 | eeprom->address_bits = 8; | 3350 | eeprom->word_size = 64; |
4425 | } else { | 3351 | eeprom->address_bits = 6; |
4426 | eeprom->word_size = 64; | 3352 | } |
4427 | eeprom->address_bits = 6; | 3353 | break; |
4428 | } | 3354 | case e1000_82541: |
4429 | eeprom->use_eerd = false; | 3355 | case e1000_82541_rev_2: |
4430 | eeprom->use_eewr = false; | 3356 | case e1000_82547: |
4431 | break; | 3357 | case e1000_82547_rev_2: |
4432 | case e1000_82541: | 3358 | if (eecd & E1000_EECD_TYPE) { |
4433 | case e1000_82541_rev_2: | 3359 | eeprom->type = e1000_eeprom_spi; |
4434 | case e1000_82547: | 3360 | eeprom->opcode_bits = 8; |
4435 | case e1000_82547_rev_2: | 3361 | eeprom->delay_usec = 1; |
4436 | if (eecd & E1000_EECD_TYPE) { | 3362 | if (eecd & E1000_EECD_ADDR_BITS) { |
4437 | eeprom->type = e1000_eeprom_spi; | 3363 | eeprom->page_size = 32; |
4438 | eeprom->opcode_bits = 8; | 3364 | eeprom->address_bits = 16; |
4439 | eeprom->delay_usec = 1; | 3365 | } else { |
4440 | if (eecd & E1000_EECD_ADDR_BITS) { | 3366 | eeprom->page_size = 8; |
4441 | eeprom->page_size = 32; | 3367 | eeprom->address_bits = 8; |
4442 | eeprom->address_bits = 16; | 3368 | } |
4443 | } else { | 3369 | } else { |
4444 | eeprom->page_size = 8; | 3370 | eeprom->type = e1000_eeprom_microwire; |
4445 | eeprom->address_bits = 8; | 3371 | eeprom->opcode_bits = 3; |
4446 | } | 3372 | eeprom->delay_usec = 50; |
4447 | } else { | 3373 | if (eecd & E1000_EECD_ADDR_BITS) { |
4448 | eeprom->type = e1000_eeprom_microwire; | 3374 | eeprom->word_size = 256; |
4449 | eeprom->opcode_bits = 3; | 3375 | eeprom->address_bits = 8; |
4450 | eeprom->delay_usec = 50; | 3376 | } else { |
4451 | if (eecd & E1000_EECD_ADDR_BITS) { | 3377 | eeprom->word_size = 64; |
4452 | eeprom->word_size = 256; | 3378 | eeprom->address_bits = 6; |
4453 | eeprom->address_bits = 8; | 3379 | } |
4454 | } else { | 3380 | } |
4455 | eeprom->word_size = 64; | 3381 | break; |
4456 | eeprom->address_bits = 6; | 3382 | default: |
4457 | } | 3383 | break; |
4458 | } | 3384 | } |
4459 | eeprom->use_eerd = false; | 3385 | |
4460 | eeprom->use_eewr = false; | 3386 | if (eeprom->type == e1000_eeprom_spi) { |
4461 | break; | 3387 | /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to |
4462 | case e1000_82571: | 3388 | * 32KB (incremented by powers of 2). |
4463 | case e1000_82572: | 3389 | */ |
4464 | eeprom->type = e1000_eeprom_spi; | 3390 | /* Set to default value for initial eeprom read. */ |
4465 | eeprom->opcode_bits = 8; | 3391 | eeprom->word_size = 64; |
4466 | eeprom->delay_usec = 1; | 3392 | ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); |
4467 | if (eecd & E1000_EECD_ADDR_BITS) { | 3393 | if (ret_val) |
4468 | eeprom->page_size = 32; | 3394 | return ret_val; |
4469 | eeprom->address_bits = 16; | 3395 | eeprom_size = |
4470 | } else { | 3396 | (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; |
4471 | eeprom->page_size = 8; | 3397 | /* 256B eeprom size was not supported in earlier hardware, so we |
4472 | eeprom->address_bits = 8; | 3398 | * bump eeprom_size up one to ensure that "1" (which maps to 256B) |
4473 | } | 3399 | * is never the result used in the shifting logic below. */ |
4474 | eeprom->use_eerd = false; | 3400 | if (eeprom_size) |
4475 | eeprom->use_eewr = false; | 3401 | eeprom_size++; |
4476 | break; | 3402 | |
4477 | case e1000_82573: | 3403 | eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); |
4478 | eeprom->type = e1000_eeprom_spi; | 3404 | } |
4479 | eeprom->opcode_bits = 8; | 3405 | return ret_val; |
4480 | eeprom->delay_usec = 1; | ||
4481 | if (eecd & E1000_EECD_ADDR_BITS) { | ||
4482 | eeprom->page_size = 32; | ||
4483 | eeprom->address_bits = 16; | ||
4484 | } else { | ||
4485 | eeprom->page_size = 8; | ||
4486 | eeprom->address_bits = 8; | ||
4487 | } | ||
4488 | eeprom->use_eerd = true; | ||
4489 | eeprom->use_eewr = true; | ||
4490 | if (!e1000_is_onboard_nvm_eeprom(hw)) { | ||
4491 | eeprom->type = e1000_eeprom_flash; | ||
4492 | eeprom->word_size = 2048; | ||
4493 | |||
4494 | /* Ensure that the Autonomous FLASH update bit is cleared due to | ||
4495 | * Flash update issue on parts which use a FLASH for NVM. */ | ||
4496 | eecd &= ~E1000_EECD_AUPDEN; | ||
4497 | ew32(EECD, eecd); | ||
4498 | } | ||
4499 | break; | ||
4500 | case e1000_80003es2lan: | ||
4501 | eeprom->type = e1000_eeprom_spi; | ||
4502 | eeprom->opcode_bits = 8; | ||
4503 | eeprom->delay_usec = 1; | ||
4504 | if (eecd & E1000_EECD_ADDR_BITS) { | ||
4505 | eeprom->page_size = 32; | ||
4506 | eeprom->address_bits = 16; | ||
4507 | } else { | ||
4508 | eeprom->page_size = 8; | ||
4509 | eeprom->address_bits = 8; | ||
4510 | } | ||
4511 | eeprom->use_eerd = true; | ||
4512 | eeprom->use_eewr = false; | ||
4513 | break; | ||
4514 | case e1000_ich8lan: | ||
4515 | { | ||
4516 | s32 i = 0; | ||
4517 | u32 flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); | ||
4518 | |||
4519 | eeprom->type = e1000_eeprom_ich8; | ||
4520 | eeprom->use_eerd = false; | ||
4521 | eeprom->use_eewr = false; | ||
4522 | eeprom->word_size = E1000_SHADOW_RAM_WORDS; | ||
4523 | |||
4524 | /* Zero the shadow RAM structure. But don't load it from NVM | ||
4525 | * so as to save time for driver init */ | ||
4526 | if (hw->eeprom_shadow_ram != NULL) { | ||
4527 | for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { | ||
4528 | hw->eeprom_shadow_ram[i].modified = false; | ||
4529 | hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; | ||
4530 | } | ||
4531 | } | ||
4532 | |||
4533 | hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * | ||
4534 | ICH_FLASH_SECTOR_SIZE; | ||
4535 | |||
4536 | hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1; | ||
4537 | hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); | ||
4538 | |||
4539 | hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; | ||
4540 | |||
4541 | hw->flash_bank_size /= 2 * sizeof(u16); | ||
4542 | |||
4543 | break; | ||
4544 | } | ||
4545 | default: | ||
4546 | break; | ||
4547 | } | ||
4548 | |||
4549 | if (eeprom->type == e1000_eeprom_spi) { | ||
4550 | /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to | ||
4551 | * 32KB (incremented by powers of 2). | ||
4552 | */ | ||
4553 | if (hw->mac_type <= e1000_82547_rev_2) { | ||
4554 | /* Set to default value for initial eeprom read. */ | ||
4555 | eeprom->word_size = 64; | ||
4556 | ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); | ||
4557 | if (ret_val) | ||
4558 | return ret_val; | ||
4559 | eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; | ||
4560 | /* 256B eeprom size was not supported in earlier hardware, so we | ||
4561 | * bump eeprom_size up one to ensure that "1" (which maps to 256B) | ||
4562 | * is never the result used in the shifting logic below. */ | ||
4563 | if (eeprom_size) | ||
4564 | eeprom_size++; | ||
4565 | } else { | ||
4566 | eeprom_size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> | ||
4567 | E1000_EECD_SIZE_EX_SHIFT); | ||
4568 | } | ||
4569 | |||
4570 | eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); | ||
4571 | } | ||
4572 | return ret_val; | ||
4573 | } | 3406 | } |
4574 | 3407 | ||
4575 | /****************************************************************************** | 3408 | /** |
4576 | * Raises the EEPROM's clock input. | 3409 | * e1000_raise_ee_clk - Raises the EEPROM's clock input. |
4577 | * | 3410 | * @hw: Struct containing variables accessed by shared code |
4578 | * hw - Struct containing variables accessed by shared code | 3411 | * @eecd: EECD's current value |
4579 | * eecd - EECD's current value | 3412 | */ |
4580 | *****************************************************************************/ | ||
4581 | static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd) | 3413 | static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd) |
4582 | { | 3414 | { |
4583 | /* Raise the clock input to the EEPROM (by setting the SK bit), and then | 3415 | /* Raise the clock input to the EEPROM (by setting the SK bit), and then |
4584 | * wait <delay> microseconds. | 3416 | * wait <delay> microseconds. |
4585 | */ | 3417 | */ |
4586 | *eecd = *eecd | E1000_EECD_SK; | 3418 | *eecd = *eecd | E1000_EECD_SK; |
4587 | ew32(EECD, *eecd); | 3419 | ew32(EECD, *eecd); |
4588 | E1000_WRITE_FLUSH(); | 3420 | E1000_WRITE_FLUSH(); |
4589 | udelay(hw->eeprom.delay_usec); | 3421 | udelay(hw->eeprom.delay_usec); |
4590 | } | 3422 | } |
4591 | 3423 | ||
4592 | /****************************************************************************** | 3424 | /** |
4593 | * Lowers the EEPROM's clock input. | 3425 | * e1000_lower_ee_clk - Lowers the EEPROM's clock input. |
4594 | * | 3426 | * @hw: Struct containing variables accessed by shared code |
4595 | * hw - Struct containing variables accessed by shared code | 3427 | * @eecd: EECD's current value |
4596 | * eecd - EECD's current value | 3428 | */ |
4597 | *****************************************************************************/ | ||
4598 | static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd) | 3429 | static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd) |
4599 | { | 3430 | { |
4600 | /* Lower the clock input to the EEPROM (by clearing the SK bit), and then | 3431 | /* Lower the clock input to the EEPROM (by clearing the SK bit), and then |
4601 | * wait 50 microseconds. | 3432 | * wait 50 microseconds. |
4602 | */ | 3433 | */ |
4603 | *eecd = *eecd & ~E1000_EECD_SK; | 3434 | *eecd = *eecd & ~E1000_EECD_SK; |
4604 | ew32(EECD, *eecd); | 3435 | ew32(EECD, *eecd); |
4605 | E1000_WRITE_FLUSH(); | 3436 | E1000_WRITE_FLUSH(); |
4606 | udelay(hw->eeprom.delay_usec); | 3437 | udelay(hw->eeprom.delay_usec); |
4607 | } | 3438 | } |
4608 | 3439 | ||
4609 | /****************************************************************************** | 3440 | /** |
4610 | * Shift data bits out to the EEPROM. | 3441 | * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM. |
4611 | * | 3442 | * @hw: Struct containing variables accessed by shared code |
4612 | * hw - Struct containing variables accessed by shared code | 3443 | * @data: data to send to the EEPROM |
4613 | * data - data to send to the EEPROM | 3444 | * @count: number of bits to shift out |
4614 | * count - number of bits to shift out | 3445 | */ |
4615 | *****************************************************************************/ | ||
4616 | static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count) | 3446 | static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count) |
4617 | { | 3447 | { |
4618 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | 3448 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
4619 | u32 eecd; | 3449 | u32 eecd; |
4620 | u32 mask; | 3450 | u32 mask; |
4621 | 3451 | ||
4622 | /* We need to shift "count" bits out to the EEPROM. So, value in the | 3452 | /* We need to shift "count" bits out to the EEPROM. So, value in the |
4623 | * "data" parameter will be shifted out to the EEPROM one bit at a time. | 3453 | * "data" parameter will be shifted out to the EEPROM one bit at a time. |
4624 | * In order to do this, "data" must be broken down into bits. | 3454 | * In order to do this, "data" must be broken down into bits. |
4625 | */ | 3455 | */ |
4626 | mask = 0x01 << (count - 1); | 3456 | mask = 0x01 << (count - 1); |
4627 | eecd = er32(EECD); | 3457 | eecd = er32(EECD); |
4628 | if (eeprom->type == e1000_eeprom_microwire) { | 3458 | if (eeprom->type == e1000_eeprom_microwire) { |
4629 | eecd &= ~E1000_EECD_DO; | 3459 | eecd &= ~E1000_EECD_DO; |
4630 | } else if (eeprom->type == e1000_eeprom_spi) { | 3460 | } else if (eeprom->type == e1000_eeprom_spi) { |
4631 | eecd |= E1000_EECD_DO; | 3461 | eecd |= E1000_EECD_DO; |
4632 | } | 3462 | } |
4633 | do { | 3463 | do { |
4634 | /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", | 3464 | /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", |
4635 | * and then raising and then lowering the clock (the SK bit controls | 3465 | * and then raising and then lowering the clock (the SK bit controls |
4636 | * the clock input to the EEPROM). A "0" is shifted out to the EEPROM | 3466 | * the clock input to the EEPROM). A "0" is shifted out to the EEPROM |
4637 | * by setting "DI" to "0" and then raising and then lowering the clock. | 3467 | * by setting "DI" to "0" and then raising and then lowering the clock. |
4638 | */ | 3468 | */ |
4639 | eecd &= ~E1000_EECD_DI; | 3469 | eecd &= ~E1000_EECD_DI; |
4640 | 3470 | ||
4641 | if (data & mask) | 3471 | if (data & mask) |
4642 | eecd |= E1000_EECD_DI; | 3472 | eecd |= E1000_EECD_DI; |
4643 | 3473 | ||
4644 | ew32(EECD, eecd); | 3474 | ew32(EECD, eecd); |
4645 | E1000_WRITE_FLUSH(); | 3475 | E1000_WRITE_FLUSH(); |
4646 | 3476 | ||
4647 | udelay(eeprom->delay_usec); | 3477 | udelay(eeprom->delay_usec); |
4648 | 3478 | ||
4649 | e1000_raise_ee_clk(hw, &eecd); | 3479 | e1000_raise_ee_clk(hw, &eecd); |
4650 | e1000_lower_ee_clk(hw, &eecd); | 3480 | e1000_lower_ee_clk(hw, &eecd); |
4651 | 3481 | ||
4652 | mask = mask >> 1; | 3482 | mask = mask >> 1; |
4653 | 3483 | ||
4654 | } while (mask); | 3484 | } while (mask); |
4655 | 3485 | ||
4656 | /* We leave the "DI" bit set to "0" when we leave this routine. */ | 3486 | /* We leave the "DI" bit set to "0" when we leave this routine. */ |
4657 | eecd &= ~E1000_EECD_DI; | 3487 | eecd &= ~E1000_EECD_DI; |
4658 | ew32(EECD, eecd); | 3488 | ew32(EECD, eecd); |
4659 | } | 3489 | } |
4660 | 3490 | ||
4661 | /****************************************************************************** | 3491 | /** |
4662 | * Shift data bits in from the EEPROM | 3492 | * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM |
4663 | * | 3493 | * @hw: Struct containing variables accessed by shared code |
4664 | * hw - Struct containing variables accessed by shared code | 3494 | * @count: number of bits to shift in |
4665 | *****************************************************************************/ | 3495 | */ |
4666 | static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count) | 3496 | static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count) |
4667 | { | 3497 | { |
4668 | u32 eecd; | 3498 | u32 eecd; |
4669 | u32 i; | 3499 | u32 i; |
4670 | u16 data; | 3500 | u16 data; |
4671 | 3501 | ||
4672 | /* In order to read a register from the EEPROM, we need to shift 'count' | 3502 | /* In order to read a register from the EEPROM, we need to shift 'count' |
4673 | * bits in from the EEPROM. Bits are "shifted in" by raising the clock | 3503 | * bits in from the EEPROM. Bits are "shifted in" by raising the clock |
4674 | * input to the EEPROM (setting the SK bit), and then reading the value of | 3504 | * input to the EEPROM (setting the SK bit), and then reading the value of |
4675 | * the "DO" bit. During this "shifting in" process the "DI" bit should | 3505 | * the "DO" bit. During this "shifting in" process the "DI" bit should |
4676 | * always be clear. | 3506 | * always be clear. |
4677 | */ | 3507 | */ |
4678 | 3508 | ||
4679 | eecd = er32(EECD); | 3509 | eecd = er32(EECD); |
4680 | 3510 | ||
4681 | eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); | 3511 | eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); |
4682 | data = 0; | 3512 | data = 0; |
4683 | 3513 | ||
4684 | for (i = 0; i < count; i++) { | 3514 | for (i = 0; i < count; i++) { |
4685 | data = data << 1; | 3515 | data = data << 1; |
4686 | e1000_raise_ee_clk(hw, &eecd); | 3516 | e1000_raise_ee_clk(hw, &eecd); |
4687 | 3517 | ||
4688 | eecd = er32(EECD); | 3518 | eecd = er32(EECD); |
4689 | 3519 | ||
4690 | eecd &= ~(E1000_EECD_DI); | 3520 | eecd &= ~(E1000_EECD_DI); |
4691 | if (eecd & E1000_EECD_DO) | 3521 | if (eecd & E1000_EECD_DO) |
4692 | data |= 1; | 3522 | data |= 1; |
4693 | 3523 | ||
4694 | e1000_lower_ee_clk(hw, &eecd); | 3524 | e1000_lower_ee_clk(hw, &eecd); |
4695 | } | 3525 | } |
4696 | 3526 | ||
4697 | return data; | 3527 | return data; |
4698 | } | 3528 | } |
4699 | 3529 | ||
4700 | /****************************************************************************** | 3530 | /** |
4701 | * Prepares EEPROM for access | 3531 | * e1000_acquire_eeprom - Prepares EEPROM for access |
4702 | * | 3532 | * @hw: Struct containing variables accessed by shared code |
4703 | * hw - Struct containing variables accessed by shared code | ||
4704 | * | 3533 | * |
4705 | * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This | 3534 | * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This |
4706 | * function should be called before issuing a command to the EEPROM. | 3535 | * function should be called before issuing a command to the EEPROM. |
4707 | *****************************************************************************/ | 3536 | */ |
4708 | static s32 e1000_acquire_eeprom(struct e1000_hw *hw) | 3537 | static s32 e1000_acquire_eeprom(struct e1000_hw *hw) |
4709 | { | 3538 | { |
4710 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | 3539 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
4711 | u32 eecd, i=0; | 3540 | u32 eecd, i = 0; |
4712 | 3541 | ||
4713 | DEBUGFUNC("e1000_acquire_eeprom"); | 3542 | DEBUGFUNC("e1000_acquire_eeprom"); |
4714 | 3543 | ||
4715 | if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) | 3544 | eecd = er32(EECD); |
4716 | return -E1000_ERR_SWFW_SYNC; | 3545 | |
4717 | eecd = er32(EECD); | 3546 | /* Request EEPROM Access */ |
4718 | 3547 | if (hw->mac_type > e1000_82544) { | |
4719 | if (hw->mac_type != e1000_82573) { | 3548 | eecd |= E1000_EECD_REQ; |
4720 | /* Request EEPROM Access */ | 3549 | ew32(EECD, eecd); |
4721 | if (hw->mac_type > e1000_82544) { | 3550 | eecd = er32(EECD); |
4722 | eecd |= E1000_EECD_REQ; | 3551 | while ((!(eecd & E1000_EECD_GNT)) && |
4723 | ew32(EECD, eecd); | 3552 | (i < E1000_EEPROM_GRANT_ATTEMPTS)) { |
4724 | eecd = er32(EECD); | 3553 | i++; |
4725 | while ((!(eecd & E1000_EECD_GNT)) && | 3554 | udelay(5); |
4726 | (i < E1000_EEPROM_GRANT_ATTEMPTS)) { | 3555 | eecd = er32(EECD); |
4727 | i++; | 3556 | } |
4728 | udelay(5); | 3557 | if (!(eecd & E1000_EECD_GNT)) { |
4729 | eecd = er32(EECD); | 3558 | eecd &= ~E1000_EECD_REQ; |
4730 | } | 3559 | ew32(EECD, eecd); |
4731 | if (!(eecd & E1000_EECD_GNT)) { | 3560 | DEBUGOUT("Could not acquire EEPROM grant\n"); |
4732 | eecd &= ~E1000_EECD_REQ; | 3561 | return -E1000_ERR_EEPROM; |
4733 | ew32(EECD, eecd); | 3562 | } |
4734 | DEBUGOUT("Could not acquire EEPROM grant\n"); | 3563 | } |
4735 | e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); | 3564 | |
4736 | return -E1000_ERR_EEPROM; | 3565 | /* Setup EEPROM for Read/Write */ |
4737 | } | 3566 | |
4738 | } | 3567 | if (eeprom->type == e1000_eeprom_microwire) { |
4739 | } | 3568 | /* Clear SK and DI */ |
4740 | 3569 | eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); | |
4741 | /* Setup EEPROM for Read/Write */ | 3570 | ew32(EECD, eecd); |
4742 | 3571 | ||
4743 | if (eeprom->type == e1000_eeprom_microwire) { | 3572 | /* Set CS */ |
4744 | /* Clear SK and DI */ | 3573 | eecd |= E1000_EECD_CS; |
4745 | eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); | 3574 | ew32(EECD, eecd); |
4746 | ew32(EECD, eecd); | 3575 | } else if (eeprom->type == e1000_eeprom_spi) { |
4747 | 3576 | /* Clear SK and CS */ | |
4748 | /* Set CS */ | 3577 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
4749 | eecd |= E1000_EECD_CS; | 3578 | ew32(EECD, eecd); |
4750 | ew32(EECD, eecd); | 3579 | udelay(1); |
4751 | } else if (eeprom->type == e1000_eeprom_spi) { | 3580 | } |
4752 | /* Clear SK and CS */ | 3581 | |
4753 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); | 3582 | return E1000_SUCCESS; |
4754 | ew32(EECD, eecd); | ||
4755 | udelay(1); | ||
4756 | } | ||
4757 | |||
4758 | return E1000_SUCCESS; | ||
4759 | } | 3583 | } |
4760 | 3584 | ||
4761 | /****************************************************************************** | 3585 | /** |
4762 | * Returns EEPROM to a "standby" state | 3586 | * e1000_standby_eeprom - Returns EEPROM to a "standby" state |
4763 | * | 3587 | * @hw: Struct containing variables accessed by shared code |
4764 | * hw - Struct containing variables accessed by shared code | 3588 | */ |
4765 | *****************************************************************************/ | ||
4766 | static void e1000_standby_eeprom(struct e1000_hw *hw) | 3589 | static void e1000_standby_eeprom(struct e1000_hw *hw) |
4767 | { | 3590 | { |
4768 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | 3591 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
4769 | u32 eecd; | 3592 | u32 eecd; |
4770 | 3593 | ||
4771 | eecd = er32(EECD); | 3594 | eecd = er32(EECD); |
4772 | 3595 | ||
4773 | if (eeprom->type == e1000_eeprom_microwire) { | 3596 | if (eeprom->type == e1000_eeprom_microwire) { |
4774 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); | 3597 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
4775 | ew32(EECD, eecd); | 3598 | ew32(EECD, eecd); |
4776 | E1000_WRITE_FLUSH(); | 3599 | E1000_WRITE_FLUSH(); |
4777 | udelay(eeprom->delay_usec); | 3600 | udelay(eeprom->delay_usec); |
4778 | 3601 | ||
4779 | /* Clock high */ | 3602 | /* Clock high */ |
4780 | eecd |= E1000_EECD_SK; | 3603 | eecd |= E1000_EECD_SK; |
4781 | ew32(EECD, eecd); | 3604 | ew32(EECD, eecd); |
4782 | E1000_WRITE_FLUSH(); | 3605 | E1000_WRITE_FLUSH(); |
4783 | udelay(eeprom->delay_usec); | 3606 | udelay(eeprom->delay_usec); |
4784 | 3607 | ||
4785 | /* Select EEPROM */ | 3608 | /* Select EEPROM */ |
4786 | eecd |= E1000_EECD_CS; | 3609 | eecd |= E1000_EECD_CS; |
4787 | ew32(EECD, eecd); | 3610 | ew32(EECD, eecd); |
4788 | E1000_WRITE_FLUSH(); | 3611 | E1000_WRITE_FLUSH(); |
4789 | udelay(eeprom->delay_usec); | 3612 | udelay(eeprom->delay_usec); |
4790 | 3613 | ||
4791 | /* Clock low */ | 3614 | /* Clock low */ |
4792 | eecd &= ~E1000_EECD_SK; | 3615 | eecd &= ~E1000_EECD_SK; |
4793 | ew32(EECD, eecd); | 3616 | ew32(EECD, eecd); |
4794 | E1000_WRITE_FLUSH(); | 3617 | E1000_WRITE_FLUSH(); |
4795 | udelay(eeprom->delay_usec); | 3618 | udelay(eeprom->delay_usec); |
4796 | } else if (eeprom->type == e1000_eeprom_spi) { | 3619 | } else if (eeprom->type == e1000_eeprom_spi) { |
4797 | /* Toggle CS to flush commands */ | 3620 | /* Toggle CS to flush commands */ |
4798 | eecd |= E1000_EECD_CS; | 3621 | eecd |= E1000_EECD_CS; |
4799 | ew32(EECD, eecd); | 3622 | ew32(EECD, eecd); |
4800 | E1000_WRITE_FLUSH(); | 3623 | E1000_WRITE_FLUSH(); |
4801 | udelay(eeprom->delay_usec); | 3624 | udelay(eeprom->delay_usec); |
4802 | eecd &= ~E1000_EECD_CS; | 3625 | eecd &= ~E1000_EECD_CS; |
4803 | ew32(EECD, eecd); | 3626 | ew32(EECD, eecd); |
4804 | E1000_WRITE_FLUSH(); | 3627 | E1000_WRITE_FLUSH(); |
4805 | udelay(eeprom->delay_usec); | 3628 | udelay(eeprom->delay_usec); |
4806 | } | 3629 | } |
4807 | } | 3630 | } |
4808 | 3631 | ||
4809 | /****************************************************************************** | 3632 | /** |
4810 | * Terminates a command by inverting the EEPROM's chip select pin | 3633 | * e1000_release_eeprom - drop chip select |
3634 | * @hw: Struct containing variables accessed by shared code | ||
4811 | * | 3635 | * |
4812 | * hw - Struct containing variables accessed by shared code | 3636 | * Terminates a command by inverting the EEPROM's chip select pin |
4813 | *****************************************************************************/ | 3637 | */ |
4814 | static void e1000_release_eeprom(struct e1000_hw *hw) | 3638 | static void e1000_release_eeprom(struct e1000_hw *hw) |
4815 | { | 3639 | { |
4816 | u32 eecd; | 3640 | u32 eecd; |
4817 | |||
4818 | DEBUGFUNC("e1000_release_eeprom"); | ||
4819 | 3641 | ||
4820 | eecd = er32(EECD); | 3642 | DEBUGFUNC("e1000_release_eeprom"); |
4821 | 3643 | ||
4822 | if (hw->eeprom.type == e1000_eeprom_spi) { | 3644 | eecd = er32(EECD); |
4823 | eecd |= E1000_EECD_CS; /* Pull CS high */ | ||
4824 | eecd &= ~E1000_EECD_SK; /* Lower SCK */ | ||
4825 | 3645 | ||
4826 | ew32(EECD, eecd); | 3646 | if (hw->eeprom.type == e1000_eeprom_spi) { |
3647 | eecd |= E1000_EECD_CS; /* Pull CS high */ | ||
3648 | eecd &= ~E1000_EECD_SK; /* Lower SCK */ | ||
4827 | 3649 | ||
4828 | udelay(hw->eeprom.delay_usec); | 3650 | ew32(EECD, eecd); |
4829 | } else if (hw->eeprom.type == e1000_eeprom_microwire) { | ||
4830 | /* cleanup eeprom */ | ||
4831 | 3651 | ||
4832 | /* CS on Microwire is active-high */ | 3652 | udelay(hw->eeprom.delay_usec); |
4833 | eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); | 3653 | } else if (hw->eeprom.type == e1000_eeprom_microwire) { |
3654 | /* cleanup eeprom */ | ||
4834 | 3655 | ||
4835 | ew32(EECD, eecd); | 3656 | /* CS on Microwire is active-high */ |
3657 | eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); | ||
4836 | 3658 | ||
4837 | /* Rising edge of clock */ | 3659 | ew32(EECD, eecd); |
4838 | eecd |= E1000_EECD_SK; | ||
4839 | ew32(EECD, eecd); | ||
4840 | E1000_WRITE_FLUSH(); | ||
4841 | udelay(hw->eeprom.delay_usec); | ||
4842 | 3660 | ||
4843 | /* Falling edge of clock */ | 3661 | /* Rising edge of clock */ |
4844 | eecd &= ~E1000_EECD_SK; | 3662 | eecd |= E1000_EECD_SK; |
4845 | ew32(EECD, eecd); | 3663 | ew32(EECD, eecd); |
4846 | E1000_WRITE_FLUSH(); | 3664 | E1000_WRITE_FLUSH(); |
4847 | udelay(hw->eeprom.delay_usec); | 3665 | udelay(hw->eeprom.delay_usec); |
4848 | } | ||
4849 | 3666 | ||
4850 | /* Stop requesting EEPROM access */ | 3667 | /* Falling edge of clock */ |
4851 | if (hw->mac_type > e1000_82544) { | 3668 | eecd &= ~E1000_EECD_SK; |
4852 | eecd &= ~E1000_EECD_REQ; | 3669 | ew32(EECD, eecd); |
4853 | ew32(EECD, eecd); | 3670 | E1000_WRITE_FLUSH(); |
4854 | } | 3671 | udelay(hw->eeprom.delay_usec); |
3672 | } | ||
4855 | 3673 | ||
4856 | e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); | 3674 | /* Stop requesting EEPROM access */ |
3675 | if (hw->mac_type > e1000_82544) { | ||
3676 | eecd &= ~E1000_EECD_REQ; | ||
3677 | ew32(EECD, eecd); | ||
3678 | } | ||
4857 | } | 3679 | } |
4858 | 3680 | ||
4859 | /****************************************************************************** | 3681 | /** |
4860 | * Reads a 16 bit word from the EEPROM. | 3682 | * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM. |
4861 | * | 3683 | * @hw: Struct containing variables accessed by shared code |
4862 | * hw - Struct containing variables accessed by shared code | 3684 | */ |
4863 | *****************************************************************************/ | ||
4864 | static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw) | 3685 | static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw) |
4865 | { | 3686 | { |
4866 | u16 retry_count = 0; | 3687 | u16 retry_count = 0; |
4867 | u8 spi_stat_reg; | 3688 | u8 spi_stat_reg; |
4868 | |||
4869 | DEBUGFUNC("e1000_spi_eeprom_ready"); | ||
4870 | |||
4871 | /* Read "Status Register" repeatedly until the LSB is cleared. The | ||
4872 | * EEPROM will signal that the command has been completed by clearing | ||
4873 | * bit 0 of the internal status register. If it's not cleared within | ||
4874 | * 5 milliseconds, then error out. | ||
4875 | */ | ||
4876 | retry_count = 0; | ||
4877 | do { | ||
4878 | e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, | ||
4879 | hw->eeprom.opcode_bits); | ||
4880 | spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8); | ||
4881 | if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) | ||
4882 | break; | ||
4883 | |||
4884 | udelay(5); | ||
4885 | retry_count += 5; | ||
4886 | |||
4887 | e1000_standby_eeprom(hw); | ||
4888 | } while (retry_count < EEPROM_MAX_RETRY_SPI); | ||
4889 | |||
4890 | /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and | ||
4891 | * only 0-5mSec on 5V devices) | ||
4892 | */ | ||
4893 | if (retry_count >= EEPROM_MAX_RETRY_SPI) { | ||
4894 | DEBUGOUT("SPI EEPROM Status error\n"); | ||
4895 | return -E1000_ERR_EEPROM; | ||
4896 | } | ||
4897 | |||
4898 | return E1000_SUCCESS; | ||
4899 | } | ||
4900 | |||
4901 | /****************************************************************************** | ||
4902 | * Reads a 16 bit word from the EEPROM. | ||
4903 | * | ||
4904 | * hw - Struct containing variables accessed by shared code | ||
4905 | * offset - offset of word in the EEPROM to read | ||
4906 | * data - word read from the EEPROM | ||
4907 | * words - number of words to read | ||
4908 | *****************************************************************************/ | ||
4909 | s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) | ||
4910 | { | ||
4911 | s32 ret; | ||
4912 | spin_lock(&e1000_eeprom_lock); | ||
4913 | ret = e1000_do_read_eeprom(hw, offset, words, data); | ||
4914 | spin_unlock(&e1000_eeprom_lock); | ||
4915 | return ret; | ||
4916 | } | ||
4917 | |||
4918 | static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) | ||
4919 | { | ||
4920 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | ||
4921 | u32 i = 0; | ||
4922 | |||
4923 | DEBUGFUNC("e1000_read_eeprom"); | ||
4924 | |||
4925 | /* If eeprom is not yet detected, do so now */ | ||
4926 | if (eeprom->word_size == 0) | ||
4927 | e1000_init_eeprom_params(hw); | ||
4928 | |||
4929 | /* A check for invalid values: offset too large, too many words, and not | ||
4930 | * enough words. | ||
4931 | */ | ||
4932 | if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || | ||
4933 | (words == 0)) { | ||
4934 | DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size); | ||
4935 | return -E1000_ERR_EEPROM; | ||
4936 | } | ||
4937 | |||
4938 | /* EEPROM's that don't use EERD to read require us to bit-bang the SPI | ||
4939 | * directly. In this case, we need to acquire the EEPROM so that | ||
4940 | * FW or other port software does not interrupt. | ||
4941 | */ | ||
4942 | if (e1000_is_onboard_nvm_eeprom(hw) && !hw->eeprom.use_eerd) { | ||
4943 | /* Prepare the EEPROM for bit-bang reading */ | ||
4944 | if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) | ||
4945 | return -E1000_ERR_EEPROM; | ||
4946 | } | ||
4947 | |||
4948 | /* Eerd register EEPROM access requires no eeprom aquire/release */ | ||
4949 | if (eeprom->use_eerd) | ||
4950 | return e1000_read_eeprom_eerd(hw, offset, words, data); | ||
4951 | |||
4952 | /* ICH EEPROM access is done via the ICH flash controller */ | ||
4953 | if (eeprom->type == e1000_eeprom_ich8) | ||
4954 | return e1000_read_eeprom_ich8(hw, offset, words, data); | ||
4955 | |||
4956 | /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have | ||
4957 | * acquired the EEPROM at this point, so any returns should relase it */ | ||
4958 | if (eeprom->type == e1000_eeprom_spi) { | ||
4959 | u16 word_in; | ||
4960 | u8 read_opcode = EEPROM_READ_OPCODE_SPI; | ||
4961 | |||
4962 | if (e1000_spi_eeprom_ready(hw)) { | ||
4963 | e1000_release_eeprom(hw); | ||
4964 | return -E1000_ERR_EEPROM; | ||
4965 | } | ||
4966 | |||
4967 | e1000_standby_eeprom(hw); | ||
4968 | |||
4969 | /* Some SPI eeproms use the 8th address bit embedded in the opcode */ | ||
4970 | if ((eeprom->address_bits == 8) && (offset >= 128)) | ||
4971 | read_opcode |= EEPROM_A8_OPCODE_SPI; | ||
4972 | |||
4973 | /* Send the READ command (opcode + addr) */ | ||
4974 | e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); | ||
4975 | e1000_shift_out_ee_bits(hw, (u16)(offset*2), eeprom->address_bits); | ||
4976 | |||
4977 | /* Read the data. The address of the eeprom internally increments with | ||
4978 | * each byte (spi) being read, saving on the overhead of eeprom setup | ||
4979 | * and tear-down. The address counter will roll over if reading beyond | ||
4980 | * the size of the eeprom, thus allowing the entire memory to be read | ||
4981 | * starting from any offset. */ | ||
4982 | for (i = 0; i < words; i++) { | ||
4983 | word_in = e1000_shift_in_ee_bits(hw, 16); | ||
4984 | data[i] = (word_in >> 8) | (word_in << 8); | ||
4985 | } | ||
4986 | } else if (eeprom->type == e1000_eeprom_microwire) { | ||
4987 | for (i = 0; i < words; i++) { | ||
4988 | /* Send the READ command (opcode + addr) */ | ||
4989 | e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, | ||
4990 | eeprom->opcode_bits); | ||
4991 | e1000_shift_out_ee_bits(hw, (u16)(offset + i), | ||
4992 | eeprom->address_bits); | ||
4993 | |||
4994 | /* Read the data. For microwire, each word requires the overhead | ||
4995 | * of eeprom setup and tear-down. */ | ||
4996 | data[i] = e1000_shift_in_ee_bits(hw, 16); | ||
4997 | e1000_standby_eeprom(hw); | ||
4998 | } | ||
4999 | } | ||
5000 | |||
5001 | /* End this read operation */ | ||
5002 | e1000_release_eeprom(hw); | ||
5003 | |||
5004 | return E1000_SUCCESS; | ||
5005 | } | ||
5006 | 3689 | ||
5007 | /****************************************************************************** | 3690 | DEBUGFUNC("e1000_spi_eeprom_ready"); |
5008 | * Reads a 16 bit word from the EEPROM using the EERD register. | ||
5009 | * | ||
5010 | * hw - Struct containing variables accessed by shared code | ||
5011 | * offset - offset of word in the EEPROM to read | ||
5012 | * data - word read from the EEPROM | ||
5013 | * words - number of words to read | ||
5014 | *****************************************************************************/ | ||
5015 | static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words, | ||
5016 | u16 *data) | ||
5017 | { | ||
5018 | u32 i, eerd = 0; | ||
5019 | s32 error = 0; | ||
5020 | 3691 | ||
5021 | for (i = 0; i < words; i++) { | 3692 | /* Read "Status Register" repeatedly until the LSB is cleared. The |
5022 | eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + | 3693 | * EEPROM will signal that the command has been completed by clearing |
5023 | E1000_EEPROM_RW_REG_START; | 3694 | * bit 0 of the internal status register. If it's not cleared within |
3695 | * 5 milliseconds, then error out. | ||
3696 | */ | ||
3697 | retry_count = 0; | ||
3698 | do { | ||
3699 | e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, | ||
3700 | hw->eeprom.opcode_bits); | ||
3701 | spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8); | ||
3702 | if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) | ||
3703 | break; | ||
5024 | 3704 | ||
5025 | ew32(EERD, eerd); | 3705 | udelay(5); |
5026 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); | 3706 | retry_count += 5; |
5027 | 3707 | ||
5028 | if (error) { | 3708 | e1000_standby_eeprom(hw); |
5029 | break; | 3709 | } while (retry_count < EEPROM_MAX_RETRY_SPI); |
5030 | } | ||
5031 | data[i] = (er32(EERD) >> E1000_EEPROM_RW_REG_DATA); | ||
5032 | 3710 | ||
5033 | } | 3711 | /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and |
3712 | * only 0-5mSec on 5V devices) | ||
3713 | */ | ||
3714 | if (retry_count >= EEPROM_MAX_RETRY_SPI) { | ||
3715 | DEBUGOUT("SPI EEPROM Status error\n"); | ||
3716 | return -E1000_ERR_EEPROM; | ||
3717 | } | ||
5034 | 3718 | ||
5035 | return error; | 3719 | return E1000_SUCCESS; |
5036 | } | 3720 | } |
5037 | 3721 | ||
5038 | /****************************************************************************** | 3722 | /** |
5039 | * Writes a 16 bit word from the EEPROM using the EEWR register. | 3723 | * e1000_read_eeprom - Reads a 16 bit word from the EEPROM. |
5040 | * | 3724 | * @hw: Struct containing variables accessed by shared code |
5041 | * hw - Struct containing variables accessed by shared code | 3725 | * @offset: offset of word in the EEPROM to read |
5042 | * offset - offset of word in the EEPROM to read | 3726 | * @data: word read from the EEPROM |
5043 | * data - word read from the EEPROM | 3727 | * @words: number of words to read |
5044 | * words - number of words to read | 3728 | */ |
5045 | *****************************************************************************/ | 3729 | s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
5046 | static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words, | ||
5047 | u16 *data) | ||
5048 | { | 3730 | { |
5049 | u32 register_value = 0; | 3731 | s32 ret; |
5050 | u32 i = 0; | 3732 | spin_lock(&e1000_eeprom_lock); |
5051 | s32 error = 0; | 3733 | ret = e1000_do_read_eeprom(hw, offset, words, data); |
5052 | 3734 | spin_unlock(&e1000_eeprom_lock); | |
5053 | if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) | 3735 | return ret; |
5054 | return -E1000_ERR_SWFW_SYNC; | ||
5055 | |||
5056 | for (i = 0; i < words; i++) { | ||
5057 | register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | | ||
5058 | ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) | | ||
5059 | E1000_EEPROM_RW_REG_START; | ||
5060 | |||
5061 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); | ||
5062 | if (error) { | ||
5063 | break; | ||
5064 | } | ||
5065 | |||
5066 | ew32(EEWR, register_value); | ||
5067 | |||
5068 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); | ||
5069 | |||
5070 | if (error) { | ||
5071 | break; | ||
5072 | } | ||
5073 | } | ||
5074 | |||
5075 | e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); | ||
5076 | return error; | ||
5077 | } | 3736 | } |
5078 | 3737 | ||
5079 | /****************************************************************************** | 3738 | static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, |
5080 | * Polls the status bit (bit 1) of the EERD to determine when the read is done. | 3739 | u16 *data) |
5081 | * | ||
5082 | * hw - Struct containing variables accessed by shared code | ||
5083 | *****************************************************************************/ | ||
5084 | static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) | ||
5085 | { | 3740 | { |
5086 | u32 attempts = 100000; | 3741 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
5087 | u32 i, reg = 0; | 3742 | u32 i = 0; |
5088 | s32 done = E1000_ERR_EEPROM; | ||
5089 | |||
5090 | for (i = 0; i < attempts; i++) { | ||
5091 | if (eerd == E1000_EEPROM_POLL_READ) | ||
5092 | reg = er32(EERD); | ||
5093 | else | ||
5094 | reg = er32(EEWR); | ||
5095 | |||
5096 | if (reg & E1000_EEPROM_RW_REG_DONE) { | ||
5097 | done = E1000_SUCCESS; | ||
5098 | break; | ||
5099 | } | ||
5100 | udelay(5); | ||
5101 | } | ||
5102 | |||
5103 | return done; | ||
5104 | } | ||
5105 | 3743 | ||
5106 | /*************************************************************************** | 3744 | DEBUGFUNC("e1000_read_eeprom"); |
5107 | * Description: Determines if the onboard NVM is FLASH or EEPROM. | ||
5108 | * | ||
5109 | * hw - Struct containing variables accessed by shared code | ||
5110 | ****************************************************************************/ | ||
5111 | static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) | ||
5112 | { | ||
5113 | u32 eecd = 0; | ||
5114 | 3745 | ||
5115 | DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); | 3746 | /* If eeprom is not yet detected, do so now */ |
3747 | if (eeprom->word_size == 0) | ||
3748 | e1000_init_eeprom_params(hw); | ||
3749 | |||
3750 | /* A check for invalid values: offset too large, too many words, and not | ||
3751 | * enough words. | ||
3752 | */ | ||
3753 | if ((offset >= eeprom->word_size) | ||
3754 | || (words > eeprom->word_size - offset) || (words == 0)) { | ||
3755 | DEBUGOUT2 | ||
3756 | ("\"words\" parameter out of bounds. Words = %d, size = %d\n", | ||
3757 | offset, eeprom->word_size); | ||
3758 | return -E1000_ERR_EEPROM; | ||
3759 | } | ||
5116 | 3760 | ||
5117 | if (hw->mac_type == e1000_ich8lan) | 3761 | /* EEPROM's that don't use EERD to read require us to bit-bang the SPI |
5118 | return false; | 3762 | * directly. In this case, we need to acquire the EEPROM so that |
3763 | * FW or other port software does not interrupt. | ||
3764 | */ | ||
3765 | /* Prepare the EEPROM for bit-bang reading */ | ||
3766 | if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) | ||
3767 | return -E1000_ERR_EEPROM; | ||
3768 | |||
3769 | /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have | ||
3770 | * acquired the EEPROM at this point, so any returns should release it */ | ||
3771 | if (eeprom->type == e1000_eeprom_spi) { | ||
3772 | u16 word_in; | ||
3773 | u8 read_opcode = EEPROM_READ_OPCODE_SPI; | ||
3774 | |||
3775 | if (e1000_spi_eeprom_ready(hw)) { | ||
3776 | e1000_release_eeprom(hw); | ||
3777 | return -E1000_ERR_EEPROM; | ||
3778 | } | ||
5119 | 3779 | ||
5120 | if (hw->mac_type == e1000_82573) { | 3780 | e1000_standby_eeprom(hw); |
5121 | eecd = er32(EECD); | 3781 | |
3782 | /* Some SPI eeproms use the 8th address bit embedded in the opcode */ | ||
3783 | if ((eeprom->address_bits == 8) && (offset >= 128)) | ||
3784 | read_opcode |= EEPROM_A8_OPCODE_SPI; | ||
3785 | |||
3786 | /* Send the READ command (opcode + addr) */ | ||
3787 | e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); | ||
3788 | e1000_shift_out_ee_bits(hw, (u16) (offset * 2), | ||
3789 | eeprom->address_bits); | ||
3790 | |||
3791 | /* Read the data. The address of the eeprom internally increments with | ||
3792 | * each byte (spi) being read, saving on the overhead of eeprom setup | ||
3793 | * and tear-down. The address counter will roll over if reading beyond | ||
3794 | * the size of the eeprom, thus allowing the entire memory to be read | ||
3795 | * starting from any offset. */ | ||
3796 | for (i = 0; i < words; i++) { | ||
3797 | word_in = e1000_shift_in_ee_bits(hw, 16); | ||
3798 | data[i] = (word_in >> 8) | (word_in << 8); | ||
3799 | } | ||
3800 | } else if (eeprom->type == e1000_eeprom_microwire) { | ||
3801 | for (i = 0; i < words; i++) { | ||
3802 | /* Send the READ command (opcode + addr) */ | ||
3803 | e1000_shift_out_ee_bits(hw, | ||
3804 | EEPROM_READ_OPCODE_MICROWIRE, | ||
3805 | eeprom->opcode_bits); | ||
3806 | e1000_shift_out_ee_bits(hw, (u16) (offset + i), | ||
3807 | eeprom->address_bits); | ||
3808 | |||
3809 | /* Read the data. For microwire, each word requires the overhead | ||
3810 | * of eeprom setup and tear-down. */ | ||
3811 | data[i] = e1000_shift_in_ee_bits(hw, 16); | ||
3812 | e1000_standby_eeprom(hw); | ||
3813 | } | ||
3814 | } | ||
5122 | 3815 | ||
5123 | /* Isolate bits 15 & 16 */ | 3816 | /* End this read operation */ |
5124 | eecd = ((eecd >> 15) & 0x03); | 3817 | e1000_release_eeprom(hw); |
5125 | 3818 | ||
5126 | /* If both bits are set, device is Flash type */ | 3819 | return E1000_SUCCESS; |
5127 | if (eecd == 0x03) { | ||
5128 | return false; | ||
5129 | } | ||
5130 | } | ||
5131 | return true; | ||
5132 | } | 3820 | } |
5133 | 3821 | ||
5134 | /****************************************************************************** | 3822 | /** |
5135 | * Verifies that the EEPROM has a valid checksum | 3823 | * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum |
5136 | * | 3824 | * @hw: Struct containing variables accessed by shared code |
5137 | * hw - Struct containing variables accessed by shared code | ||
5138 | * | 3825 | * |
5139 | * Reads the first 64 16 bit words of the EEPROM and sums the values read. | 3826 | * Reads the first 64 16 bit words of the EEPROM and sums the values read. |
5140 | * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is | 3827 | * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is |
5141 | * valid. | 3828 | * valid. |
5142 | *****************************************************************************/ | 3829 | */ |
5143 | s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw) | 3830 | s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw) |
5144 | { | 3831 | { |
5145 | u16 checksum = 0; | 3832 | u16 checksum = 0; |
5146 | u16 i, eeprom_data; | 3833 | u16 i, eeprom_data; |
5147 | 3834 | ||
5148 | DEBUGFUNC("e1000_validate_eeprom_checksum"); | 3835 | DEBUGFUNC("e1000_validate_eeprom_checksum"); |
5149 | 3836 | ||
5150 | if ((hw->mac_type == e1000_82573) && !e1000_is_onboard_nvm_eeprom(hw)) { | 3837 | for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { |
5151 | /* Check bit 4 of word 10h. If it is 0, firmware is done updating | 3838 | if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { |
5152 | * 10h-12h. Checksum may need to be fixed. */ | 3839 | DEBUGOUT("EEPROM Read Error\n"); |
5153 | e1000_read_eeprom(hw, 0x10, 1, &eeprom_data); | 3840 | return -E1000_ERR_EEPROM; |
5154 | if ((eeprom_data & 0x10) == 0) { | 3841 | } |
5155 | /* Read 0x23 and check bit 15. This bit is a 1 when the checksum | 3842 | checksum += eeprom_data; |
5156 | * has already been fixed. If the checksum is still wrong and this | 3843 | } |
5157 | * bit is a 1, we need to return bad checksum. Otherwise, we need | 3844 | |
5158 | * to set this bit to a 1 and update the checksum. */ | 3845 | if (checksum == (u16) EEPROM_SUM) |
5159 | e1000_read_eeprom(hw, 0x23, 1, &eeprom_data); | 3846 | return E1000_SUCCESS; |
5160 | if ((eeprom_data & 0x8000) == 0) { | 3847 | else { |
5161 | eeprom_data |= 0x8000; | 3848 | DEBUGOUT("EEPROM Checksum Invalid\n"); |
5162 | e1000_write_eeprom(hw, 0x23, 1, &eeprom_data); | 3849 | return -E1000_ERR_EEPROM; |
5163 | e1000_update_eeprom_checksum(hw); | 3850 | } |
5164 | } | ||
5165 | } | ||
5166 | } | ||
5167 | |||
5168 | if (hw->mac_type == e1000_ich8lan) { | ||
5169 | /* Drivers must allocate the shadow ram structure for the | ||
5170 | * EEPROM checksum to be updated. Otherwise, this bit as well | ||
5171 | * as the checksum must both be set correctly for this | ||
5172 | * validation to pass. | ||
5173 | */ | ||
5174 | e1000_read_eeprom(hw, 0x19, 1, &eeprom_data); | ||
5175 | if ((eeprom_data & 0x40) == 0) { | ||
5176 | eeprom_data |= 0x40; | ||
5177 | e1000_write_eeprom(hw, 0x19, 1, &eeprom_data); | ||
5178 | e1000_update_eeprom_checksum(hw); | ||
5179 | } | ||
5180 | } | ||
5181 | |||
5182 | for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { | ||
5183 | if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { | ||
5184 | DEBUGOUT("EEPROM Read Error\n"); | ||
5185 | return -E1000_ERR_EEPROM; | ||
5186 | } | ||
5187 | checksum += eeprom_data; | ||
5188 | } | ||
5189 | |||
5190 | if (checksum == (u16)EEPROM_SUM) | ||
5191 | return E1000_SUCCESS; | ||
5192 | else { | ||
5193 | DEBUGOUT("EEPROM Checksum Invalid\n"); | ||
5194 | return -E1000_ERR_EEPROM; | ||
5195 | } | ||
5196 | } | 3851 | } |
5197 | 3852 | ||
5198 | /****************************************************************************** | 3853 | /** |
5199 | * Calculates the EEPROM checksum and writes it to the EEPROM | 3854 | * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum |
5200 | * | 3855 | * @hw: Struct containing variables accessed by shared code |
5201 | * hw - Struct containing variables accessed by shared code | ||
5202 | * | 3856 | * |
5203 | * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. | 3857 | * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. |
5204 | * Writes the difference to word offset 63 of the EEPROM. | 3858 | * Writes the difference to word offset 63 of the EEPROM. |
5205 | *****************************************************************************/ | 3859 | */ |
5206 | s32 e1000_update_eeprom_checksum(struct e1000_hw *hw) | 3860 | s32 e1000_update_eeprom_checksum(struct e1000_hw *hw) |
5207 | { | 3861 | { |
5208 | u32 ctrl_ext; | 3862 | u16 checksum = 0; |
5209 | u16 checksum = 0; | 3863 | u16 i, eeprom_data; |
5210 | u16 i, eeprom_data; | 3864 | |
5211 | 3865 | DEBUGFUNC("e1000_update_eeprom_checksum"); | |
5212 | DEBUGFUNC("e1000_update_eeprom_checksum"); | 3866 | |
5213 | 3867 | for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { | |
5214 | for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { | 3868 | if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { |
5215 | if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { | 3869 | DEBUGOUT("EEPROM Read Error\n"); |
5216 | DEBUGOUT("EEPROM Read Error\n"); | 3870 | return -E1000_ERR_EEPROM; |
5217 | return -E1000_ERR_EEPROM; | 3871 | } |
5218 | } | 3872 | checksum += eeprom_data; |
5219 | checksum += eeprom_data; | 3873 | } |
5220 | } | 3874 | checksum = (u16) EEPROM_SUM - checksum; |
5221 | checksum = (u16)EEPROM_SUM - checksum; | 3875 | if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { |
5222 | if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { | 3876 | DEBUGOUT("EEPROM Write Error\n"); |
5223 | DEBUGOUT("EEPROM Write Error\n"); | 3877 | return -E1000_ERR_EEPROM; |
5224 | return -E1000_ERR_EEPROM; | 3878 | } |
5225 | } else if (hw->eeprom.type == e1000_eeprom_flash) { | 3879 | return E1000_SUCCESS; |
5226 | e1000_commit_shadow_ram(hw); | ||
5227 | } else if (hw->eeprom.type == e1000_eeprom_ich8) { | ||
5228 | e1000_commit_shadow_ram(hw); | ||
5229 | /* Reload the EEPROM, or else modifications will not appear | ||
5230 | * until after next adapter reset. */ | ||
5231 | ctrl_ext = er32(CTRL_EXT); | ||
5232 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | ||
5233 | ew32(CTRL_EXT, ctrl_ext); | ||
5234 | msleep(10); | ||
5235 | } | ||
5236 | return E1000_SUCCESS; | ||
5237 | } | 3880 | } |
5238 | 3881 | ||
5239 | /****************************************************************************** | 3882 | /** |
5240 | * Parent function for writing words to the different EEPROM types. | 3883 | * e1000_write_eeprom - write words to the different EEPROM types. |
5241 | * | 3884 | * @hw: Struct containing variables accessed by shared code |
5242 | * hw - Struct containing variables accessed by shared code | 3885 | * @offset: offset within the EEPROM to be written to |
5243 | * offset - offset within the EEPROM to be written to | 3886 | * @words: number of words to write |
5244 | * words - number of words to write | 3887 | * @data: 16 bit word to be written to the EEPROM |
5245 | * data - 16 bit word to be written to the EEPROM | ||
5246 | * | 3888 | * |
5247 | * If e1000_update_eeprom_checksum is not called after this function, the | 3889 | * If e1000_update_eeprom_checksum is not called after this function, the |
5248 | * EEPROM will most likely contain an invalid checksum. | 3890 | * EEPROM will most likely contain an invalid checksum. |
5249 | *****************************************************************************/ | 3891 | */ |
5250 | s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) | 3892 | s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
5251 | { | 3893 | { |
5252 | s32 ret; | 3894 | s32 ret; |
5253 | spin_lock(&e1000_eeprom_lock); | 3895 | spin_lock(&e1000_eeprom_lock); |
5254 | ret = e1000_do_write_eeprom(hw, offset, words, data); | 3896 | ret = e1000_do_write_eeprom(hw, offset, words, data); |
5255 | spin_unlock(&e1000_eeprom_lock); | 3897 | spin_unlock(&e1000_eeprom_lock); |
5256 | return ret; | 3898 | return ret; |
5257 | } | 3899 | } |
5258 | 3900 | ||
5259 | 3901 | static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, | |
5260 | static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) | 3902 | u16 *data) |
5261 | { | 3903 | { |
5262 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | 3904 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
5263 | s32 status = 0; | 3905 | s32 status = 0; |
5264 | 3906 | ||
5265 | DEBUGFUNC("e1000_write_eeprom"); | 3907 | DEBUGFUNC("e1000_write_eeprom"); |
5266 | 3908 | ||
5267 | /* If eeprom is not yet detected, do so now */ | 3909 | /* If eeprom is not yet detected, do so now */ |
5268 | if (eeprom->word_size == 0) | 3910 | if (eeprom->word_size == 0) |
5269 | e1000_init_eeprom_params(hw); | 3911 | e1000_init_eeprom_params(hw); |
5270 | 3912 | ||
5271 | /* A check for invalid values: offset too large, too many words, and not | 3913 | /* A check for invalid values: offset too large, too many words, and not |
5272 | * enough words. | 3914 | * enough words. |
5273 | */ | 3915 | */ |
5274 | if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || | 3916 | if ((offset >= eeprom->word_size) |
5275 | (words == 0)) { | 3917 | || (words > eeprom->word_size - offset) || (words == 0)) { |
5276 | DEBUGOUT("\"words\" parameter out of bounds\n"); | 3918 | DEBUGOUT("\"words\" parameter out of bounds\n"); |
5277 | return -E1000_ERR_EEPROM; | 3919 | return -E1000_ERR_EEPROM; |
5278 | } | 3920 | } |
5279 | 3921 | ||
5280 | /* 82573 writes only through eewr */ | 3922 | /* Prepare the EEPROM for writing */ |
5281 | if (eeprom->use_eewr) | 3923 | if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) |
5282 | return e1000_write_eeprom_eewr(hw, offset, words, data); | 3924 | return -E1000_ERR_EEPROM; |
5283 | 3925 | ||
5284 | if (eeprom->type == e1000_eeprom_ich8) | 3926 | if (eeprom->type == e1000_eeprom_microwire) { |
5285 | return e1000_write_eeprom_ich8(hw, offset, words, data); | 3927 | status = e1000_write_eeprom_microwire(hw, offset, words, data); |
5286 | 3928 | } else { | |
5287 | /* Prepare the EEPROM for writing */ | 3929 | status = e1000_write_eeprom_spi(hw, offset, words, data); |
5288 | if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) | 3930 | msleep(10); |
5289 | return -E1000_ERR_EEPROM; | 3931 | } |
5290 | 3932 | ||
5291 | if (eeprom->type == e1000_eeprom_microwire) { | 3933 | /* Done with writing */ |
5292 | status = e1000_write_eeprom_microwire(hw, offset, words, data); | 3934 | e1000_release_eeprom(hw); |
5293 | } else { | 3935 | |
5294 | status = e1000_write_eeprom_spi(hw, offset, words, data); | 3936 | return status; |
5295 | msleep(10); | ||
5296 | } | ||
5297 | |||
5298 | /* Done with writing */ | ||
5299 | e1000_release_eeprom(hw); | ||
5300 | |||
5301 | return status; | ||
5302 | } | 3937 | } |
5303 | 3938 | ||
5304 | /****************************************************************************** | 3939 | /** |
5305 | * Writes a 16 bit word to a given offset in an SPI EEPROM. | 3940 | * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM. |
5306 | * | 3941 | * @hw: Struct containing variables accessed by shared code |
5307 | * hw - Struct containing variables accessed by shared code | 3942 | * @offset: offset within the EEPROM to be written to |
5308 | * offset - offset within the EEPROM to be written to | 3943 | * @words: number of words to write |
5309 | * words - number of words to write | 3944 | * @data: pointer to array of 8 bit words to be written to the EEPROM |
5310 | * data - pointer to array of 8 bit words to be written to the EEPROM | 3945 | */ |
5311 | * | ||
5312 | *****************************************************************************/ | ||
5313 | static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words, | 3946 | static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words, |
5314 | u16 *data) | 3947 | u16 *data) |
5315 | { | 3948 | { |
5316 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | 3949 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
5317 | u16 widx = 0; | 3950 | u16 widx = 0; |
5318 | 3951 | ||
5319 | DEBUGFUNC("e1000_write_eeprom_spi"); | 3952 | DEBUGFUNC("e1000_write_eeprom_spi"); |
5320 | 3953 | ||
5321 | while (widx < words) { | 3954 | while (widx < words) { |
5322 | u8 write_opcode = EEPROM_WRITE_OPCODE_SPI; | 3955 | u8 write_opcode = EEPROM_WRITE_OPCODE_SPI; |
5323 | 3956 | ||
5324 | if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; | 3957 | if (e1000_spi_eeprom_ready(hw)) |
3958 | return -E1000_ERR_EEPROM; | ||
5325 | 3959 | ||
5326 | e1000_standby_eeprom(hw); | 3960 | e1000_standby_eeprom(hw); |
5327 | 3961 | ||
5328 | /* Send the WRITE ENABLE command (8 bit opcode ) */ | 3962 | /* Send the WRITE ENABLE command (8 bit opcode ) */ |
5329 | e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, | 3963 | e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, |
5330 | eeprom->opcode_bits); | 3964 | eeprom->opcode_bits); |
5331 | 3965 | ||
5332 | e1000_standby_eeprom(hw); | 3966 | e1000_standby_eeprom(hw); |
5333 | 3967 | ||
5334 | /* Some SPI eeproms use the 8th address bit embedded in the opcode */ | 3968 | /* Some SPI eeproms use the 8th address bit embedded in the opcode */ |
5335 | if ((eeprom->address_bits == 8) && (offset >= 128)) | 3969 | if ((eeprom->address_bits == 8) && (offset >= 128)) |
5336 | write_opcode |= EEPROM_A8_OPCODE_SPI; | 3970 | write_opcode |= EEPROM_A8_OPCODE_SPI; |
5337 | 3971 | ||
5338 | /* Send the Write command (8-bit opcode + addr) */ | 3972 | /* Send the Write command (8-bit opcode + addr) */ |
5339 | e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); | 3973 | e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); |
5340 | 3974 | ||
5341 | e1000_shift_out_ee_bits(hw, (u16)((offset + widx)*2), | 3975 | e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2), |
5342 | eeprom->address_bits); | 3976 | eeprom->address_bits); |
5343 | 3977 | ||
5344 | /* Send the data */ | 3978 | /* Send the data */ |
5345 | 3979 | ||
5346 | /* Loop to allow for up to whole page write (32 bytes) of eeprom */ | 3980 | /* Loop to allow for up to whole page write (32 bytes) of eeprom */ |
5347 | while (widx < words) { | 3981 | while (widx < words) { |
5348 | u16 word_out = data[widx]; | 3982 | u16 word_out = data[widx]; |
5349 | word_out = (word_out >> 8) | (word_out << 8); | 3983 | word_out = (word_out >> 8) | (word_out << 8); |
5350 | e1000_shift_out_ee_bits(hw, word_out, 16); | 3984 | e1000_shift_out_ee_bits(hw, word_out, 16); |
5351 | widx++; | 3985 | widx++; |
5352 | 3986 | ||
5353 | /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE | 3987 | /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE |
5354 | * operation, while the smaller eeproms are capable of an 8-byte | 3988 | * operation, while the smaller eeproms are capable of an 8-byte |
5355 | * PAGE WRITE operation. Break the inner loop to pass new address | 3989 | * PAGE WRITE operation. Break the inner loop to pass new address |
5356 | */ | 3990 | */ |
5357 | if ((((offset + widx)*2) % eeprom->page_size) == 0) { | 3991 | if ((((offset + widx) * 2) % eeprom->page_size) == 0) { |
5358 | e1000_standby_eeprom(hw); | 3992 | e1000_standby_eeprom(hw); |
5359 | break; | 3993 | break; |
5360 | } | 3994 | } |
5361 | } | 3995 | } |
5362 | } | 3996 | } |
5363 | 3997 | ||
5364 | return E1000_SUCCESS; | 3998 | return E1000_SUCCESS; |
5365 | } | 3999 | } |
5366 | 4000 | ||
5367 | /****************************************************************************** | 4001 | /** |
5368 | * Writes a 16 bit word to a given offset in a Microwire EEPROM. | 4002 | * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM. |
5369 | * | 4003 | * @hw: Struct containing variables accessed by shared code |
5370 | * hw - Struct containing variables accessed by shared code | 4004 | * @offset: offset within the EEPROM to be written to |
5371 | * offset - offset within the EEPROM to be written to | 4005 | * @words: number of words to write |
5372 | * words - number of words to write | 4006 | * @data: pointer to array of 8 bit words to be written to the EEPROM |
5373 | * data - pointer to array of 16 bit words to be written to the EEPROM | 4007 | */ |
5374 | * | ||
5375 | *****************************************************************************/ | ||
5376 | static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, | 4008 | static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, |
5377 | u16 words, u16 *data) | 4009 | u16 words, u16 *data) |
5378 | { | 4010 | { |
5379 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | 4011 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
5380 | u32 eecd; | 4012 | u32 eecd; |
5381 | u16 words_written = 0; | 4013 | u16 words_written = 0; |
5382 | u16 i = 0; | 4014 | u16 i = 0; |
5383 | |||
5384 | DEBUGFUNC("e1000_write_eeprom_microwire"); | ||
5385 | |||
5386 | /* Send the write enable command to the EEPROM (3-bit opcode plus | ||
5387 | * 6/8-bit dummy address beginning with 11). It's less work to include | ||
5388 | * the 11 of the dummy address as part of the opcode than it is to shift | ||
5389 | * it over the correct number of bits for the address. This puts the | ||
5390 | * EEPROM into write/erase mode. | ||
5391 | */ | ||
5392 | e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, | ||
5393 | (u16)(eeprom->opcode_bits + 2)); | ||
5394 | |||
5395 | e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2)); | ||
5396 | |||
5397 | /* Prepare the EEPROM */ | ||
5398 | e1000_standby_eeprom(hw); | ||
5399 | |||
5400 | while (words_written < words) { | ||
5401 | /* Send the Write command (3-bit opcode + addr) */ | ||
5402 | e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, | ||
5403 | eeprom->opcode_bits); | ||
5404 | |||
5405 | e1000_shift_out_ee_bits(hw, (u16)(offset + words_written), | ||
5406 | eeprom->address_bits); | ||
5407 | |||
5408 | /* Send the data */ | ||
5409 | e1000_shift_out_ee_bits(hw, data[words_written], 16); | ||
5410 | |||
5411 | /* Toggle the CS line. This in effect tells the EEPROM to execute | ||
5412 | * the previous command. | ||
5413 | */ | ||
5414 | e1000_standby_eeprom(hw); | ||
5415 | |||
5416 | /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will | ||
5417 | * signal that the command has been completed by raising the DO signal. | ||
5418 | * If DO does not go high in 10 milliseconds, then error out. | ||
5419 | */ | ||
5420 | for (i = 0; i < 200; i++) { | ||
5421 | eecd = er32(EECD); | ||
5422 | if (eecd & E1000_EECD_DO) break; | ||
5423 | udelay(50); | ||
5424 | } | ||
5425 | if (i == 200) { | ||
5426 | DEBUGOUT("EEPROM Write did not complete\n"); | ||
5427 | return -E1000_ERR_EEPROM; | ||
5428 | } | ||
5429 | |||
5430 | /* Recover from write */ | ||
5431 | e1000_standby_eeprom(hw); | ||
5432 | |||
5433 | words_written++; | ||
5434 | } | ||
5435 | |||
5436 | /* Send the write disable command to the EEPROM (3-bit opcode plus | ||
5437 | * 6/8-bit dummy address beginning with 10). It's less work to include | ||
5438 | * the 10 of the dummy address as part of the opcode than it is to shift | ||
5439 | * it over the correct number of bits for the address. This takes the | ||
5440 | * EEPROM out of write/erase mode. | ||
5441 | */ | ||
5442 | e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, | ||
5443 | (u16)(eeprom->opcode_bits + 2)); | ||
5444 | |||
5445 | e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2)); | ||
5446 | |||
5447 | return E1000_SUCCESS; | ||
5448 | } | ||
5449 | 4015 | ||
5450 | /****************************************************************************** | 4016 | DEBUGFUNC("e1000_write_eeprom_microwire"); |
5451 | * Flushes the cached eeprom to NVM. This is done by saving the modified values | 4017 | |
5452 | * in the eeprom cache and the non modified values in the currently active bank | 4018 | /* Send the write enable command to the EEPROM (3-bit opcode plus |
5453 | * to the new bank. | 4019 | * 6/8-bit dummy address beginning with 11). It's less work to include |
5454 | * | 4020 | * the 11 of the dummy address as part of the opcode than it is to shift |
5455 | * hw - Struct containing variables accessed by shared code | 4021 | * it over the correct number of bits for the address. This puts the |
5456 | * offset - offset of word in the EEPROM to read | 4022 | * EEPROM into write/erase mode. |
5457 | * data - word read from the EEPROM | 4023 | */ |
5458 | * words - number of words to read | 4024 | e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, |
5459 | *****************************************************************************/ | 4025 | (u16) (eeprom->opcode_bits + 2)); |
5460 | static s32 e1000_commit_shadow_ram(struct e1000_hw *hw) | 4026 | |
5461 | { | 4027 | e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2)); |
5462 | u32 attempts = 100000; | 4028 | |
5463 | u32 eecd = 0; | 4029 | /* Prepare the EEPROM */ |
5464 | u32 flop = 0; | 4030 | e1000_standby_eeprom(hw); |
5465 | u32 i = 0; | 4031 | |
5466 | s32 error = E1000_SUCCESS; | 4032 | while (words_written < words) { |
5467 | u32 old_bank_offset = 0; | 4033 | /* Send the Write command (3-bit opcode + addr) */ |
5468 | u32 new_bank_offset = 0; | 4034 | e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, |
5469 | u8 low_byte = 0; | 4035 | eeprom->opcode_bits); |
5470 | u8 high_byte = 0; | 4036 | |
5471 | bool sector_write_failed = false; | 4037 | e1000_shift_out_ee_bits(hw, (u16) (offset + words_written), |
5472 | 4038 | eeprom->address_bits); | |
5473 | if (hw->mac_type == e1000_82573) { | 4039 | |
5474 | /* The flop register will be used to determine if flash type is STM */ | 4040 | /* Send the data */ |
5475 | flop = er32(FLOP); | 4041 | e1000_shift_out_ee_bits(hw, data[words_written], 16); |
5476 | for (i=0; i < attempts; i++) { | 4042 | |
5477 | eecd = er32(EECD); | 4043 | /* Toggle the CS line. This in effect tells the EEPROM to execute |
5478 | if ((eecd & E1000_EECD_FLUPD) == 0) { | 4044 | * the previous command. |
5479 | break; | 4045 | */ |
5480 | } | 4046 | e1000_standby_eeprom(hw); |
5481 | udelay(5); | 4047 | |
5482 | } | 4048 | /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will |
5483 | 4049 | * signal that the command has been completed by raising the DO signal. | |
5484 | if (i == attempts) { | 4050 | * If DO does not go high in 10 milliseconds, then error out. |
5485 | return -E1000_ERR_EEPROM; | 4051 | */ |
5486 | } | 4052 | for (i = 0; i < 200; i++) { |
5487 | 4053 | eecd = er32(EECD); | |
5488 | /* If STM opcode located in bits 15:8 of flop, reset firmware */ | 4054 | if (eecd & E1000_EECD_DO) |
5489 | if ((flop & 0xFF00) == E1000_STM_OPCODE) { | 4055 | break; |
5490 | ew32(HICR, E1000_HICR_FW_RESET); | 4056 | udelay(50); |
5491 | } | 4057 | } |
5492 | 4058 | if (i == 200) { | |
5493 | /* Perform the flash update */ | 4059 | DEBUGOUT("EEPROM Write did not complete\n"); |
5494 | ew32(EECD, eecd | E1000_EECD_FLUPD); | 4060 | return -E1000_ERR_EEPROM; |
5495 | 4061 | } | |
5496 | for (i=0; i < attempts; i++) { | 4062 | |
5497 | eecd = er32(EECD); | 4063 | /* Recover from write */ |
5498 | if ((eecd & E1000_EECD_FLUPD) == 0) { | 4064 | e1000_standby_eeprom(hw); |
5499 | break; | 4065 | |
5500 | } | 4066 | words_written++; |
5501 | udelay(5); | 4067 | } |
5502 | } | 4068 | |
5503 | 4069 | /* Send the write disable command to the EEPROM (3-bit opcode plus | |
5504 | if (i == attempts) { | 4070 | * 6/8-bit dummy address beginning with 10). It's less work to include |
5505 | return -E1000_ERR_EEPROM; | 4071 | * the 10 of the dummy address as part of the opcode than it is to shift |
5506 | } | 4072 | * it over the correct number of bits for the address. This takes the |
5507 | } | 4073 | * EEPROM out of write/erase mode. |
5508 | 4074 | */ | |
5509 | if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) { | 4075 | e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, |
5510 | /* We're writing to the opposite bank so if we're on bank 1, | 4076 | (u16) (eeprom->opcode_bits + 2)); |
5511 | * write to bank 0 etc. We also need to erase the segment that | 4077 | |
5512 | * is going to be written */ | 4078 | e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2)); |
5513 | if (!(er32(EECD) & E1000_EECD_SEC1VAL)) { | 4079 | |
5514 | new_bank_offset = hw->flash_bank_size * 2; | 4080 | return E1000_SUCCESS; |
5515 | old_bank_offset = 0; | ||
5516 | e1000_erase_ich8_4k_segment(hw, 1); | ||
5517 | } else { | ||
5518 | old_bank_offset = hw->flash_bank_size * 2; | ||
5519 | new_bank_offset = 0; | ||
5520 | e1000_erase_ich8_4k_segment(hw, 0); | ||
5521 | } | ||
5522 | |||
5523 | sector_write_failed = false; | ||
5524 | /* Loop for every byte in the shadow RAM, | ||
5525 | * which is in units of words. */ | ||
5526 | for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { | ||
5527 | /* Determine whether to write the value stored | ||
5528 | * in the other NVM bank or a modified value stored | ||
5529 | * in the shadow RAM */ | ||
5530 | if (hw->eeprom_shadow_ram[i].modified) { | ||
5531 | low_byte = (u8)hw->eeprom_shadow_ram[i].eeprom_word; | ||
5532 | udelay(100); | ||
5533 | error = e1000_verify_write_ich8_byte(hw, | ||
5534 | (i << 1) + new_bank_offset, low_byte); | ||
5535 | |||
5536 | if (error != E1000_SUCCESS) | ||
5537 | sector_write_failed = true; | ||
5538 | else { | ||
5539 | high_byte = | ||
5540 | (u8)(hw->eeprom_shadow_ram[i].eeprom_word >> 8); | ||
5541 | udelay(100); | ||
5542 | } | ||
5543 | } else { | ||
5544 | e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset, | ||
5545 | &low_byte); | ||
5546 | udelay(100); | ||
5547 | error = e1000_verify_write_ich8_byte(hw, | ||
5548 | (i << 1) + new_bank_offset, low_byte); | ||
5549 | |||
5550 | if (error != E1000_SUCCESS) | ||
5551 | sector_write_failed = true; | ||
5552 | else { | ||
5553 | e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1, | ||
5554 | &high_byte); | ||
5555 | udelay(100); | ||
5556 | } | ||
5557 | } | ||
5558 | |||
5559 | /* If the write of the low byte was successful, go ahead and | ||
5560 | * write the high byte while checking to make sure that if it | ||
5561 | * is the signature byte, then it is handled properly */ | ||
5562 | if (!sector_write_failed) { | ||
5563 | /* If the word is 0x13, then make sure the signature bits | ||
5564 | * (15:14) are 11b until the commit has completed. | ||
5565 | * This will allow us to write 10b which indicates the | ||
5566 | * signature is valid. We want to do this after the write | ||
5567 | * has completed so that we don't mark the segment valid | ||
5568 | * while the write is still in progress */ | ||
5569 | if (i == E1000_ICH_NVM_SIG_WORD) | ||
5570 | high_byte = E1000_ICH_NVM_SIG_MASK | high_byte; | ||
5571 | |||
5572 | error = e1000_verify_write_ich8_byte(hw, | ||
5573 | (i << 1) + new_bank_offset + 1, high_byte); | ||
5574 | if (error != E1000_SUCCESS) | ||
5575 | sector_write_failed = true; | ||
5576 | |||
5577 | } else { | ||
5578 | /* If the write failed then break from the loop and | ||
5579 | * return an error */ | ||
5580 | break; | ||
5581 | } | ||
5582 | } | ||
5583 | |||
5584 | /* Don't bother writing the segment valid bits if sector | ||
5585 | * programming failed. */ | ||
5586 | if (!sector_write_failed) { | ||
5587 | /* Finally validate the new segment by setting bit 15:14 | ||
5588 | * to 10b in word 0x13 , this can be done without an | ||
5589 | * erase as well since these bits are 11 to start with | ||
5590 | * and we need to change bit 14 to 0b */ | ||
5591 | e1000_read_ich8_byte(hw, | ||
5592 | E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, | ||
5593 | &high_byte); | ||
5594 | high_byte &= 0xBF; | ||
5595 | error = e1000_verify_write_ich8_byte(hw, | ||
5596 | E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte); | ||
5597 | /* And invalidate the previously valid segment by setting | ||
5598 | * its signature word (0x13) high_byte to 0b. This can be | ||
5599 | * done without an erase because flash erase sets all bits | ||
5600 | * to 1's. We can write 1's to 0's without an erase */ | ||
5601 | if (error == E1000_SUCCESS) { | ||
5602 | error = e1000_verify_write_ich8_byte(hw, | ||
5603 | E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0); | ||
5604 | } | ||
5605 | |||
5606 | /* Clear the now not used entry in the cache */ | ||
5607 | for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { | ||
5608 | hw->eeprom_shadow_ram[i].modified = false; | ||
5609 | hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; | ||
5610 | } | ||
5611 | } | ||
5612 | } | ||
5613 | |||
5614 | return error; | ||
5615 | } | 4081 | } |
5616 | 4082 | ||
5617 | /****************************************************************************** | 4083 | /** |
4084 | * e1000_read_mac_addr - read the adapters MAC from eeprom | ||
4085 | * @hw: Struct containing variables accessed by shared code | ||
4086 | * | ||
5618 | * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the | 4087 | * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the |
5619 | * second function of dual function devices | 4088 | * second function of dual function devices |
5620 | * | 4089 | */ |
5621 | * hw - Struct containing variables accessed by shared code | ||
5622 | *****************************************************************************/ | ||
5623 | s32 e1000_read_mac_addr(struct e1000_hw *hw) | 4090 | s32 e1000_read_mac_addr(struct e1000_hw *hw) |
5624 | { | 4091 | { |
5625 | u16 offset; | 4092 | u16 offset; |
5626 | u16 eeprom_data, i; | 4093 | u16 eeprom_data, i; |
5627 | 4094 | ||
5628 | DEBUGFUNC("e1000_read_mac_addr"); | 4095 | DEBUGFUNC("e1000_read_mac_addr"); |
5629 | 4096 | ||
5630 | for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { | 4097 | for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { |
5631 | offset = i >> 1; | 4098 | offset = i >> 1; |
5632 | if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { | 4099 | if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { |
5633 | DEBUGOUT("EEPROM Read Error\n"); | 4100 | DEBUGOUT("EEPROM Read Error\n"); |
5634 | return -E1000_ERR_EEPROM; | 4101 | return -E1000_ERR_EEPROM; |
5635 | } | 4102 | } |
5636 | hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF); | 4103 | hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF); |
5637 | hw->perm_mac_addr[i+1] = (u8)(eeprom_data >> 8); | 4104 | hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8); |
5638 | } | 4105 | } |
5639 | 4106 | ||
5640 | switch (hw->mac_type) { | 4107 | switch (hw->mac_type) { |
5641 | default: | 4108 | default: |
5642 | break; | 4109 | break; |
5643 | case e1000_82546: | 4110 | case e1000_82546: |
5644 | case e1000_82546_rev_3: | 4111 | case e1000_82546_rev_3: |
5645 | case e1000_82571: | 4112 | if (er32(STATUS) & E1000_STATUS_FUNC_1) |
5646 | case e1000_80003es2lan: | 4113 | hw->perm_mac_addr[5] ^= 0x01; |
5647 | if (er32(STATUS) & E1000_STATUS_FUNC_1) | 4114 | break; |
5648 | hw->perm_mac_addr[5] ^= 0x01; | 4115 | } |
5649 | break; | 4116 | |
5650 | } | 4117 | for (i = 0; i < NODE_ADDRESS_SIZE; i++) |
5651 | 4118 | hw->mac_addr[i] = hw->perm_mac_addr[i]; | |
5652 | for (i = 0; i < NODE_ADDRESS_SIZE; i++) | 4119 | return E1000_SUCCESS; |
5653 | hw->mac_addr[i] = hw->perm_mac_addr[i]; | ||
5654 | return E1000_SUCCESS; | ||
5655 | } | 4120 | } |
5656 | 4121 | ||
5657 | /****************************************************************************** | 4122 | /** |
5658 | * Initializes receive address filters. | 4123 | * e1000_init_rx_addrs - Initializes receive address filters. |
5659 | * | 4124 | * @hw: Struct containing variables accessed by shared code |
5660 | * hw - Struct containing variables accessed by shared code | ||
5661 | * | 4125 | * |
5662 | * Places the MAC address in receive address register 0 and clears the rest | 4126 | * Places the MAC address in receive address register 0 and clears the rest |
5663 | * of the receive addresss registers. Clears the multicast table. Assumes | 4127 | * of the receive address registers. Clears the multicast table. Assumes |
5664 | * the receiver is in reset when the routine is called. | 4128 | * the receiver is in reset when the routine is called. |
5665 | *****************************************************************************/ | 4129 | */ |
5666 | static void e1000_init_rx_addrs(struct e1000_hw *hw) | 4130 | static void e1000_init_rx_addrs(struct e1000_hw *hw) |
5667 | { | 4131 | { |
5668 | u32 i; | 4132 | u32 i; |
5669 | u32 rar_num; | 4133 | u32 rar_num; |
5670 | 4134 | ||
5671 | DEBUGFUNC("e1000_init_rx_addrs"); | 4135 | DEBUGFUNC("e1000_init_rx_addrs"); |
5672 | 4136 | ||
5673 | /* Setup the receive address. */ | 4137 | /* Setup the receive address. */ |
5674 | DEBUGOUT("Programming MAC Address into RAR[0]\n"); | 4138 | DEBUGOUT("Programming MAC Address into RAR[0]\n"); |
5675 | 4139 | ||
5676 | e1000_rar_set(hw, hw->mac_addr, 0); | 4140 | e1000_rar_set(hw, hw->mac_addr, 0); |
5677 | 4141 | ||
5678 | rar_num = E1000_RAR_ENTRIES; | 4142 | rar_num = E1000_RAR_ENTRIES; |
5679 | 4143 | ||
5680 | /* Reserve a spot for the Locally Administered Address to work around | 4144 | /* Zero out the other 15 receive addresses. */ |
5681 | * an 82571 issue in which a reset on one port will reload the MAC on | 4145 | DEBUGOUT("Clearing RAR[1-15]\n"); |
5682 | * the other port. */ | 4146 | for (i = 1; i < rar_num; i++) { |
5683 | if ((hw->mac_type == e1000_82571) && (hw->laa_is_present)) | 4147 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); |
5684 | rar_num -= 1; | 4148 | E1000_WRITE_FLUSH(); |
5685 | if (hw->mac_type == e1000_ich8lan) | 4149 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); |
5686 | rar_num = E1000_RAR_ENTRIES_ICH8LAN; | 4150 | E1000_WRITE_FLUSH(); |
5687 | 4151 | } | |
5688 | /* Zero out the other 15 receive addresses. */ | ||
5689 | DEBUGOUT("Clearing RAR[1-15]\n"); | ||
5690 | for (i = 1; i < rar_num; i++) { | ||
5691 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); | ||
5692 | E1000_WRITE_FLUSH(); | ||
5693 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); | ||
5694 | E1000_WRITE_FLUSH(); | ||
5695 | } | ||
5696 | } | 4152 | } |
5697 | 4153 | ||
5698 | /****************************************************************************** | 4154 | /** |
5699 | * Hashes an address to determine its location in the multicast table | 4155 | * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table |
5700 | * | 4156 | * @hw: Struct containing variables accessed by shared code |
5701 | * hw - Struct containing variables accessed by shared code | 4157 | * @mc_addr: the multicast address to hash |
5702 | * mc_addr - the multicast address to hash | 4158 | */ |
5703 | *****************************************************************************/ | ||
5704 | u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) | 4159 | u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) |
5705 | { | 4160 | { |
5706 | u32 hash_value = 0; | 4161 | u32 hash_value = 0; |
5707 | 4162 | ||
5708 | /* The portion of the address that is used for the hash table is | 4163 | /* The portion of the address that is used for the hash table is |
5709 | * determined by the mc_filter_type setting. | 4164 | * determined by the mc_filter_type setting. |
5710 | */ | 4165 | */ |
5711 | switch (hw->mc_filter_type) { | 4166 | switch (hw->mc_filter_type) { |
5712 | /* [0] [1] [2] [3] [4] [5] | 4167 | /* [0] [1] [2] [3] [4] [5] |
5713 | * 01 AA 00 12 34 56 | 4168 | * 01 AA 00 12 34 56 |
5714 | * LSB MSB | 4169 | * LSB MSB |
5715 | */ | 4170 | */ |
5716 | case 0: | 4171 | case 0: |
5717 | if (hw->mac_type == e1000_ich8lan) { | 4172 | /* [47:36] i.e. 0x563 for above example address */ |
5718 | /* [47:38] i.e. 0x158 for above example address */ | 4173 | hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4)); |
5719 | hash_value = ((mc_addr[4] >> 6) | (((u16)mc_addr[5]) << 2)); | 4174 | break; |
5720 | } else { | 4175 | case 1: |
5721 | /* [47:36] i.e. 0x563 for above example address */ | 4176 | /* [46:35] i.e. 0xAC6 for above example address */ |
5722 | hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); | 4177 | hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5)); |
5723 | } | 4178 | break; |
5724 | break; | 4179 | case 2: |
5725 | case 1: | 4180 | /* [45:34] i.e. 0x5D8 for above example address */ |
5726 | if (hw->mac_type == e1000_ich8lan) { | 4181 | hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6)); |
5727 | /* [46:37] i.e. 0x2B1 for above example address */ | 4182 | break; |
5728 | hash_value = ((mc_addr[4] >> 5) | (((u16)mc_addr[5]) << 3)); | 4183 | case 3: |
5729 | } else { | 4184 | /* [43:32] i.e. 0x634 for above example address */ |
5730 | /* [46:35] i.e. 0xAC6 for above example address */ | 4185 | hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8)); |
5731 | hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); | 4186 | break; |
5732 | } | 4187 | } |
5733 | break; | 4188 | |
5734 | case 2: | 4189 | hash_value &= 0xFFF; |
5735 | if (hw->mac_type == e1000_ich8lan) { | 4190 | return hash_value; |
5736 | /*[45:36] i.e. 0x163 for above example address */ | ||
5737 | hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); | ||
5738 | } else { | ||
5739 | /* [45:34] i.e. 0x5D8 for above example address */ | ||
5740 | hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); | ||
5741 | } | ||
5742 | break; | ||
5743 | case 3: | ||
5744 | if (hw->mac_type == e1000_ich8lan) { | ||
5745 | /* [43:34] i.e. 0x18D for above example address */ | ||
5746 | hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); | ||
5747 | } else { | ||
5748 | /* [43:32] i.e. 0x634 for above example address */ | ||
5749 | hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); | ||
5750 | } | ||
5751 | break; | ||
5752 | } | ||
5753 | |||
5754 | hash_value &= 0xFFF; | ||
5755 | if (hw->mac_type == e1000_ich8lan) | ||
5756 | hash_value &= 0x3FF; | ||
5757 | |||
5758 | return hash_value; | ||
5759 | } | 4191 | } |
5760 | 4192 | ||
5761 | /****************************************************************************** | 4193 | /** |
5762 | * Puts an ethernet address into a receive address register. | 4194 | * e1000_rar_set - Puts an ethernet address into a receive address register. |
5763 | * | 4195 | * @hw: Struct containing variables accessed by shared code |
5764 | * hw - Struct containing variables accessed by shared code | 4196 | * @addr: Address to put into receive address register |
5765 | * addr - Address to put into receive address register | 4197 | * @index: Receive address register to write |
5766 | * index - Receive address register to write | 4198 | */ |
5767 | *****************************************************************************/ | ||
5768 | void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) | 4199 | void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) |
5769 | { | 4200 | { |
5770 | u32 rar_low, rar_high; | 4201 | u32 rar_low, rar_high; |
5771 | 4202 | ||
5772 | /* HW expects these in little endian so we reverse the byte order | 4203 | /* HW expects these in little endian so we reverse the byte order |
5773 | * from network order (big endian) to little endian | 4204 | * from network order (big endian) to little endian |
5774 | */ | 4205 | */ |
5775 | rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | | 4206 | rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | |
5776 | ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); | 4207 | ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); |
5777 | rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); | 4208 | rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); |
5778 | 4209 | ||
5779 | /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx | 4210 | /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx |
5780 | * unit hang. | 4211 | * unit hang. |
5781 | * | 4212 | * |
5782 | * Description: | 4213 | * Description: |
5783 | * If there are any Rx frames queued up or otherwise present in the HW | 4214 | * If there are any Rx frames queued up or otherwise present in the HW |
5784 | * before RSS is enabled, and then we enable RSS, the HW Rx unit will | 4215 | * before RSS is enabled, and then we enable RSS, the HW Rx unit will |
5785 | * hang. To work around this issue, we have to disable receives and | 4216 | * hang. To work around this issue, we have to disable receives and |
5786 | * flush out all Rx frames before we enable RSS. To do so, we modify we | 4217 | * flush out all Rx frames before we enable RSS. To do so, we modify we |
5787 | * redirect all Rx traffic to manageability and then reset the HW. | 4218 | * redirect all Rx traffic to manageability and then reset the HW. |
5788 | * This flushes away Rx frames, and (since the redirections to | 4219 | * This flushes away Rx frames, and (since the redirections to |
5789 | * manageability persists across resets) keeps new ones from coming in | 4220 | * manageability persists across resets) keeps new ones from coming in |
5790 | * while we work. Then, we clear the Address Valid AV bit for all MAC | 4221 | * while we work. Then, we clear the Address Valid AV bit for all MAC |
5791 | * addresses and undo the re-direction to manageability. | 4222 | * addresses and undo the re-direction to manageability. |
5792 | * Now, frames are coming in again, but the MAC won't accept them, so | 4223 | * Now, frames are coming in again, but the MAC won't accept them, so |
5793 | * far so good. We now proceed to initialize RSS (if necessary) and | 4224 | * far so good. We now proceed to initialize RSS (if necessary) and |
5794 | * configure the Rx unit. Last, we re-enable the AV bits and continue | 4225 | * configure the Rx unit. Last, we re-enable the AV bits and continue |
5795 | * on our merry way. | 4226 | * on our merry way. |
5796 | */ | 4227 | */ |
5797 | switch (hw->mac_type) { | 4228 | switch (hw->mac_type) { |
5798 | case e1000_82571: | 4229 | default: |
5799 | case e1000_82572: | 4230 | /* Indicate to hardware the Address is Valid. */ |
5800 | case e1000_80003es2lan: | 4231 | rar_high |= E1000_RAH_AV; |
5801 | if (hw->leave_av_bit_off) | 4232 | break; |
5802 | break; | 4233 | } |
5803 | default: | 4234 | |
5804 | /* Indicate to hardware the Address is Valid. */ | 4235 | E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); |
5805 | rar_high |= E1000_RAH_AV; | 4236 | E1000_WRITE_FLUSH(); |
5806 | break; | 4237 | E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); |
5807 | } | 4238 | E1000_WRITE_FLUSH(); |
5808 | |||
5809 | E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); | ||
5810 | E1000_WRITE_FLUSH(); | ||
5811 | E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); | ||
5812 | E1000_WRITE_FLUSH(); | ||
5813 | } | 4239 | } |
5814 | 4240 | ||
5815 | /****************************************************************************** | 4241 | /** |
5816 | * Writes a value to the specified offset in the VLAN filter table. | 4242 | * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table. |
5817 | * | 4243 | * @hw: Struct containing variables accessed by shared code |
5818 | * hw - Struct containing variables accessed by shared code | 4244 | * @offset: Offset in VLAN filer table to write |
5819 | * offset - Offset in VLAN filer table to write | 4245 | * @value: Value to write into VLAN filter table |
5820 | * value - Value to write into VLAN filter table | 4246 | */ |
5821 | *****************************************************************************/ | ||
5822 | void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) | 4247 | void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) |
5823 | { | 4248 | { |
5824 | u32 temp; | 4249 | u32 temp; |
5825 | 4250 | ||
5826 | if (hw->mac_type == e1000_ich8lan) | 4251 | if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { |
5827 | return; | 4252 | temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); |
5828 | 4253 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); | |
5829 | if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { | 4254 | E1000_WRITE_FLUSH(); |
5830 | temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); | 4255 | E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); |
5831 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); | 4256 | E1000_WRITE_FLUSH(); |
5832 | E1000_WRITE_FLUSH(); | 4257 | } else { |
5833 | E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); | 4258 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); |
5834 | E1000_WRITE_FLUSH(); | 4259 | E1000_WRITE_FLUSH(); |
5835 | } else { | 4260 | } |
5836 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); | ||
5837 | E1000_WRITE_FLUSH(); | ||
5838 | } | ||
5839 | } | 4261 | } |
5840 | 4262 | ||
5841 | /****************************************************************************** | 4263 | /** |
5842 | * Clears the VLAN filer table | 4264 | * e1000_clear_vfta - Clears the VLAN filer table |
5843 | * | 4265 | * @hw: Struct containing variables accessed by shared code |
5844 | * hw - Struct containing variables accessed by shared code | 4266 | */ |
5845 | *****************************************************************************/ | ||
5846 | static void e1000_clear_vfta(struct e1000_hw *hw) | 4267 | static void e1000_clear_vfta(struct e1000_hw *hw) |
5847 | { | 4268 | { |
5848 | u32 offset; | 4269 | u32 offset; |
5849 | u32 vfta_value = 0; | 4270 | u32 vfta_value = 0; |
5850 | u32 vfta_offset = 0; | 4271 | u32 vfta_offset = 0; |
5851 | u32 vfta_bit_in_reg = 0; | 4272 | u32 vfta_bit_in_reg = 0; |
5852 | 4273 | ||
5853 | if (hw->mac_type == e1000_ich8lan) | 4274 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { |
5854 | return; | 4275 | /* If the offset we want to clear is the same offset of the |
5855 | 4276 | * manageability VLAN ID, then clear all bits except that of the | |
5856 | if (hw->mac_type == e1000_82573) { | 4277 | * manageability unit */ |
5857 | if (hw->mng_cookie.vlan_id != 0) { | 4278 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; |
5858 | /* The VFTA is a 4096b bit-field, each identifying a single VLAN | 4279 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); |
5859 | * ID. The following operations determine which 32b entry | 4280 | E1000_WRITE_FLUSH(); |
5860 | * (i.e. offset) into the array we want to set the VLAN ID | 4281 | } |
5861 | * (i.e. bit) of the manageability unit. */ | ||
5862 | vfta_offset = (hw->mng_cookie.vlan_id >> | ||
5863 | E1000_VFTA_ENTRY_SHIFT) & | ||
5864 | E1000_VFTA_ENTRY_MASK; | ||
5865 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & | ||
5866 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); | ||
5867 | } | ||
5868 | } | ||
5869 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | ||
5870 | /* If the offset we want to clear is the same offset of the | ||
5871 | * manageability VLAN ID, then clear all bits except that of the | ||
5872 | * manageability unit */ | ||
5873 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; | ||
5874 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); | ||
5875 | E1000_WRITE_FLUSH(); | ||
5876 | } | ||
5877 | } | 4282 | } |
5878 | 4283 | ||
5879 | static s32 e1000_id_led_init(struct e1000_hw *hw) | 4284 | static s32 e1000_id_led_init(struct e1000_hw *hw) |
5880 | { | 4285 | { |
5881 | u32 ledctl; | 4286 | u32 ledctl; |
5882 | const u32 ledctl_mask = 0x000000FF; | 4287 | const u32 ledctl_mask = 0x000000FF; |
5883 | const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; | 4288 | const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; |
5884 | const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; | 4289 | const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; |
5885 | u16 eeprom_data, i, temp; | 4290 | u16 eeprom_data, i, temp; |
5886 | const u16 led_mask = 0x0F; | 4291 | const u16 led_mask = 0x0F; |
5887 | 4292 | ||
5888 | DEBUGFUNC("e1000_id_led_init"); | 4293 | DEBUGFUNC("e1000_id_led_init"); |
5889 | 4294 | ||
5890 | if (hw->mac_type < e1000_82540) { | 4295 | if (hw->mac_type < e1000_82540) { |
5891 | /* Nothing to do */ | 4296 | /* Nothing to do */ |
5892 | return E1000_SUCCESS; | 4297 | return E1000_SUCCESS; |
5893 | } | 4298 | } |
5894 | 4299 | ||
5895 | ledctl = er32(LEDCTL); | 4300 | ledctl = er32(LEDCTL); |
5896 | hw->ledctl_default = ledctl; | 4301 | hw->ledctl_default = ledctl; |
5897 | hw->ledctl_mode1 = hw->ledctl_default; | 4302 | hw->ledctl_mode1 = hw->ledctl_default; |
5898 | hw->ledctl_mode2 = hw->ledctl_default; | 4303 | hw->ledctl_mode2 = hw->ledctl_default; |
5899 | 4304 | ||
5900 | if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { | 4305 | if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { |
5901 | DEBUGOUT("EEPROM Read Error\n"); | 4306 | DEBUGOUT("EEPROM Read Error\n"); |
5902 | return -E1000_ERR_EEPROM; | 4307 | return -E1000_ERR_EEPROM; |
5903 | } | 4308 | } |
5904 | 4309 | ||
5905 | if ((hw->mac_type == e1000_82573) && | 4310 | if ((eeprom_data == ID_LED_RESERVED_0000) || |
5906 | (eeprom_data == ID_LED_RESERVED_82573)) | 4311 | (eeprom_data == ID_LED_RESERVED_FFFF)) { |
5907 | eeprom_data = ID_LED_DEFAULT_82573; | 4312 | eeprom_data = ID_LED_DEFAULT; |
5908 | else if ((eeprom_data == ID_LED_RESERVED_0000) || | 4313 | } |
5909 | (eeprom_data == ID_LED_RESERVED_FFFF)) { | 4314 | |
5910 | if (hw->mac_type == e1000_ich8lan) | 4315 | for (i = 0; i < 4; i++) { |
5911 | eeprom_data = ID_LED_DEFAULT_ICH8LAN; | 4316 | temp = (eeprom_data >> (i << 2)) & led_mask; |
5912 | else | 4317 | switch (temp) { |
5913 | eeprom_data = ID_LED_DEFAULT; | 4318 | case ID_LED_ON1_DEF2: |
5914 | } | 4319 | case ID_LED_ON1_ON2: |
5915 | 4320 | case ID_LED_ON1_OFF2: | |
5916 | for (i = 0; i < 4; i++) { | 4321 | hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
5917 | temp = (eeprom_data >> (i << 2)) & led_mask; | 4322 | hw->ledctl_mode1 |= ledctl_on << (i << 3); |
5918 | switch (temp) { | 4323 | break; |
5919 | case ID_LED_ON1_DEF2: | 4324 | case ID_LED_OFF1_DEF2: |
5920 | case ID_LED_ON1_ON2: | 4325 | case ID_LED_OFF1_ON2: |
5921 | case ID_LED_ON1_OFF2: | 4326 | case ID_LED_OFF1_OFF2: |
5922 | hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); | 4327 | hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
5923 | hw->ledctl_mode1 |= ledctl_on << (i << 3); | 4328 | hw->ledctl_mode1 |= ledctl_off << (i << 3); |
5924 | break; | 4329 | break; |
5925 | case ID_LED_OFF1_DEF2: | 4330 | default: |
5926 | case ID_LED_OFF1_ON2: | 4331 | /* Do nothing */ |
5927 | case ID_LED_OFF1_OFF2: | 4332 | break; |
5928 | hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); | 4333 | } |
5929 | hw->ledctl_mode1 |= ledctl_off << (i << 3); | 4334 | switch (temp) { |
5930 | break; | 4335 | case ID_LED_DEF1_ON2: |
5931 | default: | 4336 | case ID_LED_ON1_ON2: |
5932 | /* Do nothing */ | 4337 | case ID_LED_OFF1_ON2: |
5933 | break; | 4338 | hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
5934 | } | 4339 | hw->ledctl_mode2 |= ledctl_on << (i << 3); |
5935 | switch (temp) { | 4340 | break; |
5936 | case ID_LED_DEF1_ON2: | 4341 | case ID_LED_DEF1_OFF2: |
5937 | case ID_LED_ON1_ON2: | 4342 | case ID_LED_ON1_OFF2: |
5938 | case ID_LED_OFF1_ON2: | 4343 | case ID_LED_OFF1_OFF2: |
5939 | hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); | 4344 | hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
5940 | hw->ledctl_mode2 |= ledctl_on << (i << 3); | 4345 | hw->ledctl_mode2 |= ledctl_off << (i << 3); |
5941 | break; | 4346 | break; |
5942 | case ID_LED_DEF1_OFF2: | 4347 | default: |
5943 | case ID_LED_ON1_OFF2: | 4348 | /* Do nothing */ |
5944 | case ID_LED_OFF1_OFF2: | 4349 | break; |
5945 | hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); | 4350 | } |
5946 | hw->ledctl_mode2 |= ledctl_off << (i << 3); | 4351 | } |
5947 | break; | 4352 | return E1000_SUCCESS; |
5948 | default: | ||
5949 | /* Do nothing */ | ||
5950 | break; | ||
5951 | } | ||
5952 | } | ||
5953 | return E1000_SUCCESS; | ||
5954 | } | 4353 | } |
5955 | 4354 | ||
5956 | /****************************************************************************** | 4355 | /** |
5957 | * Prepares SW controlable LED for use and saves the current state of the LED. | 4356 | * e1000_setup_led |
4357 | * @hw: Struct containing variables accessed by shared code | ||
5958 | * | 4358 | * |
5959 | * hw - Struct containing variables accessed by shared code | 4359 | * Prepares SW controlable LED for use and saves the current state of the LED. |
5960 | *****************************************************************************/ | 4360 | */ |
5961 | s32 e1000_setup_led(struct e1000_hw *hw) | 4361 | s32 e1000_setup_led(struct e1000_hw *hw) |
5962 | { | 4362 | { |
5963 | u32 ledctl; | 4363 | u32 ledctl; |
5964 | s32 ret_val = E1000_SUCCESS; | 4364 | s32 ret_val = E1000_SUCCESS; |
5965 | |||
5966 | DEBUGFUNC("e1000_setup_led"); | ||
5967 | |||
5968 | switch (hw->mac_type) { | ||
5969 | case e1000_82542_rev2_0: | ||
5970 | case e1000_82542_rev2_1: | ||
5971 | case e1000_82543: | ||
5972 | case e1000_82544: | ||
5973 | /* No setup necessary */ | ||
5974 | break; | ||
5975 | case e1000_82541: | ||
5976 | case e1000_82547: | ||
5977 | case e1000_82541_rev_2: | ||
5978 | case e1000_82547_rev_2: | ||
5979 | /* Turn off PHY Smart Power Down (if enabled) */ | ||
5980 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, | ||
5981 | &hw->phy_spd_default); | ||
5982 | if (ret_val) | ||
5983 | return ret_val; | ||
5984 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, | ||
5985 | (u16)(hw->phy_spd_default & | ||
5986 | ~IGP01E1000_GMII_SPD)); | ||
5987 | if (ret_val) | ||
5988 | return ret_val; | ||
5989 | /* Fall Through */ | ||
5990 | default: | ||
5991 | if (hw->media_type == e1000_media_type_fiber) { | ||
5992 | ledctl = er32(LEDCTL); | ||
5993 | /* Save current LEDCTL settings */ | ||
5994 | hw->ledctl_default = ledctl; | ||
5995 | /* Turn off LED0 */ | ||
5996 | ledctl &= ~(E1000_LEDCTL_LED0_IVRT | | ||
5997 | E1000_LEDCTL_LED0_BLINK | | ||
5998 | E1000_LEDCTL_LED0_MODE_MASK); | ||
5999 | ledctl |= (E1000_LEDCTL_MODE_LED_OFF << | ||
6000 | E1000_LEDCTL_LED0_MODE_SHIFT); | ||
6001 | ew32(LEDCTL, ledctl); | ||
6002 | } else if (hw->media_type == e1000_media_type_copper) | ||
6003 | ew32(LEDCTL, hw->ledctl_mode1); | ||
6004 | break; | ||
6005 | } | ||
6006 | |||
6007 | return E1000_SUCCESS; | ||
6008 | } | ||
6009 | 4365 | ||
4366 | DEBUGFUNC("e1000_setup_led"); | ||
6010 | 4367 | ||
6011 | /****************************************************************************** | 4368 | switch (hw->mac_type) { |
6012 | * Used on 82571 and later Si that has LED blink bits. | 4369 | case e1000_82542_rev2_0: |
6013 | * Callers must use their own timer and should have already called | 4370 | case e1000_82542_rev2_1: |
6014 | * e1000_id_led_init() | 4371 | case e1000_82543: |
6015 | * Call e1000_cleanup led() to stop blinking | 4372 | case e1000_82544: |
6016 | * | 4373 | /* No setup necessary */ |
6017 | * hw - Struct containing variables accessed by shared code | 4374 | break; |
6018 | *****************************************************************************/ | 4375 | case e1000_82541: |
6019 | s32 e1000_blink_led_start(struct e1000_hw *hw) | 4376 | case e1000_82547: |
6020 | { | 4377 | case e1000_82541_rev_2: |
6021 | s16 i; | 4378 | case e1000_82547_rev_2: |
6022 | u32 ledctl_blink = 0; | 4379 | /* Turn off PHY Smart Power Down (if enabled) */ |
6023 | 4380 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, | |
6024 | DEBUGFUNC("e1000_id_led_blink_on"); | 4381 | &hw->phy_spd_default); |
6025 | 4382 | if (ret_val) | |
6026 | if (hw->mac_type < e1000_82571) { | 4383 | return ret_val; |
6027 | /* Nothing to do */ | 4384 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
6028 | return E1000_SUCCESS; | 4385 | (u16) (hw->phy_spd_default & |
6029 | } | 4386 | ~IGP01E1000_GMII_SPD)); |
6030 | if (hw->media_type == e1000_media_type_fiber) { | 4387 | if (ret_val) |
6031 | /* always blink LED0 for PCI-E fiber */ | 4388 | return ret_val; |
6032 | ledctl_blink = E1000_LEDCTL_LED0_BLINK | | 4389 | /* Fall Through */ |
6033 | (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); | 4390 | default: |
6034 | } else { | 4391 | if (hw->media_type == e1000_media_type_fiber) { |
6035 | /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */ | 4392 | ledctl = er32(LEDCTL); |
6036 | ledctl_blink = hw->ledctl_mode2; | 4393 | /* Save current LEDCTL settings */ |
6037 | for (i=0; i < 4; i++) | 4394 | hw->ledctl_default = ledctl; |
6038 | if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) == | 4395 | /* Turn off LED0 */ |
6039 | E1000_LEDCTL_MODE_LED_ON) | 4396 | ledctl &= ~(E1000_LEDCTL_LED0_IVRT | |
6040 | ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8)); | 4397 | E1000_LEDCTL_LED0_BLINK | |
6041 | } | 4398 | E1000_LEDCTL_LED0_MODE_MASK); |
6042 | 4399 | ledctl |= (E1000_LEDCTL_MODE_LED_OFF << | |
6043 | ew32(LEDCTL, ledctl_blink); | 4400 | E1000_LEDCTL_LED0_MODE_SHIFT); |
6044 | 4401 | ew32(LEDCTL, ledctl); | |
6045 | return E1000_SUCCESS; | 4402 | } else if (hw->media_type == e1000_media_type_copper) |
4403 | ew32(LEDCTL, hw->ledctl_mode1); | ||
4404 | break; | ||
4405 | } | ||
4406 | |||
4407 | return E1000_SUCCESS; | ||
6046 | } | 4408 | } |
6047 | 4409 | ||
6048 | /****************************************************************************** | 4410 | /** |
6049 | * Restores the saved state of the SW controlable LED. | 4411 | * e1000_cleanup_led - Restores the saved state of the SW controlable LED. |
6050 | * | 4412 | * @hw: Struct containing variables accessed by shared code |
6051 | * hw - Struct containing variables accessed by shared code | 4413 | */ |
6052 | *****************************************************************************/ | ||
6053 | s32 e1000_cleanup_led(struct e1000_hw *hw) | 4414 | s32 e1000_cleanup_led(struct e1000_hw *hw) |
6054 | { | 4415 | { |
6055 | s32 ret_val = E1000_SUCCESS; | 4416 | s32 ret_val = E1000_SUCCESS; |
6056 | 4417 | ||
6057 | DEBUGFUNC("e1000_cleanup_led"); | 4418 | DEBUGFUNC("e1000_cleanup_led"); |
6058 | 4419 | ||
6059 | switch (hw->mac_type) { | 4420 | switch (hw->mac_type) { |
6060 | case e1000_82542_rev2_0: | 4421 | case e1000_82542_rev2_0: |
6061 | case e1000_82542_rev2_1: | 4422 | case e1000_82542_rev2_1: |
6062 | case e1000_82543: | 4423 | case e1000_82543: |
6063 | case e1000_82544: | 4424 | case e1000_82544: |
6064 | /* No cleanup necessary */ | 4425 | /* No cleanup necessary */ |
6065 | break; | 4426 | break; |
6066 | case e1000_82541: | 4427 | case e1000_82541: |
6067 | case e1000_82547: | 4428 | case e1000_82547: |
6068 | case e1000_82541_rev_2: | 4429 | case e1000_82541_rev_2: |
6069 | case e1000_82547_rev_2: | 4430 | case e1000_82547_rev_2: |
6070 | /* Turn on PHY Smart Power Down (if previously enabled) */ | 4431 | /* Turn on PHY Smart Power Down (if previously enabled) */ |
6071 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, | 4432 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
6072 | hw->phy_spd_default); | 4433 | hw->phy_spd_default); |
6073 | if (ret_val) | 4434 | if (ret_val) |
6074 | return ret_val; | 4435 | return ret_val; |
6075 | /* Fall Through */ | 4436 | /* Fall Through */ |
6076 | default: | 4437 | default: |
6077 | if (hw->phy_type == e1000_phy_ife) { | 4438 | /* Restore LEDCTL settings */ |
6078 | e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); | 4439 | ew32(LEDCTL, hw->ledctl_default); |
6079 | break; | 4440 | break; |
6080 | } | 4441 | } |
6081 | /* Restore LEDCTL settings */ | 4442 | |
6082 | ew32(LEDCTL, hw->ledctl_default); | 4443 | return E1000_SUCCESS; |
6083 | break; | ||
6084 | } | ||
6085 | |||
6086 | return E1000_SUCCESS; | ||
6087 | } | 4444 | } |
6088 | 4445 | ||
6089 | /****************************************************************************** | 4446 | /** |
6090 | * Turns on the software controllable LED | 4447 | * e1000_led_on - Turns on the software controllable LED |
6091 | * | 4448 | * @hw: Struct containing variables accessed by shared code |
6092 | * hw - Struct containing variables accessed by shared code | 4449 | */ |
6093 | *****************************************************************************/ | ||
6094 | s32 e1000_led_on(struct e1000_hw *hw) | 4450 | s32 e1000_led_on(struct e1000_hw *hw) |
6095 | { | 4451 | { |
6096 | u32 ctrl = er32(CTRL); | 4452 | u32 ctrl = er32(CTRL); |
6097 | 4453 | ||
6098 | DEBUGFUNC("e1000_led_on"); | 4454 | DEBUGFUNC("e1000_led_on"); |
6099 | 4455 | ||
6100 | switch (hw->mac_type) { | 4456 | switch (hw->mac_type) { |
6101 | case e1000_82542_rev2_0: | 4457 | case e1000_82542_rev2_0: |
6102 | case e1000_82542_rev2_1: | 4458 | case e1000_82542_rev2_1: |
6103 | case e1000_82543: | 4459 | case e1000_82543: |
6104 | /* Set SW Defineable Pin 0 to turn on the LED */ | 4460 | /* Set SW Defineable Pin 0 to turn on the LED */ |
6105 | ctrl |= E1000_CTRL_SWDPIN0; | 4461 | ctrl |= E1000_CTRL_SWDPIN0; |
6106 | ctrl |= E1000_CTRL_SWDPIO0; | 4462 | ctrl |= E1000_CTRL_SWDPIO0; |
6107 | break; | 4463 | break; |
6108 | case e1000_82544: | 4464 | case e1000_82544: |
6109 | if (hw->media_type == e1000_media_type_fiber) { | 4465 | if (hw->media_type == e1000_media_type_fiber) { |
6110 | /* Set SW Defineable Pin 0 to turn on the LED */ | 4466 | /* Set SW Defineable Pin 0 to turn on the LED */ |
6111 | ctrl |= E1000_CTRL_SWDPIN0; | 4467 | ctrl |= E1000_CTRL_SWDPIN0; |
6112 | ctrl |= E1000_CTRL_SWDPIO0; | 4468 | ctrl |= E1000_CTRL_SWDPIO0; |
6113 | } else { | 4469 | } else { |
6114 | /* Clear SW Defineable Pin 0 to turn on the LED */ | 4470 | /* Clear SW Defineable Pin 0 to turn on the LED */ |
6115 | ctrl &= ~E1000_CTRL_SWDPIN0; | 4471 | ctrl &= ~E1000_CTRL_SWDPIN0; |
6116 | ctrl |= E1000_CTRL_SWDPIO0; | 4472 | ctrl |= E1000_CTRL_SWDPIO0; |
6117 | } | 4473 | } |
6118 | break; | 4474 | break; |
6119 | default: | 4475 | default: |
6120 | if (hw->media_type == e1000_media_type_fiber) { | 4476 | if (hw->media_type == e1000_media_type_fiber) { |
6121 | /* Clear SW Defineable Pin 0 to turn on the LED */ | 4477 | /* Clear SW Defineable Pin 0 to turn on the LED */ |
6122 | ctrl &= ~E1000_CTRL_SWDPIN0; | 4478 | ctrl &= ~E1000_CTRL_SWDPIN0; |
6123 | ctrl |= E1000_CTRL_SWDPIO0; | 4479 | ctrl |= E1000_CTRL_SWDPIO0; |
6124 | } else if (hw->phy_type == e1000_phy_ife) { | 4480 | } else if (hw->media_type == e1000_media_type_copper) { |
6125 | e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, | 4481 | ew32(LEDCTL, hw->ledctl_mode2); |
6126 | (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); | 4482 | return E1000_SUCCESS; |
6127 | } else if (hw->media_type == e1000_media_type_copper) { | 4483 | } |
6128 | ew32(LEDCTL, hw->ledctl_mode2); | 4484 | break; |
6129 | return E1000_SUCCESS; | 4485 | } |
6130 | } | 4486 | |
6131 | break; | 4487 | ew32(CTRL, ctrl); |
6132 | } | 4488 | |
6133 | 4489 | return E1000_SUCCESS; | |
6134 | ew32(CTRL, ctrl); | ||
6135 | |||
6136 | return E1000_SUCCESS; | ||
6137 | } | 4490 | } |
6138 | 4491 | ||
6139 | /****************************************************************************** | 4492 | /** |
6140 | * Turns off the software controllable LED | 4493 | * e1000_led_off - Turns off the software controllable LED |
6141 | * | 4494 | * @hw: Struct containing variables accessed by shared code |
6142 | * hw - Struct containing variables accessed by shared code | 4495 | */ |
6143 | *****************************************************************************/ | ||
6144 | s32 e1000_led_off(struct e1000_hw *hw) | 4496 | s32 e1000_led_off(struct e1000_hw *hw) |
6145 | { | 4497 | { |
6146 | u32 ctrl = er32(CTRL); | 4498 | u32 ctrl = er32(CTRL); |
6147 | 4499 | ||
6148 | DEBUGFUNC("e1000_led_off"); | 4500 | DEBUGFUNC("e1000_led_off"); |
6149 | 4501 | ||
6150 | switch (hw->mac_type) { | 4502 | switch (hw->mac_type) { |
6151 | case e1000_82542_rev2_0: | 4503 | case e1000_82542_rev2_0: |
6152 | case e1000_82542_rev2_1: | 4504 | case e1000_82542_rev2_1: |
6153 | case e1000_82543: | 4505 | case e1000_82543: |
6154 | /* Clear SW Defineable Pin 0 to turn off the LED */ | 4506 | /* Clear SW Defineable Pin 0 to turn off the LED */ |
6155 | ctrl &= ~E1000_CTRL_SWDPIN0; | 4507 | ctrl &= ~E1000_CTRL_SWDPIN0; |
6156 | ctrl |= E1000_CTRL_SWDPIO0; | 4508 | ctrl |= E1000_CTRL_SWDPIO0; |
6157 | break; | 4509 | break; |
6158 | case e1000_82544: | 4510 | case e1000_82544: |
6159 | if (hw->media_type == e1000_media_type_fiber) { | 4511 | if (hw->media_type == e1000_media_type_fiber) { |
6160 | /* Clear SW Defineable Pin 0 to turn off the LED */ | 4512 | /* Clear SW Defineable Pin 0 to turn off the LED */ |
6161 | ctrl &= ~E1000_CTRL_SWDPIN0; | 4513 | ctrl &= ~E1000_CTRL_SWDPIN0; |
6162 | ctrl |= E1000_CTRL_SWDPIO0; | 4514 | ctrl |= E1000_CTRL_SWDPIO0; |
6163 | } else { | 4515 | } else { |
6164 | /* Set SW Defineable Pin 0 to turn off the LED */ | 4516 | /* Set SW Defineable Pin 0 to turn off the LED */ |
6165 | ctrl |= E1000_CTRL_SWDPIN0; | 4517 | ctrl |= E1000_CTRL_SWDPIN0; |
6166 | ctrl |= E1000_CTRL_SWDPIO0; | 4518 | ctrl |= E1000_CTRL_SWDPIO0; |
6167 | } | 4519 | } |
6168 | break; | 4520 | break; |
6169 | default: | 4521 | default: |
6170 | if (hw->media_type == e1000_media_type_fiber) { | 4522 | if (hw->media_type == e1000_media_type_fiber) { |
6171 | /* Set SW Defineable Pin 0 to turn off the LED */ | 4523 | /* Set SW Defineable Pin 0 to turn off the LED */ |
6172 | ctrl |= E1000_CTRL_SWDPIN0; | 4524 | ctrl |= E1000_CTRL_SWDPIN0; |
6173 | ctrl |= E1000_CTRL_SWDPIO0; | 4525 | ctrl |= E1000_CTRL_SWDPIO0; |
6174 | } else if (hw->phy_type == e1000_phy_ife) { | 4526 | } else if (hw->media_type == e1000_media_type_copper) { |
6175 | e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, | 4527 | ew32(LEDCTL, hw->ledctl_mode1); |
6176 | (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); | 4528 | return E1000_SUCCESS; |
6177 | } else if (hw->media_type == e1000_media_type_copper) { | 4529 | } |
6178 | ew32(LEDCTL, hw->ledctl_mode1); | 4530 | break; |
6179 | return E1000_SUCCESS; | 4531 | } |
6180 | } | 4532 | |
6181 | break; | 4533 | ew32(CTRL, ctrl); |
6182 | } | 4534 | |
6183 | 4535 | return E1000_SUCCESS; | |
6184 | ew32(CTRL, ctrl); | ||
6185 | |||
6186 | return E1000_SUCCESS; | ||
6187 | } | 4536 | } |
6188 | 4537 | ||
6189 | /****************************************************************************** | 4538 | /** |
6190 | * Clears all hardware statistics counters. | 4539 | * e1000_clear_hw_cntrs - Clears all hardware statistics counters. |
6191 | * | 4540 | * @hw: Struct containing variables accessed by shared code |
6192 | * hw - Struct containing variables accessed by shared code | 4541 | */ |
6193 | *****************************************************************************/ | ||
6194 | static void e1000_clear_hw_cntrs(struct e1000_hw *hw) | 4542 | static void e1000_clear_hw_cntrs(struct e1000_hw *hw) |
6195 | { | 4543 | { |
6196 | volatile u32 temp; | 4544 | volatile u32 temp; |
6197 | 4545 | ||
6198 | temp = er32(CRCERRS); | 4546 | temp = er32(CRCERRS); |
6199 | temp = er32(SYMERRS); | 4547 | temp = er32(SYMERRS); |
6200 | temp = er32(MPC); | 4548 | temp = er32(MPC); |
6201 | temp = er32(SCC); | 4549 | temp = er32(SCC); |
6202 | temp = er32(ECOL); | 4550 | temp = er32(ECOL); |
6203 | temp = er32(MCC); | 4551 | temp = er32(MCC); |
6204 | temp = er32(LATECOL); | 4552 | temp = er32(LATECOL); |
6205 | temp = er32(COLC); | 4553 | temp = er32(COLC); |
6206 | temp = er32(DC); | 4554 | temp = er32(DC); |
6207 | temp = er32(SEC); | 4555 | temp = er32(SEC); |
6208 | temp = er32(RLEC); | 4556 | temp = er32(RLEC); |
6209 | temp = er32(XONRXC); | 4557 | temp = er32(XONRXC); |
6210 | temp = er32(XONTXC); | 4558 | temp = er32(XONTXC); |
6211 | temp = er32(XOFFRXC); | 4559 | temp = er32(XOFFRXC); |
6212 | temp = er32(XOFFTXC); | 4560 | temp = er32(XOFFTXC); |
6213 | temp = er32(FCRUC); | 4561 | temp = er32(FCRUC); |
6214 | 4562 | ||
6215 | if (hw->mac_type != e1000_ich8lan) { | 4563 | temp = er32(PRC64); |
6216 | temp = er32(PRC64); | 4564 | temp = er32(PRC127); |
6217 | temp = er32(PRC127); | 4565 | temp = er32(PRC255); |
6218 | temp = er32(PRC255); | 4566 | temp = er32(PRC511); |
6219 | temp = er32(PRC511); | 4567 | temp = er32(PRC1023); |
6220 | temp = er32(PRC1023); | 4568 | temp = er32(PRC1522); |
6221 | temp = er32(PRC1522); | 4569 | |
6222 | } | 4570 | temp = er32(GPRC); |
6223 | 4571 | temp = er32(BPRC); | |
6224 | temp = er32(GPRC); | 4572 | temp = er32(MPRC); |
6225 | temp = er32(BPRC); | 4573 | temp = er32(GPTC); |
6226 | temp = er32(MPRC); | 4574 | temp = er32(GORCL); |
6227 | temp = er32(GPTC); | 4575 | temp = er32(GORCH); |
6228 | temp = er32(GORCL); | 4576 | temp = er32(GOTCL); |
6229 | temp = er32(GORCH); | 4577 | temp = er32(GOTCH); |
6230 | temp = er32(GOTCL); | 4578 | temp = er32(RNBC); |
6231 | temp = er32(GOTCH); | 4579 | temp = er32(RUC); |
6232 | temp = er32(RNBC); | 4580 | temp = er32(RFC); |
6233 | temp = er32(RUC); | 4581 | temp = er32(ROC); |
6234 | temp = er32(RFC); | 4582 | temp = er32(RJC); |
6235 | temp = er32(ROC); | 4583 | temp = er32(TORL); |
6236 | temp = er32(RJC); | 4584 | temp = er32(TORH); |
6237 | temp = er32(TORL); | 4585 | temp = er32(TOTL); |
6238 | temp = er32(TORH); | 4586 | temp = er32(TOTH); |
6239 | temp = er32(TOTL); | 4587 | temp = er32(TPR); |
6240 | temp = er32(TOTH); | 4588 | temp = er32(TPT); |
6241 | temp = er32(TPR); | 4589 | |
6242 | temp = er32(TPT); | 4590 | temp = er32(PTC64); |
6243 | 4591 | temp = er32(PTC127); | |
6244 | if (hw->mac_type != e1000_ich8lan) { | 4592 | temp = er32(PTC255); |
6245 | temp = er32(PTC64); | 4593 | temp = er32(PTC511); |
6246 | temp = er32(PTC127); | 4594 | temp = er32(PTC1023); |
6247 | temp = er32(PTC255); | 4595 | temp = er32(PTC1522); |
6248 | temp = er32(PTC511); | 4596 | |
6249 | temp = er32(PTC1023); | 4597 | temp = er32(MPTC); |
6250 | temp = er32(PTC1522); | 4598 | temp = er32(BPTC); |
6251 | } | 4599 | |
6252 | 4600 | if (hw->mac_type < e1000_82543) | |
6253 | temp = er32(MPTC); | 4601 | return; |
6254 | temp = er32(BPTC); | 4602 | |
6255 | 4603 | temp = er32(ALGNERRC); | |
6256 | if (hw->mac_type < e1000_82543) return; | 4604 | temp = er32(RXERRC); |
6257 | 4605 | temp = er32(TNCRS); | |
6258 | temp = er32(ALGNERRC); | 4606 | temp = er32(CEXTERR); |
6259 | temp = er32(RXERRC); | 4607 | temp = er32(TSCTC); |
6260 | temp = er32(TNCRS); | 4608 | temp = er32(TSCTFC); |
6261 | temp = er32(CEXTERR); | 4609 | |
6262 | temp = er32(TSCTC); | 4610 | if (hw->mac_type <= e1000_82544) |
6263 | temp = er32(TSCTFC); | 4611 | return; |
6264 | 4612 | ||
6265 | if (hw->mac_type <= e1000_82544) return; | 4613 | temp = er32(MGTPRC); |
6266 | 4614 | temp = er32(MGTPDC); | |
6267 | temp = er32(MGTPRC); | 4615 | temp = er32(MGTPTC); |
6268 | temp = er32(MGTPDC); | 4616 | } |
6269 | temp = er32(MGTPTC); | 4617 | |
6270 | 4618 | /** | |
6271 | if (hw->mac_type <= e1000_82547_rev_2) return; | 4619 | * e1000_reset_adaptive - Resets Adaptive IFS to its default state. |
6272 | 4620 | * @hw: Struct containing variables accessed by shared code | |
6273 | temp = er32(IAC); | ||
6274 | temp = er32(ICRXOC); | ||
6275 | |||
6276 | if (hw->mac_type == e1000_ich8lan) return; | ||
6277 | |||
6278 | temp = er32(ICRXPTC); | ||
6279 | temp = er32(ICRXATC); | ||
6280 | temp = er32(ICTXPTC); | ||
6281 | temp = er32(ICTXATC); | ||
6282 | temp = er32(ICTXQEC); | ||
6283 | temp = er32(ICTXQMTC); | ||
6284 | temp = er32(ICRXDMTC); | ||
6285 | } | ||
6286 | |||
6287 | /****************************************************************************** | ||
6288 | * Resets Adaptive IFS to its default state. | ||
6289 | * | ||
6290 | * hw - Struct containing variables accessed by shared code | ||
6291 | * | 4621 | * |
6292 | * Call this after e1000_init_hw. You may override the IFS defaults by setting | 4622 | * Call this after e1000_init_hw. You may override the IFS defaults by setting |
6293 | * hw->ifs_params_forced to true. However, you must initialize hw-> | 4623 | * hw->ifs_params_forced to true. However, you must initialize hw-> |
6294 | * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio | 4624 | * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio |
6295 | * before calling this function. | 4625 | * before calling this function. |
6296 | *****************************************************************************/ | 4626 | */ |
6297 | void e1000_reset_adaptive(struct e1000_hw *hw) | 4627 | void e1000_reset_adaptive(struct e1000_hw *hw) |
6298 | { | 4628 | { |
6299 | DEBUGFUNC("e1000_reset_adaptive"); | 4629 | DEBUGFUNC("e1000_reset_adaptive"); |
6300 | 4630 | ||
6301 | if (hw->adaptive_ifs) { | 4631 | if (hw->adaptive_ifs) { |
6302 | if (!hw->ifs_params_forced) { | 4632 | if (!hw->ifs_params_forced) { |
6303 | hw->current_ifs_val = 0; | 4633 | hw->current_ifs_val = 0; |
6304 | hw->ifs_min_val = IFS_MIN; | 4634 | hw->ifs_min_val = IFS_MIN; |
6305 | hw->ifs_max_val = IFS_MAX; | 4635 | hw->ifs_max_val = IFS_MAX; |
6306 | hw->ifs_step_size = IFS_STEP; | 4636 | hw->ifs_step_size = IFS_STEP; |
6307 | hw->ifs_ratio = IFS_RATIO; | 4637 | hw->ifs_ratio = IFS_RATIO; |
6308 | } | 4638 | } |
6309 | hw->in_ifs_mode = false; | 4639 | hw->in_ifs_mode = false; |
6310 | ew32(AIT, 0); | 4640 | ew32(AIT, 0); |
6311 | } else { | 4641 | } else { |
6312 | DEBUGOUT("Not in Adaptive IFS mode!\n"); | 4642 | DEBUGOUT("Not in Adaptive IFS mode!\n"); |
6313 | } | 4643 | } |
6314 | } | 4644 | } |
6315 | 4645 | ||
6316 | /****************************************************************************** | 4646 | /** |
4647 | * e1000_update_adaptive - update adaptive IFS | ||
4648 | * @hw: Struct containing variables accessed by shared code | ||
4649 | * @tx_packets: Number of transmits since last callback | ||
4650 | * @total_collisions: Number of collisions since last callback | ||
4651 | * | ||
6317 | * Called during the callback/watchdog routine to update IFS value based on | 4652 | * Called during the callback/watchdog routine to update IFS value based on |
6318 | * the ratio of transmits to collisions. | 4653 | * the ratio of transmits to collisions. |
6319 | * | 4654 | */ |
6320 | * hw - Struct containing variables accessed by shared code | ||
6321 | * tx_packets - Number of transmits since last callback | ||
6322 | * total_collisions - Number of collisions since last callback | ||
6323 | *****************************************************************************/ | ||
6324 | void e1000_update_adaptive(struct e1000_hw *hw) | 4655 | void e1000_update_adaptive(struct e1000_hw *hw) |
6325 | { | 4656 | { |
6326 | DEBUGFUNC("e1000_update_adaptive"); | 4657 | DEBUGFUNC("e1000_update_adaptive"); |
6327 | 4658 | ||
6328 | if (hw->adaptive_ifs) { | 4659 | if (hw->adaptive_ifs) { |
6329 | if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { | 4660 | if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) { |
6330 | if (hw->tx_packet_delta > MIN_NUM_XMITS) { | 4661 | if (hw->tx_packet_delta > MIN_NUM_XMITS) { |
6331 | hw->in_ifs_mode = true; | 4662 | hw->in_ifs_mode = true; |
6332 | if (hw->current_ifs_val < hw->ifs_max_val) { | 4663 | if (hw->current_ifs_val < hw->ifs_max_val) { |
6333 | if (hw->current_ifs_val == 0) | 4664 | if (hw->current_ifs_val == 0) |
6334 | hw->current_ifs_val = hw->ifs_min_val; | 4665 | hw->current_ifs_val = |
6335 | else | 4666 | hw->ifs_min_val; |
6336 | hw->current_ifs_val += hw->ifs_step_size; | 4667 | else |
6337 | ew32(AIT, hw->current_ifs_val); | 4668 | hw->current_ifs_val += |
6338 | } | 4669 | hw->ifs_step_size; |
6339 | } | 4670 | ew32(AIT, hw->current_ifs_val); |
6340 | } else { | 4671 | } |
6341 | if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { | 4672 | } |
6342 | hw->current_ifs_val = 0; | 4673 | } else { |
6343 | hw->in_ifs_mode = false; | 4674 | if (hw->in_ifs_mode |
6344 | ew32(AIT, 0); | 4675 | && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { |
6345 | } | 4676 | hw->current_ifs_val = 0; |
6346 | } | 4677 | hw->in_ifs_mode = false; |
6347 | } else { | 4678 | ew32(AIT, 0); |
6348 | DEBUGOUT("Not in Adaptive IFS mode!\n"); | 4679 | } |
6349 | } | 4680 | } |
4681 | } else { | ||
4682 | DEBUGOUT("Not in Adaptive IFS mode!\n"); | ||
4683 | } | ||
6350 | } | 4684 | } |
6351 | 4685 | ||
6352 | /****************************************************************************** | 4686 | /** |
6353 | * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT | 4687 | * e1000_tbi_adjust_stats |
4688 | * @hw: Struct containing variables accessed by shared code | ||
4689 | * @frame_len: The length of the frame in question | ||
4690 | * @mac_addr: The Ethernet destination address of the frame in question | ||
6354 | * | 4691 | * |
6355 | * hw - Struct containing variables accessed by shared code | 4692 | * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT |
6356 | * frame_len - The length of the frame in question | 4693 | */ |
6357 | * mac_addr - The Ethernet destination address of the frame in question | ||
6358 | *****************************************************************************/ | ||
6359 | void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, | 4694 | void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, |
6360 | u32 frame_len, u8 *mac_addr) | 4695 | u32 frame_len, u8 *mac_addr) |
6361 | { | 4696 | { |
6362 | u64 carry_bit; | 4697 | u64 carry_bit; |
6363 | 4698 | ||
6364 | /* First adjust the frame length. */ | 4699 | /* First adjust the frame length. */ |
6365 | frame_len--; | 4700 | frame_len--; |
6366 | /* We need to adjust the statistics counters, since the hardware | 4701 | /* We need to adjust the statistics counters, since the hardware |
6367 | * counters overcount this packet as a CRC error and undercount | 4702 | * counters overcount this packet as a CRC error and undercount |
6368 | * the packet as a good packet | 4703 | * the packet as a good packet |
6369 | */ | 4704 | */ |
6370 | /* This packet should not be counted as a CRC error. */ | 4705 | /* This packet should not be counted as a CRC error. */ |
6371 | stats->crcerrs--; | 4706 | stats->crcerrs--; |
6372 | /* This packet does count as a Good Packet Received. */ | 4707 | /* This packet does count as a Good Packet Received. */ |
6373 | stats->gprc++; | 4708 | stats->gprc++; |
6374 | 4709 | ||
6375 | /* Adjust the Good Octets received counters */ | 4710 | /* Adjust the Good Octets received counters */ |
6376 | carry_bit = 0x80000000 & stats->gorcl; | 4711 | carry_bit = 0x80000000 & stats->gorcl; |
6377 | stats->gorcl += frame_len; | 4712 | stats->gorcl += frame_len; |
6378 | /* If the high bit of Gorcl (the low 32 bits of the Good Octets | 4713 | /* If the high bit of Gorcl (the low 32 bits of the Good Octets |
6379 | * Received Count) was one before the addition, | 4714 | * Received Count) was one before the addition, |
6380 | * AND it is zero after, then we lost the carry out, | 4715 | * AND it is zero after, then we lost the carry out, |
6381 | * need to add one to Gorch (Good Octets Received Count High). | 4716 | * need to add one to Gorch (Good Octets Received Count High). |
6382 | * This could be simplified if all environments supported | 4717 | * This could be simplified if all environments supported |
6383 | * 64-bit integers. | 4718 | * 64-bit integers. |
6384 | */ | 4719 | */ |
6385 | if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) | 4720 | if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) |
6386 | stats->gorch++; | 4721 | stats->gorch++; |
6387 | /* Is this a broadcast or multicast? Check broadcast first, | 4722 | /* Is this a broadcast or multicast? Check broadcast first, |
6388 | * since the test for a multicast frame will test positive on | 4723 | * since the test for a multicast frame will test positive on |
6389 | * a broadcast frame. | 4724 | * a broadcast frame. |
6390 | */ | 4725 | */ |
6391 | if ((mac_addr[0] == (u8)0xff) && (mac_addr[1] == (u8)0xff)) | 4726 | if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff)) |
6392 | /* Broadcast packet */ | 4727 | /* Broadcast packet */ |
6393 | stats->bprc++; | 4728 | stats->bprc++; |
6394 | else if (*mac_addr & 0x01) | 4729 | else if (*mac_addr & 0x01) |
6395 | /* Multicast packet */ | 4730 | /* Multicast packet */ |
6396 | stats->mprc++; | 4731 | stats->mprc++; |
6397 | 4732 | ||
6398 | if (frame_len == hw->max_frame_size) { | 4733 | if (frame_len == hw->max_frame_size) { |
6399 | /* In this case, the hardware has overcounted the number of | 4734 | /* In this case, the hardware has overcounted the number of |
6400 | * oversize frames. | 4735 | * oversize frames. |
6401 | */ | 4736 | */ |
6402 | if (stats->roc > 0) | 4737 | if (stats->roc > 0) |
6403 | stats->roc--; | 4738 | stats->roc--; |
6404 | } | 4739 | } |
6405 | 4740 | ||
6406 | /* Adjust the bin counters when the extra byte put the frame in the | 4741 | /* Adjust the bin counters when the extra byte put the frame in the |
6407 | * wrong bin. Remember that the frame_len was adjusted above. | 4742 | * wrong bin. Remember that the frame_len was adjusted above. |
6408 | */ | 4743 | */ |
6409 | if (frame_len == 64) { | 4744 | if (frame_len == 64) { |
6410 | stats->prc64++; | 4745 | stats->prc64++; |
6411 | stats->prc127--; | 4746 | stats->prc127--; |
6412 | } else if (frame_len == 127) { | 4747 | } else if (frame_len == 127) { |
6413 | stats->prc127++; | 4748 | stats->prc127++; |
6414 | stats->prc255--; | 4749 | stats->prc255--; |
6415 | } else if (frame_len == 255) { | 4750 | } else if (frame_len == 255) { |
6416 | stats->prc255++; | 4751 | stats->prc255++; |
6417 | stats->prc511--; | 4752 | stats->prc511--; |
6418 | } else if (frame_len == 511) { | 4753 | } else if (frame_len == 511) { |
6419 | stats->prc511++; | 4754 | stats->prc511++; |
6420 | stats->prc1023--; | 4755 | stats->prc1023--; |
6421 | } else if (frame_len == 1023) { | 4756 | } else if (frame_len == 1023) { |
6422 | stats->prc1023++; | 4757 | stats->prc1023++; |
6423 | stats->prc1522--; | 4758 | stats->prc1522--; |
6424 | } else if (frame_len == 1522) { | 4759 | } else if (frame_len == 1522) { |
6425 | stats->prc1522++; | 4760 | stats->prc1522++; |
6426 | } | 4761 | } |
6427 | } | 4762 | } |
6428 | 4763 | ||
6429 | /****************************************************************************** | 4764 | /** |
6430 | * Gets the current PCI bus type, speed, and width of the hardware | 4765 | * e1000_get_bus_info |
4766 | * @hw: Struct containing variables accessed by shared code | ||
6431 | * | 4767 | * |
6432 | * hw - Struct containing variables accessed by shared code | 4768 | * Gets the current PCI bus type, speed, and width of the hardware |
6433 | *****************************************************************************/ | 4769 | */ |
6434 | void e1000_get_bus_info(struct e1000_hw *hw) | 4770 | void e1000_get_bus_info(struct e1000_hw *hw) |
6435 | { | 4771 | { |
6436 | s32 ret_val; | 4772 | u32 status; |
6437 | u16 pci_ex_link_status; | 4773 | |
6438 | u32 status; | 4774 | switch (hw->mac_type) { |
6439 | 4775 | case e1000_82542_rev2_0: | |
6440 | switch (hw->mac_type) { | 4776 | case e1000_82542_rev2_1: |
6441 | case e1000_82542_rev2_0: | 4777 | hw->bus_type = e1000_bus_type_pci; |
6442 | case e1000_82542_rev2_1: | 4778 | hw->bus_speed = e1000_bus_speed_unknown; |
6443 | hw->bus_type = e1000_bus_type_pci; | 4779 | hw->bus_width = e1000_bus_width_unknown; |
6444 | hw->bus_speed = e1000_bus_speed_unknown; | 4780 | break; |
6445 | hw->bus_width = e1000_bus_width_unknown; | 4781 | default: |
6446 | break; | 4782 | status = er32(STATUS); |
6447 | case e1000_82571: | 4783 | hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? |
6448 | case e1000_82572: | 4784 | e1000_bus_type_pcix : e1000_bus_type_pci; |
6449 | case e1000_82573: | 4785 | |
6450 | case e1000_80003es2lan: | 4786 | if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { |
6451 | hw->bus_type = e1000_bus_type_pci_express; | 4787 | hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? |
6452 | hw->bus_speed = e1000_bus_speed_2500; | 4788 | e1000_bus_speed_66 : e1000_bus_speed_120; |
6453 | ret_val = e1000_read_pcie_cap_reg(hw, | 4789 | } else if (hw->bus_type == e1000_bus_type_pci) { |
6454 | PCI_EX_LINK_STATUS, | 4790 | hw->bus_speed = (status & E1000_STATUS_PCI66) ? |
6455 | &pci_ex_link_status); | 4791 | e1000_bus_speed_66 : e1000_bus_speed_33; |
6456 | if (ret_val) | 4792 | } else { |
6457 | hw->bus_width = e1000_bus_width_unknown; | 4793 | switch (status & E1000_STATUS_PCIX_SPEED) { |
6458 | else | 4794 | case E1000_STATUS_PCIX_SPEED_66: |
6459 | hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >> | 4795 | hw->bus_speed = e1000_bus_speed_66; |
6460 | PCI_EX_LINK_WIDTH_SHIFT; | 4796 | break; |
6461 | break; | 4797 | case E1000_STATUS_PCIX_SPEED_100: |
6462 | case e1000_ich8lan: | 4798 | hw->bus_speed = e1000_bus_speed_100; |
6463 | hw->bus_type = e1000_bus_type_pci_express; | 4799 | break; |
6464 | hw->bus_speed = e1000_bus_speed_2500; | 4800 | case E1000_STATUS_PCIX_SPEED_133: |
6465 | hw->bus_width = e1000_bus_width_pciex_1; | 4801 | hw->bus_speed = e1000_bus_speed_133; |
6466 | break; | 4802 | break; |
6467 | default: | 4803 | default: |
6468 | status = er32(STATUS); | 4804 | hw->bus_speed = e1000_bus_speed_reserved; |
6469 | hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? | 4805 | break; |
6470 | e1000_bus_type_pcix : e1000_bus_type_pci; | 4806 | } |
6471 | 4807 | } | |
6472 | if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { | 4808 | hw->bus_width = (status & E1000_STATUS_BUS64) ? |
6473 | hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? | 4809 | e1000_bus_width_64 : e1000_bus_width_32; |
6474 | e1000_bus_speed_66 : e1000_bus_speed_120; | 4810 | break; |
6475 | } else if (hw->bus_type == e1000_bus_type_pci) { | 4811 | } |
6476 | hw->bus_speed = (status & E1000_STATUS_PCI66) ? | ||
6477 | e1000_bus_speed_66 : e1000_bus_speed_33; | ||
6478 | } else { | ||
6479 | switch (status & E1000_STATUS_PCIX_SPEED) { | ||
6480 | case E1000_STATUS_PCIX_SPEED_66: | ||
6481 | hw->bus_speed = e1000_bus_speed_66; | ||
6482 | break; | ||
6483 | case E1000_STATUS_PCIX_SPEED_100: | ||
6484 | hw->bus_speed = e1000_bus_speed_100; | ||
6485 | break; | ||
6486 | case E1000_STATUS_PCIX_SPEED_133: | ||
6487 | hw->bus_speed = e1000_bus_speed_133; | ||
6488 | break; | ||
6489 | default: | ||
6490 | hw->bus_speed = e1000_bus_speed_reserved; | ||
6491 | break; | ||
6492 | } | ||
6493 | } | ||
6494 | hw->bus_width = (status & E1000_STATUS_BUS64) ? | ||
6495 | e1000_bus_width_64 : e1000_bus_width_32; | ||
6496 | break; | ||
6497 | } | ||
6498 | } | 4812 | } |
6499 | 4813 | ||
6500 | /****************************************************************************** | 4814 | /** |
4815 | * e1000_write_reg_io | ||
4816 | * @hw: Struct containing variables accessed by shared code | ||
4817 | * @offset: offset to write to | ||
4818 | * @value: value to write | ||
4819 | * | ||
6501 | * Writes a value to one of the devices registers using port I/O (as opposed to | 4820 | * Writes a value to one of the devices registers using port I/O (as opposed to |
6502 | * memory mapped I/O). Only 82544 and newer devices support port I/O. | 4821 | * memory mapped I/O). Only 82544 and newer devices support port I/O. |
6503 | * | 4822 | */ |
6504 | * hw - Struct containing variables accessed by shared code | ||
6505 | * offset - offset to write to | ||
6506 | * value - value to write | ||
6507 | *****************************************************************************/ | ||
6508 | static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value) | 4823 | static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value) |
6509 | { | 4824 | { |
6510 | unsigned long io_addr = hw->io_base; | 4825 | unsigned long io_addr = hw->io_base; |
6511 | unsigned long io_data = hw->io_base + 4; | 4826 | unsigned long io_data = hw->io_base + 4; |
6512 | 4827 | ||
6513 | e1000_io_write(hw, io_addr, offset); | 4828 | e1000_io_write(hw, io_addr, offset); |
6514 | e1000_io_write(hw, io_data, value); | 4829 | e1000_io_write(hw, io_data, value); |
6515 | } | 4830 | } |
6516 | 4831 | ||
6517 | /****************************************************************************** | 4832 | /** |
6518 | * Estimates the cable length. | 4833 | * e1000_get_cable_length - Estimates the cable length. |
6519 | * | 4834 | * @hw: Struct containing variables accessed by shared code |
6520 | * hw - Struct containing variables accessed by shared code | 4835 | * @min_length: The estimated minimum length |
6521 | * min_length - The estimated minimum length | 4836 | * @max_length: The estimated maximum length |
6522 | * max_length - The estimated maximum length | ||
6523 | * | 4837 | * |
6524 | * returns: - E1000_ERR_XXX | 4838 | * returns: - E1000_ERR_XXX |
6525 | * E1000_SUCCESS | 4839 | * E1000_SUCCESS |
@@ -6528,185 +4842,115 @@ static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value) | |||
6528 | * So for M88 phy's, this function interprets the one value returned from the | 4842 | * So for M88 phy's, this function interprets the one value returned from the |
6529 | * register to the minimum and maximum range. | 4843 | * register to the minimum and maximum range. |
6530 | * For IGP phy's, the function calculates the range by the AGC registers. | 4844 | * For IGP phy's, the function calculates the range by the AGC registers. |
6531 | *****************************************************************************/ | 4845 | */ |
6532 | static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, | 4846 | static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, |
6533 | u16 *max_length) | 4847 | u16 *max_length) |
6534 | { | 4848 | { |
6535 | s32 ret_val; | 4849 | s32 ret_val; |
6536 | u16 agc_value = 0; | 4850 | u16 agc_value = 0; |
6537 | u16 i, phy_data; | 4851 | u16 i, phy_data; |
6538 | u16 cable_length; | 4852 | u16 cable_length; |
6539 | 4853 | ||
6540 | DEBUGFUNC("e1000_get_cable_length"); | 4854 | DEBUGFUNC("e1000_get_cable_length"); |
6541 | 4855 | ||
6542 | *min_length = *max_length = 0; | 4856 | *min_length = *max_length = 0; |
6543 | 4857 | ||
6544 | /* Use old method for Phy older than IGP */ | 4858 | /* Use old method for Phy older than IGP */ |
6545 | if (hw->phy_type == e1000_phy_m88) { | 4859 | if (hw->phy_type == e1000_phy_m88) { |
6546 | 4860 | ||
6547 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, | 4861 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
6548 | &phy_data); | 4862 | &phy_data); |
6549 | if (ret_val) | 4863 | if (ret_val) |
6550 | return ret_val; | 4864 | return ret_val; |
6551 | cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> | 4865 | cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
6552 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; | 4866 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; |
6553 | 4867 | ||
6554 | /* Convert the enum value to ranged values */ | 4868 | /* Convert the enum value to ranged values */ |
6555 | switch (cable_length) { | 4869 | switch (cable_length) { |
6556 | case e1000_cable_length_50: | 4870 | case e1000_cable_length_50: |
6557 | *min_length = 0; | 4871 | *min_length = 0; |
6558 | *max_length = e1000_igp_cable_length_50; | 4872 | *max_length = e1000_igp_cable_length_50; |
6559 | break; | 4873 | break; |
6560 | case e1000_cable_length_50_80: | 4874 | case e1000_cable_length_50_80: |
6561 | *min_length = e1000_igp_cable_length_50; | 4875 | *min_length = e1000_igp_cable_length_50; |
6562 | *max_length = e1000_igp_cable_length_80; | 4876 | *max_length = e1000_igp_cable_length_80; |
6563 | break; | 4877 | break; |
6564 | case e1000_cable_length_80_110: | 4878 | case e1000_cable_length_80_110: |
6565 | *min_length = e1000_igp_cable_length_80; | 4879 | *min_length = e1000_igp_cable_length_80; |
6566 | *max_length = e1000_igp_cable_length_110; | 4880 | *max_length = e1000_igp_cable_length_110; |
6567 | break; | 4881 | break; |
6568 | case e1000_cable_length_110_140: | 4882 | case e1000_cable_length_110_140: |
6569 | *min_length = e1000_igp_cable_length_110; | 4883 | *min_length = e1000_igp_cable_length_110; |
6570 | *max_length = e1000_igp_cable_length_140; | 4884 | *max_length = e1000_igp_cable_length_140; |
6571 | break; | 4885 | break; |
6572 | case e1000_cable_length_140: | 4886 | case e1000_cable_length_140: |
6573 | *min_length = e1000_igp_cable_length_140; | 4887 | *min_length = e1000_igp_cable_length_140; |
6574 | *max_length = e1000_igp_cable_length_170; | 4888 | *max_length = e1000_igp_cable_length_170; |
6575 | break; | 4889 | break; |
6576 | default: | 4890 | default: |
6577 | return -E1000_ERR_PHY; | 4891 | return -E1000_ERR_PHY; |
6578 | break; | 4892 | break; |
6579 | } | 4893 | } |
6580 | } else if (hw->phy_type == e1000_phy_gg82563) { | 4894 | } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ |
6581 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, | 4895 | u16 cur_agc_value; |
6582 | &phy_data); | 4896 | u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; |
6583 | if (ret_val) | 4897 | u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = |
6584 | return ret_val; | 4898 | { IGP01E1000_PHY_AGC_A, |
6585 | cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; | 4899 | IGP01E1000_PHY_AGC_B, |
6586 | 4900 | IGP01E1000_PHY_AGC_C, | |
6587 | switch (cable_length) { | 4901 | IGP01E1000_PHY_AGC_D |
6588 | case e1000_gg_cable_length_60: | 4902 | }; |
6589 | *min_length = 0; | 4903 | /* Read the AGC registers for all channels */ |
6590 | *max_length = e1000_igp_cable_length_60; | 4904 | for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
6591 | break; | 4905 | |
6592 | case e1000_gg_cable_length_60_115: | 4906 | ret_val = |
6593 | *min_length = e1000_igp_cable_length_60; | 4907 | e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); |
6594 | *max_length = e1000_igp_cable_length_115; | 4908 | if (ret_val) |
6595 | break; | 4909 | return ret_val; |
6596 | case e1000_gg_cable_length_115_150: | 4910 | |
6597 | *min_length = e1000_igp_cable_length_115; | 4911 | cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; |
6598 | *max_length = e1000_igp_cable_length_150; | 4912 | |
6599 | break; | 4913 | /* Value bound check. */ |
6600 | case e1000_gg_cable_length_150: | 4914 | if ((cur_agc_value >= |
6601 | *min_length = e1000_igp_cable_length_150; | 4915 | IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) |
6602 | *max_length = e1000_igp_cable_length_180; | 4916 | || (cur_agc_value == 0)) |
6603 | break; | 4917 | return -E1000_ERR_PHY; |
6604 | default: | 4918 | |
6605 | return -E1000_ERR_PHY; | 4919 | agc_value += cur_agc_value; |
6606 | break; | 4920 | |
6607 | } | 4921 | /* Update minimal AGC value. */ |
6608 | } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ | 4922 | if (min_agc_value > cur_agc_value) |
6609 | u16 cur_agc_value; | 4923 | min_agc_value = cur_agc_value; |
6610 | u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; | 4924 | } |
6611 | u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = | 4925 | |
6612 | {IGP01E1000_PHY_AGC_A, | 4926 | /* Remove the minimal AGC result for length < 50m */ |
6613 | IGP01E1000_PHY_AGC_B, | 4927 | if (agc_value < |
6614 | IGP01E1000_PHY_AGC_C, | 4928 | IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { |
6615 | IGP01E1000_PHY_AGC_D}; | 4929 | agc_value -= min_agc_value; |
6616 | /* Read the AGC registers for all channels */ | 4930 | |
6617 | for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { | 4931 | /* Get the average length of the remaining 3 channels */ |
6618 | 4932 | agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); | |
6619 | ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); | 4933 | } else { |
6620 | if (ret_val) | 4934 | /* Get the average length of all the 4 channels. */ |
6621 | return ret_val; | 4935 | agc_value /= IGP01E1000_PHY_CHANNEL_NUM; |
6622 | 4936 | } | |
6623 | cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; | 4937 | |
6624 | 4938 | /* Set the range of the calculated length. */ | |
6625 | /* Value bound check. */ | 4939 | *min_length = ((e1000_igp_cable_length_table[agc_value] - |
6626 | if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || | 4940 | IGP01E1000_AGC_RANGE) > 0) ? |
6627 | (cur_agc_value == 0)) | 4941 | (e1000_igp_cable_length_table[agc_value] - |
6628 | return -E1000_ERR_PHY; | 4942 | IGP01E1000_AGC_RANGE) : 0; |
6629 | 4943 | *max_length = e1000_igp_cable_length_table[agc_value] + | |
6630 | agc_value += cur_agc_value; | 4944 | IGP01E1000_AGC_RANGE; |
6631 | 4945 | } | |
6632 | /* Update minimal AGC value. */ | 4946 | |
6633 | if (min_agc_value > cur_agc_value) | 4947 | return E1000_SUCCESS; |
6634 | min_agc_value = cur_agc_value; | ||
6635 | } | ||
6636 | |||
6637 | /* Remove the minimal AGC result for length < 50m */ | ||
6638 | if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { | ||
6639 | agc_value -= min_agc_value; | ||
6640 | |||
6641 | /* Get the average length of the remaining 3 channels */ | ||
6642 | agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); | ||
6643 | } else { | ||
6644 | /* Get the average length of all the 4 channels. */ | ||
6645 | agc_value /= IGP01E1000_PHY_CHANNEL_NUM; | ||
6646 | } | ||
6647 | |||
6648 | /* Set the range of the calculated length. */ | ||
6649 | *min_length = ((e1000_igp_cable_length_table[agc_value] - | ||
6650 | IGP01E1000_AGC_RANGE) > 0) ? | ||
6651 | (e1000_igp_cable_length_table[agc_value] - | ||
6652 | IGP01E1000_AGC_RANGE) : 0; | ||
6653 | *max_length = e1000_igp_cable_length_table[agc_value] + | ||
6654 | IGP01E1000_AGC_RANGE; | ||
6655 | } else if (hw->phy_type == e1000_phy_igp_2 || | ||
6656 | hw->phy_type == e1000_phy_igp_3) { | ||
6657 | u16 cur_agc_index, max_agc_index = 0; | ||
6658 | u16 min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; | ||
6659 | u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = | ||
6660 | {IGP02E1000_PHY_AGC_A, | ||
6661 | IGP02E1000_PHY_AGC_B, | ||
6662 | IGP02E1000_PHY_AGC_C, | ||
6663 | IGP02E1000_PHY_AGC_D}; | ||
6664 | /* Read the AGC registers for all channels */ | ||
6665 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { | ||
6666 | ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); | ||
6667 | if (ret_val) | ||
6668 | return ret_val; | ||
6669 | |||
6670 | /* Getting bits 15:9, which represent the combination of course and | ||
6671 | * fine gain values. The result is a number that can be put into | ||
6672 | * the lookup table to obtain the approximate cable length. */ | ||
6673 | cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & | ||
6674 | IGP02E1000_AGC_LENGTH_MASK; | ||
6675 | |||
6676 | /* Array index bound check. */ | ||
6677 | if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) || | ||
6678 | (cur_agc_index == 0)) | ||
6679 | return -E1000_ERR_PHY; | ||
6680 | |||
6681 | /* Remove min & max AGC values from calculation. */ | ||
6682 | if (e1000_igp_2_cable_length_table[min_agc_index] > | ||
6683 | e1000_igp_2_cable_length_table[cur_agc_index]) | ||
6684 | min_agc_index = cur_agc_index; | ||
6685 | if (e1000_igp_2_cable_length_table[max_agc_index] < | ||
6686 | e1000_igp_2_cable_length_table[cur_agc_index]) | ||
6687 | max_agc_index = cur_agc_index; | ||
6688 | |||
6689 | agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; | ||
6690 | } | ||
6691 | |||
6692 | agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + | ||
6693 | e1000_igp_2_cable_length_table[max_agc_index]); | ||
6694 | agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); | ||
6695 | |||
6696 | /* Calculate cable length with the error range of +/- 10 meters. */ | ||
6697 | *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? | ||
6698 | (agc_value - IGP02E1000_AGC_RANGE) : 0; | ||
6699 | *max_length = agc_value + IGP02E1000_AGC_RANGE; | ||
6700 | } | ||
6701 | |||
6702 | return E1000_SUCCESS; | ||
6703 | } | 4948 | } |
6704 | 4949 | ||
6705 | /****************************************************************************** | 4950 | /** |
6706 | * Check the cable polarity | 4951 | * e1000_check_polarity - Check the cable polarity |
6707 | * | 4952 | * @hw: Struct containing variables accessed by shared code |
6708 | * hw - Struct containing variables accessed by shared code | 4953 | * @polarity: output parameter : 0 - Polarity is not reversed |
6709 | * polarity - output parameter : 0 - Polarity is not reversed | ||
6710 | * 1 - Polarity is reversed. | 4954 | * 1 - Polarity is reversed. |
6711 | * | 4955 | * |
6712 | * returns: - E1000_ERR_XXX | 4956 | * returns: - E1000_ERR_XXX |
@@ -6717,73 +4961,65 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, | |||
6717 | * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will | 4961 | * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will |
6718 | * return 0. If the link speed is 1000 Mbps the polarity status is in the | 4962 | * return 0. If the link speed is 1000 Mbps the polarity status is in the |
6719 | * IGP01E1000_PHY_PCS_INIT_REG. | 4963 | * IGP01E1000_PHY_PCS_INIT_REG. |
6720 | *****************************************************************************/ | 4964 | */ |
6721 | static s32 e1000_check_polarity(struct e1000_hw *hw, | 4965 | static s32 e1000_check_polarity(struct e1000_hw *hw, |
6722 | e1000_rev_polarity *polarity) | 4966 | e1000_rev_polarity *polarity) |
6723 | { | 4967 | { |
6724 | s32 ret_val; | 4968 | s32 ret_val; |
6725 | u16 phy_data; | 4969 | u16 phy_data; |
6726 | 4970 | ||
6727 | DEBUGFUNC("e1000_check_polarity"); | 4971 | DEBUGFUNC("e1000_check_polarity"); |
6728 | 4972 | ||
6729 | if ((hw->phy_type == e1000_phy_m88) || | 4973 | if (hw->phy_type == e1000_phy_m88) { |
6730 | (hw->phy_type == e1000_phy_gg82563)) { | 4974 | /* return the Polarity bit in the Status register. */ |
6731 | /* return the Polarity bit in the Status register. */ | 4975 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
6732 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, | 4976 | &phy_data); |
6733 | &phy_data); | 4977 | if (ret_val) |
6734 | if (ret_val) | 4978 | return ret_val; |
6735 | return ret_val; | 4979 | *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> |
6736 | *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> | 4980 | M88E1000_PSSR_REV_POLARITY_SHIFT) ? |
6737 | M88E1000_PSSR_REV_POLARITY_SHIFT) ? | 4981 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; |
6738 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; | 4982 | |
6739 | 4983 | } else if (hw->phy_type == e1000_phy_igp) { | |
6740 | } else if (hw->phy_type == e1000_phy_igp || | 4984 | /* Read the Status register to check the speed */ |
6741 | hw->phy_type == e1000_phy_igp_3 || | 4985 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, |
6742 | hw->phy_type == e1000_phy_igp_2) { | 4986 | &phy_data); |
6743 | /* Read the Status register to check the speed */ | 4987 | if (ret_val) |
6744 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, | 4988 | return ret_val; |
6745 | &phy_data); | 4989 | |
6746 | if (ret_val) | 4990 | /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to |
6747 | return ret_val; | 4991 | * find the polarity status */ |
6748 | 4992 | if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == | |
6749 | /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to | 4993 | IGP01E1000_PSSR_SPEED_1000MBPS) { |
6750 | * find the polarity status */ | 4994 | |
6751 | if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == | 4995 | /* Read the GIG initialization PCS register (0x00B4) */ |
6752 | IGP01E1000_PSSR_SPEED_1000MBPS) { | 4996 | ret_val = |
6753 | 4997 | e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, | |
6754 | /* Read the GIG initialization PCS register (0x00B4) */ | 4998 | &phy_data); |
6755 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, | 4999 | if (ret_val) |
6756 | &phy_data); | 5000 | return ret_val; |
6757 | if (ret_val) | 5001 | |
6758 | return ret_val; | 5002 | /* Check the polarity bits */ |
6759 | 5003 | *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? | |
6760 | /* Check the polarity bits */ | 5004 | e1000_rev_polarity_reversed : |
6761 | *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? | 5005 | e1000_rev_polarity_normal; |
6762 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; | 5006 | } else { |
6763 | } else { | 5007 | /* For 10 Mbps, read the polarity bit in the status register. (for |
6764 | /* For 10 Mbps, read the polarity bit in the status register. (for | 5008 | * 100 Mbps this bit is always 0) */ |
6765 | * 100 Mbps this bit is always 0) */ | 5009 | *polarity = |
6766 | *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? | 5010 | (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? |
6767 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; | 5011 | e1000_rev_polarity_reversed : |
6768 | } | 5012 | e1000_rev_polarity_normal; |
6769 | } else if (hw->phy_type == e1000_phy_ife) { | 5013 | } |
6770 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL, | 5014 | } |
6771 | &phy_data); | 5015 | return E1000_SUCCESS; |
6772 | if (ret_val) | ||
6773 | return ret_val; | ||
6774 | *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >> | ||
6775 | IFE_PESC_POLARITY_REVERSED_SHIFT) ? | ||
6776 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; | ||
6777 | } | ||
6778 | return E1000_SUCCESS; | ||
6779 | } | 5016 | } |
6780 | 5017 | ||
6781 | /****************************************************************************** | 5018 | /** |
6782 | * Check if Downshift occured | 5019 | * e1000_check_downshift - Check if Downshift occurred |
6783 | * | 5020 | * @hw: Struct containing variables accessed by shared code |
6784 | * hw - Struct containing variables accessed by shared code | 5021 | * @downshift: output parameter : 0 - No Downshift occurred. |
6785 | * downshift - output parameter : 0 - No Downshift ocured. | 5022 | * 1 - Downshift occurred. |
6786 | * 1 - Downshift ocured. | ||
6787 | * | 5023 | * |
6788 | * returns: - E1000_ERR_XXX | 5024 | * returns: - E1000_ERR_XXX |
6789 | * E1000_SUCCESS | 5025 | * E1000_SUCCESS |
@@ -6792,2041 +5028,607 @@ static s32 e1000_check_polarity(struct e1000_hw *hw, | |||
6792 | * Specific Status register. For IGP phy's, it reads the Downgrade bit in the | 5028 | * Specific Status register. For IGP phy's, it reads the Downgrade bit in the |
6793 | * Link Health register. In IGP this bit is latched high, so the driver must | 5029 | * Link Health register. In IGP this bit is latched high, so the driver must |
6794 | * read it immediately after link is established. | 5030 | * read it immediately after link is established. |
6795 | *****************************************************************************/ | 5031 | */ |
6796 | static s32 e1000_check_downshift(struct e1000_hw *hw) | 5032 | static s32 e1000_check_downshift(struct e1000_hw *hw) |
6797 | { | 5033 | { |
6798 | s32 ret_val; | 5034 | s32 ret_val; |
6799 | u16 phy_data; | 5035 | u16 phy_data; |
6800 | |||
6801 | DEBUGFUNC("e1000_check_downshift"); | ||
6802 | |||
6803 | if (hw->phy_type == e1000_phy_igp || | ||
6804 | hw->phy_type == e1000_phy_igp_3 || | ||
6805 | hw->phy_type == e1000_phy_igp_2) { | ||
6806 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, | ||
6807 | &phy_data); | ||
6808 | if (ret_val) | ||
6809 | return ret_val; | ||
6810 | |||
6811 | hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; | ||
6812 | } else if ((hw->phy_type == e1000_phy_m88) || | ||
6813 | (hw->phy_type == e1000_phy_gg82563)) { | ||
6814 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, | ||
6815 | &phy_data); | ||
6816 | if (ret_val) | ||
6817 | return ret_val; | ||
6818 | |||
6819 | hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> | ||
6820 | M88E1000_PSSR_DOWNSHIFT_SHIFT; | ||
6821 | } else if (hw->phy_type == e1000_phy_ife) { | ||
6822 | /* e1000_phy_ife supports 10/100 speed only */ | ||
6823 | hw->speed_downgraded = false; | ||
6824 | } | ||
6825 | |||
6826 | return E1000_SUCCESS; | ||
6827 | } | ||
6828 | 5036 | ||
6829 | /***************************************************************************** | 5037 | DEBUGFUNC("e1000_check_downshift"); |
6830 | * | ||
6831 | * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a | ||
6832 | * gigabit link is achieved to improve link quality. | ||
6833 | * | ||
6834 | * hw: Struct containing variables accessed by shared code | ||
6835 | * | ||
6836 | * returns: - E1000_ERR_PHY if fail to read/write the PHY | ||
6837 | * E1000_SUCCESS at any other case. | ||
6838 | * | ||
6839 | ****************************************************************************/ | ||
6840 | 5038 | ||
6841 | static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up) | 5039 | if (hw->phy_type == e1000_phy_igp) { |
6842 | { | 5040 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, |
6843 | s32 ret_val; | 5041 | &phy_data); |
6844 | u16 phy_data, phy_saved_data, speed, duplex, i; | 5042 | if (ret_val) |
6845 | u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = | 5043 | return ret_val; |
6846 | {IGP01E1000_PHY_AGC_PARAM_A, | ||
6847 | IGP01E1000_PHY_AGC_PARAM_B, | ||
6848 | IGP01E1000_PHY_AGC_PARAM_C, | ||
6849 | IGP01E1000_PHY_AGC_PARAM_D}; | ||
6850 | u16 min_length, max_length; | ||
6851 | |||
6852 | DEBUGFUNC("e1000_config_dsp_after_link_change"); | ||
6853 | |||
6854 | if (hw->phy_type != e1000_phy_igp) | ||
6855 | return E1000_SUCCESS; | ||
6856 | |||
6857 | if (link_up) { | ||
6858 | ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); | ||
6859 | if (ret_val) { | ||
6860 | DEBUGOUT("Error getting link speed and duplex\n"); | ||
6861 | return ret_val; | ||
6862 | } | ||
6863 | |||
6864 | if (speed == SPEED_1000) { | ||
6865 | |||
6866 | ret_val = e1000_get_cable_length(hw, &min_length, &max_length); | ||
6867 | if (ret_val) | ||
6868 | return ret_val; | ||
6869 | |||
6870 | if ((hw->dsp_config_state == e1000_dsp_config_enabled) && | ||
6871 | min_length >= e1000_igp_cable_length_50) { | ||
6872 | |||
6873 | for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { | ||
6874 | ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], | ||
6875 | &phy_data); | ||
6876 | if (ret_val) | ||
6877 | return ret_val; | ||
6878 | |||
6879 | phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; | ||
6880 | |||
6881 | ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], | ||
6882 | phy_data); | ||
6883 | if (ret_val) | ||
6884 | return ret_val; | ||
6885 | } | ||
6886 | hw->dsp_config_state = e1000_dsp_config_activated; | ||
6887 | } | ||
6888 | |||
6889 | if ((hw->ffe_config_state == e1000_ffe_config_enabled) && | ||
6890 | (min_length < e1000_igp_cable_length_50)) { | ||
6891 | |||
6892 | u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; | ||
6893 | u32 idle_errs = 0; | ||
6894 | |||
6895 | /* clear previous idle error counts */ | ||
6896 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, | ||
6897 | &phy_data); | ||
6898 | if (ret_val) | ||
6899 | return ret_val; | ||
6900 | |||
6901 | for (i = 0; i < ffe_idle_err_timeout; i++) { | ||
6902 | udelay(1000); | ||
6903 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, | ||
6904 | &phy_data); | ||
6905 | if (ret_val) | ||
6906 | return ret_val; | ||
6907 | |||
6908 | idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); | ||
6909 | if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { | ||
6910 | hw->ffe_config_state = e1000_ffe_config_active; | ||
6911 | |||
6912 | ret_val = e1000_write_phy_reg(hw, | ||
6913 | IGP01E1000_PHY_DSP_FFE, | ||
6914 | IGP01E1000_PHY_DSP_FFE_CM_CP); | ||
6915 | if (ret_val) | ||
6916 | return ret_val; | ||
6917 | break; | ||
6918 | } | ||
6919 | |||
6920 | if (idle_errs) | ||
6921 | ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; | ||
6922 | } | ||
6923 | } | ||
6924 | } | ||
6925 | } else { | ||
6926 | if (hw->dsp_config_state == e1000_dsp_config_activated) { | ||
6927 | /* Save off the current value of register 0x2F5B to be restored at | ||
6928 | * the end of the routines. */ | ||
6929 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); | ||
6930 | |||
6931 | if (ret_val) | ||
6932 | return ret_val; | ||
6933 | |||
6934 | /* Disable the PHY transmitter */ | ||
6935 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); | ||
6936 | |||
6937 | if (ret_val) | ||
6938 | return ret_val; | ||
6939 | |||
6940 | mdelay(20); | ||
6941 | |||
6942 | ret_val = e1000_write_phy_reg(hw, 0x0000, | ||
6943 | IGP01E1000_IEEE_FORCE_GIGA); | ||
6944 | if (ret_val) | ||
6945 | return ret_val; | ||
6946 | for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { | ||
6947 | ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data); | ||
6948 | if (ret_val) | ||
6949 | return ret_val; | ||
6950 | |||
6951 | phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; | ||
6952 | phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; | ||
6953 | |||
6954 | ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data); | ||
6955 | if (ret_val) | ||
6956 | return ret_val; | ||
6957 | } | ||
6958 | |||
6959 | ret_val = e1000_write_phy_reg(hw, 0x0000, | ||
6960 | IGP01E1000_IEEE_RESTART_AUTONEG); | ||
6961 | if (ret_val) | ||
6962 | return ret_val; | ||
6963 | |||
6964 | mdelay(20); | ||
6965 | |||
6966 | /* Now enable the transmitter */ | ||
6967 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | ||
6968 | |||
6969 | if (ret_val) | ||
6970 | return ret_val; | ||
6971 | |||
6972 | hw->dsp_config_state = e1000_dsp_config_enabled; | ||
6973 | } | ||
6974 | |||
6975 | if (hw->ffe_config_state == e1000_ffe_config_active) { | ||
6976 | /* Save off the current value of register 0x2F5B to be restored at | ||
6977 | * the end of the routines. */ | ||
6978 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); | ||
6979 | |||
6980 | if (ret_val) | ||
6981 | return ret_val; | ||
6982 | |||
6983 | /* Disable the PHY transmitter */ | ||
6984 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); | ||
6985 | |||
6986 | if (ret_val) | ||
6987 | return ret_val; | ||
6988 | |||
6989 | mdelay(20); | ||
6990 | |||
6991 | ret_val = e1000_write_phy_reg(hw, 0x0000, | ||
6992 | IGP01E1000_IEEE_FORCE_GIGA); | ||
6993 | if (ret_val) | ||
6994 | return ret_val; | ||
6995 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, | ||
6996 | IGP01E1000_PHY_DSP_FFE_DEFAULT); | ||
6997 | if (ret_val) | ||
6998 | return ret_val; | ||
6999 | |||
7000 | ret_val = e1000_write_phy_reg(hw, 0x0000, | ||
7001 | IGP01E1000_IEEE_RESTART_AUTONEG); | ||
7002 | if (ret_val) | ||
7003 | return ret_val; | ||
7004 | |||
7005 | mdelay(20); | ||
7006 | |||
7007 | /* Now enable the transmitter */ | ||
7008 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | ||
7009 | |||
7010 | if (ret_val) | ||
7011 | return ret_val; | ||
7012 | |||
7013 | hw->ffe_config_state = e1000_ffe_config_enabled; | ||
7014 | } | ||
7015 | } | ||
7016 | return E1000_SUCCESS; | ||
7017 | } | ||
7018 | 5044 | ||
7019 | /***************************************************************************** | 5045 | hw->speed_downgraded = |
7020 | * Set PHY to class A mode | 5046 | (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; |
7021 | * Assumes the following operations will follow to enable the new class mode. | 5047 | } else if (hw->phy_type == e1000_phy_m88) { |
7022 | * 1. Do a PHY soft reset | 5048 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
7023 | * 2. Restart auto-negotiation or force link. | 5049 | &phy_data); |
7024 | * | 5050 | if (ret_val) |
7025 | * hw - Struct containing variables accessed by shared code | 5051 | return ret_val; |
7026 | ****************************************************************************/ | ||
7027 | static s32 e1000_set_phy_mode(struct e1000_hw *hw) | ||
7028 | { | ||
7029 | s32 ret_val; | ||
7030 | u16 eeprom_data; | ||
7031 | |||
7032 | DEBUGFUNC("e1000_set_phy_mode"); | ||
7033 | |||
7034 | if ((hw->mac_type == e1000_82545_rev_3) && | ||
7035 | (hw->media_type == e1000_media_type_copper)) { | ||
7036 | ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); | ||
7037 | if (ret_val) { | ||
7038 | return ret_val; | ||
7039 | } | ||
7040 | |||
7041 | if ((eeprom_data != EEPROM_RESERVED_WORD) && | ||
7042 | (eeprom_data & EEPROM_PHY_CLASS_A)) { | ||
7043 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); | ||
7044 | if (ret_val) | ||
7045 | return ret_val; | ||
7046 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); | ||
7047 | if (ret_val) | ||
7048 | return ret_val; | ||
7049 | |||
7050 | hw->phy_reset_disable = false; | ||
7051 | } | ||
7052 | } | ||
7053 | |||
7054 | return E1000_SUCCESS; | ||
7055 | } | ||
7056 | 5052 | ||
7057 | /***************************************************************************** | 5053 | hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> |
7058 | * | 5054 | M88E1000_PSSR_DOWNSHIFT_SHIFT; |
7059 | * This function sets the lplu state according to the active flag. When | 5055 | } |
7060 | * activating lplu this function also disables smart speed and vise versa. | ||
7061 | * lplu will not be activated unless the device autonegotiation advertisment | ||
7062 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. | ||
7063 | * hw: Struct containing variables accessed by shared code | ||
7064 | * active - true to enable lplu false to disable lplu. | ||
7065 | * | ||
7066 | * returns: - E1000_ERR_PHY if fail to read/write the PHY | ||
7067 | * E1000_SUCCESS at any other case. | ||
7068 | * | ||
7069 | ****************************************************************************/ | ||
7070 | 5056 | ||
7071 | static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) | 5057 | return E1000_SUCCESS; |
7072 | { | ||
7073 | u32 phy_ctrl = 0; | ||
7074 | s32 ret_val; | ||
7075 | u16 phy_data; | ||
7076 | DEBUGFUNC("e1000_set_d3_lplu_state"); | ||
7077 | |||
7078 | if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 | ||
7079 | && hw->phy_type != e1000_phy_igp_3) | ||
7080 | return E1000_SUCCESS; | ||
7081 | |||
7082 | /* During driver activity LPLU should not be used or it will attain link | ||
7083 | * from the lowest speeds starting from 10Mbps. The capability is used for | ||
7084 | * Dx transitions and states */ | ||
7085 | if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { | ||
7086 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); | ||
7087 | if (ret_val) | ||
7088 | return ret_val; | ||
7089 | } else if (hw->mac_type == e1000_ich8lan) { | ||
7090 | /* MAC writes into PHY register based on the state transition | ||
7091 | * and start auto-negotiation. SW driver can overwrite the settings | ||
7092 | * in CSR PHY power control E1000_PHY_CTRL register. */ | ||
7093 | phy_ctrl = er32(PHY_CTRL); | ||
7094 | } else { | ||
7095 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); | ||
7096 | if (ret_val) | ||
7097 | return ret_val; | ||
7098 | } | ||
7099 | |||
7100 | if (!active) { | ||
7101 | if (hw->mac_type == e1000_82541_rev_2 || | ||
7102 | hw->mac_type == e1000_82547_rev_2) { | ||
7103 | phy_data &= ~IGP01E1000_GMII_FLEX_SPD; | ||
7104 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); | ||
7105 | if (ret_val) | ||
7106 | return ret_val; | ||
7107 | } else { | ||
7108 | if (hw->mac_type == e1000_ich8lan) { | ||
7109 | phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; | ||
7110 | ew32(PHY_CTRL, phy_ctrl); | ||
7111 | } else { | ||
7112 | phy_data &= ~IGP02E1000_PM_D3_LPLU; | ||
7113 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, | ||
7114 | phy_data); | ||
7115 | if (ret_val) | ||
7116 | return ret_val; | ||
7117 | } | ||
7118 | } | ||
7119 | |||
7120 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during | ||
7121 | * Dx states where the power conservation is most important. During | ||
7122 | * driver activity we should enable SmartSpeed, so performance is | ||
7123 | * maintained. */ | ||
7124 | if (hw->smart_speed == e1000_smart_speed_on) { | ||
7125 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | ||
7126 | &phy_data); | ||
7127 | if (ret_val) | ||
7128 | return ret_val; | ||
7129 | |||
7130 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; | ||
7131 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | ||
7132 | phy_data); | ||
7133 | if (ret_val) | ||
7134 | return ret_val; | ||
7135 | } else if (hw->smart_speed == e1000_smart_speed_off) { | ||
7136 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | ||
7137 | &phy_data); | ||
7138 | if (ret_val) | ||
7139 | return ret_val; | ||
7140 | |||
7141 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | ||
7142 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | ||
7143 | phy_data); | ||
7144 | if (ret_val) | ||
7145 | return ret_val; | ||
7146 | } | ||
7147 | |||
7148 | } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || | ||
7149 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || | ||
7150 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { | ||
7151 | |||
7152 | if (hw->mac_type == e1000_82541_rev_2 || | ||
7153 | hw->mac_type == e1000_82547_rev_2) { | ||
7154 | phy_data |= IGP01E1000_GMII_FLEX_SPD; | ||
7155 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); | ||
7156 | if (ret_val) | ||
7157 | return ret_val; | ||
7158 | } else { | ||
7159 | if (hw->mac_type == e1000_ich8lan) { | ||
7160 | phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; | ||
7161 | ew32(PHY_CTRL, phy_ctrl); | ||
7162 | } else { | ||
7163 | phy_data |= IGP02E1000_PM_D3_LPLU; | ||
7164 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, | ||
7165 | phy_data); | ||
7166 | if (ret_val) | ||
7167 | return ret_val; | ||
7168 | } | ||
7169 | } | ||
7170 | |||
7171 | /* When LPLU is enabled we should disable SmartSpeed */ | ||
7172 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); | ||
7173 | if (ret_val) | ||
7174 | return ret_val; | ||
7175 | |||
7176 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | ||
7177 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); | ||
7178 | if (ret_val) | ||
7179 | return ret_val; | ||
7180 | |||
7181 | } | ||
7182 | return E1000_SUCCESS; | ||
7183 | } | 5058 | } |
7184 | 5059 | ||
7185 | /***************************************************************************** | 5060 | /** |
7186 | * | 5061 | * e1000_config_dsp_after_link_change |
7187 | * This function sets the lplu d0 state according to the active flag. When | 5062 | * @hw: Struct containing variables accessed by shared code |
7188 | * activating lplu this function also disables smart speed and vise versa. | 5063 | * @link_up: was link up at the time this was called |
7189 | * lplu will not be activated unless the device autonegotiation advertisment | ||
7190 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. | ||
7191 | * hw: Struct containing variables accessed by shared code | ||
7192 | * active - true to enable lplu false to disable lplu. | ||
7193 | * | 5064 | * |
7194 | * returns: - E1000_ERR_PHY if fail to read/write the PHY | 5065 | * returns: - E1000_ERR_PHY if fail to read/write the PHY |
7195 | * E1000_SUCCESS at any other case. | 5066 | * E1000_SUCCESS at any other case. |
7196 | * | 5067 | * |
7197 | ****************************************************************************/ | 5068 | * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a |
7198 | 5069 | * gigabit link is achieved to improve link quality. | |
7199 | static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) | 5070 | */ |
7200 | { | ||
7201 | u32 phy_ctrl = 0; | ||
7202 | s32 ret_val; | ||
7203 | u16 phy_data; | ||
7204 | DEBUGFUNC("e1000_set_d0_lplu_state"); | ||
7205 | |||
7206 | if (hw->mac_type <= e1000_82547_rev_2) | ||
7207 | return E1000_SUCCESS; | ||
7208 | |||
7209 | if (hw->mac_type == e1000_ich8lan) { | ||
7210 | phy_ctrl = er32(PHY_CTRL); | ||
7211 | } else { | ||
7212 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); | ||
7213 | if (ret_val) | ||
7214 | return ret_val; | ||
7215 | } | ||
7216 | |||
7217 | if (!active) { | ||
7218 | if (hw->mac_type == e1000_ich8lan) { | ||
7219 | phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; | ||
7220 | ew32(PHY_CTRL, phy_ctrl); | ||
7221 | } else { | ||
7222 | phy_data &= ~IGP02E1000_PM_D0_LPLU; | ||
7223 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); | ||
7224 | if (ret_val) | ||
7225 | return ret_val; | ||
7226 | } | ||
7227 | |||
7228 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during | ||
7229 | * Dx states where the power conservation is most important. During | ||
7230 | * driver activity we should enable SmartSpeed, so performance is | ||
7231 | * maintained. */ | ||
7232 | if (hw->smart_speed == e1000_smart_speed_on) { | ||
7233 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | ||
7234 | &phy_data); | ||
7235 | if (ret_val) | ||
7236 | return ret_val; | ||
7237 | |||
7238 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; | ||
7239 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | ||
7240 | phy_data); | ||
7241 | if (ret_val) | ||
7242 | return ret_val; | ||
7243 | } else if (hw->smart_speed == e1000_smart_speed_off) { | ||
7244 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | ||
7245 | &phy_data); | ||
7246 | if (ret_val) | ||
7247 | return ret_val; | ||
7248 | |||
7249 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | ||
7250 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | ||
7251 | phy_data); | ||
7252 | if (ret_val) | ||
7253 | return ret_val; | ||
7254 | } | ||
7255 | |||
7256 | |||
7257 | } else { | ||
7258 | |||
7259 | if (hw->mac_type == e1000_ich8lan) { | ||
7260 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; | ||
7261 | ew32(PHY_CTRL, phy_ctrl); | ||
7262 | } else { | ||
7263 | phy_data |= IGP02E1000_PM_D0_LPLU; | ||
7264 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); | ||
7265 | if (ret_val) | ||
7266 | return ret_val; | ||
7267 | } | ||
7268 | |||
7269 | /* When LPLU is enabled we should disable SmartSpeed */ | ||
7270 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); | ||
7271 | if (ret_val) | ||
7272 | return ret_val; | ||
7273 | |||
7274 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | ||
7275 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); | ||
7276 | if (ret_val) | ||
7277 | return ret_val; | ||
7278 | |||
7279 | } | ||
7280 | return E1000_SUCCESS; | ||
7281 | } | ||
7282 | 5071 | ||
7283 | /****************************************************************************** | 5072 | static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up) |
7284 | * Change VCO speed register to improve Bit Error Rate performance of SERDES. | ||
7285 | * | ||
7286 | * hw - Struct containing variables accessed by shared code | ||
7287 | *****************************************************************************/ | ||
7288 | static s32 e1000_set_vco_speed(struct e1000_hw *hw) | ||
7289 | { | 5073 | { |
7290 | s32 ret_val; | 5074 | s32 ret_val; |
7291 | u16 default_page = 0; | 5075 | u16 phy_data, phy_saved_data, speed, duplex, i; |
7292 | u16 phy_data; | 5076 | u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = |
7293 | 5077 | { IGP01E1000_PHY_AGC_PARAM_A, | |
7294 | DEBUGFUNC("e1000_set_vco_speed"); | 5078 | IGP01E1000_PHY_AGC_PARAM_B, |
5079 | IGP01E1000_PHY_AGC_PARAM_C, | ||
5080 | IGP01E1000_PHY_AGC_PARAM_D | ||
5081 | }; | ||
5082 | u16 min_length, max_length; | ||
5083 | |||
5084 | DEBUGFUNC("e1000_config_dsp_after_link_change"); | ||
5085 | |||
5086 | if (hw->phy_type != e1000_phy_igp) | ||
5087 | return E1000_SUCCESS; | ||
5088 | |||
5089 | if (link_up) { | ||
5090 | ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); | ||
5091 | if (ret_val) { | ||
5092 | DEBUGOUT("Error getting link speed and duplex\n"); | ||
5093 | return ret_val; | ||
5094 | } | ||
7295 | 5095 | ||
7296 | switch (hw->mac_type) { | 5096 | if (speed == SPEED_1000) { |
7297 | case e1000_82545_rev_3: | 5097 | |
7298 | case e1000_82546_rev_3: | 5098 | ret_val = |
7299 | break; | 5099 | e1000_get_cable_length(hw, &min_length, |
7300 | default: | 5100 | &max_length); |
7301 | return E1000_SUCCESS; | 5101 | if (ret_val) |
7302 | } | 5102 | return ret_val; |
5103 | |||
5104 | if ((hw->dsp_config_state == e1000_dsp_config_enabled) | ||
5105 | && min_length >= e1000_igp_cable_length_50) { | ||
5106 | |||
5107 | for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { | ||
5108 | ret_val = | ||
5109 | e1000_read_phy_reg(hw, | ||
5110 | dsp_reg_array[i], | ||
5111 | &phy_data); | ||
5112 | if (ret_val) | ||
5113 | return ret_val; | ||
5114 | |||
5115 | phy_data &= | ||
5116 | ~IGP01E1000_PHY_EDAC_MU_INDEX; | ||
5117 | |||
5118 | ret_val = | ||
5119 | e1000_write_phy_reg(hw, | ||
5120 | dsp_reg_array | ||
5121 | [i], phy_data); | ||
5122 | if (ret_val) | ||
5123 | return ret_val; | ||
5124 | } | ||
5125 | hw->dsp_config_state = | ||
5126 | e1000_dsp_config_activated; | ||
5127 | } | ||
5128 | |||
5129 | if ((hw->ffe_config_state == e1000_ffe_config_enabled) | ||
5130 | && (min_length < e1000_igp_cable_length_50)) { | ||
5131 | |||
5132 | u16 ffe_idle_err_timeout = | ||
5133 | FFE_IDLE_ERR_COUNT_TIMEOUT_20; | ||
5134 | u32 idle_errs = 0; | ||
5135 | |||
5136 | /* clear previous idle error counts */ | ||
5137 | ret_val = | ||
5138 | e1000_read_phy_reg(hw, PHY_1000T_STATUS, | ||
5139 | &phy_data); | ||
5140 | if (ret_val) | ||
5141 | return ret_val; | ||
5142 | |||
5143 | for (i = 0; i < ffe_idle_err_timeout; i++) { | ||
5144 | udelay(1000); | ||
5145 | ret_val = | ||
5146 | e1000_read_phy_reg(hw, | ||
5147 | PHY_1000T_STATUS, | ||
5148 | &phy_data); | ||
5149 | if (ret_val) | ||
5150 | return ret_val; | ||
5151 | |||
5152 | idle_errs += | ||
5153 | (phy_data & | ||
5154 | SR_1000T_IDLE_ERROR_CNT); | ||
5155 | if (idle_errs > | ||
5156 | SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) | ||
5157 | { | ||
5158 | hw->ffe_config_state = | ||
5159 | e1000_ffe_config_active; | ||
5160 | |||
5161 | ret_val = | ||
5162 | e1000_write_phy_reg(hw, | ||
5163 | IGP01E1000_PHY_DSP_FFE, | ||
5164 | IGP01E1000_PHY_DSP_FFE_CM_CP); | ||
5165 | if (ret_val) | ||
5166 | return ret_val; | ||
5167 | break; | ||
5168 | } | ||
5169 | |||
5170 | if (idle_errs) | ||
5171 | ffe_idle_err_timeout = | ||
5172 | FFE_IDLE_ERR_COUNT_TIMEOUT_100; | ||
5173 | } | ||
5174 | } | ||
5175 | } | ||
5176 | } else { | ||
5177 | if (hw->dsp_config_state == e1000_dsp_config_activated) { | ||
5178 | /* Save off the current value of register 0x2F5B to be restored at | ||
5179 | * the end of the routines. */ | ||
5180 | ret_val = | ||
5181 | e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); | ||
5182 | |||
5183 | if (ret_val) | ||
5184 | return ret_val; | ||
5185 | |||
5186 | /* Disable the PHY transmitter */ | ||
5187 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); | ||
5188 | |||
5189 | if (ret_val) | ||
5190 | return ret_val; | ||
5191 | |||
5192 | mdelay(20); | ||
5193 | |||
5194 | ret_val = e1000_write_phy_reg(hw, 0x0000, | ||
5195 | IGP01E1000_IEEE_FORCE_GIGA); | ||
5196 | if (ret_val) | ||
5197 | return ret_val; | ||
5198 | for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { | ||
5199 | ret_val = | ||
5200 | e1000_read_phy_reg(hw, dsp_reg_array[i], | ||
5201 | &phy_data); | ||
5202 | if (ret_val) | ||
5203 | return ret_val; | ||
5204 | |||
5205 | phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; | ||
5206 | phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; | ||
5207 | |||
5208 | ret_val = | ||
5209 | e1000_write_phy_reg(hw, dsp_reg_array[i], | ||
5210 | phy_data); | ||
5211 | if (ret_val) | ||
5212 | return ret_val; | ||
5213 | } | ||
5214 | |||
5215 | ret_val = e1000_write_phy_reg(hw, 0x0000, | ||
5216 | IGP01E1000_IEEE_RESTART_AUTONEG); | ||
5217 | if (ret_val) | ||
5218 | return ret_val; | ||
5219 | |||
5220 | mdelay(20); | ||
5221 | |||
5222 | /* Now enable the transmitter */ | ||
5223 | ret_val = | ||
5224 | e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | ||
5225 | |||
5226 | if (ret_val) | ||
5227 | return ret_val; | ||
5228 | |||
5229 | hw->dsp_config_state = e1000_dsp_config_enabled; | ||
5230 | } | ||
7303 | 5231 | ||
7304 | /* Set PHY register 30, page 5, bit 8 to 0 */ | 5232 | if (hw->ffe_config_state == e1000_ffe_config_active) { |
5233 | /* Save off the current value of register 0x2F5B to be restored at | ||
5234 | * the end of the routines. */ | ||
5235 | ret_val = | ||
5236 | e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); | ||
7305 | 5237 | ||
7306 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); | 5238 | if (ret_val) |
7307 | if (ret_val) | 5239 | return ret_val; |
7308 | return ret_val; | ||
7309 | 5240 | ||
7310 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); | 5241 | /* Disable the PHY transmitter */ |
7311 | if (ret_val) | 5242 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
7312 | return ret_val; | ||
7313 | 5243 | ||
7314 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); | 5244 | if (ret_val) |
7315 | if (ret_val) | 5245 | return ret_val; |
7316 | return ret_val; | ||
7317 | 5246 | ||
7318 | phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; | 5247 | mdelay(20); |
7319 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); | ||
7320 | if (ret_val) | ||
7321 | return ret_val; | ||
7322 | 5248 | ||
7323 | /* Set PHY register 30, page 4, bit 11 to 1 */ | 5249 | ret_val = e1000_write_phy_reg(hw, 0x0000, |
5250 | IGP01E1000_IEEE_FORCE_GIGA); | ||
5251 | if (ret_val) | ||
5252 | return ret_val; | ||
5253 | ret_val = | ||
5254 | e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, | ||
5255 | IGP01E1000_PHY_DSP_FFE_DEFAULT); | ||
5256 | if (ret_val) | ||
5257 | return ret_val; | ||
7324 | 5258 | ||
7325 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); | 5259 | ret_val = e1000_write_phy_reg(hw, 0x0000, |
7326 | if (ret_val) | 5260 | IGP01E1000_IEEE_RESTART_AUTONEG); |
7327 | return ret_val; | 5261 | if (ret_val) |
5262 | return ret_val; | ||
7328 | 5263 | ||
7329 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); | 5264 | mdelay(20); |
7330 | if (ret_val) | ||
7331 | return ret_val; | ||
7332 | 5265 | ||
7333 | phy_data |= M88E1000_PHY_VCO_REG_BIT11; | 5266 | /* Now enable the transmitter */ |
7334 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); | 5267 | ret_val = |
7335 | if (ret_val) | 5268 | e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
7336 | return ret_val; | ||
7337 | 5269 | ||
7338 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); | 5270 | if (ret_val) |
7339 | if (ret_val) | 5271 | return ret_val; |
7340 | return ret_val; | ||
7341 | 5272 | ||
7342 | return E1000_SUCCESS; | 5273 | hw->ffe_config_state = e1000_ffe_config_enabled; |
5274 | } | ||
5275 | } | ||
5276 | return E1000_SUCCESS; | ||
7343 | } | 5277 | } |
7344 | 5278 | ||
7345 | 5279 | /** | |
7346 | /***************************************************************************** | 5280 | * e1000_set_phy_mode - Set PHY to class A mode |
7347 | * This function reads the cookie from ARC ram. | 5281 | * @hw: Struct containing variables accessed by shared code |
7348 | * | 5282 | * |
7349 | * returns: - E1000_SUCCESS . | 5283 | * Assumes the following operations will follow to enable the new class mode. |
7350 | ****************************************************************************/ | 5284 | * 1. Do a PHY soft reset |
7351 | static s32 e1000_host_if_read_cookie(struct e1000_hw *hw, u8 *buffer) | 5285 | * 2. Restart auto-negotiation or force link. |
5286 | */ | ||
5287 | static s32 e1000_set_phy_mode(struct e1000_hw *hw) | ||
7352 | { | 5288 | { |
7353 | u8 i; | 5289 | s32 ret_val; |
7354 | u32 offset = E1000_MNG_DHCP_COOKIE_OFFSET; | 5290 | u16 eeprom_data; |
7355 | u8 length = E1000_MNG_DHCP_COOKIE_LENGTH; | ||
7356 | |||
7357 | length = (length >> 2); | ||
7358 | offset = (offset >> 2); | ||
7359 | |||
7360 | for (i = 0; i < length; i++) { | ||
7361 | *((u32 *)buffer + i) = | ||
7362 | E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); | ||
7363 | } | ||
7364 | return E1000_SUCCESS; | ||
7365 | } | ||
7366 | 5291 | ||
5292 | DEBUGFUNC("e1000_set_phy_mode"); | ||
7367 | 5293 | ||
7368 | /***************************************************************************** | 5294 | if ((hw->mac_type == e1000_82545_rev_3) && |
7369 | * This function checks whether the HOST IF is enabled for command operaton | 5295 | (hw->media_type == e1000_media_type_copper)) { |
7370 | * and also checks whether the previous command is completed. | 5296 | ret_val = |
7371 | * It busy waits in case of previous command is not completed. | 5297 | e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, |
7372 | * | 5298 | &eeprom_data); |
7373 | * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or | 5299 | if (ret_val) { |
7374 | * timeout | 5300 | return ret_val; |
7375 | * - E1000_SUCCESS for success. | 5301 | } |
7376 | ****************************************************************************/ | ||
7377 | static s32 e1000_mng_enable_host_if(struct e1000_hw *hw) | ||
7378 | { | ||
7379 | u32 hicr; | ||
7380 | u8 i; | ||
7381 | |||
7382 | /* Check that the host interface is enabled. */ | ||
7383 | hicr = er32(HICR); | ||
7384 | if ((hicr & E1000_HICR_EN) == 0) { | ||
7385 | DEBUGOUT("E1000_HOST_EN bit disabled.\n"); | ||
7386 | return -E1000_ERR_HOST_INTERFACE_COMMAND; | ||
7387 | } | ||
7388 | /* check the previous command is completed */ | ||
7389 | for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { | ||
7390 | hicr = er32(HICR); | ||
7391 | if (!(hicr & E1000_HICR_C)) | ||
7392 | break; | ||
7393 | mdelay(1); | ||
7394 | } | ||
7395 | |||
7396 | if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { | ||
7397 | DEBUGOUT("Previous command timeout failed .\n"); | ||
7398 | return -E1000_ERR_HOST_INTERFACE_COMMAND; | ||
7399 | } | ||
7400 | return E1000_SUCCESS; | ||
7401 | } | ||
7402 | 5302 | ||
7403 | /***************************************************************************** | 5303 | if ((eeprom_data != EEPROM_RESERVED_WORD) && |
7404 | * This function writes the buffer content at the offset given on the host if. | 5304 | (eeprom_data & EEPROM_PHY_CLASS_A)) { |
7405 | * It also does alignment considerations to do the writes in most efficient way. | 5305 | ret_val = |
7406 | * Also fills up the sum of the buffer in *buffer parameter. | 5306 | e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, |
7407 | * | 5307 | 0x000B); |
7408 | * returns - E1000_SUCCESS for success. | 5308 | if (ret_val) |
7409 | ****************************************************************************/ | 5309 | return ret_val; |
7410 | static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length, | 5310 | ret_val = |
7411 | u16 offset, u8 *sum) | 5311 | e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, |
7412 | { | 5312 | 0x8104); |
7413 | u8 *tmp; | 5313 | if (ret_val) |
7414 | u8 *bufptr = buffer; | 5314 | return ret_val; |
7415 | u32 data = 0; | 5315 | |
7416 | u16 remaining, i, j, prev_bytes; | 5316 | hw->phy_reset_disable = false; |
7417 | 5317 | } | |
7418 | /* sum = only sum of the data and it is not checksum */ | 5318 | } |
7419 | |||
7420 | if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { | ||
7421 | return -E1000_ERR_PARAM; | ||
7422 | } | ||
7423 | |||
7424 | tmp = (u8 *)&data; | ||
7425 | prev_bytes = offset & 0x3; | ||
7426 | offset &= 0xFFFC; | ||
7427 | offset >>= 2; | ||
7428 | |||
7429 | if (prev_bytes) { | ||
7430 | data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset); | ||
7431 | for (j = prev_bytes; j < sizeof(u32); j++) { | ||
7432 | *(tmp + j) = *bufptr++; | ||
7433 | *sum += *(tmp + j); | ||
7434 | } | ||
7435 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data); | ||
7436 | length -= j - prev_bytes; | ||
7437 | offset++; | ||
7438 | } | ||
7439 | |||
7440 | remaining = length & 0x3; | ||
7441 | length -= remaining; | ||
7442 | |||
7443 | /* Calculate length in DWORDs */ | ||
7444 | length >>= 2; | ||
7445 | |||
7446 | /* The device driver writes the relevant command block into the | ||
7447 | * ram area. */ | ||
7448 | for (i = 0; i < length; i++) { | ||
7449 | for (j = 0; j < sizeof(u32); j++) { | ||
7450 | *(tmp + j) = *bufptr++; | ||
7451 | *sum += *(tmp + j); | ||
7452 | } | ||
7453 | |||
7454 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); | ||
7455 | } | ||
7456 | if (remaining) { | ||
7457 | for (j = 0; j < sizeof(u32); j++) { | ||
7458 | if (j < remaining) | ||
7459 | *(tmp + j) = *bufptr++; | ||
7460 | else | ||
7461 | *(tmp + j) = 0; | ||
7462 | |||
7463 | *sum += *(tmp + j); | ||
7464 | } | ||
7465 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); | ||
7466 | } | ||
7467 | |||
7468 | return E1000_SUCCESS; | ||
7469 | } | ||
7470 | 5319 | ||
5320 | return E1000_SUCCESS; | ||
5321 | } | ||
7471 | 5322 | ||
7472 | /***************************************************************************** | 5323 | /** |
7473 | * This function writes the command header after does the checksum calculation. | 5324 | * e1000_set_d3_lplu_state - set d3 link power state |
5325 | * @hw: Struct containing variables accessed by shared code | ||
5326 | * @active: true to enable lplu false to disable lplu. | ||
5327 | * | ||
5328 | * This function sets the lplu state according to the active flag. When | ||
5329 | * activating lplu this function also disables smart speed and vise versa. | ||
5330 | * lplu will not be activated unless the device autonegotiation advertisement | ||
5331 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. | ||
7474 | * | 5332 | * |
7475 | * returns - E1000_SUCCESS for success. | 5333 | * returns: - E1000_ERR_PHY if fail to read/write the PHY |
7476 | ****************************************************************************/ | 5334 | * E1000_SUCCESS at any other case. |
7477 | static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw, | 5335 | */ |
7478 | struct e1000_host_mng_command_header *hdr) | 5336 | static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) |
7479 | { | 5337 | { |
7480 | u16 i; | 5338 | s32 ret_val; |
7481 | u8 sum; | 5339 | u16 phy_data; |
7482 | u8 *buffer; | 5340 | DEBUGFUNC("e1000_set_d3_lplu_state"); |
7483 | 5341 | ||
7484 | /* Write the whole command header structure which includes sum of | 5342 | if (hw->phy_type != e1000_phy_igp) |
7485 | * the buffer */ | 5343 | return E1000_SUCCESS; |
7486 | 5344 | ||
7487 | u16 length = sizeof(struct e1000_host_mng_command_header); | 5345 | /* During driver activity LPLU should not be used or it will attain link |
5346 | * from the lowest speeds starting from 10Mbps. The capability is used for | ||
5347 | * Dx transitions and states */ | ||
5348 | if (hw->mac_type == e1000_82541_rev_2 | ||
5349 | || hw->mac_type == e1000_82547_rev_2) { | ||
5350 | ret_val = | ||
5351 | e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); | ||
5352 | if (ret_val) | ||
5353 | return ret_val; | ||
5354 | } | ||
7488 | 5355 | ||
7489 | sum = hdr->checksum; | 5356 | if (!active) { |
7490 | hdr->checksum = 0; | 5357 | if (hw->mac_type == e1000_82541_rev_2 || |
5358 | hw->mac_type == e1000_82547_rev_2) { | ||
5359 | phy_data &= ~IGP01E1000_GMII_FLEX_SPD; | ||
5360 | ret_val = | ||
5361 | e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, | ||
5362 | phy_data); | ||
5363 | if (ret_val) | ||
5364 | return ret_val; | ||
5365 | } | ||
7491 | 5366 | ||
7492 | buffer = (u8 *)hdr; | 5367 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during |
7493 | i = length; | 5368 | * Dx states where the power conservation is most important. During |
7494 | while (i--) | 5369 | * driver activity we should enable SmartSpeed, so performance is |
7495 | sum += buffer[i]; | 5370 | * maintained. */ |
5371 | if (hw->smart_speed == e1000_smart_speed_on) { | ||
5372 | ret_val = | ||
5373 | e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | ||
5374 | &phy_data); | ||
5375 | if (ret_val) | ||
5376 | return ret_val; | ||
5377 | |||
5378 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; | ||
5379 | ret_val = | ||
5380 | e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | ||
5381 | phy_data); | ||
5382 | if (ret_val) | ||
5383 | return ret_val; | ||
5384 | } else if (hw->smart_speed == e1000_smart_speed_off) { | ||
5385 | ret_val = | ||
5386 | e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | ||
5387 | &phy_data); | ||
5388 | if (ret_val) | ||
5389 | return ret_val; | ||
5390 | |||
5391 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | ||
5392 | ret_val = | ||
5393 | e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | ||
5394 | phy_data); | ||
5395 | if (ret_val) | ||
5396 | return ret_val; | ||
5397 | } | ||
5398 | } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) | ||
5399 | || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) | ||
5400 | || (hw->autoneg_advertised == | ||
5401 | AUTONEG_ADVERTISE_10_100_ALL)) { | ||
5402 | |||
5403 | if (hw->mac_type == e1000_82541_rev_2 || | ||
5404 | hw->mac_type == e1000_82547_rev_2) { | ||
5405 | phy_data |= IGP01E1000_GMII_FLEX_SPD; | ||
5406 | ret_val = | ||
5407 | e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, | ||
5408 | phy_data); | ||
5409 | if (ret_val) | ||
5410 | return ret_val; | ||
5411 | } | ||
7496 | 5412 | ||
7497 | hdr->checksum = 0 - sum; | 5413 | /* When LPLU is enabled we should disable SmartSpeed */ |
5414 | ret_val = | ||
5415 | e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | ||
5416 | &phy_data); | ||
5417 | if (ret_val) | ||
5418 | return ret_val; | ||
7498 | 5419 | ||
7499 | length >>= 2; | 5420 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
7500 | /* The device driver writes the relevant command block into the ram area. */ | 5421 | ret_val = |
7501 | for (i = 0; i < length; i++) { | 5422 | e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
7502 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((u32 *)hdr + i)); | 5423 | phy_data); |
7503 | E1000_WRITE_FLUSH(); | 5424 | if (ret_val) |
7504 | } | 5425 | return ret_val; |
7505 | 5426 | ||
7506 | return E1000_SUCCESS; | 5427 | } |
5428 | return E1000_SUCCESS; | ||
7507 | } | 5429 | } |
7508 | 5430 | ||
7509 | 5431 | /** | |
7510 | /***************************************************************************** | 5432 | * e1000_set_vco_speed |
7511 | * This function indicates to ARC that a new command is pending which completes | 5433 | * @hw: Struct containing variables accessed by shared code |
7512 | * one write operation by the driver. | ||
7513 | * | 5434 | * |
7514 | * returns - E1000_SUCCESS for success. | 5435 | * Change VCO speed register to improve Bit Error Rate performance of SERDES. |
7515 | ****************************************************************************/ | 5436 | */ |
7516 | static s32 e1000_mng_write_commit(struct e1000_hw *hw) | 5437 | static s32 e1000_set_vco_speed(struct e1000_hw *hw) |
7517 | { | 5438 | { |
7518 | u32 hicr; | 5439 | s32 ret_val; |
5440 | u16 default_page = 0; | ||
5441 | u16 phy_data; | ||
7519 | 5442 | ||
7520 | hicr = er32(HICR); | 5443 | DEBUGFUNC("e1000_set_vco_speed"); |
7521 | /* Setting this bit tells the ARC that a new command is pending. */ | ||
7522 | ew32(HICR, hicr | E1000_HICR_C); | ||
7523 | 5444 | ||
7524 | return E1000_SUCCESS; | 5445 | switch (hw->mac_type) { |
7525 | } | 5446 | case e1000_82545_rev_3: |
5447 | case e1000_82546_rev_3: | ||
5448 | break; | ||
5449 | default: | ||
5450 | return E1000_SUCCESS; | ||
5451 | } | ||
7526 | 5452 | ||
5453 | /* Set PHY register 30, page 5, bit 8 to 0 */ | ||
7527 | 5454 | ||
7528 | /***************************************************************************** | 5455 | ret_val = |
7529 | * This function checks the mode of the firmware. | 5456 | e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); |
7530 | * | 5457 | if (ret_val) |
7531 | * returns - true when the mode is IAMT or false. | 5458 | return ret_val; |
7532 | ****************************************************************************/ | ||
7533 | bool e1000_check_mng_mode(struct e1000_hw *hw) | ||
7534 | { | ||
7535 | u32 fwsm; | ||
7536 | |||
7537 | fwsm = er32(FWSM); | ||
7538 | 5459 | ||
7539 | if (hw->mac_type == e1000_ich8lan) { | 5460 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); |
7540 | if ((fwsm & E1000_FWSM_MODE_MASK) == | 5461 | if (ret_val) |
7541 | (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) | 5462 | return ret_val; |
7542 | return true; | ||
7543 | } else if ((fwsm & E1000_FWSM_MODE_MASK) == | ||
7544 | (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) | ||
7545 | return true; | ||
7546 | 5463 | ||
7547 | return false; | 5464 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); |
7548 | } | 5465 | if (ret_val) |
5466 | return ret_val; | ||
7549 | 5467 | ||
5468 | phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; | ||
5469 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); | ||
5470 | if (ret_val) | ||
5471 | return ret_val; | ||
7550 | 5472 | ||
7551 | /***************************************************************************** | 5473 | /* Set PHY register 30, page 4, bit 11 to 1 */ |
7552 | * This function writes the dhcp info . | ||
7553 | ****************************************************************************/ | ||
7554 | s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length) | ||
7555 | { | ||
7556 | s32 ret_val; | ||
7557 | struct e1000_host_mng_command_header hdr; | ||
7558 | |||
7559 | hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; | ||
7560 | hdr.command_length = length; | ||
7561 | hdr.reserved1 = 0; | ||
7562 | hdr.reserved2 = 0; | ||
7563 | hdr.checksum = 0; | ||
7564 | |||
7565 | ret_val = e1000_mng_enable_host_if(hw); | ||
7566 | if (ret_val == E1000_SUCCESS) { | ||
7567 | ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr), | ||
7568 | &(hdr.checksum)); | ||
7569 | if (ret_val == E1000_SUCCESS) { | ||
7570 | ret_val = e1000_mng_write_cmd_header(hw, &hdr); | ||
7571 | if (ret_val == E1000_SUCCESS) | ||
7572 | ret_val = e1000_mng_write_commit(hw); | ||
7573 | } | ||
7574 | } | ||
7575 | return ret_val; | ||
7576 | } | ||
7577 | 5474 | ||
5475 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); | ||
5476 | if (ret_val) | ||
5477 | return ret_val; | ||
7578 | 5478 | ||
7579 | /***************************************************************************** | 5479 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); |
7580 | * This function calculates the checksum. | 5480 | if (ret_val) |
7581 | * | 5481 | return ret_val; |
7582 | * returns - checksum of buffer contents. | ||
7583 | ****************************************************************************/ | ||
7584 | static u8 e1000_calculate_mng_checksum(char *buffer, u32 length) | ||
7585 | { | ||
7586 | u8 sum = 0; | ||
7587 | u32 i; | ||
7588 | 5482 | ||
7589 | if (!buffer) | 5483 | phy_data |= M88E1000_PHY_VCO_REG_BIT11; |
7590 | return 0; | 5484 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); |
5485 | if (ret_val) | ||
5486 | return ret_val; | ||
7591 | 5487 | ||
7592 | for (i=0; i < length; i++) | 5488 | ret_val = |
7593 | sum += buffer[i]; | 5489 | e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); |
5490 | if (ret_val) | ||
5491 | return ret_val; | ||
7594 | 5492 | ||
7595 | return (u8)(0 - sum); | 5493 | return E1000_SUCCESS; |
7596 | } | 5494 | } |
7597 | 5495 | ||
7598 | /***************************************************************************** | ||
7599 | * This function checks whether tx pkt filtering needs to be enabled or not. | ||
7600 | * | ||
7601 | * returns - true for packet filtering or false. | ||
7602 | ****************************************************************************/ | ||
7603 | bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) | ||
7604 | { | ||
7605 | /* called in init as well as watchdog timer functions */ | ||
7606 | |||
7607 | s32 ret_val, checksum; | ||
7608 | bool tx_filter = false; | ||
7609 | struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); | ||
7610 | u8 *buffer = (u8 *) &(hw->mng_cookie); | ||
7611 | |||
7612 | if (e1000_check_mng_mode(hw)) { | ||
7613 | ret_val = e1000_mng_enable_host_if(hw); | ||
7614 | if (ret_val == E1000_SUCCESS) { | ||
7615 | ret_val = e1000_host_if_read_cookie(hw, buffer); | ||
7616 | if (ret_val == E1000_SUCCESS) { | ||
7617 | checksum = hdr->checksum; | ||
7618 | hdr->checksum = 0; | ||
7619 | if ((hdr->signature == E1000_IAMT_SIGNATURE) && | ||
7620 | checksum == e1000_calculate_mng_checksum((char *)buffer, | ||
7621 | E1000_MNG_DHCP_COOKIE_LENGTH)) { | ||
7622 | if (hdr->status & | ||
7623 | E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) | ||
7624 | tx_filter = true; | ||
7625 | } else | ||
7626 | tx_filter = true; | ||
7627 | } else | ||
7628 | tx_filter = true; | ||
7629 | } | ||
7630 | } | ||
7631 | |||
7632 | hw->tx_pkt_filtering = tx_filter; | ||
7633 | return tx_filter; | ||
7634 | } | ||
7635 | 5496 | ||
7636 | /****************************************************************************** | 5497 | /** |
7637 | * Verifies the hardware needs to allow ARPs to be processed by the host | 5498 | * e1000_enable_mng_pass_thru - check for bmc pass through |
7638 | * | 5499 | * @hw: Struct containing variables accessed by shared code |
7639 | * hw - Struct containing variables accessed by shared code | ||
7640 | * | 5500 | * |
5501 | * Verifies the hardware needs to allow ARPs to be processed by the host | ||
7641 | * returns: - true/false | 5502 | * returns: - true/false |
7642 | * | 5503 | */ |
7643 | *****************************************************************************/ | ||
7644 | u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw) | 5504 | u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw) |
7645 | { | 5505 | { |
7646 | u32 manc; | 5506 | u32 manc; |
7647 | u32 fwsm, factps; | ||
7648 | |||
7649 | if (hw->asf_firmware_present) { | ||
7650 | manc = er32(MANC); | ||
7651 | |||
7652 | if (!(manc & E1000_MANC_RCV_TCO_EN) || | ||
7653 | !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) | ||
7654 | return false; | ||
7655 | if (e1000_arc_subsystem_valid(hw)) { | ||
7656 | fwsm = er32(FWSM); | ||
7657 | factps = er32(FACTPS); | ||
7658 | |||
7659 | if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) == | ||
7660 | e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG)) | ||
7661 | return true; | ||
7662 | } else | ||
7663 | if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) | ||
7664 | return true; | ||
7665 | } | ||
7666 | return false; | ||
7667 | } | ||
7668 | 5507 | ||
7669 | static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw) | 5508 | if (hw->asf_firmware_present) { |
7670 | { | 5509 | manc = er32(MANC); |
7671 | s32 ret_val; | 5510 | |
7672 | u16 mii_status_reg; | 5511 | if (!(manc & E1000_MANC_RCV_TCO_EN) || |
7673 | u16 i; | 5512 | !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) |
7674 | 5513 | return false; | |
7675 | /* Polarity reversal workaround for forced 10F/10H links. */ | 5514 | if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) |
7676 | 5515 | return true; | |
7677 | /* Disable the transmitter on the PHY */ | 5516 | } |
7678 | 5517 | return false; | |
7679 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); | ||
7680 | if (ret_val) | ||
7681 | return ret_val; | ||
7682 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); | ||
7683 | if (ret_val) | ||
7684 | return ret_val; | ||
7685 | |||
7686 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); | ||
7687 | if (ret_val) | ||
7688 | return ret_val; | ||
7689 | |||
7690 | /* This loop will early-out if the NO link condition has been met. */ | ||
7691 | for (i = PHY_FORCE_TIME; i > 0; i--) { | ||
7692 | /* Read the MII Status Register and wait for Link Status bit | ||
7693 | * to be clear. | ||
7694 | */ | ||
7695 | |||
7696 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | ||
7697 | if (ret_val) | ||
7698 | return ret_val; | ||
7699 | |||
7700 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | ||
7701 | if (ret_val) | ||
7702 | return ret_val; | ||
7703 | |||
7704 | if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; | ||
7705 | mdelay(100); | ||
7706 | } | ||
7707 | |||
7708 | /* Recommended delay time after link has been lost */ | ||
7709 | mdelay(1000); | ||
7710 | |||
7711 | /* Now we will re-enable th transmitter on the PHY */ | ||
7712 | |||
7713 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); | ||
7714 | if (ret_val) | ||
7715 | return ret_val; | ||
7716 | mdelay(50); | ||
7717 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); | ||
7718 | if (ret_val) | ||
7719 | return ret_val; | ||
7720 | mdelay(50); | ||
7721 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); | ||
7722 | if (ret_val) | ||
7723 | return ret_val; | ||
7724 | mdelay(50); | ||
7725 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); | ||
7726 | if (ret_val) | ||
7727 | return ret_val; | ||
7728 | |||
7729 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); | ||
7730 | if (ret_val) | ||
7731 | return ret_val; | ||
7732 | |||
7733 | /* This loop will early-out if the link condition has been met. */ | ||
7734 | for (i = PHY_FORCE_TIME; i > 0; i--) { | ||
7735 | /* Read the MII Status Register and wait for Link Status bit | ||
7736 | * to be set. | ||
7737 | */ | ||
7738 | |||
7739 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | ||
7740 | if (ret_val) | ||
7741 | return ret_val; | ||
7742 | |||
7743 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | ||
7744 | if (ret_val) | ||
7745 | return ret_val; | ||
7746 | |||
7747 | if (mii_status_reg & MII_SR_LINK_STATUS) break; | ||
7748 | mdelay(100); | ||
7749 | } | ||
7750 | return E1000_SUCCESS; | ||
7751 | } | 5518 | } |
7752 | 5519 | ||
7753 | /*************************************************************************** | 5520 | static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw) |
7754 | * | ||
7755 | * Disables PCI-Express master access. | ||
7756 | * | ||
7757 | * hw: Struct containing variables accessed by shared code | ||
7758 | * | ||
7759 | * returns: - none. | ||
7760 | * | ||
7761 | ***************************************************************************/ | ||
7762 | static void e1000_set_pci_express_master_disable(struct e1000_hw *hw) | ||
7763 | { | 5521 | { |
7764 | u32 ctrl; | 5522 | s32 ret_val; |
5523 | u16 mii_status_reg; | ||
5524 | u16 i; | ||
7765 | 5525 | ||
7766 | DEBUGFUNC("e1000_set_pci_express_master_disable"); | 5526 | /* Polarity reversal workaround for forced 10F/10H links. */ |
7767 | 5527 | ||
7768 | if (hw->bus_type != e1000_bus_type_pci_express) | 5528 | /* Disable the transmitter on the PHY */ |
7769 | return; | ||
7770 | 5529 | ||
7771 | ctrl = er32(CTRL); | 5530 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); |
7772 | ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; | 5531 | if (ret_val) |
7773 | ew32(CTRL, ctrl); | 5532 | return ret_val; |
7774 | } | 5533 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); |
5534 | if (ret_val) | ||
5535 | return ret_val; | ||
7775 | 5536 | ||
7776 | /******************************************************************************* | 5537 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); |
7777 | * | 5538 | if (ret_val) |
7778 | * Disables PCI-Express master access and verifies there are no pending requests | 5539 | return ret_val; |
7779 | * | ||
7780 | * hw: Struct containing variables accessed by shared code | ||
7781 | * | ||
7782 | * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't | ||
7783 | * caused the master requests to be disabled. | ||
7784 | * E1000_SUCCESS master requests disabled. | ||
7785 | * | ||
7786 | ******************************************************************************/ | ||
7787 | s32 e1000_disable_pciex_master(struct e1000_hw *hw) | ||
7788 | { | ||
7789 | s32 timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ | ||
7790 | 5540 | ||
7791 | DEBUGFUNC("e1000_disable_pciex_master"); | 5541 | /* This loop will early-out if the NO link condition has been met. */ |
5542 | for (i = PHY_FORCE_TIME; i > 0; i--) { | ||
5543 | /* Read the MII Status Register and wait for Link Status bit | ||
5544 | * to be clear. | ||
5545 | */ | ||
7792 | 5546 | ||
7793 | if (hw->bus_type != e1000_bus_type_pci_express) | 5547 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
7794 | return E1000_SUCCESS; | 5548 | if (ret_val) |
5549 | return ret_val; | ||
7795 | 5550 | ||
7796 | e1000_set_pci_express_master_disable(hw); | 5551 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
5552 | if (ret_val) | ||
5553 | return ret_val; | ||
7797 | 5554 | ||
7798 | while (timeout) { | 5555 | if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) |
7799 | if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) | 5556 | break; |
7800 | break; | 5557 | mdelay(100); |
7801 | else | 5558 | } |
7802 | udelay(100); | ||
7803 | timeout--; | ||
7804 | } | ||
7805 | |||
7806 | if (!timeout) { | ||
7807 | DEBUGOUT("Master requests are pending.\n"); | ||
7808 | return -E1000_ERR_MASTER_REQUESTS_PENDING; | ||
7809 | } | ||
7810 | 5559 | ||
7811 | return E1000_SUCCESS; | 5560 | /* Recommended delay time after link has been lost */ |
5561 | mdelay(1000); | ||
5562 | |||
5563 | /* Now we will re-enable th transmitter on the PHY */ | ||
5564 | |||
5565 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); | ||
5566 | if (ret_val) | ||
5567 | return ret_val; | ||
5568 | mdelay(50); | ||
5569 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); | ||
5570 | if (ret_val) | ||
5571 | return ret_val; | ||
5572 | mdelay(50); | ||
5573 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); | ||
5574 | if (ret_val) | ||
5575 | return ret_val; | ||
5576 | mdelay(50); | ||
5577 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); | ||
5578 | if (ret_val) | ||
5579 | return ret_val; | ||
5580 | |||
5581 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); | ||
5582 | if (ret_val) | ||
5583 | return ret_val; | ||
5584 | |||
5585 | /* This loop will early-out if the link condition has been met. */ | ||
5586 | for (i = PHY_FORCE_TIME; i > 0; i--) { | ||
5587 | /* Read the MII Status Register and wait for Link Status bit | ||
5588 | * to be set. | ||
5589 | */ | ||
5590 | |||
5591 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | ||
5592 | if (ret_val) | ||
5593 | return ret_val; | ||
5594 | |||
5595 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | ||
5596 | if (ret_val) | ||
5597 | return ret_val; | ||
5598 | |||
5599 | if (mii_status_reg & MII_SR_LINK_STATUS) | ||
5600 | break; | ||
5601 | mdelay(100); | ||
5602 | } | ||
5603 | return E1000_SUCCESS; | ||
7812 | } | 5604 | } |
7813 | 5605 | ||
7814 | /******************************************************************************* | 5606 | /** |
5607 | * e1000_get_auto_rd_done | ||
5608 | * @hw: Struct containing variables accessed by shared code | ||
7815 | * | 5609 | * |
7816 | * Check for EEPROM Auto Read bit done. | 5610 | * Check for EEPROM Auto Read bit done. |
7817 | * | ||
7818 | * hw: Struct containing variables accessed by shared code | ||
7819 | * | ||
7820 | * returns: - E1000_ERR_RESET if fail to reset MAC | 5611 | * returns: - E1000_ERR_RESET if fail to reset MAC |
7821 | * E1000_SUCCESS at any other case. | 5612 | * E1000_SUCCESS at any other case. |
7822 | * | 5613 | */ |
7823 | ******************************************************************************/ | ||
7824 | static s32 e1000_get_auto_rd_done(struct e1000_hw *hw) | 5614 | static s32 e1000_get_auto_rd_done(struct e1000_hw *hw) |
7825 | { | 5615 | { |
7826 | s32 timeout = AUTO_READ_DONE_TIMEOUT; | 5616 | DEBUGFUNC("e1000_get_auto_rd_done"); |
7827 | 5617 | msleep(5); | |
7828 | DEBUGFUNC("e1000_get_auto_rd_done"); | 5618 | return E1000_SUCCESS; |
7829 | |||
7830 | switch (hw->mac_type) { | ||
7831 | default: | ||
7832 | msleep(5); | ||
7833 | break; | ||
7834 | case e1000_82571: | ||
7835 | case e1000_82572: | ||
7836 | case e1000_82573: | ||
7837 | case e1000_80003es2lan: | ||
7838 | case e1000_ich8lan: | ||
7839 | while (timeout) { | ||
7840 | if (er32(EECD) & E1000_EECD_AUTO_RD) | ||
7841 | break; | ||
7842 | else msleep(1); | ||
7843 | timeout--; | ||
7844 | } | ||
7845 | |||
7846 | if (!timeout) { | ||
7847 | DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); | ||
7848 | return -E1000_ERR_RESET; | ||
7849 | } | ||
7850 | break; | ||
7851 | } | ||
7852 | |||
7853 | /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high. | ||
7854 | * Need to wait for PHY configuration completion before accessing NVM | ||
7855 | * and PHY. */ | ||
7856 | if (hw->mac_type == e1000_82573) | ||
7857 | msleep(25); | ||
7858 | |||
7859 | return E1000_SUCCESS; | ||
7860 | } | 5619 | } |
7861 | 5620 | ||
7862 | /*************************************************************************** | 5621 | /** |
7863 | * Checks if the PHY configuration is done | 5622 | * e1000_get_phy_cfg_done |
7864 | * | 5623 | * @hw: Struct containing variables accessed by shared code |
7865 | * hw: Struct containing variables accessed by shared code | ||
7866 | * | 5624 | * |
5625 | * Checks if the PHY configuration is done | ||
7867 | * returns: - E1000_ERR_RESET if fail to reset MAC | 5626 | * returns: - E1000_ERR_RESET if fail to reset MAC |
7868 | * E1000_SUCCESS at any other case. | 5627 | * E1000_SUCCESS at any other case. |
7869 | * | 5628 | */ |
7870 | ***************************************************************************/ | ||
7871 | static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) | 5629 | static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) |
7872 | { | 5630 | { |
7873 | s32 timeout = PHY_CFG_TIMEOUT; | 5631 | DEBUGFUNC("e1000_get_phy_cfg_done"); |
7874 | u32 cfg_mask = E1000_EEPROM_CFG_DONE; | 5632 | mdelay(10); |
7875 | 5633 | return E1000_SUCCESS; | |
7876 | DEBUGFUNC("e1000_get_phy_cfg_done"); | ||
7877 | |||
7878 | switch (hw->mac_type) { | ||
7879 | default: | ||
7880 | mdelay(10); | ||
7881 | break; | ||
7882 | case e1000_80003es2lan: | ||
7883 | /* Separate *_CFG_DONE_* bit for each port */ | ||
7884 | if (er32(STATUS) & E1000_STATUS_FUNC_1) | ||
7885 | cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; | ||
7886 | /* Fall Through */ | ||
7887 | case e1000_82571: | ||
7888 | case e1000_82572: | ||
7889 | while (timeout) { | ||
7890 | if (er32(EEMNGCTL) & cfg_mask) | ||
7891 | break; | ||
7892 | else | ||
7893 | msleep(1); | ||
7894 | timeout--; | ||
7895 | } | ||
7896 | if (!timeout) { | ||
7897 | DEBUGOUT("MNG configuration cycle has not completed.\n"); | ||
7898 | return -E1000_ERR_RESET; | ||
7899 | } | ||
7900 | break; | ||
7901 | } | ||
7902 | |||
7903 | return E1000_SUCCESS; | ||
7904 | } | ||
7905 | |||
7906 | /*************************************************************************** | ||
7907 | * | ||
7908 | * Using the combination of SMBI and SWESMBI semaphore bits when resetting | ||
7909 | * adapter or Eeprom access. | ||
7910 | * | ||
7911 | * hw: Struct containing variables accessed by shared code | ||
7912 | * | ||
7913 | * returns: - E1000_ERR_EEPROM if fail to access EEPROM. | ||
7914 | * E1000_SUCCESS at any other case. | ||
7915 | * | ||
7916 | ***************************************************************************/ | ||
7917 | static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) | ||
7918 | { | ||
7919 | s32 timeout; | ||
7920 | u32 swsm; | ||
7921 | |||
7922 | DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); | ||
7923 | |||
7924 | if (!hw->eeprom_semaphore_present) | ||
7925 | return E1000_SUCCESS; | ||
7926 | |||
7927 | if (hw->mac_type == e1000_80003es2lan) { | ||
7928 | /* Get the SW semaphore. */ | ||
7929 | if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) | ||
7930 | return -E1000_ERR_EEPROM; | ||
7931 | } | ||
7932 | |||
7933 | /* Get the FW semaphore. */ | ||
7934 | timeout = hw->eeprom.word_size + 1; | ||
7935 | while (timeout) { | ||
7936 | swsm = er32(SWSM); | ||
7937 | swsm |= E1000_SWSM_SWESMBI; | ||
7938 | ew32(SWSM, swsm); | ||
7939 | /* if we managed to set the bit we got the semaphore. */ | ||
7940 | swsm = er32(SWSM); | ||
7941 | if (swsm & E1000_SWSM_SWESMBI) | ||
7942 | break; | ||
7943 | |||
7944 | udelay(50); | ||
7945 | timeout--; | ||
7946 | } | ||
7947 | |||
7948 | if (!timeout) { | ||
7949 | /* Release semaphores */ | ||
7950 | e1000_put_hw_eeprom_semaphore(hw); | ||
7951 | DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); | ||
7952 | return -E1000_ERR_EEPROM; | ||
7953 | } | ||
7954 | |||
7955 | return E1000_SUCCESS; | ||
7956 | } | ||
7957 | |||
7958 | /*************************************************************************** | ||
7959 | * This function clears HW semaphore bits. | ||
7960 | * | ||
7961 | * hw: Struct containing variables accessed by shared code | ||
7962 | * | ||
7963 | * returns: - None. | ||
7964 | * | ||
7965 | ***************************************************************************/ | ||
7966 | static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) | ||
7967 | { | ||
7968 | u32 swsm; | ||
7969 | |||
7970 | DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); | ||
7971 | |||
7972 | if (!hw->eeprom_semaphore_present) | ||
7973 | return; | ||
7974 | |||
7975 | swsm = er32(SWSM); | ||
7976 | if (hw->mac_type == e1000_80003es2lan) { | ||
7977 | /* Release both semaphores. */ | ||
7978 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); | ||
7979 | } else | ||
7980 | swsm &= ~(E1000_SWSM_SWESMBI); | ||
7981 | ew32(SWSM, swsm); | ||
7982 | } | ||
7983 | |||
7984 | /*************************************************************************** | ||
7985 | * | ||
7986 | * Obtaining software semaphore bit (SMBI) before resetting PHY. | ||
7987 | * | ||
7988 | * hw: Struct containing variables accessed by shared code | ||
7989 | * | ||
7990 | * returns: - E1000_ERR_RESET if fail to obtain semaphore. | ||
7991 | * E1000_SUCCESS at any other case. | ||
7992 | * | ||
7993 | ***************************************************************************/ | ||
7994 | static s32 e1000_get_software_semaphore(struct e1000_hw *hw) | ||
7995 | { | ||
7996 | s32 timeout = hw->eeprom.word_size + 1; | ||
7997 | u32 swsm; | ||
7998 | |||
7999 | DEBUGFUNC("e1000_get_software_semaphore"); | ||
8000 | |||
8001 | if (hw->mac_type != e1000_80003es2lan) { | ||
8002 | return E1000_SUCCESS; | ||
8003 | } | ||
8004 | |||
8005 | while (timeout) { | ||
8006 | swsm = er32(SWSM); | ||
8007 | /* If SMBI bit cleared, it is now set and we hold the semaphore */ | ||
8008 | if (!(swsm & E1000_SWSM_SMBI)) | ||
8009 | break; | ||
8010 | mdelay(1); | ||
8011 | timeout--; | ||
8012 | } | ||
8013 | |||
8014 | if (!timeout) { | ||
8015 | DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); | ||
8016 | return -E1000_ERR_RESET; | ||
8017 | } | ||
8018 | |||
8019 | return E1000_SUCCESS; | ||
8020 | } | ||
8021 | |||
8022 | /*************************************************************************** | ||
8023 | * | ||
8024 | * Release semaphore bit (SMBI). | ||
8025 | * | ||
8026 | * hw: Struct containing variables accessed by shared code | ||
8027 | * | ||
8028 | ***************************************************************************/ | ||
8029 | static void e1000_release_software_semaphore(struct e1000_hw *hw) | ||
8030 | { | ||
8031 | u32 swsm; | ||
8032 | |||
8033 | DEBUGFUNC("e1000_release_software_semaphore"); | ||
8034 | |||
8035 | if (hw->mac_type != e1000_80003es2lan) { | ||
8036 | return; | ||
8037 | } | ||
8038 | |||
8039 | swsm = er32(SWSM); | ||
8040 | /* Release the SW semaphores.*/ | ||
8041 | swsm &= ~E1000_SWSM_SMBI; | ||
8042 | ew32(SWSM, swsm); | ||
8043 | } | ||
8044 | |||
8045 | /****************************************************************************** | ||
8046 | * Checks if PHY reset is blocked due to SOL/IDER session, for example. | ||
8047 | * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to | ||
8048 | * the caller to figure out how to deal with it. | ||
8049 | * | ||
8050 | * hw - Struct containing variables accessed by shared code | ||
8051 | * | ||
8052 | * returns: - E1000_BLK_PHY_RESET | ||
8053 | * E1000_SUCCESS | ||
8054 | * | ||
8055 | *****************************************************************************/ | ||
8056 | s32 e1000_check_phy_reset_block(struct e1000_hw *hw) | ||
8057 | { | ||
8058 | u32 manc = 0; | ||
8059 | u32 fwsm = 0; | ||
8060 | |||
8061 | if (hw->mac_type == e1000_ich8lan) { | ||
8062 | fwsm = er32(FWSM); | ||
8063 | return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS | ||
8064 | : E1000_BLK_PHY_RESET; | ||
8065 | } | ||
8066 | |||
8067 | if (hw->mac_type > e1000_82547_rev_2) | ||
8068 | manc = er32(MANC); | ||
8069 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? | ||
8070 | E1000_BLK_PHY_RESET : E1000_SUCCESS; | ||
8071 | } | ||
8072 | |||
8073 | static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw) | ||
8074 | { | ||
8075 | u32 fwsm; | ||
8076 | |||
8077 | /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC | ||
8078 | * may not be provided a DMA clock when no manageability features are | ||
8079 | * enabled. We do not want to perform any reads/writes to these registers | ||
8080 | * if this is the case. We read FWSM to determine the manageability mode. | ||
8081 | */ | ||
8082 | switch (hw->mac_type) { | ||
8083 | case e1000_82571: | ||
8084 | case e1000_82572: | ||
8085 | case e1000_82573: | ||
8086 | case e1000_80003es2lan: | ||
8087 | fwsm = er32(FWSM); | ||
8088 | if ((fwsm & E1000_FWSM_MODE_MASK) != 0) | ||
8089 | return true; | ||
8090 | break; | ||
8091 | case e1000_ich8lan: | ||
8092 | return true; | ||
8093 | default: | ||
8094 | break; | ||
8095 | } | ||
8096 | return false; | ||
8097 | } | ||
8098 | |||
8099 | |||
8100 | /****************************************************************************** | ||
8101 | * Configure PCI-Ex no-snoop | ||
8102 | * | ||
8103 | * hw - Struct containing variables accessed by shared code. | ||
8104 | * no_snoop - Bitmap of no-snoop events. | ||
8105 | * | ||
8106 | * returns: E1000_SUCCESS | ||
8107 | * | ||
8108 | *****************************************************************************/ | ||
8109 | static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop) | ||
8110 | { | ||
8111 | u32 gcr_reg = 0; | ||
8112 | |||
8113 | DEBUGFUNC("e1000_set_pci_ex_no_snoop"); | ||
8114 | |||
8115 | if (hw->bus_type == e1000_bus_type_unknown) | ||
8116 | e1000_get_bus_info(hw); | ||
8117 | |||
8118 | if (hw->bus_type != e1000_bus_type_pci_express) | ||
8119 | return E1000_SUCCESS; | ||
8120 | |||
8121 | if (no_snoop) { | ||
8122 | gcr_reg = er32(GCR); | ||
8123 | gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); | ||
8124 | gcr_reg |= no_snoop; | ||
8125 | ew32(GCR, gcr_reg); | ||
8126 | } | ||
8127 | if (hw->mac_type == e1000_ich8lan) { | ||
8128 | u32 ctrl_ext; | ||
8129 | |||
8130 | ew32(GCR, PCI_EX_82566_SNOOP_ALL); | ||
8131 | |||
8132 | ctrl_ext = er32(CTRL_EXT); | ||
8133 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; | ||
8134 | ew32(CTRL_EXT, ctrl_ext); | ||
8135 | } | ||
8136 | |||
8137 | return E1000_SUCCESS; | ||
8138 | } | ||
8139 | |||
8140 | /*************************************************************************** | ||
8141 | * | ||
8142 | * Get software semaphore FLAG bit (SWFLAG). | ||
8143 | * SWFLAG is used to synchronize the access to all shared resource between | ||
8144 | * SW, FW and HW. | ||
8145 | * | ||
8146 | * hw: Struct containing variables accessed by shared code | ||
8147 | * | ||
8148 | ***************************************************************************/ | ||
8149 | static s32 e1000_get_software_flag(struct e1000_hw *hw) | ||
8150 | { | ||
8151 | s32 timeout = PHY_CFG_TIMEOUT; | ||
8152 | u32 extcnf_ctrl; | ||
8153 | |||
8154 | DEBUGFUNC("e1000_get_software_flag"); | ||
8155 | |||
8156 | if (hw->mac_type == e1000_ich8lan) { | ||
8157 | while (timeout) { | ||
8158 | extcnf_ctrl = er32(EXTCNF_CTRL); | ||
8159 | extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; | ||
8160 | ew32(EXTCNF_CTRL, extcnf_ctrl); | ||
8161 | |||
8162 | extcnf_ctrl = er32(EXTCNF_CTRL); | ||
8163 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) | ||
8164 | break; | ||
8165 | mdelay(1); | ||
8166 | timeout--; | ||
8167 | } | ||
8168 | |||
8169 | if (!timeout) { | ||
8170 | DEBUGOUT("FW or HW locks the resource too long.\n"); | ||
8171 | return -E1000_ERR_CONFIG; | ||
8172 | } | ||
8173 | } | ||
8174 | |||
8175 | return E1000_SUCCESS; | ||
8176 | } | ||
8177 | |||
8178 | /*************************************************************************** | ||
8179 | * | ||
8180 | * Release software semaphore FLAG bit (SWFLAG). | ||
8181 | * SWFLAG is used to synchronize the access to all shared resource between | ||
8182 | * SW, FW and HW. | ||
8183 | * | ||
8184 | * hw: Struct containing variables accessed by shared code | ||
8185 | * | ||
8186 | ***************************************************************************/ | ||
8187 | static void e1000_release_software_flag(struct e1000_hw *hw) | ||
8188 | { | ||
8189 | u32 extcnf_ctrl; | ||
8190 | |||
8191 | DEBUGFUNC("e1000_release_software_flag"); | ||
8192 | |||
8193 | if (hw->mac_type == e1000_ich8lan) { | ||
8194 | extcnf_ctrl= er32(EXTCNF_CTRL); | ||
8195 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; | ||
8196 | ew32(EXTCNF_CTRL, extcnf_ctrl); | ||
8197 | } | ||
8198 | |||
8199 | return; | ||
8200 | } | ||
8201 | |||
8202 | /****************************************************************************** | ||
8203 | * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access | ||
8204 | * register. | ||
8205 | * | ||
8206 | * hw - Struct containing variables accessed by shared code | ||
8207 | * offset - offset of word in the EEPROM to read | ||
8208 | * data - word read from the EEPROM | ||
8209 | * words - number of words to read | ||
8210 | *****************************************************************************/ | ||
8211 | static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, | ||
8212 | u16 *data) | ||
8213 | { | ||
8214 | s32 error = E1000_SUCCESS; | ||
8215 | u32 flash_bank = 0; | ||
8216 | u32 act_offset = 0; | ||
8217 | u32 bank_offset = 0; | ||
8218 | u16 word = 0; | ||
8219 | u16 i = 0; | ||
8220 | |||
8221 | /* We need to know which is the valid flash bank. In the event | ||
8222 | * that we didn't allocate eeprom_shadow_ram, we may not be | ||
8223 | * managing flash_bank. So it cannot be trusted and needs | ||
8224 | * to be updated with each read. | ||
8225 | */ | ||
8226 | /* Value of bit 22 corresponds to the flash bank we're on. */ | ||
8227 | flash_bank = (er32(EECD) & E1000_EECD_SEC1VAL) ? 1 : 0; | ||
8228 | |||
8229 | /* Adjust offset appropriately if we're on bank 1 - adjust for word size */ | ||
8230 | bank_offset = flash_bank * (hw->flash_bank_size * 2); | ||
8231 | |||
8232 | error = e1000_get_software_flag(hw); | ||
8233 | if (error != E1000_SUCCESS) | ||
8234 | return error; | ||
8235 | |||
8236 | for (i = 0; i < words; i++) { | ||
8237 | if (hw->eeprom_shadow_ram != NULL && | ||
8238 | hw->eeprom_shadow_ram[offset+i].modified) { | ||
8239 | data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; | ||
8240 | } else { | ||
8241 | /* The NVM part needs a byte offset, hence * 2 */ | ||
8242 | act_offset = bank_offset + ((offset + i) * 2); | ||
8243 | error = e1000_read_ich8_word(hw, act_offset, &word); | ||
8244 | if (error != E1000_SUCCESS) | ||
8245 | break; | ||
8246 | data[i] = word; | ||
8247 | } | ||
8248 | } | ||
8249 | |||
8250 | e1000_release_software_flag(hw); | ||
8251 | |||
8252 | return error; | ||
8253 | } | ||
8254 | |||
8255 | /****************************************************************************** | ||
8256 | * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access | ||
8257 | * register. Actually, writes are written to the shadow ram cache in the hw | ||
8258 | * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to | ||
8259 | * the NVM, which occurs when the NVM checksum is updated. | ||
8260 | * | ||
8261 | * hw - Struct containing variables accessed by shared code | ||
8262 | * offset - offset of word in the EEPROM to write | ||
8263 | * words - number of words to write | ||
8264 | * data - words to write to the EEPROM | ||
8265 | *****************************************************************************/ | ||
8266 | static s32 e1000_write_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words, | ||
8267 | u16 *data) | ||
8268 | { | ||
8269 | u32 i = 0; | ||
8270 | s32 error = E1000_SUCCESS; | ||
8271 | |||
8272 | error = e1000_get_software_flag(hw); | ||
8273 | if (error != E1000_SUCCESS) | ||
8274 | return error; | ||
8275 | |||
8276 | /* A driver can write to the NVM only if it has eeprom_shadow_ram | ||
8277 | * allocated. Subsequent reads to the modified words are read from | ||
8278 | * this cached structure as well. Writes will only go into this | ||
8279 | * cached structure unless it's followed by a call to | ||
8280 | * e1000_update_eeprom_checksum() where it will commit the changes | ||
8281 | * and clear the "modified" field. | ||
8282 | */ | ||
8283 | if (hw->eeprom_shadow_ram != NULL) { | ||
8284 | for (i = 0; i < words; i++) { | ||
8285 | if ((offset + i) < E1000_SHADOW_RAM_WORDS) { | ||
8286 | hw->eeprom_shadow_ram[offset+i].modified = true; | ||
8287 | hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i]; | ||
8288 | } else { | ||
8289 | error = -E1000_ERR_EEPROM; | ||
8290 | break; | ||
8291 | } | ||
8292 | } | ||
8293 | } else { | ||
8294 | /* Drivers have the option to not allocate eeprom_shadow_ram as long | ||
8295 | * as they don't perform any NVM writes. An attempt in doing so | ||
8296 | * will result in this error. | ||
8297 | */ | ||
8298 | error = -E1000_ERR_EEPROM; | ||
8299 | } | ||
8300 | |||
8301 | e1000_release_software_flag(hw); | ||
8302 | |||
8303 | return error; | ||
8304 | } | ||
8305 | |||
8306 | /****************************************************************************** | ||
8307 | * This function does initial flash setup so that a new read/write/erase cycle | ||
8308 | * can be started. | ||
8309 | * | ||
8310 | * hw - The pointer to the hw structure | ||
8311 | ****************************************************************************/ | ||
8312 | static s32 e1000_ich8_cycle_init(struct e1000_hw *hw) | ||
8313 | { | ||
8314 | union ich8_hws_flash_status hsfsts; | ||
8315 | s32 error = E1000_ERR_EEPROM; | ||
8316 | s32 i = 0; | ||
8317 | |||
8318 | DEBUGFUNC("e1000_ich8_cycle_init"); | ||
8319 | |||
8320 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); | ||
8321 | |||
8322 | /* May be check the Flash Des Valid bit in Hw status */ | ||
8323 | if (hsfsts.hsf_status.fldesvalid == 0) { | ||
8324 | DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used."); | ||
8325 | return error; | ||
8326 | } | ||
8327 | |||
8328 | /* Clear FCERR in Hw status by writing 1 */ | ||
8329 | /* Clear DAEL in Hw status by writing a 1 */ | ||
8330 | hsfsts.hsf_status.flcerr = 1; | ||
8331 | hsfsts.hsf_status.dael = 1; | ||
8332 | |||
8333 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); | ||
8334 | |||
8335 | /* Either we should have a hardware SPI cycle in progress bit to check | ||
8336 | * against, in order to start a new cycle or FDONE bit should be changed | ||
8337 | * in the hardware so that it is 1 after harware reset, which can then be | ||
8338 | * used as an indication whether a cycle is in progress or has been | ||
8339 | * completed .. we should also have some software semaphore mechanism to | ||
8340 | * guard FDONE or the cycle in progress bit so that two threads access to | ||
8341 | * those bits can be sequentiallized or a way so that 2 threads dont | ||
8342 | * start the cycle at the same time */ | ||
8343 | |||
8344 | if (hsfsts.hsf_status.flcinprog == 0) { | ||
8345 | /* There is no cycle running at present, so we can start a cycle */ | ||
8346 | /* Begin by setting Flash Cycle Done. */ | ||
8347 | hsfsts.hsf_status.flcdone = 1; | ||
8348 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); | ||
8349 | error = E1000_SUCCESS; | ||
8350 | } else { | ||
8351 | /* otherwise poll for sometime so the current cycle has a chance | ||
8352 | * to end before giving up. */ | ||
8353 | for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { | ||
8354 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); | ||
8355 | if (hsfsts.hsf_status.flcinprog == 0) { | ||
8356 | error = E1000_SUCCESS; | ||
8357 | break; | ||
8358 | } | ||
8359 | udelay(1); | ||
8360 | } | ||
8361 | if (error == E1000_SUCCESS) { | ||
8362 | /* Successful in waiting for previous cycle to timeout, | ||
8363 | * now set the Flash Cycle Done. */ | ||
8364 | hsfsts.hsf_status.flcdone = 1; | ||
8365 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); | ||
8366 | } else { | ||
8367 | DEBUGOUT("Flash controller busy, cannot get access"); | ||
8368 | } | ||
8369 | } | ||
8370 | return error; | ||
8371 | } | ||
8372 | |||
8373 | /****************************************************************************** | ||
8374 | * This function starts a flash cycle and waits for its completion | ||
8375 | * | ||
8376 | * hw - The pointer to the hw structure | ||
8377 | ****************************************************************************/ | ||
8378 | static s32 e1000_ich8_flash_cycle(struct e1000_hw *hw, u32 timeout) | ||
8379 | { | ||
8380 | union ich8_hws_flash_ctrl hsflctl; | ||
8381 | union ich8_hws_flash_status hsfsts; | ||
8382 | s32 error = E1000_ERR_EEPROM; | ||
8383 | u32 i = 0; | ||
8384 | |||
8385 | /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ | ||
8386 | hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); | ||
8387 | hsflctl.hsf_ctrl.flcgo = 1; | ||
8388 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); | ||
8389 | |||
8390 | /* wait till FDONE bit is set to 1 */ | ||
8391 | do { | ||
8392 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); | ||
8393 | if (hsfsts.hsf_status.flcdone == 1) | ||
8394 | break; | ||
8395 | udelay(1); | ||
8396 | i++; | ||
8397 | } while (i < timeout); | ||
8398 | if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { | ||
8399 | error = E1000_SUCCESS; | ||
8400 | } | ||
8401 | return error; | ||
8402 | } | ||
8403 | |||
8404 | /****************************************************************************** | ||
8405 | * Reads a byte or word from the NVM using the ICH8 flash access registers. | ||
8406 | * | ||
8407 | * hw - The pointer to the hw structure | ||
8408 | * index - The index of the byte or word to read. | ||
8409 | * size - Size of data to read, 1=byte 2=word | ||
8410 | * data - Pointer to the word to store the value read. | ||
8411 | *****************************************************************************/ | ||
8412 | static s32 e1000_read_ich8_data(struct e1000_hw *hw, u32 index, u32 size, | ||
8413 | u16 *data) | ||
8414 | { | ||
8415 | union ich8_hws_flash_status hsfsts; | ||
8416 | union ich8_hws_flash_ctrl hsflctl; | ||
8417 | u32 flash_linear_address; | ||
8418 | u32 flash_data = 0; | ||
8419 | s32 error = -E1000_ERR_EEPROM; | ||
8420 | s32 count = 0; | ||
8421 | |||
8422 | DEBUGFUNC("e1000_read_ich8_data"); | ||
8423 | |||
8424 | if (size < 1 || size > 2 || data == NULL || | ||
8425 | index > ICH_FLASH_LINEAR_ADDR_MASK) | ||
8426 | return error; | ||
8427 | |||
8428 | flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + | ||
8429 | hw->flash_base_addr; | ||
8430 | |||
8431 | do { | ||
8432 | udelay(1); | ||
8433 | /* Steps */ | ||
8434 | error = e1000_ich8_cycle_init(hw); | ||
8435 | if (error != E1000_SUCCESS) | ||
8436 | break; | ||
8437 | |||
8438 | hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); | ||
8439 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ | ||
8440 | hsflctl.hsf_ctrl.fldbcount = size - 1; | ||
8441 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; | ||
8442 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); | ||
8443 | |||
8444 | /* Write the last 24 bits of index into Flash Linear address field in | ||
8445 | * Flash Address */ | ||
8446 | /* TODO: TBD maybe check the index against the size of flash */ | ||
8447 | |||
8448 | E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); | ||
8449 | |||
8450 | error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); | ||
8451 | |||
8452 | /* Check if FCERR is set to 1, if set to 1, clear it and try the whole | ||
8453 | * sequence a few more times, else read in (shift in) the Flash Data0, | ||
8454 | * the order is least significant byte first msb to lsb */ | ||
8455 | if (error == E1000_SUCCESS) { | ||
8456 | flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0); | ||
8457 | if (size == 1) { | ||
8458 | *data = (u8)(flash_data & 0x000000FF); | ||
8459 | } else if (size == 2) { | ||
8460 | *data = (u16)(flash_data & 0x0000FFFF); | ||
8461 | } | ||
8462 | break; | ||
8463 | } else { | ||
8464 | /* If we've gotten here, then things are probably completely hosed, | ||
8465 | * but if the error condition is detected, it won't hurt to give | ||
8466 | * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. | ||
8467 | */ | ||
8468 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); | ||
8469 | if (hsfsts.hsf_status.flcerr == 1) { | ||
8470 | /* Repeat for some time before giving up. */ | ||
8471 | continue; | ||
8472 | } else if (hsfsts.hsf_status.flcdone == 0) { | ||
8473 | DEBUGOUT("Timeout error - flash cycle did not complete."); | ||
8474 | break; | ||
8475 | } | ||
8476 | } | ||
8477 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); | ||
8478 | |||
8479 | return error; | ||
8480 | } | ||
8481 | |||
8482 | /****************************************************************************** | ||
8483 | * Writes One /two bytes to the NVM using the ICH8 flash access registers. | ||
8484 | * | ||
8485 | * hw - The pointer to the hw structure | ||
8486 | * index - The index of the byte/word to read. | ||
8487 | * size - Size of data to read, 1=byte 2=word | ||
8488 | * data - The byte(s) to write to the NVM. | ||
8489 | *****************************************************************************/ | ||
8490 | static s32 e1000_write_ich8_data(struct e1000_hw *hw, u32 index, u32 size, | ||
8491 | u16 data) | ||
8492 | { | ||
8493 | union ich8_hws_flash_status hsfsts; | ||
8494 | union ich8_hws_flash_ctrl hsflctl; | ||
8495 | u32 flash_linear_address; | ||
8496 | u32 flash_data = 0; | ||
8497 | s32 error = -E1000_ERR_EEPROM; | ||
8498 | s32 count = 0; | ||
8499 | |||
8500 | DEBUGFUNC("e1000_write_ich8_data"); | ||
8501 | |||
8502 | if (size < 1 || size > 2 || data > size * 0xff || | ||
8503 | index > ICH_FLASH_LINEAR_ADDR_MASK) | ||
8504 | return error; | ||
8505 | |||
8506 | flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + | ||
8507 | hw->flash_base_addr; | ||
8508 | |||
8509 | do { | ||
8510 | udelay(1); | ||
8511 | /* Steps */ | ||
8512 | error = e1000_ich8_cycle_init(hw); | ||
8513 | if (error != E1000_SUCCESS) | ||
8514 | break; | ||
8515 | |||
8516 | hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); | ||
8517 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ | ||
8518 | hsflctl.hsf_ctrl.fldbcount = size -1; | ||
8519 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; | ||
8520 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); | ||
8521 | |||
8522 | /* Write the last 24 bits of index into Flash Linear address field in | ||
8523 | * Flash Address */ | ||
8524 | E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); | ||
8525 | |||
8526 | if (size == 1) | ||
8527 | flash_data = (u32)data & 0x00FF; | ||
8528 | else | ||
8529 | flash_data = (u32)data; | ||
8530 | |||
8531 | E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); | ||
8532 | |||
8533 | /* check if FCERR is set to 1 , if set to 1, clear it and try the whole | ||
8534 | * sequence a few more times else done */ | ||
8535 | error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); | ||
8536 | if (error == E1000_SUCCESS) { | ||
8537 | break; | ||
8538 | } else { | ||
8539 | /* If we're here, then things are most likely completely hosed, | ||
8540 | * but if the error condition is detected, it won't hurt to give | ||
8541 | * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. | ||
8542 | */ | ||
8543 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); | ||
8544 | if (hsfsts.hsf_status.flcerr == 1) { | ||
8545 | /* Repeat for some time before giving up. */ | ||
8546 | continue; | ||
8547 | } else if (hsfsts.hsf_status.flcdone == 0) { | ||
8548 | DEBUGOUT("Timeout error - flash cycle did not complete."); | ||
8549 | break; | ||
8550 | } | ||
8551 | } | ||
8552 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); | ||
8553 | |||
8554 | return error; | ||
8555 | } | ||
8556 | |||
8557 | /****************************************************************************** | ||
8558 | * Reads a single byte from the NVM using the ICH8 flash access registers. | ||
8559 | * | ||
8560 | * hw - pointer to e1000_hw structure | ||
8561 | * index - The index of the byte to read. | ||
8562 | * data - Pointer to a byte to store the value read. | ||
8563 | *****************************************************************************/ | ||
8564 | static s32 e1000_read_ich8_byte(struct e1000_hw *hw, u32 index, u8 *data) | ||
8565 | { | ||
8566 | s32 status = E1000_SUCCESS; | ||
8567 | u16 word = 0; | ||
8568 | |||
8569 | status = e1000_read_ich8_data(hw, index, 1, &word); | ||
8570 | if (status == E1000_SUCCESS) { | ||
8571 | *data = (u8)word; | ||
8572 | } | ||
8573 | |||
8574 | return status; | ||
8575 | } | ||
8576 | |||
8577 | /****************************************************************************** | ||
8578 | * Writes a single byte to the NVM using the ICH8 flash access registers. | ||
8579 | * Performs verification by reading back the value and then going through | ||
8580 | * a retry algorithm before giving up. | ||
8581 | * | ||
8582 | * hw - pointer to e1000_hw structure | ||
8583 | * index - The index of the byte to write. | ||
8584 | * byte - The byte to write to the NVM. | ||
8585 | *****************************************************************************/ | ||
8586 | static s32 e1000_verify_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 byte) | ||
8587 | { | ||
8588 | s32 error = E1000_SUCCESS; | ||
8589 | s32 program_retries = 0; | ||
8590 | |||
8591 | DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); | ||
8592 | |||
8593 | error = e1000_write_ich8_byte(hw, index, byte); | ||
8594 | |||
8595 | if (error != E1000_SUCCESS) { | ||
8596 | for (program_retries = 0; program_retries < 100; program_retries++) { | ||
8597 | DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index); | ||
8598 | error = e1000_write_ich8_byte(hw, index, byte); | ||
8599 | udelay(100); | ||
8600 | if (error == E1000_SUCCESS) | ||
8601 | break; | ||
8602 | } | ||
8603 | } | ||
8604 | |||
8605 | if (program_retries == 100) | ||
8606 | error = E1000_ERR_EEPROM; | ||
8607 | |||
8608 | return error; | ||
8609 | } | ||
8610 | |||
8611 | /****************************************************************************** | ||
8612 | * Writes a single byte to the NVM using the ICH8 flash access registers. | ||
8613 | * | ||
8614 | * hw - pointer to e1000_hw structure | ||
8615 | * index - The index of the byte to read. | ||
8616 | * data - The byte to write to the NVM. | ||
8617 | *****************************************************************************/ | ||
8618 | static s32 e1000_write_ich8_byte(struct e1000_hw *hw, u32 index, u8 data) | ||
8619 | { | ||
8620 | s32 status = E1000_SUCCESS; | ||
8621 | u16 word = (u16)data; | ||
8622 | |||
8623 | status = e1000_write_ich8_data(hw, index, 1, word); | ||
8624 | |||
8625 | return status; | ||
8626 | } | ||
8627 | |||
8628 | /****************************************************************************** | ||
8629 | * Reads a word from the NVM using the ICH8 flash access registers. | ||
8630 | * | ||
8631 | * hw - pointer to e1000_hw structure | ||
8632 | * index - The starting byte index of the word to read. | ||
8633 | * data - Pointer to a word to store the value read. | ||
8634 | *****************************************************************************/ | ||
8635 | static s32 e1000_read_ich8_word(struct e1000_hw *hw, u32 index, u16 *data) | ||
8636 | { | ||
8637 | s32 status = E1000_SUCCESS; | ||
8638 | status = e1000_read_ich8_data(hw, index, 2, data); | ||
8639 | return status; | ||
8640 | } | ||
8641 | |||
8642 | /****************************************************************************** | ||
8643 | * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 | ||
8644 | * based. | ||
8645 | * | ||
8646 | * hw - pointer to e1000_hw structure | ||
8647 | * bank - 0 for first bank, 1 for second bank | ||
8648 | * | ||
8649 | * Note that this function may actually erase as much as 8 or 64 KBytes. The | ||
8650 | * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the | ||
8651 | * bank size may be 4, 8 or 64 KBytes | ||
8652 | *****************************************************************************/ | ||
8653 | static s32 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, u32 bank) | ||
8654 | { | ||
8655 | union ich8_hws_flash_status hsfsts; | ||
8656 | union ich8_hws_flash_ctrl hsflctl; | ||
8657 | u32 flash_linear_address; | ||
8658 | s32 count = 0; | ||
8659 | s32 error = E1000_ERR_EEPROM; | ||
8660 | s32 iteration; | ||
8661 | s32 sub_sector_size = 0; | ||
8662 | s32 bank_size; | ||
8663 | s32 j = 0; | ||
8664 | s32 error_flag = 0; | ||
8665 | |||
8666 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); | ||
8667 | |||
8668 | /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */ | ||
8669 | /* 00: The Hw sector is 256 bytes, hence we need to erase 16 | ||
8670 | * consecutive sectors. The start index for the nth Hw sector can be | ||
8671 | * calculated as bank * 4096 + n * 256 | ||
8672 | * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. | ||
8673 | * The start index for the nth Hw sector can be calculated | ||
8674 | * as bank * 4096 | ||
8675 | * 10: The HW sector is 8K bytes | ||
8676 | * 11: The Hw sector size is 64K bytes */ | ||
8677 | if (hsfsts.hsf_status.berasesz == 0x0) { | ||
8678 | /* Hw sector size 256 */ | ||
8679 | sub_sector_size = ICH_FLASH_SEG_SIZE_256; | ||
8680 | bank_size = ICH_FLASH_SECTOR_SIZE; | ||
8681 | iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; | ||
8682 | } else if (hsfsts.hsf_status.berasesz == 0x1) { | ||
8683 | bank_size = ICH_FLASH_SEG_SIZE_4K; | ||
8684 | iteration = 1; | ||
8685 | } else if (hsfsts.hsf_status.berasesz == 0x3) { | ||
8686 | bank_size = ICH_FLASH_SEG_SIZE_64K; | ||
8687 | iteration = 1; | ||
8688 | } else { | ||
8689 | return error; | ||
8690 | } | ||
8691 | |||
8692 | for (j = 0; j < iteration ; j++) { | ||
8693 | do { | ||
8694 | count++; | ||
8695 | /* Steps */ | ||
8696 | error = e1000_ich8_cycle_init(hw); | ||
8697 | if (error != E1000_SUCCESS) { | ||
8698 | error_flag = 1; | ||
8699 | break; | ||
8700 | } | ||
8701 | |||
8702 | /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash | ||
8703 | * Control */ | ||
8704 | hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); | ||
8705 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; | ||
8706 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); | ||
8707 | |||
8708 | /* Write the last 24 bits of an index within the block into Flash | ||
8709 | * Linear address field in Flash Address. This probably needs to | ||
8710 | * be calculated here based off the on-chip erase sector size and | ||
8711 | * the software bank size (4, 8 or 64 KBytes) */ | ||
8712 | flash_linear_address = bank * bank_size + j * sub_sector_size; | ||
8713 | flash_linear_address += hw->flash_base_addr; | ||
8714 | flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; | ||
8715 | |||
8716 | E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); | ||
8717 | |||
8718 | error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); | ||
8719 | /* Check if FCERR is set to 1. If 1, clear it and try the whole | ||
8720 | * sequence a few more times else Done */ | ||
8721 | if (error == E1000_SUCCESS) { | ||
8722 | break; | ||
8723 | } else { | ||
8724 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); | ||
8725 | if (hsfsts.hsf_status.flcerr == 1) { | ||
8726 | /* repeat for some time before giving up */ | ||
8727 | continue; | ||
8728 | } else if (hsfsts.hsf_status.flcdone == 0) { | ||
8729 | error_flag = 1; | ||
8730 | break; | ||
8731 | } | ||
8732 | } | ||
8733 | } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); | ||
8734 | if (error_flag == 1) | ||
8735 | break; | ||
8736 | } | ||
8737 | if (error_flag != 1) | ||
8738 | error = E1000_SUCCESS; | ||
8739 | return error; | ||
8740 | } | ||
8741 | |||
8742 | static s32 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, | ||
8743 | u32 cnf_base_addr, | ||
8744 | u32 cnf_size) | ||
8745 | { | ||
8746 | u32 ret_val = E1000_SUCCESS; | ||
8747 | u16 word_addr, reg_data, reg_addr; | ||
8748 | u16 i; | ||
8749 | |||
8750 | /* cnf_base_addr is in DWORD */ | ||
8751 | word_addr = (u16)(cnf_base_addr << 1); | ||
8752 | |||
8753 | /* cnf_size is returned in size of dwords */ | ||
8754 | for (i = 0; i < cnf_size; i++) { | ||
8755 | ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, ®_data); | ||
8756 | if (ret_val) | ||
8757 | return ret_val; | ||
8758 | |||
8759 | ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr); | ||
8760 | if (ret_val) | ||
8761 | return ret_val; | ||
8762 | |||
8763 | ret_val = e1000_get_software_flag(hw); | ||
8764 | if (ret_val != E1000_SUCCESS) | ||
8765 | return ret_val; | ||
8766 | |||
8767 | ret_val = e1000_write_phy_reg_ex(hw, (u32)reg_addr, reg_data); | ||
8768 | |||
8769 | e1000_release_software_flag(hw); | ||
8770 | } | ||
8771 | |||
8772 | return ret_val; | ||
8773 | } | ||
8774 | |||
8775 | |||
8776 | /****************************************************************************** | ||
8777 | * This function initializes the PHY from the NVM on ICH8 platforms. This | ||
8778 | * is needed due to an issue where the NVM configuration is not properly | ||
8779 | * autoloaded after power transitions. Therefore, after each PHY reset, we | ||
8780 | * will load the configuration data out of the NVM manually. | ||
8781 | * | ||
8782 | * hw: Struct containing variables accessed by shared code | ||
8783 | *****************************************************************************/ | ||
8784 | static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw) | ||
8785 | { | ||
8786 | u32 reg_data, cnf_base_addr, cnf_size, ret_val, loop; | ||
8787 | |||
8788 | if (hw->phy_type != e1000_phy_igp_3) | ||
8789 | return E1000_SUCCESS; | ||
8790 | |||
8791 | /* Check if SW needs configure the PHY */ | ||
8792 | reg_data = er32(FEXTNVM); | ||
8793 | if (!(reg_data & FEXTNVM_SW_CONFIG)) | ||
8794 | return E1000_SUCCESS; | ||
8795 | |||
8796 | /* Wait for basic configuration completes before proceeding*/ | ||
8797 | loop = 0; | ||
8798 | do { | ||
8799 | reg_data = er32(STATUS) & E1000_STATUS_LAN_INIT_DONE; | ||
8800 | udelay(100); | ||
8801 | loop++; | ||
8802 | } while ((!reg_data) && (loop < 50)); | ||
8803 | |||
8804 | /* Clear the Init Done bit for the next init event */ | ||
8805 | reg_data = er32(STATUS); | ||
8806 | reg_data &= ~E1000_STATUS_LAN_INIT_DONE; | ||
8807 | ew32(STATUS, reg_data); | ||
8808 | |||
8809 | /* Make sure HW does not configure LCD from PHY extended configuration | ||
8810 | before SW configuration */ | ||
8811 | reg_data = er32(EXTCNF_CTRL); | ||
8812 | if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { | ||
8813 | reg_data = er32(EXTCNF_SIZE); | ||
8814 | cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; | ||
8815 | cnf_size >>= 16; | ||
8816 | if (cnf_size) { | ||
8817 | reg_data = er32(EXTCNF_CTRL); | ||
8818 | cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; | ||
8819 | /* cnf_base_addr is in DWORD */ | ||
8820 | cnf_base_addr >>= 16; | ||
8821 | |||
8822 | /* Configure LCD from extended configuration region. */ | ||
8823 | ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr, | ||
8824 | cnf_size); | ||
8825 | if (ret_val) | ||
8826 | return ret_val; | ||
8827 | } | ||
8828 | } | ||
8829 | |||
8830 | return E1000_SUCCESS; | ||
8831 | } | 5634 | } |
8832 | |||
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h index a8866bdbb671..9acfddb0dafb 100644 --- a/drivers/net/e1000/e1000_hw.h +++ b/drivers/net/e1000/e1000_hw.h | |||
@@ -35,7 +35,6 @@ | |||
35 | 35 | ||
36 | #include "e1000_osdep.h" | 36 | #include "e1000_osdep.h" |
37 | 37 | ||
38 | |||
39 | /* Forward declarations of structures used by the shared code */ | 38 | /* Forward declarations of structures used by the shared code */ |
40 | struct e1000_hw; | 39 | struct e1000_hw; |
41 | struct e1000_hw_stats; | 40 | struct e1000_hw_stats; |
@@ -43,252 +42,231 @@ struct e1000_hw_stats; | |||
43 | /* Enumerated types specific to the e1000 hardware */ | 42 | /* Enumerated types specific to the e1000 hardware */ |
44 | /* Media Access Controlers */ | 43 | /* Media Access Controlers */ |
45 | typedef enum { | 44 | typedef enum { |
46 | e1000_undefined = 0, | 45 | e1000_undefined = 0, |
47 | e1000_82542_rev2_0, | 46 | e1000_82542_rev2_0, |
48 | e1000_82542_rev2_1, | 47 | e1000_82542_rev2_1, |
49 | e1000_82543, | 48 | e1000_82543, |
50 | e1000_82544, | 49 | e1000_82544, |
51 | e1000_82540, | 50 | e1000_82540, |
52 | e1000_82545, | 51 | e1000_82545, |
53 | e1000_82545_rev_3, | 52 | e1000_82545_rev_3, |
54 | e1000_82546, | 53 | e1000_82546, |
55 | e1000_82546_rev_3, | 54 | e1000_82546_rev_3, |
56 | e1000_82541, | 55 | e1000_82541, |
57 | e1000_82541_rev_2, | 56 | e1000_82541_rev_2, |
58 | e1000_82547, | 57 | e1000_82547, |
59 | e1000_82547_rev_2, | 58 | e1000_82547_rev_2, |
60 | e1000_82571, | 59 | e1000_num_macs |
61 | e1000_82572, | ||
62 | e1000_82573, | ||
63 | e1000_80003es2lan, | ||
64 | e1000_ich8lan, | ||
65 | e1000_num_macs | ||
66 | } e1000_mac_type; | 60 | } e1000_mac_type; |
67 | 61 | ||
68 | typedef enum { | 62 | typedef enum { |
69 | e1000_eeprom_uninitialized = 0, | 63 | e1000_eeprom_uninitialized = 0, |
70 | e1000_eeprom_spi, | 64 | e1000_eeprom_spi, |
71 | e1000_eeprom_microwire, | 65 | e1000_eeprom_microwire, |
72 | e1000_eeprom_flash, | 66 | e1000_eeprom_flash, |
73 | e1000_eeprom_ich8, | 67 | e1000_eeprom_none, /* No NVM support */ |
74 | e1000_eeprom_none, /* No NVM support */ | 68 | e1000_num_eeprom_types |
75 | e1000_num_eeprom_types | ||
76 | } e1000_eeprom_type; | 69 | } e1000_eeprom_type; |
77 | 70 | ||
78 | /* Media Types */ | 71 | /* Media Types */ |
79 | typedef enum { | 72 | typedef enum { |
80 | e1000_media_type_copper = 0, | 73 | e1000_media_type_copper = 0, |
81 | e1000_media_type_fiber = 1, | 74 | e1000_media_type_fiber = 1, |
82 | e1000_media_type_internal_serdes = 2, | 75 | e1000_media_type_internal_serdes = 2, |
83 | e1000_num_media_types | 76 | e1000_num_media_types |
84 | } e1000_media_type; | 77 | } e1000_media_type; |
85 | 78 | ||
86 | typedef enum { | 79 | typedef enum { |
87 | e1000_10_half = 0, | 80 | e1000_10_half = 0, |
88 | e1000_10_full = 1, | 81 | e1000_10_full = 1, |
89 | e1000_100_half = 2, | 82 | e1000_100_half = 2, |
90 | e1000_100_full = 3 | 83 | e1000_100_full = 3 |
91 | } e1000_speed_duplex_type; | 84 | } e1000_speed_duplex_type; |
92 | 85 | ||
93 | /* Flow Control Settings */ | 86 | /* Flow Control Settings */ |
94 | typedef enum { | 87 | typedef enum { |
95 | E1000_FC_NONE = 0, | 88 | E1000_FC_NONE = 0, |
96 | E1000_FC_RX_PAUSE = 1, | 89 | E1000_FC_RX_PAUSE = 1, |
97 | E1000_FC_TX_PAUSE = 2, | 90 | E1000_FC_TX_PAUSE = 2, |
98 | E1000_FC_FULL = 3, | 91 | E1000_FC_FULL = 3, |
99 | E1000_FC_DEFAULT = 0xFF | 92 | E1000_FC_DEFAULT = 0xFF |
100 | } e1000_fc_type; | 93 | } e1000_fc_type; |
101 | 94 | ||
102 | struct e1000_shadow_ram { | 95 | struct e1000_shadow_ram { |
103 | u16 eeprom_word; | 96 | u16 eeprom_word; |
104 | bool modified; | 97 | bool modified; |
105 | }; | 98 | }; |
106 | 99 | ||
107 | /* PCI bus types */ | 100 | /* PCI bus types */ |
108 | typedef enum { | 101 | typedef enum { |
109 | e1000_bus_type_unknown = 0, | 102 | e1000_bus_type_unknown = 0, |
110 | e1000_bus_type_pci, | 103 | e1000_bus_type_pci, |
111 | e1000_bus_type_pcix, | 104 | e1000_bus_type_pcix, |
112 | e1000_bus_type_pci_express, | 105 | e1000_bus_type_reserved |
113 | e1000_bus_type_reserved | ||
114 | } e1000_bus_type; | 106 | } e1000_bus_type; |
115 | 107 | ||
116 | /* PCI bus speeds */ | 108 | /* PCI bus speeds */ |
117 | typedef enum { | 109 | typedef enum { |
118 | e1000_bus_speed_unknown = 0, | 110 | e1000_bus_speed_unknown = 0, |
119 | e1000_bus_speed_33, | 111 | e1000_bus_speed_33, |
120 | e1000_bus_speed_66, | 112 | e1000_bus_speed_66, |
121 | e1000_bus_speed_100, | 113 | e1000_bus_speed_100, |
122 | e1000_bus_speed_120, | 114 | e1000_bus_speed_120, |
123 | e1000_bus_speed_133, | 115 | e1000_bus_speed_133, |
124 | e1000_bus_speed_2500, | 116 | e1000_bus_speed_reserved |
125 | e1000_bus_speed_reserved | ||
126 | } e1000_bus_speed; | 117 | } e1000_bus_speed; |
127 | 118 | ||
128 | /* PCI bus widths */ | 119 | /* PCI bus widths */ |
129 | typedef enum { | 120 | typedef enum { |
130 | e1000_bus_width_unknown = 0, | 121 | e1000_bus_width_unknown = 0, |
131 | /* These PCIe values should literally match the possible return values | 122 | e1000_bus_width_32, |
132 | * from config space */ | 123 | e1000_bus_width_64, |
133 | e1000_bus_width_pciex_1 = 1, | 124 | e1000_bus_width_reserved |
134 | e1000_bus_width_pciex_2 = 2, | ||
135 | e1000_bus_width_pciex_4 = 4, | ||
136 | e1000_bus_width_32, | ||
137 | e1000_bus_width_64, | ||
138 | e1000_bus_width_reserved | ||
139 | } e1000_bus_width; | 125 | } e1000_bus_width; |
140 | 126 | ||
141 | /* PHY status info structure and supporting enums */ | 127 | /* PHY status info structure and supporting enums */ |
142 | typedef enum { | 128 | typedef enum { |
143 | e1000_cable_length_50 = 0, | 129 | e1000_cable_length_50 = 0, |
144 | e1000_cable_length_50_80, | 130 | e1000_cable_length_50_80, |
145 | e1000_cable_length_80_110, | 131 | e1000_cable_length_80_110, |
146 | e1000_cable_length_110_140, | 132 | e1000_cable_length_110_140, |
147 | e1000_cable_length_140, | 133 | e1000_cable_length_140, |
148 | e1000_cable_length_undefined = 0xFF | 134 | e1000_cable_length_undefined = 0xFF |
149 | } e1000_cable_length; | 135 | } e1000_cable_length; |
150 | 136 | ||
151 | typedef enum { | 137 | typedef enum { |
152 | e1000_gg_cable_length_60 = 0, | 138 | e1000_gg_cable_length_60 = 0, |
153 | e1000_gg_cable_length_60_115 = 1, | 139 | e1000_gg_cable_length_60_115 = 1, |
154 | e1000_gg_cable_length_115_150 = 2, | 140 | e1000_gg_cable_length_115_150 = 2, |
155 | e1000_gg_cable_length_150 = 4 | 141 | e1000_gg_cable_length_150 = 4 |
156 | } e1000_gg_cable_length; | 142 | } e1000_gg_cable_length; |
157 | 143 | ||
158 | typedef enum { | 144 | typedef enum { |
159 | e1000_igp_cable_length_10 = 10, | 145 | e1000_igp_cable_length_10 = 10, |
160 | e1000_igp_cable_length_20 = 20, | 146 | e1000_igp_cable_length_20 = 20, |
161 | e1000_igp_cable_length_30 = 30, | 147 | e1000_igp_cable_length_30 = 30, |
162 | e1000_igp_cable_length_40 = 40, | 148 | e1000_igp_cable_length_40 = 40, |
163 | e1000_igp_cable_length_50 = 50, | 149 | e1000_igp_cable_length_50 = 50, |
164 | e1000_igp_cable_length_60 = 60, | 150 | e1000_igp_cable_length_60 = 60, |
165 | e1000_igp_cable_length_70 = 70, | 151 | e1000_igp_cable_length_70 = 70, |
166 | e1000_igp_cable_length_80 = 80, | 152 | e1000_igp_cable_length_80 = 80, |
167 | e1000_igp_cable_length_90 = 90, | 153 | e1000_igp_cable_length_90 = 90, |
168 | e1000_igp_cable_length_100 = 100, | 154 | e1000_igp_cable_length_100 = 100, |
169 | e1000_igp_cable_length_110 = 110, | 155 | e1000_igp_cable_length_110 = 110, |
170 | e1000_igp_cable_length_115 = 115, | 156 | e1000_igp_cable_length_115 = 115, |
171 | e1000_igp_cable_length_120 = 120, | 157 | e1000_igp_cable_length_120 = 120, |
172 | e1000_igp_cable_length_130 = 130, | 158 | e1000_igp_cable_length_130 = 130, |
173 | e1000_igp_cable_length_140 = 140, | 159 | e1000_igp_cable_length_140 = 140, |
174 | e1000_igp_cable_length_150 = 150, | 160 | e1000_igp_cable_length_150 = 150, |
175 | e1000_igp_cable_length_160 = 160, | 161 | e1000_igp_cable_length_160 = 160, |
176 | e1000_igp_cable_length_170 = 170, | 162 | e1000_igp_cable_length_170 = 170, |
177 | e1000_igp_cable_length_180 = 180 | 163 | e1000_igp_cable_length_180 = 180 |
178 | } e1000_igp_cable_length; | 164 | } e1000_igp_cable_length; |
179 | 165 | ||
180 | typedef enum { | 166 | typedef enum { |
181 | e1000_10bt_ext_dist_enable_normal = 0, | 167 | e1000_10bt_ext_dist_enable_normal = 0, |
182 | e1000_10bt_ext_dist_enable_lower, | 168 | e1000_10bt_ext_dist_enable_lower, |
183 | e1000_10bt_ext_dist_enable_undefined = 0xFF | 169 | e1000_10bt_ext_dist_enable_undefined = 0xFF |
184 | } e1000_10bt_ext_dist_enable; | 170 | } e1000_10bt_ext_dist_enable; |
185 | 171 | ||
186 | typedef enum { | 172 | typedef enum { |
187 | e1000_rev_polarity_normal = 0, | 173 | e1000_rev_polarity_normal = 0, |
188 | e1000_rev_polarity_reversed, | 174 | e1000_rev_polarity_reversed, |
189 | e1000_rev_polarity_undefined = 0xFF | 175 | e1000_rev_polarity_undefined = 0xFF |
190 | } e1000_rev_polarity; | 176 | } e1000_rev_polarity; |
191 | 177 | ||
192 | typedef enum { | 178 | typedef enum { |
193 | e1000_downshift_normal = 0, | 179 | e1000_downshift_normal = 0, |
194 | e1000_downshift_activated, | 180 | e1000_downshift_activated, |
195 | e1000_downshift_undefined = 0xFF | 181 | e1000_downshift_undefined = 0xFF |
196 | } e1000_downshift; | 182 | } e1000_downshift; |
197 | 183 | ||
198 | typedef enum { | 184 | typedef enum { |
199 | e1000_smart_speed_default = 0, | 185 | e1000_smart_speed_default = 0, |
200 | e1000_smart_speed_on, | 186 | e1000_smart_speed_on, |
201 | e1000_smart_speed_off | 187 | e1000_smart_speed_off |
202 | } e1000_smart_speed; | 188 | } e1000_smart_speed; |
203 | 189 | ||
204 | typedef enum { | 190 | typedef enum { |
205 | e1000_polarity_reversal_enabled = 0, | 191 | e1000_polarity_reversal_enabled = 0, |
206 | e1000_polarity_reversal_disabled, | 192 | e1000_polarity_reversal_disabled, |
207 | e1000_polarity_reversal_undefined = 0xFF | 193 | e1000_polarity_reversal_undefined = 0xFF |
208 | } e1000_polarity_reversal; | 194 | } e1000_polarity_reversal; |
209 | 195 | ||
210 | typedef enum { | 196 | typedef enum { |
211 | e1000_auto_x_mode_manual_mdi = 0, | 197 | e1000_auto_x_mode_manual_mdi = 0, |
212 | e1000_auto_x_mode_manual_mdix, | 198 | e1000_auto_x_mode_manual_mdix, |
213 | e1000_auto_x_mode_auto1, | 199 | e1000_auto_x_mode_auto1, |
214 | e1000_auto_x_mode_auto2, | 200 | e1000_auto_x_mode_auto2, |
215 | e1000_auto_x_mode_undefined = 0xFF | 201 | e1000_auto_x_mode_undefined = 0xFF |
216 | } e1000_auto_x_mode; | 202 | } e1000_auto_x_mode; |
217 | 203 | ||
218 | typedef enum { | 204 | typedef enum { |
219 | e1000_1000t_rx_status_not_ok = 0, | 205 | e1000_1000t_rx_status_not_ok = 0, |
220 | e1000_1000t_rx_status_ok, | 206 | e1000_1000t_rx_status_ok, |
221 | e1000_1000t_rx_status_undefined = 0xFF | 207 | e1000_1000t_rx_status_undefined = 0xFF |
222 | } e1000_1000t_rx_status; | 208 | } e1000_1000t_rx_status; |
223 | 209 | ||
224 | typedef enum { | 210 | typedef enum { |
225 | e1000_phy_m88 = 0, | 211 | e1000_phy_m88 = 0, |
226 | e1000_phy_igp, | 212 | e1000_phy_igp, |
227 | e1000_phy_igp_2, | ||
228 | e1000_phy_gg82563, | ||
229 | e1000_phy_igp_3, | ||
230 | e1000_phy_ife, | ||
231 | e1000_phy_undefined = 0xFF | 213 | e1000_phy_undefined = 0xFF |
232 | } e1000_phy_type; | 214 | } e1000_phy_type; |
233 | 215 | ||
234 | typedef enum { | 216 | typedef enum { |
235 | e1000_ms_hw_default = 0, | 217 | e1000_ms_hw_default = 0, |
236 | e1000_ms_force_master, | 218 | e1000_ms_force_master, |
237 | e1000_ms_force_slave, | 219 | e1000_ms_force_slave, |
238 | e1000_ms_auto | 220 | e1000_ms_auto |
239 | } e1000_ms_type; | 221 | } e1000_ms_type; |
240 | 222 | ||
241 | typedef enum { | 223 | typedef enum { |
242 | e1000_ffe_config_enabled = 0, | 224 | e1000_ffe_config_enabled = 0, |
243 | e1000_ffe_config_active, | 225 | e1000_ffe_config_active, |
244 | e1000_ffe_config_blocked | 226 | e1000_ffe_config_blocked |
245 | } e1000_ffe_config; | 227 | } e1000_ffe_config; |
246 | 228 | ||
247 | typedef enum { | 229 | typedef enum { |
248 | e1000_dsp_config_disabled = 0, | 230 | e1000_dsp_config_disabled = 0, |
249 | e1000_dsp_config_enabled, | 231 | e1000_dsp_config_enabled, |
250 | e1000_dsp_config_activated, | 232 | e1000_dsp_config_activated, |
251 | e1000_dsp_config_undefined = 0xFF | 233 | e1000_dsp_config_undefined = 0xFF |
252 | } e1000_dsp_config; | 234 | } e1000_dsp_config; |
253 | 235 | ||
254 | struct e1000_phy_info { | 236 | struct e1000_phy_info { |
255 | e1000_cable_length cable_length; | 237 | e1000_cable_length cable_length; |
256 | e1000_10bt_ext_dist_enable extended_10bt_distance; | 238 | e1000_10bt_ext_dist_enable extended_10bt_distance; |
257 | e1000_rev_polarity cable_polarity; | 239 | e1000_rev_polarity cable_polarity; |
258 | e1000_downshift downshift; | 240 | e1000_downshift downshift; |
259 | e1000_polarity_reversal polarity_correction; | 241 | e1000_polarity_reversal polarity_correction; |
260 | e1000_auto_x_mode mdix_mode; | 242 | e1000_auto_x_mode mdix_mode; |
261 | e1000_1000t_rx_status local_rx; | 243 | e1000_1000t_rx_status local_rx; |
262 | e1000_1000t_rx_status remote_rx; | 244 | e1000_1000t_rx_status remote_rx; |
263 | }; | 245 | }; |
264 | 246 | ||
265 | struct e1000_phy_stats { | 247 | struct e1000_phy_stats { |
266 | u32 idle_errors; | 248 | u32 idle_errors; |
267 | u32 receive_errors; | 249 | u32 receive_errors; |
268 | }; | 250 | }; |
269 | 251 | ||
270 | struct e1000_eeprom_info { | 252 | struct e1000_eeprom_info { |
271 | e1000_eeprom_type type; | 253 | e1000_eeprom_type type; |
272 | u16 word_size; | 254 | u16 word_size; |
273 | u16 opcode_bits; | 255 | u16 opcode_bits; |
274 | u16 address_bits; | 256 | u16 address_bits; |
275 | u16 delay_usec; | 257 | u16 delay_usec; |
276 | u16 page_size; | 258 | u16 page_size; |
277 | bool use_eerd; | ||
278 | bool use_eewr; | ||
279 | }; | 259 | }; |
280 | 260 | ||
281 | /* Flex ASF Information */ | 261 | /* Flex ASF Information */ |
282 | #define E1000_HOST_IF_MAX_SIZE 2048 | 262 | #define E1000_HOST_IF_MAX_SIZE 2048 |
283 | 263 | ||
284 | typedef enum { | 264 | typedef enum { |
285 | e1000_byte_align = 0, | 265 | e1000_byte_align = 0, |
286 | e1000_word_align = 1, | 266 | e1000_word_align = 1, |
287 | e1000_dword_align = 2 | 267 | e1000_dword_align = 2 |
288 | } e1000_align_type; | 268 | } e1000_align_type; |
289 | 269 | ||
290 | |||
291 | |||
292 | /* Error Codes */ | 270 | /* Error Codes */ |
293 | #define E1000_SUCCESS 0 | 271 | #define E1000_SUCCESS 0 |
294 | #define E1000_ERR_EEPROM 1 | 272 | #define E1000_ERR_EEPROM 1 |
@@ -301,7 +279,6 @@ typedef enum { | |||
301 | #define E1000_ERR_MASTER_REQUESTS_PENDING 10 | 279 | #define E1000_ERR_MASTER_REQUESTS_PENDING 10 |
302 | #define E1000_ERR_HOST_INTERFACE_COMMAND 11 | 280 | #define E1000_ERR_HOST_INTERFACE_COMMAND 11 |
303 | #define E1000_BLK_PHY_RESET 12 | 281 | #define E1000_BLK_PHY_RESET 12 |
304 | #define E1000_ERR_SWFW_SYNC 13 | ||
305 | 282 | ||
306 | #define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \ | 283 | #define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \ |
307 | (((_value) & 0xff00) >> 8)) | 284 | (((_value) & 0xff00) >> 8)) |
@@ -318,19 +295,17 @@ s32 e1000_setup_link(struct e1000_hw *hw); | |||
318 | s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); | 295 | s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); |
319 | void e1000_config_collision_dist(struct e1000_hw *hw); | 296 | void e1000_config_collision_dist(struct e1000_hw *hw); |
320 | s32 e1000_check_for_link(struct e1000_hw *hw); | 297 | s32 e1000_check_for_link(struct e1000_hw *hw); |
321 | s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex); | 298 | s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 * speed, u16 * duplex); |
322 | s32 e1000_force_mac_fc(struct e1000_hw *hw); | 299 | s32 e1000_force_mac_fc(struct e1000_hw *hw); |
323 | 300 | ||
324 | /* PHY */ | 301 | /* PHY */ |
325 | s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data); | 302 | s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 * phy_data); |
326 | s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data); | 303 | s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data); |
327 | s32 e1000_phy_hw_reset(struct e1000_hw *hw); | 304 | s32 e1000_phy_hw_reset(struct e1000_hw *hw); |
328 | s32 e1000_phy_reset(struct e1000_hw *hw); | 305 | s32 e1000_phy_reset(struct e1000_hw *hw); |
329 | s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); | 306 | s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); |
330 | s32 e1000_validate_mdi_setting(struct e1000_hw *hw); | 307 | s32 e1000_validate_mdi_setting(struct e1000_hw *hw); |
331 | 308 | ||
332 | void e1000_phy_powerdown_workaround(struct e1000_hw *hw); | ||
333 | |||
334 | /* EEPROM Functions */ | 309 | /* EEPROM Functions */ |
335 | s32 e1000_init_eeprom_params(struct e1000_hw *hw); | 310 | s32 e1000_init_eeprom_params(struct e1000_hw *hw); |
336 | 311 | ||
@@ -338,66 +313,63 @@ s32 e1000_init_eeprom_params(struct e1000_hw *hw); | |||
338 | u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw); | 313 | u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw); |
339 | 314 | ||
340 | #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 | 315 | #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 |
341 | #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */ | 316 | #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */ |
342 | 317 | ||
343 | #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */ | 318 | #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */ |
344 | #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ | 319 | #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ |
345 | #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ | 320 | #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ |
346 | #define E1000_MNG_IAMT_MODE 0x3 | 321 | #define E1000_MNG_IAMT_MODE 0x3 |
347 | #define E1000_MNG_ICH_IAMT_MODE 0x2 | 322 | #define E1000_MNG_ICH_IAMT_MODE 0x2 |
348 | #define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ | 323 | #define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ |
349 | 324 | ||
350 | #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */ | 325 | #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */ |
351 | #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */ | 326 | #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */ |
352 | #define E1000_VFTA_ENTRY_SHIFT 0x5 | 327 | #define E1000_VFTA_ENTRY_SHIFT 0x5 |
353 | #define E1000_VFTA_ENTRY_MASK 0x7F | 328 | #define E1000_VFTA_ENTRY_MASK 0x7F |
354 | #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F | 329 | #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F |
355 | 330 | ||
356 | struct e1000_host_mng_command_header { | 331 | struct e1000_host_mng_command_header { |
357 | u8 command_id; | 332 | u8 command_id; |
358 | u8 checksum; | 333 | u8 checksum; |
359 | u16 reserved1; | 334 | u16 reserved1; |
360 | u16 reserved2; | 335 | u16 reserved2; |
361 | u16 command_length; | 336 | u16 command_length; |
362 | }; | 337 | }; |
363 | 338 | ||
364 | struct e1000_host_mng_command_info { | 339 | struct e1000_host_mng_command_info { |
365 | struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ | 340 | struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ |
366 | u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/ | 341 | u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658 */ |
367 | }; | 342 | }; |
368 | #ifdef __BIG_ENDIAN | 343 | #ifdef __BIG_ENDIAN |
369 | struct e1000_host_mng_dhcp_cookie{ | 344 | struct e1000_host_mng_dhcp_cookie { |
370 | u32 signature; | 345 | u32 signature; |
371 | u16 vlan_id; | 346 | u16 vlan_id; |
372 | u8 reserved0; | 347 | u8 reserved0; |
373 | u8 status; | 348 | u8 status; |
374 | u32 reserved1; | 349 | u32 reserved1; |
375 | u8 checksum; | 350 | u8 checksum; |
376 | u8 reserved3; | 351 | u8 reserved3; |
377 | u16 reserved2; | 352 | u16 reserved2; |
378 | }; | 353 | }; |
379 | #else | 354 | #else |
380 | struct e1000_host_mng_dhcp_cookie{ | 355 | struct e1000_host_mng_dhcp_cookie { |
381 | u32 signature; | 356 | u32 signature; |
382 | u8 status; | 357 | u8 status; |
383 | u8 reserved0; | 358 | u8 reserved0; |
384 | u16 vlan_id; | 359 | u16 vlan_id; |
385 | u32 reserved1; | 360 | u32 reserved1; |
386 | u16 reserved2; | 361 | u16 reserved2; |
387 | u8 reserved3; | 362 | u8 reserved3; |
388 | u8 checksum; | 363 | u8 checksum; |
389 | }; | 364 | }; |
390 | #endif | 365 | #endif |
391 | 366 | ||
392 | s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, | ||
393 | u16 length); | ||
394 | bool e1000_check_mng_mode(struct e1000_hw *hw); | 367 | bool e1000_check_mng_mode(struct e1000_hw *hw); |
395 | bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); | 368 | s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data); |
396 | s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data); | ||
397 | s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw); | 369 | s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw); |
398 | s32 e1000_update_eeprom_checksum(struct e1000_hw *hw); | 370 | s32 e1000_update_eeprom_checksum(struct e1000_hw *hw); |
399 | s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data); | 371 | s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data); |
400 | s32 e1000_read_mac_addr(struct e1000_hw * hw); | 372 | s32 e1000_read_mac_addr(struct e1000_hw *hw); |
401 | 373 | ||
402 | /* Filters (multicast, vlan, receive) */ | 374 | /* Filters (multicast, vlan, receive) */ |
403 | u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr); | 375 | u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr); |
@@ -417,18 +389,15 @@ s32 e1000_blink_led_start(struct e1000_hw *hw); | |||
417 | /* Everything else */ | 389 | /* Everything else */ |
418 | void e1000_reset_adaptive(struct e1000_hw *hw); | 390 | void e1000_reset_adaptive(struct e1000_hw *hw); |
419 | void e1000_update_adaptive(struct e1000_hw *hw); | 391 | void e1000_update_adaptive(struct e1000_hw *hw); |
420 | void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, u32 frame_len, u8 * mac_addr); | 392 | void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, |
393 | u32 frame_len, u8 * mac_addr); | ||
421 | void e1000_get_bus_info(struct e1000_hw *hw); | 394 | void e1000_get_bus_info(struct e1000_hw *hw); |
422 | void e1000_pci_set_mwi(struct e1000_hw *hw); | 395 | void e1000_pci_set_mwi(struct e1000_hw *hw); |
423 | void e1000_pci_clear_mwi(struct e1000_hw *hw); | 396 | void e1000_pci_clear_mwi(struct e1000_hw *hw); |
424 | s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); | ||
425 | void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc); | 397 | void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc); |
426 | int e1000_pcix_get_mmrbc(struct e1000_hw *hw); | 398 | int e1000_pcix_get_mmrbc(struct e1000_hw *hw); |
427 | /* Port I/O is only supported on 82544 and newer */ | 399 | /* Port I/O is only supported on 82544 and newer */ |
428 | void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value); | 400 | void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value); |
429 | s32 e1000_disable_pciex_master(struct e1000_hw *hw); | ||
430 | s32 e1000_check_phy_reset_block(struct e1000_hw *hw); | ||
431 | |||
432 | 401 | ||
433 | #define E1000_READ_REG_IO(a, reg) \ | 402 | #define E1000_READ_REG_IO(a, reg) \ |
434 | e1000_read_reg_io((a), E1000_##reg) | 403 | e1000_read_reg_io((a), E1000_##reg) |
@@ -471,36 +440,7 @@ s32 e1000_check_phy_reset_block(struct e1000_hw *hw); | |||
471 | #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 | 440 | #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 |
472 | #define E1000_DEV_ID_82547EI 0x1019 | 441 | #define E1000_DEV_ID_82547EI 0x1019 |
473 | #define E1000_DEV_ID_82547EI_MOBILE 0x101A | 442 | #define E1000_DEV_ID_82547EI_MOBILE 0x101A |
474 | #define E1000_DEV_ID_82571EB_COPPER 0x105E | ||
475 | #define E1000_DEV_ID_82571EB_FIBER 0x105F | ||
476 | #define E1000_DEV_ID_82571EB_SERDES 0x1060 | ||
477 | #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 | ||
478 | #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 | ||
479 | #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 | ||
480 | #define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC | ||
481 | #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 | ||
482 | #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA | ||
483 | #define E1000_DEV_ID_82572EI_COPPER 0x107D | ||
484 | #define E1000_DEV_ID_82572EI_FIBER 0x107E | ||
485 | #define E1000_DEV_ID_82572EI_SERDES 0x107F | ||
486 | #define E1000_DEV_ID_82572EI 0x10B9 | ||
487 | #define E1000_DEV_ID_82573E 0x108B | ||
488 | #define E1000_DEV_ID_82573E_IAMT 0x108C | ||
489 | #define E1000_DEV_ID_82573L 0x109A | ||
490 | #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 | 443 | #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 |
491 | #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 | ||
492 | #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 | ||
493 | #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA | ||
494 | #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB | ||
495 | |||
496 | #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 | ||
497 | #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A | ||
498 | #define E1000_DEV_ID_ICH8_IGP_C 0x104B | ||
499 | #define E1000_DEV_ID_ICH8_IFE 0x104C | ||
500 | #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 | ||
501 | #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 | ||
502 | #define E1000_DEV_ID_ICH8_IGP_M 0x104D | ||
503 | |||
504 | 444 | ||
505 | #define NODE_ADDRESS_SIZE 6 | 445 | #define NODE_ADDRESS_SIZE 6 |
506 | #define ETH_LENGTH_OF_ADDRESS 6 | 446 | #define ETH_LENGTH_OF_ADDRESS 6 |
@@ -523,21 +463,20 @@ s32 e1000_check_phy_reset_block(struct e1000_hw *hw); | |||
523 | 463 | ||
524 | /* The sizes (in bytes) of a ethernet packet */ | 464 | /* The sizes (in bytes) of a ethernet packet */ |
525 | #define ENET_HEADER_SIZE 14 | 465 | #define ENET_HEADER_SIZE 14 |
526 | #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ | 466 | #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ |
527 | #define ETHERNET_FCS_SIZE 4 | 467 | #define ETHERNET_FCS_SIZE 4 |
528 | #define MINIMUM_ETHERNET_PACKET_SIZE \ | 468 | #define MINIMUM_ETHERNET_PACKET_SIZE \ |
529 | (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) | 469 | (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) |
530 | #define CRC_LENGTH ETHERNET_FCS_SIZE | 470 | #define CRC_LENGTH ETHERNET_FCS_SIZE |
531 | #define MAX_JUMBO_FRAME_SIZE 0x3F00 | 471 | #define MAX_JUMBO_FRAME_SIZE 0x3F00 |
532 | 472 | ||
533 | |||
534 | /* 802.1q VLAN Packet Sizes */ | 473 | /* 802.1q VLAN Packet Sizes */ |
535 | #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ | 474 | #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ |
536 | 475 | ||
537 | /* Ethertype field values */ | 476 | /* Ethertype field values */ |
538 | #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ | 477 | #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ |
539 | #define ETHERNET_IP_TYPE 0x0800 /* IP packets */ | 478 | #define ETHERNET_IP_TYPE 0x0800 /* IP packets */ |
540 | #define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ | 479 | #define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ |
541 | 480 | ||
542 | /* Packet Header defines */ | 481 | /* Packet Header defines */ |
543 | #define IP_PROTOCOL_TCP 6 | 482 | #define IP_PROTOCOL_TCP 6 |
@@ -567,15 +506,6 @@ s32 e1000_check_phy_reset_block(struct e1000_hw *hw); | |||
567 | E1000_IMS_RXSEQ | \ | 506 | E1000_IMS_RXSEQ | \ |
568 | E1000_IMS_LSC) | 507 | E1000_IMS_LSC) |
569 | 508 | ||
570 | /* Additional interrupts need to be handled for e1000_ich8lan: | ||
571 | DSW = The FW changed the status of the DISSW bit in FWSM | ||
572 | PHYINT = The LAN connected device generates an interrupt | ||
573 | EPRST = Manageability reset event */ | ||
574 | #define IMS_ICH8LAN_ENABLE_MASK (\ | ||
575 | E1000_IMS_DSW | \ | ||
576 | E1000_IMS_PHYINT | \ | ||
577 | E1000_IMS_EPRST) | ||
578 | |||
579 | /* Number of high/low register pairs in the RAR. The RAR (Receive Address | 509 | /* Number of high/low register pairs in the RAR. The RAR (Receive Address |
580 | * Registers) holds the directed and multicast addresses that we monitor. We | 510 | * Registers) holds the directed and multicast addresses that we monitor. We |
581 | * reserve one of these spots for our directed address, allowing us room for | 511 | * reserve one of these spots for our directed address, allowing us room for |
@@ -583,100 +513,98 @@ s32 e1000_check_phy_reset_block(struct e1000_hw *hw); | |||
583 | */ | 513 | */ |
584 | #define E1000_RAR_ENTRIES 15 | 514 | #define E1000_RAR_ENTRIES 15 |
585 | 515 | ||
586 | #define E1000_RAR_ENTRIES_ICH8LAN 6 | ||
587 | |||
588 | #define MIN_NUMBER_OF_DESCRIPTORS 8 | 516 | #define MIN_NUMBER_OF_DESCRIPTORS 8 |
589 | #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 | 517 | #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 |
590 | 518 | ||
591 | /* Receive Descriptor */ | 519 | /* Receive Descriptor */ |
592 | struct e1000_rx_desc { | 520 | struct e1000_rx_desc { |
593 | __le64 buffer_addr; /* Address of the descriptor's data buffer */ | 521 | __le64 buffer_addr; /* Address of the descriptor's data buffer */ |
594 | __le16 length; /* Length of data DMAed into data buffer */ | 522 | __le16 length; /* Length of data DMAed into data buffer */ |
595 | __le16 csum; /* Packet checksum */ | 523 | __le16 csum; /* Packet checksum */ |
596 | u8 status; /* Descriptor status */ | 524 | u8 status; /* Descriptor status */ |
597 | u8 errors; /* Descriptor Errors */ | 525 | u8 errors; /* Descriptor Errors */ |
598 | __le16 special; | 526 | __le16 special; |
599 | }; | 527 | }; |
600 | 528 | ||
601 | /* Receive Descriptor - Extended */ | 529 | /* Receive Descriptor - Extended */ |
602 | union e1000_rx_desc_extended { | 530 | union e1000_rx_desc_extended { |
603 | struct { | 531 | struct { |
604 | __le64 buffer_addr; | 532 | __le64 buffer_addr; |
605 | __le64 reserved; | 533 | __le64 reserved; |
606 | } read; | 534 | } read; |
607 | struct { | 535 | struct { |
608 | struct { | 536 | struct { |
609 | __le32 mrq; /* Multiple Rx Queues */ | 537 | __le32 mrq; /* Multiple Rx Queues */ |
610 | union { | 538 | union { |
611 | __le32 rss; /* RSS Hash */ | 539 | __le32 rss; /* RSS Hash */ |
612 | struct { | 540 | struct { |
613 | __le16 ip_id; /* IP id */ | 541 | __le16 ip_id; /* IP id */ |
614 | __le16 csum; /* Packet Checksum */ | 542 | __le16 csum; /* Packet Checksum */ |
615 | } csum_ip; | 543 | } csum_ip; |
616 | } hi_dword; | 544 | } hi_dword; |
617 | } lower; | 545 | } lower; |
618 | struct { | 546 | struct { |
619 | __le32 status_error; /* ext status/error */ | 547 | __le32 status_error; /* ext status/error */ |
620 | __le16 length; | 548 | __le16 length; |
621 | __le16 vlan; /* VLAN tag */ | 549 | __le16 vlan; /* VLAN tag */ |
622 | } upper; | 550 | } upper; |
623 | } wb; /* writeback */ | 551 | } wb; /* writeback */ |
624 | }; | 552 | }; |
625 | 553 | ||
626 | #define MAX_PS_BUFFERS 4 | 554 | #define MAX_PS_BUFFERS 4 |
627 | /* Receive Descriptor - Packet Split */ | 555 | /* Receive Descriptor - Packet Split */ |
628 | union e1000_rx_desc_packet_split { | 556 | union e1000_rx_desc_packet_split { |
629 | struct { | 557 | struct { |
630 | /* one buffer for protocol header(s), three data buffers */ | 558 | /* one buffer for protocol header(s), three data buffers */ |
631 | __le64 buffer_addr[MAX_PS_BUFFERS]; | 559 | __le64 buffer_addr[MAX_PS_BUFFERS]; |
632 | } read; | 560 | } read; |
633 | struct { | 561 | struct { |
634 | struct { | 562 | struct { |
635 | __le32 mrq; /* Multiple Rx Queues */ | 563 | __le32 mrq; /* Multiple Rx Queues */ |
636 | union { | 564 | union { |
637 | __le32 rss; /* RSS Hash */ | 565 | __le32 rss; /* RSS Hash */ |
638 | struct { | 566 | struct { |
639 | __le16 ip_id; /* IP id */ | 567 | __le16 ip_id; /* IP id */ |
640 | __le16 csum; /* Packet Checksum */ | 568 | __le16 csum; /* Packet Checksum */ |
641 | } csum_ip; | 569 | } csum_ip; |
642 | } hi_dword; | 570 | } hi_dword; |
643 | } lower; | 571 | } lower; |
644 | struct { | 572 | struct { |
645 | __le32 status_error; /* ext status/error */ | 573 | __le32 status_error; /* ext status/error */ |
646 | __le16 length0; /* length of buffer 0 */ | 574 | __le16 length0; /* length of buffer 0 */ |
647 | __le16 vlan; /* VLAN tag */ | 575 | __le16 vlan; /* VLAN tag */ |
648 | } middle; | 576 | } middle; |
649 | struct { | 577 | struct { |
650 | __le16 header_status; | 578 | __le16 header_status; |
651 | __le16 length[3]; /* length of buffers 1-3 */ | 579 | __le16 length[3]; /* length of buffers 1-3 */ |
652 | } upper; | 580 | } upper; |
653 | __le64 reserved; | 581 | __le64 reserved; |
654 | } wb; /* writeback */ | 582 | } wb; /* writeback */ |
655 | }; | 583 | }; |
656 | 584 | ||
657 | /* Receive Decriptor bit definitions */ | 585 | /* Receive Descriptor bit definitions */ |
658 | #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ | 586 | #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ |
659 | #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ | 587 | #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ |
660 | #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ | 588 | #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ |
661 | #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ | 589 | #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ |
662 | #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ | 590 | #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ |
663 | #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ | 591 | #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ |
664 | #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ | 592 | #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ |
665 | #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ | 593 | #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ |
666 | #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ | 594 | #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ |
667 | #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ | 595 | #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ |
668 | #define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ | 596 | #define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ |
669 | #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ | 597 | #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ |
670 | #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ | 598 | #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ |
671 | #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ | 599 | #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ |
672 | #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ | 600 | #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ |
673 | #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ | 601 | #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ |
674 | #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ | 602 | #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ |
675 | #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ | 603 | #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ |
676 | #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ | 604 | #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ |
677 | #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ | 605 | #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ |
678 | #define E1000_RXD_SPC_PRI_SHIFT 13 | 606 | #define E1000_RXD_SPC_PRI_SHIFT 13 |
679 | #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ | 607 | #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ |
680 | #define E1000_RXD_SPC_CFI_SHIFT 12 | 608 | #define E1000_RXD_SPC_CFI_SHIFT 12 |
681 | 609 | ||
682 | #define E1000_RXDEXT_STATERR_CE 0x01000000 | 610 | #define E1000_RXDEXT_STATERR_CE 0x01000000 |
@@ -698,7 +626,6 @@ union e1000_rx_desc_packet_split { | |||
698 | E1000_RXD_ERR_CXE | \ | 626 | E1000_RXD_ERR_CXE | \ |
699 | E1000_RXD_ERR_RXE) | 627 | E1000_RXD_ERR_RXE) |
700 | 628 | ||
701 | |||
702 | /* Same mask, but for extended and packet split descriptors */ | 629 | /* Same mask, but for extended and packet split descriptors */ |
703 | #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ | 630 | #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ |
704 | E1000_RXDEXT_STATERR_CE | \ | 631 | E1000_RXDEXT_STATERR_CE | \ |
@@ -707,152 +634,145 @@ union e1000_rx_desc_packet_split { | |||
707 | E1000_RXDEXT_STATERR_CXE | \ | 634 | E1000_RXDEXT_STATERR_CXE | \ |
708 | E1000_RXDEXT_STATERR_RXE) | 635 | E1000_RXDEXT_STATERR_RXE) |
709 | 636 | ||
710 | |||
711 | /* Transmit Descriptor */ | 637 | /* Transmit Descriptor */ |
712 | struct e1000_tx_desc { | 638 | struct e1000_tx_desc { |
713 | __le64 buffer_addr; /* Address of the descriptor's data buffer */ | 639 | __le64 buffer_addr; /* Address of the descriptor's data buffer */ |
714 | union { | 640 | union { |
715 | __le32 data; | 641 | __le32 data; |
716 | struct { | 642 | struct { |
717 | __le16 length; /* Data buffer length */ | 643 | __le16 length; /* Data buffer length */ |
718 | u8 cso; /* Checksum offset */ | 644 | u8 cso; /* Checksum offset */ |
719 | u8 cmd; /* Descriptor control */ | 645 | u8 cmd; /* Descriptor control */ |
720 | } flags; | 646 | } flags; |
721 | } lower; | 647 | } lower; |
722 | union { | 648 | union { |
723 | __le32 data; | 649 | __le32 data; |
724 | struct { | 650 | struct { |
725 | u8 status; /* Descriptor status */ | 651 | u8 status; /* Descriptor status */ |
726 | u8 css; /* Checksum start */ | 652 | u8 css; /* Checksum start */ |
727 | __le16 special; | 653 | __le16 special; |
728 | } fields; | 654 | } fields; |
729 | } upper; | 655 | } upper; |
730 | }; | 656 | }; |
731 | 657 | ||
732 | /* Transmit Descriptor bit definitions */ | 658 | /* Transmit Descriptor bit definitions */ |
733 | #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ | 659 | #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ |
734 | #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ | 660 | #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ |
735 | #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ | 661 | #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ |
736 | #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ | 662 | #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ |
737 | #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ | 663 | #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ |
738 | #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ | 664 | #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ |
739 | #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ | 665 | #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ |
740 | #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ | 666 | #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ |
741 | #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ | 667 | #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ |
742 | #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ | 668 | #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ |
743 | #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ | 669 | #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ |
744 | #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ | 670 | #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ |
745 | #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ | 671 | #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ |
746 | #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ | 672 | #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ |
747 | #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ | 673 | #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ |
748 | #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ | 674 | #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ |
749 | #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ | 675 | #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ |
750 | #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ | 676 | #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ |
751 | #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ | 677 | #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ |
752 | #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ | 678 | #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ |
753 | 679 | ||
754 | /* Offload Context Descriptor */ | 680 | /* Offload Context Descriptor */ |
755 | struct e1000_context_desc { | 681 | struct e1000_context_desc { |
756 | union { | 682 | union { |
757 | __le32 ip_config; | 683 | __le32 ip_config; |
758 | struct { | 684 | struct { |
759 | u8 ipcss; /* IP checksum start */ | 685 | u8 ipcss; /* IP checksum start */ |
760 | u8 ipcso; /* IP checksum offset */ | 686 | u8 ipcso; /* IP checksum offset */ |
761 | __le16 ipcse; /* IP checksum end */ | 687 | __le16 ipcse; /* IP checksum end */ |
762 | } ip_fields; | 688 | } ip_fields; |
763 | } lower_setup; | 689 | } lower_setup; |
764 | union { | 690 | union { |
765 | __le32 tcp_config; | 691 | __le32 tcp_config; |
766 | struct { | 692 | struct { |
767 | u8 tucss; /* TCP checksum start */ | 693 | u8 tucss; /* TCP checksum start */ |
768 | u8 tucso; /* TCP checksum offset */ | 694 | u8 tucso; /* TCP checksum offset */ |
769 | __le16 tucse; /* TCP checksum end */ | 695 | __le16 tucse; /* TCP checksum end */ |
770 | } tcp_fields; | 696 | } tcp_fields; |
771 | } upper_setup; | 697 | } upper_setup; |
772 | __le32 cmd_and_length; /* */ | 698 | __le32 cmd_and_length; /* */ |
773 | union { | 699 | union { |
774 | __le32 data; | 700 | __le32 data; |
775 | struct { | 701 | struct { |
776 | u8 status; /* Descriptor status */ | 702 | u8 status; /* Descriptor status */ |
777 | u8 hdr_len; /* Header length */ | 703 | u8 hdr_len; /* Header length */ |
778 | __le16 mss; /* Maximum segment size */ | 704 | __le16 mss; /* Maximum segment size */ |
779 | } fields; | 705 | } fields; |
780 | } tcp_seg_setup; | 706 | } tcp_seg_setup; |
781 | }; | 707 | }; |
782 | 708 | ||
783 | /* Offload data descriptor */ | 709 | /* Offload data descriptor */ |
784 | struct e1000_data_desc { | 710 | struct e1000_data_desc { |
785 | __le64 buffer_addr; /* Address of the descriptor's buffer address */ | 711 | __le64 buffer_addr; /* Address of the descriptor's buffer address */ |
786 | union { | 712 | union { |
787 | __le32 data; | 713 | __le32 data; |
788 | struct { | 714 | struct { |
789 | __le16 length; /* Data buffer length */ | 715 | __le16 length; /* Data buffer length */ |
790 | u8 typ_len_ext; /* */ | 716 | u8 typ_len_ext; /* */ |
791 | u8 cmd; /* */ | 717 | u8 cmd; /* */ |
792 | } flags; | 718 | } flags; |
793 | } lower; | 719 | } lower; |
794 | union { | 720 | union { |
795 | __le32 data; | 721 | __le32 data; |
796 | struct { | 722 | struct { |
797 | u8 status; /* Descriptor status */ | 723 | u8 status; /* Descriptor status */ |
798 | u8 popts; /* Packet Options */ | 724 | u8 popts; /* Packet Options */ |
799 | __le16 special; /* */ | 725 | __le16 special; /* */ |
800 | } fields; | 726 | } fields; |
801 | } upper; | 727 | } upper; |
802 | }; | 728 | }; |
803 | 729 | ||
804 | /* Filters */ | 730 | /* Filters */ |
805 | #define E1000_NUM_UNICAST 16 /* Unicast filter entries */ | 731 | #define E1000_NUM_UNICAST 16 /* Unicast filter entries */ |
806 | #define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ | 732 | #define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ |
807 | #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ | 733 | #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ |
808 | |||
809 | #define E1000_NUM_UNICAST_ICH8LAN 7 | ||
810 | #define E1000_MC_TBL_SIZE_ICH8LAN 32 | ||
811 | |||
812 | 734 | ||
813 | /* Receive Address Register */ | 735 | /* Receive Address Register */ |
814 | struct e1000_rar { | 736 | struct e1000_rar { |
815 | volatile __le32 low; /* receive address low */ | 737 | volatile __le32 low; /* receive address low */ |
816 | volatile __le32 high; /* receive address high */ | 738 | volatile __le32 high; /* receive address high */ |
817 | }; | 739 | }; |
818 | 740 | ||
819 | /* Number of entries in the Multicast Table Array (MTA). */ | 741 | /* Number of entries in the Multicast Table Array (MTA). */ |
820 | #define E1000_NUM_MTA_REGISTERS 128 | 742 | #define E1000_NUM_MTA_REGISTERS 128 |
821 | #define E1000_NUM_MTA_REGISTERS_ICH8LAN 32 | ||
822 | 743 | ||
823 | /* IPv4 Address Table Entry */ | 744 | /* IPv4 Address Table Entry */ |
824 | struct e1000_ipv4_at_entry { | 745 | struct e1000_ipv4_at_entry { |
825 | volatile u32 ipv4_addr; /* IP Address (RW) */ | 746 | volatile u32 ipv4_addr; /* IP Address (RW) */ |
826 | volatile u32 reserved; | 747 | volatile u32 reserved; |
827 | }; | 748 | }; |
828 | 749 | ||
829 | /* Four wakeup IP addresses are supported */ | 750 | /* Four wakeup IP addresses are supported */ |
830 | #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 | 751 | #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 |
831 | #define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX | 752 | #define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX |
832 | #define E1000_IP4AT_SIZE_ICH8LAN 3 | ||
833 | #define E1000_IP6AT_SIZE 1 | 753 | #define E1000_IP6AT_SIZE 1 |
834 | 754 | ||
835 | /* IPv6 Address Table Entry */ | 755 | /* IPv6 Address Table Entry */ |
836 | struct e1000_ipv6_at_entry { | 756 | struct e1000_ipv6_at_entry { |
837 | volatile u8 ipv6_addr[16]; | 757 | volatile u8 ipv6_addr[16]; |
838 | }; | 758 | }; |
839 | 759 | ||
840 | /* Flexible Filter Length Table Entry */ | 760 | /* Flexible Filter Length Table Entry */ |
841 | struct e1000_fflt_entry { | 761 | struct e1000_fflt_entry { |
842 | volatile u32 length; /* Flexible Filter Length (RW) */ | 762 | volatile u32 length; /* Flexible Filter Length (RW) */ |
843 | volatile u32 reserved; | 763 | volatile u32 reserved; |
844 | }; | 764 | }; |
845 | 765 | ||
846 | /* Flexible Filter Mask Table Entry */ | 766 | /* Flexible Filter Mask Table Entry */ |
847 | struct e1000_ffmt_entry { | 767 | struct e1000_ffmt_entry { |
848 | volatile u32 mask; /* Flexible Filter Mask (RW) */ | 768 | volatile u32 mask; /* Flexible Filter Mask (RW) */ |
849 | volatile u32 reserved; | 769 | volatile u32 reserved; |
850 | }; | 770 | }; |
851 | 771 | ||
852 | /* Flexible Filter Value Table Entry */ | 772 | /* Flexible Filter Value Table Entry */ |
853 | struct e1000_ffvt_entry { | 773 | struct e1000_ffvt_entry { |
854 | volatile u32 value; /* Flexible Filter Value (RW) */ | 774 | volatile u32 value; /* Flexible Filter Value (RW) */ |
855 | volatile u32 reserved; | 775 | volatile u32 reserved; |
856 | }; | 776 | }; |
857 | 777 | ||
858 | /* Four Flexible Filters are supported */ | 778 | /* Four Flexible Filters are supported */ |
@@ -879,211 +799,211 @@ struct e1000_ffvt_entry { | |||
879 | * R/clr - register is read only and is cleared when read | 799 | * R/clr - register is read only and is cleared when read |
880 | * A - register array | 800 | * A - register array |
881 | */ | 801 | */ |
882 | #define E1000_CTRL 0x00000 /* Device Control - RW */ | 802 | #define E1000_CTRL 0x00000 /* Device Control - RW */ |
883 | #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ | 803 | #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ |
884 | #define E1000_STATUS 0x00008 /* Device Status - RO */ | 804 | #define E1000_STATUS 0x00008 /* Device Status - RO */ |
885 | #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ | 805 | #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ |
886 | #define E1000_EERD 0x00014 /* EEPROM Read - RW */ | 806 | #define E1000_EERD 0x00014 /* EEPROM Read - RW */ |
887 | #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ | 807 | #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ |
888 | #define E1000_FLA 0x0001C /* Flash Access - RW */ | 808 | #define E1000_FLA 0x0001C /* Flash Access - RW */ |
889 | #define E1000_MDIC 0x00020 /* MDI Control - RW */ | 809 | #define E1000_MDIC 0x00020 /* MDI Control - RW */ |
890 | #define E1000_SCTL 0x00024 /* SerDes Control - RW */ | 810 | #define E1000_SCTL 0x00024 /* SerDes Control - RW */ |
891 | #define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */ | 811 | #define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */ |
892 | #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ | 812 | #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ |
893 | #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ | 813 | #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ |
894 | #define E1000_FCT 0x00030 /* Flow Control Type - RW */ | 814 | #define E1000_FCT 0x00030 /* Flow Control Type - RW */ |
895 | #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ | 815 | #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ |
896 | #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ | 816 | #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ |
897 | #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ | 817 | #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ |
898 | #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ | 818 | #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ |
899 | #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ | 819 | #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ |
900 | #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ | 820 | #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ |
901 | #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ | 821 | #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ |
902 | #define E1000_RCTL 0x00100 /* RX Control - RW */ | 822 | #define E1000_RCTL 0x00100 /* RX Control - RW */ |
903 | #define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */ | 823 | #define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */ |
904 | #define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */ | 824 | #define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */ |
905 | #define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */ | 825 | #define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */ |
906 | #define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */ | 826 | #define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */ |
907 | #define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */ | 827 | #define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */ |
908 | #define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */ | 828 | #define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */ |
909 | #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ | 829 | #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ |
910 | #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ | 830 | #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ |
911 | #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ | 831 | #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ |
912 | #define E1000_TCTL 0x00400 /* TX Control - RW */ | 832 | #define E1000_TCTL 0x00400 /* TX Control - RW */ |
913 | #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ | 833 | #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ |
914 | #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ | 834 | #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ |
915 | #define E1000_TBT 0x00448 /* TX Burst Timer - RW */ | 835 | #define E1000_TBT 0x00448 /* TX Burst Timer - RW */ |
916 | #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ | 836 | #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ |
917 | #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ | 837 | #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ |
918 | #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ | 838 | #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ |
919 | #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ | 839 | #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ |
920 | #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ | 840 | #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ |
921 | #define FEXTNVM_SW_CONFIG 0x0001 | 841 | #define FEXTNVM_SW_CONFIG 0x0001 |
922 | #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ | 842 | #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ |
923 | #define E1000_PBS 0x01008 /* Packet Buffer Size */ | 843 | #define E1000_PBS 0x01008 /* Packet Buffer Size */ |
924 | #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ | 844 | #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ |
925 | #define E1000_FLASH_UPDATES 1000 | 845 | #define E1000_FLASH_UPDATES 1000 |
926 | #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ | 846 | #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ |
927 | #define E1000_FLASHT 0x01028 /* FLASH Timer Register */ | 847 | #define E1000_FLASHT 0x01028 /* FLASH Timer Register */ |
928 | #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ | 848 | #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ |
929 | #define E1000_FLSWCTL 0x01030 /* FLASH control register */ | 849 | #define E1000_FLSWCTL 0x01030 /* FLASH control register */ |
930 | #define E1000_FLSWDATA 0x01034 /* FLASH data register */ | 850 | #define E1000_FLSWDATA 0x01034 /* FLASH data register */ |
931 | #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ | 851 | #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ |
932 | #define E1000_FLOP 0x0103C /* FLASH Opcode Register */ | 852 | #define E1000_FLOP 0x0103C /* FLASH Opcode Register */ |
933 | #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ | 853 | #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ |
934 | #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ | 854 | #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ |
935 | #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ | 855 | #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ |
936 | #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ | 856 | #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ |
937 | #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ | 857 | #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ |
938 | #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ | 858 | #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ |
939 | #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ | 859 | #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ |
940 | #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ | 860 | #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ |
941 | #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ | 861 | #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ |
942 | #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ | 862 | #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ |
943 | #define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */ | 863 | #define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */ |
944 | #define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */ | 864 | #define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */ |
945 | #define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */ | 865 | #define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */ |
946 | #define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */ | 866 | #define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */ |
947 | #define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */ | 867 | #define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */ |
948 | #define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */ | 868 | #define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */ |
949 | #define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */ | 869 | #define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */ |
950 | #define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */ | 870 | #define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */ |
951 | #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ | 871 | #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ |
952 | #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ | 872 | #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ |
953 | #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ | 873 | #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ |
954 | #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ | 874 | #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ |
955 | #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ | 875 | #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ |
956 | #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ | 876 | #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ |
957 | #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ | 877 | #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ |
958 | #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ | 878 | #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ |
959 | #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ | 879 | #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ |
960 | #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ | 880 | #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ |
961 | #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ | 881 | #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ |
962 | #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ | 882 | #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ |
963 | #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ | 883 | #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ |
964 | #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ | 884 | #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ |
965 | #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ | 885 | #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ |
966 | #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ | 886 | #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ |
967 | #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ | 887 | #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ |
968 | #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ | 888 | #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ |
969 | #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ | 889 | #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ |
970 | #define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ | 890 | #define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ |
971 | #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ | 891 | #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ |
972 | #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ | 892 | #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ |
973 | #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ | 893 | #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ |
974 | #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ | 894 | #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ |
975 | #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ | 895 | #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ |
976 | #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */ | 896 | #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */ |
977 | #define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ | 897 | #define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ |
978 | #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ | 898 | #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ |
979 | #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ | 899 | #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ |
980 | #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ | 900 | #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ |
981 | #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ | 901 | #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ |
982 | #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ | 902 | #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ |
983 | #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ | 903 | #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ |
984 | #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ | 904 | #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ |
985 | #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ | 905 | #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ |
986 | #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ | 906 | #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ |
987 | #define E1000_COLC 0x04028 /* Collision Count - R/clr */ | 907 | #define E1000_COLC 0x04028 /* Collision Count - R/clr */ |
988 | #define E1000_DC 0x04030 /* Defer Count - R/clr */ | 908 | #define E1000_DC 0x04030 /* Defer Count - R/clr */ |
989 | #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ | 909 | #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ |
990 | #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ | 910 | #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ |
991 | #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ | 911 | #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ |
992 | #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ | 912 | #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ |
993 | #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ | 913 | #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ |
994 | #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ | 914 | #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ |
995 | #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ | 915 | #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ |
996 | #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ | 916 | #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ |
997 | #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ | 917 | #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ |
998 | #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ | 918 | #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ |
999 | #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ | 919 | #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ |
1000 | #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ | 920 | #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ |
1001 | #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ | 921 | #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ |
1002 | #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ | 922 | #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ |
1003 | #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ | 923 | #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ |
1004 | #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ | 924 | #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ |
1005 | #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ | 925 | #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ |
1006 | #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ | 926 | #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ |
1007 | #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ | 927 | #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ |
1008 | #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ | 928 | #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ |
1009 | #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ | 929 | #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ |
1010 | #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ | 930 | #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ |
1011 | #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ | 931 | #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ |
1012 | #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ | 932 | #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ |
1013 | #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ | 933 | #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ |
1014 | #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ | 934 | #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ |
1015 | #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ | 935 | #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ |
1016 | #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ | 936 | #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ |
1017 | #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ | 937 | #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ |
1018 | #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ | 938 | #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ |
1019 | #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ | 939 | #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ |
1020 | #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ | 940 | #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ |
1021 | #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ | 941 | #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ |
1022 | #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ | 942 | #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ |
1023 | #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ | 943 | #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ |
1024 | #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ | 944 | #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ |
1025 | #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ | 945 | #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ |
1026 | #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ | 946 | #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ |
1027 | #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ | 947 | #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ |
1028 | #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ | 948 | #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ |
1029 | #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ | 949 | #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ |
1030 | #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ | 950 | #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ |
1031 | #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ | 951 | #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ |
1032 | #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ | 952 | #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ |
1033 | #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ | 953 | #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ |
1034 | #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ | 954 | #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ |
1035 | #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ | 955 | #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ |
1036 | #define E1000_IAC 0x04100 /* Interrupt Assertion Count */ | 956 | #define E1000_IAC 0x04100 /* Interrupt Assertion Count */ |
1037 | #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */ | 957 | #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */ |
1038 | #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */ | 958 | #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */ |
1039 | #define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */ | 959 | #define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */ |
1040 | #define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */ | 960 | #define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */ |
1041 | #define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ | 961 | #define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ |
1042 | #define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */ | 962 | #define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */ |
1043 | #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */ | 963 | #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */ |
1044 | #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ | 964 | #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ |
1045 | #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ | 965 | #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ |
1046 | #define E1000_RFCTL 0x05008 /* Receive Filter Control*/ | 966 | #define E1000_RFCTL 0x05008 /* Receive Filter Control */ |
1047 | #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ | 967 | #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ |
1048 | #define E1000_RA 0x05400 /* Receive Address - RW Array */ | 968 | #define E1000_RA 0x05400 /* Receive Address - RW Array */ |
1049 | #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ | 969 | #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ |
1050 | #define E1000_WUC 0x05800 /* Wakeup Control - RW */ | 970 | #define E1000_WUC 0x05800 /* Wakeup Control - RW */ |
1051 | #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ | 971 | #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ |
1052 | #define E1000_WUS 0x05810 /* Wakeup Status - RO */ | 972 | #define E1000_WUS 0x05810 /* Wakeup Status - RO */ |
1053 | #define E1000_MANC 0x05820 /* Management Control - RW */ | 973 | #define E1000_MANC 0x05820 /* Management Control - RW */ |
1054 | #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ | 974 | #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ |
1055 | #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ | 975 | #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ |
1056 | #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ | 976 | #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ |
1057 | #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ | 977 | #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ |
1058 | #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ | 978 | #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ |
1059 | #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ | 979 | #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ |
1060 | #define E1000_HOST_IF 0x08800 /* Host Interface */ | 980 | #define E1000_HOST_IF 0x08800 /* Host Interface */ |
1061 | #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ | 981 | #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ |
1062 | #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ | 982 | #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ |
1063 | 983 | ||
1064 | #define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */ | 984 | #define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */ |
1065 | #define E1000_MDPHYA 0x0003C /* PHY address - RW */ | 985 | #define E1000_MDPHYA 0x0003C /* PHY address - RW */ |
1066 | #define E1000_MANC2H 0x05860 /* Managment Control To Host - RW */ | 986 | #define E1000_MANC2H 0x05860 /* Managment Control To Host - RW */ |
1067 | #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ | 987 | #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ |
1068 | 988 | ||
1069 | #define E1000_GCR 0x05B00 /* PCI-Ex Control */ | 989 | #define E1000_GCR 0x05B00 /* PCI-Ex Control */ |
1070 | #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ | 990 | #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ |
1071 | #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ | 991 | #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ |
1072 | #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ | 992 | #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ |
1073 | #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ | 993 | #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ |
1074 | #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ | 994 | #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ |
1075 | #define E1000_SWSM 0x05B50 /* SW Semaphore */ | 995 | #define E1000_SWSM 0x05B50 /* SW Semaphore */ |
1076 | #define E1000_FWSM 0x05B54 /* FW Semaphore */ | 996 | #define E1000_FWSM 0x05B54 /* FW Semaphore */ |
1077 | #define E1000_FFLT_DBG 0x05F04 /* Debug Register */ | 997 | #define E1000_FFLT_DBG 0x05F04 /* Debug Register */ |
1078 | #define E1000_HICR 0x08F00 /* Host Inteface Control */ | 998 | #define E1000_HICR 0x08F00 /* Host Interface Control */ |
1079 | 999 | ||
1080 | /* RSS registers */ | 1000 | /* RSS registers */ |
1081 | #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ | 1001 | #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ |
1082 | #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ | 1002 | #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ |
1083 | #define E1000_RETA 0x05C00 /* Redirection Table - RW Array */ | 1003 | #define E1000_RETA 0x05C00 /* Redirection Table - RW Array */ |
1084 | #define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */ | 1004 | #define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */ |
1085 | #define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ | 1005 | #define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ |
1086 | #define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ | 1006 | #define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ |
1087 | /* Register Set (82542) | 1007 | /* Register Set (82542) |
1088 | * | 1008 | * |
1089 | * Some of the 82542 registers are located at different offsets than they are | 1009 | * Some of the 82542 registers are located at different offsets than they are |
@@ -1123,19 +1043,19 @@ struct e1000_ffvt_entry { | |||
1123 | #define E1000_82542_RDLEN0 E1000_82542_RDLEN | 1043 | #define E1000_82542_RDLEN0 E1000_82542_RDLEN |
1124 | #define E1000_82542_RDH0 E1000_82542_RDH | 1044 | #define E1000_82542_RDH0 E1000_82542_RDH |
1125 | #define E1000_82542_RDT0 E1000_82542_RDT | 1045 | #define E1000_82542_RDT0 E1000_82542_RDT |
1126 | #define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication | 1046 | #define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication |
1127 | * RX Control - RW */ | 1047 | * RX Control - RW */ |
1128 | #define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8)) | 1048 | #define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8)) |
1129 | #define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */ | 1049 | #define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */ |
1130 | #define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */ | 1050 | #define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */ |
1131 | #define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */ | 1051 | #define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */ |
1132 | #define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */ | 1052 | #define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */ |
1133 | #define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */ | 1053 | #define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */ |
1134 | #define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */ | 1054 | #define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */ |
1135 | #define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */ | 1055 | #define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */ |
1136 | #define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */ | 1056 | #define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */ |
1137 | #define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */ | 1057 | #define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */ |
1138 | #define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */ | 1058 | #define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */ |
1139 | #define E1000_82542_RDTR1 0x00130 | 1059 | #define E1000_82542_RDTR1 0x00130 |
1140 | #define E1000_82542_RDBAL1 0x00138 | 1060 | #define E1000_82542_RDBAL1 0x00138 |
1141 | #define E1000_82542_RDBAH1 0x0013C | 1061 | #define E1000_82542_RDBAH1 0x0013C |
@@ -1302,288 +1222,281 @@ struct e1000_ffvt_entry { | |||
1302 | #define E1000_82542_RSSIR E1000_RSSIR | 1222 | #define E1000_82542_RSSIR E1000_RSSIR |
1303 | #define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA | 1223 | #define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA |
1304 | #define E1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC | 1224 | #define E1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC |
1305 | #define E1000_82542_MANC2H E1000_MANC2H | ||
1306 | 1225 | ||
1307 | /* Statistics counters collected by the MAC */ | 1226 | /* Statistics counters collected by the MAC */ |
1308 | struct e1000_hw_stats { | 1227 | struct e1000_hw_stats { |
1309 | u64 crcerrs; | 1228 | u64 crcerrs; |
1310 | u64 algnerrc; | 1229 | u64 algnerrc; |
1311 | u64 symerrs; | 1230 | u64 symerrs; |
1312 | u64 rxerrc; | 1231 | u64 rxerrc; |
1313 | u64 txerrc; | 1232 | u64 txerrc; |
1314 | u64 mpc; | 1233 | u64 mpc; |
1315 | u64 scc; | 1234 | u64 scc; |
1316 | u64 ecol; | 1235 | u64 ecol; |
1317 | u64 mcc; | 1236 | u64 mcc; |
1318 | u64 latecol; | 1237 | u64 latecol; |
1319 | u64 colc; | 1238 | u64 colc; |
1320 | u64 dc; | 1239 | u64 dc; |
1321 | u64 tncrs; | 1240 | u64 tncrs; |
1322 | u64 sec; | 1241 | u64 sec; |
1323 | u64 cexterr; | 1242 | u64 cexterr; |
1324 | u64 rlec; | 1243 | u64 rlec; |
1325 | u64 xonrxc; | 1244 | u64 xonrxc; |
1326 | u64 xontxc; | 1245 | u64 xontxc; |
1327 | u64 xoffrxc; | 1246 | u64 xoffrxc; |
1328 | u64 xofftxc; | 1247 | u64 xofftxc; |
1329 | u64 fcruc; | 1248 | u64 fcruc; |
1330 | u64 prc64; | 1249 | u64 prc64; |
1331 | u64 prc127; | 1250 | u64 prc127; |
1332 | u64 prc255; | 1251 | u64 prc255; |
1333 | u64 prc511; | 1252 | u64 prc511; |
1334 | u64 prc1023; | 1253 | u64 prc1023; |
1335 | u64 prc1522; | 1254 | u64 prc1522; |
1336 | u64 gprc; | 1255 | u64 gprc; |
1337 | u64 bprc; | 1256 | u64 bprc; |
1338 | u64 mprc; | 1257 | u64 mprc; |
1339 | u64 gptc; | 1258 | u64 gptc; |
1340 | u64 gorcl; | 1259 | u64 gorcl; |
1341 | u64 gorch; | 1260 | u64 gorch; |
1342 | u64 gotcl; | 1261 | u64 gotcl; |
1343 | u64 gotch; | 1262 | u64 gotch; |
1344 | u64 rnbc; | 1263 | u64 rnbc; |
1345 | u64 ruc; | 1264 | u64 ruc; |
1346 | u64 rfc; | 1265 | u64 rfc; |
1347 | u64 roc; | 1266 | u64 roc; |
1348 | u64 rlerrc; | 1267 | u64 rlerrc; |
1349 | u64 rjc; | 1268 | u64 rjc; |
1350 | u64 mgprc; | 1269 | u64 mgprc; |
1351 | u64 mgpdc; | 1270 | u64 mgpdc; |
1352 | u64 mgptc; | 1271 | u64 mgptc; |
1353 | u64 torl; | 1272 | u64 torl; |
1354 | u64 torh; | 1273 | u64 torh; |
1355 | u64 totl; | 1274 | u64 totl; |
1356 | u64 toth; | 1275 | u64 toth; |
1357 | u64 tpr; | 1276 | u64 tpr; |
1358 | u64 tpt; | 1277 | u64 tpt; |
1359 | u64 ptc64; | 1278 | u64 ptc64; |
1360 | u64 ptc127; | 1279 | u64 ptc127; |
1361 | u64 ptc255; | 1280 | u64 ptc255; |
1362 | u64 ptc511; | 1281 | u64 ptc511; |
1363 | u64 ptc1023; | 1282 | u64 ptc1023; |
1364 | u64 ptc1522; | 1283 | u64 ptc1522; |
1365 | u64 mptc; | 1284 | u64 mptc; |
1366 | u64 bptc; | 1285 | u64 bptc; |
1367 | u64 tsctc; | 1286 | u64 tsctc; |
1368 | u64 tsctfc; | 1287 | u64 tsctfc; |
1369 | u64 iac; | 1288 | u64 iac; |
1370 | u64 icrxptc; | 1289 | u64 icrxptc; |
1371 | u64 icrxatc; | 1290 | u64 icrxatc; |
1372 | u64 ictxptc; | 1291 | u64 ictxptc; |
1373 | u64 ictxatc; | 1292 | u64 ictxatc; |
1374 | u64 ictxqec; | 1293 | u64 ictxqec; |
1375 | u64 ictxqmtc; | 1294 | u64 ictxqmtc; |
1376 | u64 icrxdmtc; | 1295 | u64 icrxdmtc; |
1377 | u64 icrxoc; | 1296 | u64 icrxoc; |
1378 | }; | 1297 | }; |
1379 | 1298 | ||
1380 | /* Structure containing variables used by the shared code (e1000_hw.c) */ | 1299 | /* Structure containing variables used by the shared code (e1000_hw.c) */ |
1381 | struct e1000_hw { | 1300 | struct e1000_hw { |
1382 | u8 __iomem *hw_addr; | 1301 | u8 __iomem *hw_addr; |
1383 | u8 __iomem *flash_address; | 1302 | u8 __iomem *flash_address; |
1384 | e1000_mac_type mac_type; | 1303 | e1000_mac_type mac_type; |
1385 | e1000_phy_type phy_type; | 1304 | e1000_phy_type phy_type; |
1386 | u32 phy_init_script; | 1305 | u32 phy_init_script; |
1387 | e1000_media_type media_type; | 1306 | e1000_media_type media_type; |
1388 | void *back; | 1307 | void *back; |
1389 | struct e1000_shadow_ram *eeprom_shadow_ram; | 1308 | struct e1000_shadow_ram *eeprom_shadow_ram; |
1390 | u32 flash_bank_size; | 1309 | u32 flash_bank_size; |
1391 | u32 flash_base_addr; | 1310 | u32 flash_base_addr; |
1392 | e1000_fc_type fc; | 1311 | e1000_fc_type fc; |
1393 | e1000_bus_speed bus_speed; | 1312 | e1000_bus_speed bus_speed; |
1394 | e1000_bus_width bus_width; | 1313 | e1000_bus_width bus_width; |
1395 | e1000_bus_type bus_type; | 1314 | e1000_bus_type bus_type; |
1396 | struct e1000_eeprom_info eeprom; | 1315 | struct e1000_eeprom_info eeprom; |
1397 | e1000_ms_type master_slave; | 1316 | e1000_ms_type master_slave; |
1398 | e1000_ms_type original_master_slave; | 1317 | e1000_ms_type original_master_slave; |
1399 | e1000_ffe_config ffe_config_state; | 1318 | e1000_ffe_config ffe_config_state; |
1400 | u32 asf_firmware_present; | 1319 | u32 asf_firmware_present; |
1401 | u32 eeprom_semaphore_present; | 1320 | u32 eeprom_semaphore_present; |
1402 | u32 swfw_sync_present; | 1321 | unsigned long io_base; |
1403 | u32 swfwhw_semaphore_present; | 1322 | u32 phy_id; |
1404 | unsigned long io_base; | 1323 | u32 phy_revision; |
1405 | u32 phy_id; | 1324 | u32 phy_addr; |
1406 | u32 phy_revision; | 1325 | u32 original_fc; |
1407 | u32 phy_addr; | 1326 | u32 txcw; |
1408 | u32 original_fc; | 1327 | u32 autoneg_failed; |
1409 | u32 txcw; | 1328 | u32 max_frame_size; |
1410 | u32 autoneg_failed; | 1329 | u32 min_frame_size; |
1411 | u32 max_frame_size; | 1330 | u32 mc_filter_type; |
1412 | u32 min_frame_size; | 1331 | u32 num_mc_addrs; |
1413 | u32 mc_filter_type; | 1332 | u32 collision_delta; |
1414 | u32 num_mc_addrs; | 1333 | u32 tx_packet_delta; |
1415 | u32 collision_delta; | 1334 | u32 ledctl_default; |
1416 | u32 tx_packet_delta; | 1335 | u32 ledctl_mode1; |
1417 | u32 ledctl_default; | 1336 | u32 ledctl_mode2; |
1418 | u32 ledctl_mode1; | 1337 | bool tx_pkt_filtering; |
1419 | u32 ledctl_mode2; | ||
1420 | bool tx_pkt_filtering; | ||
1421 | struct e1000_host_mng_dhcp_cookie mng_cookie; | 1338 | struct e1000_host_mng_dhcp_cookie mng_cookie; |
1422 | u16 phy_spd_default; | 1339 | u16 phy_spd_default; |
1423 | u16 autoneg_advertised; | 1340 | u16 autoneg_advertised; |
1424 | u16 pci_cmd_word; | 1341 | u16 pci_cmd_word; |
1425 | u16 fc_high_water; | 1342 | u16 fc_high_water; |
1426 | u16 fc_low_water; | 1343 | u16 fc_low_water; |
1427 | u16 fc_pause_time; | 1344 | u16 fc_pause_time; |
1428 | u16 current_ifs_val; | 1345 | u16 current_ifs_val; |
1429 | u16 ifs_min_val; | 1346 | u16 ifs_min_val; |
1430 | u16 ifs_max_val; | 1347 | u16 ifs_max_val; |
1431 | u16 ifs_step_size; | 1348 | u16 ifs_step_size; |
1432 | u16 ifs_ratio; | 1349 | u16 ifs_ratio; |
1433 | u16 device_id; | 1350 | u16 device_id; |
1434 | u16 vendor_id; | 1351 | u16 vendor_id; |
1435 | u16 subsystem_id; | 1352 | u16 subsystem_id; |
1436 | u16 subsystem_vendor_id; | 1353 | u16 subsystem_vendor_id; |
1437 | u8 revision_id; | 1354 | u8 revision_id; |
1438 | u8 autoneg; | 1355 | u8 autoneg; |
1439 | u8 mdix; | 1356 | u8 mdix; |
1440 | u8 forced_speed_duplex; | 1357 | u8 forced_speed_duplex; |
1441 | u8 wait_autoneg_complete; | 1358 | u8 wait_autoneg_complete; |
1442 | u8 dma_fairness; | 1359 | u8 dma_fairness; |
1443 | u8 mac_addr[NODE_ADDRESS_SIZE]; | 1360 | u8 mac_addr[NODE_ADDRESS_SIZE]; |
1444 | u8 perm_mac_addr[NODE_ADDRESS_SIZE]; | 1361 | u8 perm_mac_addr[NODE_ADDRESS_SIZE]; |
1445 | bool disable_polarity_correction; | 1362 | bool disable_polarity_correction; |
1446 | bool speed_downgraded; | 1363 | bool speed_downgraded; |
1447 | e1000_smart_speed smart_speed; | 1364 | e1000_smart_speed smart_speed; |
1448 | e1000_dsp_config dsp_config_state; | 1365 | e1000_dsp_config dsp_config_state; |
1449 | bool get_link_status; | 1366 | bool get_link_status; |
1450 | bool serdes_link_down; | 1367 | bool serdes_has_link; |
1451 | bool tbi_compatibility_en; | 1368 | bool tbi_compatibility_en; |
1452 | bool tbi_compatibility_on; | 1369 | bool tbi_compatibility_on; |
1453 | bool laa_is_present; | 1370 | bool laa_is_present; |
1454 | bool phy_reset_disable; | 1371 | bool phy_reset_disable; |
1455 | bool initialize_hw_bits_disable; | 1372 | bool initialize_hw_bits_disable; |
1456 | bool fc_send_xon; | 1373 | bool fc_send_xon; |
1457 | bool fc_strict_ieee; | 1374 | bool fc_strict_ieee; |
1458 | bool report_tx_early; | 1375 | bool report_tx_early; |
1459 | bool adaptive_ifs; | 1376 | bool adaptive_ifs; |
1460 | bool ifs_params_forced; | 1377 | bool ifs_params_forced; |
1461 | bool in_ifs_mode; | 1378 | bool in_ifs_mode; |
1462 | bool mng_reg_access_disabled; | 1379 | bool mng_reg_access_disabled; |
1463 | bool leave_av_bit_off; | 1380 | bool leave_av_bit_off; |
1464 | bool kmrn_lock_loss_workaround_disabled; | 1381 | bool bad_tx_carr_stats_fd; |
1465 | bool bad_tx_carr_stats_fd; | 1382 | bool has_smbus; |
1466 | bool has_manc2h; | ||
1467 | bool rx_needs_kicking; | ||
1468 | bool has_smbus; | ||
1469 | }; | 1383 | }; |
1470 | 1384 | ||
1471 | 1385 | #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ | |
1472 | #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ | 1386 | #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ |
1473 | #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ | 1387 | #define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */ |
1474 | #define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */ | 1388 | #define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ |
1475 | #define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ | 1389 | #define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */ |
1476 | #define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */ | 1390 | #define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ |
1477 | #define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ | 1391 | #define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */ |
1478 | #define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */ | 1392 | #define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */ |
1479 | #define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */ | ||
1480 | /* Register Bit Masks */ | 1393 | /* Register Bit Masks */ |
1481 | /* Device Control */ | 1394 | /* Device Control */ |
1482 | #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ | 1395 | #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ |
1483 | #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ | 1396 | #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ |
1484 | #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ | 1397 | #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ |
1485 | #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ | 1398 | #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ |
1486 | #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ | 1399 | #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ |
1487 | #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ | 1400 | #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ |
1488 | #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ | 1401 | #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ |
1489 | #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ | 1402 | #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ |
1490 | #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ | 1403 | #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ |
1491 | #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ | 1404 | #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ |
1492 | #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ | 1405 | #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ |
1493 | #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ | 1406 | #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ |
1494 | #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ | 1407 | #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ |
1495 | #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ | 1408 | #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ |
1496 | #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ | 1409 | #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ |
1497 | #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ | 1410 | #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ |
1498 | #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ | 1411 | #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ |
1499 | #define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ | 1412 | #define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ |
1500 | #define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */ | 1413 | #define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */ |
1501 | #define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */ | 1414 | #define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */ |
1502 | #define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */ | 1415 | #define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */ |
1503 | #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ | 1416 | #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ |
1504 | #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ | 1417 | #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ |
1505 | #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ | 1418 | #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ |
1506 | #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ | 1419 | #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ |
1507 | #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ | 1420 | #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ |
1508 | #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ | 1421 | #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ |
1509 | #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ | 1422 | #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ |
1510 | #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ | 1423 | #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ |
1511 | #define E1000_CTRL_RST 0x04000000 /* Global reset */ | 1424 | #define E1000_CTRL_RST 0x04000000 /* Global reset */ |
1512 | #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ | 1425 | #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ |
1513 | #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ | 1426 | #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ |
1514 | #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ | 1427 | #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ |
1515 | #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ | 1428 | #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ |
1516 | #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ | 1429 | #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ |
1517 | #define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */ | 1430 | #define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */ |
1518 | 1431 | ||
1519 | /* Device Status */ | 1432 | /* Device Status */ |
1520 | #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ | 1433 | #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ |
1521 | #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ | 1434 | #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ |
1522 | #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ | 1435 | #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ |
1523 | #define E1000_STATUS_FUNC_SHIFT 2 | 1436 | #define E1000_STATUS_FUNC_SHIFT 2 |
1524 | #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ | 1437 | #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ |
1525 | #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ | 1438 | #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ |
1526 | #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ | 1439 | #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ |
1527 | #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ | 1440 | #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ |
1528 | #define E1000_STATUS_SPEED_MASK 0x000000C0 | 1441 | #define E1000_STATUS_SPEED_MASK 0x000000C0 |
1529 | #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ | 1442 | #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ |
1530 | #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ | 1443 | #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ |
1531 | #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ | 1444 | #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ |
1532 | #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion | 1445 | #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion |
1533 | by EEPROM/Flash */ | 1446 | by EEPROM/Flash */ |
1534 | #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ | 1447 | #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ |
1535 | #define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */ | 1448 | #define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */ |
1536 | #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ | 1449 | #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ |
1537 | #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ | 1450 | #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ |
1538 | #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ | 1451 | #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ |
1539 | #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ | 1452 | #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ |
1540 | #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ | 1453 | #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ |
1541 | #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ | 1454 | #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ |
1542 | #define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ | 1455 | #define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ |
1543 | #define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ | 1456 | #define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ |
1544 | #define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ | 1457 | #define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ |
1545 | #define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ | 1458 | #define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ |
1546 | #define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */ | 1459 | #define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */ |
1547 | #define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ | 1460 | #define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ |
1548 | #define E1000_STATUS_FUSE_8 0x04000000 | 1461 | #define E1000_STATUS_FUSE_8 0x04000000 |
1549 | #define E1000_STATUS_FUSE_9 0x08000000 | 1462 | #define E1000_STATUS_FUSE_9 0x08000000 |
1550 | #define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ | 1463 | #define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ |
1551 | #define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ | 1464 | #define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ |
1552 | 1465 | ||
1553 | /* Constants used to intrepret the masked PCI-X bus speed. */ | 1466 | /* Constants used to interpret the masked PCI-X bus speed. */ |
1554 | #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ | 1467 | #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ |
1555 | #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ | 1468 | #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ |
1556 | #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ | 1469 | #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ |
1557 | 1470 | ||
1558 | /* EEPROM/Flash Control */ | 1471 | /* EEPROM/Flash Control */ |
1559 | #define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ | 1472 | #define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ |
1560 | #define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ | 1473 | #define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ |
1561 | #define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ | 1474 | #define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ |
1562 | #define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ | 1475 | #define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ |
1563 | #define E1000_EECD_FWE_MASK 0x00000030 | 1476 | #define E1000_EECD_FWE_MASK 0x00000030 |
1564 | #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ | 1477 | #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ |
1565 | #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ | 1478 | #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ |
1566 | #define E1000_EECD_FWE_SHIFT 4 | 1479 | #define E1000_EECD_FWE_SHIFT 4 |
1567 | #define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ | 1480 | #define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ |
1568 | #define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ | 1481 | #define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ |
1569 | #define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ | 1482 | #define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ |
1570 | #define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ | 1483 | #define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ |
1571 | #define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type | 1484 | #define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type |
1572 | * (0-small, 1-large) */ | 1485 | * (0-small, 1-large) */ |
1573 | #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */ | 1486 | #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */ |
1574 | #ifndef E1000_EEPROM_GRANT_ATTEMPTS | 1487 | #ifndef E1000_EEPROM_GRANT_ATTEMPTS |
1575 | #define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ | 1488 | #define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ |
1576 | #endif | 1489 | #endif |
1577 | #define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */ | 1490 | #define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */ |
1578 | #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */ | 1491 | #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */ |
1579 | #define E1000_EECD_SIZE_EX_SHIFT 11 | 1492 | #define E1000_EECD_SIZE_EX_SHIFT 11 |
1580 | #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ | 1493 | #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ |
1581 | #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ | 1494 | #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ |
1582 | #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ | 1495 | #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ |
1583 | #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ | 1496 | #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ |
1584 | #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ | 1497 | #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ |
1585 | #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ | 1498 | #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ |
1586 | #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ | 1499 | #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ |
1587 | #define E1000_EECD_SECVAL_SHIFT 22 | 1500 | #define E1000_EECD_SECVAL_SHIFT 22 |
1588 | #define E1000_STM_OPCODE 0xDB00 | 1501 | #define E1000_STM_OPCODE 0xDB00 |
1589 | #define E1000_HICR_FW_RESET 0xC0 | 1502 | #define E1000_HICR_FW_RESET 0xC0 |
@@ -1593,12 +1506,12 @@ struct e1000_hw { | |||
1593 | #define E1000_ICH_NVM_SIG_MASK 0xC0 | 1506 | #define E1000_ICH_NVM_SIG_MASK 0xC0 |
1594 | 1507 | ||
1595 | /* EEPROM Read */ | 1508 | /* EEPROM Read */ |
1596 | #define E1000_EERD_START 0x00000001 /* Start Read */ | 1509 | #define E1000_EERD_START 0x00000001 /* Start Read */ |
1597 | #define E1000_EERD_DONE 0x00000010 /* Read Done */ | 1510 | #define E1000_EERD_DONE 0x00000010 /* Read Done */ |
1598 | #define E1000_EERD_ADDR_SHIFT 8 | 1511 | #define E1000_EERD_ADDR_SHIFT 8 |
1599 | #define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */ | 1512 | #define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */ |
1600 | #define E1000_EERD_DATA_SHIFT 16 | 1513 | #define E1000_EERD_DATA_SHIFT 16 |
1601 | #define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */ | 1514 | #define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */ |
1602 | 1515 | ||
1603 | /* SPI EEPROM Status Register */ | 1516 | /* SPI EEPROM Status Register */ |
1604 | #define EEPROM_STATUS_RDY_SPI 0x01 | 1517 | #define EEPROM_STATUS_RDY_SPI 0x01 |
@@ -1608,25 +1521,25 @@ struct e1000_hw { | |||
1608 | #define EEPROM_STATUS_WPEN_SPI 0x80 | 1521 | #define EEPROM_STATUS_WPEN_SPI 0x80 |
1609 | 1522 | ||
1610 | /* Extended Device Control */ | 1523 | /* Extended Device Control */ |
1611 | #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ | 1524 | #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ |
1612 | #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ | 1525 | #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ |
1613 | #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN | 1526 | #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN |
1614 | #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ | 1527 | #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ |
1615 | #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ | 1528 | #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ |
1616 | #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ | 1529 | #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ |
1617 | #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ | 1530 | #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ |
1618 | #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA | 1531 | #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA |
1619 | #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ | 1532 | #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ |
1620 | #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ | 1533 | #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ |
1621 | #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ | 1534 | #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ |
1622 | #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ | 1535 | #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ |
1623 | #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ | 1536 | #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ |
1624 | #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ | 1537 | #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ |
1625 | #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ | 1538 | #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ |
1626 | #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ | 1539 | #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ |
1627 | #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ | 1540 | #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ |
1628 | #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ | 1541 | #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ |
1629 | #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ | 1542 | #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ |
1630 | #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 | 1543 | #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 |
1631 | #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 | 1544 | #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 |
1632 | #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 | 1545 | #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 |
@@ -1638,11 +1551,11 @@ struct e1000_hw { | |||
1638 | #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 | 1551 | #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 |
1639 | #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 | 1552 | #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 |
1640 | #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 | 1553 | #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 |
1641 | #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ | 1554 | #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ |
1642 | #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ | 1555 | #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ |
1643 | #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ | 1556 | #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ |
1644 | #define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */ | 1557 | #define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */ |
1645 | #define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */ | 1558 | #define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */ |
1646 | #define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 | 1559 | #define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 |
1647 | 1560 | ||
1648 | /* MDI Control */ | 1561 | /* MDI Control */ |
@@ -1742,167 +1655,167 @@ struct e1000_hw { | |||
1742 | #define E1000_LEDCTL_MODE_LED_OFF 0xF | 1655 | #define E1000_LEDCTL_MODE_LED_OFF 0xF |
1743 | 1656 | ||
1744 | /* Receive Address */ | 1657 | /* Receive Address */ |
1745 | #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ | 1658 | #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ |
1746 | 1659 | ||
1747 | /* Interrupt Cause Read */ | 1660 | /* Interrupt Cause Read */ |
1748 | #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ | 1661 | #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ |
1749 | #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ | 1662 | #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ |
1750 | #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ | 1663 | #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ |
1751 | #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ | 1664 | #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ |
1752 | #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ | 1665 | #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ |
1753 | #define E1000_ICR_RXO 0x00000040 /* rx overrun */ | 1666 | #define E1000_ICR_RXO 0x00000040 /* rx overrun */ |
1754 | #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ | 1667 | #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ |
1755 | #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ | 1668 | #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ |
1756 | #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ | 1669 | #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ |
1757 | #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ | 1670 | #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ |
1758 | #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ | 1671 | #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ |
1759 | #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ | 1672 | #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ |
1760 | #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ | 1673 | #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ |
1761 | #define E1000_ICR_TXD_LOW 0x00008000 | 1674 | #define E1000_ICR_TXD_LOW 0x00008000 |
1762 | #define E1000_ICR_SRPD 0x00010000 | 1675 | #define E1000_ICR_SRPD 0x00010000 |
1763 | #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ | 1676 | #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ |
1764 | #define E1000_ICR_MNG 0x00040000 /* Manageability event */ | 1677 | #define E1000_ICR_MNG 0x00040000 /* Manageability event */ |
1765 | #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ | 1678 | #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ |
1766 | #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ | 1679 | #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ |
1767 | #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */ | 1680 | #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */ |
1768 | #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */ | 1681 | #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */ |
1769 | #define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */ | 1682 | #define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */ |
1770 | #define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ | 1683 | #define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ |
1771 | #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */ | 1684 | #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */ |
1772 | #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */ | 1685 | #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */ |
1773 | #define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ | 1686 | #define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ |
1774 | #define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */ | 1687 | #define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */ |
1775 | #define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */ | 1688 | #define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */ |
1776 | #define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */ | 1689 | #define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */ |
1777 | 1690 | ||
1778 | /* Interrupt Cause Set */ | 1691 | /* Interrupt Cause Set */ |
1779 | #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ | 1692 | #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ |
1780 | #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ | 1693 | #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ |
1781 | #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ | 1694 | #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ |
1782 | #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ | 1695 | #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ |
1783 | #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ | 1696 | #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ |
1784 | #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ | 1697 | #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ |
1785 | #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ | 1698 | #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ |
1786 | #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ | 1699 | #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ |
1787 | #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ | 1700 | #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ |
1788 | #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ | 1701 | #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ |
1789 | #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ | 1702 | #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ |
1790 | #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ | 1703 | #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ |
1791 | #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ | 1704 | #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ |
1792 | #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW | 1705 | #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW |
1793 | #define E1000_ICS_SRPD E1000_ICR_SRPD | 1706 | #define E1000_ICS_SRPD E1000_ICR_SRPD |
1794 | #define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ | 1707 | #define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ |
1795 | #define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ | 1708 | #define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ |
1796 | #define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ | 1709 | #define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ |
1797 | #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ | 1710 | #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ |
1798 | #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ | 1711 | #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ |
1799 | #define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ | 1712 | #define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ |
1800 | #define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ | 1713 | #define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ |
1801 | #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ | 1714 | #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ |
1802 | #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ | 1715 | #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ |
1803 | #define E1000_ICS_DSW E1000_ICR_DSW | 1716 | #define E1000_ICS_DSW E1000_ICR_DSW |
1804 | #define E1000_ICS_PHYINT E1000_ICR_PHYINT | 1717 | #define E1000_ICS_PHYINT E1000_ICR_PHYINT |
1805 | #define E1000_ICS_EPRST E1000_ICR_EPRST | 1718 | #define E1000_ICS_EPRST E1000_ICR_EPRST |
1806 | 1719 | ||
1807 | /* Interrupt Mask Set */ | 1720 | /* Interrupt Mask Set */ |
1808 | #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ | 1721 | #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ |
1809 | #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ | 1722 | #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ |
1810 | #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ | 1723 | #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ |
1811 | #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ | 1724 | #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ |
1812 | #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ | 1725 | #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ |
1813 | #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ | 1726 | #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ |
1814 | #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ | 1727 | #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ |
1815 | #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ | 1728 | #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ |
1816 | #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ | 1729 | #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ |
1817 | #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ | 1730 | #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ |
1818 | #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ | 1731 | #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ |
1819 | #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ | 1732 | #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ |
1820 | #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ | 1733 | #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ |
1821 | #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW | 1734 | #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW |
1822 | #define E1000_IMS_SRPD E1000_ICR_SRPD | 1735 | #define E1000_IMS_SRPD E1000_ICR_SRPD |
1823 | #define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ | 1736 | #define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ |
1824 | #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ | 1737 | #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ |
1825 | #define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ | 1738 | #define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ |
1826 | #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ | 1739 | #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ |
1827 | #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ | 1740 | #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ |
1828 | #define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ | 1741 | #define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ |
1829 | #define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ | 1742 | #define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ |
1830 | #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ | 1743 | #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ |
1831 | #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ | 1744 | #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ |
1832 | #define E1000_IMS_DSW E1000_ICR_DSW | 1745 | #define E1000_IMS_DSW E1000_ICR_DSW |
1833 | #define E1000_IMS_PHYINT E1000_ICR_PHYINT | 1746 | #define E1000_IMS_PHYINT E1000_ICR_PHYINT |
1834 | #define E1000_IMS_EPRST E1000_ICR_EPRST | 1747 | #define E1000_IMS_EPRST E1000_ICR_EPRST |
1835 | 1748 | ||
1836 | /* Interrupt Mask Clear */ | 1749 | /* Interrupt Mask Clear */ |
1837 | #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ | 1750 | #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ |
1838 | #define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ | 1751 | #define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ |
1839 | #define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ | 1752 | #define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ |
1840 | #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ | 1753 | #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ |
1841 | #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ | 1754 | #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ |
1842 | #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ | 1755 | #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ |
1843 | #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ | 1756 | #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ |
1844 | #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ | 1757 | #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ |
1845 | #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ | 1758 | #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ |
1846 | #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ | 1759 | #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ |
1847 | #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ | 1760 | #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ |
1848 | #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ | 1761 | #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ |
1849 | #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ | 1762 | #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ |
1850 | #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW | 1763 | #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW |
1851 | #define E1000_IMC_SRPD E1000_ICR_SRPD | 1764 | #define E1000_IMC_SRPD E1000_ICR_SRPD |
1852 | #define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */ | 1765 | #define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */ |
1853 | #define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */ | 1766 | #define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */ |
1854 | #define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */ | 1767 | #define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */ |
1855 | #define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ | 1768 | #define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ |
1856 | #define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ | 1769 | #define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ |
1857 | #define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ | 1770 | #define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ |
1858 | #define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ | 1771 | #define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ |
1859 | #define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ | 1772 | #define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ |
1860 | #define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ | 1773 | #define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ |
1861 | #define E1000_IMC_DSW E1000_ICR_DSW | 1774 | #define E1000_IMC_DSW E1000_ICR_DSW |
1862 | #define E1000_IMC_PHYINT E1000_ICR_PHYINT | 1775 | #define E1000_IMC_PHYINT E1000_ICR_PHYINT |
1863 | #define E1000_IMC_EPRST E1000_ICR_EPRST | 1776 | #define E1000_IMC_EPRST E1000_ICR_EPRST |
1864 | 1777 | ||
1865 | /* Receive Control */ | 1778 | /* Receive Control */ |
1866 | #define E1000_RCTL_RST 0x00000001 /* Software reset */ | 1779 | #define E1000_RCTL_RST 0x00000001 /* Software reset */ |
1867 | #define E1000_RCTL_EN 0x00000002 /* enable */ | 1780 | #define E1000_RCTL_EN 0x00000002 /* enable */ |
1868 | #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ | 1781 | #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ |
1869 | #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ | 1782 | #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ |
1870 | #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ | 1783 | #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ |
1871 | #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ | 1784 | #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ |
1872 | #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ | 1785 | #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ |
1873 | #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ | 1786 | #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ |
1874 | #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ | 1787 | #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ |
1875 | #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ | 1788 | #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ |
1876 | #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ | 1789 | #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ |
1877 | #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ | 1790 | #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ |
1878 | #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ | 1791 | #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ |
1879 | #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ | 1792 | #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ |
1880 | #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ | 1793 | #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ |
1881 | #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ | 1794 | #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ |
1882 | #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ | 1795 | #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ |
1883 | #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ | 1796 | #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ |
1884 | #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ | 1797 | #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ |
1885 | #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ | 1798 | #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ |
1886 | #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ | 1799 | #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ |
1887 | #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ | 1800 | #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ |
1888 | /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ | 1801 | /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ |
1889 | #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ | 1802 | #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ |
1890 | #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ | 1803 | #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ |
1891 | #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ | 1804 | #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ |
1892 | #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ | 1805 | #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ |
1893 | /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ | 1806 | /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ |
1894 | #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ | 1807 | #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ |
1895 | #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ | 1808 | #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ |
1896 | #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ | 1809 | #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ |
1897 | #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ | 1810 | #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ |
1898 | #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ | 1811 | #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ |
1899 | #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ | 1812 | #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ |
1900 | #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ | 1813 | #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ |
1901 | #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ | 1814 | #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ |
1902 | #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ | 1815 | #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ |
1903 | #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ | 1816 | #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ |
1904 | #define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ | 1817 | #define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ |
1905 | #define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ | 1818 | #define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ |
1906 | 1819 | ||
1907 | /* Use byte values for the following shift parameters | 1820 | /* Use byte values for the following shift parameters |
1908 | * Usage: | 1821 | * Usage: |
@@ -1925,10 +1838,10 @@ struct e1000_hw { | |||
1925 | #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 | 1838 | #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 |
1926 | #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 | 1839 | #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 |
1927 | 1840 | ||
1928 | #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ | 1841 | #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ |
1929 | #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ | 1842 | #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ |
1930 | #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ | 1843 | #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ |
1931 | #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ | 1844 | #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ |
1932 | 1845 | ||
1933 | /* SW_W_SYNC definitions */ | 1846 | /* SW_W_SYNC definitions */ |
1934 | #define E1000_SWFW_EEP_SM 0x0001 | 1847 | #define E1000_SWFW_EEP_SM 0x0001 |
@@ -1937,17 +1850,17 @@ struct e1000_hw { | |||
1937 | #define E1000_SWFW_MAC_CSR_SM 0x0008 | 1850 | #define E1000_SWFW_MAC_CSR_SM 0x0008 |
1938 | 1851 | ||
1939 | /* Receive Descriptor */ | 1852 | /* Receive Descriptor */ |
1940 | #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ | 1853 | #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ |
1941 | #define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ | 1854 | #define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ |
1942 | #define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */ | 1855 | #define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */ |
1943 | #define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ | 1856 | #define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ |
1944 | #define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ | 1857 | #define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ |
1945 | 1858 | ||
1946 | /* Flow Control */ | 1859 | /* Flow Control */ |
1947 | #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ | 1860 | #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ |
1948 | #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ | 1861 | #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ |
1949 | #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ | 1862 | #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ |
1950 | #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ | 1863 | #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ |
1951 | 1864 | ||
1952 | /* Header split receive */ | 1865 | /* Header split receive */ |
1953 | #define E1000_RFCTL_ISCSI_DIS 0x00000001 | 1866 | #define E1000_RFCTL_ISCSI_DIS 0x00000001 |
@@ -1967,66 +1880,64 @@ struct e1000_hw { | |||
1967 | #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 | 1880 | #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 |
1968 | 1881 | ||
1969 | /* Receive Descriptor Control */ | 1882 | /* Receive Descriptor Control */ |
1970 | #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ | 1883 | #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ |
1971 | #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ | 1884 | #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ |
1972 | #define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */ | 1885 | #define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */ |
1973 | #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */ | 1886 | #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */ |
1974 | 1887 | ||
1975 | /* Transmit Descriptor Control */ | 1888 | /* Transmit Descriptor Control */ |
1976 | #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ | 1889 | #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ |
1977 | #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ | 1890 | #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ |
1978 | #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ | 1891 | #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ |
1979 | #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ | 1892 | #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ |
1980 | #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ | 1893 | #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ |
1981 | #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ | 1894 | #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ |
1982 | #define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc. | 1895 | #define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc. |
1983 | still to be processed. */ | 1896 | still to be processed. */ |
1984 | /* Transmit Configuration Word */ | 1897 | /* Transmit Configuration Word */ |
1985 | #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ | 1898 | #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ |
1986 | #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ | 1899 | #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ |
1987 | #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ | 1900 | #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ |
1988 | #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ | 1901 | #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ |
1989 | #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ | 1902 | #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ |
1990 | #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ | 1903 | #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ |
1991 | #define E1000_TXCW_NP 0x00008000 /* TXCW next page */ | 1904 | #define E1000_TXCW_NP 0x00008000 /* TXCW next page */ |
1992 | #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ | 1905 | #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ |
1993 | #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ | 1906 | #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ |
1994 | #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ | 1907 | #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ |
1995 | 1908 | ||
1996 | /* Receive Configuration Word */ | 1909 | /* Receive Configuration Word */ |
1997 | #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ | 1910 | #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ |
1998 | #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ | 1911 | #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ |
1999 | #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ | 1912 | #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ |
2000 | #define E1000_RXCW_CC 0x10000000 /* Receive config change */ | 1913 | #define E1000_RXCW_CC 0x10000000 /* Receive config change */ |
2001 | #define E1000_RXCW_C 0x20000000 /* Receive config */ | 1914 | #define E1000_RXCW_C 0x20000000 /* Receive config */ |
2002 | #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ | 1915 | #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ |
2003 | #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ | 1916 | #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ |
2004 | 1917 | ||
2005 | /* Transmit Control */ | 1918 | /* Transmit Control */ |
2006 | #define E1000_TCTL_RST 0x00000001 /* software reset */ | 1919 | #define E1000_TCTL_RST 0x00000001 /* software reset */ |
2007 | #define E1000_TCTL_EN 0x00000002 /* enable tx */ | 1920 | #define E1000_TCTL_EN 0x00000002 /* enable tx */ |
2008 | #define E1000_TCTL_BCE 0x00000004 /* busy check enable */ | 1921 | #define E1000_TCTL_BCE 0x00000004 /* busy check enable */ |
2009 | #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ | 1922 | #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ |
2010 | #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ | 1923 | #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ |
2011 | #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ | 1924 | #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ |
2012 | #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ | 1925 | #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ |
2013 | #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ | 1926 | #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ |
2014 | #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ | 1927 | #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ |
2015 | #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ | 1928 | #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ |
2016 | #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ | 1929 | #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ |
2017 | /* Extended Transmit Control */ | 1930 | /* Extended Transmit Control */ |
2018 | #define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ | 1931 | #define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ |
2019 | #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ | 1932 | #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ |
2020 | |||
2021 | #define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000 | ||
2022 | 1933 | ||
2023 | /* Receive Checksum Control */ | 1934 | /* Receive Checksum Control */ |
2024 | #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ | 1935 | #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ |
2025 | #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ | 1936 | #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ |
2026 | #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ | 1937 | #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ |
2027 | #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ | 1938 | #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ |
2028 | #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ | 1939 | #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ |
2029 | #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ | 1940 | #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ |
2030 | 1941 | ||
2031 | /* Multiple Receive Queue Control */ | 1942 | /* Multiple Receive Queue Control */ |
2032 | #define E1000_MRQC_ENABLE_MASK 0x00000003 | 1943 | #define E1000_MRQC_ENABLE_MASK 0x00000003 |
@@ -2042,141 +1953,141 @@ struct e1000_hw { | |||
2042 | 1953 | ||
2043 | /* Definitions for power management and wakeup registers */ | 1954 | /* Definitions for power management and wakeup registers */ |
2044 | /* Wake Up Control */ | 1955 | /* Wake Up Control */ |
2045 | #define E1000_WUC_APME 0x00000001 /* APM Enable */ | 1956 | #define E1000_WUC_APME 0x00000001 /* APM Enable */ |
2046 | #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ | 1957 | #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ |
2047 | #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ | 1958 | #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ |
2048 | #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ | 1959 | #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ |
2049 | #define E1000_WUC_SPM 0x80000000 /* Enable SPM */ | 1960 | #define E1000_WUC_SPM 0x80000000 /* Enable SPM */ |
2050 | 1961 | ||
2051 | /* Wake Up Filter Control */ | 1962 | /* Wake Up Filter Control */ |
2052 | #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ | 1963 | #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ |
2053 | #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ | 1964 | #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ |
2054 | #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ | 1965 | #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ |
2055 | #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ | 1966 | #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ |
2056 | #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ | 1967 | #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ |
2057 | #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ | 1968 | #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ |
2058 | #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ | 1969 | #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ |
2059 | #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ | 1970 | #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ |
2060 | #define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ | 1971 | #define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ |
2061 | #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ | 1972 | #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ |
2062 | #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ | 1973 | #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ |
2063 | #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ | 1974 | #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ |
2064 | #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ | 1975 | #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ |
2065 | #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ | 1976 | #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ |
2066 | #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ | 1977 | #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ |
2067 | #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ | 1978 | #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ |
2068 | 1979 | ||
2069 | /* Wake Up Status */ | 1980 | /* Wake Up Status */ |
2070 | #define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */ | 1981 | #define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */ |
2071 | #define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */ | 1982 | #define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */ |
2072 | #define E1000_WUS_EX 0x00000004 /* Directed Exact Received */ | 1983 | #define E1000_WUS_EX 0x00000004 /* Directed Exact Received */ |
2073 | #define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */ | 1984 | #define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */ |
2074 | #define E1000_WUS_BC 0x00000010 /* Broadcast Received */ | 1985 | #define E1000_WUS_BC 0x00000010 /* Broadcast Received */ |
2075 | #define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */ | 1986 | #define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */ |
2076 | #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */ | 1987 | #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */ |
2077 | #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */ | 1988 | #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */ |
2078 | #define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */ | 1989 | #define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */ |
2079 | #define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */ | 1990 | #define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */ |
2080 | #define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */ | 1991 | #define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */ |
2081 | #define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */ | 1992 | #define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */ |
2082 | #define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ | 1993 | #define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ |
2083 | 1994 | ||
2084 | /* Management Control */ | 1995 | /* Management Control */ |
2085 | #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ | 1996 | #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ |
2086 | #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ | 1997 | #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ |
2087 | #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ | 1998 | #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ |
2088 | #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ | 1999 | #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ |
2089 | #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ | 2000 | #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ |
2090 | #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ | 2001 | #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ |
2091 | #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ | 2002 | #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ |
2092 | #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ | 2003 | #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ |
2093 | #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ | 2004 | #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ |
2094 | #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery | 2005 | #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery |
2095 | * Filtering */ | 2006 | * Filtering */ |
2096 | #define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ | 2007 | #define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ |
2097 | #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ | 2008 | #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ |
2098 | #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ | 2009 | #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ |
2099 | #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ | 2010 | #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ |
2100 | #define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ | 2011 | #define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ |
2101 | #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ | 2012 | #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ |
2102 | #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address | 2013 | #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address |
2103 | * filtering */ | 2014 | * filtering */ |
2104 | #define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host | 2015 | #define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host |
2105 | * memory */ | 2016 | * memory */ |
2106 | #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address | 2017 | #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address |
2107 | * filtering */ | 2018 | * filtering */ |
2108 | #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ | 2019 | #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ |
2109 | #define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ | 2020 | #define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ |
2110 | #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ | 2021 | #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ |
2111 | #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ | 2022 | #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ |
2112 | #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ | 2023 | #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ |
2113 | #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ | 2024 | #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ |
2114 | #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ | 2025 | #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ |
2115 | #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ | 2026 | #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ |
2116 | 2027 | ||
2117 | #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ | 2028 | #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ |
2118 | #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ | 2029 | #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ |
2119 | 2030 | ||
2120 | /* SW Semaphore Register */ | 2031 | /* SW Semaphore Register */ |
2121 | #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ | 2032 | #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ |
2122 | #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ | 2033 | #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ |
2123 | #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ | 2034 | #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ |
2124 | #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ | 2035 | #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ |
2125 | 2036 | ||
2126 | /* FW Semaphore Register */ | 2037 | /* FW Semaphore Register */ |
2127 | #define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */ | 2038 | #define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */ |
2128 | #define E1000_FWSM_MODE_SHIFT 1 | 2039 | #define E1000_FWSM_MODE_SHIFT 1 |
2129 | #define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ | 2040 | #define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ |
2130 | 2041 | ||
2131 | #define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */ | 2042 | #define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */ |
2132 | #define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */ | 2043 | #define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */ |
2133 | #define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */ | 2044 | #define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */ |
2134 | #define E1000_FWSM_SKUEL_SHIFT 29 | 2045 | #define E1000_FWSM_SKUEL_SHIFT 29 |
2135 | #define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */ | 2046 | #define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */ |
2136 | #define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */ | 2047 | #define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */ |
2137 | #define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */ | 2048 | #define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */ |
2138 | #define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */ | 2049 | #define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */ |
2139 | 2050 | ||
2140 | /* FFLT Debug Register */ | 2051 | /* FFLT Debug Register */ |
2141 | #define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */ | 2052 | #define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */ |
2142 | 2053 | ||
2143 | typedef enum { | 2054 | typedef enum { |
2144 | e1000_mng_mode_none = 0, | 2055 | e1000_mng_mode_none = 0, |
2145 | e1000_mng_mode_asf, | 2056 | e1000_mng_mode_asf, |
2146 | e1000_mng_mode_pt, | 2057 | e1000_mng_mode_pt, |
2147 | e1000_mng_mode_ipmi, | 2058 | e1000_mng_mode_ipmi, |
2148 | e1000_mng_mode_host_interface_only | 2059 | e1000_mng_mode_host_interface_only |
2149 | } e1000_mng_mode; | 2060 | } e1000_mng_mode; |
2150 | 2061 | ||
2151 | /* Host Inteface Control Register */ | 2062 | /* Host Interface Control Register */ |
2152 | #define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */ | 2063 | #define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */ |
2153 | #define E1000_HICR_C 0x00000002 /* Driver sets this bit when done | 2064 | #define E1000_HICR_C 0x00000002 /* Driver sets this bit when done |
2154 | * to put command in RAM */ | 2065 | * to put command in RAM */ |
2155 | #define E1000_HICR_SV 0x00000004 /* Status Validity */ | 2066 | #define E1000_HICR_SV 0x00000004 /* Status Validity */ |
2156 | #define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */ | 2067 | #define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */ |
2157 | 2068 | ||
2158 | /* Host Interface Command Interface - Address range 0x8800-0x8EFF */ | 2069 | /* Host Interface Command Interface - Address range 0x8800-0x8EFF */ |
2159 | #define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */ | 2070 | #define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */ |
2160 | #define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */ | 2071 | #define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */ |
2161 | #define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */ | 2072 | #define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */ |
2162 | #define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */ | 2073 | #define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */ |
2163 | 2074 | ||
2164 | struct e1000_host_command_header { | 2075 | struct e1000_host_command_header { |
2165 | u8 command_id; | 2076 | u8 command_id; |
2166 | u8 command_length; | 2077 | u8 command_length; |
2167 | u8 command_options; /* I/F bits for command, status for return */ | 2078 | u8 command_options; /* I/F bits for command, status for return */ |
2168 | u8 checksum; | 2079 | u8 checksum; |
2169 | }; | 2080 | }; |
2170 | struct e1000_host_command_info { | 2081 | struct e1000_host_command_info { |
2171 | struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ | 2082 | struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ |
2172 | u8 command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */ | 2083 | u8 command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */ |
2173 | }; | 2084 | }; |
2174 | 2085 | ||
2175 | /* Host SMB register #0 */ | 2086 | /* Host SMB register #0 */ |
2176 | #define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */ | 2087 | #define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */ |
2177 | #define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */ | 2088 | #define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */ |
2178 | #define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */ | 2089 | #define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */ |
2179 | #define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */ | 2090 | #define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */ |
2180 | 2091 | ||
2181 | /* Host SMB register #1 */ | 2092 | /* Host SMB register #1 */ |
2182 | #define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN | 2093 | #define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN |
@@ -2185,10 +2096,10 @@ struct e1000_host_command_info { | |||
2185 | #define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT | 2096 | #define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT |
2186 | 2097 | ||
2187 | /* FW Status Register */ | 2098 | /* FW Status Register */ |
2188 | #define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */ | 2099 | #define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */ |
2189 | 2100 | ||
2190 | /* Wake Up Packet Length */ | 2101 | /* Wake Up Packet Length */ |
2191 | #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ | 2102 | #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ |
2192 | 2103 | ||
2193 | #define E1000_MDALIGN 4096 | 2104 | #define E1000_MDALIGN 4096 |
2194 | 2105 | ||
@@ -2242,24 +2153,24 @@ struct e1000_host_command_info { | |||
2242 | #define PCI_EX_LINK_WIDTH_SHIFT 4 | 2153 | #define PCI_EX_LINK_WIDTH_SHIFT 4 |
2243 | 2154 | ||
2244 | /* EEPROM Commands - Microwire */ | 2155 | /* EEPROM Commands - Microwire */ |
2245 | #define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ | 2156 | #define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ |
2246 | #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ | 2157 | #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ |
2247 | #define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ | 2158 | #define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ |
2248 | #define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ | 2159 | #define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ |
2249 | #define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ | 2160 | #define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erase/write disable */ |
2250 | 2161 | ||
2251 | /* EEPROM Commands - SPI */ | 2162 | /* EEPROM Commands - SPI */ |
2252 | #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ | 2163 | #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ |
2253 | #define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ | 2164 | #define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ |
2254 | #define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ | 2165 | #define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ |
2255 | #define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ | 2166 | #define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ |
2256 | #define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */ | 2167 | #define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */ |
2257 | #define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */ | 2168 | #define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */ |
2258 | #define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */ | 2169 | #define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */ |
2259 | #define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */ | 2170 | #define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */ |
2260 | #define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ | 2171 | #define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ |
2261 | #define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ | 2172 | #define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ |
2262 | #define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ | 2173 | #define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ |
2263 | 2174 | ||
2264 | /* EEPROM Size definitions */ | 2175 | /* EEPROM Size definitions */ |
2265 | #define EEPROM_WORD_SIZE_SHIFT 6 | 2176 | #define EEPROM_WORD_SIZE_SHIFT 6 |
@@ -2270,7 +2181,7 @@ struct e1000_host_command_info { | |||
2270 | #define EEPROM_COMPAT 0x0003 | 2181 | #define EEPROM_COMPAT 0x0003 |
2271 | #define EEPROM_ID_LED_SETTINGS 0x0004 | 2182 | #define EEPROM_ID_LED_SETTINGS 0x0004 |
2272 | #define EEPROM_VERSION 0x0005 | 2183 | #define EEPROM_VERSION 0x0005 |
2273 | #define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */ | 2184 | #define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */ |
2274 | #define EEPROM_PHY_CLASS_WORD 0x0007 | 2185 | #define EEPROM_PHY_CLASS_WORD 0x0007 |
2275 | #define EEPROM_INIT_CONTROL1_REG 0x000A | 2186 | #define EEPROM_INIT_CONTROL1_REG 0x000A |
2276 | #define EEPROM_INIT_CONTROL2_REG 0x000F | 2187 | #define EEPROM_INIT_CONTROL2_REG 0x000F |
@@ -2283,22 +2194,16 @@ struct e1000_host_command_info { | |||
2283 | #define EEPROM_FLASH_VERSION 0x0032 | 2194 | #define EEPROM_FLASH_VERSION 0x0032 |
2284 | #define EEPROM_CHECKSUM_REG 0x003F | 2195 | #define EEPROM_CHECKSUM_REG 0x003F |
2285 | 2196 | ||
2286 | #define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */ | 2197 | #define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */ |
2287 | #define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */ | 2198 | #define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */ |
2288 | 2199 | ||
2289 | /* Word definitions for ID LED Settings */ | 2200 | /* Word definitions for ID LED Settings */ |
2290 | #define ID_LED_RESERVED_0000 0x0000 | 2201 | #define ID_LED_RESERVED_0000 0x0000 |
2291 | #define ID_LED_RESERVED_FFFF 0xFFFF | 2202 | #define ID_LED_RESERVED_FFFF 0xFFFF |
2292 | #define ID_LED_RESERVED_82573 0xF746 | ||
2293 | #define ID_LED_DEFAULT_82573 0x1811 | ||
2294 | #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ | 2203 | #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ |
2295 | (ID_LED_OFF1_OFF2 << 8) | \ | 2204 | (ID_LED_OFF1_OFF2 << 8) | \ |
2296 | (ID_LED_DEF1_DEF2 << 4) | \ | 2205 | (ID_LED_DEF1_DEF2 << 4) | \ |
2297 | (ID_LED_DEF1_DEF2)) | 2206 | (ID_LED_DEF1_DEF2)) |
2298 | #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ | ||
2299 | (ID_LED_DEF1_OFF2 << 8) | \ | ||
2300 | (ID_LED_DEF1_ON2 << 4) | \ | ||
2301 | (ID_LED_DEF1_DEF2)) | ||
2302 | #define ID_LED_DEF1_DEF2 0x1 | 2207 | #define ID_LED_DEF1_DEF2 0x1 |
2303 | #define ID_LED_DEF1_ON2 0x2 | 2208 | #define ID_LED_DEF1_ON2 0x2 |
2304 | #define ID_LED_DEF1_OFF2 0x3 | 2209 | #define ID_LED_DEF1_OFF2 0x3 |
@@ -2313,7 +2218,6 @@ struct e1000_host_command_info { | |||
2313 | #define IGP_ACTIVITY_LED_ENABLE 0x0300 | 2218 | #define IGP_ACTIVITY_LED_ENABLE 0x0300 |
2314 | #define IGP_LED3_MODE 0x07000000 | 2219 | #define IGP_LED3_MODE 0x07000000 |
2315 | 2220 | ||
2316 | |||
2317 | /* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */ | 2221 | /* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */ |
2318 | #define EEPROM_SERDES_AMPLITUDE_MASK 0x000F | 2222 | #define EEPROM_SERDES_AMPLITUDE_MASK 0x000F |
2319 | 2223 | ||
@@ -2384,11 +2288,8 @@ struct e1000_host_command_info { | |||
2384 | 2288 | ||
2385 | #define DEFAULT_82542_TIPG_IPGR2 10 | 2289 | #define DEFAULT_82542_TIPG_IPGR2 10 |
2386 | #define DEFAULT_82543_TIPG_IPGR2 6 | 2290 | #define DEFAULT_82543_TIPG_IPGR2 6 |
2387 | #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 | ||
2388 | #define E1000_TIPG_IPGR2_SHIFT 20 | 2291 | #define E1000_TIPG_IPGR2_SHIFT 20 |
2389 | 2292 | ||
2390 | #define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009 | ||
2391 | #define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008 | ||
2392 | #define E1000_TXDMAC_DPP 0x00000001 | 2293 | #define E1000_TXDMAC_DPP 0x00000001 |
2393 | 2294 | ||
2394 | /* Adaptive IFS defines */ | 2295 | /* Adaptive IFS defines */ |
@@ -2421,9 +2322,9 @@ struct e1000_host_command_info { | |||
2421 | #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 | 2322 | #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 |
2422 | 2323 | ||
2423 | /* PBA constants */ | 2324 | /* PBA constants */ |
2424 | #define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */ | 2325 | #define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */ |
2425 | #define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */ | 2326 | #define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */ |
2426 | #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ | 2327 | #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ |
2427 | #define E1000_PBA_20K 0x0014 | 2328 | #define E1000_PBA_20K 0x0014 |
2428 | #define E1000_PBA_22K 0x0016 | 2329 | #define E1000_PBA_22K 0x0016 |
2429 | #define E1000_PBA_24K 0x0018 | 2330 | #define E1000_PBA_24K 0x0018 |
@@ -2432,7 +2333,7 @@ struct e1000_host_command_info { | |||
2432 | #define E1000_PBA_34K 0x0022 | 2333 | #define E1000_PBA_34K 0x0022 |
2433 | #define E1000_PBA_38K 0x0026 | 2334 | #define E1000_PBA_38K 0x0026 |
2434 | #define E1000_PBA_40K 0x0028 | 2335 | #define E1000_PBA_40K 0x0028 |
2435 | #define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ | 2336 | #define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ |
2436 | 2337 | ||
2437 | #define E1000_PBS_16K E1000_PBA_16K | 2338 | #define E1000_PBS_16K E1000_PBA_16K |
2438 | 2339 | ||
@@ -2442,9 +2343,9 @@ struct e1000_host_command_info { | |||
2442 | #define FLOW_CONTROL_TYPE 0x8808 | 2343 | #define FLOW_CONTROL_TYPE 0x8808 |
2443 | 2344 | ||
2444 | /* The historical defaults for the flow control values are given below. */ | 2345 | /* The historical defaults for the flow control values are given below. */ |
2445 | #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ | 2346 | #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ |
2446 | #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ | 2347 | #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ |
2447 | #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ | 2348 | #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ |
2448 | 2349 | ||
2449 | /* PCIX Config space */ | 2350 | /* PCIX Config space */ |
2450 | #define PCIX_COMMAND_REGISTER 0xE6 | 2351 | #define PCIX_COMMAND_REGISTER 0xE6 |
@@ -2458,7 +2359,6 @@ struct e1000_host_command_info { | |||
2458 | #define PCIX_STATUS_HI_MMRBC_4K 0x3 | 2359 | #define PCIX_STATUS_HI_MMRBC_4K 0x3 |
2459 | #define PCIX_STATUS_HI_MMRBC_2K 0x2 | 2360 | #define PCIX_STATUS_HI_MMRBC_2K 0x2 |
2460 | 2361 | ||
2461 | |||
2462 | /* Number of bits required to shift right the "pause" bits from the | 2362 | /* Number of bits required to shift right the "pause" bits from the |
2463 | * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register. | 2363 | * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register. |
2464 | */ | 2364 | */ |
@@ -2479,14 +2379,11 @@ struct e1000_host_command_info { | |||
2479 | */ | 2379 | */ |
2480 | #define ILOS_SHIFT 3 | 2380 | #define ILOS_SHIFT 3 |
2481 | 2381 | ||
2482 | |||
2483 | #define RECEIVE_BUFFER_ALIGN_SIZE (256) | 2382 | #define RECEIVE_BUFFER_ALIGN_SIZE (256) |
2484 | 2383 | ||
2485 | /* Number of milliseconds we wait for auto-negotiation to complete */ | 2384 | /* Number of milliseconds we wait for auto-negotiation to complete */ |
2486 | #define LINK_UP_TIMEOUT 500 | 2385 | #define LINK_UP_TIMEOUT 500 |
2487 | 2386 | ||
2488 | /* Number of 100 microseconds we wait for PCI Express master disable */ | ||
2489 | #define MASTER_DISABLE_TIMEOUT 800 | ||
2490 | /* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */ | 2387 | /* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */ |
2491 | #define AUTO_READ_DONE_TIMEOUT 10 | 2388 | #define AUTO_READ_DONE_TIMEOUT 10 |
2492 | /* Number of milliseconds we wait for PHY configuration done after MAC reset */ | 2389 | /* Number of milliseconds we wait for PHY configuration done after MAC reset */ |
@@ -2534,7 +2431,6 @@ struct e1000_host_command_info { | |||
2534 | (((length) > (adapter)->min_frame_size) && \ | 2431 | (((length) > (adapter)->min_frame_size) && \ |
2535 | ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1))))) | 2432 | ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1))))) |
2536 | 2433 | ||
2537 | |||
2538 | /* Structures, enums, and macros for the PHY */ | 2434 | /* Structures, enums, and macros for the PHY */ |
2539 | 2435 | ||
2540 | /* Bit definitions for the Management Data IO (MDIO) and Management Data | 2436 | /* Bit definitions for the Management Data IO (MDIO) and Management Data |
@@ -2551,49 +2447,49 @@ struct e1000_host_command_info { | |||
2551 | 2447 | ||
2552 | /* PHY 1000 MII Register/Bit Definitions */ | 2448 | /* PHY 1000 MII Register/Bit Definitions */ |
2553 | /* PHY Registers defined by IEEE */ | 2449 | /* PHY Registers defined by IEEE */ |
2554 | #define PHY_CTRL 0x00 /* Control Register */ | 2450 | #define PHY_CTRL 0x00 /* Control Register */ |
2555 | #define PHY_STATUS 0x01 /* Status Regiser */ | 2451 | #define PHY_STATUS 0x01 /* Status Register */ |
2556 | #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ | 2452 | #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ |
2557 | #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ | 2453 | #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ |
2558 | #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ | 2454 | #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ |
2559 | #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ | 2455 | #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ |
2560 | #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ | 2456 | #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ |
2561 | #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ | 2457 | #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ |
2562 | #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ | 2458 | #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ |
2563 | #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ | 2459 | #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ |
2564 | #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ | 2460 | #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ |
2565 | #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ | 2461 | #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ |
2566 | 2462 | ||
2567 | #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ | 2463 | #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ |
2568 | #define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */ | 2464 | #define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */ |
2569 | 2465 | ||
2570 | /* M88E1000 Specific Registers */ | 2466 | /* M88E1000 Specific Registers */ |
2571 | #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ | 2467 | #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ |
2572 | #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ | 2468 | #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ |
2573 | #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ | 2469 | #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ |
2574 | #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ | 2470 | #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ |
2575 | #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ | 2471 | #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ |
2576 | #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ | 2472 | #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ |
2577 | 2473 | ||
2578 | #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ | 2474 | #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ |
2579 | #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ | 2475 | #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ |
2580 | #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ | 2476 | #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ |
2581 | #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ | 2477 | #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ |
2582 | #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ | 2478 | #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ |
2583 | 2479 | ||
2584 | #define IGP01E1000_IEEE_REGS_PAGE 0x0000 | 2480 | #define IGP01E1000_IEEE_REGS_PAGE 0x0000 |
2585 | #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 | 2481 | #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 |
2586 | #define IGP01E1000_IEEE_FORCE_GIGA 0x0140 | 2482 | #define IGP01E1000_IEEE_FORCE_GIGA 0x0140 |
2587 | 2483 | ||
2588 | /* IGP01E1000 Specific Registers */ | 2484 | /* IGP01E1000 Specific Registers */ |
2589 | #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ | 2485 | #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ |
2590 | #define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ | 2486 | #define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ |
2591 | #define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ | 2487 | #define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ |
2592 | #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ | 2488 | #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ |
2593 | #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ | 2489 | #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ |
2594 | #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ | 2490 | #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ |
2595 | #define IGP02E1000_PHY_POWER_MGMT 0x19 | 2491 | #define IGP02E1000_PHY_POWER_MGMT 0x19 |
2596 | #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ | 2492 | #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ |
2597 | 2493 | ||
2598 | /* IGP01E1000 AGC Registers - stores the cable length values*/ | 2494 | /* IGP01E1000 AGC Registers - stores the cable length values*/ |
2599 | #define IGP01E1000_PHY_AGC_A 0x1172 | 2495 | #define IGP01E1000_PHY_AGC_A 0x1172 |
@@ -2636,192 +2532,119 @@ struct e1000_host_command_info { | |||
2636 | 2532 | ||
2637 | #define IGP01E1000_ANALOG_REGS_PAGE 0x20C0 | 2533 | #define IGP01E1000_ANALOG_REGS_PAGE 0x20C0 |
2638 | 2534 | ||
2639 | /* Bits... | ||
2640 | * 15-5: page | ||
2641 | * 4-0: register offset | ||
2642 | */ | ||
2643 | #define GG82563_PAGE_SHIFT 5 | ||
2644 | #define GG82563_REG(page, reg) \ | ||
2645 | (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) | ||
2646 | #define GG82563_MIN_ALT_REG 30 | ||
2647 | |||
2648 | /* GG82563 Specific Registers */ | ||
2649 | #define GG82563_PHY_SPEC_CTRL \ | ||
2650 | GG82563_REG(0, 16) /* PHY Specific Control */ | ||
2651 | #define GG82563_PHY_SPEC_STATUS \ | ||
2652 | GG82563_REG(0, 17) /* PHY Specific Status */ | ||
2653 | #define GG82563_PHY_INT_ENABLE \ | ||
2654 | GG82563_REG(0, 18) /* Interrupt Enable */ | ||
2655 | #define GG82563_PHY_SPEC_STATUS_2 \ | ||
2656 | GG82563_REG(0, 19) /* PHY Specific Status 2 */ | ||
2657 | #define GG82563_PHY_RX_ERR_CNTR \ | ||
2658 | GG82563_REG(0, 21) /* Receive Error Counter */ | ||
2659 | #define GG82563_PHY_PAGE_SELECT \ | ||
2660 | GG82563_REG(0, 22) /* Page Select */ | ||
2661 | #define GG82563_PHY_SPEC_CTRL_2 \ | ||
2662 | GG82563_REG(0, 26) /* PHY Specific Control 2 */ | ||
2663 | #define GG82563_PHY_PAGE_SELECT_ALT \ | ||
2664 | GG82563_REG(0, 29) /* Alternate Page Select */ | ||
2665 | #define GG82563_PHY_TEST_CLK_CTRL \ | ||
2666 | GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */ | ||
2667 | |||
2668 | #define GG82563_PHY_MAC_SPEC_CTRL \ | ||
2669 | GG82563_REG(2, 21) /* MAC Specific Control Register */ | ||
2670 | #define GG82563_PHY_MAC_SPEC_CTRL_2 \ | ||
2671 | GG82563_REG(2, 26) /* MAC Specific Control 2 */ | ||
2672 | |||
2673 | #define GG82563_PHY_DSP_DISTANCE \ | ||
2674 | GG82563_REG(5, 26) /* DSP Distance */ | ||
2675 | |||
2676 | /* Page 193 - Port Control Registers */ | ||
2677 | #define GG82563_PHY_KMRN_MODE_CTRL \ | ||
2678 | GG82563_REG(193, 16) /* Kumeran Mode Control */ | ||
2679 | #define GG82563_PHY_PORT_RESET \ | ||
2680 | GG82563_REG(193, 17) /* Port Reset */ | ||
2681 | #define GG82563_PHY_REVISION_ID \ | ||
2682 | GG82563_REG(193, 18) /* Revision ID */ | ||
2683 | #define GG82563_PHY_DEVICE_ID \ | ||
2684 | GG82563_REG(193, 19) /* Device ID */ | ||
2685 | #define GG82563_PHY_PWR_MGMT_CTRL \ | ||
2686 | GG82563_REG(193, 20) /* Power Management Control */ | ||
2687 | #define GG82563_PHY_RATE_ADAPT_CTRL \ | ||
2688 | GG82563_REG(193, 25) /* Rate Adaptation Control */ | ||
2689 | |||
2690 | /* Page 194 - KMRN Registers */ | ||
2691 | #define GG82563_PHY_KMRN_FIFO_CTRL_STAT \ | ||
2692 | GG82563_REG(194, 16) /* FIFO's Control/Status */ | ||
2693 | #define GG82563_PHY_KMRN_CTRL \ | ||
2694 | GG82563_REG(194, 17) /* Control */ | ||
2695 | #define GG82563_PHY_INBAND_CTRL \ | ||
2696 | GG82563_REG(194, 18) /* Inband Control */ | ||
2697 | #define GG82563_PHY_KMRN_DIAGNOSTIC \ | ||
2698 | GG82563_REG(194, 19) /* Diagnostic */ | ||
2699 | #define GG82563_PHY_ACK_TIMEOUTS \ | ||
2700 | GG82563_REG(194, 20) /* Acknowledge Timeouts */ | ||
2701 | #define GG82563_PHY_ADV_ABILITY \ | ||
2702 | GG82563_REG(194, 21) /* Advertised Ability */ | ||
2703 | #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \ | ||
2704 | GG82563_REG(194, 23) /* Link Partner Advertised Ability */ | ||
2705 | #define GG82563_PHY_ADV_NEXT_PAGE \ | ||
2706 | GG82563_REG(194, 24) /* Advertised Next Page */ | ||
2707 | #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \ | ||
2708 | GG82563_REG(194, 25) /* Link Partner Advertised Next page */ | ||
2709 | #define GG82563_PHY_KMRN_MISC \ | ||
2710 | GG82563_REG(194, 26) /* Misc. */ | ||
2711 | |||
2712 | /* PHY Control Register */ | 2535 | /* PHY Control Register */ |
2713 | #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ | 2536 | #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ |
2714 | #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ | 2537 | #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ |
2715 | #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ | 2538 | #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ |
2716 | #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ | 2539 | #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ |
2717 | #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ | 2540 | #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ |
2718 | #define MII_CR_POWER_DOWN 0x0800 /* Power down */ | 2541 | #define MII_CR_POWER_DOWN 0x0800 /* Power down */ |
2719 | #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ | 2542 | #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ |
2720 | #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ | 2543 | #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ |
2721 | #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ | 2544 | #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ |
2722 | #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ | 2545 | #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ |
2723 | 2546 | ||
2724 | /* PHY Status Register */ | 2547 | /* PHY Status Register */ |
2725 | #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ | 2548 | #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ |
2726 | #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ | 2549 | #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ |
2727 | #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ | 2550 | #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ |
2728 | #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ | 2551 | #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ |
2729 | #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ | 2552 | #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ |
2730 | #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ | 2553 | #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ |
2731 | #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ | 2554 | #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ |
2732 | #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ | 2555 | #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ |
2733 | #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ | 2556 | #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ |
2734 | #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ | 2557 | #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ |
2735 | #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ | 2558 | #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ |
2736 | #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ | 2559 | #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ |
2737 | #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ | 2560 | #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ |
2738 | #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ | 2561 | #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ |
2739 | #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ | 2562 | #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ |
2740 | 2563 | ||
2741 | /* Autoneg Advertisement Register */ | 2564 | /* Autoneg Advertisement Register */ |
2742 | #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ | 2565 | #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ |
2743 | #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ | 2566 | #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ |
2744 | #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ | 2567 | #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ |
2745 | #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ | 2568 | #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ |
2746 | #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ | 2569 | #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ |
2747 | #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ | 2570 | #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ |
2748 | #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ | 2571 | #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ |
2749 | #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ | 2572 | #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ |
2750 | #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ | 2573 | #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ |
2751 | #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ | 2574 | #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ |
2752 | 2575 | ||
2753 | /* Link Partner Ability Register (Base Page) */ | 2576 | /* Link Partner Ability Register (Base Page) */ |
2754 | #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ | 2577 | #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ |
2755 | #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ | 2578 | #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ |
2756 | #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ | 2579 | #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ |
2757 | #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ | 2580 | #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ |
2758 | #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ | 2581 | #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ |
2759 | #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ | 2582 | #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ |
2760 | #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ | 2583 | #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ |
2761 | #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ | 2584 | #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ |
2762 | #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ | 2585 | #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ |
2763 | #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ | 2586 | #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ |
2764 | #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ | 2587 | #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ |
2765 | 2588 | ||
2766 | /* Autoneg Expansion Register */ | 2589 | /* Autoneg Expansion Register */ |
2767 | #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ | 2590 | #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ |
2768 | #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ | 2591 | #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ |
2769 | #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ | 2592 | #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ |
2770 | #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ | 2593 | #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ |
2771 | #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ | 2594 | #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ |
2772 | 2595 | ||
2773 | /* Next Page TX Register */ | 2596 | /* Next Page TX Register */ |
2774 | #define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ | 2597 | #define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ |
2775 | #define NPTX_TOGGLE 0x0800 /* Toggles between exchanges | 2598 | #define NPTX_TOGGLE 0x0800 /* Toggles between exchanges |
2776 | * of different NP | 2599 | * of different NP |
2777 | */ | 2600 | */ |
2778 | #define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg | 2601 | #define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg |
2779 | * 0 = cannot comply with msg | 2602 | * 0 = cannot comply with msg |
2780 | */ | 2603 | */ |
2781 | #define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ | 2604 | #define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ |
2782 | #define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow | 2605 | #define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow |
2783 | * 0 = sending last NP | 2606 | * 0 = sending last NP |
2784 | */ | 2607 | */ |
2785 | 2608 | ||
2786 | /* Link Partner Next Page Register */ | 2609 | /* Link Partner Next Page Register */ |
2787 | #define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ | 2610 | #define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ |
2788 | #define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges | 2611 | #define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges |
2789 | * of different NP | 2612 | * of different NP |
2790 | */ | 2613 | */ |
2791 | #define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg | 2614 | #define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg |
2792 | * 0 = cannot comply with msg | 2615 | * 0 = cannot comply with msg |
2793 | */ | 2616 | */ |
2794 | #define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ | 2617 | #define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ |
2795 | #define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ | 2618 | #define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ |
2796 | #define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow | 2619 | #define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow |
2797 | * 0 = sending last NP | 2620 | * 0 = sending last NP |
2798 | */ | 2621 | */ |
2799 | 2622 | ||
2800 | /* 1000BASE-T Control Register */ | 2623 | /* 1000BASE-T Control Register */ |
2801 | #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ | 2624 | #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ |
2802 | #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ | 2625 | #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ |
2803 | #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ | 2626 | #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ |
2804 | #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ | 2627 | #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ |
2805 | /* 0=DTE device */ | 2628 | /* 0=DTE device */ |
2806 | #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ | 2629 | #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ |
2807 | /* 0=Configure PHY as Slave */ | 2630 | /* 0=Configure PHY as Slave */ |
2808 | #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ | 2631 | #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ |
2809 | /* 0=Automatic Master/Slave config */ | 2632 | /* 0=Automatic Master/Slave config */ |
2810 | #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ | 2633 | #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ |
2811 | #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ | 2634 | #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ |
2812 | #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ | 2635 | #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ |
2813 | #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ | 2636 | #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ |
2814 | #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ | 2637 | #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ |
2815 | 2638 | ||
2816 | /* 1000BASE-T Status Register */ | 2639 | /* 1000BASE-T Status Register */ |
2817 | #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ | 2640 | #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ |
2818 | #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ | 2641 | #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ |
2819 | #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ | 2642 | #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ |
2820 | #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ | 2643 | #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ |
2821 | #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ | 2644 | #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ |
2822 | #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ | 2645 | #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ |
2823 | #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ | 2646 | #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ |
2824 | #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ | 2647 | #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ |
2825 | #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 | 2648 | #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 |
2826 | #define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 | 2649 | #define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 |
2827 | #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 | 2650 | #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 |
@@ -2829,64 +2652,64 @@ struct e1000_host_command_info { | |||
2829 | #define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100 | 2652 | #define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100 |
2830 | 2653 | ||
2831 | /* Extended Status Register */ | 2654 | /* Extended Status Register */ |
2832 | #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ | 2655 | #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ |
2833 | #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ | 2656 | #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ |
2834 | #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ | 2657 | #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ |
2835 | #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ | 2658 | #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ |
2836 | 2659 | ||
2837 | #define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ | 2660 | #define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ |
2838 | #define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ | 2661 | #define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ |
2839 | 2662 | ||
2840 | #define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ | 2663 | #define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ |
2841 | /* (0=enable, 1=disable) */ | 2664 | /* (0=enable, 1=disable) */ |
2842 | 2665 | ||
2843 | /* M88E1000 PHY Specific Control Register */ | 2666 | /* M88E1000 PHY Specific Control Register */ |
2844 | #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ | 2667 | #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ |
2845 | #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ | 2668 | #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ |
2846 | #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ | 2669 | #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ |
2847 | #define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, | 2670 | #define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, |
2848 | * 0=CLK125 toggling | 2671 | * 0=CLK125 toggling |
2849 | */ | 2672 | */ |
2850 | #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ | 2673 | #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ |
2851 | /* Manual MDI configuration */ | 2674 | /* Manual MDI configuration */ |
2852 | #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ | 2675 | #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ |
2853 | #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, | 2676 | #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, |
2854 | * 100BASE-TX/10BASE-T: | 2677 | * 100BASE-TX/10BASE-T: |
2855 | * MDI Mode | 2678 | * MDI Mode |
2856 | */ | 2679 | */ |
2857 | #define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled | 2680 | #define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled |
2858 | * all speeds. | 2681 | * all speeds. |
2859 | */ | 2682 | */ |
2860 | #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 | 2683 | #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 |
2861 | /* 1=Enable Extended 10BASE-T distance | 2684 | /* 1=Enable Extended 10BASE-T distance |
2862 | * (Lower 10BASE-T RX Threshold) | 2685 | * (Lower 10BASE-T RX Threshold) |
2863 | * 0=Normal 10BASE-T RX Threshold */ | 2686 | * 0=Normal 10BASE-T RX Threshold */ |
2864 | #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 | 2687 | #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 |
2865 | /* 1=5-Bit interface in 100BASE-TX | 2688 | /* 1=5-Bit interface in 100BASE-TX |
2866 | * 0=MII interface in 100BASE-TX */ | 2689 | * 0=MII interface in 100BASE-TX */ |
2867 | #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ | 2690 | #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ |
2868 | #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ | 2691 | #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ |
2869 | #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ | 2692 | #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ |
2870 | 2693 | ||
2871 | #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 | 2694 | #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 |
2872 | #define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 | 2695 | #define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 |
2873 | #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 | 2696 | #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 |
2874 | 2697 | ||
2875 | /* M88E1000 PHY Specific Status Register */ | 2698 | /* M88E1000 PHY Specific Status Register */ |
2876 | #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ | 2699 | #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ |
2877 | #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ | 2700 | #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ |
2878 | #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ | 2701 | #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ |
2879 | #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ | 2702 | #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ |
2880 | #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; | 2703 | #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; |
2881 | * 3=110-140M;4=>140M */ | 2704 | * 3=110-140M;4=>140M */ |
2882 | #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ | 2705 | #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ |
2883 | #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ | 2706 | #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ |
2884 | #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ | 2707 | #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ |
2885 | #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ | 2708 | #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ |
2886 | #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ | 2709 | #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ |
2887 | #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ | 2710 | #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ |
2888 | #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ | 2711 | #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ |
2889 | #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ | 2712 | #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ |
2890 | 2713 | ||
2891 | #define M88E1000_PSSR_REV_POLARITY_SHIFT 1 | 2714 | #define M88E1000_PSSR_REV_POLARITY_SHIFT 1 |
2892 | #define M88E1000_PSSR_DOWNSHIFT_SHIFT 5 | 2715 | #define M88E1000_PSSR_DOWNSHIFT_SHIFT 5 |
@@ -2894,12 +2717,12 @@ struct e1000_host_command_info { | |||
2894 | #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 | 2717 | #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 |
2895 | 2718 | ||
2896 | /* M88E1000 Extended PHY Specific Control Register */ | 2719 | /* M88E1000 Extended PHY Specific Control Register */ |
2897 | #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ | 2720 | #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ |
2898 | #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. | 2721 | #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. |
2899 | * Will assert lost lock and bring | 2722 | * Will assert lost lock and bring |
2900 | * link down if idle not seen | 2723 | * link down if idle not seen |
2901 | * within 1ms in 1000BASE-T | 2724 | * within 1ms in 1000BASE-T |
2902 | */ | 2725 | */ |
2903 | /* Number of times we will attempt to autonegotiate before downshifting if we | 2726 | /* Number of times we will attempt to autonegotiate before downshifting if we |
2904 | * are the master */ | 2727 | * are the master */ |
2905 | #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 | 2728 | #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 |
@@ -2914,9 +2737,9 @@ struct e1000_host_command_info { | |||
2914 | #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 | 2737 | #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 |
2915 | #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 | 2738 | #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 |
2916 | #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 | 2739 | #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 |
2917 | #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ | 2740 | #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ |
2918 | #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ | 2741 | #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ |
2919 | #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ | 2742 | #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ |
2920 | 2743 | ||
2921 | /* M88EC018 Rev 2 specific DownShift settings */ | 2744 | /* M88EC018 Rev 2 specific DownShift settings */ |
2922 | #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 | 2745 | #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 |
@@ -2938,18 +2761,18 @@ struct e1000_host_command_info { | |||
2938 | #define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000 | 2761 | #define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000 |
2939 | 2762 | ||
2940 | /* IGP01E1000 Specific Port Status Register - R/O */ | 2763 | /* IGP01E1000 Specific Port Status Register - R/O */ |
2941 | #define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */ | 2764 | #define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */ |
2942 | #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 | 2765 | #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 |
2943 | #define IGP01E1000_PSSR_CABLE_LENGTH 0x007C | 2766 | #define IGP01E1000_PSSR_CABLE_LENGTH 0x007C |
2944 | #define IGP01E1000_PSSR_FULL_DUPLEX 0x0200 | 2767 | #define IGP01E1000_PSSR_FULL_DUPLEX 0x0200 |
2945 | #define IGP01E1000_PSSR_LINK_UP 0x0400 | 2768 | #define IGP01E1000_PSSR_LINK_UP 0x0400 |
2946 | #define IGP01E1000_PSSR_MDIX 0x0800 | 2769 | #define IGP01E1000_PSSR_MDIX 0x0800 |
2947 | #define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */ | 2770 | #define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */ |
2948 | #define IGP01E1000_PSSR_SPEED_10MBPS 0x4000 | 2771 | #define IGP01E1000_PSSR_SPEED_10MBPS 0x4000 |
2949 | #define IGP01E1000_PSSR_SPEED_100MBPS 0x8000 | 2772 | #define IGP01E1000_PSSR_SPEED_100MBPS 0x8000 |
2950 | #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 | 2773 | #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 |
2951 | #define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */ | 2774 | #define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */ |
2952 | #define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */ | 2775 | #define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */ |
2953 | 2776 | ||
2954 | /* IGP01E1000 Specific Port Control Register - R/W */ | 2777 | /* IGP01E1000 Specific Port Control Register - R/W */ |
2955 | #define IGP01E1000_PSCR_TP_LOOPBACK 0x0010 | 2778 | #define IGP01E1000_PSCR_TP_LOOPBACK 0x0010 |
@@ -2957,16 +2780,16 @@ struct e1000_host_command_info { | |||
2957 | #define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400 | 2780 | #define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400 |
2958 | #define IGP01E1000_PSCR_FLIP_CHIP 0x0800 | 2781 | #define IGP01E1000_PSCR_FLIP_CHIP 0x0800 |
2959 | #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 | 2782 | #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 |
2960 | #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */ | 2783 | #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */ |
2961 | 2784 | ||
2962 | /* IGP01E1000 Specific Port Link Health Register */ | 2785 | /* IGP01E1000 Specific Port Link Health Register */ |
2963 | #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 | 2786 | #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 |
2964 | #define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000 | 2787 | #define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000 |
2965 | #define IGP01E1000_PLHR_MASTER_FAULT 0x2000 | 2788 | #define IGP01E1000_PLHR_MASTER_FAULT 0x2000 |
2966 | #define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000 | 2789 | #define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000 |
2967 | #define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */ | 2790 | #define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */ |
2968 | #define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */ | 2791 | #define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */ |
2969 | #define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */ | 2792 | #define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */ |
2970 | #define IGP01E1000_PLHR_DATA_ERR_0 0x0100 | 2793 | #define IGP01E1000_PLHR_DATA_ERR_0 0x0100 |
2971 | #define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040 | 2794 | #define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040 |
2972 | #define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010 | 2795 | #define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010 |
@@ -2981,9 +2804,9 @@ struct e1000_host_command_info { | |||
2981 | #define IGP01E1000_MSE_CHANNEL_B 0x0F00 | 2804 | #define IGP01E1000_MSE_CHANNEL_B 0x0F00 |
2982 | #define IGP01E1000_MSE_CHANNEL_A 0xF000 | 2805 | #define IGP01E1000_MSE_CHANNEL_A 0xF000 |
2983 | 2806 | ||
2984 | #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ | 2807 | #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ |
2985 | #define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */ | 2808 | #define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */ |
2986 | #define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */ | 2809 | #define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */ |
2987 | 2810 | ||
2988 | /* IGP01E1000 DSP reset macros */ | 2811 | /* IGP01E1000 DSP reset macros */ |
2989 | #define DSP_RESET_ENABLE 0x0 | 2812 | #define DSP_RESET_ENABLE 0x0 |
@@ -2992,8 +2815,8 @@ struct e1000_host_command_info { | |||
2992 | 2815 | ||
2993 | /* IGP01E1000 & IGP02E1000 AGC Registers */ | 2816 | /* IGP01E1000 & IGP02E1000 AGC Registers */ |
2994 | 2817 | ||
2995 | #define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */ | 2818 | #define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */ |
2996 | #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */ | 2819 | #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */ |
2997 | 2820 | ||
2998 | /* IGP02E1000 AGC Register Length 9-bit mask */ | 2821 | /* IGP02E1000 AGC Register Length 9-bit mask */ |
2999 | #define IGP02E1000_AGC_LENGTH_MASK 0x7F | 2822 | #define IGP02E1000_AGC_LENGTH_MASK 0x7F |
@@ -3011,9 +2834,9 @@ struct e1000_host_command_info { | |||
3011 | #define IGP01E1000_PHY_POLARITY_MASK 0x0078 | 2834 | #define IGP01E1000_PHY_POLARITY_MASK 0x0078 |
3012 | 2835 | ||
3013 | /* IGP01E1000 GMII FIFO Register */ | 2836 | /* IGP01E1000 GMII FIFO Register */ |
3014 | #define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed | 2837 | #define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed |
3015 | * on Link-Up */ | 2838 | * on Link-Up */ |
3016 | #define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */ | 2839 | #define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */ |
3017 | 2840 | ||
3018 | /* IGP01E1000 Analog Register */ | 2841 | /* IGP01E1000 Analog Register */ |
3019 | #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1 | 2842 | #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1 |
@@ -3032,114 +2855,6 @@ struct e1000_host_command_info { | |||
3032 | #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 | 2855 | #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 |
3033 | #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 | 2856 | #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 |
3034 | 2857 | ||
3035 | /* GG82563 PHY Specific Status Register (Page 0, Register 16 */ | ||
3036 | #define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */ | ||
3037 | #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal Disabled */ | ||
3038 | #define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */ | ||
3039 | #define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter Disabled */ | ||
3040 | #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 | ||
3041 | #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI configuration */ | ||
3042 | #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX configuration */ | ||
3043 | #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic crossover */ | ||
3044 | #define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended Distance */ | ||
3045 | #define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300 | ||
3046 | #define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */ | ||
3047 | #define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only (Energy Detect) */ | ||
3048 | #define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */ | ||
3049 | #define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */ | ||
3050 | #define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */ | ||
3051 | #define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000 | ||
3052 | #define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12 | ||
3053 | |||
3054 | /* PHY Specific Status Register (Page 0, Register 17) */ | ||
3055 | #define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */ | ||
3056 | #define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */ | ||
3057 | #define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */ | ||
3058 | #define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */ | ||
3059 | #define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */ | ||
3060 | #define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */ | ||
3061 | #define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */ | ||
3062 | #define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */ | ||
3063 | #define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */ | ||
3064 | #define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */ | ||
3065 | #define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */ | ||
3066 | #define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */ | ||
3067 | #define GG82563_PSSR_SPEED_MASK 0xC000 | ||
3068 | #define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */ | ||
3069 | #define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */ | ||
3070 | #define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */ | ||
3071 | |||
3072 | /* PHY Specific Status Register 2 (Page 0, Register 19) */ | ||
3073 | #define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */ | ||
3074 | #define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */ | ||
3075 | #define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */ | ||
3076 | #define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */ | ||
3077 | #define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */ | ||
3078 | #define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */ | ||
3079 | #define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */ | ||
3080 | #define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */ | ||
3081 | #define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */ | ||
3082 | #define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */ | ||
3083 | #define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */ | ||
3084 | #define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */ | ||
3085 | #define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */ | ||
3086 | |||
3087 | /* PHY Specific Control Register 2 (Page 0, Register 26) */ | ||
3088 | #define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative Polarity */ | ||
3089 | #define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C | ||
3090 | #define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal Operation */ | ||
3091 | #define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns Sequence */ | ||
3092 | #define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns Sequence */ | ||
3093 | #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Negotiation */ | ||
3094 | #define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable 1000BASE-T */ | ||
3095 | #define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000 | ||
3096 | #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */ | ||
3097 | #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */ | ||
3098 | |||
3099 | /* MAC Specific Control Register (Page 2, Register 21) */ | ||
3100 | /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ | ||
3101 | #define GG82563_MSCR_TX_CLK_MASK 0x0007 | ||
3102 | #define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004 | ||
3103 | #define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005 | ||
3104 | #define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006 | ||
3105 | #define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007 | ||
3106 | |||
3107 | #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ | ||
3108 | |||
3109 | /* DSP Distance Register (Page 5, Register 26) */ | ||
3110 | #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M; | ||
3111 | 1 = 50-80M; | ||
3112 | 2 = 80-110M; | ||
3113 | 3 = 110-140M; | ||
3114 | 4 = >140M */ | ||
3115 | |||
3116 | /* Kumeran Mode Control Register (Page 193, Register 16) */ | ||
3117 | #define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */ | ||
3118 | #define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */ | ||
3119 | #define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080 | ||
3120 | #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400 | ||
3121 | #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz, 0=0.8MHz */ | ||
3122 | #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 | ||
3123 | |||
3124 | /* Power Management Control Register (Page 193, Register 20) */ | ||
3125 | #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES Electrical Idle */ | ||
3126 | #define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */ | ||
3127 | #define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */ | ||
3128 | #define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse Auto-Negotiation */ | ||
3129 | #define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps Auto-Neg in non D0 */ | ||
3130 | #define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps Auto-Neg Always */ | ||
3131 | #define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a Reverse Auto-Negotiation */ | ||
3132 | #define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */ | ||
3133 | #define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300 | ||
3134 | #define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */ | ||
3135 | #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */ | ||
3136 | #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */ | ||
3137 | #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */ | ||
3138 | |||
3139 | /* In-Band Control Register (Page 194, Register 18) */ | ||
3140 | #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */ | ||
3141 | |||
3142 | |||
3143 | /* Bit definitions for valid PHY IDs. */ | 2858 | /* Bit definitions for valid PHY IDs. */ |
3144 | /* I = Integrated | 2859 | /* I = Integrated |
3145 | * E = External | 2860 | * E = External |
@@ -3154,8 +2869,6 @@ struct e1000_host_command_info { | |||
3154 | #define M88E1011_I_REV_4 0x04 | 2869 | #define M88E1011_I_REV_4 0x04 |
3155 | #define M88E1111_I_PHY_ID 0x01410CC0 | 2870 | #define M88E1111_I_PHY_ID 0x01410CC0 |
3156 | #define L1LXT971A_PHY_ID 0x001378E0 | 2871 | #define L1LXT971A_PHY_ID 0x001378E0 |
3157 | #define GG82563_E_PHY_ID 0x01410CA0 | ||
3158 | |||
3159 | 2872 | ||
3160 | /* Bits... | 2873 | /* Bits... |
3161 | * 15-5: page | 2874 | * 15-5: page |
@@ -3166,41 +2879,41 @@ struct e1000_host_command_info { | |||
3166 | (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) | 2879 | (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) |
3167 | 2880 | ||
3168 | #define IGP3_PHY_PORT_CTRL \ | 2881 | #define IGP3_PHY_PORT_CTRL \ |
3169 | PHY_REG(769, 17) /* Port General Configuration */ | 2882 | PHY_REG(769, 17) /* Port General Configuration */ |
3170 | #define IGP3_PHY_RATE_ADAPT_CTRL \ | 2883 | #define IGP3_PHY_RATE_ADAPT_CTRL \ |
3171 | PHY_REG(769, 25) /* Rate Adapter Control Register */ | 2884 | PHY_REG(769, 25) /* Rate Adapter Control Register */ |
3172 | 2885 | ||
3173 | #define IGP3_KMRN_FIFO_CTRL_STATS \ | 2886 | #define IGP3_KMRN_FIFO_CTRL_STATS \ |
3174 | PHY_REG(770, 16) /* KMRN FIFO's control/status register */ | 2887 | PHY_REG(770, 16) /* KMRN FIFO's control/status register */ |
3175 | #define IGP3_KMRN_POWER_MNG_CTRL \ | 2888 | #define IGP3_KMRN_POWER_MNG_CTRL \ |
3176 | PHY_REG(770, 17) /* KMRN Power Management Control Register */ | 2889 | PHY_REG(770, 17) /* KMRN Power Management Control Register */ |
3177 | #define IGP3_KMRN_INBAND_CTRL \ | 2890 | #define IGP3_KMRN_INBAND_CTRL \ |
3178 | PHY_REG(770, 18) /* KMRN Inband Control Register */ | 2891 | PHY_REG(770, 18) /* KMRN Inband Control Register */ |
3179 | #define IGP3_KMRN_DIAG \ | 2892 | #define IGP3_KMRN_DIAG \ |
3180 | PHY_REG(770, 19) /* KMRN Diagnostic register */ | 2893 | PHY_REG(770, 19) /* KMRN Diagnostic register */ |
3181 | #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */ | 2894 | #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */ |
3182 | #define IGP3_KMRN_ACK_TIMEOUT \ | 2895 | #define IGP3_KMRN_ACK_TIMEOUT \ |
3183 | PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */ | 2896 | PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */ |
3184 | 2897 | ||
3185 | #define IGP3_VR_CTRL \ | 2898 | #define IGP3_VR_CTRL \ |
3186 | PHY_REG(776, 18) /* Voltage regulator control register */ | 2899 | PHY_REG(776, 18) /* Voltage regulator control register */ |
3187 | #define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */ | 2900 | #define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */ |
3188 | #define IGP3_VR_CTRL_MODE_MASK 0x0300 /* Shutdown VR Mask */ | 2901 | #define IGP3_VR_CTRL_MODE_MASK 0x0300 /* Shutdown VR Mask */ |
3189 | 2902 | ||
3190 | #define IGP3_CAPABILITY \ | 2903 | #define IGP3_CAPABILITY \ |
3191 | PHY_REG(776, 19) /* IGP3 Capability Register */ | 2904 | PHY_REG(776, 19) /* IGP3 Capability Register */ |
3192 | 2905 | ||
3193 | /* Capabilities for SKU Control */ | 2906 | /* Capabilities for SKU Control */ |
3194 | #define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */ | 2907 | #define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */ |
3195 | #define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */ | 2908 | #define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */ |
3196 | #define IGP3_CAP_ASF 0x0004 /* Support ASF */ | 2909 | #define IGP3_CAP_ASF 0x0004 /* Support ASF */ |
3197 | #define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */ | 2910 | #define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */ |
3198 | #define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */ | 2911 | #define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */ |
3199 | #define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */ | 2912 | #define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */ |
3200 | #define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */ | 2913 | #define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */ |
3201 | #define IGP3_CAP_RSS 0x0080 /* Support RSS */ | 2914 | #define IGP3_CAP_RSS 0x0080 /* Support RSS */ |
3202 | #define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */ | 2915 | #define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */ |
3203 | #define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */ | 2916 | #define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */ |
3204 | 2917 | ||
3205 | #define IGP3_PPC_JORDAN_EN 0x0001 | 2918 | #define IGP3_PPC_JORDAN_EN 0x0001 |
3206 | #define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002 | 2919 | #define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002 |
@@ -3210,69 +2923,69 @@ struct e1000_host_command_info { | |||
3210 | #define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020 | 2923 | #define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020 |
3211 | #define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040 | 2924 | #define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040 |
3212 | 2925 | ||
3213 | #define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */ | 2926 | #define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */ |
3214 | #define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */ | 2927 | #define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */ |
3215 | 2928 | ||
3216 | #define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18) | 2929 | #define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18) |
3217 | #define IGP3_KMRN_EC_DIS_INBAND 0x0080 | 2930 | #define IGP3_KMRN_EC_DIS_INBAND 0x0080 |
3218 | 2931 | ||
3219 | #define IGP03E1000_E_PHY_ID 0x02A80390 | 2932 | #define IGP03E1000_E_PHY_ID 0x02A80390 |
3220 | #define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */ | 2933 | #define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */ |
3221 | #define IFE_PLUS_E_PHY_ID 0x02A80320 | 2934 | #define IFE_PLUS_E_PHY_ID 0x02A80320 |
3222 | #define IFE_C_E_PHY_ID 0x02A80310 | 2935 | #define IFE_C_E_PHY_ID 0x02A80310 |
3223 | 2936 | ||
3224 | #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */ | 2937 | #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */ |
3225 | #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */ | 2938 | #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */ |
3226 | #define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */ | 2939 | #define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */ |
3227 | #define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet Counter */ | 2940 | #define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnect Counter */ |
3228 | #define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */ | 2941 | #define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */ |
3229 | #define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */ | 2942 | #define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */ |
3230 | #define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */ | 2943 | #define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */ |
3231 | #define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */ | 2944 | #define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */ |
3232 | #define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */ | 2945 | #define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */ |
3233 | #define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */ | 2946 | #define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */ |
3234 | #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */ | 2947 | #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */ |
3235 | #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */ | 2948 | #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */ |
3236 | #define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */ | 2949 | #define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */ |
3237 | 2950 | ||
3238 | #define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto reduced power down */ | 2951 | #define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Default 1 = Disable auto reduced power down */ |
3239 | #define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */ | 2952 | #define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */ |
3240 | #define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */ | 2953 | #define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */ |
3241 | #define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */ | 2954 | #define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */ |
3242 | #define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */ | 2955 | #define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */ |
3243 | #define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */ | 2956 | #define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */ |
3244 | #define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */ | 2957 | #define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */ |
3245 | #define IFE_PESC_POLARITY_REVERSED_SHIFT 8 | 2958 | #define IFE_PESC_POLARITY_REVERSED_SHIFT 8 |
3246 | 2959 | ||
3247 | #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down disabled */ | 2960 | #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dynamic Power Down disabled */ |
3248 | #define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */ | 2961 | #define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */ |
3249 | #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */ | 2962 | #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */ |
3250 | #define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */ | 2963 | #define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */ |
3251 | #define IFE_PSC_FORCE_POLARITY_SHIFT 5 | 2964 | #define IFE_PSC_FORCE_POLARITY_SHIFT 5 |
3252 | #define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4 | 2965 | #define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4 |
3253 | 2966 | ||
3254 | #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */ | 2967 | #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */ |
3255 | #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */ | 2968 | #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */ |
3256 | #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ | 2969 | #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ |
3257 | #define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm is completed */ | 2970 | #define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm is completed */ |
3258 | #define IFE_PMC_MDIX_MODE_SHIFT 6 | 2971 | #define IFE_PMC_MDIX_MODE_SHIFT 6 |
3259 | #define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */ | 2972 | #define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */ |
3260 | 2973 | ||
3261 | #define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */ | 2974 | #define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */ |
3262 | #define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */ | 2975 | #define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */ |
3263 | #define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */ | 2976 | #define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */ |
3264 | #define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */ | 2977 | #define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */ |
3265 | #define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */ | 2978 | #define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */ |
3266 | #define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */ | 2979 | #define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */ |
3267 | #define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */ | 2980 | #define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */ |
3268 | #define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */ | 2981 | #define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */ |
3269 | #define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */ | 2982 | #define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */ |
3270 | #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ | 2983 | #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ |
3271 | #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ | 2984 | #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ |
3272 | 2985 | ||
3273 | #define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ | 2986 | #define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ |
3274 | #define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ | 2987 | #define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ |
3275 | #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ | 2988 | #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ |
3276 | #define ICH_FLASH_SEG_SIZE_256 256 | 2989 | #define ICH_FLASH_SEG_SIZE_256 256 |
3277 | #define ICH_FLASH_SEG_SIZE_4K 4096 | 2990 | #define ICH_FLASH_SEG_SIZE_4K 4096 |
3278 | #define ICH_FLASH_SEG_SIZE_64K 65536 | 2991 | #define ICH_FLASH_SEG_SIZE_64K 65536 |
@@ -3305,74 +3018,6 @@ struct e1000_host_command_info { | |||
3305 | #define ICH_GFPREG_BASE_MASK 0x1FFF | 3018 | #define ICH_GFPREG_BASE_MASK 0x1FFF |
3306 | #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF | 3019 | #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF |
3307 | 3020 | ||
3308 | /* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ | ||
3309 | /* Offset 04h HSFSTS */ | ||
3310 | union ich8_hws_flash_status { | ||
3311 | struct ich8_hsfsts { | ||
3312 | #ifdef __BIG_ENDIAN | ||
3313 | u16 reserved2 :6; | ||
3314 | u16 fldesvalid :1; | ||
3315 | u16 flockdn :1; | ||
3316 | u16 flcdone :1; | ||
3317 | u16 flcerr :1; | ||
3318 | u16 dael :1; | ||
3319 | u16 berasesz :2; | ||
3320 | u16 flcinprog :1; | ||
3321 | u16 reserved1 :2; | ||
3322 | #else | ||
3323 | u16 flcdone :1; /* bit 0 Flash Cycle Done */ | ||
3324 | u16 flcerr :1; /* bit 1 Flash Cycle Error */ | ||
3325 | u16 dael :1; /* bit 2 Direct Access error Log */ | ||
3326 | u16 berasesz :2; /* bit 4:3 Block/Sector Erase Size */ | ||
3327 | u16 flcinprog :1; /* bit 5 flash SPI cycle in Progress */ | ||
3328 | u16 reserved1 :2; /* bit 13:6 Reserved */ | ||
3329 | u16 reserved2 :6; /* bit 13:6 Reserved */ | ||
3330 | u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ | ||
3331 | u16 flockdn :1; /* bit 15 Flash Configuration Lock-Down */ | ||
3332 | #endif | ||
3333 | } hsf_status; | ||
3334 | u16 regval; | ||
3335 | }; | ||
3336 | |||
3337 | /* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */ | ||
3338 | /* Offset 06h FLCTL */ | ||
3339 | union ich8_hws_flash_ctrl { | ||
3340 | struct ich8_hsflctl { | ||
3341 | #ifdef __BIG_ENDIAN | ||
3342 | u16 fldbcount :2; | ||
3343 | u16 flockdn :6; | ||
3344 | u16 flcgo :1; | ||
3345 | u16 flcycle :2; | ||
3346 | u16 reserved :5; | ||
3347 | #else | ||
3348 | u16 flcgo :1; /* 0 Flash Cycle Go */ | ||
3349 | u16 flcycle :2; /* 2:1 Flash Cycle */ | ||
3350 | u16 reserved :5; /* 7:3 Reserved */ | ||
3351 | u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ | ||
3352 | u16 flockdn :6; /* 15:10 Reserved */ | ||
3353 | #endif | ||
3354 | } hsf_ctrl; | ||
3355 | u16 regval; | ||
3356 | }; | ||
3357 | |||
3358 | /* ICH8 Flash Region Access Permissions */ | ||
3359 | union ich8_hws_flash_regacc { | ||
3360 | struct ich8_flracc { | ||
3361 | #ifdef __BIG_ENDIAN | ||
3362 | u32 gmwag :8; | ||
3363 | u32 gmrag :8; | ||
3364 | u32 grwa :8; | ||
3365 | u32 grra :8; | ||
3366 | #else | ||
3367 | u32 grra :8; /* 0:7 GbE region Read Access */ | ||
3368 | u32 grwa :8; /* 8:15 GbE region Write Access */ | ||
3369 | u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ | ||
3370 | u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ | ||
3371 | #endif | ||
3372 | } hsf_flregacc; | ||
3373 | u16 regval; | ||
3374 | }; | ||
3375 | |||
3376 | /* Miscellaneous PHY bit definitions. */ | 3021 | /* Miscellaneous PHY bit definitions. */ |
3377 | #define PHY_PREAMBLE 0xFFFFFFFF | 3022 | #define PHY_PREAMBLE 0xFFFFFFFF |
3378 | #define PHY_SOF 0x01 | 3023 | #define PHY_SOF 0x01 |
@@ -3384,10 +3029,10 @@ union ich8_hws_flash_regacc { | |||
3384 | #define MII_CR_SPEED_100 0x2000 | 3029 | #define MII_CR_SPEED_100 0x2000 |
3385 | #define MII_CR_SPEED_10 0x0000 | 3030 | #define MII_CR_SPEED_10 0x0000 |
3386 | #define E1000_PHY_ADDRESS 0x01 | 3031 | #define E1000_PHY_ADDRESS 0x01 |
3387 | #define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ | 3032 | #define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ |
3388 | #define PHY_FORCE_TIME 20 /* 2.0 Seconds */ | 3033 | #define PHY_FORCE_TIME 20 /* 2.0 Seconds */ |
3389 | #define PHY_REVISION_MASK 0xFFFFFFF0 | 3034 | #define PHY_REVISION_MASK 0xFFFFFFF0 |
3390 | #define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ | 3035 | #define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ |
3391 | #define REG4_SPEED_MASK 0x01E0 | 3036 | #define REG4_SPEED_MASK 0x01E0 |
3392 | #define REG9_SPEED_MASK 0x0300 | 3037 | #define REG9_SPEED_MASK 0x0300 |
3393 | #define ADVERTISE_10_HALF 0x0001 | 3038 | #define ADVERTISE_10_HALF 0x0001 |
@@ -3396,8 +3041,8 @@ union ich8_hws_flash_regacc { | |||
3396 | #define ADVERTISE_100_FULL 0x0008 | 3041 | #define ADVERTISE_100_FULL 0x0008 |
3397 | #define ADVERTISE_1000_HALF 0x0010 | 3042 | #define ADVERTISE_1000_HALF 0x0010 |
3398 | #define ADVERTISE_1000_FULL 0x0020 | 3043 | #define ADVERTISE_1000_FULL 0x0020 |
3399 | #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ | 3044 | #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ |
3400 | #define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/ | 3045 | #define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */ |
3401 | #define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/ | 3046 | #define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */ |
3402 | 3047 | ||
3403 | #endif /* _E1000_HW_H_ */ | 3048 | #endif /* _E1000_HW_H_ */ |
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c index c66dd4f9437c..bcd192ca47b0 100644 --- a/drivers/net/e1000/e1000_main.c +++ b/drivers/net/e1000/e1000_main.c | |||
@@ -31,7 +31,7 @@ | |||
31 | 31 | ||
32 | char e1000_driver_name[] = "e1000"; | 32 | char e1000_driver_name[] = "e1000"; |
33 | static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver"; | 33 | static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver"; |
34 | #define DRV_VERSION "7.3.21-k3-NAPI" | 34 | #define DRV_VERSION "7.3.21-k5-NAPI" |
35 | const char e1000_driver_version[] = DRV_VERSION; | 35 | const char e1000_driver_version[] = DRV_VERSION; |
36 | static const char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation."; | 36 | static const char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation."; |
37 | 37 | ||
@@ -131,7 +131,6 @@ static struct net_device_stats * e1000_get_stats(struct net_device *netdev); | |||
131 | static int e1000_change_mtu(struct net_device *netdev, int new_mtu); | 131 | static int e1000_change_mtu(struct net_device *netdev, int new_mtu); |
132 | static int e1000_set_mac(struct net_device *netdev, void *p); | 132 | static int e1000_set_mac(struct net_device *netdev, void *p); |
133 | static irqreturn_t e1000_intr(int irq, void *data); | 133 | static irqreturn_t e1000_intr(int irq, void *data); |
134 | static irqreturn_t e1000_intr_msi(int irq, void *data); | ||
135 | static bool e1000_clean_tx_irq(struct e1000_adapter *adapter, | 134 | static bool e1000_clean_tx_irq(struct e1000_adapter *adapter, |
136 | struct e1000_tx_ring *tx_ring); | 135 | struct e1000_tx_ring *tx_ring); |
137 | static int e1000_clean(struct napi_struct *napi, int budget); | 136 | static int e1000_clean(struct napi_struct *napi, int budget); |
@@ -258,25 +257,14 @@ module_exit(e1000_exit_module); | |||
258 | 257 | ||
259 | static int e1000_request_irq(struct e1000_adapter *adapter) | 258 | static int e1000_request_irq(struct e1000_adapter *adapter) |
260 | { | 259 | { |
261 | struct e1000_hw *hw = &adapter->hw; | ||
262 | struct net_device *netdev = adapter->netdev; | 260 | struct net_device *netdev = adapter->netdev; |
263 | irq_handler_t handler = e1000_intr; | 261 | irq_handler_t handler = e1000_intr; |
264 | int irq_flags = IRQF_SHARED; | 262 | int irq_flags = IRQF_SHARED; |
265 | int err; | 263 | int err; |
266 | 264 | ||
267 | if (hw->mac_type >= e1000_82571) { | ||
268 | adapter->have_msi = !pci_enable_msi(adapter->pdev); | ||
269 | if (adapter->have_msi) { | ||
270 | handler = e1000_intr_msi; | ||
271 | irq_flags = 0; | ||
272 | } | ||
273 | } | ||
274 | |||
275 | err = request_irq(adapter->pdev->irq, handler, irq_flags, netdev->name, | 265 | err = request_irq(adapter->pdev->irq, handler, irq_flags, netdev->name, |
276 | netdev); | 266 | netdev); |
277 | if (err) { | 267 | if (err) { |
278 | if (adapter->have_msi) | ||
279 | pci_disable_msi(adapter->pdev); | ||
280 | DPRINTK(PROBE, ERR, | 268 | DPRINTK(PROBE, ERR, |
281 | "Unable to allocate interrupt Error: %d\n", err); | 269 | "Unable to allocate interrupt Error: %d\n", err); |
282 | } | 270 | } |
@@ -289,9 +277,6 @@ static void e1000_free_irq(struct e1000_adapter *adapter) | |||
289 | struct net_device *netdev = adapter->netdev; | 277 | struct net_device *netdev = adapter->netdev; |
290 | 278 | ||
291 | free_irq(adapter->pdev->irq, netdev); | 279 | free_irq(adapter->pdev->irq, netdev); |
292 | |||
293 | if (adapter->have_msi) | ||
294 | pci_disable_msi(adapter->pdev); | ||
295 | } | 280 | } |
296 | 281 | ||
297 | /** | 282 | /** |
@@ -345,76 +330,6 @@ static void e1000_update_mng_vlan(struct e1000_adapter *adapter) | |||
345 | } | 330 | } |
346 | } | 331 | } |
347 | 332 | ||
348 | /** | ||
349 | * e1000_release_hw_control - release control of the h/w to f/w | ||
350 | * @adapter: address of board private structure | ||
351 | * | ||
352 | * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. | ||
353 | * For ASF and Pass Through versions of f/w this means that the | ||
354 | * driver is no longer loaded. For AMT version (only with 82573) i | ||
355 | * of the f/w this means that the network i/f is closed. | ||
356 | * | ||
357 | **/ | ||
358 | |||
359 | static void e1000_release_hw_control(struct e1000_adapter *adapter) | ||
360 | { | ||
361 | u32 ctrl_ext; | ||
362 | u32 swsm; | ||
363 | struct e1000_hw *hw = &adapter->hw; | ||
364 | |||
365 | /* Let firmware taken over control of h/w */ | ||
366 | switch (hw->mac_type) { | ||
367 | case e1000_82573: | ||
368 | swsm = er32(SWSM); | ||
369 | ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); | ||
370 | break; | ||
371 | case e1000_82571: | ||
372 | case e1000_82572: | ||
373 | case e1000_80003es2lan: | ||
374 | case e1000_ich8lan: | ||
375 | ctrl_ext = er32(CTRL_EXT); | ||
376 | ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); | ||
377 | break; | ||
378 | default: | ||
379 | break; | ||
380 | } | ||
381 | } | ||
382 | |||
383 | /** | ||
384 | * e1000_get_hw_control - get control of the h/w from f/w | ||
385 | * @adapter: address of board private structure | ||
386 | * | ||
387 | * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit. | ||
388 | * For ASF and Pass Through versions of f/w this means that | ||
389 | * the driver is loaded. For AMT version (only with 82573) | ||
390 | * of the f/w this means that the network i/f is open. | ||
391 | * | ||
392 | **/ | ||
393 | |||
394 | static void e1000_get_hw_control(struct e1000_adapter *adapter) | ||
395 | { | ||
396 | u32 ctrl_ext; | ||
397 | u32 swsm; | ||
398 | struct e1000_hw *hw = &adapter->hw; | ||
399 | |||
400 | /* Let firmware know the driver has taken over */ | ||
401 | switch (hw->mac_type) { | ||
402 | case e1000_82573: | ||
403 | swsm = er32(SWSM); | ||
404 | ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); | ||
405 | break; | ||
406 | case e1000_82571: | ||
407 | case e1000_82572: | ||
408 | case e1000_80003es2lan: | ||
409 | case e1000_ich8lan: | ||
410 | ctrl_ext = er32(CTRL_EXT); | ||
411 | ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); | ||
412 | break; | ||
413 | default: | ||
414 | break; | ||
415 | } | ||
416 | } | ||
417 | |||
418 | static void e1000_init_manageability(struct e1000_adapter *adapter) | 333 | static void e1000_init_manageability(struct e1000_adapter *adapter) |
419 | { | 334 | { |
420 | struct e1000_hw *hw = &adapter->hw; | 335 | struct e1000_hw *hw = &adapter->hw; |
@@ -425,20 +340,6 @@ static void e1000_init_manageability(struct e1000_adapter *adapter) | |||
425 | /* disable hardware interception of ARP */ | 340 | /* disable hardware interception of ARP */ |
426 | manc &= ~(E1000_MANC_ARP_EN); | 341 | manc &= ~(E1000_MANC_ARP_EN); |
427 | 342 | ||
428 | /* enable receiving management packets to the host */ | ||
429 | /* this will probably generate destination unreachable messages | ||
430 | * from the host OS, but the packets will be handled on SMBUS */ | ||
431 | if (hw->has_manc2h) { | ||
432 | u32 manc2h = er32(MANC2H); | ||
433 | |||
434 | manc |= E1000_MANC_EN_MNG2HOST; | ||
435 | #define E1000_MNG2HOST_PORT_623 (1 << 5) | ||
436 | #define E1000_MNG2HOST_PORT_664 (1 << 6) | ||
437 | manc2h |= E1000_MNG2HOST_PORT_623; | ||
438 | manc2h |= E1000_MNG2HOST_PORT_664; | ||
439 | ew32(MANC2H, manc2h); | ||
440 | } | ||
441 | |||
442 | ew32(MANC, manc); | 343 | ew32(MANC, manc); |
443 | } | 344 | } |
444 | } | 345 | } |
@@ -453,12 +354,6 @@ static void e1000_release_manageability(struct e1000_adapter *adapter) | |||
453 | /* re-enable hardware interception of ARP */ | 354 | /* re-enable hardware interception of ARP */ |
454 | manc |= E1000_MANC_ARP_EN; | 355 | manc |= E1000_MANC_ARP_EN; |
455 | 356 | ||
456 | if (hw->has_manc2h) | ||
457 | manc &= ~E1000_MANC_EN_MNG2HOST; | ||
458 | |||
459 | /* don't explicitly have to mess with MANC2H since | ||
460 | * MANC has an enable disable that gates MANC2H */ | ||
461 | |||
462 | ew32(MANC, manc); | 357 | ew32(MANC, manc); |
463 | } | 358 | } |
464 | } | 359 | } |
@@ -563,15 +458,6 @@ static void e1000_power_down_phy(struct e1000_adapter *adapter) | |||
563 | if (er32(MANC) & E1000_MANC_SMBUS_EN) | 458 | if (er32(MANC) & E1000_MANC_SMBUS_EN) |
564 | goto out; | 459 | goto out; |
565 | break; | 460 | break; |
566 | case e1000_82571: | ||
567 | case e1000_82572: | ||
568 | case e1000_82573: | ||
569 | case e1000_80003es2lan: | ||
570 | case e1000_ich8lan: | ||
571 | if (e1000_check_mng_mode(hw) || | ||
572 | e1000_check_phy_reset_block(hw)) | ||
573 | goto out; | ||
574 | break; | ||
575 | default: | 461 | default: |
576 | goto out; | 462 | goto out; |
577 | } | 463 | } |
@@ -599,8 +485,7 @@ void e1000_down(struct e1000_adapter *adapter) | |||
599 | ew32(RCTL, rctl & ~E1000_RCTL_EN); | 485 | ew32(RCTL, rctl & ~E1000_RCTL_EN); |
600 | /* flush and sleep below */ | 486 | /* flush and sleep below */ |
601 | 487 | ||
602 | /* can be netif_tx_disable when NETIF_F_LLTX is removed */ | 488 | netif_tx_disable(netdev); |
603 | netif_stop_queue(netdev); | ||
604 | 489 | ||
605 | /* disable transmits in the hardware */ | 490 | /* disable transmits in the hardware */ |
606 | tctl = er32(TCTL); | 491 | tctl = er32(TCTL); |
@@ -671,16 +556,6 @@ void e1000_reset(struct e1000_adapter *adapter) | |||
671 | legacy_pba_adjust = true; | 556 | legacy_pba_adjust = true; |
672 | pba = E1000_PBA_30K; | 557 | pba = E1000_PBA_30K; |
673 | break; | 558 | break; |
674 | case e1000_82571: | ||
675 | case e1000_82572: | ||
676 | case e1000_80003es2lan: | ||
677 | pba = E1000_PBA_38K; | ||
678 | break; | ||
679 | case e1000_82573: | ||
680 | pba = E1000_PBA_20K; | ||
681 | break; | ||
682 | case e1000_ich8lan: | ||
683 | pba = E1000_PBA_8K; | ||
684 | case e1000_undefined: | 559 | case e1000_undefined: |
685 | case e1000_num_macs: | 560 | case e1000_num_macs: |
686 | break; | 561 | break; |
@@ -744,16 +619,8 @@ void e1000_reset(struct e1000_adapter *adapter) | |||
744 | 619 | ||
745 | /* if short on rx space, rx wins and must trump tx | 620 | /* if short on rx space, rx wins and must trump tx |
746 | * adjustment or use Early Receive if available */ | 621 | * adjustment or use Early Receive if available */ |
747 | if (pba < min_rx_space) { | 622 | if (pba < min_rx_space) |
748 | switch (hw->mac_type) { | 623 | pba = min_rx_space; |
749 | case e1000_82573: | ||
750 | /* ERT enabled in e1000_configure_rx */ | ||
751 | break; | ||
752 | default: | ||
753 | pba = min_rx_space; | ||
754 | break; | ||
755 | } | ||
756 | } | ||
757 | } | 624 | } |
758 | } | 625 | } |
759 | 626 | ||
@@ -789,7 +656,6 @@ void e1000_reset(struct e1000_adapter *adapter) | |||
789 | 656 | ||
790 | /* if (adapter->hwflags & HWFLAGS_PHY_PWR_BIT) { */ | 657 | /* if (adapter->hwflags & HWFLAGS_PHY_PWR_BIT) { */ |
791 | if (hw->mac_type >= e1000_82544 && | 658 | if (hw->mac_type >= e1000_82544 && |
792 | hw->mac_type <= e1000_82547_rev_2 && | ||
793 | hw->autoneg == 1 && | 659 | hw->autoneg == 1 && |
794 | hw->autoneg_advertised == ADVERTISE_1000_FULL) { | 660 | hw->autoneg_advertised == ADVERTISE_1000_FULL) { |
795 | u32 ctrl = er32(CTRL); | 661 | u32 ctrl = er32(CTRL); |
@@ -806,20 +672,6 @@ void e1000_reset(struct e1000_adapter *adapter) | |||
806 | e1000_reset_adaptive(hw); | 672 | e1000_reset_adaptive(hw); |
807 | e1000_phy_get_info(hw, &adapter->phy_info); | 673 | e1000_phy_get_info(hw, &adapter->phy_info); |
808 | 674 | ||
809 | if (!adapter->smart_power_down && | ||
810 | (hw->mac_type == e1000_82571 || | ||
811 | hw->mac_type == e1000_82572)) { | ||
812 | u16 phy_data = 0; | ||
813 | /* speed up time to link by disabling smart power down, ignore | ||
814 | * the return value of this function because there is nothing | ||
815 | * different we would do if it failed */ | ||
816 | e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, | ||
817 | &phy_data); | ||
818 | phy_data &= ~IGP02E1000_PM_SPD; | ||
819 | e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, | ||
820 | phy_data); | ||
821 | } | ||
822 | |||
823 | e1000_release_manageability(adapter); | 675 | e1000_release_manageability(adapter); |
824 | } | 676 | } |
825 | 677 | ||
@@ -1046,17 +898,6 @@ static int __devinit e1000_probe(struct pci_dev *pdev, | |||
1046 | goto err_sw_init; | 898 | goto err_sw_init; |
1047 | 899 | ||
1048 | err = -EIO; | 900 | err = -EIO; |
1049 | /* Flash BAR mapping must happen after e1000_sw_init | ||
1050 | * because it depends on mac_type */ | ||
1051 | if ((hw->mac_type == e1000_ich8lan) && | ||
1052 | (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) { | ||
1053 | hw->flash_address = pci_ioremap_bar(pdev, 1); | ||
1054 | if (!hw->flash_address) | ||
1055 | goto err_flashmap; | ||
1056 | } | ||
1057 | |||
1058 | if (e1000_check_phy_reset_block(hw)) | ||
1059 | DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n"); | ||
1060 | 901 | ||
1061 | if (hw->mac_type >= e1000_82543) { | 902 | if (hw->mac_type >= e1000_82543) { |
1062 | netdev->features = NETIF_F_SG | | 903 | netdev->features = NETIF_F_SG | |
@@ -1064,21 +905,16 @@ static int __devinit e1000_probe(struct pci_dev *pdev, | |||
1064 | NETIF_F_HW_VLAN_TX | | 905 | NETIF_F_HW_VLAN_TX | |
1065 | NETIF_F_HW_VLAN_RX | | 906 | NETIF_F_HW_VLAN_RX | |
1066 | NETIF_F_HW_VLAN_FILTER; | 907 | NETIF_F_HW_VLAN_FILTER; |
1067 | if (hw->mac_type == e1000_ich8lan) | ||
1068 | netdev->features &= ~NETIF_F_HW_VLAN_FILTER; | ||
1069 | } | 908 | } |
1070 | 909 | ||
1071 | if ((hw->mac_type >= e1000_82544) && | 910 | if ((hw->mac_type >= e1000_82544) && |
1072 | (hw->mac_type != e1000_82547)) | 911 | (hw->mac_type != e1000_82547)) |
1073 | netdev->features |= NETIF_F_TSO; | 912 | netdev->features |= NETIF_F_TSO; |
1074 | 913 | ||
1075 | if (hw->mac_type > e1000_82547_rev_2) | ||
1076 | netdev->features |= NETIF_F_TSO6; | ||
1077 | if (pci_using_dac) | 914 | if (pci_using_dac) |
1078 | netdev->features |= NETIF_F_HIGHDMA; | 915 | netdev->features |= NETIF_F_HIGHDMA; |
1079 | 916 | ||
1080 | netdev->vlan_features |= NETIF_F_TSO; | 917 | netdev->vlan_features |= NETIF_F_TSO; |
1081 | netdev->vlan_features |= NETIF_F_TSO6; | ||
1082 | netdev->vlan_features |= NETIF_F_HW_CSUM; | 918 | netdev->vlan_features |= NETIF_F_HW_CSUM; |
1083 | netdev->vlan_features |= NETIF_F_SG; | 919 | netdev->vlan_features |= NETIF_F_SG; |
1084 | 920 | ||
@@ -1153,15 +989,8 @@ static int __devinit e1000_probe(struct pci_dev *pdev, | |||
1153 | EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); | 989 | EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); |
1154 | eeprom_apme_mask = E1000_EEPROM_82544_APM; | 990 | eeprom_apme_mask = E1000_EEPROM_82544_APM; |
1155 | break; | 991 | break; |
1156 | case e1000_ich8lan: | ||
1157 | e1000_read_eeprom(hw, | ||
1158 | EEPROM_INIT_CONTROL1_REG, 1, &eeprom_data); | ||
1159 | eeprom_apme_mask = E1000_EEPROM_ICH8_APME; | ||
1160 | break; | ||
1161 | case e1000_82546: | 992 | case e1000_82546: |
1162 | case e1000_82546_rev_3: | 993 | case e1000_82546_rev_3: |
1163 | case e1000_82571: | ||
1164 | case e1000_80003es2lan: | ||
1165 | if (er32(STATUS) & E1000_STATUS_FUNC_1){ | 994 | if (er32(STATUS) & E1000_STATUS_FUNC_1){ |
1166 | e1000_read_eeprom(hw, | 995 | e1000_read_eeprom(hw, |
1167 | EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); | 996 | EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); |
@@ -1185,17 +1014,12 @@ static int __devinit e1000_probe(struct pci_dev *pdev, | |||
1185 | break; | 1014 | break; |
1186 | case E1000_DEV_ID_82546EB_FIBER: | 1015 | case E1000_DEV_ID_82546EB_FIBER: |
1187 | case E1000_DEV_ID_82546GB_FIBER: | 1016 | case E1000_DEV_ID_82546GB_FIBER: |
1188 | case E1000_DEV_ID_82571EB_FIBER: | ||
1189 | /* Wake events only supported on port A for dual fiber | 1017 | /* Wake events only supported on port A for dual fiber |
1190 | * regardless of eeprom setting */ | 1018 | * regardless of eeprom setting */ |
1191 | if (er32(STATUS) & E1000_STATUS_FUNC_1) | 1019 | if (er32(STATUS) & E1000_STATUS_FUNC_1) |
1192 | adapter->eeprom_wol = 0; | 1020 | adapter->eeprom_wol = 0; |
1193 | break; | 1021 | break; |
1194 | case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: | 1022 | case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: |
1195 | case E1000_DEV_ID_82571EB_QUAD_COPPER: | ||
1196 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | ||
1197 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: | ||
1198 | case E1000_DEV_ID_82571PT_QUAD_COPPER: | ||
1199 | /* if quad port adapter, disable WoL on all but port A */ | 1023 | /* if quad port adapter, disable WoL on all but port A */ |
1200 | if (global_quad_port_a != 0) | 1024 | if (global_quad_port_a != 0) |
1201 | adapter->eeprom_wol = 0; | 1025 | adapter->eeprom_wol = 0; |
@@ -1213,39 +1037,18 @@ static int __devinit e1000_probe(struct pci_dev *pdev, | |||
1213 | 1037 | ||
1214 | /* print bus type/speed/width info */ | 1038 | /* print bus type/speed/width info */ |
1215 | DPRINTK(PROBE, INFO, "(PCI%s:%s:%s) ", | 1039 | DPRINTK(PROBE, INFO, "(PCI%s:%s:%s) ", |
1216 | ((hw->bus_type == e1000_bus_type_pcix) ? "-X" : | 1040 | ((hw->bus_type == e1000_bus_type_pcix) ? "-X" : ""), |
1217 | (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")), | 1041 | ((hw->bus_speed == e1000_bus_speed_133) ? "133MHz" : |
1218 | ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" : | ||
1219 | (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" : | ||
1220 | (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" : | 1042 | (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" : |
1221 | (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" : | 1043 | (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" : |
1222 | (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"), | 1044 | (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"), |
1223 | ((hw->bus_width == e1000_bus_width_64) ? "64-bit" : | 1045 | ((hw->bus_width == e1000_bus_width_64) ? "64-bit" : "32-bit")); |
1224 | (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" : | ||
1225 | (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" : | ||
1226 | "32-bit")); | ||
1227 | 1046 | ||
1228 | printk("%pM\n", netdev->dev_addr); | 1047 | printk("%pM\n", netdev->dev_addr); |
1229 | 1048 | ||
1230 | if (hw->bus_type == e1000_bus_type_pci_express) { | ||
1231 | DPRINTK(PROBE, WARNING, "This device (id %04x:%04x) will no " | ||
1232 | "longer be supported by this driver in the future.\n", | ||
1233 | pdev->vendor, pdev->device); | ||
1234 | DPRINTK(PROBE, WARNING, "please use the \"e1000e\" " | ||
1235 | "driver instead.\n"); | ||
1236 | } | ||
1237 | |||
1238 | /* reset the hardware with the new settings */ | 1049 | /* reset the hardware with the new settings */ |
1239 | e1000_reset(adapter); | 1050 | e1000_reset(adapter); |
1240 | 1051 | ||
1241 | /* If the controller is 82573 and f/w is AMT, do not set | ||
1242 | * DRV_LOAD until the interface is up. For all other cases, | ||
1243 | * let the f/w know that the h/w is now under the control | ||
1244 | * of the driver. */ | ||
1245 | if (hw->mac_type != e1000_82573 || | ||
1246 | !e1000_check_mng_mode(hw)) | ||
1247 | e1000_get_hw_control(adapter); | ||
1248 | |||
1249 | strcpy(netdev->name, "eth%d"); | 1052 | strcpy(netdev->name, "eth%d"); |
1250 | err = register_netdev(netdev); | 1053 | err = register_netdev(netdev); |
1251 | if (err) | 1054 | if (err) |
@@ -1260,14 +1063,11 @@ static int __devinit e1000_probe(struct pci_dev *pdev, | |||
1260 | return 0; | 1063 | return 0; |
1261 | 1064 | ||
1262 | err_register: | 1065 | err_register: |
1263 | e1000_release_hw_control(adapter); | ||
1264 | err_eeprom: | 1066 | err_eeprom: |
1265 | if (!e1000_check_phy_reset_block(hw)) | 1067 | e1000_phy_hw_reset(hw); |
1266 | e1000_phy_hw_reset(hw); | ||
1267 | 1068 | ||
1268 | if (hw->flash_address) | 1069 | if (hw->flash_address) |
1269 | iounmap(hw->flash_address); | 1070 | iounmap(hw->flash_address); |
1270 | err_flashmap: | ||
1271 | kfree(adapter->tx_ring); | 1071 | kfree(adapter->tx_ring); |
1272 | kfree(adapter->rx_ring); | 1072 | kfree(adapter->rx_ring); |
1273 | err_sw_init: | 1073 | err_sw_init: |
@@ -1298,18 +1098,18 @@ static void __devexit e1000_remove(struct pci_dev *pdev) | |||
1298 | struct e1000_adapter *adapter = netdev_priv(netdev); | 1098 | struct e1000_adapter *adapter = netdev_priv(netdev); |
1299 | struct e1000_hw *hw = &adapter->hw; | 1099 | struct e1000_hw *hw = &adapter->hw; |
1300 | 1100 | ||
1101 | set_bit(__E1000_DOWN, &adapter->flags); | ||
1102 | del_timer_sync(&adapter->tx_fifo_stall_timer); | ||
1103 | del_timer_sync(&adapter->watchdog_timer); | ||
1104 | del_timer_sync(&adapter->phy_info_timer); | ||
1105 | |||
1301 | cancel_work_sync(&adapter->reset_task); | 1106 | cancel_work_sync(&adapter->reset_task); |
1302 | 1107 | ||
1303 | e1000_release_manageability(adapter); | 1108 | e1000_release_manageability(adapter); |
1304 | 1109 | ||
1305 | /* Release control of h/w to f/w. If f/w is AMT enabled, this | ||
1306 | * would have already happened in close and is redundant. */ | ||
1307 | e1000_release_hw_control(adapter); | ||
1308 | |||
1309 | unregister_netdev(netdev); | 1110 | unregister_netdev(netdev); |
1310 | 1111 | ||
1311 | if (!e1000_check_phy_reset_block(hw)) | 1112 | e1000_phy_hw_reset(hw); |
1312 | e1000_phy_hw_reset(hw); | ||
1313 | 1113 | ||
1314 | kfree(adapter->tx_ring); | 1114 | kfree(adapter->tx_ring); |
1315 | kfree(adapter->rx_ring); | 1115 | kfree(adapter->rx_ring); |
@@ -1472,12 +1272,6 @@ static int e1000_open(struct net_device *netdev) | |||
1472 | e1000_update_mng_vlan(adapter); | 1272 | e1000_update_mng_vlan(adapter); |
1473 | } | 1273 | } |
1474 | 1274 | ||
1475 | /* If AMT is enabled, let the firmware know that the network | ||
1476 | * interface is now open */ | ||
1477 | if (hw->mac_type == e1000_82573 && | ||
1478 | e1000_check_mng_mode(hw)) | ||
1479 | e1000_get_hw_control(adapter); | ||
1480 | |||
1481 | /* before we allocate an interrupt, we must be ready to handle it. | 1275 | /* before we allocate an interrupt, we must be ready to handle it. |
1482 | * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt | 1276 | * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt |
1483 | * as soon as we call pci_request_irq, so we have to setup our | 1277 | * as soon as we call pci_request_irq, so we have to setup our |
@@ -1503,7 +1297,6 @@ static int e1000_open(struct net_device *netdev) | |||
1503 | return E1000_SUCCESS; | 1297 | return E1000_SUCCESS; |
1504 | 1298 | ||
1505 | err_req_irq: | 1299 | err_req_irq: |
1506 | e1000_release_hw_control(adapter); | ||
1507 | e1000_power_down_phy(adapter); | 1300 | e1000_power_down_phy(adapter); |
1508 | e1000_free_all_rx_resources(adapter); | 1301 | e1000_free_all_rx_resources(adapter); |
1509 | err_setup_rx: | 1302 | err_setup_rx: |
@@ -1548,12 +1341,6 @@ static int e1000_close(struct net_device *netdev) | |||
1548 | e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); | 1341 | e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); |
1549 | } | 1342 | } |
1550 | 1343 | ||
1551 | /* If AMT is enabled, let the firmware know that the network | ||
1552 | * interface is now closed */ | ||
1553 | if (hw->mac_type == e1000_82573 && | ||
1554 | e1000_check_mng_mode(hw)) | ||
1555 | e1000_release_hw_control(adapter); | ||
1556 | |||
1557 | return 0; | 1344 | return 0; |
1558 | } | 1345 | } |
1559 | 1346 | ||
@@ -1692,7 +1479,7 @@ static void e1000_configure_tx(struct e1000_adapter *adapter) | |||
1692 | { | 1479 | { |
1693 | u64 tdba; | 1480 | u64 tdba; |
1694 | struct e1000_hw *hw = &adapter->hw; | 1481 | struct e1000_hw *hw = &adapter->hw; |
1695 | u32 tdlen, tctl, tipg, tarc; | 1482 | u32 tdlen, tctl, tipg; |
1696 | u32 ipgr1, ipgr2; | 1483 | u32 ipgr1, ipgr2; |
1697 | 1484 | ||
1698 | /* Setup the HW Tx Head and Tail descriptor pointers */ | 1485 | /* Setup the HW Tx Head and Tail descriptor pointers */ |
@@ -1714,8 +1501,7 @@ static void e1000_configure_tx(struct e1000_adapter *adapter) | |||
1714 | } | 1501 | } |
1715 | 1502 | ||
1716 | /* Set the default values for the Tx Inter Packet Gap timer */ | 1503 | /* Set the default values for the Tx Inter Packet Gap timer */ |
1717 | if (hw->mac_type <= e1000_82547_rev_2 && | 1504 | if ((hw->media_type == e1000_media_type_fiber || |
1718 | (hw->media_type == e1000_media_type_fiber || | ||
1719 | hw->media_type == e1000_media_type_internal_serdes)) | 1505 | hw->media_type == e1000_media_type_internal_serdes)) |
1720 | tipg = DEFAULT_82543_TIPG_IPGT_FIBER; | 1506 | tipg = DEFAULT_82543_TIPG_IPGT_FIBER; |
1721 | else | 1507 | else |
@@ -1728,10 +1514,6 @@ static void e1000_configure_tx(struct e1000_adapter *adapter) | |||
1728 | ipgr1 = DEFAULT_82542_TIPG_IPGR1; | 1514 | ipgr1 = DEFAULT_82542_TIPG_IPGR1; |
1729 | ipgr2 = DEFAULT_82542_TIPG_IPGR2; | 1515 | ipgr2 = DEFAULT_82542_TIPG_IPGR2; |
1730 | break; | 1516 | break; |
1731 | case e1000_80003es2lan: | ||
1732 | ipgr1 = DEFAULT_82543_TIPG_IPGR1; | ||
1733 | ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; | ||
1734 | break; | ||
1735 | default: | 1517 | default: |
1736 | ipgr1 = DEFAULT_82543_TIPG_IPGR1; | 1518 | ipgr1 = DEFAULT_82543_TIPG_IPGR1; |
1737 | ipgr2 = DEFAULT_82543_TIPG_IPGR2; | 1519 | ipgr2 = DEFAULT_82543_TIPG_IPGR2; |
@@ -1754,21 +1536,6 @@ static void e1000_configure_tx(struct e1000_adapter *adapter) | |||
1754 | tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | | 1536 | tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | |
1755 | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); | 1537 | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); |
1756 | 1538 | ||
1757 | if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { | ||
1758 | tarc = er32(TARC0); | ||
1759 | /* set the speed mode bit, we'll clear it if we're not at | ||
1760 | * gigabit link later */ | ||
1761 | tarc |= (1 << 21); | ||
1762 | ew32(TARC0, tarc); | ||
1763 | } else if (hw->mac_type == e1000_80003es2lan) { | ||
1764 | tarc = er32(TARC0); | ||
1765 | tarc |= 1; | ||
1766 | ew32(TARC0, tarc); | ||
1767 | tarc = er32(TARC1); | ||
1768 | tarc |= 1; | ||
1769 | ew32(TARC1, tarc); | ||
1770 | } | ||
1771 | |||
1772 | e1000_config_collision_dist(hw); | 1539 | e1000_config_collision_dist(hw); |
1773 | 1540 | ||
1774 | /* Setup Transmit Descriptor Settings for eop descriptor */ | 1541 | /* Setup Transmit Descriptor Settings for eop descriptor */ |
@@ -1804,7 +1571,6 @@ static void e1000_configure_tx(struct e1000_adapter *adapter) | |||
1804 | static int e1000_setup_rx_resources(struct e1000_adapter *adapter, | 1571 | static int e1000_setup_rx_resources(struct e1000_adapter *adapter, |
1805 | struct e1000_rx_ring *rxdr) | 1572 | struct e1000_rx_ring *rxdr) |
1806 | { | 1573 | { |
1807 | struct e1000_hw *hw = &adapter->hw; | ||
1808 | struct pci_dev *pdev = adapter->pdev; | 1574 | struct pci_dev *pdev = adapter->pdev; |
1809 | int size, desc_len; | 1575 | int size, desc_len; |
1810 | 1576 | ||
@@ -1817,10 +1583,7 @@ static int e1000_setup_rx_resources(struct e1000_adapter *adapter, | |||
1817 | } | 1583 | } |
1818 | memset(rxdr->buffer_info, 0, size); | 1584 | memset(rxdr->buffer_info, 0, size); |
1819 | 1585 | ||
1820 | if (hw->mac_type <= e1000_82547_rev_2) | 1586 | desc_len = sizeof(struct e1000_rx_desc); |
1821 | desc_len = sizeof(struct e1000_rx_desc); | ||
1822 | else | ||
1823 | desc_len = sizeof(union e1000_rx_desc_packet_split); | ||
1824 | 1587 | ||
1825 | /* Round up to nearest 4K */ | 1588 | /* Round up to nearest 4K */ |
1826 | 1589 | ||
@@ -1977,7 +1740,7 @@ static void e1000_configure_rx(struct e1000_adapter *adapter) | |||
1977 | { | 1740 | { |
1978 | u64 rdba; | 1741 | u64 rdba; |
1979 | struct e1000_hw *hw = &adapter->hw; | 1742 | struct e1000_hw *hw = &adapter->hw; |
1980 | u32 rdlen, rctl, rxcsum, ctrl_ext; | 1743 | u32 rdlen, rctl, rxcsum; |
1981 | 1744 | ||
1982 | if (adapter->netdev->mtu > ETH_DATA_LEN) { | 1745 | if (adapter->netdev->mtu > ETH_DATA_LEN) { |
1983 | rdlen = adapter->rx_ring[0].count * | 1746 | rdlen = adapter->rx_ring[0].count * |
@@ -2004,17 +1767,6 @@ static void e1000_configure_rx(struct e1000_adapter *adapter) | |||
2004 | ew32(ITR, 1000000000 / (adapter->itr * 256)); | 1767 | ew32(ITR, 1000000000 / (adapter->itr * 256)); |
2005 | } | 1768 | } |
2006 | 1769 | ||
2007 | if (hw->mac_type >= e1000_82571) { | ||
2008 | ctrl_ext = er32(CTRL_EXT); | ||
2009 | /* Reset delay timers after every interrupt */ | ||
2010 | ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; | ||
2011 | /* Auto-Mask interrupts upon ICR access */ | ||
2012 | ctrl_ext |= E1000_CTRL_EXT_IAME; | ||
2013 | ew32(IAM, 0xffffffff); | ||
2014 | ew32(CTRL_EXT, ctrl_ext); | ||
2015 | E1000_WRITE_FLUSH(); | ||
2016 | } | ||
2017 | |||
2018 | /* Setup the HW Rx Head and Tail Descriptor Pointers and | 1770 | /* Setup the HW Rx Head and Tail Descriptor Pointers and |
2019 | * the Base and Length of the Rx Descriptor Ring */ | 1771 | * the Base and Length of the Rx Descriptor Ring */ |
2020 | switch (adapter->num_rx_queues) { | 1772 | switch (adapter->num_rx_queues) { |
@@ -2329,22 +2081,6 @@ static int e1000_set_mac(struct net_device *netdev, void *p) | |||
2329 | 2081 | ||
2330 | e1000_rar_set(hw, hw->mac_addr, 0); | 2082 | e1000_rar_set(hw, hw->mac_addr, 0); |
2331 | 2083 | ||
2332 | /* With 82571 controllers, LAA may be overwritten (with the default) | ||
2333 | * due to controller reset from the other port. */ | ||
2334 | if (hw->mac_type == e1000_82571) { | ||
2335 | /* activate the work around */ | ||
2336 | hw->laa_is_present = 1; | ||
2337 | |||
2338 | /* Hold a copy of the LAA in RAR[14] This is done so that | ||
2339 | * between the time RAR[0] gets clobbered and the time it | ||
2340 | * gets fixed (in e1000_watchdog), the actual LAA is in one | ||
2341 | * of the RARs and no incoming packets directed to this port | ||
2342 | * are dropped. Eventaully the LAA will be in RAR[0] and | ||
2343 | * RAR[14] */ | ||
2344 | e1000_rar_set(hw, hw->mac_addr, | ||
2345 | E1000_RAR_ENTRIES - 1); | ||
2346 | } | ||
2347 | |||
2348 | if (hw->mac_type == e1000_82542_rev2_0) | 2084 | if (hw->mac_type == e1000_82542_rev2_0) |
2349 | e1000_leave_82542_rst(adapter); | 2085 | e1000_leave_82542_rst(adapter); |
2350 | 2086 | ||
@@ -2371,9 +2107,7 @@ static void e1000_set_rx_mode(struct net_device *netdev) | |||
2371 | u32 rctl; | 2107 | u32 rctl; |
2372 | u32 hash_value; | 2108 | u32 hash_value; |
2373 | int i, rar_entries = E1000_RAR_ENTRIES; | 2109 | int i, rar_entries = E1000_RAR_ENTRIES; |
2374 | int mta_reg_count = (hw->mac_type == e1000_ich8lan) ? | 2110 | int mta_reg_count = E1000_NUM_MTA_REGISTERS; |
2375 | E1000_NUM_MTA_REGISTERS_ICH8LAN : | ||
2376 | E1000_NUM_MTA_REGISTERS; | ||
2377 | u32 *mcarray = kcalloc(mta_reg_count, sizeof(u32), GFP_ATOMIC); | 2111 | u32 *mcarray = kcalloc(mta_reg_count, sizeof(u32), GFP_ATOMIC); |
2378 | 2112 | ||
2379 | if (!mcarray) { | 2113 | if (!mcarray) { |
@@ -2381,13 +2115,6 @@ static void e1000_set_rx_mode(struct net_device *netdev) | |||
2381 | return; | 2115 | return; |
2382 | } | 2116 | } |
2383 | 2117 | ||
2384 | if (hw->mac_type == e1000_ich8lan) | ||
2385 | rar_entries = E1000_RAR_ENTRIES_ICH8LAN; | ||
2386 | |||
2387 | /* reserve RAR[14] for LAA over-write work-around */ | ||
2388 | if (hw->mac_type == e1000_82571) | ||
2389 | rar_entries--; | ||
2390 | |||
2391 | /* Check for Promiscuous and All Multicast modes */ | 2118 | /* Check for Promiscuous and All Multicast modes */ |
2392 | 2119 | ||
2393 | rctl = er32(RCTL); | 2120 | rctl = er32(RCTL); |
@@ -2396,15 +2123,13 @@ static void e1000_set_rx_mode(struct net_device *netdev) | |||
2396 | rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); | 2123 | rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); |
2397 | rctl &= ~E1000_RCTL_VFE; | 2124 | rctl &= ~E1000_RCTL_VFE; |
2398 | } else { | 2125 | } else { |
2399 | if (netdev->flags & IFF_ALLMULTI) { | 2126 | if (netdev->flags & IFF_ALLMULTI) |
2400 | rctl |= E1000_RCTL_MPE; | 2127 | rctl |= E1000_RCTL_MPE; |
2401 | } else { | 2128 | else |
2402 | rctl &= ~E1000_RCTL_MPE; | 2129 | rctl &= ~E1000_RCTL_MPE; |
2403 | } | 2130 | /* Enable VLAN filter if there is a VLAN */ |
2404 | if (adapter->hw.mac_type != e1000_ich8lan) | 2131 | if (adapter->vlgrp) |
2405 | /* Enable VLAN filter if there is a VLAN */ | 2132 | rctl |= E1000_RCTL_VFE; |
2406 | if (adapter->vlgrp) | ||
2407 | rctl |= E1000_RCTL_VFE; | ||
2408 | } | 2133 | } |
2409 | 2134 | ||
2410 | if (netdev->uc.count > rar_entries - 1) { | 2135 | if (netdev->uc.count > rar_entries - 1) { |
@@ -2427,7 +2152,6 @@ static void e1000_set_rx_mode(struct net_device *netdev) | |||
2427 | * | 2152 | * |
2428 | * RAR 0 is used for the station MAC adddress | 2153 | * RAR 0 is used for the station MAC adddress |
2429 | * if there are not 14 addresses, go ahead and clear the filters | 2154 | * if there are not 14 addresses, go ahead and clear the filters |
2430 | * -- with 82571 controllers only 0-13 entries are filled here | ||
2431 | */ | 2155 | */ |
2432 | i = 1; | 2156 | i = 1; |
2433 | if (use_uc) | 2157 | if (use_uc) |
@@ -2521,12 +2245,46 @@ static void e1000_82547_tx_fifo_stall(unsigned long data) | |||
2521 | adapter->tx_fifo_head = 0; | 2245 | adapter->tx_fifo_head = 0; |
2522 | atomic_set(&adapter->tx_fifo_stall, 0); | 2246 | atomic_set(&adapter->tx_fifo_stall, 0); |
2523 | netif_wake_queue(netdev); | 2247 | netif_wake_queue(netdev); |
2524 | } else { | 2248 | } else if (!test_bit(__E1000_DOWN, &adapter->flags)) { |
2525 | mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1); | 2249 | mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1); |
2526 | } | 2250 | } |
2527 | } | 2251 | } |
2528 | } | 2252 | } |
2529 | 2253 | ||
2254 | static bool e1000_has_link(struct e1000_adapter *adapter) | ||
2255 | { | ||
2256 | struct e1000_hw *hw = &adapter->hw; | ||
2257 | bool link_active = false; | ||
2258 | |||
2259 | /* get_link_status is set on LSC (link status) interrupt or | ||
2260 | * rx sequence error interrupt. get_link_status will stay | ||
2261 | * false until the e1000_check_for_link establishes link | ||
2262 | * for copper adapters ONLY | ||
2263 | */ | ||
2264 | switch (hw->media_type) { | ||
2265 | case e1000_media_type_copper: | ||
2266 | if (hw->get_link_status) { | ||
2267 | e1000_check_for_link(hw); | ||
2268 | link_active = !hw->get_link_status; | ||
2269 | } else { | ||
2270 | link_active = true; | ||
2271 | } | ||
2272 | break; | ||
2273 | case e1000_media_type_fiber: | ||
2274 | e1000_check_for_link(hw); | ||
2275 | link_active = !!(er32(STATUS) & E1000_STATUS_LU); | ||
2276 | break; | ||
2277 | case e1000_media_type_internal_serdes: | ||
2278 | e1000_check_for_link(hw); | ||
2279 | link_active = hw->serdes_has_link; | ||
2280 | break; | ||
2281 | default: | ||
2282 | break; | ||
2283 | } | ||
2284 | |||
2285 | return link_active; | ||
2286 | } | ||
2287 | |||
2530 | /** | 2288 | /** |
2531 | * e1000_watchdog - Timer Call-back | 2289 | * e1000_watchdog - Timer Call-back |
2532 | * @data: pointer to adapter cast into an unsigned long | 2290 | * @data: pointer to adapter cast into an unsigned long |
@@ -2538,33 +2296,16 @@ static void e1000_watchdog(unsigned long data) | |||
2538 | struct net_device *netdev = adapter->netdev; | 2296 | struct net_device *netdev = adapter->netdev; |
2539 | struct e1000_tx_ring *txdr = adapter->tx_ring; | 2297 | struct e1000_tx_ring *txdr = adapter->tx_ring; |
2540 | u32 link, tctl; | 2298 | u32 link, tctl; |
2541 | s32 ret_val; | ||
2542 | |||
2543 | ret_val = e1000_check_for_link(hw); | ||
2544 | if ((ret_val == E1000_ERR_PHY) && | ||
2545 | (hw->phy_type == e1000_phy_igp_3) && | ||
2546 | (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { | ||
2547 | /* See e1000_kumeran_lock_loss_workaround() */ | ||
2548 | DPRINTK(LINK, INFO, | ||
2549 | "Gigabit has been disabled, downgrading speed\n"); | ||
2550 | } | ||
2551 | 2299 | ||
2552 | if (hw->mac_type == e1000_82573) { | 2300 | link = e1000_has_link(adapter); |
2553 | e1000_enable_tx_pkt_filtering(hw); | 2301 | if ((netif_carrier_ok(netdev)) && link) |
2554 | if (adapter->mng_vlan_id != hw->mng_cookie.vlan_id) | 2302 | goto link_up; |
2555 | e1000_update_mng_vlan(adapter); | ||
2556 | } | ||
2557 | |||
2558 | if ((hw->media_type == e1000_media_type_internal_serdes) && | ||
2559 | !(er32(TXCW) & E1000_TXCW_ANE)) | ||
2560 | link = !hw->serdes_link_down; | ||
2561 | else | ||
2562 | link = er32(STATUS) & E1000_STATUS_LU; | ||
2563 | 2303 | ||
2564 | if (link) { | 2304 | if (link) { |
2565 | if (!netif_carrier_ok(netdev)) { | 2305 | if (!netif_carrier_ok(netdev)) { |
2566 | u32 ctrl; | 2306 | u32 ctrl; |
2567 | bool txb2b = true; | 2307 | bool txb2b = true; |
2308 | /* update snapshot of PHY registers on LSC */ | ||
2568 | e1000_get_speed_and_duplex(hw, | 2309 | e1000_get_speed_and_duplex(hw, |
2569 | &adapter->link_speed, | 2310 | &adapter->link_speed, |
2570 | &adapter->link_duplex); | 2311 | &adapter->link_duplex); |
@@ -2589,7 +2330,7 @@ static void e1000_watchdog(unsigned long data) | |||
2589 | case SPEED_10: | 2330 | case SPEED_10: |
2590 | txb2b = false; | 2331 | txb2b = false; |
2591 | netdev->tx_queue_len = 10; | 2332 | netdev->tx_queue_len = 10; |
2592 | adapter->tx_timeout_factor = 8; | 2333 | adapter->tx_timeout_factor = 16; |
2593 | break; | 2334 | break; |
2594 | case SPEED_100: | 2335 | case SPEED_100: |
2595 | txb2b = false; | 2336 | txb2b = false; |
@@ -2598,52 +2339,16 @@ static void e1000_watchdog(unsigned long data) | |||
2598 | break; | 2339 | break; |
2599 | } | 2340 | } |
2600 | 2341 | ||
2601 | if ((hw->mac_type == e1000_82571 || | 2342 | /* enable transmits in the hardware */ |
2602 | hw->mac_type == e1000_82572) && | ||
2603 | !txb2b) { | ||
2604 | u32 tarc0; | ||
2605 | tarc0 = er32(TARC0); | ||
2606 | tarc0 &= ~(1 << 21); | ||
2607 | ew32(TARC0, tarc0); | ||
2608 | } | ||
2609 | |||
2610 | /* disable TSO for pcie and 10/100 speeds, to avoid | ||
2611 | * some hardware issues */ | ||
2612 | if (!adapter->tso_force && | ||
2613 | hw->bus_type == e1000_bus_type_pci_express){ | ||
2614 | switch (adapter->link_speed) { | ||
2615 | case SPEED_10: | ||
2616 | case SPEED_100: | ||
2617 | DPRINTK(PROBE,INFO, | ||
2618 | "10/100 speed: disabling TSO\n"); | ||
2619 | netdev->features &= ~NETIF_F_TSO; | ||
2620 | netdev->features &= ~NETIF_F_TSO6; | ||
2621 | break; | ||
2622 | case SPEED_1000: | ||
2623 | netdev->features |= NETIF_F_TSO; | ||
2624 | netdev->features |= NETIF_F_TSO6; | ||
2625 | break; | ||
2626 | default: | ||
2627 | /* oops */ | ||
2628 | break; | ||
2629 | } | ||
2630 | } | ||
2631 | |||
2632 | /* enable transmits in the hardware, need to do this | ||
2633 | * after setting TARC0 */ | ||
2634 | tctl = er32(TCTL); | 2343 | tctl = er32(TCTL); |
2635 | tctl |= E1000_TCTL_EN; | 2344 | tctl |= E1000_TCTL_EN; |
2636 | ew32(TCTL, tctl); | 2345 | ew32(TCTL, tctl); |
2637 | 2346 | ||
2638 | netif_carrier_on(netdev); | 2347 | netif_carrier_on(netdev); |
2639 | mod_timer(&adapter->phy_info_timer, round_jiffies(jiffies + 2 * HZ)); | 2348 | if (!test_bit(__E1000_DOWN, &adapter->flags)) |
2349 | mod_timer(&adapter->phy_info_timer, | ||
2350 | round_jiffies(jiffies + 2 * HZ)); | ||
2640 | adapter->smartspeed = 0; | 2351 | adapter->smartspeed = 0; |
2641 | } else { | ||
2642 | /* make sure the receive unit is started */ | ||
2643 | if (hw->rx_needs_kicking) { | ||
2644 | u32 rctl = er32(RCTL); | ||
2645 | ew32(RCTL, rctl | E1000_RCTL_EN); | ||
2646 | } | ||
2647 | } | 2352 | } |
2648 | } else { | 2353 | } else { |
2649 | if (netif_carrier_ok(netdev)) { | 2354 | if (netif_carrier_ok(netdev)) { |
@@ -2652,21 +2357,16 @@ static void e1000_watchdog(unsigned long data) | |||
2652 | printk(KERN_INFO "e1000: %s NIC Link is Down\n", | 2357 | printk(KERN_INFO "e1000: %s NIC Link is Down\n", |
2653 | netdev->name); | 2358 | netdev->name); |
2654 | netif_carrier_off(netdev); | 2359 | netif_carrier_off(netdev); |
2655 | mod_timer(&adapter->phy_info_timer, round_jiffies(jiffies + 2 * HZ)); | 2360 | |
2656 | 2361 | if (!test_bit(__E1000_DOWN, &adapter->flags)) | |
2657 | /* 80003ES2LAN workaround-- | 2362 | mod_timer(&adapter->phy_info_timer, |
2658 | * For packet buffer work-around on link down event; | 2363 | round_jiffies(jiffies + 2 * HZ)); |
2659 | * disable receives in the ISR and | ||
2660 | * reset device here in the watchdog | ||
2661 | */ | ||
2662 | if (hw->mac_type == e1000_80003es2lan) | ||
2663 | /* reset device */ | ||
2664 | schedule_work(&adapter->reset_task); | ||
2665 | } | 2364 | } |
2666 | 2365 | ||
2667 | e1000_smartspeed(adapter); | 2366 | e1000_smartspeed(adapter); |
2668 | } | 2367 | } |
2669 | 2368 | ||
2369 | link_up: | ||
2670 | e1000_update_stats(adapter); | 2370 | e1000_update_stats(adapter); |
2671 | 2371 | ||
2672 | hw->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; | 2372 | hw->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; |
@@ -2700,13 +2400,10 @@ static void e1000_watchdog(unsigned long data) | |||
2700 | /* Force detection of hung controller every watchdog period */ | 2400 | /* Force detection of hung controller every watchdog period */ |
2701 | adapter->detect_tx_hung = true; | 2401 | adapter->detect_tx_hung = true; |
2702 | 2402 | ||
2703 | /* With 82571 controllers, LAA may be overwritten due to controller | ||
2704 | * reset from the other port. Set the appropriate LAA in RAR[0] */ | ||
2705 | if (hw->mac_type == e1000_82571 && hw->laa_is_present) | ||
2706 | e1000_rar_set(hw, hw->mac_addr, 0); | ||
2707 | |||
2708 | /* Reset the timer */ | 2403 | /* Reset the timer */ |
2709 | mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ)); | 2404 | if (!test_bit(__E1000_DOWN, &adapter->flags)) |
2405 | mod_timer(&adapter->watchdog_timer, | ||
2406 | round_jiffies(jiffies + 2 * HZ)); | ||
2710 | } | 2407 | } |
2711 | 2408 | ||
2712 | enum latency_range { | 2409 | enum latency_range { |
@@ -2718,6 +2415,11 @@ enum latency_range { | |||
2718 | 2415 | ||
2719 | /** | 2416 | /** |
2720 | * e1000_update_itr - update the dynamic ITR value based on statistics | 2417 | * e1000_update_itr - update the dynamic ITR value based on statistics |
2418 | * @adapter: pointer to adapter | ||
2419 | * @itr_setting: current adapter->itr | ||
2420 | * @packets: the number of packets during this measurement interval | ||
2421 | * @bytes: the number of bytes during this measurement interval | ||
2422 | * | ||
2721 | * Stores a new ITR value based on packets and byte | 2423 | * Stores a new ITR value based on packets and byte |
2722 | * counts during the last interrupt. The advantage of per interrupt | 2424 | * counts during the last interrupt. The advantage of per interrupt |
2723 | * computation is faster updates and more accurate ITR for the current | 2425 | * computation is faster updates and more accurate ITR for the current |
@@ -2727,10 +2429,6 @@ enum latency_range { | |||
2727 | * while increasing bulk throughput. | 2429 | * while increasing bulk throughput. |
2728 | * this functionality is controlled by the InterruptThrottleRate module | 2430 | * this functionality is controlled by the InterruptThrottleRate module |
2729 | * parameter (see e1000_param.c) | 2431 | * parameter (see e1000_param.c) |
2730 | * @adapter: pointer to adapter | ||
2731 | * @itr_setting: current adapter->itr | ||
2732 | * @packets: the number of packets during this measurement interval | ||
2733 | * @bytes: the number of bytes during this measurement interval | ||
2734 | **/ | 2432 | **/ |
2735 | static unsigned int e1000_update_itr(struct e1000_adapter *adapter, | 2433 | static unsigned int e1000_update_itr(struct e1000_adapter *adapter, |
2736 | u16 itr_setting, int packets, int bytes) | 2434 | u16 itr_setting, int packets, int bytes) |
@@ -3035,8 +2733,9 @@ static int e1000_tx_map(struct e1000_adapter *adapter, | |||
3035 | size -= 4; | 2733 | size -= 4; |
3036 | 2734 | ||
3037 | buffer_info->length = size; | 2735 | buffer_info->length = size; |
3038 | buffer_info->dma = skb_shinfo(skb)->dma_head + offset; | 2736 | /* set time_stamp *before* dma to help avoid a possible race */ |
3039 | buffer_info->time_stamp = jiffies; | 2737 | buffer_info->time_stamp = jiffies; |
2738 | buffer_info->dma = skb_shinfo(skb)->dma_head + offset; | ||
3040 | buffer_info->next_to_watch = i; | 2739 | buffer_info->next_to_watch = i; |
3041 | 2740 | ||
3042 | len -= size; | 2741 | len -= size; |
@@ -3071,13 +2770,14 @@ static int e1000_tx_map(struct e1000_adapter *adapter, | |||
3071 | * Avoid terminating buffers within evenly-aligned | 2770 | * Avoid terminating buffers within evenly-aligned |
3072 | * dwords. */ | 2771 | * dwords. */ |
3073 | if (unlikely(adapter->pcix_82544 && | 2772 | if (unlikely(adapter->pcix_82544 && |
3074 | !((unsigned long)(frag->page+offset+size-1) & 4) && | 2773 | !((unsigned long)(page_to_phys(frag->page) + offset |
3075 | size > 4)) | 2774 | + size - 1) & 4) && |
2775 | size > 4)) | ||
3076 | size -= 4; | 2776 | size -= 4; |
3077 | 2777 | ||
3078 | buffer_info->length = size; | 2778 | buffer_info->length = size; |
3079 | buffer_info->dma = map[f] + offset; | ||
3080 | buffer_info->time_stamp = jiffies; | 2779 | buffer_info->time_stamp = jiffies; |
2780 | buffer_info->dma = map[f] + offset; | ||
3081 | buffer_info->next_to_watch = i; | 2781 | buffer_info->next_to_watch = i; |
3082 | 2782 | ||
3083 | len -= size; | 2783 | len -= size; |
@@ -3186,41 +2886,6 @@ no_fifo_stall_required: | |||
3186 | return 0; | 2886 | return 0; |
3187 | } | 2887 | } |
3188 | 2888 | ||
3189 | #define MINIMUM_DHCP_PACKET_SIZE 282 | ||
3190 | static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, | ||
3191 | struct sk_buff *skb) | ||
3192 | { | ||
3193 | struct e1000_hw *hw = &adapter->hw; | ||
3194 | u16 length, offset; | ||
3195 | if (vlan_tx_tag_present(skb)) { | ||
3196 | if (!((vlan_tx_tag_get(skb) == hw->mng_cookie.vlan_id) && | ||
3197 | ( hw->mng_cookie.status & | ||
3198 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) ) | ||
3199 | return 0; | ||
3200 | } | ||
3201 | if (skb->len > MINIMUM_DHCP_PACKET_SIZE) { | ||
3202 | struct ethhdr *eth = (struct ethhdr *)skb->data; | ||
3203 | if ((htons(ETH_P_IP) == eth->h_proto)) { | ||
3204 | const struct iphdr *ip = | ||
3205 | (struct iphdr *)((u8 *)skb->data+14); | ||
3206 | if (IPPROTO_UDP == ip->protocol) { | ||
3207 | struct udphdr *udp = | ||
3208 | (struct udphdr *)((u8 *)ip + | ||
3209 | (ip->ihl << 2)); | ||
3210 | if (ntohs(udp->dest) == 67) { | ||
3211 | offset = (u8 *)udp + 8 - skb->data; | ||
3212 | length = skb->len - offset; | ||
3213 | |||
3214 | return e1000_mng_write_dhcp_info(hw, | ||
3215 | (u8 *)udp + 8, | ||
3216 | length); | ||
3217 | } | ||
3218 | } | ||
3219 | } | ||
3220 | } | ||
3221 | return 0; | ||
3222 | } | ||
3223 | |||
3224 | static int __e1000_maybe_stop_tx(struct net_device *netdev, int size) | 2889 | static int __e1000_maybe_stop_tx(struct net_device *netdev, int size) |
3225 | { | 2890 | { |
3226 | struct e1000_adapter *adapter = netdev_priv(netdev); | 2891 | struct e1000_adapter *adapter = netdev_priv(netdev); |
@@ -3279,11 +2944,6 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, | |||
3279 | return NETDEV_TX_OK; | 2944 | return NETDEV_TX_OK; |
3280 | } | 2945 | } |
3281 | 2946 | ||
3282 | /* 82571 and newer doesn't need the workaround that limited descriptor | ||
3283 | * length to 4kB */ | ||
3284 | if (hw->mac_type >= e1000_82571) | ||
3285 | max_per_txd = 8192; | ||
3286 | |||
3287 | mss = skb_shinfo(skb)->gso_size; | 2947 | mss = skb_shinfo(skb)->gso_size; |
3288 | /* The controller does a simple calculation to | 2948 | /* The controller does a simple calculation to |
3289 | * make sure there is enough room in the FIFO before | 2949 | * make sure there is enough room in the FIFO before |
@@ -3296,9 +2956,6 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, | |||
3296 | max_per_txd = min(mss << 2, max_per_txd); | 2956 | max_per_txd = min(mss << 2, max_per_txd); |
3297 | max_txd_pwr = fls(max_per_txd) - 1; | 2957 | max_txd_pwr = fls(max_per_txd) - 1; |
3298 | 2958 | ||
3299 | /* TSO Workaround for 82571/2/3 Controllers -- if skb->data | ||
3300 | * points to just header, pull a few bytes of payload from | ||
3301 | * frags into skb->data */ | ||
3302 | hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | 2959 | hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); |
3303 | if (skb->data_len && hdr_len == len) { | 2960 | if (skb->data_len && hdr_len == len) { |
3304 | switch (hw->mac_type) { | 2961 | switch (hw->mac_type) { |
@@ -3313,10 +2970,6 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, | |||
3313 | if ((unsigned long)(skb_tail_pointer(skb) - 1) & 4) | 2970 | if ((unsigned long)(skb_tail_pointer(skb) - 1) & 4) |
3314 | break; | 2971 | break; |
3315 | /* fall through */ | 2972 | /* fall through */ |
3316 | case e1000_82571: | ||
3317 | case e1000_82572: | ||
3318 | case e1000_82573: | ||
3319 | case e1000_ich8lan: | ||
3320 | pull_size = min((unsigned int)4, skb->data_len); | 2973 | pull_size = min((unsigned int)4, skb->data_len); |
3321 | if (!__pskb_pull_tail(skb, pull_size)) { | 2974 | if (!__pskb_pull_tail(skb, pull_size)) { |
3322 | DPRINTK(DRV, ERR, | 2975 | DPRINTK(DRV, ERR, |
@@ -3361,11 +3014,6 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, | |||
3361 | if (adapter->pcix_82544) | 3014 | if (adapter->pcix_82544) |
3362 | count += nr_frags; | 3015 | count += nr_frags; |
3363 | 3016 | ||
3364 | |||
3365 | if (hw->tx_pkt_filtering && | ||
3366 | (hw->mac_type == e1000_82573)) | ||
3367 | e1000_transfer_dhcp_info(adapter, skb); | ||
3368 | |||
3369 | /* need: count + 2 desc gap to keep tail from touching | 3017 | /* need: count + 2 desc gap to keep tail from touching |
3370 | * head, otherwise try next time */ | 3018 | * head, otherwise try next time */ |
3371 | if (unlikely(e1000_maybe_stop_tx(netdev, tx_ring, count + 2))) | 3019 | if (unlikely(e1000_maybe_stop_tx(netdev, tx_ring, count + 2))) |
@@ -3374,7 +3022,9 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, | |||
3374 | if (unlikely(hw->mac_type == e1000_82547)) { | 3022 | if (unlikely(hw->mac_type == e1000_82547)) { |
3375 | if (unlikely(e1000_82547_fifo_workaround(adapter, skb))) { | 3023 | if (unlikely(e1000_82547_fifo_workaround(adapter, skb))) { |
3376 | netif_stop_queue(netdev); | 3024 | netif_stop_queue(netdev); |
3377 | mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1); | 3025 | if (!test_bit(__E1000_DOWN, &adapter->flags)) |
3026 | mod_timer(&adapter->tx_fifo_stall_timer, | ||
3027 | jiffies + 1); | ||
3378 | return NETDEV_TX_BUSY; | 3028 | return NETDEV_TX_BUSY; |
3379 | } | 3029 | } |
3380 | } | 3030 | } |
@@ -3393,14 +3043,12 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, | |||
3393 | } | 3043 | } |
3394 | 3044 | ||
3395 | if (likely(tso)) { | 3045 | if (likely(tso)) { |
3396 | tx_ring->last_tx_tso = 1; | 3046 | if (likely(hw->mac_type != e1000_82544)) |
3047 | tx_ring->last_tx_tso = 1; | ||
3397 | tx_flags |= E1000_TX_FLAGS_TSO; | 3048 | tx_flags |= E1000_TX_FLAGS_TSO; |
3398 | } else if (likely(e1000_tx_csum(adapter, tx_ring, skb))) | 3049 | } else if (likely(e1000_tx_csum(adapter, tx_ring, skb))) |
3399 | tx_flags |= E1000_TX_FLAGS_CSUM; | 3050 | tx_flags |= E1000_TX_FLAGS_CSUM; |
3400 | 3051 | ||
3401 | /* Old method was to assume IPv4 packet by default if TSO was enabled. | ||
3402 | * 82571 hardware supports TSO capabilities for IPv6 as well... | ||
3403 | * no longer assume, we must. */ | ||
3404 | if (likely(skb->protocol == htons(ETH_P_IP))) | 3052 | if (likely(skb->protocol == htons(ETH_P_IP))) |
3405 | tx_flags |= E1000_TX_FLAGS_IPV4; | 3053 | tx_flags |= E1000_TX_FLAGS_IPV4; |
3406 | 3054 | ||
@@ -3472,7 +3120,6 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu) | |||
3472 | struct e1000_adapter *adapter = netdev_priv(netdev); | 3120 | struct e1000_adapter *adapter = netdev_priv(netdev); |
3473 | struct e1000_hw *hw = &adapter->hw; | 3121 | struct e1000_hw *hw = &adapter->hw; |
3474 | int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE; | 3122 | int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE; |
3475 | u16 eeprom_data = 0; | ||
3476 | 3123 | ||
3477 | if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) || | 3124 | if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) || |
3478 | (max_frame > MAX_JUMBO_FRAME_SIZE)) { | 3125 | (max_frame > MAX_JUMBO_FRAME_SIZE)) { |
@@ -3483,44 +3130,23 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu) | |||
3483 | /* Adapter-specific max frame size limits. */ | 3130 | /* Adapter-specific max frame size limits. */ |
3484 | switch (hw->mac_type) { | 3131 | switch (hw->mac_type) { |
3485 | case e1000_undefined ... e1000_82542_rev2_1: | 3132 | case e1000_undefined ... e1000_82542_rev2_1: |
3486 | case e1000_ich8lan: | ||
3487 | if (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)) { | 3133 | if (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)) { |
3488 | DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n"); | 3134 | DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n"); |
3489 | return -EINVAL; | 3135 | return -EINVAL; |
3490 | } | 3136 | } |
3491 | break; | 3137 | break; |
3492 | case e1000_82573: | ||
3493 | /* Jumbo Frames not supported if: | ||
3494 | * - this is not an 82573L device | ||
3495 | * - ASPM is enabled in any way (0x1A bits 3:2) */ | ||
3496 | e1000_read_eeprom(hw, EEPROM_INIT_3GIO_3, 1, | ||
3497 | &eeprom_data); | ||
3498 | if ((hw->device_id != E1000_DEV_ID_82573L) || | ||
3499 | (eeprom_data & EEPROM_WORD1A_ASPM_MASK)) { | ||
3500 | if (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)) { | ||
3501 | DPRINTK(PROBE, ERR, | ||
3502 | "Jumbo Frames not supported.\n"); | ||
3503 | return -EINVAL; | ||
3504 | } | ||
3505 | break; | ||
3506 | } | ||
3507 | /* ERT will be enabled later to enable wire speed receives */ | ||
3508 | |||
3509 | /* fall through to get support */ | ||
3510 | case e1000_82571: | ||
3511 | case e1000_82572: | ||
3512 | case e1000_80003es2lan: | ||
3513 | #define MAX_STD_JUMBO_FRAME_SIZE 9234 | ||
3514 | if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { | ||
3515 | DPRINTK(PROBE, ERR, "MTU > 9216 not supported.\n"); | ||
3516 | return -EINVAL; | ||
3517 | } | ||
3518 | break; | ||
3519 | default: | 3138 | default: |
3520 | /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */ | 3139 | /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */ |
3521 | break; | 3140 | break; |
3522 | } | 3141 | } |
3523 | 3142 | ||
3143 | while (test_and_set_bit(__E1000_RESETTING, &adapter->flags)) | ||
3144 | msleep(1); | ||
3145 | /* e1000_down has a dependency on max_frame_size */ | ||
3146 | hw->max_frame_size = max_frame; | ||
3147 | if (netif_running(netdev)) | ||
3148 | e1000_down(adapter); | ||
3149 | |||
3524 | /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN | 3150 | /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN |
3525 | * means we reserve 2 more, this pushes us to allocate from the next | 3151 | * means we reserve 2 more, this pushes us to allocate from the next |
3526 | * larger slab size. | 3152 | * larger slab size. |
@@ -3549,11 +3175,16 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu) | |||
3549 | (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))) | 3175 | (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))) |
3550 | adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; | 3176 | adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
3551 | 3177 | ||
3178 | printk(KERN_INFO "e1000: %s changing MTU from %d to %d\n", | ||
3179 | netdev->name, netdev->mtu, new_mtu); | ||
3552 | netdev->mtu = new_mtu; | 3180 | netdev->mtu = new_mtu; |
3553 | hw->max_frame_size = max_frame; | ||
3554 | 3181 | ||
3555 | if (netif_running(netdev)) | 3182 | if (netif_running(netdev)) |
3556 | e1000_reinit_locked(adapter); | 3183 | e1000_up(adapter); |
3184 | else | ||
3185 | e1000_reset(adapter); | ||
3186 | |||
3187 | clear_bit(__E1000_RESETTING, &adapter->flags); | ||
3557 | 3188 | ||
3558 | return 0; | 3189 | return 0; |
3559 | } | 3190 | } |
@@ -3596,14 +3227,12 @@ void e1000_update_stats(struct e1000_adapter *adapter) | |||
3596 | adapter->stats.mprc += er32(MPRC); | 3227 | adapter->stats.mprc += er32(MPRC); |
3597 | adapter->stats.roc += er32(ROC); | 3228 | adapter->stats.roc += er32(ROC); |
3598 | 3229 | ||
3599 | if (hw->mac_type != e1000_ich8lan) { | 3230 | adapter->stats.prc64 += er32(PRC64); |
3600 | adapter->stats.prc64 += er32(PRC64); | 3231 | adapter->stats.prc127 += er32(PRC127); |
3601 | adapter->stats.prc127 += er32(PRC127); | 3232 | adapter->stats.prc255 += er32(PRC255); |
3602 | adapter->stats.prc255 += er32(PRC255); | 3233 | adapter->stats.prc511 += er32(PRC511); |
3603 | adapter->stats.prc511 += er32(PRC511); | 3234 | adapter->stats.prc1023 += er32(PRC1023); |
3604 | adapter->stats.prc1023 += er32(PRC1023); | 3235 | adapter->stats.prc1522 += er32(PRC1522); |
3605 | adapter->stats.prc1522 += er32(PRC1522); | ||
3606 | } | ||
3607 | 3236 | ||
3608 | adapter->stats.symerrs += er32(SYMERRS); | 3237 | adapter->stats.symerrs += er32(SYMERRS); |
3609 | adapter->stats.mpc += er32(MPC); | 3238 | adapter->stats.mpc += er32(MPC); |
@@ -3632,14 +3261,12 @@ void e1000_update_stats(struct e1000_adapter *adapter) | |||
3632 | adapter->stats.toth += er32(TOTH); | 3261 | adapter->stats.toth += er32(TOTH); |
3633 | adapter->stats.tpr += er32(TPR); | 3262 | adapter->stats.tpr += er32(TPR); |
3634 | 3263 | ||
3635 | if (hw->mac_type != e1000_ich8lan) { | 3264 | adapter->stats.ptc64 += er32(PTC64); |
3636 | adapter->stats.ptc64 += er32(PTC64); | 3265 | adapter->stats.ptc127 += er32(PTC127); |
3637 | adapter->stats.ptc127 += er32(PTC127); | 3266 | adapter->stats.ptc255 += er32(PTC255); |
3638 | adapter->stats.ptc255 += er32(PTC255); | 3267 | adapter->stats.ptc511 += er32(PTC511); |
3639 | adapter->stats.ptc511 += er32(PTC511); | 3268 | adapter->stats.ptc1023 += er32(PTC1023); |
3640 | adapter->stats.ptc1023 += er32(PTC1023); | 3269 | adapter->stats.ptc1522 += er32(PTC1522); |
3641 | adapter->stats.ptc1522 += er32(PTC1522); | ||
3642 | } | ||
3643 | 3270 | ||
3644 | adapter->stats.mptc += er32(MPTC); | 3271 | adapter->stats.mptc += er32(MPTC); |
3645 | adapter->stats.bptc += er32(BPTC); | 3272 | adapter->stats.bptc += er32(BPTC); |
@@ -3659,20 +3286,6 @@ void e1000_update_stats(struct e1000_adapter *adapter) | |||
3659 | adapter->stats.tsctc += er32(TSCTC); | 3286 | adapter->stats.tsctc += er32(TSCTC); |
3660 | adapter->stats.tsctfc += er32(TSCTFC); | 3287 | adapter->stats.tsctfc += er32(TSCTFC); |
3661 | } | 3288 | } |
3662 | if (hw->mac_type > e1000_82547_rev_2) { | ||
3663 | adapter->stats.iac += er32(IAC); | ||
3664 | adapter->stats.icrxoc += er32(ICRXOC); | ||
3665 | |||
3666 | if (hw->mac_type != e1000_ich8lan) { | ||
3667 | adapter->stats.icrxptc += er32(ICRXPTC); | ||
3668 | adapter->stats.icrxatc += er32(ICRXATC); | ||
3669 | adapter->stats.ictxptc += er32(ICTXPTC); | ||
3670 | adapter->stats.ictxatc += er32(ICTXATC); | ||
3671 | adapter->stats.ictxqec += er32(ICTXQEC); | ||
3672 | adapter->stats.ictxqmtc += er32(ICTXQMTC); | ||
3673 | adapter->stats.icrxdmtc += er32(ICRXDMTC); | ||
3674 | } | ||
3675 | } | ||
3676 | 3289 | ||
3677 | /* Fill out the OS statistics structure */ | 3290 | /* Fill out the OS statistics structure */ |
3678 | adapter->net_stats.multicast = adapter->stats.mprc; | 3291 | adapter->net_stats.multicast = adapter->stats.mprc; |
@@ -3731,49 +3344,6 @@ void e1000_update_stats(struct e1000_adapter *adapter) | |||
3731 | } | 3344 | } |
3732 | 3345 | ||
3733 | /** | 3346 | /** |
3734 | * e1000_intr_msi - Interrupt Handler | ||
3735 | * @irq: interrupt number | ||
3736 | * @data: pointer to a network interface device structure | ||
3737 | **/ | ||
3738 | |||
3739 | static irqreturn_t e1000_intr_msi(int irq, void *data) | ||
3740 | { | ||
3741 | struct net_device *netdev = data; | ||
3742 | struct e1000_adapter *adapter = netdev_priv(netdev); | ||
3743 | struct e1000_hw *hw = &adapter->hw; | ||
3744 | u32 icr = er32(ICR); | ||
3745 | |||
3746 | /* in NAPI mode read ICR disables interrupts using IAM */ | ||
3747 | |||
3748 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { | ||
3749 | hw->get_link_status = 1; | ||
3750 | /* 80003ES2LAN workaround-- For packet buffer work-around on | ||
3751 | * link down event; disable receives here in the ISR and reset | ||
3752 | * adapter in watchdog */ | ||
3753 | if (netif_carrier_ok(netdev) && | ||
3754 | (hw->mac_type == e1000_80003es2lan)) { | ||
3755 | /* disable receives */ | ||
3756 | u32 rctl = er32(RCTL); | ||
3757 | ew32(RCTL, rctl & ~E1000_RCTL_EN); | ||
3758 | } | ||
3759 | /* guard against interrupt when we're going down */ | ||
3760 | if (!test_bit(__E1000_DOWN, &adapter->flags)) | ||
3761 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | ||
3762 | } | ||
3763 | |||
3764 | if (likely(napi_schedule_prep(&adapter->napi))) { | ||
3765 | adapter->total_tx_bytes = 0; | ||
3766 | adapter->total_tx_packets = 0; | ||
3767 | adapter->total_rx_bytes = 0; | ||
3768 | adapter->total_rx_packets = 0; | ||
3769 | __napi_schedule(&adapter->napi); | ||
3770 | } else | ||
3771 | e1000_irq_enable(adapter); | ||
3772 | |||
3773 | return IRQ_HANDLED; | ||
3774 | } | ||
3775 | |||
3776 | /** | ||
3777 | * e1000_intr - Interrupt Handler | 3347 | * e1000_intr - Interrupt Handler |
3778 | * @irq: interrupt number | 3348 | * @irq: interrupt number |
3779 | * @data: pointer to a network interface device structure | 3349 | * @data: pointer to a network interface device structure |
@@ -3784,43 +3354,22 @@ static irqreturn_t e1000_intr(int irq, void *data) | |||
3784 | struct net_device *netdev = data; | 3354 | struct net_device *netdev = data; |
3785 | struct e1000_adapter *adapter = netdev_priv(netdev); | 3355 | struct e1000_adapter *adapter = netdev_priv(netdev); |
3786 | struct e1000_hw *hw = &adapter->hw; | 3356 | struct e1000_hw *hw = &adapter->hw; |
3787 | u32 rctl, icr = er32(ICR); | 3357 | u32 icr = er32(ICR); |
3788 | 3358 | ||
3789 | if (unlikely((!icr) || test_bit(__E1000_DOWN, &adapter->flags))) | 3359 | if (unlikely((!icr) || test_bit(__E1000_DOWN, &adapter->flags))) |
3790 | return IRQ_NONE; /* Not our interrupt */ | 3360 | return IRQ_NONE; /* Not our interrupt */ |
3791 | 3361 | ||
3792 | /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is | ||
3793 | * not set, then the adapter didn't send an interrupt */ | ||
3794 | if (unlikely(hw->mac_type >= e1000_82571 && | ||
3795 | !(icr & E1000_ICR_INT_ASSERTED))) | ||
3796 | return IRQ_NONE; | ||
3797 | |||
3798 | /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No | ||
3799 | * need for the IMC write */ | ||
3800 | |||
3801 | if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) { | 3362 | if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) { |
3802 | hw->get_link_status = 1; | 3363 | hw->get_link_status = 1; |
3803 | /* 80003ES2LAN workaround-- | ||
3804 | * For packet buffer work-around on link down event; | ||
3805 | * disable receives here in the ISR and | ||
3806 | * reset adapter in watchdog | ||
3807 | */ | ||
3808 | if (netif_carrier_ok(netdev) && | ||
3809 | (hw->mac_type == e1000_80003es2lan)) { | ||
3810 | /* disable receives */ | ||
3811 | rctl = er32(RCTL); | ||
3812 | ew32(RCTL, rctl & ~E1000_RCTL_EN); | ||
3813 | } | ||
3814 | /* guard against interrupt when we're going down */ | 3364 | /* guard against interrupt when we're going down */ |
3815 | if (!test_bit(__E1000_DOWN, &adapter->flags)) | 3365 | if (!test_bit(__E1000_DOWN, &adapter->flags)) |
3816 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | 3366 | mod_timer(&adapter->watchdog_timer, jiffies + 1); |
3817 | } | 3367 | } |
3818 | 3368 | ||
3819 | if (unlikely(hw->mac_type < e1000_82571)) { | 3369 | /* disable interrupts, without the synchronize_irq bit */ |
3820 | /* disable interrupts, without the synchronize_irq bit */ | 3370 | ew32(IMC, ~0); |
3821 | ew32(IMC, ~0); | 3371 | E1000_WRITE_FLUSH(); |
3822 | E1000_WRITE_FLUSH(); | 3372 | |
3823 | } | ||
3824 | if (likely(napi_schedule_prep(&adapter->napi))) { | 3373 | if (likely(napi_schedule_prep(&adapter->napi))) { |
3825 | adapter->total_tx_bytes = 0; | 3374 | adapter->total_tx_bytes = 0; |
3826 | adapter->total_tx_packets = 0; | 3375 | adapter->total_tx_packets = 0; |
@@ -3844,17 +3393,13 @@ static irqreturn_t e1000_intr(int irq, void *data) | |||
3844 | static int e1000_clean(struct napi_struct *napi, int budget) | 3393 | static int e1000_clean(struct napi_struct *napi, int budget) |
3845 | { | 3394 | { |
3846 | struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, napi); | 3395 | struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, napi); |
3847 | struct net_device *poll_dev = adapter->netdev; | 3396 | int tx_clean_complete = 0, work_done = 0; |
3848 | int tx_cleaned = 0, work_done = 0; | ||
3849 | |||
3850 | adapter = netdev_priv(poll_dev); | ||
3851 | 3397 | ||
3852 | tx_cleaned = e1000_clean_tx_irq(adapter, &adapter->tx_ring[0]); | 3398 | tx_clean_complete = e1000_clean_tx_irq(adapter, &adapter->tx_ring[0]); |
3853 | 3399 | ||
3854 | adapter->clean_rx(adapter, &adapter->rx_ring[0], | 3400 | adapter->clean_rx(adapter, &adapter->rx_ring[0], &work_done, budget); |
3855 | &work_done, budget); | ||
3856 | 3401 | ||
3857 | if (!tx_cleaned) | 3402 | if (!tx_clean_complete) |
3858 | work_done = budget; | 3403 | work_done = budget; |
3859 | 3404 | ||
3860 | /* If budget not fully consumed, exit the polling mode */ | 3405 | /* If budget not fully consumed, exit the polling mode */ |
@@ -3925,7 +3470,9 @@ static bool e1000_clean_tx_irq(struct e1000_adapter *adapter, | |||
3925 | * sees the new next_to_clean. | 3470 | * sees the new next_to_clean. |
3926 | */ | 3471 | */ |
3927 | smp_mb(); | 3472 | smp_mb(); |
3928 | if (netif_queue_stopped(netdev)) { | 3473 | |
3474 | if (netif_queue_stopped(netdev) && | ||
3475 | !(test_bit(__E1000_DOWN, &adapter->flags))) { | ||
3929 | netif_wake_queue(netdev); | 3476 | netif_wake_queue(netdev); |
3930 | ++adapter->restart_queue; | 3477 | ++adapter->restart_queue; |
3931 | } | 3478 | } |
@@ -3935,8 +3482,8 @@ static bool e1000_clean_tx_irq(struct e1000_adapter *adapter, | |||
3935 | /* Detect a transmit hang in hardware, this serializes the | 3482 | /* Detect a transmit hang in hardware, this serializes the |
3936 | * check with the clearing of time_stamp and movement of i */ | 3483 | * check with the clearing of time_stamp and movement of i */ |
3937 | adapter->detect_tx_hung = false; | 3484 | adapter->detect_tx_hung = false; |
3938 | if (tx_ring->buffer_info[i].time_stamp && | 3485 | if (tx_ring->buffer_info[eop].time_stamp && |
3939 | time_after(jiffies, tx_ring->buffer_info[i].time_stamp + | 3486 | time_after(jiffies, tx_ring->buffer_info[eop].time_stamp + |
3940 | (adapter->tx_timeout_factor * HZ)) | 3487 | (adapter->tx_timeout_factor * HZ)) |
3941 | && !(er32(STATUS) & E1000_STATUS_TXOFF)) { | 3488 | && !(er32(STATUS) & E1000_STATUS_TXOFF)) { |
3942 | 3489 | ||
@@ -3958,7 +3505,7 @@ static bool e1000_clean_tx_irq(struct e1000_adapter *adapter, | |||
3958 | readl(hw->hw_addr + tx_ring->tdt), | 3505 | readl(hw->hw_addr + tx_ring->tdt), |
3959 | tx_ring->next_to_use, | 3506 | tx_ring->next_to_use, |
3960 | tx_ring->next_to_clean, | 3507 | tx_ring->next_to_clean, |
3961 | tx_ring->buffer_info[i].time_stamp, | 3508 | tx_ring->buffer_info[eop].time_stamp, |
3962 | eop, | 3509 | eop, |
3963 | jiffies, | 3510 | jiffies, |
3964 | eop_desc->upper.fields.status); | 3511 | eop_desc->upper.fields.status); |
@@ -3999,25 +3546,13 @@ static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, | |||
3999 | return; | 3546 | return; |
4000 | } | 3547 | } |
4001 | /* TCP/UDP Checksum has not been calculated */ | 3548 | /* TCP/UDP Checksum has not been calculated */ |
4002 | if (hw->mac_type <= e1000_82547_rev_2) { | 3549 | if (!(status & E1000_RXD_STAT_TCPCS)) |
4003 | if (!(status & E1000_RXD_STAT_TCPCS)) | 3550 | return; |
4004 | return; | 3551 | |
4005 | } else { | ||
4006 | if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) | ||
4007 | return; | ||
4008 | } | ||
4009 | /* It must be a TCP or UDP packet with a valid checksum */ | 3552 | /* It must be a TCP or UDP packet with a valid checksum */ |
4010 | if (likely(status & E1000_RXD_STAT_TCPCS)) { | 3553 | if (likely(status & E1000_RXD_STAT_TCPCS)) { |
4011 | /* TCP checksum is good */ | 3554 | /* TCP checksum is good */ |
4012 | skb->ip_summed = CHECKSUM_UNNECESSARY; | 3555 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
4013 | } else if (hw->mac_type > e1000_82547_rev_2) { | ||
4014 | /* IP fragment with UDP payload */ | ||
4015 | /* Hardware complements the payload checksum, so we undo it | ||
4016 | * and then put the value in host order for further stack use. | ||
4017 | */ | ||
4018 | __sum16 sum = (__force __sum16)htons(csum); | ||
4019 | skb->csum = csum_unfold(~sum); | ||
4020 | skb->ip_summed = CHECKSUM_COMPLETE; | ||
4021 | } | 3556 | } |
4022 | adapter->hw_csum_good++; | 3557 | adapter->hw_csum_good++; |
4023 | } | 3558 | } |
@@ -4814,20 +4349,6 @@ void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc) | |||
4814 | pcix_set_mmrbc(adapter->pdev, mmrbc); | 4349 | pcix_set_mmrbc(adapter->pdev, mmrbc); |
4815 | } | 4350 | } |
4816 | 4351 | ||
4817 | s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) | ||
4818 | { | ||
4819 | struct e1000_adapter *adapter = hw->back; | ||
4820 | u16 cap_offset; | ||
4821 | |||
4822 | cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); | ||
4823 | if (!cap_offset) | ||
4824 | return -E1000_ERR_CONFIG; | ||
4825 | |||
4826 | pci_read_config_word(adapter->pdev, cap_offset + reg, value); | ||
4827 | |||
4828 | return E1000_SUCCESS; | ||
4829 | } | ||
4830 | |||
4831 | void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value) | 4352 | void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value) |
4832 | { | 4353 | { |
4833 | outl(value, port); | 4354 | outl(value, port); |
@@ -4850,33 +4371,27 @@ static void e1000_vlan_rx_register(struct net_device *netdev, | |||
4850 | ctrl |= E1000_CTRL_VME; | 4371 | ctrl |= E1000_CTRL_VME; |
4851 | ew32(CTRL, ctrl); | 4372 | ew32(CTRL, ctrl); |
4852 | 4373 | ||
4853 | if (adapter->hw.mac_type != e1000_ich8lan) { | 4374 | /* enable VLAN receive filtering */ |
4854 | /* enable VLAN receive filtering */ | 4375 | rctl = er32(RCTL); |
4855 | rctl = er32(RCTL); | 4376 | rctl &= ~E1000_RCTL_CFIEN; |
4856 | rctl &= ~E1000_RCTL_CFIEN; | 4377 | if (!(netdev->flags & IFF_PROMISC)) |
4857 | if (!(netdev->flags & IFF_PROMISC)) | 4378 | rctl |= E1000_RCTL_VFE; |
4858 | rctl |= E1000_RCTL_VFE; | 4379 | ew32(RCTL, rctl); |
4859 | ew32(RCTL, rctl); | 4380 | e1000_update_mng_vlan(adapter); |
4860 | e1000_update_mng_vlan(adapter); | ||
4861 | } | ||
4862 | } else { | 4381 | } else { |
4863 | /* disable VLAN tag insert/strip */ | 4382 | /* disable VLAN tag insert/strip */ |
4864 | ctrl = er32(CTRL); | 4383 | ctrl = er32(CTRL); |
4865 | ctrl &= ~E1000_CTRL_VME; | 4384 | ctrl &= ~E1000_CTRL_VME; |
4866 | ew32(CTRL, ctrl); | 4385 | ew32(CTRL, ctrl); |
4867 | 4386 | ||
4868 | if (adapter->hw.mac_type != e1000_ich8lan) { | 4387 | /* disable VLAN receive filtering */ |
4869 | /* disable VLAN receive filtering */ | 4388 | rctl = er32(RCTL); |
4870 | rctl = er32(RCTL); | 4389 | rctl &= ~E1000_RCTL_VFE; |
4871 | rctl &= ~E1000_RCTL_VFE; | 4390 | ew32(RCTL, rctl); |
4872 | ew32(RCTL, rctl); | ||
4873 | 4391 | ||
4874 | if (adapter->mng_vlan_id != | 4392 | if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) { |
4875 | (u16)E1000_MNG_VLAN_NONE) { | 4393 | e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); |
4876 | e1000_vlan_rx_kill_vid(netdev, | 4394 | adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; |
4877 | adapter->mng_vlan_id); | ||
4878 | adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; | ||
4879 | } | ||
4880 | } | 4395 | } |
4881 | } | 4396 | } |
4882 | 4397 | ||
@@ -4913,14 +4428,6 @@ static void e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |||
4913 | if (!test_bit(__E1000_DOWN, &adapter->flags)) | 4428 | if (!test_bit(__E1000_DOWN, &adapter->flags)) |
4914 | e1000_irq_enable(adapter); | 4429 | e1000_irq_enable(adapter); |
4915 | 4430 | ||
4916 | if ((hw->mng_cookie.status & | ||
4917 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) && | ||
4918 | (vid == adapter->mng_vlan_id)) { | ||
4919 | /* release control to f/w */ | ||
4920 | e1000_release_hw_control(adapter); | ||
4921 | return; | ||
4922 | } | ||
4923 | |||
4924 | /* remove VID from filter table */ | 4431 | /* remove VID from filter table */ |
4925 | index = (vid >> 5) & 0x7F; | 4432 | index = (vid >> 5) & 0x7F; |
4926 | vfta = E1000_READ_REG_ARRAY(hw, VFTA, index); | 4433 | vfta = E1000_READ_REG_ARRAY(hw, VFTA, index); |
@@ -5031,16 +4538,13 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake) | |||
5031 | } | 4538 | } |
5032 | 4539 | ||
5033 | if (hw->media_type == e1000_media_type_fiber || | 4540 | if (hw->media_type == e1000_media_type_fiber || |
5034 | hw->media_type == e1000_media_type_internal_serdes) { | 4541 | hw->media_type == e1000_media_type_internal_serdes) { |
5035 | /* keep the laser running in D3 */ | 4542 | /* keep the laser running in D3 */ |
5036 | ctrl_ext = er32(CTRL_EXT); | 4543 | ctrl_ext = er32(CTRL_EXT); |
5037 | ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA; | 4544 | ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA; |
5038 | ew32(CTRL_EXT, ctrl_ext); | 4545 | ew32(CTRL_EXT, ctrl_ext); |
5039 | } | 4546 | } |
5040 | 4547 | ||
5041 | /* Allow time for pending master requests to run */ | ||
5042 | e1000_disable_pciex_master(hw); | ||
5043 | |||
5044 | ew32(WUC, E1000_WUC_PME_EN); | 4548 | ew32(WUC, E1000_WUC_PME_EN); |
5045 | ew32(WUFC, wufc); | 4549 | ew32(WUFC, wufc); |
5046 | } else { | 4550 | } else { |
@@ -5056,16 +4560,9 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake) | |||
5056 | if (adapter->en_mng_pt) | 4560 | if (adapter->en_mng_pt) |
5057 | *enable_wake = true; | 4561 | *enable_wake = true; |
5058 | 4562 | ||
5059 | if (hw->phy_type == e1000_phy_igp_3) | ||
5060 | e1000_phy_powerdown_workaround(hw); | ||
5061 | |||
5062 | if (netif_running(netdev)) | 4563 | if (netif_running(netdev)) |
5063 | e1000_free_irq(adapter); | 4564 | e1000_free_irq(adapter); |
5064 | 4565 | ||
5065 | /* Release control of h/w to f/w. If f/w is AMT enabled, this | ||
5066 | * would have already happened in close and is redundant. */ | ||
5067 | e1000_release_hw_control(adapter); | ||
5068 | |||
5069 | pci_disable_device(pdev); | 4566 | pci_disable_device(pdev); |
5070 | 4567 | ||
5071 | return 0; | 4568 | return 0; |
@@ -5131,14 +4628,6 @@ static int e1000_resume(struct pci_dev *pdev) | |||
5131 | 4628 | ||
5132 | netif_device_attach(netdev); | 4629 | netif_device_attach(netdev); |
5133 | 4630 | ||
5134 | /* If the controller is 82573 and f/w is AMT, do not set | ||
5135 | * DRV_LOAD until the interface is up. For all other cases, | ||
5136 | * let the f/w know that the h/w is now under the control | ||
5137 | * of the driver. */ | ||
5138 | if (hw->mac_type != e1000_82573 || | ||
5139 | !e1000_check_mng_mode(hw)) | ||
5140 | e1000_get_hw_control(adapter); | ||
5141 | |||
5142 | return 0; | 4631 | return 0; |
5143 | } | 4632 | } |
5144 | #endif | 4633 | #endif |
@@ -5174,7 +4663,7 @@ static void e1000_netpoll(struct net_device *netdev) | |||
5174 | /** | 4663 | /** |
5175 | * e1000_io_error_detected - called when PCI error is detected | 4664 | * e1000_io_error_detected - called when PCI error is detected |
5176 | * @pdev: Pointer to PCI device | 4665 | * @pdev: Pointer to PCI device |
5177 | * @state: The current pci conneection state | 4666 | * @state: The current pci connection state |
5178 | * | 4667 | * |
5179 | * This function is called after a PCI bus error affecting | 4668 | * This function is called after a PCI bus error affecting |
5180 | * this device has been detected. | 4669 | * this device has been detected. |
@@ -5243,7 +4732,6 @@ static void e1000_io_resume(struct pci_dev *pdev) | |||
5243 | { | 4732 | { |
5244 | struct net_device *netdev = pci_get_drvdata(pdev); | 4733 | struct net_device *netdev = pci_get_drvdata(pdev); |
5245 | struct e1000_adapter *adapter = netdev_priv(netdev); | 4734 | struct e1000_adapter *adapter = netdev_priv(netdev); |
5246 | struct e1000_hw *hw = &adapter->hw; | ||
5247 | 4735 | ||
5248 | e1000_init_manageability(adapter); | 4736 | e1000_init_manageability(adapter); |
5249 | 4737 | ||
@@ -5255,15 +4743,6 @@ static void e1000_io_resume(struct pci_dev *pdev) | |||
5255 | } | 4743 | } |
5256 | 4744 | ||
5257 | netif_device_attach(netdev); | 4745 | netif_device_attach(netdev); |
5258 | |||
5259 | /* If the controller is 82573 and f/w is AMT, do not set | ||
5260 | * DRV_LOAD until the interface is up. For all other cases, | ||
5261 | * let the f/w know that the h/w is now under the control | ||
5262 | * of the driver. */ | ||
5263 | if (hw->mac_type != e1000_82573 || | ||
5264 | !e1000_check_mng_mode(hw)) | ||
5265 | e1000_get_hw_control(adapter); | ||
5266 | |||
5267 | } | 4746 | } |
5268 | 4747 | ||
5269 | /* e1000_main.c */ | 4748 | /* e1000_main.c */ |
diff --git a/drivers/net/e1000/e1000_param.c b/drivers/net/e1000/e1000_param.c index 213437d13154..38d2741ccae9 100644 --- a/drivers/net/e1000/e1000_param.c +++ b/drivers/net/e1000/e1000_param.c | |||
@@ -518,22 +518,6 @@ void __devinit e1000_check_options(struct e1000_adapter *adapter) | |||
518 | adapter->smart_power_down = opt.def; | 518 | adapter->smart_power_down = opt.def; |
519 | } | 519 | } |
520 | } | 520 | } |
521 | { /* Kumeran Lock Loss Workaround */ | ||
522 | opt = (struct e1000_option) { | ||
523 | .type = enable_option, | ||
524 | .name = "Kumeran Lock Loss Workaround", | ||
525 | .err = "defaulting to Enabled", | ||
526 | .def = OPTION_ENABLED | ||
527 | }; | ||
528 | |||
529 | if (num_KumeranLockLoss > bd) { | ||
530 | unsigned int kmrn_lock_loss = KumeranLockLoss[bd]; | ||
531 | e1000_validate_option(&kmrn_lock_loss, &opt, adapter); | ||
532 | adapter->hw.kmrn_lock_loss_workaround_disabled = !kmrn_lock_loss; | ||
533 | } else { | ||
534 | adapter->hw.kmrn_lock_loss_workaround_disabled = !opt.def; | ||
535 | } | ||
536 | } | ||
537 | 521 | ||
538 | switch (adapter->hw.media_type) { | 522 | switch (adapter->hw.media_type) { |
539 | case e1000_media_type_fiber: | 523 | case e1000_media_type_fiber: |
@@ -626,12 +610,6 @@ static void __devinit e1000_check_copper_options(struct e1000_adapter *adapter) | |||
626 | .p = dplx_list }} | 610 | .p = dplx_list }} |
627 | }; | 611 | }; |
628 | 612 | ||
629 | if (e1000_check_phy_reset_block(&adapter->hw)) { | ||
630 | DPRINTK(PROBE, INFO, | ||
631 | "Link active due to SoL/IDER Session. " | ||
632 | "Speed/Duplex/AutoNeg parameter ignored.\n"); | ||
633 | return; | ||
634 | } | ||
635 | if (num_Duplex > bd) { | 613 | if (num_Duplex > bd) { |
636 | dplx = Duplex[bd]; | 614 | dplx = Duplex[bd]; |
637 | e1000_validate_option(&dplx, &opt, adapter); | 615 | e1000_validate_option(&dplx, &opt, adapter); |
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c index 16c193a6c95c..0687c6aa4e46 100644 --- a/drivers/net/e1000e/netdev.c +++ b/drivers/net/e1000e/netdev.c | |||
@@ -4982,12 +4982,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev, | |||
4982 | goto err_pci_reg; | 4982 | goto err_pci_reg; |
4983 | 4983 | ||
4984 | /* AER (Advanced Error Reporting) hooks */ | 4984 | /* AER (Advanced Error Reporting) hooks */ |
4985 | err = pci_enable_pcie_error_reporting(pdev); | 4985 | pci_enable_pcie_error_reporting(pdev); |
4986 | if (err) { | ||
4987 | dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed " | ||
4988 | "0x%x\n", err); | ||
4989 | /* non-fatal, continue */ | ||
4990 | } | ||
4991 | 4986 | ||
4992 | pci_set_master(pdev); | 4987 | pci_set_master(pdev); |
4993 | /* PCI config space info */ | 4988 | /* PCI config space info */ |
@@ -5263,7 +5258,6 @@ static void __devexit e1000_remove(struct pci_dev *pdev) | |||
5263 | { | 5258 | { |
5264 | struct net_device *netdev = pci_get_drvdata(pdev); | 5259 | struct net_device *netdev = pci_get_drvdata(pdev); |
5265 | struct e1000_adapter *adapter = netdev_priv(netdev); | 5260 | struct e1000_adapter *adapter = netdev_priv(netdev); |
5266 | int err; | ||
5267 | 5261 | ||
5268 | /* | 5262 | /* |
5269 | * flush_scheduled work may reschedule our watchdog task, so | 5263 | * flush_scheduled work may reschedule our watchdog task, so |
@@ -5299,10 +5293,7 @@ static void __devexit e1000_remove(struct pci_dev *pdev) | |||
5299 | free_netdev(netdev); | 5293 | free_netdev(netdev); |
5300 | 5294 | ||
5301 | /* AER disable */ | 5295 | /* AER disable */ |
5302 | err = pci_disable_pcie_error_reporting(pdev); | 5296 | pci_disable_pcie_error_reporting(pdev); |
5303 | if (err) | ||
5304 | dev_err(&pdev->dev, | ||
5305 | "pci_disable_pcie_error_reporting failed 0x%x\n", err); | ||
5306 | 5297 | ||
5307 | pci_disable_device(pdev); | 5298 | pci_disable_device(pdev); |
5308 | } | 5299 | } |
diff --git a/drivers/net/hamradio/mkiss.c b/drivers/net/hamradio/mkiss.c index 33b55f729742..db4b7f1603f6 100644 --- a/drivers/net/hamradio/mkiss.c +++ b/drivers/net/hamradio/mkiss.c | |||
@@ -258,7 +258,7 @@ static void ax_bump(struct mkiss *ax) | |||
258 | } | 258 | } |
259 | if (ax->crcmode != CRC_MODE_SMACK && ax->crcauto) { | 259 | if (ax->crcmode != CRC_MODE_SMACK && ax->crcauto) { |
260 | printk(KERN_INFO | 260 | printk(KERN_INFO |
261 | "mkiss: %s: Switchting to crc-smack\n", | 261 | "mkiss: %s: Switching to crc-smack\n", |
262 | ax->dev->name); | 262 | ax->dev->name); |
263 | ax->crcmode = CRC_MODE_SMACK; | 263 | ax->crcmode = CRC_MODE_SMACK; |
264 | } | 264 | } |
@@ -272,7 +272,7 @@ static void ax_bump(struct mkiss *ax) | |||
272 | } | 272 | } |
273 | if (ax->crcmode != CRC_MODE_FLEX && ax->crcauto) { | 273 | if (ax->crcmode != CRC_MODE_FLEX && ax->crcauto) { |
274 | printk(KERN_INFO | 274 | printk(KERN_INFO |
275 | "mkiss: %s: Switchting to crc-flexnet\n", | 275 | "mkiss: %s: Switching to crc-flexnet\n", |
276 | ax->dev->name); | 276 | ax->dev->name); |
277 | ax->crcmode = CRC_MODE_FLEX; | 277 | ax->crcmode = CRC_MODE_FLEX; |
278 | } | 278 | } |
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c index 5d6c1530a8c0..714c3a4a44ef 100644 --- a/drivers/net/igb/igb_main.c +++ b/drivers/net/igb/igb_main.c | |||
@@ -1246,12 +1246,7 @@ static int __devinit igb_probe(struct pci_dev *pdev, | |||
1246 | if (err) | 1246 | if (err) |
1247 | goto err_pci_reg; | 1247 | goto err_pci_reg; |
1248 | 1248 | ||
1249 | err = pci_enable_pcie_error_reporting(pdev); | 1249 | pci_enable_pcie_error_reporting(pdev); |
1250 | if (err) { | ||
1251 | dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed " | ||
1252 | "0x%x\n", err); | ||
1253 | /* non-fatal, continue */ | ||
1254 | } | ||
1255 | 1250 | ||
1256 | pci_set_master(pdev); | 1251 | pci_set_master(pdev); |
1257 | pci_save_state(pdev); | 1252 | pci_save_state(pdev); |
@@ -1628,7 +1623,6 @@ static void __devexit igb_remove(struct pci_dev *pdev) | |||
1628 | struct net_device *netdev = pci_get_drvdata(pdev); | 1623 | struct net_device *netdev = pci_get_drvdata(pdev); |
1629 | struct igb_adapter *adapter = netdev_priv(netdev); | 1624 | struct igb_adapter *adapter = netdev_priv(netdev); |
1630 | struct e1000_hw *hw = &adapter->hw; | 1625 | struct e1000_hw *hw = &adapter->hw; |
1631 | int err; | ||
1632 | 1626 | ||
1633 | /* flush_scheduled work may reschedule our watchdog task, so | 1627 | /* flush_scheduled work may reschedule our watchdog task, so |
1634 | * explicitly disable watchdog tasks from being rescheduled */ | 1628 | * explicitly disable watchdog tasks from being rescheduled */ |
@@ -1682,10 +1676,7 @@ static void __devexit igb_remove(struct pci_dev *pdev) | |||
1682 | 1676 | ||
1683 | free_netdev(netdev); | 1677 | free_netdev(netdev); |
1684 | 1678 | ||
1685 | err = pci_disable_pcie_error_reporting(pdev); | 1679 | pci_disable_pcie_error_reporting(pdev); |
1686 | if (err) | ||
1687 | dev_err(&pdev->dev, | ||
1688 | "pci_disable_pcie_error_reporting failed 0x%x\n", err); | ||
1689 | 1680 | ||
1690 | pci_disable_device(pdev); | 1681 | pci_disable_device(pdev); |
1691 | } | 1682 | } |
diff --git a/drivers/net/iseries_veth.c b/drivers/net/iseries_veth.c index e36e951cbc65..aa7286bc4364 100644 --- a/drivers/net/iseries_veth.c +++ b/drivers/net/iseries_veth.c | |||
@@ -495,7 +495,7 @@ static void veth_take_cap_ack(struct veth_lpar_connection *cnx, | |||
495 | cnx->remote_lp); | 495 | cnx->remote_lp); |
496 | } else { | 496 | } else { |
497 | memcpy(&cnx->cap_ack_event, event, | 497 | memcpy(&cnx->cap_ack_event, event, |
498 | sizeof(&cnx->cap_ack_event)); | 498 | sizeof(cnx->cap_ack_event)); |
499 | cnx->state |= VETH_STATE_GOTCAPACK; | 499 | cnx->state |= VETH_STATE_GOTCAPACK; |
500 | veth_kick_statemachine(cnx); | 500 | veth_kick_statemachine(cnx); |
501 | } | 501 | } |
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c index 56b12f3192f1..e2d5343f1275 100644 --- a/drivers/net/ixgbe/ixgbe_82598.c +++ b/drivers/net/ixgbe/ixgbe_82598.c | |||
@@ -425,7 +425,7 @@ static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) | |||
425 | #endif /* CONFIG_DCB */ | 425 | #endif /* CONFIG_DCB */ |
426 | default: | 426 | default: |
427 | hw_dbg(hw, "Flow control param set incorrectly\n"); | 427 | hw_dbg(hw, "Flow control param set incorrectly\n"); |
428 | ret_val = -IXGBE_ERR_CONFIG; | 428 | ret_val = IXGBE_ERR_CONFIG; |
429 | goto out; | 429 | goto out; |
430 | break; | 430 | break; |
431 | } | 431 | } |
diff --git a/drivers/net/ixgbe/ixgbe_common.c b/drivers/net/ixgbe/ixgbe_common.c index 6621e172df3d..40ff120a9ad4 100644 --- a/drivers/net/ixgbe/ixgbe_common.c +++ b/drivers/net/ixgbe/ixgbe_common.c | |||
@@ -1355,9 +1355,7 @@ static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) | |||
1355 | /** | 1355 | /** |
1356 | * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses | 1356 | * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses |
1357 | * @hw: pointer to hardware structure | 1357 | * @hw: pointer to hardware structure |
1358 | * @addr_list: the list of new addresses | 1358 | * @uc_list: the list of new addresses |
1359 | * @addr_count: number of addresses | ||
1360 | * @next: iterator function to walk the address list | ||
1361 | * | 1359 | * |
1362 | * The given list replaces any existing list. Clears the secondary addrs from | 1360 | * The given list replaces any existing list. Clears the secondary addrs from |
1363 | * receive address registers. Uses unused receive address registers for the | 1361 | * receive address registers. Uses unused receive address registers for the |
@@ -1663,7 +1661,7 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num) | |||
1663 | #endif /* CONFIG_DCB */ | 1661 | #endif /* CONFIG_DCB */ |
1664 | default: | 1662 | default: |
1665 | hw_dbg(hw, "Flow control param set incorrectly\n"); | 1663 | hw_dbg(hw, "Flow control param set incorrectly\n"); |
1666 | ret_val = -IXGBE_ERR_CONFIG; | 1664 | ret_val = IXGBE_ERR_CONFIG; |
1667 | goto out; | 1665 | goto out; |
1668 | break; | 1666 | break; |
1669 | } | 1667 | } |
@@ -1734,75 +1732,140 @@ s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw) | |||
1734 | s32 ret_val = 0; | 1732 | s32 ret_val = 0; |
1735 | ixgbe_link_speed speed; | 1733 | ixgbe_link_speed speed; |
1736 | u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; | 1734 | u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; |
1735 | u32 links2, anlp1_reg, autoc_reg, links; | ||
1737 | bool link_up; | 1736 | bool link_up; |
1738 | 1737 | ||
1739 | /* | 1738 | /* |
1740 | * AN should have completed when the cable was plugged in. | 1739 | * AN should have completed when the cable was plugged in. |
1741 | * Look for reasons to bail out. Bail out if: | 1740 | * Look for reasons to bail out. Bail out if: |
1742 | * - FC autoneg is disabled, or if | 1741 | * - FC autoneg is disabled, or if |
1743 | * - we don't have multispeed fiber, or if | 1742 | * - link is not up. |
1744 | * - we're not running at 1G, or if | ||
1745 | * - link is not up, or if | ||
1746 | * - link is up but AN did not complete, or if | ||
1747 | * - link is up and AN completed but timed out | ||
1748 | * | 1743 | * |
1749 | * Since we're being called from an LSC, link is already know to be up. | 1744 | * Since we're being called from an LSC, link is already known to be up. |
1750 | * So use link_up_wait_to_complete=false. | 1745 | * So use link_up_wait_to_complete=false. |
1751 | */ | 1746 | */ |
1752 | hw->mac.ops.check_link(hw, &speed, &link_up, false); | 1747 | hw->mac.ops.check_link(hw, &speed, &link_up, false); |
1753 | linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); | 1748 | |
1754 | 1749 | if (hw->fc.disable_fc_autoneg || (!link_up)) { | |
1755 | if (hw->fc.disable_fc_autoneg || | ||
1756 | !hw->phy.multispeed_fiber || | ||
1757 | (speed != IXGBE_LINK_SPEED_1GB_FULL) || | ||
1758 | !link_up || | ||
1759 | ((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || | ||
1760 | ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { | ||
1761 | hw->fc.fc_was_autonegged = false; | 1750 | hw->fc.fc_was_autonegged = false; |
1762 | hw->fc.current_mode = hw->fc.requested_mode; | 1751 | hw->fc.current_mode = hw->fc.requested_mode; |
1763 | hw_dbg(hw, "Autoneg FC was skipped.\n"); | ||
1764 | goto out; | 1752 | goto out; |
1765 | } | 1753 | } |
1766 | 1754 | ||
1767 | /* | 1755 | /* |
1756 | * On backplane, bail out if | ||
1757 | * - backplane autoneg was not completed, or if | ||
1758 | * - link partner is not AN enabled | ||
1759 | */ | ||
1760 | if (hw->phy.media_type == ixgbe_media_type_backplane) { | ||
1761 | links = IXGBE_READ_REG(hw, IXGBE_LINKS); | ||
1762 | links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); | ||
1763 | if (((links & IXGBE_LINKS_KX_AN_COMP) == 0) || | ||
1764 | ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)) { | ||
1765 | hw->fc.fc_was_autonegged = false; | ||
1766 | hw->fc.current_mode = hw->fc.requested_mode; | ||
1767 | goto out; | ||
1768 | } | ||
1769 | } | ||
1770 | |||
1771 | /* | ||
1772 | * On multispeed fiber at 1g, bail out if | ||
1773 | * - link is up but AN did not complete, or if | ||
1774 | * - link is up and AN completed but timed out | ||
1775 | */ | ||
1776 | if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL)) { | ||
1777 | linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); | ||
1778 | if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || | ||
1779 | ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { | ||
1780 | hw->fc.fc_was_autonegged = false; | ||
1781 | hw->fc.current_mode = hw->fc.requested_mode; | ||
1782 | goto out; | ||
1783 | } | ||
1784 | } | ||
1785 | |||
1786 | /* | ||
1768 | * Read the AN advertisement and LP ability registers and resolve | 1787 | * Read the AN advertisement and LP ability registers and resolve |
1769 | * local flow control settings accordingly | 1788 | * local flow control settings accordingly |
1770 | */ | 1789 | */ |
1771 | pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); | 1790 | if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && |
1772 | pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); | 1791 | (hw->phy.media_type != ixgbe_media_type_backplane)) { |
1773 | if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | 1792 | pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); |
1774 | (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { | 1793 | pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); |
1794 | if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1795 | (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { | ||
1796 | /* | ||
1797 | * Now we need to check if the user selected Rx ONLY | ||
1798 | * of pause frames. In this case, we had to advertise | ||
1799 | * FULL flow control because we could not advertise RX | ||
1800 | * ONLY. Hence, we must now check to see if we need to | ||
1801 | * turn OFF the TRANSMISSION of PAUSE frames. | ||
1802 | */ | ||
1803 | if (hw->fc.requested_mode == ixgbe_fc_full) { | ||
1804 | hw->fc.current_mode = ixgbe_fc_full; | ||
1805 | hw_dbg(hw, "Flow Control = FULL.\n"); | ||
1806 | } else { | ||
1807 | hw->fc.current_mode = ixgbe_fc_rx_pause; | ||
1808 | hw_dbg(hw, "Flow Control=RX PAUSE only\n"); | ||
1809 | } | ||
1810 | } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1811 | (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && | ||
1812 | (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1813 | (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { | ||
1814 | hw->fc.current_mode = ixgbe_fc_tx_pause; | ||
1815 | hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); | ||
1816 | } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1817 | (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && | ||
1818 | !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1819 | (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { | ||
1820 | hw->fc.current_mode = ixgbe_fc_rx_pause; | ||
1821 | hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); | ||
1822 | } else { | ||
1823 | hw->fc.current_mode = ixgbe_fc_none; | ||
1824 | hw_dbg(hw, "Flow Control = NONE.\n"); | ||
1825 | } | ||
1826 | } | ||
1827 | |||
1828 | if (hw->phy.media_type == ixgbe_media_type_backplane) { | ||
1775 | /* | 1829 | /* |
1776 | * Now we need to check if the user selected Rx ONLY | 1830 | * Read the 10g AN autoc and LP ability registers and resolve |
1777 | * of pause frames. In this case, we had to advertise | 1831 | * local flow control settings accordingly |
1778 | * FULL flow control because we could not advertise RX | ||
1779 | * ONLY. Hence, we must now check to see if we need to | ||
1780 | * turn OFF the TRANSMISSION of PAUSE frames. | ||
1781 | */ | 1832 | */ |
1782 | if (hw->fc.requested_mode == ixgbe_fc_full) { | 1833 | autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
1783 | hw->fc.current_mode = ixgbe_fc_full; | 1834 | anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); |
1784 | hw_dbg(hw, "Flow Control = FULL.\n"); | 1835 | |
1785 | } else { | 1836 | if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && |
1837 | (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE)) { | ||
1838 | /* | ||
1839 | * Now we need to check if the user selected Rx ONLY | ||
1840 | * of pause frames. In this case, we had to advertise | ||
1841 | * FULL flow control because we could not advertise RX | ||
1842 | * ONLY. Hence, we must now check to see if we need to | ||
1843 | * turn OFF the TRANSMISSION of PAUSE frames. | ||
1844 | */ | ||
1845 | if (hw->fc.requested_mode == ixgbe_fc_full) { | ||
1846 | hw->fc.current_mode = ixgbe_fc_full; | ||
1847 | hw_dbg(hw, "Flow Control = FULL.\n"); | ||
1848 | } else { | ||
1849 | hw->fc.current_mode = ixgbe_fc_rx_pause; | ||
1850 | hw_dbg(hw, "Flow Control=RX PAUSE only\n"); | ||
1851 | } | ||
1852 | } else if (!(autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && | ||
1853 | (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) && | ||
1854 | (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) && | ||
1855 | (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) { | ||
1856 | hw->fc.current_mode = ixgbe_fc_tx_pause; | ||
1857 | hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); | ||
1858 | } else if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && | ||
1859 | (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) && | ||
1860 | !(anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) && | ||
1861 | (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) { | ||
1786 | hw->fc.current_mode = ixgbe_fc_rx_pause; | 1862 | hw->fc.current_mode = ixgbe_fc_rx_pause; |
1787 | hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); | 1863 | hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); |
1864 | } else { | ||
1865 | hw->fc.current_mode = ixgbe_fc_none; | ||
1866 | hw_dbg(hw, "Flow Control = NONE.\n"); | ||
1788 | } | 1867 | } |
1789 | } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1790 | (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && | ||
1791 | (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1792 | (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { | ||
1793 | hw->fc.current_mode = ixgbe_fc_tx_pause; | ||
1794 | hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); | ||
1795 | } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1796 | (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && | ||
1797 | !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && | ||
1798 | (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { | ||
1799 | hw->fc.current_mode = ixgbe_fc_rx_pause; | ||
1800 | hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); | ||
1801 | } else { | ||
1802 | hw->fc.current_mode = ixgbe_fc_none; | ||
1803 | hw_dbg(hw, "Flow Control = NONE.\n"); | ||
1804 | } | 1868 | } |
1805 | |||
1806 | /* Record that current_mode is the result of a successful autoneg */ | 1869 | /* Record that current_mode is the result of a successful autoneg */ |
1807 | hw->fc.fc_was_autonegged = true; | 1870 | hw->fc.fc_was_autonegged = true; |
1808 | 1871 | ||
@@ -1919,7 +1982,7 @@ static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) | |||
1919 | #endif /* CONFIG_DCB */ | 1982 | #endif /* CONFIG_DCB */ |
1920 | default: | 1983 | default: |
1921 | hw_dbg(hw, "Flow control param set incorrectly\n"); | 1984 | hw_dbg(hw, "Flow control param set incorrectly\n"); |
1922 | ret_val = -IXGBE_ERR_CONFIG; | 1985 | ret_val = IXGBE_ERR_CONFIG; |
1923 | goto out; | 1986 | goto out; |
1924 | break; | 1987 | break; |
1925 | } | 1988 | } |
@@ -1927,9 +1990,6 @@ static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) | |||
1927 | IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); | 1990 | IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); |
1928 | reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); | 1991 | reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); |
1929 | 1992 | ||
1930 | /* Enable and restart autoneg to inform the link partner */ | ||
1931 | reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART; | ||
1932 | |||
1933 | /* Disable AN timeout */ | 1993 | /* Disable AN timeout */ |
1934 | if (hw->fc.strict_ieee) | 1994 | if (hw->fc.strict_ieee) |
1935 | reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; | 1995 | reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; |
@@ -1937,6 +1997,70 @@ static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) | |||
1937 | IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); | 1997 | IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); |
1938 | hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); | 1998 | hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); |
1939 | 1999 | ||
2000 | /* | ||
2001 | * Set up the 10G flow control advertisement registers so the HW | ||
2002 | * can do fc autoneg once the cable is plugged in. If we end up | ||
2003 | * using 1g instead, this is harmless. | ||
2004 | */ | ||
2005 | reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); | ||
2006 | |||
2007 | /* | ||
2008 | * The possible values of fc.requested_mode are: | ||
2009 | * 0: Flow control is completely disabled | ||
2010 | * 1: Rx flow control is enabled (we can receive pause frames, | ||
2011 | * but not send pause frames). | ||
2012 | * 2: Tx flow control is enabled (we can send pause frames but | ||
2013 | * we do not support receiving pause frames). | ||
2014 | * 3: Both Rx and Tx flow control (symmetric) are enabled. | ||
2015 | * other: Invalid. | ||
2016 | */ | ||
2017 | switch (hw->fc.requested_mode) { | ||
2018 | case ixgbe_fc_none: | ||
2019 | /* Flow control completely disabled by software override. */ | ||
2020 | reg &= ~(IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); | ||
2021 | break; | ||
2022 | case ixgbe_fc_rx_pause: | ||
2023 | /* | ||
2024 | * Rx Flow control is enabled and Tx Flow control is | ||
2025 | * disabled by software override. Since there really | ||
2026 | * isn't a way to advertise that we are capable of RX | ||
2027 | * Pause ONLY, we will advertise that we support both | ||
2028 | * symmetric and asymmetric Rx PAUSE. Later, we will | ||
2029 | * disable the adapter's ability to send PAUSE frames. | ||
2030 | */ | ||
2031 | reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); | ||
2032 | break; | ||
2033 | case ixgbe_fc_tx_pause: | ||
2034 | /* | ||
2035 | * Tx Flow control is enabled, and Rx Flow control is | ||
2036 | * disabled by software override. | ||
2037 | */ | ||
2038 | reg |= (IXGBE_AUTOC_ASM_PAUSE); | ||
2039 | reg &= ~(IXGBE_AUTOC_SYM_PAUSE); | ||
2040 | break; | ||
2041 | case ixgbe_fc_full: | ||
2042 | /* Flow control (both Rx and Tx) is enabled by SW override. */ | ||
2043 | reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); | ||
2044 | break; | ||
2045 | #ifdef CONFIG_DCB | ||
2046 | case ixgbe_fc_pfc: | ||
2047 | goto out; | ||
2048 | break; | ||
2049 | #endif /* CONFIG_DCB */ | ||
2050 | default: | ||
2051 | hw_dbg(hw, "Flow control param set incorrectly\n"); | ||
2052 | ret_val = IXGBE_ERR_CONFIG; | ||
2053 | goto out; | ||
2054 | break; | ||
2055 | } | ||
2056 | /* | ||
2057 | * AUTOC restart handles negotiation of 1G and 10G. There is | ||
2058 | * no need to set the PCS1GCTL register. | ||
2059 | */ | ||
2060 | reg |= IXGBE_AUTOC_AN_RESTART; | ||
2061 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg); | ||
2062 | hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); | ||
2063 | |||
1940 | out: | 2064 | out: |
1941 | return ret_val; | 2065 | return ret_val; |
1942 | } | 2066 | } |
@@ -2000,7 +2124,7 @@ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) | |||
2000 | 2124 | ||
2001 | while (timeout) { | 2125 | while (timeout) { |
2002 | if (ixgbe_get_eeprom_semaphore(hw)) | 2126 | if (ixgbe_get_eeprom_semaphore(hw)) |
2003 | return -IXGBE_ERR_SWFW_SYNC; | 2127 | return IXGBE_ERR_SWFW_SYNC; |
2004 | 2128 | ||
2005 | gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); | 2129 | gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); |
2006 | if (!(gssr & (fwmask | swmask))) | 2130 | if (!(gssr & (fwmask | swmask))) |
@@ -2017,7 +2141,7 @@ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) | |||
2017 | 2141 | ||
2018 | if (!timeout) { | 2142 | if (!timeout) { |
2019 | hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n"); | 2143 | hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n"); |
2020 | return -IXGBE_ERR_SWFW_SYNC; | 2144 | return IXGBE_ERR_SWFW_SYNC; |
2021 | } | 2145 | } |
2022 | 2146 | ||
2023 | gssr |= swmask; | 2147 | gssr |= swmask; |
diff --git a/drivers/net/ixgbe/ixgbe_ethtool.c b/drivers/net/ixgbe/ixgbe_ethtool.c index 53b0a6680254..fa314cb005a4 100644 --- a/drivers/net/ixgbe/ixgbe_ethtool.c +++ b/drivers/net/ixgbe/ixgbe_ethtool.c | |||
@@ -53,6 +53,10 @@ static struct ixgbe_stats ixgbe_gstrings_stats[] = { | |||
53 | {"tx_packets", IXGBE_STAT(net_stats.tx_packets)}, | 53 | {"tx_packets", IXGBE_STAT(net_stats.tx_packets)}, |
54 | {"rx_bytes", IXGBE_STAT(net_stats.rx_bytes)}, | 54 | {"rx_bytes", IXGBE_STAT(net_stats.rx_bytes)}, |
55 | {"tx_bytes", IXGBE_STAT(net_stats.tx_bytes)}, | 55 | {"tx_bytes", IXGBE_STAT(net_stats.tx_bytes)}, |
56 | {"rx_pkts_nic", IXGBE_STAT(stats.gprc)}, | ||
57 | {"tx_pkts_nic", IXGBE_STAT(stats.gptc)}, | ||
58 | {"rx_bytes_nic", IXGBE_STAT(stats.gorc)}, | ||
59 | {"tx_bytes_nic", IXGBE_STAT(stats.gotc)}, | ||
56 | {"lsc_int", IXGBE_STAT(lsc_int)}, | 60 | {"lsc_int", IXGBE_STAT(lsc_int)}, |
57 | {"tx_busy", IXGBE_STAT(tx_busy)}, | 61 | {"tx_busy", IXGBE_STAT(tx_busy)}, |
58 | {"non_eop_descs", IXGBE_STAT(non_eop_descs)}, | 62 | {"non_eop_descs", IXGBE_STAT(non_eop_descs)}, |
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c index c407bd9de0dd..28fbb9d281f9 100644 --- a/drivers/net/ixgbe/ixgbe_main.c +++ b/drivers/net/ixgbe/ixgbe_main.c | |||
@@ -49,7 +49,7 @@ char ixgbe_driver_name[] = "ixgbe"; | |||
49 | static const char ixgbe_driver_string[] = | 49 | static const char ixgbe_driver_string[] = |
50 | "Intel(R) 10 Gigabit PCI Express Network Driver"; | 50 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
51 | 51 | ||
52 | #define DRV_VERSION "2.0.37-k2" | 52 | #define DRV_VERSION "2.0.44-k2" |
53 | const char ixgbe_driver_version[] = DRV_VERSION; | 53 | const char ixgbe_driver_version[] = DRV_VERSION; |
54 | static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation."; | 54 | static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation."; |
55 | 55 | ||
@@ -1885,12 +1885,29 @@ static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |||
1885 | IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); | 1885 | IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); |
1886 | adapter->tx_ring[i].head = IXGBE_TDH(j); | 1886 | adapter->tx_ring[i].head = IXGBE_TDH(j); |
1887 | adapter->tx_ring[i].tail = IXGBE_TDT(j); | 1887 | adapter->tx_ring[i].tail = IXGBE_TDT(j); |
1888 | /* Disable Tx Head Writeback RO bit, since this hoses | 1888 | /* |
1889 | * Disable Tx Head Writeback RO bit, since this hoses | ||
1889 | * bookkeeping if things aren't delivered in order. | 1890 | * bookkeeping if things aren't delivered in order. |
1890 | */ | 1891 | */ |
1891 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); | 1892 | switch (hw->mac.type) { |
1893 | case ixgbe_mac_82598EB: | ||
1894 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); | ||
1895 | break; | ||
1896 | case ixgbe_mac_82599EB: | ||
1897 | default: | ||
1898 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j)); | ||
1899 | break; | ||
1900 | } | ||
1892 | txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; | 1901 | txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; |
1893 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); | 1902 | switch (hw->mac.type) { |
1903 | case ixgbe_mac_82598EB: | ||
1904 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); | ||
1905 | break; | ||
1906 | case ixgbe_mac_82599EB: | ||
1907 | default: | ||
1908 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl); | ||
1909 | break; | ||
1910 | } | ||
1894 | } | 1911 | } |
1895 | if (hw->mac.type == ixgbe_mac_82599EB) { | 1912 | if (hw->mac.type == ixgbe_mac_82599EB) { |
1896 | /* We enable 8 traffic classes, DCB only */ | 1913 | /* We enable 8 traffic classes, DCB only */ |
@@ -4432,10 +4449,13 @@ void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |||
4432 | 4449 | ||
4433 | /* 82598 hardware only has a 32 bit counter in the high register */ | 4450 | /* 82598 hardware only has a 32 bit counter in the high register */ |
4434 | if (hw->mac.type == ixgbe_mac_82599EB) { | 4451 | if (hw->mac.type == ixgbe_mac_82599EB) { |
4452 | u64 tmp; | ||
4435 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); | 4453 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
4436 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ | 4454 | tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */ |
4455 | adapter->stats.gorc += (tmp << 32); | ||
4437 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); | 4456 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); |
4438 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ | 4457 | tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */ |
4458 | adapter->stats.gotc += (tmp << 32); | ||
4439 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL); | 4459 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL); |
4440 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ | 4460 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ |
4441 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); | 4461 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); |
@@ -5071,7 +5091,6 @@ static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb, | |||
5071 | /* Right now, we support IPv4 only */ | 5091 | /* Right now, we support IPv4 only */ |
5072 | struct ixgbe_atr_input atr_input; | 5092 | struct ixgbe_atr_input atr_input; |
5073 | struct tcphdr *th; | 5093 | struct tcphdr *th; |
5074 | struct udphdr *uh; | ||
5075 | struct iphdr *iph = ip_hdr(skb); | 5094 | struct iphdr *iph = ip_hdr(skb); |
5076 | struct ethhdr *eth = (struct ethhdr *)skb->data; | 5095 | struct ethhdr *eth = (struct ethhdr *)skb->data; |
5077 | u16 vlan_id, src_port, dst_port, flex_bytes; | 5096 | u16 vlan_id, src_port, dst_port, flex_bytes; |
@@ -5085,12 +5104,6 @@ static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb, | |||
5085 | dst_port = th->dest; | 5104 | dst_port = th->dest; |
5086 | l4type |= IXGBE_ATR_L4TYPE_TCP; | 5105 | l4type |= IXGBE_ATR_L4TYPE_TCP; |
5087 | /* l4type IPv4 type is 0, no need to assign */ | 5106 | /* l4type IPv4 type is 0, no need to assign */ |
5088 | } else if(iph->protocol == IPPROTO_UDP) { | ||
5089 | uh = udp_hdr(skb); | ||
5090 | src_port = uh->source; | ||
5091 | dst_port = uh->dest; | ||
5092 | l4type |= IXGBE_ATR_L4TYPE_UDP; | ||
5093 | /* l4type IPv4 type is 0, no need to assign */ | ||
5094 | } else { | 5107 | } else { |
5095 | /* Unsupported L4 header, just bail here */ | 5108 | /* Unsupported L4 header, just bail here */ |
5096 | return; | 5109 | return; |
@@ -5494,12 +5507,7 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev, | |||
5494 | goto err_pci_reg; | 5507 | goto err_pci_reg; |
5495 | } | 5508 | } |
5496 | 5509 | ||
5497 | err = pci_enable_pcie_error_reporting(pdev); | 5510 | pci_enable_pcie_error_reporting(pdev); |
5498 | if (err) { | ||
5499 | dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed " | ||
5500 | "0x%x\n", err); | ||
5501 | /* non-fatal, continue */ | ||
5502 | } | ||
5503 | 5511 | ||
5504 | pci_set_master(pdev); | 5512 | pci_set_master(pdev); |
5505 | pci_save_state(pdev); | 5513 | pci_save_state(pdev); |
@@ -5808,7 +5816,6 @@ static void __devexit ixgbe_remove(struct pci_dev *pdev) | |||
5808 | { | 5816 | { |
5809 | struct net_device *netdev = pci_get_drvdata(pdev); | 5817 | struct net_device *netdev = pci_get_drvdata(pdev); |
5810 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | 5818 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
5811 | int err; | ||
5812 | 5819 | ||
5813 | set_bit(__IXGBE_DOWN, &adapter->state); | 5820 | set_bit(__IXGBE_DOWN, &adapter->state); |
5814 | /* clear the module not found bit to make sure the worker won't | 5821 | /* clear the module not found bit to make sure the worker won't |
@@ -5859,10 +5866,7 @@ static void __devexit ixgbe_remove(struct pci_dev *pdev) | |||
5859 | 5866 | ||
5860 | free_netdev(netdev); | 5867 | free_netdev(netdev); |
5861 | 5868 | ||
5862 | err = pci_disable_pcie_error_reporting(pdev); | 5869 | pci_disable_pcie_error_reporting(pdev); |
5863 | if (err) | ||
5864 | dev_err(&pdev->dev, | ||
5865 | "pci_disable_pcie_error_reporting failed 0x%x\n", err); | ||
5866 | 5870 | ||
5867 | pci_disable_device(pdev); | 5871 | pci_disable_device(pdev); |
5868 | } | 5872 | } |
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h index 8761d7899f7d..7c93e923bf2e 100644 --- a/drivers/net/ixgbe/ixgbe_type.h +++ b/drivers/net/ixgbe/ixgbe_type.h | |||
@@ -1336,6 +1336,8 @@ | |||
1336 | #define IXGBE_AUTOC_KX4_SUPP 0x80000000 | 1336 | #define IXGBE_AUTOC_KX4_SUPP 0x80000000 |
1337 | #define IXGBE_AUTOC_KX_SUPP 0x40000000 | 1337 | #define IXGBE_AUTOC_KX_SUPP 0x40000000 |
1338 | #define IXGBE_AUTOC_PAUSE 0x30000000 | 1338 | #define IXGBE_AUTOC_PAUSE 0x30000000 |
1339 | #define IXGBE_AUTOC_ASM_PAUSE 0x20000000 | ||
1340 | #define IXGBE_AUTOC_SYM_PAUSE 0x10000000 | ||
1339 | #define IXGBE_AUTOC_RF 0x08000000 | 1341 | #define IXGBE_AUTOC_RF 0x08000000 |
1340 | #define IXGBE_AUTOC_PD_TMR 0x06000000 | 1342 | #define IXGBE_AUTOC_PD_TMR 0x06000000 |
1341 | #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 | 1343 | #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 |
@@ -1404,6 +1406,8 @@ | |||
1404 | #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ | 1406 | #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ |
1405 | #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ | 1407 | #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ |
1406 | 1408 | ||
1409 | #define IXGBE_LINKS2_AN_SUPPORTED 0x00000040 | ||
1410 | |||
1407 | /* PCS1GLSTA Bit Masks */ | 1411 | /* PCS1GLSTA Bit Masks */ |
1408 | #define IXGBE_PCS1GLSTA_LINK_OK 1 | 1412 | #define IXGBE_PCS1GLSTA_LINK_OK 1 |
1409 | #define IXGBE_PCS1GLSTA_SYNK_OK 0x10 | 1413 | #define IXGBE_PCS1GLSTA_SYNK_OK 0x10 |
@@ -1424,6 +1428,11 @@ | |||
1424 | #define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000 | 1428 | #define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000 |
1425 | #define IXGBE_PCS1GLCTL_AN_RESTART 0x20000 | 1429 | #define IXGBE_PCS1GLCTL_AN_RESTART 0x20000 |
1426 | 1430 | ||
1431 | /* ANLP1 Bit Masks */ | ||
1432 | #define IXGBE_ANLP1_PAUSE 0x0C00 | ||
1433 | #define IXGBE_ANLP1_SYM_PAUSE 0x0400 | ||
1434 | #define IXGBE_ANLP1_ASM_PAUSE 0x0800 | ||
1435 | |||
1427 | /* SW Semaphore Register bitmasks */ | 1436 | /* SW Semaphore Register bitmasks */ |
1428 | #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ | 1437 | #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ |
1429 | #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ | 1438 | #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ |
diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c new file mode 100644 index 000000000000..0be14d702beb --- /dev/null +++ b/drivers/net/ks8851_mll.c | |||
@@ -0,0 +1,1697 @@ | |||
1 | /** | ||
2 | * drivers/net/ks8851_mll.c | ||
3 | * Copyright (c) 2009 Micrel Inc. | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License version 2 as | ||
7 | * published by the Free Software Foundation. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
17 | */ | ||
18 | |||
19 | /** | ||
20 | * Supports: | ||
21 | * KS8851 16bit MLL chip from Micrel Inc. | ||
22 | */ | ||
23 | |||
24 | #include <linux/module.h> | ||
25 | #include <linux/kernel.h> | ||
26 | #include <linux/netdevice.h> | ||
27 | #include <linux/etherdevice.h> | ||
28 | #include <linux/ethtool.h> | ||
29 | #include <linux/cache.h> | ||
30 | #include <linux/crc32.h> | ||
31 | #include <linux/mii.h> | ||
32 | #include <linux/platform_device.h> | ||
33 | #include <linux/delay.h> | ||
34 | |||
35 | #define DRV_NAME "ks8851_mll" | ||
36 | |||
37 | static u8 KS_DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x86, 0x95, 0x11 }; | ||
38 | #define MAX_RECV_FRAMES 32 | ||
39 | #define MAX_BUF_SIZE 2048 | ||
40 | #define TX_BUF_SIZE 2000 | ||
41 | #define RX_BUF_SIZE 2000 | ||
42 | |||
43 | #define KS_CCR 0x08 | ||
44 | #define CCR_EEPROM (1 << 9) | ||
45 | #define CCR_SPI (1 << 8) | ||
46 | #define CCR_8BIT (1 << 7) | ||
47 | #define CCR_16BIT (1 << 6) | ||
48 | #define CCR_32BIT (1 << 5) | ||
49 | #define CCR_SHARED (1 << 4) | ||
50 | #define CCR_32PIN (1 << 0) | ||
51 | |||
52 | /* MAC address registers */ | ||
53 | #define KS_MARL 0x10 | ||
54 | #define KS_MARM 0x12 | ||
55 | #define KS_MARH 0x14 | ||
56 | |||
57 | #define KS_OBCR 0x20 | ||
58 | #define OBCR_ODS_16MA (1 << 6) | ||
59 | |||
60 | #define KS_EEPCR 0x22 | ||
61 | #define EEPCR_EESA (1 << 4) | ||
62 | #define EEPCR_EESB (1 << 3) | ||
63 | #define EEPCR_EEDO (1 << 2) | ||
64 | #define EEPCR_EESCK (1 << 1) | ||
65 | #define EEPCR_EECS (1 << 0) | ||
66 | |||
67 | #define KS_MBIR 0x24 | ||
68 | #define MBIR_TXMBF (1 << 12) | ||
69 | #define MBIR_TXMBFA (1 << 11) | ||
70 | #define MBIR_RXMBF (1 << 4) | ||
71 | #define MBIR_RXMBFA (1 << 3) | ||
72 | |||
73 | #define KS_GRR 0x26 | ||
74 | #define GRR_QMU (1 << 1) | ||
75 | #define GRR_GSR (1 << 0) | ||
76 | |||
77 | #define KS_WFCR 0x2A | ||
78 | #define WFCR_MPRXE (1 << 7) | ||
79 | #define WFCR_WF3E (1 << 3) | ||
80 | #define WFCR_WF2E (1 << 2) | ||
81 | #define WFCR_WF1E (1 << 1) | ||
82 | #define WFCR_WF0E (1 << 0) | ||
83 | |||
84 | #define KS_WF0CRC0 0x30 | ||
85 | #define KS_WF0CRC1 0x32 | ||
86 | #define KS_WF0BM0 0x34 | ||
87 | #define KS_WF0BM1 0x36 | ||
88 | #define KS_WF0BM2 0x38 | ||
89 | #define KS_WF0BM3 0x3A | ||
90 | |||
91 | #define KS_WF1CRC0 0x40 | ||
92 | #define KS_WF1CRC1 0x42 | ||
93 | #define KS_WF1BM0 0x44 | ||
94 | #define KS_WF1BM1 0x46 | ||
95 | #define KS_WF1BM2 0x48 | ||
96 | #define KS_WF1BM3 0x4A | ||
97 | |||
98 | #define KS_WF2CRC0 0x50 | ||
99 | #define KS_WF2CRC1 0x52 | ||
100 | #define KS_WF2BM0 0x54 | ||
101 | #define KS_WF2BM1 0x56 | ||
102 | #define KS_WF2BM2 0x58 | ||
103 | #define KS_WF2BM3 0x5A | ||
104 | |||
105 | #define KS_WF3CRC0 0x60 | ||
106 | #define KS_WF3CRC1 0x62 | ||
107 | #define KS_WF3BM0 0x64 | ||
108 | #define KS_WF3BM1 0x66 | ||
109 | #define KS_WF3BM2 0x68 | ||
110 | #define KS_WF3BM3 0x6A | ||
111 | |||
112 | #define KS_TXCR 0x70 | ||
113 | #define TXCR_TCGICMP (1 << 8) | ||
114 | #define TXCR_TCGUDP (1 << 7) | ||
115 | #define TXCR_TCGTCP (1 << 6) | ||
116 | #define TXCR_TCGIP (1 << 5) | ||
117 | #define TXCR_FTXQ (1 << 4) | ||
118 | #define TXCR_TXFCE (1 << 3) | ||
119 | #define TXCR_TXPE (1 << 2) | ||
120 | #define TXCR_TXCRC (1 << 1) | ||
121 | #define TXCR_TXE (1 << 0) | ||
122 | |||
123 | #define KS_TXSR 0x72 | ||
124 | #define TXSR_TXLC (1 << 13) | ||
125 | #define TXSR_TXMC (1 << 12) | ||
126 | #define TXSR_TXFID_MASK (0x3f << 0) | ||
127 | #define TXSR_TXFID_SHIFT (0) | ||
128 | #define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f) | ||
129 | |||
130 | |||
131 | #define KS_RXCR1 0x74 | ||
132 | #define RXCR1_FRXQ (1 << 15) | ||
133 | #define RXCR1_RXUDPFCC (1 << 14) | ||
134 | #define RXCR1_RXTCPFCC (1 << 13) | ||
135 | #define RXCR1_RXIPFCC (1 << 12) | ||
136 | #define RXCR1_RXPAFMA (1 << 11) | ||
137 | #define RXCR1_RXFCE (1 << 10) | ||
138 | #define RXCR1_RXEFE (1 << 9) | ||
139 | #define RXCR1_RXMAFMA (1 << 8) | ||
140 | #define RXCR1_RXBE (1 << 7) | ||
141 | #define RXCR1_RXME (1 << 6) | ||
142 | #define RXCR1_RXUE (1 << 5) | ||
143 | #define RXCR1_RXAE (1 << 4) | ||
144 | #define RXCR1_RXINVF (1 << 1) | ||
145 | #define RXCR1_RXE (1 << 0) | ||
146 | #define RXCR1_FILTER_MASK (RXCR1_RXINVF | RXCR1_RXAE | \ | ||
147 | RXCR1_RXMAFMA | RXCR1_RXPAFMA) | ||
148 | |||
149 | #define KS_RXCR2 0x76 | ||
150 | #define RXCR2_SRDBL_MASK (0x7 << 5) | ||
151 | #define RXCR2_SRDBL_SHIFT (5) | ||
152 | #define RXCR2_SRDBL_4B (0x0 << 5) | ||
153 | #define RXCR2_SRDBL_8B (0x1 << 5) | ||
154 | #define RXCR2_SRDBL_16B (0x2 << 5) | ||
155 | #define RXCR2_SRDBL_32B (0x3 << 5) | ||
156 | /* #define RXCR2_SRDBL_FRAME (0x4 << 5) */ | ||
157 | #define RXCR2_IUFFP (1 << 4) | ||
158 | #define RXCR2_RXIUFCEZ (1 << 3) | ||
159 | #define RXCR2_UDPLFE (1 << 2) | ||
160 | #define RXCR2_RXICMPFCC (1 << 1) | ||
161 | #define RXCR2_RXSAF (1 << 0) | ||
162 | |||
163 | #define KS_TXMIR 0x78 | ||
164 | |||
165 | #define KS_RXFHSR 0x7C | ||
166 | #define RXFSHR_RXFV (1 << 15) | ||
167 | #define RXFSHR_RXICMPFCS (1 << 13) | ||
168 | #define RXFSHR_RXIPFCS (1 << 12) | ||
169 | #define RXFSHR_RXTCPFCS (1 << 11) | ||
170 | #define RXFSHR_RXUDPFCS (1 << 10) | ||
171 | #define RXFSHR_RXBF (1 << 7) | ||
172 | #define RXFSHR_RXMF (1 << 6) | ||
173 | #define RXFSHR_RXUF (1 << 5) | ||
174 | #define RXFSHR_RXMR (1 << 4) | ||
175 | #define RXFSHR_RXFT (1 << 3) | ||
176 | #define RXFSHR_RXFTL (1 << 2) | ||
177 | #define RXFSHR_RXRF (1 << 1) | ||
178 | #define RXFSHR_RXCE (1 << 0) | ||
179 | #define RXFSHR_ERR (RXFSHR_RXCE | RXFSHR_RXRF |\ | ||
180 | RXFSHR_RXFTL | RXFSHR_RXMR |\ | ||
181 | RXFSHR_RXICMPFCS | RXFSHR_RXIPFCS |\ | ||
182 | RXFSHR_RXTCPFCS) | ||
183 | #define KS_RXFHBCR 0x7E | ||
184 | #define RXFHBCR_CNT_MASK 0x0FFF | ||
185 | |||
186 | #define KS_TXQCR 0x80 | ||
187 | #define TXQCR_AETFE (1 << 2) | ||
188 | #define TXQCR_TXQMAM (1 << 1) | ||
189 | #define TXQCR_METFE (1 << 0) | ||
190 | |||
191 | #define KS_RXQCR 0x82 | ||
192 | #define RXQCR_RXDTTS (1 << 12) | ||
193 | #define RXQCR_RXDBCTS (1 << 11) | ||
194 | #define RXQCR_RXFCTS (1 << 10) | ||
195 | #define RXQCR_RXIPHTOE (1 << 9) | ||
196 | #define RXQCR_RXDTTE (1 << 7) | ||
197 | #define RXQCR_RXDBCTE (1 << 6) | ||
198 | #define RXQCR_RXFCTE (1 << 5) | ||
199 | #define RXQCR_ADRFE (1 << 4) | ||
200 | #define RXQCR_SDA (1 << 3) | ||
201 | #define RXQCR_RRXEF (1 << 0) | ||
202 | #define RXQCR_CMD_CNTL (RXQCR_RXFCTE|RXQCR_ADRFE) | ||
203 | |||
204 | #define KS_TXFDPR 0x84 | ||
205 | #define TXFDPR_TXFPAI (1 << 14) | ||
206 | #define TXFDPR_TXFP_MASK (0x7ff << 0) | ||
207 | #define TXFDPR_TXFP_SHIFT (0) | ||
208 | |||
209 | #define KS_RXFDPR 0x86 | ||
210 | #define RXFDPR_RXFPAI (1 << 14) | ||
211 | |||
212 | #define KS_RXDTTR 0x8C | ||
213 | #define KS_RXDBCTR 0x8E | ||
214 | |||
215 | #define KS_IER 0x90 | ||
216 | #define KS_ISR 0x92 | ||
217 | #define IRQ_LCI (1 << 15) | ||
218 | #define IRQ_TXI (1 << 14) | ||
219 | #define IRQ_RXI (1 << 13) | ||
220 | #define IRQ_RXOI (1 << 11) | ||
221 | #define IRQ_TXPSI (1 << 9) | ||
222 | #define IRQ_RXPSI (1 << 8) | ||
223 | #define IRQ_TXSAI (1 << 6) | ||
224 | #define IRQ_RXWFDI (1 << 5) | ||
225 | #define IRQ_RXMPDI (1 << 4) | ||
226 | #define IRQ_LDI (1 << 3) | ||
227 | #define IRQ_EDI (1 << 2) | ||
228 | #define IRQ_SPIBEI (1 << 1) | ||
229 | #define IRQ_DEDI (1 << 0) | ||
230 | |||
231 | #define KS_RXFCTR 0x9C | ||
232 | #define RXFCTR_THRESHOLD_MASK 0x00FF | ||
233 | |||
234 | #define KS_RXFC 0x9D | ||
235 | #define RXFCTR_RXFC_MASK (0xff << 8) | ||
236 | #define RXFCTR_RXFC_SHIFT (8) | ||
237 | #define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff) | ||
238 | #define RXFCTR_RXFCT_MASK (0xff << 0) | ||
239 | #define RXFCTR_RXFCT_SHIFT (0) | ||
240 | |||
241 | #define KS_TXNTFSR 0x9E | ||
242 | |||
243 | #define KS_MAHTR0 0xA0 | ||
244 | #define KS_MAHTR1 0xA2 | ||
245 | #define KS_MAHTR2 0xA4 | ||
246 | #define KS_MAHTR3 0xA6 | ||
247 | |||
248 | #define KS_FCLWR 0xB0 | ||
249 | #define KS_FCHWR 0xB2 | ||
250 | #define KS_FCOWR 0xB4 | ||
251 | |||
252 | #define KS_CIDER 0xC0 | ||
253 | #define CIDER_ID 0x8870 | ||
254 | #define CIDER_REV_MASK (0x7 << 1) | ||
255 | #define CIDER_REV_SHIFT (1) | ||
256 | #define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7) | ||
257 | |||
258 | #define KS_CGCR 0xC6 | ||
259 | #define KS_IACR 0xC8 | ||
260 | #define IACR_RDEN (1 << 12) | ||
261 | #define IACR_TSEL_MASK (0x3 << 10) | ||
262 | #define IACR_TSEL_SHIFT (10) | ||
263 | #define IACR_TSEL_MIB (0x3 << 10) | ||
264 | #define IACR_ADDR_MASK (0x1f << 0) | ||
265 | #define IACR_ADDR_SHIFT (0) | ||
266 | |||
267 | #define KS_IADLR 0xD0 | ||
268 | #define KS_IAHDR 0xD2 | ||
269 | |||
270 | #define KS_PMECR 0xD4 | ||
271 | #define PMECR_PME_DELAY (1 << 14) | ||
272 | #define PMECR_PME_POL (1 << 12) | ||
273 | #define PMECR_WOL_WAKEUP (1 << 11) | ||
274 | #define PMECR_WOL_MAGICPKT (1 << 10) | ||
275 | #define PMECR_WOL_LINKUP (1 << 9) | ||
276 | #define PMECR_WOL_ENERGY (1 << 8) | ||
277 | #define PMECR_AUTO_WAKE_EN (1 << 7) | ||
278 | #define PMECR_WAKEUP_NORMAL (1 << 6) | ||
279 | #define PMECR_WKEVT_MASK (0xf << 2) | ||
280 | #define PMECR_WKEVT_SHIFT (2) | ||
281 | #define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf) | ||
282 | #define PMECR_WKEVT_ENERGY (0x1 << 2) | ||
283 | #define PMECR_WKEVT_LINK (0x2 << 2) | ||
284 | #define PMECR_WKEVT_MAGICPKT (0x4 << 2) | ||
285 | #define PMECR_WKEVT_FRAME (0x8 << 2) | ||
286 | #define PMECR_PM_MASK (0x3 << 0) | ||
287 | #define PMECR_PM_SHIFT (0) | ||
288 | #define PMECR_PM_NORMAL (0x0 << 0) | ||
289 | #define PMECR_PM_ENERGY (0x1 << 0) | ||
290 | #define PMECR_PM_SOFTDOWN (0x2 << 0) | ||
291 | #define PMECR_PM_POWERSAVE (0x3 << 0) | ||
292 | |||
293 | /* Standard MII PHY data */ | ||
294 | #define KS_P1MBCR 0xE4 | ||
295 | #define P1MBCR_FORCE_FDX (1 << 8) | ||
296 | |||
297 | #define KS_P1MBSR 0xE6 | ||
298 | #define P1MBSR_AN_COMPLETE (1 << 5) | ||
299 | #define P1MBSR_AN_CAPABLE (1 << 3) | ||
300 | #define P1MBSR_LINK_UP (1 << 2) | ||
301 | |||
302 | #define KS_PHY1ILR 0xE8 | ||
303 | #define KS_PHY1IHR 0xEA | ||
304 | #define KS_P1ANAR 0xEC | ||
305 | #define KS_P1ANLPR 0xEE | ||
306 | |||
307 | #define KS_P1SCLMD 0xF4 | ||
308 | #define P1SCLMD_LEDOFF (1 << 15) | ||
309 | #define P1SCLMD_TXIDS (1 << 14) | ||
310 | #define P1SCLMD_RESTARTAN (1 << 13) | ||
311 | #define P1SCLMD_DISAUTOMDIX (1 << 10) | ||
312 | #define P1SCLMD_FORCEMDIX (1 << 9) | ||
313 | #define P1SCLMD_AUTONEGEN (1 << 7) | ||
314 | #define P1SCLMD_FORCE100 (1 << 6) | ||
315 | #define P1SCLMD_FORCEFDX (1 << 5) | ||
316 | #define P1SCLMD_ADV_FLOW (1 << 4) | ||
317 | #define P1SCLMD_ADV_100BT_FDX (1 << 3) | ||
318 | #define P1SCLMD_ADV_100BT_HDX (1 << 2) | ||
319 | #define P1SCLMD_ADV_10BT_FDX (1 << 1) | ||
320 | #define P1SCLMD_ADV_10BT_HDX (1 << 0) | ||
321 | |||
322 | #define KS_P1CR 0xF6 | ||
323 | #define P1CR_HP_MDIX (1 << 15) | ||
324 | #define P1CR_REV_POL (1 << 13) | ||
325 | #define P1CR_OP_100M (1 << 10) | ||
326 | #define P1CR_OP_FDX (1 << 9) | ||
327 | #define P1CR_OP_MDI (1 << 7) | ||
328 | #define P1CR_AN_DONE (1 << 6) | ||
329 | #define P1CR_LINK_GOOD (1 << 5) | ||
330 | #define P1CR_PNTR_FLOW (1 << 4) | ||
331 | #define P1CR_PNTR_100BT_FDX (1 << 3) | ||
332 | #define P1CR_PNTR_100BT_HDX (1 << 2) | ||
333 | #define P1CR_PNTR_10BT_FDX (1 << 1) | ||
334 | #define P1CR_PNTR_10BT_HDX (1 << 0) | ||
335 | |||
336 | /* TX Frame control */ | ||
337 | |||
338 | #define TXFR_TXIC (1 << 15) | ||
339 | #define TXFR_TXFID_MASK (0x3f << 0) | ||
340 | #define TXFR_TXFID_SHIFT (0) | ||
341 | |||
342 | #define KS_P1SR 0xF8 | ||
343 | #define P1SR_HP_MDIX (1 << 15) | ||
344 | #define P1SR_REV_POL (1 << 13) | ||
345 | #define P1SR_OP_100M (1 << 10) | ||
346 | #define P1SR_OP_FDX (1 << 9) | ||
347 | #define P1SR_OP_MDI (1 << 7) | ||
348 | #define P1SR_AN_DONE (1 << 6) | ||
349 | #define P1SR_LINK_GOOD (1 << 5) | ||
350 | #define P1SR_PNTR_FLOW (1 << 4) | ||
351 | #define P1SR_PNTR_100BT_FDX (1 << 3) | ||
352 | #define P1SR_PNTR_100BT_HDX (1 << 2) | ||
353 | #define P1SR_PNTR_10BT_FDX (1 << 1) | ||
354 | #define P1SR_PNTR_10BT_HDX (1 << 0) | ||
355 | |||
356 | #define ENUM_BUS_NONE 0 | ||
357 | #define ENUM_BUS_8BIT 1 | ||
358 | #define ENUM_BUS_16BIT 2 | ||
359 | #define ENUM_BUS_32BIT 3 | ||
360 | |||
361 | #define MAX_MCAST_LST 32 | ||
362 | #define HW_MCAST_SIZE 8 | ||
363 | #define MAC_ADDR_LEN 6 | ||
364 | |||
365 | /** | ||
366 | * union ks_tx_hdr - tx header data | ||
367 | * @txb: The header as bytes | ||
368 | * @txw: The header as 16bit, little-endian words | ||
369 | * | ||
370 | * A dual representation of the tx header data to allow | ||
371 | * access to individual bytes, and to allow 16bit accesses | ||
372 | * with 16bit alignment. | ||
373 | */ | ||
374 | union ks_tx_hdr { | ||
375 | u8 txb[4]; | ||
376 | __le16 txw[2]; | ||
377 | }; | ||
378 | |||
379 | /** | ||
380 | * struct ks_net - KS8851 driver private data | ||
381 | * @net_device : The network device we're bound to | ||
382 | * @hw_addr : start address of data register. | ||
383 | * @hw_addr_cmd : start address of command register. | ||
384 | * @txh : temporaly buffer to save status/length. | ||
385 | * @lock : Lock to ensure that the device is not accessed when busy. | ||
386 | * @pdev : Pointer to platform device. | ||
387 | * @mii : The MII state information for the mii calls. | ||
388 | * @frame_head_info : frame header information for multi-pkt rx. | ||
389 | * @statelock : Lock on this structure for tx list. | ||
390 | * @msg_enable : The message flags controlling driver output (see ethtool). | ||
391 | * @frame_cnt : number of frames received. | ||
392 | * @bus_width : i/o bus width. | ||
393 | * @irq : irq number assigned to this device. | ||
394 | * @rc_rxqcr : Cached copy of KS_RXQCR. | ||
395 | * @rc_txcr : Cached copy of KS_TXCR. | ||
396 | * @rc_ier : Cached copy of KS_IER. | ||
397 | * @sharedbus : Multipex(addr and data bus) mode indicator. | ||
398 | * @cmd_reg_cache : command register cached. | ||
399 | * @cmd_reg_cache_int : command register cached. Used in the irq handler. | ||
400 | * @promiscuous : promiscuous mode indicator. | ||
401 | * @all_mcast : mutlicast indicator. | ||
402 | * @mcast_lst_size : size of multicast list. | ||
403 | * @mcast_lst : multicast list. | ||
404 | * @mcast_bits : multicast enabed. | ||
405 | * @mac_addr : MAC address assigned to this device. | ||
406 | * @fid : frame id. | ||
407 | * @extra_byte : number of extra byte prepended rx pkt. | ||
408 | * @enabled : indicator this device works. | ||
409 | * | ||
410 | * The @lock ensures that the chip is protected when certain operations are | ||
411 | * in progress. When the read or write packet transfer is in progress, most | ||
412 | * of the chip registers are not accessible until the transfer is finished and | ||
413 | * the DMA has been de-asserted. | ||
414 | * | ||
415 | * The @statelock is used to protect information in the structure which may | ||
416 | * need to be accessed via several sources, such as the network driver layer | ||
417 | * or one of the work queues. | ||
418 | * | ||
419 | */ | ||
420 | |||
421 | /* Receive multiplex framer header info */ | ||
422 | struct type_frame_head { | ||
423 | u16 sts; /* Frame status */ | ||
424 | u16 len; /* Byte count */ | ||
425 | }; | ||
426 | |||
427 | struct ks_net { | ||
428 | struct net_device *netdev; | ||
429 | void __iomem *hw_addr; | ||
430 | void __iomem *hw_addr_cmd; | ||
431 | union ks_tx_hdr txh ____cacheline_aligned; | ||
432 | struct mutex lock; /* spinlock to be interrupt safe */ | ||
433 | struct platform_device *pdev; | ||
434 | struct mii_if_info mii; | ||
435 | struct type_frame_head *frame_head_info; | ||
436 | spinlock_t statelock; | ||
437 | u32 msg_enable; | ||
438 | u32 frame_cnt; | ||
439 | int bus_width; | ||
440 | int irq; | ||
441 | |||
442 | u16 rc_rxqcr; | ||
443 | u16 rc_txcr; | ||
444 | u16 rc_ier; | ||
445 | u16 sharedbus; | ||
446 | u16 cmd_reg_cache; | ||
447 | u16 cmd_reg_cache_int; | ||
448 | u16 promiscuous; | ||
449 | u16 all_mcast; | ||
450 | u16 mcast_lst_size; | ||
451 | u8 mcast_lst[MAX_MCAST_LST][MAC_ADDR_LEN]; | ||
452 | u8 mcast_bits[HW_MCAST_SIZE]; | ||
453 | u8 mac_addr[6]; | ||
454 | u8 fid; | ||
455 | u8 extra_byte; | ||
456 | u8 enabled; | ||
457 | }; | ||
458 | |||
459 | static int msg_enable; | ||
460 | |||
461 | #define ks_info(_ks, _msg...) dev_info(&(_ks)->pdev->dev, _msg) | ||
462 | #define ks_warn(_ks, _msg...) dev_warn(&(_ks)->pdev->dev, _msg) | ||
463 | #define ks_dbg(_ks, _msg...) dev_dbg(&(_ks)->pdev->dev, _msg) | ||
464 | #define ks_err(_ks, _msg...) dev_err(&(_ks)->pdev->dev, _msg) | ||
465 | |||
466 | #define BE3 0x8000 /* Byte Enable 3 */ | ||
467 | #define BE2 0x4000 /* Byte Enable 2 */ | ||
468 | #define BE1 0x2000 /* Byte Enable 1 */ | ||
469 | #define BE0 0x1000 /* Byte Enable 0 */ | ||
470 | |||
471 | /** | ||
472 | * register read/write calls. | ||
473 | * | ||
474 | * All these calls issue transactions to access the chip's registers. They | ||
475 | * all require that the necessary lock is held to prevent accesses when the | ||
476 | * chip is busy transfering packet data (RX/TX FIFO accesses). | ||
477 | */ | ||
478 | |||
479 | /** | ||
480 | * ks_rdreg8 - read 8 bit register from device | ||
481 | * @ks : The chip information | ||
482 | * @offset: The register address | ||
483 | * | ||
484 | * Read a 8bit register from the chip, returning the result | ||
485 | */ | ||
486 | static u8 ks_rdreg8(struct ks_net *ks, int offset) | ||
487 | { | ||
488 | u16 data; | ||
489 | u8 shift_bit = offset & 0x03; | ||
490 | u8 shift_data = (offset & 1) << 3; | ||
491 | ks->cmd_reg_cache = (u16) offset | (u16)(BE0 << shift_bit); | ||
492 | iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd); | ||
493 | data = ioread16(ks->hw_addr); | ||
494 | return (u8)(data >> shift_data); | ||
495 | } | ||
496 | |||
497 | /** | ||
498 | * ks_rdreg16 - read 16 bit register from device | ||
499 | * @ks : The chip information | ||
500 | * @offset: The register address | ||
501 | * | ||
502 | * Read a 16bit register from the chip, returning the result | ||
503 | */ | ||
504 | |||
505 | static u16 ks_rdreg16(struct ks_net *ks, int offset) | ||
506 | { | ||
507 | ks->cmd_reg_cache = (u16)offset | ((BE1 | BE0) << (offset & 0x02)); | ||
508 | iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd); | ||
509 | return ioread16(ks->hw_addr); | ||
510 | } | ||
511 | |||
512 | /** | ||
513 | * ks_wrreg8 - write 8bit register value to chip | ||
514 | * @ks: The chip information | ||
515 | * @offset: The register address | ||
516 | * @value: The value to write | ||
517 | * | ||
518 | */ | ||
519 | static void ks_wrreg8(struct ks_net *ks, int offset, u8 value) | ||
520 | { | ||
521 | u8 shift_bit = (offset & 0x03); | ||
522 | u16 value_write = (u16)(value << ((offset & 1) << 3)); | ||
523 | ks->cmd_reg_cache = (u16)offset | (BE0 << shift_bit); | ||
524 | iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd); | ||
525 | iowrite16(value_write, ks->hw_addr); | ||
526 | } | ||
527 | |||
528 | /** | ||
529 | * ks_wrreg16 - write 16bit register value to chip | ||
530 | * @ks: The chip information | ||
531 | * @offset: The register address | ||
532 | * @value: The value to write | ||
533 | * | ||
534 | */ | ||
535 | |||
536 | static void ks_wrreg16(struct ks_net *ks, int offset, u16 value) | ||
537 | { | ||
538 | ks->cmd_reg_cache = (u16)offset | ((BE1 | BE0) << (offset & 0x02)); | ||
539 | iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd); | ||
540 | iowrite16(value, ks->hw_addr); | ||
541 | } | ||
542 | |||
543 | /** | ||
544 | * ks_inblk - read a block of data from QMU. This is called after sudo DMA mode enabled. | ||
545 | * @ks: The chip state | ||
546 | * @wptr: buffer address to save data | ||
547 | * @len: length in byte to read | ||
548 | * | ||
549 | */ | ||
550 | static inline void ks_inblk(struct ks_net *ks, u16 *wptr, u32 len) | ||
551 | { | ||
552 | len >>= 1; | ||
553 | while (len--) | ||
554 | *wptr++ = (u16)ioread16(ks->hw_addr); | ||
555 | } | ||
556 | |||
557 | /** | ||
558 | * ks_outblk - write data to QMU. This is called after sudo DMA mode enabled. | ||
559 | * @ks: The chip information | ||
560 | * @wptr: buffer address | ||
561 | * @len: length in byte to write | ||
562 | * | ||
563 | */ | ||
564 | static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len) | ||
565 | { | ||
566 | len >>= 1; | ||
567 | while (len--) | ||
568 | iowrite16(*wptr++, ks->hw_addr); | ||
569 | } | ||
570 | |||
571 | /** | ||
572 | * ks_tx_fifo_space - return the available hardware buffer size. | ||
573 | * @ks: The chip information | ||
574 | * | ||
575 | */ | ||
576 | static inline u16 ks_tx_fifo_space(struct ks_net *ks) | ||
577 | { | ||
578 | return ks_rdreg16(ks, KS_TXMIR) & 0x1fff; | ||
579 | } | ||
580 | |||
581 | /** | ||
582 | * ks_save_cmd_reg - save the command register from the cache. | ||
583 | * @ks: The chip information | ||
584 | * | ||
585 | */ | ||
586 | static inline void ks_save_cmd_reg(struct ks_net *ks) | ||
587 | { | ||
588 | /*ks8851 MLL has a bug to read back the command register. | ||
589 | * So rely on software to save the content of command register. | ||
590 | */ | ||
591 | ks->cmd_reg_cache_int = ks->cmd_reg_cache; | ||
592 | } | ||
593 | |||
594 | /** | ||
595 | * ks_restore_cmd_reg - restore the command register from the cache and | ||
596 | * write to hardware register. | ||
597 | * @ks: The chip information | ||
598 | * | ||
599 | */ | ||
600 | static inline void ks_restore_cmd_reg(struct ks_net *ks) | ||
601 | { | ||
602 | ks->cmd_reg_cache = ks->cmd_reg_cache_int; | ||
603 | iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd); | ||
604 | } | ||
605 | |||
606 | /** | ||
607 | * ks_set_powermode - set power mode of the device | ||
608 | * @ks: The chip information | ||
609 | * @pwrmode: The power mode value to write to KS_PMECR. | ||
610 | * | ||
611 | * Change the power mode of the chip. | ||
612 | */ | ||
613 | static void ks_set_powermode(struct ks_net *ks, unsigned pwrmode) | ||
614 | { | ||
615 | unsigned pmecr; | ||
616 | |||
617 | if (netif_msg_hw(ks)) | ||
618 | ks_dbg(ks, "setting power mode %d\n", pwrmode); | ||
619 | |||
620 | ks_rdreg16(ks, KS_GRR); | ||
621 | pmecr = ks_rdreg16(ks, KS_PMECR); | ||
622 | pmecr &= ~PMECR_PM_MASK; | ||
623 | pmecr |= pwrmode; | ||
624 | |||
625 | ks_wrreg16(ks, KS_PMECR, pmecr); | ||
626 | } | ||
627 | |||
628 | /** | ||
629 | * ks_read_config - read chip configuration of bus width. | ||
630 | * @ks: The chip information | ||
631 | * | ||
632 | */ | ||
633 | static void ks_read_config(struct ks_net *ks) | ||
634 | { | ||
635 | u16 reg_data = 0; | ||
636 | |||
637 | /* Regardless of bus width, 8 bit read should always work.*/ | ||
638 | reg_data = ks_rdreg8(ks, KS_CCR) & 0x00FF; | ||
639 | reg_data |= ks_rdreg8(ks, KS_CCR+1) << 8; | ||
640 | |||
641 | /* addr/data bus are multiplexed */ | ||
642 | ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED; | ||
643 | |||
644 | /* There are garbage data when reading data from QMU, | ||
645 | depending on bus-width. | ||
646 | */ | ||
647 | |||
648 | if (reg_data & CCR_8BIT) { | ||
649 | ks->bus_width = ENUM_BUS_8BIT; | ||
650 | ks->extra_byte = 1; | ||
651 | } else if (reg_data & CCR_16BIT) { | ||
652 | ks->bus_width = ENUM_BUS_16BIT; | ||
653 | ks->extra_byte = 2; | ||
654 | } else { | ||
655 | ks->bus_width = ENUM_BUS_32BIT; | ||
656 | ks->extra_byte = 4; | ||
657 | } | ||
658 | } | ||
659 | |||
660 | /** | ||
661 | * ks_soft_reset - issue one of the soft reset to the device | ||
662 | * @ks: The device state. | ||
663 | * @op: The bit(s) to set in the GRR | ||
664 | * | ||
665 | * Issue the relevant soft-reset command to the device's GRR register | ||
666 | * specified by @op. | ||
667 | * | ||
668 | * Note, the delays are in there as a caution to ensure that the reset | ||
669 | * has time to take effect and then complete. Since the datasheet does | ||
670 | * not currently specify the exact sequence, we have chosen something | ||
671 | * that seems to work with our device. | ||
672 | */ | ||
673 | static void ks_soft_reset(struct ks_net *ks, unsigned op) | ||
674 | { | ||
675 | /* Disable interrupt first */ | ||
676 | ks_wrreg16(ks, KS_IER, 0x0000); | ||
677 | ks_wrreg16(ks, KS_GRR, op); | ||
678 | mdelay(10); /* wait a short time to effect reset */ | ||
679 | ks_wrreg16(ks, KS_GRR, 0); | ||
680 | mdelay(1); /* wait for condition to clear */ | ||
681 | } | ||
682 | |||
683 | |||
684 | /** | ||
685 | * ks_read_qmu - read 1 pkt data from the QMU. | ||
686 | * @ks: The chip information | ||
687 | * @buf: buffer address to save 1 pkt | ||
688 | * @len: Pkt length | ||
689 | * Here is the sequence to read 1 pkt: | ||
690 | * 1. set sudo DMA mode | ||
691 | * 2. read prepend data | ||
692 | * 3. read pkt data | ||
693 | * 4. reset sudo DMA Mode | ||
694 | */ | ||
695 | static inline void ks_read_qmu(struct ks_net *ks, u16 *buf, u32 len) | ||
696 | { | ||
697 | u32 r = ks->extra_byte & 0x1 ; | ||
698 | u32 w = ks->extra_byte - r; | ||
699 | |||
700 | /* 1. set sudo DMA mode */ | ||
701 | ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI); | ||
702 | ks_wrreg8(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff); | ||
703 | |||
704 | /* 2. read prepend data */ | ||
705 | /** | ||
706 | * read 4 + extra bytes and discard them. | ||
707 | * extra bytes for dummy, 2 for status, 2 for len | ||
708 | */ | ||
709 | |||
710 | /* use likely(r) for 8 bit access for performance */ | ||
711 | if (unlikely(r)) | ||
712 | ioread8(ks->hw_addr); | ||
713 | ks_inblk(ks, buf, w + 2 + 2); | ||
714 | |||
715 | /* 3. read pkt data */ | ||
716 | ks_inblk(ks, buf, ALIGN(len, 4)); | ||
717 | |||
718 | /* 4. reset sudo DMA Mode */ | ||
719 | ks_wrreg8(ks, KS_RXQCR, ks->rc_rxqcr); | ||
720 | } | ||
721 | |||
722 | /** | ||
723 | * ks_rcv - read multiple pkts data from the QMU. | ||
724 | * @ks: The chip information | ||
725 | * @netdev: The network device being opened. | ||
726 | * | ||
727 | * Read all of header information before reading pkt content. | ||
728 | * It is not allowed only port of pkts in QMU after issuing | ||
729 | * interrupt ack. | ||
730 | */ | ||
731 | static void ks_rcv(struct ks_net *ks, struct net_device *netdev) | ||
732 | { | ||
733 | u32 i; | ||
734 | struct type_frame_head *frame_hdr = ks->frame_head_info; | ||
735 | struct sk_buff *skb; | ||
736 | |||
737 | ks->frame_cnt = ks_rdreg16(ks, KS_RXFCTR) >> 8; | ||
738 | |||
739 | /* read all header information */ | ||
740 | for (i = 0; i < ks->frame_cnt; i++) { | ||
741 | /* Checking Received packet status */ | ||
742 | frame_hdr->sts = ks_rdreg16(ks, KS_RXFHSR); | ||
743 | /* Get packet len from hardware */ | ||
744 | frame_hdr->len = ks_rdreg16(ks, KS_RXFHBCR); | ||
745 | frame_hdr++; | ||
746 | } | ||
747 | |||
748 | frame_hdr = ks->frame_head_info; | ||
749 | while (ks->frame_cnt--) { | ||
750 | skb = dev_alloc_skb(frame_hdr->len + 16); | ||
751 | if (likely(skb && (frame_hdr->sts & RXFSHR_RXFV) && | ||
752 | (frame_hdr->len < RX_BUF_SIZE) && frame_hdr->len)) { | ||
753 | skb_reserve(skb, 2); | ||
754 | /* read data block including CRC 4 bytes */ | ||
755 | ks_read_qmu(ks, (u16 *)skb->data, frame_hdr->len + 4); | ||
756 | skb_put(skb, frame_hdr->len); | ||
757 | skb->dev = netdev; | ||
758 | skb->protocol = eth_type_trans(skb, netdev); | ||
759 | netif_rx(skb); | ||
760 | } else { | ||
761 | printk(KERN_ERR "%s: err:skb alloc\n", __func__); | ||
762 | ks_wrreg16(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF)); | ||
763 | if (skb) | ||
764 | dev_kfree_skb_irq(skb); | ||
765 | } | ||
766 | frame_hdr++; | ||
767 | } | ||
768 | } | ||
769 | |||
770 | /** | ||
771 | * ks_update_link_status - link status update. | ||
772 | * @netdev: The network device being opened. | ||
773 | * @ks: The chip information | ||
774 | * | ||
775 | */ | ||
776 | |||
777 | static void ks_update_link_status(struct net_device *netdev, struct ks_net *ks) | ||
778 | { | ||
779 | /* check the status of the link */ | ||
780 | u32 link_up_status; | ||
781 | if (ks_rdreg16(ks, KS_P1SR) & P1SR_LINK_GOOD) { | ||
782 | netif_carrier_on(netdev); | ||
783 | link_up_status = true; | ||
784 | } else { | ||
785 | netif_carrier_off(netdev); | ||
786 | link_up_status = false; | ||
787 | } | ||
788 | if (netif_msg_link(ks)) | ||
789 | ks_dbg(ks, "%s: %s\n", | ||
790 | __func__, link_up_status ? "UP" : "DOWN"); | ||
791 | } | ||
792 | |||
793 | /** | ||
794 | * ks_irq - device interrupt handler | ||
795 | * @irq: Interrupt number passed from the IRQ hnalder. | ||
796 | * @pw: The private word passed to register_irq(), our struct ks_net. | ||
797 | * | ||
798 | * This is the handler invoked to find out what happened | ||
799 | * | ||
800 | * Read the interrupt status, work out what needs to be done and then clear | ||
801 | * any of the interrupts that are not needed. | ||
802 | */ | ||
803 | |||
804 | static irqreturn_t ks_irq(int irq, void *pw) | ||
805 | { | ||
806 | struct ks_net *ks = pw; | ||
807 | struct net_device *netdev = ks->netdev; | ||
808 | u16 status; | ||
809 | |||
810 | /*this should be the first in IRQ handler */ | ||
811 | ks_save_cmd_reg(ks); | ||
812 | |||
813 | status = ks_rdreg16(ks, KS_ISR); | ||
814 | if (unlikely(!status)) { | ||
815 | ks_restore_cmd_reg(ks); | ||
816 | return IRQ_NONE; | ||
817 | } | ||
818 | |||
819 | ks_wrreg16(ks, KS_ISR, status); | ||
820 | |||
821 | if (likely(status & IRQ_RXI)) | ||
822 | ks_rcv(ks, netdev); | ||
823 | |||
824 | if (unlikely(status & IRQ_LCI)) | ||
825 | ks_update_link_status(netdev, ks); | ||
826 | |||
827 | if (unlikely(status & IRQ_TXI)) | ||
828 | netif_wake_queue(netdev); | ||
829 | |||
830 | if (unlikely(status & IRQ_LDI)) { | ||
831 | |||
832 | u16 pmecr = ks_rdreg16(ks, KS_PMECR); | ||
833 | pmecr &= ~PMECR_WKEVT_MASK; | ||
834 | ks_wrreg16(ks, KS_PMECR, pmecr | PMECR_WKEVT_LINK); | ||
835 | } | ||
836 | |||
837 | /* this should be the last in IRQ handler*/ | ||
838 | ks_restore_cmd_reg(ks); | ||
839 | return IRQ_HANDLED; | ||
840 | } | ||
841 | |||
842 | |||
843 | /** | ||
844 | * ks_net_open - open network device | ||
845 | * @netdev: The network device being opened. | ||
846 | * | ||
847 | * Called when the network device is marked active, such as a user executing | ||
848 | * 'ifconfig up' on the device. | ||
849 | */ | ||
850 | static int ks_net_open(struct net_device *netdev) | ||
851 | { | ||
852 | struct ks_net *ks = netdev_priv(netdev); | ||
853 | int err; | ||
854 | |||
855 | #define KS_INT_FLAGS (IRQF_DISABLED|IRQF_TRIGGER_LOW) | ||
856 | /* lock the card, even if we may not actually do anything | ||
857 | * else at the moment. | ||
858 | */ | ||
859 | |||
860 | if (netif_msg_ifup(ks)) | ||
861 | ks_dbg(ks, "%s - entry\n", __func__); | ||
862 | |||
863 | /* reset the HW */ | ||
864 | err = request_irq(ks->irq, ks_irq, KS_INT_FLAGS, DRV_NAME, ks); | ||
865 | |||
866 | if (err) { | ||
867 | printk(KERN_ERR "Failed to request IRQ: %d: %d\n", | ||
868 | ks->irq, err); | ||
869 | return err; | ||
870 | } | ||
871 | |||
872 | if (netif_msg_ifup(ks)) | ||
873 | ks_dbg(ks, "network device %s up\n", netdev->name); | ||
874 | |||
875 | return 0; | ||
876 | } | ||
877 | |||
878 | /** | ||
879 | * ks_net_stop - close network device | ||
880 | * @netdev: The device being closed. | ||
881 | * | ||
882 | * Called to close down a network device which has been active. Cancell any | ||
883 | * work, shutdown the RX and TX process and then place the chip into a low | ||
884 | * power state whilst it is not being used. | ||
885 | */ | ||
886 | static int ks_net_stop(struct net_device *netdev) | ||
887 | { | ||
888 | struct ks_net *ks = netdev_priv(netdev); | ||
889 | |||
890 | if (netif_msg_ifdown(ks)) | ||
891 | ks_info(ks, "%s: shutting down\n", netdev->name); | ||
892 | |||
893 | netif_stop_queue(netdev); | ||
894 | |||
895 | kfree(ks->frame_head_info); | ||
896 | |||
897 | mutex_lock(&ks->lock); | ||
898 | |||
899 | /* turn off the IRQs and ack any outstanding */ | ||
900 | ks_wrreg16(ks, KS_IER, 0x0000); | ||
901 | ks_wrreg16(ks, KS_ISR, 0xffff); | ||
902 | |||
903 | /* shutdown RX process */ | ||
904 | ks_wrreg16(ks, KS_RXCR1, 0x0000); | ||
905 | |||
906 | /* shutdown TX process */ | ||
907 | ks_wrreg16(ks, KS_TXCR, 0x0000); | ||
908 | |||
909 | /* set powermode to soft power down to save power */ | ||
910 | ks_set_powermode(ks, PMECR_PM_SOFTDOWN); | ||
911 | free_irq(ks->irq, netdev); | ||
912 | mutex_unlock(&ks->lock); | ||
913 | return 0; | ||
914 | } | ||
915 | |||
916 | |||
917 | /** | ||
918 | * ks_write_qmu - write 1 pkt data to the QMU. | ||
919 | * @ks: The chip information | ||
920 | * @pdata: buffer address to save 1 pkt | ||
921 | * @len: Pkt length in byte | ||
922 | * Here is the sequence to write 1 pkt: | ||
923 | * 1. set sudo DMA mode | ||
924 | * 2. write status/length | ||
925 | * 3. write pkt data | ||
926 | * 4. reset sudo DMA Mode | ||
927 | * 5. reset sudo DMA mode | ||
928 | * 6. Wait until pkt is out | ||
929 | */ | ||
930 | static void ks_write_qmu(struct ks_net *ks, u8 *pdata, u16 len) | ||
931 | { | ||
932 | unsigned fid = ks->fid; | ||
933 | |||
934 | fid = ks->fid; | ||
935 | ks->fid = (ks->fid + 1) & TXFR_TXFID_MASK; | ||
936 | |||
937 | /* reduce the tx interrupt occurrances. */ | ||
938 | if (!fid) | ||
939 | fid |= TXFR_TXIC; /* irq on completion */ | ||
940 | |||
941 | /* start header at txb[0] to align txw entries */ | ||
942 | ks->txh.txw[0] = cpu_to_le16(fid); | ||
943 | ks->txh.txw[1] = cpu_to_le16(len); | ||
944 | |||
945 | /* 1. set sudo-DMA mode */ | ||
946 | ks_wrreg8(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff); | ||
947 | /* 2. write status/lenth info */ | ||
948 | ks_outblk(ks, ks->txh.txw, 4); | ||
949 | /* 3. write pkt data */ | ||
950 | ks_outblk(ks, (u16 *)pdata, ALIGN(len, 4)); | ||
951 | /* 4. reset sudo-DMA mode */ | ||
952 | ks_wrreg8(ks, KS_RXQCR, ks->rc_rxqcr); | ||
953 | /* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */ | ||
954 | ks_wrreg16(ks, KS_TXQCR, TXQCR_METFE); | ||
955 | /* 6. wait until TXQCR_METFE is auto-cleared */ | ||
956 | while (ks_rdreg16(ks, KS_TXQCR) & TXQCR_METFE) | ||
957 | ; | ||
958 | } | ||
959 | |||
960 | static void ks_disable_int(struct ks_net *ks) | ||
961 | { | ||
962 | ks_wrreg16(ks, KS_IER, 0x0000); | ||
963 | } /* ks_disable_int */ | ||
964 | |||
965 | static void ks_enable_int(struct ks_net *ks) | ||
966 | { | ||
967 | ks_wrreg16(ks, KS_IER, ks->rc_ier); | ||
968 | } /* ks_enable_int */ | ||
969 | |||
970 | /** | ||
971 | * ks_start_xmit - transmit packet | ||
972 | * @skb : The buffer to transmit | ||
973 | * @netdev : The device used to transmit the packet. | ||
974 | * | ||
975 | * Called by the network layer to transmit the @skb. | ||
976 | * spin_lock_irqsave is required because tx and rx should be mutual exclusive. | ||
977 | * So while tx is in-progress, prevent IRQ interrupt from happenning. | ||
978 | */ | ||
979 | static int ks_start_xmit(struct sk_buff *skb, struct net_device *netdev) | ||
980 | { | ||
981 | int retv = NETDEV_TX_OK; | ||
982 | struct ks_net *ks = netdev_priv(netdev); | ||
983 | |||
984 | disable_irq(netdev->irq); | ||
985 | ks_disable_int(ks); | ||
986 | spin_lock(&ks->statelock); | ||
987 | |||
988 | /* Extra space are required: | ||
989 | * 4 byte for alignment, 4 for status/length, 4 for CRC | ||
990 | */ | ||
991 | |||
992 | if (likely(ks_tx_fifo_space(ks) >= skb->len + 12)) { | ||
993 | ks_write_qmu(ks, skb->data, skb->len); | ||
994 | dev_kfree_skb(skb); | ||
995 | } else | ||
996 | retv = NETDEV_TX_BUSY; | ||
997 | spin_unlock(&ks->statelock); | ||
998 | ks_enable_int(ks); | ||
999 | enable_irq(netdev->irq); | ||
1000 | return retv; | ||
1001 | } | ||
1002 | |||
1003 | /** | ||
1004 | * ks_start_rx - ready to serve pkts | ||
1005 | * @ks : The chip information | ||
1006 | * | ||
1007 | */ | ||
1008 | static void ks_start_rx(struct ks_net *ks) | ||
1009 | { | ||
1010 | u16 cntl; | ||
1011 | |||
1012 | /* Enables QMU Receive (RXCR1). */ | ||
1013 | cntl = ks_rdreg16(ks, KS_RXCR1); | ||
1014 | cntl |= RXCR1_RXE ; | ||
1015 | ks_wrreg16(ks, KS_RXCR1, cntl); | ||
1016 | } /* ks_start_rx */ | ||
1017 | |||
1018 | /** | ||
1019 | * ks_stop_rx - stop to serve pkts | ||
1020 | * @ks : The chip information | ||
1021 | * | ||
1022 | */ | ||
1023 | static void ks_stop_rx(struct ks_net *ks) | ||
1024 | { | ||
1025 | u16 cntl; | ||
1026 | |||
1027 | /* Disables QMU Receive (RXCR1). */ | ||
1028 | cntl = ks_rdreg16(ks, KS_RXCR1); | ||
1029 | cntl &= ~RXCR1_RXE ; | ||
1030 | ks_wrreg16(ks, KS_RXCR1, cntl); | ||
1031 | |||
1032 | } /* ks_stop_rx */ | ||
1033 | |||
1034 | static unsigned long const ethernet_polynomial = 0x04c11db7U; | ||
1035 | |||
1036 | static unsigned long ether_gen_crc(int length, u8 *data) | ||
1037 | { | ||
1038 | long crc = -1; | ||
1039 | while (--length >= 0) { | ||
1040 | u8 current_octet = *data++; | ||
1041 | int bit; | ||
1042 | |||
1043 | for (bit = 0; bit < 8; bit++, current_octet >>= 1) { | ||
1044 | crc = (crc << 1) ^ | ||
1045 | ((crc < 0) ^ (current_octet & 1) ? | ||
1046 | ethernet_polynomial : 0); | ||
1047 | } | ||
1048 | } | ||
1049 | return (unsigned long)crc; | ||
1050 | } /* ether_gen_crc */ | ||
1051 | |||
1052 | /** | ||
1053 | * ks_set_grpaddr - set multicast information | ||
1054 | * @ks : The chip information | ||
1055 | */ | ||
1056 | |||
1057 | static void ks_set_grpaddr(struct ks_net *ks) | ||
1058 | { | ||
1059 | u8 i; | ||
1060 | u32 index, position, value; | ||
1061 | |||
1062 | memset(ks->mcast_bits, 0, sizeof(u8) * HW_MCAST_SIZE); | ||
1063 | |||
1064 | for (i = 0; i < ks->mcast_lst_size; i++) { | ||
1065 | position = (ether_gen_crc(6, ks->mcast_lst[i]) >> 26) & 0x3f; | ||
1066 | index = position >> 3; | ||
1067 | value = 1 << (position & 7); | ||
1068 | ks->mcast_bits[index] |= (u8)value; | ||
1069 | } | ||
1070 | |||
1071 | for (i = 0; i < HW_MCAST_SIZE; i++) { | ||
1072 | if (i & 1) { | ||
1073 | ks_wrreg16(ks, (u16)((KS_MAHTR0 + i) & ~1), | ||
1074 | (ks->mcast_bits[i] << 8) | | ||
1075 | ks->mcast_bits[i - 1]); | ||
1076 | } | ||
1077 | } | ||
1078 | } /* ks_set_grpaddr */ | ||
1079 | |||
1080 | /* | ||
1081 | * ks_clear_mcast - clear multicast information | ||
1082 | * | ||
1083 | * @ks : The chip information | ||
1084 | * This routine removes all mcast addresses set in the hardware. | ||
1085 | */ | ||
1086 | |||
1087 | static void ks_clear_mcast(struct ks_net *ks) | ||
1088 | { | ||
1089 | u16 i, mcast_size; | ||
1090 | for (i = 0; i < HW_MCAST_SIZE; i++) | ||
1091 | ks->mcast_bits[i] = 0; | ||
1092 | |||
1093 | mcast_size = HW_MCAST_SIZE >> 2; | ||
1094 | for (i = 0; i < mcast_size; i++) | ||
1095 | ks_wrreg16(ks, KS_MAHTR0 + (2*i), 0); | ||
1096 | } | ||
1097 | |||
1098 | static void ks_set_promis(struct ks_net *ks, u16 promiscuous_mode) | ||
1099 | { | ||
1100 | u16 cntl; | ||
1101 | ks->promiscuous = promiscuous_mode; | ||
1102 | ks_stop_rx(ks); /* Stop receiving for reconfiguration */ | ||
1103 | cntl = ks_rdreg16(ks, KS_RXCR1); | ||
1104 | |||
1105 | cntl &= ~RXCR1_FILTER_MASK; | ||
1106 | if (promiscuous_mode) | ||
1107 | /* Enable Promiscuous mode */ | ||
1108 | cntl |= RXCR1_RXAE | RXCR1_RXINVF; | ||
1109 | else | ||
1110 | /* Disable Promiscuous mode (default normal mode) */ | ||
1111 | cntl |= RXCR1_RXPAFMA; | ||
1112 | |||
1113 | ks_wrreg16(ks, KS_RXCR1, cntl); | ||
1114 | |||
1115 | if (ks->enabled) | ||
1116 | ks_start_rx(ks); | ||
1117 | |||
1118 | } /* ks_set_promis */ | ||
1119 | |||
1120 | static void ks_set_mcast(struct ks_net *ks, u16 mcast) | ||
1121 | { | ||
1122 | u16 cntl; | ||
1123 | |||
1124 | ks->all_mcast = mcast; | ||
1125 | ks_stop_rx(ks); /* Stop receiving for reconfiguration */ | ||
1126 | cntl = ks_rdreg16(ks, KS_RXCR1); | ||
1127 | cntl &= ~RXCR1_FILTER_MASK; | ||
1128 | if (mcast) | ||
1129 | /* Enable "Perfect with Multicast address passed mode" */ | ||
1130 | cntl |= (RXCR1_RXAE | RXCR1_RXMAFMA | RXCR1_RXPAFMA); | ||
1131 | else | ||
1132 | /** | ||
1133 | * Disable "Perfect with Multicast address passed | ||
1134 | * mode" (normal mode). | ||
1135 | */ | ||
1136 | cntl |= RXCR1_RXPAFMA; | ||
1137 | |||
1138 | ks_wrreg16(ks, KS_RXCR1, cntl); | ||
1139 | |||
1140 | if (ks->enabled) | ||
1141 | ks_start_rx(ks); | ||
1142 | } /* ks_set_mcast */ | ||
1143 | |||
1144 | static void ks_set_rx_mode(struct net_device *netdev) | ||
1145 | { | ||
1146 | struct ks_net *ks = netdev_priv(netdev); | ||
1147 | struct dev_mc_list *ptr; | ||
1148 | |||
1149 | /* Turn on/off promiscuous mode. */ | ||
1150 | if ((netdev->flags & IFF_PROMISC) == IFF_PROMISC) | ||
1151 | ks_set_promis(ks, | ||
1152 | (u16)((netdev->flags & IFF_PROMISC) == IFF_PROMISC)); | ||
1153 | /* Turn on/off all mcast mode. */ | ||
1154 | else if ((netdev->flags & IFF_ALLMULTI) == IFF_ALLMULTI) | ||
1155 | ks_set_mcast(ks, | ||
1156 | (u16)((netdev->flags & IFF_ALLMULTI) == IFF_ALLMULTI)); | ||
1157 | else | ||
1158 | ks_set_promis(ks, false); | ||
1159 | |||
1160 | if ((netdev->flags & IFF_MULTICAST) && netdev->mc_count) { | ||
1161 | if (netdev->mc_count <= MAX_MCAST_LST) { | ||
1162 | int i = 0; | ||
1163 | for (ptr = netdev->mc_list; ptr; ptr = ptr->next) { | ||
1164 | if (!(*ptr->dmi_addr & 1)) | ||
1165 | continue; | ||
1166 | if (i >= MAX_MCAST_LST) | ||
1167 | break; | ||
1168 | memcpy(ks->mcast_lst[i++], ptr->dmi_addr, | ||
1169 | MAC_ADDR_LEN); | ||
1170 | } | ||
1171 | ks->mcast_lst_size = (u8)i; | ||
1172 | ks_set_grpaddr(ks); | ||
1173 | } else { | ||
1174 | /** | ||
1175 | * List too big to support so | ||
1176 | * turn on all mcast mode. | ||
1177 | */ | ||
1178 | ks->mcast_lst_size = MAX_MCAST_LST; | ||
1179 | ks_set_mcast(ks, true); | ||
1180 | } | ||
1181 | } else { | ||
1182 | ks->mcast_lst_size = 0; | ||
1183 | ks_clear_mcast(ks); | ||
1184 | } | ||
1185 | } /* ks_set_rx_mode */ | ||
1186 | |||
1187 | static void ks_set_mac(struct ks_net *ks, u8 *data) | ||
1188 | { | ||
1189 | u16 *pw = (u16 *)data; | ||
1190 | u16 w, u; | ||
1191 | |||
1192 | ks_stop_rx(ks); /* Stop receiving for reconfiguration */ | ||
1193 | |||
1194 | u = *pw++; | ||
1195 | w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF); | ||
1196 | ks_wrreg16(ks, KS_MARH, w); | ||
1197 | |||
1198 | u = *pw++; | ||
1199 | w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF); | ||
1200 | ks_wrreg16(ks, KS_MARM, w); | ||
1201 | |||
1202 | u = *pw; | ||
1203 | w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF); | ||
1204 | ks_wrreg16(ks, KS_MARL, w); | ||
1205 | |||
1206 | memcpy(ks->mac_addr, data, 6); | ||
1207 | |||
1208 | if (ks->enabled) | ||
1209 | ks_start_rx(ks); | ||
1210 | } | ||
1211 | |||
1212 | static int ks_set_mac_address(struct net_device *netdev, void *paddr) | ||
1213 | { | ||
1214 | struct ks_net *ks = netdev_priv(netdev); | ||
1215 | struct sockaddr *addr = paddr; | ||
1216 | u8 *da; | ||
1217 | |||
1218 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | ||
1219 | |||
1220 | da = (u8 *)netdev->dev_addr; | ||
1221 | |||
1222 | ks_set_mac(ks, da); | ||
1223 | return 0; | ||
1224 | } | ||
1225 | |||
1226 | static int ks_net_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | ||
1227 | { | ||
1228 | struct ks_net *ks = netdev_priv(netdev); | ||
1229 | |||
1230 | if (!netif_running(netdev)) | ||
1231 | return -EINVAL; | ||
1232 | |||
1233 | return generic_mii_ioctl(&ks->mii, if_mii(req), cmd, NULL); | ||
1234 | } | ||
1235 | |||
1236 | static const struct net_device_ops ks_netdev_ops = { | ||
1237 | .ndo_open = ks_net_open, | ||
1238 | .ndo_stop = ks_net_stop, | ||
1239 | .ndo_do_ioctl = ks_net_ioctl, | ||
1240 | .ndo_start_xmit = ks_start_xmit, | ||
1241 | .ndo_set_mac_address = ks_set_mac_address, | ||
1242 | .ndo_set_rx_mode = ks_set_rx_mode, | ||
1243 | .ndo_change_mtu = eth_change_mtu, | ||
1244 | .ndo_validate_addr = eth_validate_addr, | ||
1245 | }; | ||
1246 | |||
1247 | /* ethtool support */ | ||
1248 | |||
1249 | static void ks_get_drvinfo(struct net_device *netdev, | ||
1250 | struct ethtool_drvinfo *di) | ||
1251 | { | ||
1252 | strlcpy(di->driver, DRV_NAME, sizeof(di->driver)); | ||
1253 | strlcpy(di->version, "1.00", sizeof(di->version)); | ||
1254 | strlcpy(di->bus_info, dev_name(netdev->dev.parent), | ||
1255 | sizeof(di->bus_info)); | ||
1256 | } | ||
1257 | |||
1258 | static u32 ks_get_msglevel(struct net_device *netdev) | ||
1259 | { | ||
1260 | struct ks_net *ks = netdev_priv(netdev); | ||
1261 | return ks->msg_enable; | ||
1262 | } | ||
1263 | |||
1264 | static void ks_set_msglevel(struct net_device *netdev, u32 to) | ||
1265 | { | ||
1266 | struct ks_net *ks = netdev_priv(netdev); | ||
1267 | ks->msg_enable = to; | ||
1268 | } | ||
1269 | |||
1270 | static int ks_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) | ||
1271 | { | ||
1272 | struct ks_net *ks = netdev_priv(netdev); | ||
1273 | return mii_ethtool_gset(&ks->mii, cmd); | ||
1274 | } | ||
1275 | |||
1276 | static int ks_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd) | ||
1277 | { | ||
1278 | struct ks_net *ks = netdev_priv(netdev); | ||
1279 | return mii_ethtool_sset(&ks->mii, cmd); | ||
1280 | } | ||
1281 | |||
1282 | static u32 ks_get_link(struct net_device *netdev) | ||
1283 | { | ||
1284 | struct ks_net *ks = netdev_priv(netdev); | ||
1285 | return mii_link_ok(&ks->mii); | ||
1286 | } | ||
1287 | |||
1288 | static int ks_nway_reset(struct net_device *netdev) | ||
1289 | { | ||
1290 | struct ks_net *ks = netdev_priv(netdev); | ||
1291 | return mii_nway_restart(&ks->mii); | ||
1292 | } | ||
1293 | |||
1294 | static const struct ethtool_ops ks_ethtool_ops = { | ||
1295 | .get_drvinfo = ks_get_drvinfo, | ||
1296 | .get_msglevel = ks_get_msglevel, | ||
1297 | .set_msglevel = ks_set_msglevel, | ||
1298 | .get_settings = ks_get_settings, | ||
1299 | .set_settings = ks_set_settings, | ||
1300 | .get_link = ks_get_link, | ||
1301 | .nway_reset = ks_nway_reset, | ||
1302 | }; | ||
1303 | |||
1304 | /* MII interface controls */ | ||
1305 | |||
1306 | /** | ||
1307 | * ks_phy_reg - convert MII register into a KS8851 register | ||
1308 | * @reg: MII register number. | ||
1309 | * | ||
1310 | * Return the KS8851 register number for the corresponding MII PHY register | ||
1311 | * if possible. Return zero if the MII register has no direct mapping to the | ||
1312 | * KS8851 register set. | ||
1313 | */ | ||
1314 | static int ks_phy_reg(int reg) | ||
1315 | { | ||
1316 | switch (reg) { | ||
1317 | case MII_BMCR: | ||
1318 | return KS_P1MBCR; | ||
1319 | case MII_BMSR: | ||
1320 | return KS_P1MBSR; | ||
1321 | case MII_PHYSID1: | ||
1322 | return KS_PHY1ILR; | ||
1323 | case MII_PHYSID2: | ||
1324 | return KS_PHY1IHR; | ||
1325 | case MII_ADVERTISE: | ||
1326 | return KS_P1ANAR; | ||
1327 | case MII_LPA: | ||
1328 | return KS_P1ANLPR; | ||
1329 | } | ||
1330 | |||
1331 | return 0x0; | ||
1332 | } | ||
1333 | |||
1334 | /** | ||
1335 | * ks_phy_read - MII interface PHY register read. | ||
1336 | * @netdev: The network device the PHY is on. | ||
1337 | * @phy_addr: Address of PHY (ignored as we only have one) | ||
1338 | * @reg: The register to read. | ||
1339 | * | ||
1340 | * This call reads data from the PHY register specified in @reg. Since the | ||
1341 | * device does not support all the MII registers, the non-existant values | ||
1342 | * are always returned as zero. | ||
1343 | * | ||
1344 | * We return zero for unsupported registers as the MII code does not check | ||
1345 | * the value returned for any error status, and simply returns it to the | ||
1346 | * caller. The mii-tool that the driver was tested with takes any -ve error | ||
1347 | * as real PHY capabilities, thus displaying incorrect data to the user. | ||
1348 | */ | ||
1349 | static int ks_phy_read(struct net_device *netdev, int phy_addr, int reg) | ||
1350 | { | ||
1351 | struct ks_net *ks = netdev_priv(netdev); | ||
1352 | int ksreg; | ||
1353 | int result; | ||
1354 | |||
1355 | ksreg = ks_phy_reg(reg); | ||
1356 | if (!ksreg) | ||
1357 | return 0x0; /* no error return allowed, so use zero */ | ||
1358 | |||
1359 | mutex_lock(&ks->lock); | ||
1360 | result = ks_rdreg16(ks, ksreg); | ||
1361 | mutex_unlock(&ks->lock); | ||
1362 | |||
1363 | return result; | ||
1364 | } | ||
1365 | |||
1366 | static void ks_phy_write(struct net_device *netdev, | ||
1367 | int phy, int reg, int value) | ||
1368 | { | ||
1369 | struct ks_net *ks = netdev_priv(netdev); | ||
1370 | int ksreg; | ||
1371 | |||
1372 | ksreg = ks_phy_reg(reg); | ||
1373 | if (ksreg) { | ||
1374 | mutex_lock(&ks->lock); | ||
1375 | ks_wrreg16(ks, ksreg, value); | ||
1376 | mutex_unlock(&ks->lock); | ||
1377 | } | ||
1378 | } | ||
1379 | |||
1380 | /** | ||
1381 | * ks_read_selftest - read the selftest memory info. | ||
1382 | * @ks: The device state | ||
1383 | * | ||
1384 | * Read and check the TX/RX memory selftest information. | ||
1385 | */ | ||
1386 | static int ks_read_selftest(struct ks_net *ks) | ||
1387 | { | ||
1388 | unsigned both_done = MBIR_TXMBF | MBIR_RXMBF; | ||
1389 | int ret = 0; | ||
1390 | unsigned rd; | ||
1391 | |||
1392 | rd = ks_rdreg16(ks, KS_MBIR); | ||
1393 | |||
1394 | if ((rd & both_done) != both_done) { | ||
1395 | ks_warn(ks, "Memory selftest not finished\n"); | ||
1396 | return 0; | ||
1397 | } | ||
1398 | |||
1399 | if (rd & MBIR_TXMBFA) { | ||
1400 | ks_err(ks, "TX memory selftest fails\n"); | ||
1401 | ret |= 1; | ||
1402 | } | ||
1403 | |||
1404 | if (rd & MBIR_RXMBFA) { | ||
1405 | ks_err(ks, "RX memory selftest fails\n"); | ||
1406 | ret |= 2; | ||
1407 | } | ||
1408 | |||
1409 | ks_info(ks, "the selftest passes\n"); | ||
1410 | return ret; | ||
1411 | } | ||
1412 | |||
1413 | static void ks_disable(struct ks_net *ks) | ||
1414 | { | ||
1415 | u16 w; | ||
1416 | |||
1417 | w = ks_rdreg16(ks, KS_TXCR); | ||
1418 | |||
1419 | /* Disables QMU Transmit (TXCR). */ | ||
1420 | w &= ~TXCR_TXE; | ||
1421 | ks_wrreg16(ks, KS_TXCR, w); | ||
1422 | |||
1423 | /* Disables QMU Receive (RXCR1). */ | ||
1424 | w = ks_rdreg16(ks, KS_RXCR1); | ||
1425 | w &= ~RXCR1_RXE ; | ||
1426 | ks_wrreg16(ks, KS_RXCR1, w); | ||
1427 | |||
1428 | ks->enabled = false; | ||
1429 | |||
1430 | } /* ks_disable */ | ||
1431 | |||
1432 | static void ks_setup(struct ks_net *ks) | ||
1433 | { | ||
1434 | u16 w; | ||
1435 | |||
1436 | /** | ||
1437 | * Configure QMU Transmit | ||
1438 | */ | ||
1439 | |||
1440 | /* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */ | ||
1441 | ks_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI); | ||
1442 | |||
1443 | /* Setup Receive Frame Data Pointer Auto-Increment */ | ||
1444 | ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI); | ||
1445 | |||
1446 | /* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */ | ||
1447 | ks_wrreg16(ks, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK); | ||
1448 | |||
1449 | /* Setup RxQ Command Control (RXQCR) */ | ||
1450 | ks->rc_rxqcr = RXQCR_CMD_CNTL; | ||
1451 | ks_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr); | ||
1452 | |||
1453 | /** | ||
1454 | * set the force mode to half duplex, default is full duplex | ||
1455 | * because if the auto-negotiation fails, most switch uses | ||
1456 | * half-duplex. | ||
1457 | */ | ||
1458 | |||
1459 | w = ks_rdreg16(ks, KS_P1MBCR); | ||
1460 | w &= ~P1MBCR_FORCE_FDX; | ||
1461 | ks_wrreg16(ks, KS_P1MBCR, w); | ||
1462 | |||
1463 | w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP; | ||
1464 | ks_wrreg16(ks, KS_TXCR, w); | ||
1465 | |||
1466 | w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE; | ||
1467 | |||
1468 | if (ks->promiscuous) /* bPromiscuous */ | ||
1469 | w |= (RXCR1_RXAE | RXCR1_RXINVF); | ||
1470 | else if (ks->all_mcast) /* Multicast address passed mode */ | ||
1471 | w |= (RXCR1_RXAE | RXCR1_RXMAFMA | RXCR1_RXPAFMA); | ||
1472 | else /* Normal mode */ | ||
1473 | w |= RXCR1_RXPAFMA; | ||
1474 | |||
1475 | ks_wrreg16(ks, KS_RXCR1, w); | ||
1476 | } /*ks_setup */ | ||
1477 | |||
1478 | |||
1479 | static void ks_setup_int(struct ks_net *ks) | ||
1480 | { | ||
1481 | ks->rc_ier = 0x00; | ||
1482 | /* Clear the interrupts status of the hardware. */ | ||
1483 | ks_wrreg16(ks, KS_ISR, 0xffff); | ||
1484 | |||
1485 | /* Enables the interrupts of the hardware. */ | ||
1486 | ks->rc_ier = (IRQ_LCI | IRQ_TXI | IRQ_RXI); | ||
1487 | } /* ks_setup_int */ | ||
1488 | |||
1489 | void ks_enable(struct ks_net *ks) | ||
1490 | { | ||
1491 | u16 w; | ||
1492 | |||
1493 | w = ks_rdreg16(ks, KS_TXCR); | ||
1494 | /* Enables QMU Transmit (TXCR). */ | ||
1495 | ks_wrreg16(ks, KS_TXCR, w | TXCR_TXE); | ||
1496 | |||
1497 | /* | ||
1498 | * RX Frame Count Threshold Enable and Auto-Dequeue RXQ Frame | ||
1499 | * Enable | ||
1500 | */ | ||
1501 | |||
1502 | w = ks_rdreg16(ks, KS_RXQCR); | ||
1503 | ks_wrreg16(ks, KS_RXQCR, w | RXQCR_RXFCTE); | ||
1504 | |||
1505 | /* Enables QMU Receive (RXCR1). */ | ||
1506 | w = ks_rdreg16(ks, KS_RXCR1); | ||
1507 | ks_wrreg16(ks, KS_RXCR1, w | RXCR1_RXE); | ||
1508 | ks->enabled = true; | ||
1509 | } /* ks_enable */ | ||
1510 | |||
1511 | static int ks_hw_init(struct ks_net *ks) | ||
1512 | { | ||
1513 | #define MHEADER_SIZE (sizeof(struct type_frame_head) * MAX_RECV_FRAMES) | ||
1514 | ks->promiscuous = 0; | ||
1515 | ks->all_mcast = 0; | ||
1516 | ks->mcast_lst_size = 0; | ||
1517 | |||
1518 | ks->frame_head_info = (struct type_frame_head *) \ | ||
1519 | kmalloc(MHEADER_SIZE, GFP_KERNEL); | ||
1520 | if (!ks->frame_head_info) { | ||
1521 | printk(KERN_ERR "Error: Fail to allocate frame memory\n"); | ||
1522 | return false; | ||
1523 | } | ||
1524 | |||
1525 | ks_set_mac(ks, KS_DEFAULT_MAC_ADDRESS); | ||
1526 | return true; | ||
1527 | } | ||
1528 | |||
1529 | |||
1530 | static int __devinit ks8851_probe(struct platform_device *pdev) | ||
1531 | { | ||
1532 | int err = -ENOMEM; | ||
1533 | struct resource *io_d, *io_c; | ||
1534 | struct net_device *netdev; | ||
1535 | struct ks_net *ks; | ||
1536 | u16 id, data; | ||
1537 | |||
1538 | io_d = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
1539 | io_c = platform_get_resource(pdev, IORESOURCE_MEM, 1); | ||
1540 | |||
1541 | if (!request_mem_region(io_d->start, resource_size(io_d), DRV_NAME)) | ||
1542 | goto err_mem_region; | ||
1543 | |||
1544 | if (!request_mem_region(io_c->start, resource_size(io_c), DRV_NAME)) | ||
1545 | goto err_mem_region1; | ||
1546 | |||
1547 | netdev = alloc_etherdev(sizeof(struct ks_net)); | ||
1548 | if (!netdev) | ||
1549 | goto err_alloc_etherdev; | ||
1550 | |||
1551 | SET_NETDEV_DEV(netdev, &pdev->dev); | ||
1552 | |||
1553 | ks = netdev_priv(netdev); | ||
1554 | ks->netdev = netdev; | ||
1555 | ks->hw_addr = ioremap(io_d->start, resource_size(io_d)); | ||
1556 | |||
1557 | if (!ks->hw_addr) | ||
1558 | goto err_ioremap; | ||
1559 | |||
1560 | ks->hw_addr_cmd = ioremap(io_c->start, resource_size(io_c)); | ||
1561 | if (!ks->hw_addr_cmd) | ||
1562 | goto err_ioremap1; | ||
1563 | |||
1564 | ks->irq = platform_get_irq(pdev, 0); | ||
1565 | |||
1566 | if (ks->irq < 0) { | ||
1567 | err = ks->irq; | ||
1568 | goto err_get_irq; | ||
1569 | } | ||
1570 | |||
1571 | ks->pdev = pdev; | ||
1572 | |||
1573 | mutex_init(&ks->lock); | ||
1574 | spin_lock_init(&ks->statelock); | ||
1575 | |||
1576 | netdev->netdev_ops = &ks_netdev_ops; | ||
1577 | netdev->ethtool_ops = &ks_ethtool_ops; | ||
1578 | |||
1579 | /* setup mii state */ | ||
1580 | ks->mii.dev = netdev; | ||
1581 | ks->mii.phy_id = 1, | ||
1582 | ks->mii.phy_id_mask = 1; | ||
1583 | ks->mii.reg_num_mask = 0xf; | ||
1584 | ks->mii.mdio_read = ks_phy_read; | ||
1585 | ks->mii.mdio_write = ks_phy_write; | ||
1586 | |||
1587 | ks_info(ks, "message enable is %d\n", msg_enable); | ||
1588 | /* set the default message enable */ | ||
1589 | ks->msg_enable = netif_msg_init(msg_enable, (NETIF_MSG_DRV | | ||
1590 | NETIF_MSG_PROBE | | ||
1591 | NETIF_MSG_LINK)); | ||
1592 | ks_read_config(ks); | ||
1593 | |||
1594 | /* simple check for a valid chip being connected to the bus */ | ||
1595 | if ((ks_rdreg16(ks, KS_CIDER) & ~CIDER_REV_MASK) != CIDER_ID) { | ||
1596 | ks_err(ks, "failed to read device ID\n"); | ||
1597 | err = -ENODEV; | ||
1598 | goto err_register; | ||
1599 | } | ||
1600 | |||
1601 | if (ks_read_selftest(ks)) { | ||
1602 | ks_err(ks, "failed to read device ID\n"); | ||
1603 | err = -ENODEV; | ||
1604 | goto err_register; | ||
1605 | } | ||
1606 | |||
1607 | err = register_netdev(netdev); | ||
1608 | if (err) | ||
1609 | goto err_register; | ||
1610 | |||
1611 | platform_set_drvdata(pdev, netdev); | ||
1612 | |||
1613 | ks_soft_reset(ks, GRR_GSR); | ||
1614 | ks_hw_init(ks); | ||
1615 | ks_disable(ks); | ||
1616 | ks_setup(ks); | ||
1617 | ks_setup_int(ks); | ||
1618 | ks_enable_int(ks); | ||
1619 | ks_enable(ks); | ||
1620 | memcpy(netdev->dev_addr, ks->mac_addr, 6); | ||
1621 | |||
1622 | data = ks_rdreg16(ks, KS_OBCR); | ||
1623 | ks_wrreg16(ks, KS_OBCR, data | OBCR_ODS_16MA); | ||
1624 | |||
1625 | /** | ||
1626 | * If you want to use the default MAC addr, | ||
1627 | * comment out the 2 functions below. | ||
1628 | */ | ||
1629 | |||
1630 | random_ether_addr(netdev->dev_addr); | ||
1631 | ks_set_mac(ks, netdev->dev_addr); | ||
1632 | |||
1633 | id = ks_rdreg16(ks, KS_CIDER); | ||
1634 | |||
1635 | printk(KERN_INFO DRV_NAME | ||
1636 | " Found chip, family: 0x%x, id: 0x%x, rev: 0x%x\n", | ||
1637 | (id >> 8) & 0xff, (id >> 4) & 0xf, (id >> 1) & 0x7); | ||
1638 | return 0; | ||
1639 | |||
1640 | err_register: | ||
1641 | err_get_irq: | ||
1642 | iounmap(ks->hw_addr_cmd); | ||
1643 | err_ioremap1: | ||
1644 | iounmap(ks->hw_addr); | ||
1645 | err_ioremap: | ||
1646 | free_netdev(netdev); | ||
1647 | err_alloc_etherdev: | ||
1648 | release_mem_region(io_c->start, resource_size(io_c)); | ||
1649 | err_mem_region1: | ||
1650 | release_mem_region(io_d->start, resource_size(io_d)); | ||
1651 | err_mem_region: | ||
1652 | return err; | ||
1653 | } | ||
1654 | |||
1655 | static int __devexit ks8851_remove(struct platform_device *pdev) | ||
1656 | { | ||
1657 | struct net_device *netdev = platform_get_drvdata(pdev); | ||
1658 | struct ks_net *ks = netdev_priv(netdev); | ||
1659 | struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
1660 | |||
1661 | unregister_netdev(netdev); | ||
1662 | iounmap(ks->hw_addr); | ||
1663 | free_netdev(netdev); | ||
1664 | release_mem_region(iomem->start, resource_size(iomem)); | ||
1665 | platform_set_drvdata(pdev, NULL); | ||
1666 | return 0; | ||
1667 | |||
1668 | } | ||
1669 | |||
1670 | static struct platform_driver ks8851_platform_driver = { | ||
1671 | .driver = { | ||
1672 | .name = DRV_NAME, | ||
1673 | .owner = THIS_MODULE, | ||
1674 | }, | ||
1675 | .probe = ks8851_probe, | ||
1676 | .remove = __devexit_p(ks8851_remove), | ||
1677 | }; | ||
1678 | |||
1679 | static int __init ks8851_init(void) | ||
1680 | { | ||
1681 | return platform_driver_register(&ks8851_platform_driver); | ||
1682 | } | ||
1683 | |||
1684 | static void __exit ks8851_exit(void) | ||
1685 | { | ||
1686 | platform_driver_unregister(&ks8851_platform_driver); | ||
1687 | } | ||
1688 | |||
1689 | module_init(ks8851_init); | ||
1690 | module_exit(ks8851_exit); | ||
1691 | |||
1692 | MODULE_DESCRIPTION("KS8851 MLL Network driver"); | ||
1693 | MODULE_AUTHOR("David Choi <david.choi@micrel.com>"); | ||
1694 | MODULE_LICENSE("GPL"); | ||
1695 | module_param_named(message, msg_enable, int, 0); | ||
1696 | MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)"); | ||
1697 | |||
diff --git a/drivers/net/meth.c b/drivers/net/meth.c index 92ceb689b4d4..2af81735386b 100644 --- a/drivers/net/meth.c +++ b/drivers/net/meth.c | |||
@@ -828,7 +828,7 @@ static int __exit meth_remove(struct platform_device *pdev) | |||
828 | 828 | ||
829 | static struct platform_driver meth_driver = { | 829 | static struct platform_driver meth_driver = { |
830 | .probe = meth_probe, | 830 | .probe = meth_probe, |
831 | .remove = __devexit_p(meth_remove), | 831 | .remove = __exit_p(meth_remove), |
832 | .driver = { | 832 | .driver = { |
833 | .name = "meth", | 833 | .name = "meth", |
834 | .owner = THIS_MODULE, | 834 | .owner = THIS_MODULE, |
diff --git a/drivers/net/pppol2tp.c b/drivers/net/pppol2tp.c index cc394d073755..5910df60c93e 100644 --- a/drivers/net/pppol2tp.c +++ b/drivers/net/pppol2tp.c | |||
@@ -2179,7 +2179,7 @@ static int pppol2tp_session_setsockopt(struct sock *sk, | |||
2179 | * session or the special tunnel type. | 2179 | * session or the special tunnel type. |
2180 | */ | 2180 | */ |
2181 | static int pppol2tp_setsockopt(struct socket *sock, int level, int optname, | 2181 | static int pppol2tp_setsockopt(struct socket *sock, int level, int optname, |
2182 | char __user *optval, int optlen) | 2182 | char __user *optval, unsigned int optlen) |
2183 | { | 2183 | { |
2184 | struct sock *sk = sock->sk; | 2184 | struct sock *sk = sock->sk; |
2185 | struct pppol2tp_session *session = sk->sk_user_data; | 2185 | struct pppol2tp_session *session = sk->sk_user_data; |
diff --git a/drivers/net/qlge/qlge.h b/drivers/net/qlge/qlge.h index a9845a2f243f..30d5585beeee 100644 --- a/drivers/net/qlge/qlge.h +++ b/drivers/net/qlge/qlge.h | |||
@@ -1381,15 +1381,15 @@ struct intr_context { | |||
1381 | 1381 | ||
1382 | /* adapter flags definitions. */ | 1382 | /* adapter flags definitions. */ |
1383 | enum { | 1383 | enum { |
1384 | QL_ADAPTER_UP = (1 << 0), /* Adapter has been brought up. */ | 1384 | QL_ADAPTER_UP = 0, /* Adapter has been brought up. */ |
1385 | QL_LEGACY_ENABLED = (1 << 3), | 1385 | QL_LEGACY_ENABLED = 1, |
1386 | QL_MSI_ENABLED = (1 << 3), | 1386 | QL_MSI_ENABLED = 2, |
1387 | QL_MSIX_ENABLED = (1 << 4), | 1387 | QL_MSIX_ENABLED = 3, |
1388 | QL_DMA64 = (1 << 5), | 1388 | QL_DMA64 = 4, |
1389 | QL_PROMISCUOUS = (1 << 6), | 1389 | QL_PROMISCUOUS = 5, |
1390 | QL_ALLMULTI = (1 << 7), | 1390 | QL_ALLMULTI = 6, |
1391 | QL_PORT_CFG = (1 << 8), | 1391 | QL_PORT_CFG = 7, |
1392 | QL_CAM_RT_SET = (1 << 9), | 1392 | QL_CAM_RT_SET = 8, |
1393 | }; | 1393 | }; |
1394 | 1394 | ||
1395 | /* link_status bit definitions */ | 1395 | /* link_status bit definitions */ |
diff --git a/drivers/net/qlge/qlge_main.c b/drivers/net/qlge/qlge_main.c index 7783c5db81dc..3d0efea32111 100644 --- a/drivers/net/qlge/qlge_main.c +++ b/drivers/net/qlge/qlge_main.c | |||
@@ -3142,14 +3142,14 @@ static int ql_route_initialize(struct ql_adapter *qdev) | |||
3142 | { | 3142 | { |
3143 | int status = 0; | 3143 | int status = 0; |
3144 | 3144 | ||
3145 | status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK); | 3145 | /* Clear all the entries in the routing table. */ |
3146 | status = ql_clear_routing_entries(qdev); | ||
3146 | if (status) | 3147 | if (status) |
3147 | return status; | 3148 | return status; |
3148 | 3149 | ||
3149 | /* Clear all the entries in the routing table. */ | 3150 | status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK); |
3150 | status = ql_clear_routing_entries(qdev); | ||
3151 | if (status) | 3151 | if (status) |
3152 | goto exit; | 3152 | return status; |
3153 | 3153 | ||
3154 | status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1); | 3154 | status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1); |
3155 | if (status) { | 3155 | if (status) { |
@@ -3380,12 +3380,10 @@ static int ql_adapter_down(struct ql_adapter *qdev) | |||
3380 | 3380 | ||
3381 | ql_free_rx_buffers(qdev); | 3381 | ql_free_rx_buffers(qdev); |
3382 | 3382 | ||
3383 | spin_lock(&qdev->hw_lock); | ||
3384 | status = ql_adapter_reset(qdev); | 3383 | status = ql_adapter_reset(qdev); |
3385 | if (status) | 3384 | if (status) |
3386 | QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n", | 3385 | QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n", |
3387 | qdev->func); | 3386 | qdev->func); |
3388 | spin_unlock(&qdev->hw_lock); | ||
3389 | return status; | 3387 | return status; |
3390 | } | 3388 | } |
3391 | 3389 | ||
@@ -3705,7 +3703,7 @@ static void ql_asic_reset_work(struct work_struct *work) | |||
3705 | struct ql_adapter *qdev = | 3703 | struct ql_adapter *qdev = |
3706 | container_of(work, struct ql_adapter, asic_reset_work.work); | 3704 | container_of(work, struct ql_adapter, asic_reset_work.work); |
3707 | int status; | 3705 | int status; |
3708 | 3706 | rtnl_lock(); | |
3709 | status = ql_adapter_down(qdev); | 3707 | status = ql_adapter_down(qdev); |
3710 | if (status) | 3708 | if (status) |
3711 | goto error; | 3709 | goto error; |
@@ -3713,12 +3711,12 @@ static void ql_asic_reset_work(struct work_struct *work) | |||
3713 | status = ql_adapter_up(qdev); | 3711 | status = ql_adapter_up(qdev); |
3714 | if (status) | 3712 | if (status) |
3715 | goto error; | 3713 | goto error; |
3716 | 3714 | rtnl_unlock(); | |
3717 | return; | 3715 | return; |
3718 | error: | 3716 | error: |
3719 | QPRINTK(qdev, IFUP, ALERT, | 3717 | QPRINTK(qdev, IFUP, ALERT, |
3720 | "Driver up/down cycle failed, closing device\n"); | 3718 | "Driver up/down cycle failed, closing device\n"); |
3721 | rtnl_lock(); | 3719 | |
3722 | set_bit(QL_ADAPTER_UP, &qdev->flags); | 3720 | set_bit(QL_ADAPTER_UP, &qdev->flags); |
3723 | dev_close(qdev->ndev); | 3721 | dev_close(qdev->ndev); |
3724 | rtnl_unlock(); | 3722 | rtnl_unlock(); |
@@ -3834,11 +3832,14 @@ static int __devinit ql_init_device(struct pci_dev *pdev, | |||
3834 | return err; | 3832 | return err; |
3835 | } | 3833 | } |
3836 | 3834 | ||
3835 | qdev->ndev = ndev; | ||
3836 | qdev->pdev = pdev; | ||
3837 | pci_set_drvdata(pdev, ndev); | ||
3837 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | 3838 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
3838 | if (pos <= 0) { | 3839 | if (pos <= 0) { |
3839 | dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, " | 3840 | dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, " |
3840 | "aborting.\n"); | 3841 | "aborting.\n"); |
3841 | goto err_out; | 3842 | return pos; |
3842 | } else { | 3843 | } else { |
3843 | pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16); | 3844 | pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16); |
3844 | val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; | 3845 | val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; |
@@ -3851,7 +3852,7 @@ static int __devinit ql_init_device(struct pci_dev *pdev, | |||
3851 | err = pci_request_regions(pdev, DRV_NAME); | 3852 | err = pci_request_regions(pdev, DRV_NAME); |
3852 | if (err) { | 3853 | if (err) { |
3853 | dev_err(&pdev->dev, "PCI region request failed.\n"); | 3854 | dev_err(&pdev->dev, "PCI region request failed.\n"); |
3854 | goto err_out; | 3855 | return err; |
3855 | } | 3856 | } |
3856 | 3857 | ||
3857 | pci_set_master(pdev); | 3858 | pci_set_master(pdev); |
@@ -3869,7 +3870,6 @@ static int __devinit ql_init_device(struct pci_dev *pdev, | |||
3869 | goto err_out; | 3870 | goto err_out; |
3870 | } | 3871 | } |
3871 | 3872 | ||
3872 | pci_set_drvdata(pdev, ndev); | ||
3873 | qdev->reg_base = | 3873 | qdev->reg_base = |
3874 | ioremap_nocache(pci_resource_start(pdev, 1), | 3874 | ioremap_nocache(pci_resource_start(pdev, 1), |
3875 | pci_resource_len(pdev, 1)); | 3875 | pci_resource_len(pdev, 1)); |
@@ -3889,8 +3889,6 @@ static int __devinit ql_init_device(struct pci_dev *pdev, | |||
3889 | goto err_out; | 3889 | goto err_out; |
3890 | } | 3890 | } |
3891 | 3891 | ||
3892 | qdev->ndev = ndev; | ||
3893 | qdev->pdev = pdev; | ||
3894 | err = ql_get_board_info(qdev); | 3892 | err = ql_get_board_info(qdev); |
3895 | if (err) { | 3893 | if (err) { |
3896 | dev_err(&pdev->dev, "Register access failed.\n"); | 3894 | dev_err(&pdev->dev, "Register access failed.\n"); |
diff --git a/drivers/net/sgiseeq.c b/drivers/net/sgiseeq.c index ecf3279fbef5..f4dfd1f679a9 100644 --- a/drivers/net/sgiseeq.c +++ b/drivers/net/sgiseeq.c | |||
@@ -826,7 +826,7 @@ static int __exit sgiseeq_remove(struct platform_device *pdev) | |||
826 | 826 | ||
827 | static struct platform_driver sgiseeq_driver = { | 827 | static struct platform_driver sgiseeq_driver = { |
828 | .probe = sgiseeq_probe, | 828 | .probe = sgiseeq_probe, |
829 | .remove = __devexit_p(sgiseeq_remove), | 829 | .remove = __exit_p(sgiseeq_remove), |
830 | .driver = { | 830 | .driver = { |
831 | .name = "sgiseeq", | 831 | .name = "sgiseeq", |
832 | .owner = THIS_MODULE, | 832 | .owner = THIS_MODULE, |
diff --git a/drivers/net/skge.c b/drivers/net/skge.c index 55bad4081966..01f6811f1324 100644 --- a/drivers/net/skge.c +++ b/drivers/net/skge.c | |||
@@ -3935,11 +3935,14 @@ static int __devinit skge_probe(struct pci_dev *pdev, | |||
3935 | #endif | 3935 | #endif |
3936 | 3936 | ||
3937 | err = -ENOMEM; | 3937 | err = -ENOMEM; |
3938 | hw = kzalloc(sizeof(*hw), GFP_KERNEL); | 3938 | /* space for skge@pci:0000:04:00.0 */ |
3939 | hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:" ) | ||
3940 | + strlen(pci_name(pdev)) + 1, GFP_KERNEL); | ||
3939 | if (!hw) { | 3941 | if (!hw) { |
3940 | dev_err(&pdev->dev, "cannot allocate hardware struct\n"); | 3942 | dev_err(&pdev->dev, "cannot allocate hardware struct\n"); |
3941 | goto err_out_free_regions; | 3943 | goto err_out_free_regions; |
3942 | } | 3944 | } |
3945 | sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); | ||
3943 | 3946 | ||
3944 | hw->pdev = pdev; | 3947 | hw->pdev = pdev; |
3945 | spin_lock_init(&hw->hw_lock); | 3948 | spin_lock_init(&hw->hw_lock); |
@@ -3974,7 +3977,7 @@ static int __devinit skge_probe(struct pci_dev *pdev, | |||
3974 | goto err_out_free_netdev; | 3977 | goto err_out_free_netdev; |
3975 | } | 3978 | } |
3976 | 3979 | ||
3977 | err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw); | 3980 | err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, hw->irq_name, hw); |
3978 | if (err) { | 3981 | if (err) { |
3979 | dev_err(&pdev->dev, "%s: cannot assign irq %d\n", | 3982 | dev_err(&pdev->dev, "%s: cannot assign irq %d\n", |
3980 | dev->name, pdev->irq); | 3983 | dev->name, pdev->irq); |
@@ -3982,14 +3985,17 @@ static int __devinit skge_probe(struct pci_dev *pdev, | |||
3982 | } | 3985 | } |
3983 | skge_show_addr(dev); | 3986 | skge_show_addr(dev); |
3984 | 3987 | ||
3985 | if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) { | 3988 | if (hw->ports > 1) { |
3986 | if (register_netdev(dev1) == 0) | 3989 | dev1 = skge_devinit(hw, 1, using_dac); |
3990 | if (dev1 && register_netdev(dev1) == 0) | ||
3987 | skge_show_addr(dev1); | 3991 | skge_show_addr(dev1); |
3988 | else { | 3992 | else { |
3989 | /* Failure to register second port need not be fatal */ | 3993 | /* Failure to register second port need not be fatal */ |
3990 | dev_warn(&pdev->dev, "register of second port failed\n"); | 3994 | dev_warn(&pdev->dev, "register of second port failed\n"); |
3991 | hw->dev[1] = NULL; | 3995 | hw->dev[1] = NULL; |
3992 | free_netdev(dev1); | 3996 | hw->ports = 1; |
3997 | if (dev1) | ||
3998 | free_netdev(dev1); | ||
3993 | } | 3999 | } |
3994 | } | 4000 | } |
3995 | pci_set_drvdata(pdev, hw); | 4001 | pci_set_drvdata(pdev, hw); |
diff --git a/drivers/net/skge.h b/drivers/net/skge.h index 17caccbb7685..831de1b6e96e 100644 --- a/drivers/net/skge.h +++ b/drivers/net/skge.h | |||
@@ -2423,6 +2423,8 @@ struct skge_hw { | |||
2423 | u16 phy_addr; | 2423 | u16 phy_addr; |
2424 | spinlock_t phy_lock; | 2424 | spinlock_t phy_lock; |
2425 | struct tasklet_struct phy_task; | 2425 | struct tasklet_struct phy_task; |
2426 | |||
2427 | char irq_name[0]; /* skge@pci:000:04:00.0 */ | ||
2426 | }; | 2428 | }; |
2427 | 2429 | ||
2428 | enum pause_control { | 2430 | enum pause_control { |
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c index ef1165718dd7..2ab5c39f33ca 100644 --- a/drivers/net/sky2.c +++ b/drivers/net/sky2.c | |||
@@ -4487,13 +4487,16 @@ static int __devinit sky2_probe(struct pci_dev *pdev, | |||
4487 | wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0; | 4487 | wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0; |
4488 | 4488 | ||
4489 | err = -ENOMEM; | 4489 | err = -ENOMEM; |
4490 | hw = kzalloc(sizeof(*hw), GFP_KERNEL); | 4490 | |
4491 | hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") | ||
4492 | + strlen(pci_name(pdev)) + 1, GFP_KERNEL); | ||
4491 | if (!hw) { | 4493 | if (!hw) { |
4492 | dev_err(&pdev->dev, "cannot allocate hardware struct\n"); | 4494 | dev_err(&pdev->dev, "cannot allocate hardware struct\n"); |
4493 | goto err_out_free_regions; | 4495 | goto err_out_free_regions; |
4494 | } | 4496 | } |
4495 | 4497 | ||
4496 | hw->pdev = pdev; | 4498 | hw->pdev = pdev; |
4499 | sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); | ||
4497 | 4500 | ||
4498 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); | 4501 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); |
4499 | if (!hw->regs) { | 4502 | if (!hw->regs) { |
@@ -4539,7 +4542,7 @@ static int __devinit sky2_probe(struct pci_dev *pdev, | |||
4539 | 4542 | ||
4540 | err = request_irq(pdev->irq, sky2_intr, | 4543 | err = request_irq(pdev->irq, sky2_intr, |
4541 | (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED, | 4544 | (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED, |
4542 | dev->name, hw); | 4545 | hw->irq_name, hw); |
4543 | if (err) { | 4546 | if (err) { |
4544 | dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); | 4547 | dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); |
4545 | goto err_out_unregister; | 4548 | goto err_out_unregister; |
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h index e0f23a101043..ed54129698b4 100644 --- a/drivers/net/sky2.h +++ b/drivers/net/sky2.h | |||
@@ -2085,6 +2085,8 @@ struct sky2_hw { | |||
2085 | struct timer_list watchdog_timer; | 2085 | struct timer_list watchdog_timer; |
2086 | struct work_struct restart_work; | 2086 | struct work_struct restart_work; |
2087 | wait_queue_head_t msi_wait; | 2087 | wait_queue_head_t msi_wait; |
2088 | |||
2089 | char irq_name[0]; | ||
2088 | }; | 2090 | }; |
2089 | 2091 | ||
2090 | static inline int sky2_is_copper(const struct sky2_hw *hw) | 2092 | static inline int sky2_is_copper(const struct sky2_hw *hw) |
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 82b45d8797b4..524691cd9896 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -2412,7 +2412,6 @@ struct ring_info { | |||
2412 | 2412 | ||
2413 | struct tx_ring_info { | 2413 | struct tx_ring_info { |
2414 | struct sk_buff *skb; | 2414 | struct sk_buff *skb; |
2415 | u32 prev_vlan_tag; | ||
2416 | }; | 2415 | }; |
2417 | 2416 | ||
2418 | struct tg3_config_info { | 2417 | struct tg3_config_info { |
diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index d445845f2779..8d009760277c 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c | |||
@@ -948,7 +948,7 @@ free: | |||
948 | return err; | 948 | return err; |
949 | } | 949 | } |
950 | 950 | ||
951 | static void virtnet_remove(struct virtio_device *vdev) | 951 | static void __devexit virtnet_remove(struct virtio_device *vdev) |
952 | { | 952 | { |
953 | struct virtnet_info *vi = vdev->priv; | 953 | struct virtnet_info *vi = vdev->priv; |
954 | struct sk_buff *skb; | 954 | struct sk_buff *skb; |
diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig index 49ea9c92b7e6..d7a764a2fc1a 100644 --- a/drivers/net/wireless/Kconfig +++ b/drivers/net/wireless/Kconfig | |||
@@ -31,13 +31,12 @@ config STRIP | |||
31 | ---help--- | 31 | ---help--- |
32 | Say Y if you have a Metricom radio and intend to use Starmode Radio | 32 | Say Y if you have a Metricom radio and intend to use Starmode Radio |
33 | IP. STRIP is a radio protocol developed for the MosquitoNet project | 33 | IP. STRIP is a radio protocol developed for the MosquitoNet project |
34 | (on the WWW at <http://mosquitonet.stanford.edu/>) to send Internet | 34 | to send Internet traffic using Metricom radios. Metricom radios are |
35 | traffic using Metricom radios. Metricom radios are small, battery | 35 | small, battery powered, 100kbit/sec packet radio transceivers, about |
36 | powered, 100kbit/sec packet radio transceivers, about the size and | 36 | the size and weight of a cellular telephone. (You may also have heard |
37 | weight of a cellular telephone. (You may also have heard them called | 37 | them called "Metricom modems" but we avoid the term "modem" because |
38 | "Metricom modems" but we avoid the term "modem" because it misleads | 38 | it misleads many people into thinking that you can plug a Metricom |
39 | many people into thinking that you can plug a Metricom modem into a | 39 | modem into a phone line and use it as a modem.) |
40 | phone line and use it as a modem.) | ||
41 | 40 | ||
42 | You can use STRIP on any Linux machine with a serial port, although | 41 | You can use STRIP on any Linux machine with a serial port, although |
43 | it is obviously most useful for people with laptop computers. If you | 42 | it is obviously most useful for people with laptop computers. If you |
diff --git a/drivers/net/wireless/ath/ar9170/phy.c b/drivers/net/wireless/ath/ar9170/phy.c index b3e5cf3735b0..dbd488da18b1 100644 --- a/drivers/net/wireless/ath/ar9170/phy.c +++ b/drivers/net/wireless/ath/ar9170/phy.c | |||
@@ -1141,7 +1141,8 @@ static int ar9170_set_freq_cal_data(struct ar9170 *ar, | |||
1141 | u8 vpds[2][AR5416_PD_GAIN_ICEPTS]; | 1141 | u8 vpds[2][AR5416_PD_GAIN_ICEPTS]; |
1142 | u8 pwrs[2][AR5416_PD_GAIN_ICEPTS]; | 1142 | u8 pwrs[2][AR5416_PD_GAIN_ICEPTS]; |
1143 | int chain, idx, i; | 1143 | int chain, idx, i; |
1144 | u8 f; | 1144 | u32 phy_data = 0; |
1145 | u8 f, tmp; | ||
1145 | 1146 | ||
1146 | switch (channel->band) { | 1147 | switch (channel->band) { |
1147 | case IEEE80211_BAND_2GHZ: | 1148 | case IEEE80211_BAND_2GHZ: |
@@ -1208,9 +1209,6 @@ static int ar9170_set_freq_cal_data(struct ar9170 *ar, | |||
1208 | } | 1209 | } |
1209 | 1210 | ||
1210 | for (i = 0; i < 76; i++) { | 1211 | for (i = 0; i < 76; i++) { |
1211 | u32 phy_data; | ||
1212 | u8 tmp; | ||
1213 | |||
1214 | if (i < 25) { | 1212 | if (i < 25) { |
1215 | tmp = ar9170_interpolate_val(i, &pwrs[0][0], | 1213 | tmp = ar9170_interpolate_val(i, &pwrs[0][0], |
1216 | &vpds[0][0]); | 1214 | &vpds[0][0]); |
diff --git a/drivers/net/wireless/b43/pio.c b/drivers/net/wireless/b43/pio.c index e96091b31499..9c1397996e0a 100644 --- a/drivers/net/wireless/b43/pio.c +++ b/drivers/net/wireless/b43/pio.c | |||
@@ -340,10 +340,15 @@ static u16 tx_write_2byte_queue(struct b43_pio_txqueue *q, | |||
340 | q->mmio_base + B43_PIO_TXDATA, | 340 | q->mmio_base + B43_PIO_TXDATA, |
341 | sizeof(u16)); | 341 | sizeof(u16)); |
342 | if (data_len & 1) { | 342 | if (data_len & 1) { |
343 | u8 tail[2] = { 0, }; | ||
344 | |||
343 | /* Write the last byte. */ | 345 | /* Write the last byte. */ |
344 | ctl &= ~B43_PIO_TXCTL_WRITEHI; | 346 | ctl &= ~B43_PIO_TXCTL_WRITEHI; |
345 | b43_piotx_write16(q, B43_PIO_TXCTL, ctl); | 347 | b43_piotx_write16(q, B43_PIO_TXCTL, ctl); |
346 | b43_piotx_write16(q, B43_PIO_TXDATA, data[data_len - 1]); | 348 | tail[0] = data[data_len - 1]; |
349 | ssb_block_write(dev->dev, tail, 2, | ||
350 | q->mmio_base + B43_PIO_TXDATA, | ||
351 | sizeof(u16)); | ||
347 | } | 352 | } |
348 | 353 | ||
349 | return ctl; | 354 | return ctl; |
@@ -386,26 +391,31 @@ static u32 tx_write_4byte_queue(struct b43_pio_txqueue *q, | |||
386 | q->mmio_base + B43_PIO8_TXDATA, | 391 | q->mmio_base + B43_PIO8_TXDATA, |
387 | sizeof(u32)); | 392 | sizeof(u32)); |
388 | if (data_len & 3) { | 393 | if (data_len & 3) { |
389 | u32 value = 0; | 394 | u8 tail[4] = { 0, }; |
390 | 395 | ||
391 | /* Write the last few bytes. */ | 396 | /* Write the last few bytes. */ |
392 | ctl &= ~(B43_PIO8_TXCTL_8_15 | B43_PIO8_TXCTL_16_23 | | 397 | ctl &= ~(B43_PIO8_TXCTL_8_15 | B43_PIO8_TXCTL_16_23 | |
393 | B43_PIO8_TXCTL_24_31); | 398 | B43_PIO8_TXCTL_24_31); |
394 | data = &(data[data_len - 1]); | ||
395 | switch (data_len & 3) { | 399 | switch (data_len & 3) { |
396 | case 3: | 400 | case 3: |
397 | ctl |= B43_PIO8_TXCTL_16_23; | 401 | ctl |= B43_PIO8_TXCTL_16_23 | B43_PIO8_TXCTL_8_15; |
398 | value |= (u32)(*data) << 16; | 402 | tail[0] = data[data_len - 3]; |
399 | data--; | 403 | tail[1] = data[data_len - 2]; |
404 | tail[2] = data[data_len - 1]; | ||
405 | break; | ||
400 | case 2: | 406 | case 2: |
401 | ctl |= B43_PIO8_TXCTL_8_15; | 407 | ctl |= B43_PIO8_TXCTL_8_15; |
402 | value |= (u32)(*data) << 8; | 408 | tail[0] = data[data_len - 2]; |
403 | data--; | 409 | tail[1] = data[data_len - 1]; |
410 | break; | ||
404 | case 1: | 411 | case 1: |
405 | value |= (u32)(*data); | 412 | tail[0] = data[data_len - 1]; |
413 | break; | ||
406 | } | 414 | } |
407 | b43_piotx_write32(q, B43_PIO8_TXCTL, ctl); | 415 | b43_piotx_write32(q, B43_PIO8_TXCTL, ctl); |
408 | b43_piotx_write32(q, B43_PIO8_TXDATA, value); | 416 | ssb_block_write(dev->dev, tail, 4, |
417 | q->mmio_base + B43_PIO8_TXDATA, | ||
418 | sizeof(u32)); | ||
409 | } | 419 | } |
410 | 420 | ||
411 | return ctl; | 421 | return ctl; |
@@ -693,21 +703,25 @@ data_ready: | |||
693 | q->mmio_base + B43_PIO8_RXDATA, | 703 | q->mmio_base + B43_PIO8_RXDATA, |
694 | sizeof(u32)); | 704 | sizeof(u32)); |
695 | if (len & 3) { | 705 | if (len & 3) { |
696 | u32 value; | 706 | u8 tail[4] = { 0, }; |
697 | char *data; | ||
698 | 707 | ||
699 | /* Read the last few bytes. */ | 708 | /* Read the last few bytes. */ |
700 | value = b43_piorx_read32(q, B43_PIO8_RXDATA); | 709 | ssb_block_read(dev->dev, tail, 4, |
701 | data = &(skb->data[len + padding - 1]); | 710 | q->mmio_base + B43_PIO8_RXDATA, |
711 | sizeof(u32)); | ||
702 | switch (len & 3) { | 712 | switch (len & 3) { |
703 | case 3: | 713 | case 3: |
704 | *data = (value >> 16); | 714 | skb->data[len + padding - 3] = tail[0]; |
705 | data--; | 715 | skb->data[len + padding - 2] = tail[1]; |
716 | skb->data[len + padding - 1] = tail[2]; | ||
717 | break; | ||
706 | case 2: | 718 | case 2: |
707 | *data = (value >> 8); | 719 | skb->data[len + padding - 2] = tail[0]; |
708 | data--; | 720 | skb->data[len + padding - 1] = tail[1]; |
721 | break; | ||
709 | case 1: | 722 | case 1: |
710 | *data = value; | 723 | skb->data[len + padding - 1] = tail[0]; |
724 | break; | ||
711 | } | 725 | } |
712 | } | 726 | } |
713 | } else { | 727 | } else { |
@@ -715,11 +729,13 @@ data_ready: | |||
715 | q->mmio_base + B43_PIO_RXDATA, | 729 | q->mmio_base + B43_PIO_RXDATA, |
716 | sizeof(u16)); | 730 | sizeof(u16)); |
717 | if (len & 1) { | 731 | if (len & 1) { |
718 | u16 value; | 732 | u8 tail[2] = { 0, }; |
719 | 733 | ||
720 | /* Read the last byte. */ | 734 | /* Read the last byte. */ |
721 | value = b43_piorx_read16(q, B43_PIO_RXDATA); | 735 | ssb_block_read(dev->dev, tail, 2, |
722 | skb->data[len + padding - 1] = value; | 736 | q->mmio_base + B43_PIO_RXDATA, |
737 | sizeof(u16)); | ||
738 | skb->data[len + padding - 1] = tail[0]; | ||
723 | } | 739 | } |
724 | } | 740 | } |
725 | 741 | ||
diff --git a/drivers/net/wireless/iwlwifi/iwl-1000.c b/drivers/net/wireless/iwlwifi/iwl-1000.c index a95caa014143..2716b91ba9fa 100644 --- a/drivers/net/wireless/iwlwifi/iwl-1000.c +++ b/drivers/net/wireless/iwlwifi/iwl-1000.c | |||
@@ -99,6 +99,8 @@ static struct iwl_lib_ops iwl1000_lib = { | |||
99 | .setup_deferred_work = iwl5000_setup_deferred_work, | 99 | .setup_deferred_work = iwl5000_setup_deferred_work, |
100 | .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, | 100 | .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, |
101 | .load_ucode = iwl5000_load_ucode, | 101 | .load_ucode = iwl5000_load_ucode, |
102 | .dump_nic_event_log = iwl_dump_nic_event_log, | ||
103 | .dump_nic_error_log = iwl_dump_nic_error_log, | ||
102 | .init_alive_start = iwl5000_init_alive_start, | 104 | .init_alive_start = iwl5000_init_alive_start, |
103 | .alive_notify = iwl5000_alive_notify, | 105 | .alive_notify = iwl5000_alive_notify, |
104 | .send_tx_power = iwl5000_send_tx_power, | 106 | .send_tx_power = iwl5000_send_tx_power, |
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c index e9a685d8e3a1..e70c5b0af364 100644 --- a/drivers/net/wireless/iwlwifi/iwl-3945.c +++ b/drivers/net/wireless/iwlwifi/iwl-3945.c | |||
@@ -2839,6 +2839,8 @@ static struct iwl_lib_ops iwl3945_lib = { | |||
2839 | .txq_free_tfd = iwl3945_hw_txq_free_tfd, | 2839 | .txq_free_tfd = iwl3945_hw_txq_free_tfd, |
2840 | .txq_init = iwl3945_hw_tx_queue_init, | 2840 | .txq_init = iwl3945_hw_tx_queue_init, |
2841 | .load_ucode = iwl3945_load_bsm, | 2841 | .load_ucode = iwl3945_load_bsm, |
2842 | .dump_nic_event_log = iwl3945_dump_nic_event_log, | ||
2843 | .dump_nic_error_log = iwl3945_dump_nic_error_log, | ||
2842 | .apm_ops = { | 2844 | .apm_ops = { |
2843 | .init = iwl3945_apm_init, | 2845 | .init = iwl3945_apm_init, |
2844 | .reset = iwl3945_apm_reset, | 2846 | .reset = iwl3945_apm_reset, |
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.h b/drivers/net/wireless/iwlwifi/iwl-3945.h index f24036909916..21679bf3a1aa 100644 --- a/drivers/net/wireless/iwlwifi/iwl-3945.h +++ b/drivers/net/wireless/iwlwifi/iwl-3945.h | |||
@@ -209,6 +209,8 @@ extern int __must_check iwl3945_send_cmd(struct iwl_priv *priv, | |||
209 | struct iwl_host_cmd *cmd); | 209 | struct iwl_host_cmd *cmd); |
210 | extern unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv, | 210 | extern unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv, |
211 | struct ieee80211_hdr *hdr,int left); | 211 | struct ieee80211_hdr *hdr,int left); |
212 | extern void iwl3945_dump_nic_event_log(struct iwl_priv *priv); | ||
213 | extern void iwl3945_dump_nic_error_log(struct iwl_priv *priv); | ||
212 | 214 | ||
213 | /* | 215 | /* |
214 | * Currently used by iwl-3945-rs... look at restructuring so that it doesn't | 216 | * Currently used by iwl-3945-rs... look at restructuring so that it doesn't |
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.c b/drivers/net/wireless/iwlwifi/iwl-4965.c index 3259b8841544..a22a0501c190 100644 --- a/drivers/net/wireless/iwlwifi/iwl-4965.c +++ b/drivers/net/wireless/iwlwifi/iwl-4965.c | |||
@@ -2298,6 +2298,8 @@ static struct iwl_lib_ops iwl4965_lib = { | |||
2298 | .alive_notify = iwl4965_alive_notify, | 2298 | .alive_notify = iwl4965_alive_notify, |
2299 | .init_alive_start = iwl4965_init_alive_start, | 2299 | .init_alive_start = iwl4965_init_alive_start, |
2300 | .load_ucode = iwl4965_load_bsm, | 2300 | .load_ucode = iwl4965_load_bsm, |
2301 | .dump_nic_event_log = iwl_dump_nic_event_log, | ||
2302 | .dump_nic_error_log = iwl_dump_nic_error_log, | ||
2301 | .apm_ops = { | 2303 | .apm_ops = { |
2302 | .init = iwl4965_apm_init, | 2304 | .init = iwl4965_apm_init, |
2303 | .reset = iwl4965_apm_reset, | 2305 | .reset = iwl4965_apm_reset, |
diff --git a/drivers/net/wireless/iwlwifi/iwl-5000.c b/drivers/net/wireless/iwlwifi/iwl-5000.c index a6391c7fea53..eb08f4411000 100644 --- a/drivers/net/wireless/iwlwifi/iwl-5000.c +++ b/drivers/net/wireless/iwlwifi/iwl-5000.c | |||
@@ -1535,6 +1535,8 @@ struct iwl_lib_ops iwl5000_lib = { | |||
1535 | .rx_handler_setup = iwl5000_rx_handler_setup, | 1535 | .rx_handler_setup = iwl5000_rx_handler_setup, |
1536 | .setup_deferred_work = iwl5000_setup_deferred_work, | 1536 | .setup_deferred_work = iwl5000_setup_deferred_work, |
1537 | .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, | 1537 | .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, |
1538 | .dump_nic_event_log = iwl_dump_nic_event_log, | ||
1539 | .dump_nic_error_log = iwl_dump_nic_error_log, | ||
1538 | .load_ucode = iwl5000_load_ucode, | 1540 | .load_ucode = iwl5000_load_ucode, |
1539 | .init_alive_start = iwl5000_init_alive_start, | 1541 | .init_alive_start = iwl5000_init_alive_start, |
1540 | .alive_notify = iwl5000_alive_notify, | 1542 | .alive_notify = iwl5000_alive_notify, |
@@ -1585,6 +1587,8 @@ static struct iwl_lib_ops iwl5150_lib = { | |||
1585 | .rx_handler_setup = iwl5000_rx_handler_setup, | 1587 | .rx_handler_setup = iwl5000_rx_handler_setup, |
1586 | .setup_deferred_work = iwl5000_setup_deferred_work, | 1588 | .setup_deferred_work = iwl5000_setup_deferred_work, |
1587 | .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, | 1589 | .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, |
1590 | .dump_nic_event_log = iwl_dump_nic_event_log, | ||
1591 | .dump_nic_error_log = iwl_dump_nic_error_log, | ||
1588 | .load_ucode = iwl5000_load_ucode, | 1592 | .load_ucode = iwl5000_load_ucode, |
1589 | .init_alive_start = iwl5000_init_alive_start, | 1593 | .init_alive_start = iwl5000_init_alive_start, |
1590 | .alive_notify = iwl5000_alive_notify, | 1594 | .alive_notify = iwl5000_alive_notify, |
diff --git a/drivers/net/wireless/iwlwifi/iwl-6000.c b/drivers/net/wireless/iwlwifi/iwl-6000.c index 82b9c93dff54..c295b8ee9228 100644 --- a/drivers/net/wireless/iwlwifi/iwl-6000.c +++ b/drivers/net/wireless/iwlwifi/iwl-6000.c | |||
@@ -100,6 +100,8 @@ static struct iwl_lib_ops iwl6000_lib = { | |||
100 | .setup_deferred_work = iwl5000_setup_deferred_work, | 100 | .setup_deferred_work = iwl5000_setup_deferred_work, |
101 | .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, | 101 | .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, |
102 | .load_ucode = iwl5000_load_ucode, | 102 | .load_ucode = iwl5000_load_ucode, |
103 | .dump_nic_event_log = iwl_dump_nic_event_log, | ||
104 | .dump_nic_error_log = iwl_dump_nic_error_log, | ||
103 | .init_alive_start = iwl5000_init_alive_start, | 105 | .init_alive_start = iwl5000_init_alive_start, |
104 | .alive_notify = iwl5000_alive_notify, | 106 | .alive_notify = iwl5000_alive_notify, |
105 | .send_tx_power = iwl5000_send_tx_power, | 107 | .send_tx_power = iwl5000_send_tx_power, |
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c index 00457bff1ed1..cdc07c477457 100644 --- a/drivers/net/wireless/iwlwifi/iwl-agn.c +++ b/drivers/net/wireless/iwlwifi/iwl-agn.c | |||
@@ -1526,6 +1526,191 @@ static int iwl_read_ucode(struct iwl_priv *priv) | |||
1526 | return ret; | 1526 | return ret; |
1527 | } | 1527 | } |
1528 | 1528 | ||
1529 | #ifdef CONFIG_IWLWIFI_DEBUG | ||
1530 | static const char *desc_lookup_text[] = { | ||
1531 | "OK", | ||
1532 | "FAIL", | ||
1533 | "BAD_PARAM", | ||
1534 | "BAD_CHECKSUM", | ||
1535 | "NMI_INTERRUPT_WDG", | ||
1536 | "SYSASSERT", | ||
1537 | "FATAL_ERROR", | ||
1538 | "BAD_COMMAND", | ||
1539 | "HW_ERROR_TUNE_LOCK", | ||
1540 | "HW_ERROR_TEMPERATURE", | ||
1541 | "ILLEGAL_CHAN_FREQ", | ||
1542 | "VCC_NOT_STABLE", | ||
1543 | "FH_ERROR", | ||
1544 | "NMI_INTERRUPT_HOST", | ||
1545 | "NMI_INTERRUPT_ACTION_PT", | ||
1546 | "NMI_INTERRUPT_UNKNOWN", | ||
1547 | "UCODE_VERSION_MISMATCH", | ||
1548 | "HW_ERROR_ABS_LOCK", | ||
1549 | "HW_ERROR_CAL_LOCK_FAIL", | ||
1550 | "NMI_INTERRUPT_INST_ACTION_PT", | ||
1551 | "NMI_INTERRUPT_DATA_ACTION_PT", | ||
1552 | "NMI_TRM_HW_ER", | ||
1553 | "NMI_INTERRUPT_TRM", | ||
1554 | "NMI_INTERRUPT_BREAK_POINT" | ||
1555 | "DEBUG_0", | ||
1556 | "DEBUG_1", | ||
1557 | "DEBUG_2", | ||
1558 | "DEBUG_3", | ||
1559 | "UNKNOWN" | ||
1560 | }; | ||
1561 | |||
1562 | static const char *desc_lookup(int i) | ||
1563 | { | ||
1564 | int max = ARRAY_SIZE(desc_lookup_text) - 1; | ||
1565 | |||
1566 | if (i < 0 || i > max) | ||
1567 | i = max; | ||
1568 | |||
1569 | return desc_lookup_text[i]; | ||
1570 | } | ||
1571 | |||
1572 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | ||
1573 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | ||
1574 | |||
1575 | void iwl_dump_nic_error_log(struct iwl_priv *priv) | ||
1576 | { | ||
1577 | u32 data2, line; | ||
1578 | u32 desc, time, count, base, data1; | ||
1579 | u32 blink1, blink2, ilink1, ilink2; | ||
1580 | |||
1581 | if (priv->ucode_type == UCODE_INIT) | ||
1582 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); | ||
1583 | else | ||
1584 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | ||
1585 | |||
1586 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | ||
1587 | IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base); | ||
1588 | return; | ||
1589 | } | ||
1590 | |||
1591 | count = iwl_read_targ_mem(priv, base); | ||
1592 | |||
1593 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | ||
1594 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); | ||
1595 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | ||
1596 | priv->status, count); | ||
1597 | } | ||
1598 | |||
1599 | desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32)); | ||
1600 | blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32)); | ||
1601 | blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32)); | ||
1602 | ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32)); | ||
1603 | ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32)); | ||
1604 | data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32)); | ||
1605 | data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32)); | ||
1606 | line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32)); | ||
1607 | time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32)); | ||
1608 | |||
1609 | IWL_ERR(priv, "Desc Time " | ||
1610 | "data1 data2 line\n"); | ||
1611 | IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n", | ||
1612 | desc_lookup(desc), desc, time, data1, data2, line); | ||
1613 | IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n"); | ||
1614 | IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2, | ||
1615 | ilink1, ilink2); | ||
1616 | |||
1617 | } | ||
1618 | |||
1619 | #define EVENT_START_OFFSET (4 * sizeof(u32)) | ||
1620 | |||
1621 | /** | ||
1622 | * iwl_print_event_log - Dump error event log to syslog | ||
1623 | * | ||
1624 | */ | ||
1625 | static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, | ||
1626 | u32 num_events, u32 mode) | ||
1627 | { | ||
1628 | u32 i; | ||
1629 | u32 base; /* SRAM byte address of event log header */ | ||
1630 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | ||
1631 | u32 ptr; /* SRAM byte address of log data */ | ||
1632 | u32 ev, time, data; /* event log data */ | ||
1633 | |||
1634 | if (num_events == 0) | ||
1635 | return; | ||
1636 | if (priv->ucode_type == UCODE_INIT) | ||
1637 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); | ||
1638 | else | ||
1639 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | ||
1640 | |||
1641 | if (mode == 0) | ||
1642 | event_size = 2 * sizeof(u32); | ||
1643 | else | ||
1644 | event_size = 3 * sizeof(u32); | ||
1645 | |||
1646 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | ||
1647 | |||
1648 | /* "time" is actually "data" for mode 0 (no timestamp). | ||
1649 | * place event id # at far right for easier visual parsing. */ | ||
1650 | for (i = 0; i < num_events; i++) { | ||
1651 | ev = iwl_read_targ_mem(priv, ptr); | ||
1652 | ptr += sizeof(u32); | ||
1653 | time = iwl_read_targ_mem(priv, ptr); | ||
1654 | ptr += sizeof(u32); | ||
1655 | if (mode == 0) { | ||
1656 | /* data, ev */ | ||
1657 | IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev); | ||
1658 | } else { | ||
1659 | data = iwl_read_targ_mem(priv, ptr); | ||
1660 | ptr += sizeof(u32); | ||
1661 | IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n", | ||
1662 | time, data, ev); | ||
1663 | } | ||
1664 | } | ||
1665 | } | ||
1666 | |||
1667 | void iwl_dump_nic_event_log(struct iwl_priv *priv) | ||
1668 | { | ||
1669 | u32 base; /* SRAM byte address of event log header */ | ||
1670 | u32 capacity; /* event log capacity in # entries */ | ||
1671 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | ||
1672 | u32 num_wraps; /* # times uCode wrapped to top of log */ | ||
1673 | u32 next_entry; /* index of next entry to be written by uCode */ | ||
1674 | u32 size; /* # entries that we'll print */ | ||
1675 | |||
1676 | if (priv->ucode_type == UCODE_INIT) | ||
1677 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); | ||
1678 | else | ||
1679 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | ||
1680 | |||
1681 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | ||
1682 | IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base); | ||
1683 | return; | ||
1684 | } | ||
1685 | |||
1686 | /* event log header */ | ||
1687 | capacity = iwl_read_targ_mem(priv, base); | ||
1688 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | ||
1689 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | ||
1690 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | ||
1691 | |||
1692 | size = num_wraps ? capacity : next_entry; | ||
1693 | |||
1694 | /* bail out if nothing in log */ | ||
1695 | if (size == 0) { | ||
1696 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); | ||
1697 | return; | ||
1698 | } | ||
1699 | |||
1700 | IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n", | ||
1701 | size, num_wraps); | ||
1702 | |||
1703 | /* if uCode has wrapped back to top of log, start at the oldest entry, | ||
1704 | * i.e the next one that uCode would fill. */ | ||
1705 | if (num_wraps) | ||
1706 | iwl_print_event_log(priv, next_entry, | ||
1707 | capacity - next_entry, mode); | ||
1708 | /* (then/else) start at top of log */ | ||
1709 | iwl_print_event_log(priv, 0, next_entry, mode); | ||
1710 | |||
1711 | } | ||
1712 | #endif | ||
1713 | |||
1529 | /** | 1714 | /** |
1530 | * iwl_alive_start - called after REPLY_ALIVE notification received | 1715 | * iwl_alive_start - called after REPLY_ALIVE notification received |
1531 | * from protocol/runtime uCode (initialization uCode's | 1716 | * from protocol/runtime uCode (initialization uCode's |
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.c b/drivers/net/wireless/iwlwifi/iwl-core.c index fd26c0dc9c54..484d5c1a7312 100644 --- a/drivers/net/wireless/iwlwifi/iwl-core.c +++ b/drivers/net/wireless/iwlwifi/iwl-core.c | |||
@@ -1309,189 +1309,6 @@ static void iwl_print_rx_config_cmd(struct iwl_priv *priv) | |||
1309 | IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr); | 1309 | IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr); |
1310 | IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); | 1310 | IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); |
1311 | } | 1311 | } |
1312 | |||
1313 | static const char *desc_lookup_text[] = { | ||
1314 | "OK", | ||
1315 | "FAIL", | ||
1316 | "BAD_PARAM", | ||
1317 | "BAD_CHECKSUM", | ||
1318 | "NMI_INTERRUPT_WDG", | ||
1319 | "SYSASSERT", | ||
1320 | "FATAL_ERROR", | ||
1321 | "BAD_COMMAND", | ||
1322 | "HW_ERROR_TUNE_LOCK", | ||
1323 | "HW_ERROR_TEMPERATURE", | ||
1324 | "ILLEGAL_CHAN_FREQ", | ||
1325 | "VCC_NOT_STABLE", | ||
1326 | "FH_ERROR", | ||
1327 | "NMI_INTERRUPT_HOST", | ||
1328 | "NMI_INTERRUPT_ACTION_PT", | ||
1329 | "NMI_INTERRUPT_UNKNOWN", | ||
1330 | "UCODE_VERSION_MISMATCH", | ||
1331 | "HW_ERROR_ABS_LOCK", | ||
1332 | "HW_ERROR_CAL_LOCK_FAIL", | ||
1333 | "NMI_INTERRUPT_INST_ACTION_PT", | ||
1334 | "NMI_INTERRUPT_DATA_ACTION_PT", | ||
1335 | "NMI_TRM_HW_ER", | ||
1336 | "NMI_INTERRUPT_TRM", | ||
1337 | "NMI_INTERRUPT_BREAK_POINT" | ||
1338 | "DEBUG_0", | ||
1339 | "DEBUG_1", | ||
1340 | "DEBUG_2", | ||
1341 | "DEBUG_3", | ||
1342 | "UNKNOWN" | ||
1343 | }; | ||
1344 | |||
1345 | static const char *desc_lookup(int i) | ||
1346 | { | ||
1347 | int max = ARRAY_SIZE(desc_lookup_text) - 1; | ||
1348 | |||
1349 | if (i < 0 || i > max) | ||
1350 | i = max; | ||
1351 | |||
1352 | return desc_lookup_text[i]; | ||
1353 | } | ||
1354 | |||
1355 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | ||
1356 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | ||
1357 | |||
1358 | static void iwl_dump_nic_error_log(struct iwl_priv *priv) | ||
1359 | { | ||
1360 | u32 data2, line; | ||
1361 | u32 desc, time, count, base, data1; | ||
1362 | u32 blink1, blink2, ilink1, ilink2; | ||
1363 | |||
1364 | if (priv->ucode_type == UCODE_INIT) | ||
1365 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); | ||
1366 | else | ||
1367 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | ||
1368 | |||
1369 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | ||
1370 | IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base); | ||
1371 | return; | ||
1372 | } | ||
1373 | |||
1374 | count = iwl_read_targ_mem(priv, base); | ||
1375 | |||
1376 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | ||
1377 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); | ||
1378 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | ||
1379 | priv->status, count); | ||
1380 | } | ||
1381 | |||
1382 | desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32)); | ||
1383 | blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32)); | ||
1384 | blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32)); | ||
1385 | ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32)); | ||
1386 | ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32)); | ||
1387 | data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32)); | ||
1388 | data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32)); | ||
1389 | line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32)); | ||
1390 | time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32)); | ||
1391 | |||
1392 | IWL_ERR(priv, "Desc Time " | ||
1393 | "data1 data2 line\n"); | ||
1394 | IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n", | ||
1395 | desc_lookup(desc), desc, time, data1, data2, line); | ||
1396 | IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n"); | ||
1397 | IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2, | ||
1398 | ilink1, ilink2); | ||
1399 | |||
1400 | } | ||
1401 | |||
1402 | #define EVENT_START_OFFSET (4 * sizeof(u32)) | ||
1403 | |||
1404 | /** | ||
1405 | * iwl_print_event_log - Dump error event log to syslog | ||
1406 | * | ||
1407 | */ | ||
1408 | static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, | ||
1409 | u32 num_events, u32 mode) | ||
1410 | { | ||
1411 | u32 i; | ||
1412 | u32 base; /* SRAM byte address of event log header */ | ||
1413 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | ||
1414 | u32 ptr; /* SRAM byte address of log data */ | ||
1415 | u32 ev, time, data; /* event log data */ | ||
1416 | |||
1417 | if (num_events == 0) | ||
1418 | return; | ||
1419 | if (priv->ucode_type == UCODE_INIT) | ||
1420 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); | ||
1421 | else | ||
1422 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | ||
1423 | |||
1424 | if (mode == 0) | ||
1425 | event_size = 2 * sizeof(u32); | ||
1426 | else | ||
1427 | event_size = 3 * sizeof(u32); | ||
1428 | |||
1429 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | ||
1430 | |||
1431 | /* "time" is actually "data" for mode 0 (no timestamp). | ||
1432 | * place event id # at far right for easier visual parsing. */ | ||
1433 | for (i = 0; i < num_events; i++) { | ||
1434 | ev = iwl_read_targ_mem(priv, ptr); | ||
1435 | ptr += sizeof(u32); | ||
1436 | time = iwl_read_targ_mem(priv, ptr); | ||
1437 | ptr += sizeof(u32); | ||
1438 | if (mode == 0) { | ||
1439 | /* data, ev */ | ||
1440 | IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev); | ||
1441 | } else { | ||
1442 | data = iwl_read_targ_mem(priv, ptr); | ||
1443 | ptr += sizeof(u32); | ||
1444 | IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n", | ||
1445 | time, data, ev); | ||
1446 | } | ||
1447 | } | ||
1448 | } | ||
1449 | |||
1450 | void iwl_dump_nic_event_log(struct iwl_priv *priv) | ||
1451 | { | ||
1452 | u32 base; /* SRAM byte address of event log header */ | ||
1453 | u32 capacity; /* event log capacity in # entries */ | ||
1454 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | ||
1455 | u32 num_wraps; /* # times uCode wrapped to top of log */ | ||
1456 | u32 next_entry; /* index of next entry to be written by uCode */ | ||
1457 | u32 size; /* # entries that we'll print */ | ||
1458 | |||
1459 | if (priv->ucode_type == UCODE_INIT) | ||
1460 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); | ||
1461 | else | ||
1462 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | ||
1463 | |||
1464 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | ||
1465 | IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base); | ||
1466 | return; | ||
1467 | } | ||
1468 | |||
1469 | /* event log header */ | ||
1470 | capacity = iwl_read_targ_mem(priv, base); | ||
1471 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | ||
1472 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | ||
1473 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | ||
1474 | |||
1475 | size = num_wraps ? capacity : next_entry; | ||
1476 | |||
1477 | /* bail out if nothing in log */ | ||
1478 | if (size == 0) { | ||
1479 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); | ||
1480 | return; | ||
1481 | } | ||
1482 | |||
1483 | IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n", | ||
1484 | size, num_wraps); | ||
1485 | |||
1486 | /* if uCode has wrapped back to top of log, start at the oldest entry, | ||
1487 | * i.e the next one that uCode would fill. */ | ||
1488 | if (num_wraps) | ||
1489 | iwl_print_event_log(priv, next_entry, | ||
1490 | capacity - next_entry, mode); | ||
1491 | /* (then/else) start at top of log */ | ||
1492 | iwl_print_event_log(priv, 0, next_entry, mode); | ||
1493 | |||
1494 | } | ||
1495 | #endif | 1312 | #endif |
1496 | /** | 1313 | /** |
1497 | * iwl_irq_handle_error - called for HW or SW error interrupt from card | 1314 | * iwl_irq_handle_error - called for HW or SW error interrupt from card |
@@ -1506,8 +1323,8 @@ void iwl_irq_handle_error(struct iwl_priv *priv) | |||
1506 | 1323 | ||
1507 | #ifdef CONFIG_IWLWIFI_DEBUG | 1324 | #ifdef CONFIG_IWLWIFI_DEBUG |
1508 | if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) { | 1325 | if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) { |
1509 | iwl_dump_nic_error_log(priv); | 1326 | priv->cfg->ops->lib->dump_nic_error_log(priv); |
1510 | iwl_dump_nic_event_log(priv); | 1327 | priv->cfg->ops->lib->dump_nic_event_log(priv); |
1511 | iwl_print_rx_config_cmd(priv); | 1328 | iwl_print_rx_config_cmd(priv); |
1512 | } | 1329 | } |
1513 | #endif | 1330 | #endif |
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.h b/drivers/net/wireless/iwlwifi/iwl-core.h index 7ff9ffb2b702..e50103a956b1 100644 --- a/drivers/net/wireless/iwlwifi/iwl-core.h +++ b/drivers/net/wireless/iwlwifi/iwl-core.h | |||
@@ -166,6 +166,8 @@ struct iwl_lib_ops { | |||
166 | int (*is_valid_rtc_data_addr)(u32 addr); | 166 | int (*is_valid_rtc_data_addr)(u32 addr); |
167 | /* 1st ucode load */ | 167 | /* 1st ucode load */ |
168 | int (*load_ucode)(struct iwl_priv *priv); | 168 | int (*load_ucode)(struct iwl_priv *priv); |
169 | void (*dump_nic_event_log)(struct iwl_priv *priv); | ||
170 | void (*dump_nic_error_log)(struct iwl_priv *priv); | ||
169 | /* power management */ | 171 | /* power management */ |
170 | struct iwl_apm_ops apm_ops; | 172 | struct iwl_apm_ops apm_ops; |
171 | 173 | ||
@@ -540,7 +542,19 @@ int iwl_pci_resume(struct pci_dev *pdev); | |||
540 | /***************************************************** | 542 | /***************************************************** |
541 | * Error Handling Debugging | 543 | * Error Handling Debugging |
542 | ******************************************************/ | 544 | ******************************************************/ |
545 | #ifdef CONFIG_IWLWIFI_DEBUG | ||
543 | void iwl_dump_nic_event_log(struct iwl_priv *priv); | 546 | void iwl_dump_nic_event_log(struct iwl_priv *priv); |
547 | void iwl_dump_nic_error_log(struct iwl_priv *priv); | ||
548 | #else | ||
549 | static inline void iwl_dump_nic_event_log(struct iwl_priv *priv) | ||
550 | { | ||
551 | } | ||
552 | |||
553 | static inline void iwl_dump_nic_error_log(struct iwl_priv *priv) | ||
554 | { | ||
555 | } | ||
556 | #endif | ||
557 | |||
544 | void iwl_clear_isr_stats(struct iwl_priv *priv); | 558 | void iwl_clear_isr_stats(struct iwl_priv *priv); |
545 | 559 | ||
546 | /***************************************************** | 560 | /***************************************************** |
diff --git a/drivers/net/wireless/iwlwifi/iwl-debugfs.c b/drivers/net/wireless/iwlwifi/iwl-debugfs.c index fb844859a443..a198bcf61022 100644 --- a/drivers/net/wireless/iwlwifi/iwl-debugfs.c +++ b/drivers/net/wireless/iwlwifi/iwl-debugfs.c | |||
@@ -410,7 +410,7 @@ static ssize_t iwl_dbgfs_nvm_read(struct file *file, | |||
410 | pos += scnprintf(buf + pos, buf_size - pos, "0x%.4x ", ofs); | 410 | pos += scnprintf(buf + pos, buf_size - pos, "0x%.4x ", ofs); |
411 | hex_dump_to_buffer(ptr + ofs, 16 , 16, 2, buf + pos, | 411 | hex_dump_to_buffer(ptr + ofs, 16 , 16, 2, buf + pos, |
412 | buf_size - pos, 0); | 412 | buf_size - pos, 0); |
413 | pos += strlen(buf); | 413 | pos += strlen(buf + pos); |
414 | if (buf_size - pos > 0) | 414 | if (buf_size - pos > 0) |
415 | buf[pos++] = '\n'; | 415 | buf[pos++] = '\n'; |
416 | } | 416 | } |
@@ -436,7 +436,7 @@ static ssize_t iwl_dbgfs_log_event_write(struct file *file, | |||
436 | if (sscanf(buf, "%d", &event_log_flag) != 1) | 436 | if (sscanf(buf, "%d", &event_log_flag) != 1) |
437 | return -EFAULT; | 437 | return -EFAULT; |
438 | if (event_log_flag == 1) | 438 | if (event_log_flag == 1) |
439 | iwl_dump_nic_event_log(priv); | 439 | priv->cfg->ops->lib->dump_nic_event_log(priv); |
440 | 440 | ||
441 | return count; | 441 | return count; |
442 | } | 442 | } |
@@ -909,7 +909,7 @@ static ssize_t iwl_dbgfs_traffic_log_read(struct file *file, | |||
909 | "0x%.4x ", ofs); | 909 | "0x%.4x ", ofs); |
910 | hex_dump_to_buffer(ptr + ofs, 16, 16, 2, | 910 | hex_dump_to_buffer(ptr + ofs, 16, 16, 2, |
911 | buf + pos, bufsz - pos, 0); | 911 | buf + pos, bufsz - pos, 0); |
912 | pos += strlen(buf); | 912 | pos += strlen(buf + pos); |
913 | if (bufsz - pos > 0) | 913 | if (bufsz - pos > 0) |
914 | buf[pos++] = '\n'; | 914 | buf[pos++] = '\n'; |
915 | } | 915 | } |
@@ -932,7 +932,7 @@ static ssize_t iwl_dbgfs_traffic_log_read(struct file *file, | |||
932 | "0x%.4x ", ofs); | 932 | "0x%.4x ", ofs); |
933 | hex_dump_to_buffer(ptr + ofs, 16, 16, 2, | 933 | hex_dump_to_buffer(ptr + ofs, 16, 16, 2, |
934 | buf + pos, bufsz - pos, 0); | 934 | buf + pos, bufsz - pos, 0); |
935 | pos += strlen(buf); | 935 | pos += strlen(buf + pos); |
936 | if (bufsz - pos > 0) | 936 | if (bufsz - pos > 0) |
937 | buf[pos++] = '\n'; | 937 | buf[pos++] = '\n'; |
938 | } | 938 | } |
diff --git a/drivers/net/wireless/iwlwifi/iwl-tx.c b/drivers/net/wireless/iwlwifi/iwl-tx.c index a7422e52d883..c18907544701 100644 --- a/drivers/net/wireless/iwlwifi/iwl-tx.c +++ b/drivers/net/wireless/iwlwifi/iwl-tx.c | |||
@@ -197,6 +197,12 @@ void iwl_cmd_queue_free(struct iwl_priv *priv) | |||
197 | pci_free_consistent(dev, priv->hw_params.tfd_size * | 197 | pci_free_consistent(dev, priv->hw_params.tfd_size * |
198 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); | 198 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); |
199 | 199 | ||
200 | /* deallocate arrays */ | ||
201 | kfree(txq->cmd); | ||
202 | kfree(txq->meta); | ||
203 | txq->cmd = NULL; | ||
204 | txq->meta = NULL; | ||
205 | |||
200 | /* 0-fill queue descriptor structure */ | 206 | /* 0-fill queue descriptor structure */ |
201 | memset(txq, 0, sizeof(*txq)); | 207 | memset(txq, 0, sizeof(*txq)); |
202 | } | 208 | } |
diff --git a/drivers/net/wireless/iwlwifi/iwl3945-base.c b/drivers/net/wireless/iwlwifi/iwl3945-base.c index 4f2d43937283..c390dbd877e4 100644 --- a/drivers/net/wireless/iwlwifi/iwl3945-base.c +++ b/drivers/net/wireless/iwlwifi/iwl3945-base.c | |||
@@ -1481,6 +1481,7 @@ static inline void iwl_synchronize_irq(struct iwl_priv *priv) | |||
1481 | tasklet_kill(&priv->irq_tasklet); | 1481 | tasklet_kill(&priv->irq_tasklet); |
1482 | } | 1482 | } |
1483 | 1483 | ||
1484 | #ifdef CONFIG_IWLWIFI_DEBUG | ||
1484 | static const char *desc_lookup(int i) | 1485 | static const char *desc_lookup(int i) |
1485 | { | 1486 | { |
1486 | switch (i) { | 1487 | switch (i) { |
@@ -1504,7 +1505,7 @@ static const char *desc_lookup(int i) | |||
1504 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | 1505 | #define ERROR_START_OFFSET (1 * sizeof(u32)) |
1505 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | 1506 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) |
1506 | 1507 | ||
1507 | static void iwl3945_dump_nic_error_log(struct iwl_priv *priv) | 1508 | void iwl3945_dump_nic_error_log(struct iwl_priv *priv) |
1508 | { | 1509 | { |
1509 | u32 i; | 1510 | u32 i; |
1510 | u32 desc, time, count, base, data1; | 1511 | u32 desc, time, count, base, data1; |
@@ -1598,7 +1599,7 @@ static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx, | |||
1598 | } | 1599 | } |
1599 | } | 1600 | } |
1600 | 1601 | ||
1601 | static void iwl3945_dump_nic_event_log(struct iwl_priv *priv) | 1602 | void iwl3945_dump_nic_event_log(struct iwl_priv *priv) |
1602 | { | 1603 | { |
1603 | u32 base; /* SRAM byte address of event log header */ | 1604 | u32 base; /* SRAM byte address of event log header */ |
1604 | u32 capacity; /* event log capacity in # entries */ | 1605 | u32 capacity; /* event log capacity in # entries */ |
@@ -1640,6 +1641,16 @@ static void iwl3945_dump_nic_event_log(struct iwl_priv *priv) | |||
1640 | iwl3945_print_event_log(priv, 0, next_entry, mode); | 1641 | iwl3945_print_event_log(priv, 0, next_entry, mode); |
1641 | 1642 | ||
1642 | } | 1643 | } |
1644 | #else | ||
1645 | void iwl3945_dump_nic_event_log(struct iwl_priv *priv) | ||
1646 | { | ||
1647 | } | ||
1648 | |||
1649 | void iwl3945_dump_nic_error_log(struct iwl_priv *priv) | ||
1650 | { | ||
1651 | } | ||
1652 | |||
1653 | #endif | ||
1643 | 1654 | ||
1644 | static void iwl3945_irq_tasklet(struct iwl_priv *priv) | 1655 | static void iwl3945_irq_tasklet(struct iwl_priv *priv) |
1645 | { | 1656 | { |
@@ -3683,21 +3694,6 @@ static ssize_t dump_error_log(struct device *d, | |||
3683 | 3694 | ||
3684 | static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log); | 3695 | static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log); |
3685 | 3696 | ||
3686 | static ssize_t dump_event_log(struct device *d, | ||
3687 | struct device_attribute *attr, | ||
3688 | const char *buf, size_t count) | ||
3689 | { | ||
3690 | struct iwl_priv *priv = dev_get_drvdata(d); | ||
3691 | char *p = (char *)buf; | ||
3692 | |||
3693 | if (p[0] == '1') | ||
3694 | iwl3945_dump_nic_event_log(priv); | ||
3695 | |||
3696 | return strnlen(buf, count); | ||
3697 | } | ||
3698 | |||
3699 | static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log); | ||
3700 | |||
3701 | /***************************************************************************** | 3697 | /***************************************************************************** |
3702 | * | 3698 | * |
3703 | * driver setup and tear down | 3699 | * driver setup and tear down |
@@ -3742,7 +3738,6 @@ static struct attribute *iwl3945_sysfs_entries[] = { | |||
3742 | &dev_attr_antenna.attr, | 3738 | &dev_attr_antenna.attr, |
3743 | &dev_attr_channels.attr, | 3739 | &dev_attr_channels.attr, |
3744 | &dev_attr_dump_errors.attr, | 3740 | &dev_attr_dump_errors.attr, |
3745 | &dev_attr_dump_events.attr, | ||
3746 | &dev_attr_flags.attr, | 3741 | &dev_attr_flags.attr, |
3747 | &dev_attr_filter_flags.attr, | 3742 | &dev_attr_filter_flags.attr, |
3748 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT | 3743 | #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT |
diff --git a/drivers/net/wireless/mac80211_hwsim.c b/drivers/net/wireless/mac80211_hwsim.c index 896f532182f0..38cfd79e0590 100644 --- a/drivers/net/wireless/mac80211_hwsim.c +++ b/drivers/net/wireless/mac80211_hwsim.c | |||
@@ -631,6 +631,9 @@ static void mac80211_hwsim_bss_info_changed(struct ieee80211_hw *hw, | |||
631 | data->beacon_int = 1024 * info->beacon_int / 1000 * HZ / 1000; | 631 | data->beacon_int = 1024 * info->beacon_int / 1000 * HZ / 1000; |
632 | if (WARN_ON(!data->beacon_int)) | 632 | if (WARN_ON(!data->beacon_int)) |
633 | data->beacon_int = 1; | 633 | data->beacon_int = 1; |
634 | if (data->started) | ||
635 | mod_timer(&data->beacon_timer, | ||
636 | jiffies + data->beacon_int); | ||
634 | } | 637 | } |
635 | 638 | ||
636 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { | 639 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
diff --git a/drivers/net/wireless/rt2x00/rt73usb.c b/drivers/net/wireless/rt2x00/rt73usb.c index 1cbd9b4a3efc..b8f5ee33445e 100644 --- a/drivers/net/wireless/rt2x00/rt73usb.c +++ b/drivers/net/wireless/rt2x00/rt73usb.c | |||
@@ -2381,6 +2381,7 @@ static struct usb_device_id rt73usb_device_table[] = { | |||
2381 | /* Huawei-3Com */ | 2381 | /* Huawei-3Com */ |
2382 | { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) }, | 2382 | { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) }, |
2383 | /* Hercules */ | 2383 | /* Hercules */ |
2384 | { USB_DEVICE(0x06f8, 0xe002), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
2384 | { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) }, | 2385 | { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) }, |
2385 | { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) }, | 2386 | { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) }, |
2386 | /* Linksys */ | 2387 | /* Linksys */ |
diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig index fbf965b31c14..17f38a781d47 100644 --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig | |||
@@ -192,6 +192,10 @@ config PCMCIA_AU1X00 | |||
192 | tristate "Au1x00 pcmcia support" | 192 | tristate "Au1x00 pcmcia support" |
193 | depends on SOC_AU1X00 && PCMCIA | 193 | depends on SOC_AU1X00 && PCMCIA |
194 | 194 | ||
195 | config PCMCIA_BCM63XX | ||
196 | tristate "bcm63xx pcmcia support" | ||
197 | depends on BCM63XX && PCMCIA | ||
198 | |||
195 | config PCMCIA_SA1100 | 199 | config PCMCIA_SA1100 |
196 | tristate "SA1100 support" | 200 | tristate "SA1100 support" |
197 | depends on ARM && ARCH_SA1100 && PCMCIA | 201 | depends on ARM && ARCH_SA1100 && PCMCIA |
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index 3247828aa203..a03a38acd77d 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile | |||
@@ -27,6 +27,7 @@ obj-$(CONFIG_PCMCIA_SA1111) += sa11xx_core.o sa1111_cs.o | |||
27 | obj-$(CONFIG_M32R_PCC) += m32r_pcc.o | 27 | obj-$(CONFIG_M32R_PCC) += m32r_pcc.o |
28 | obj-$(CONFIG_M32R_CFC) += m32r_cfc.o | 28 | obj-$(CONFIG_M32R_CFC) += m32r_cfc.o |
29 | obj-$(CONFIG_PCMCIA_AU1X00) += au1x00_ss.o | 29 | obj-$(CONFIG_PCMCIA_AU1X00) += au1x00_ss.o |
30 | obj-$(CONFIG_PCMCIA_BCM63XX) += bcm63xx_pcmcia.o | ||
30 | obj-$(CONFIG_PCMCIA_VRC4171) += vrc4171_card.o | 31 | obj-$(CONFIG_PCMCIA_VRC4171) += vrc4171_card.o |
31 | obj-$(CONFIG_PCMCIA_VRC4173) += vrc4173_cardu.o | 32 | obj-$(CONFIG_PCMCIA_VRC4173) += vrc4173_cardu.o |
32 | obj-$(CONFIG_OMAP_CF) += omap_cf.o | 33 | obj-$(CONFIG_OMAP_CF) += omap_cf.o |
diff --git a/drivers/pcmcia/at91_cf.c b/drivers/pcmcia/at91_cf.c index 9e1140f085fd..e1dccedc5960 100644 --- a/drivers/pcmcia/at91_cf.c +++ b/drivers/pcmcia/at91_cf.c | |||
@@ -363,7 +363,7 @@ static int at91_cf_suspend(struct platform_device *pdev, pm_message_t mesg) | |||
363 | struct at91_cf_socket *cf = platform_get_drvdata(pdev); | 363 | struct at91_cf_socket *cf = platform_get_drvdata(pdev); |
364 | struct at91_cf_data *board = cf->board; | 364 | struct at91_cf_data *board = cf->board; |
365 | 365 | ||
366 | pcmcia_socket_dev_suspend(&pdev->dev, mesg); | 366 | pcmcia_socket_dev_suspend(&pdev->dev); |
367 | if (device_may_wakeup(&pdev->dev)) { | 367 | if (device_may_wakeup(&pdev->dev)) { |
368 | enable_irq_wake(board->det_pin); | 368 | enable_irq_wake(board->det_pin); |
369 | if (board->irq_pin) | 369 | if (board->irq_pin) |
diff --git a/drivers/pcmcia/au1000_generic.c b/drivers/pcmcia/au1000_generic.c index 90013341cd5f..02088704ac2c 100644 --- a/drivers/pcmcia/au1000_generic.c +++ b/drivers/pcmcia/au1000_generic.c | |||
@@ -515,7 +515,7 @@ static int au1x00_drv_pcmcia_probe(struct platform_device *dev) | |||
515 | static int au1x00_drv_pcmcia_suspend(struct platform_device *dev, | 515 | static int au1x00_drv_pcmcia_suspend(struct platform_device *dev, |
516 | pm_message_t state) | 516 | pm_message_t state) |
517 | { | 517 | { |
518 | return pcmcia_socket_dev_suspend(&dev->dev, state); | 518 | return pcmcia_socket_dev_suspend(&dev->dev); |
519 | } | 519 | } |
520 | 520 | ||
521 | static int au1x00_drv_pcmcia_resume(struct platform_device *dev) | 521 | static int au1x00_drv_pcmcia_resume(struct platform_device *dev) |
diff --git a/drivers/pcmcia/bcm63xx_pcmcia.c b/drivers/pcmcia/bcm63xx_pcmcia.c new file mode 100644 index 000000000000..bc88a3b19bb3 --- /dev/null +++ b/drivers/pcmcia/bcm63xx_pcmcia.c | |||
@@ -0,0 +1,536 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> | ||
7 | */ | ||
8 | |||
9 | #include <linux/kernel.h> | ||
10 | #include <linux/module.h> | ||
11 | #include <linux/ioport.h> | ||
12 | #include <linux/timer.h> | ||
13 | #include <linux/platform_device.h> | ||
14 | #include <linux/delay.h> | ||
15 | #include <linux/pci.h> | ||
16 | #include <linux/gpio.h> | ||
17 | |||
18 | #include <bcm63xx_regs.h> | ||
19 | #include <bcm63xx_io.h> | ||
20 | #include "bcm63xx_pcmcia.h" | ||
21 | |||
22 | #define PFX "bcm63xx_pcmcia: " | ||
23 | |||
24 | #ifdef CONFIG_CARDBUS | ||
25 | /* if cardbus is used, platform device needs reference to actual pci | ||
26 | * device */ | ||
27 | static struct pci_dev *bcm63xx_cb_dev; | ||
28 | #endif | ||
29 | |||
30 | /* | ||
31 | * read/write helper for pcmcia regs | ||
32 | */ | ||
33 | static inline u32 pcmcia_readl(struct bcm63xx_pcmcia_socket *skt, u32 off) | ||
34 | { | ||
35 | return bcm_readl(skt->base + off); | ||
36 | } | ||
37 | |||
38 | static inline void pcmcia_writel(struct bcm63xx_pcmcia_socket *skt, | ||
39 | u32 val, u32 off) | ||
40 | { | ||
41 | bcm_writel(val, skt->base + off); | ||
42 | } | ||
43 | |||
44 | /* | ||
45 | * This callback should (re-)initialise the socket, turn on status | ||
46 | * interrupts and PCMCIA bus, and wait for power to stabilise so that | ||
47 | * the card status signals report correctly. | ||
48 | * | ||
49 | * Hardware cannot do that. | ||
50 | */ | ||
51 | static int bcm63xx_pcmcia_sock_init(struct pcmcia_socket *sock) | ||
52 | { | ||
53 | return 0; | ||
54 | } | ||
55 | |||
56 | /* | ||
57 | * This callback should remove power on the socket, disable IRQs from | ||
58 | * the card, turn off status interrupts, and disable the PCMCIA bus. | ||
59 | * | ||
60 | * Hardware cannot do that. | ||
61 | */ | ||
62 | static int bcm63xx_pcmcia_suspend(struct pcmcia_socket *sock) | ||
63 | { | ||
64 | return 0; | ||
65 | } | ||
66 | |||
67 | /* | ||
68 | * Implements the set_socket() operation for the in-kernel PCMCIA | ||
69 | * service (formerly SS_SetSocket in Card Services). We more or | ||
70 | * less punt all of this work and let the kernel handle the details | ||
71 | * of power configuration, reset, &c. We also record the value of | ||
72 | * `state' in order to regurgitate it to the PCMCIA core later. | ||
73 | */ | ||
74 | static int bcm63xx_pcmcia_set_socket(struct pcmcia_socket *sock, | ||
75 | socket_state_t *state) | ||
76 | { | ||
77 | struct bcm63xx_pcmcia_socket *skt; | ||
78 | unsigned long flags; | ||
79 | u32 val; | ||
80 | |||
81 | skt = sock->driver_data; | ||
82 | |||
83 | spin_lock_irqsave(&skt->lock, flags); | ||
84 | |||
85 | /* note: hardware cannot control socket power, so we will | ||
86 | * always report SS_POWERON */ | ||
87 | |||
88 | /* apply socket reset */ | ||
89 | val = pcmcia_readl(skt, PCMCIA_C1_REG); | ||
90 | if (state->flags & SS_RESET) | ||
91 | val |= PCMCIA_C1_RESET_MASK; | ||
92 | else | ||
93 | val &= ~PCMCIA_C1_RESET_MASK; | ||
94 | |||
95 | /* reverse reset logic for cardbus card */ | ||
96 | if (skt->card_detected && (skt->card_type & CARD_CARDBUS)) | ||
97 | val ^= PCMCIA_C1_RESET_MASK; | ||
98 | |||
99 | pcmcia_writel(skt, val, PCMCIA_C1_REG); | ||
100 | |||
101 | /* keep requested state for event reporting */ | ||
102 | skt->requested_state = *state; | ||
103 | |||
104 | spin_unlock_irqrestore(&skt->lock, flags); | ||
105 | |||
106 | return 0; | ||
107 | } | ||
108 | |||
109 | /* | ||
110 | * identity cardtype from VS[12] input, CD[12] input while only VS2 is | ||
111 | * floating, and CD[12] input while only VS1 is floating | ||
112 | */ | ||
113 | enum { | ||
114 | IN_VS1 = (1 << 0), | ||
115 | IN_VS2 = (1 << 1), | ||
116 | IN_CD1_VS2H = (1 << 2), | ||
117 | IN_CD2_VS2H = (1 << 3), | ||
118 | IN_CD1_VS1H = (1 << 4), | ||
119 | IN_CD2_VS1H = (1 << 5), | ||
120 | }; | ||
121 | |||
122 | static const u8 vscd_to_cardtype[] = { | ||
123 | |||
124 | /* VS1 float, VS2 float */ | ||
125 | [IN_VS1 | IN_VS2] = (CARD_PCCARD | CARD_5V), | ||
126 | |||
127 | /* VS1 grounded, VS2 float */ | ||
128 | [IN_VS2] = (CARD_PCCARD | CARD_5V | CARD_3V), | ||
129 | |||
130 | /* VS1 grounded, VS2 grounded */ | ||
131 | [0] = (CARD_PCCARD | CARD_5V | CARD_3V | CARD_XV), | ||
132 | |||
133 | /* VS1 tied to CD1, VS2 float */ | ||
134 | [IN_VS1 | IN_VS2 | IN_CD1_VS1H] = (CARD_CARDBUS | CARD_3V), | ||
135 | |||
136 | /* VS1 grounded, VS2 tied to CD2 */ | ||
137 | [IN_VS2 | IN_CD2_VS2H] = (CARD_CARDBUS | CARD_3V | CARD_XV), | ||
138 | |||
139 | /* VS1 tied to CD2, VS2 grounded */ | ||
140 | [IN_VS1 | IN_CD2_VS1H] = (CARD_CARDBUS | CARD_3V | CARD_XV | CARD_YV), | ||
141 | |||
142 | /* VS1 float, VS2 grounded */ | ||
143 | [IN_VS1] = (CARD_PCCARD | CARD_XV), | ||
144 | |||
145 | /* VS1 float, VS2 tied to CD2 */ | ||
146 | [IN_VS1 | IN_VS2 | IN_CD2_VS2H] = (CARD_CARDBUS | CARD_3V), | ||
147 | |||
148 | /* VS1 float, VS2 tied to CD1 */ | ||
149 | [IN_VS1 | IN_VS2 | IN_CD1_VS2H] = (CARD_CARDBUS | CARD_XV | CARD_YV), | ||
150 | |||
151 | /* VS1 tied to CD2, VS2 float */ | ||
152 | [IN_VS1 | IN_VS2 | IN_CD2_VS1H] = (CARD_CARDBUS | CARD_YV), | ||
153 | |||
154 | /* VS2 grounded, VS1 is tied to CD1, CD2 is grounded */ | ||
155 | [IN_VS1 | IN_CD1_VS1H] = 0, /* ignore cardbay */ | ||
156 | }; | ||
157 | |||
158 | /* | ||
159 | * poll hardware to check card insertion status | ||
160 | */ | ||
161 | static unsigned int __get_socket_status(struct bcm63xx_pcmcia_socket *skt) | ||
162 | { | ||
163 | unsigned int stat; | ||
164 | u32 val; | ||
165 | |||
166 | stat = 0; | ||
167 | |||
168 | /* check CD for card presence */ | ||
169 | val = pcmcia_readl(skt, PCMCIA_C1_REG); | ||
170 | |||
171 | if (!(val & PCMCIA_C1_CD1_MASK) && !(val & PCMCIA_C1_CD2_MASK)) | ||
172 | stat |= SS_DETECT; | ||
173 | |||
174 | /* if new insertion, detect cardtype */ | ||
175 | if ((stat & SS_DETECT) && !skt->card_detected) { | ||
176 | unsigned int stat = 0; | ||
177 | |||
178 | /* float VS1, float VS2 */ | ||
179 | val |= PCMCIA_C1_VS1OE_MASK; | ||
180 | val |= PCMCIA_C1_VS2OE_MASK; | ||
181 | pcmcia_writel(skt, val, PCMCIA_C1_REG); | ||
182 | |||
183 | /* wait for output to stabilize and read VS[12] */ | ||
184 | udelay(10); | ||
185 | val = pcmcia_readl(skt, PCMCIA_C1_REG); | ||
186 | stat |= (val & PCMCIA_C1_VS1_MASK) ? IN_VS1 : 0; | ||
187 | stat |= (val & PCMCIA_C1_VS2_MASK) ? IN_VS2 : 0; | ||
188 | |||
189 | /* drive VS1 low, float VS2 */ | ||
190 | val &= ~PCMCIA_C1_VS1OE_MASK; | ||
191 | val |= PCMCIA_C1_VS2OE_MASK; | ||
192 | pcmcia_writel(skt, val, PCMCIA_C1_REG); | ||
193 | |||
194 | /* wait for output to stabilize and read CD[12] */ | ||
195 | udelay(10); | ||
196 | val = pcmcia_readl(skt, PCMCIA_C1_REG); | ||
197 | stat |= (val & PCMCIA_C1_CD1_MASK) ? IN_CD1_VS2H : 0; | ||
198 | stat |= (val & PCMCIA_C1_CD2_MASK) ? IN_CD2_VS2H : 0; | ||
199 | |||
200 | /* float VS1, drive VS2 low */ | ||
201 | val |= PCMCIA_C1_VS1OE_MASK; | ||
202 | val &= ~PCMCIA_C1_VS2OE_MASK; | ||
203 | pcmcia_writel(skt, val, PCMCIA_C1_REG); | ||
204 | |||
205 | /* wait for output to stabilize and read CD[12] */ | ||
206 | udelay(10); | ||
207 | val = pcmcia_readl(skt, PCMCIA_C1_REG); | ||
208 | stat |= (val & PCMCIA_C1_CD1_MASK) ? IN_CD1_VS1H : 0; | ||
209 | stat |= (val & PCMCIA_C1_CD2_MASK) ? IN_CD2_VS1H : 0; | ||
210 | |||
211 | /* guess cardtype from all this */ | ||
212 | skt->card_type = vscd_to_cardtype[stat]; | ||
213 | if (!skt->card_type) | ||
214 | dev_err(&skt->socket.dev, "unsupported card type\n"); | ||
215 | |||
216 | /* drive both VS pin to 0 again */ | ||
217 | val &= ~(PCMCIA_C1_VS1OE_MASK | PCMCIA_C1_VS2OE_MASK); | ||
218 | |||
219 | /* enable correct logic */ | ||
220 | val &= ~(PCMCIA_C1_EN_PCMCIA_MASK | PCMCIA_C1_EN_CARDBUS_MASK); | ||
221 | if (skt->card_type & CARD_PCCARD) | ||
222 | val |= PCMCIA_C1_EN_PCMCIA_MASK; | ||
223 | else | ||
224 | val |= PCMCIA_C1_EN_CARDBUS_MASK; | ||
225 | |||
226 | pcmcia_writel(skt, val, PCMCIA_C1_REG); | ||
227 | } | ||
228 | skt->card_detected = (stat & SS_DETECT) ? 1 : 0; | ||
229 | |||
230 | /* report card type/voltage */ | ||
231 | if (skt->card_type & CARD_CARDBUS) | ||
232 | stat |= SS_CARDBUS; | ||
233 | if (skt->card_type & CARD_3V) | ||
234 | stat |= SS_3VCARD; | ||
235 | if (skt->card_type & CARD_XV) | ||
236 | stat |= SS_XVCARD; | ||
237 | stat |= SS_POWERON; | ||
238 | |||
239 | if (gpio_get_value(skt->pd->ready_gpio)) | ||
240 | stat |= SS_READY; | ||
241 | |||
242 | return stat; | ||
243 | } | ||
244 | |||
245 | /* | ||
246 | * core request to get current socket status | ||
247 | */ | ||
248 | static int bcm63xx_pcmcia_get_status(struct pcmcia_socket *sock, | ||
249 | unsigned int *status) | ||
250 | { | ||
251 | struct bcm63xx_pcmcia_socket *skt; | ||
252 | |||
253 | skt = sock->driver_data; | ||
254 | |||
255 | spin_lock_bh(&skt->lock); | ||
256 | *status = __get_socket_status(skt); | ||
257 | spin_unlock_bh(&skt->lock); | ||
258 | |||
259 | return 0; | ||
260 | } | ||
261 | |||
262 | /* | ||
263 | * socket polling timer callback | ||
264 | */ | ||
265 | static void bcm63xx_pcmcia_poll(unsigned long data) | ||
266 | { | ||
267 | struct bcm63xx_pcmcia_socket *skt; | ||
268 | unsigned int stat, events; | ||
269 | |||
270 | skt = (struct bcm63xx_pcmcia_socket *)data; | ||
271 | |||
272 | spin_lock_bh(&skt->lock); | ||
273 | |||
274 | stat = __get_socket_status(skt); | ||
275 | |||
276 | /* keep only changed bits, and mask with required one from the | ||
277 | * core */ | ||
278 | events = (stat ^ skt->old_status) & skt->requested_state.csc_mask; | ||
279 | skt->old_status = stat; | ||
280 | spin_unlock_bh(&skt->lock); | ||
281 | |||
282 | if (events) | ||
283 | pcmcia_parse_events(&skt->socket, events); | ||
284 | |||
285 | mod_timer(&skt->timer, | ||
286 | jiffies + msecs_to_jiffies(BCM63XX_PCMCIA_POLL_RATE)); | ||
287 | } | ||
288 | |||
289 | static int bcm63xx_pcmcia_set_io_map(struct pcmcia_socket *sock, | ||
290 | struct pccard_io_map *map) | ||
291 | { | ||
292 | /* this doesn't seem to be called by pcmcia layer if static | ||
293 | * mapping is used */ | ||
294 | return 0; | ||
295 | } | ||
296 | |||
297 | static int bcm63xx_pcmcia_set_mem_map(struct pcmcia_socket *sock, | ||
298 | struct pccard_mem_map *map) | ||
299 | { | ||
300 | struct bcm63xx_pcmcia_socket *skt; | ||
301 | struct resource *res; | ||
302 | |||
303 | skt = sock->driver_data; | ||
304 | if (map->flags & MAP_ATTRIB) | ||
305 | res = skt->attr_res; | ||
306 | else | ||
307 | res = skt->common_res; | ||
308 | |||
309 | map->static_start = res->start + map->card_start; | ||
310 | return 0; | ||
311 | } | ||
312 | |||
313 | static struct pccard_operations bcm63xx_pcmcia_operations = { | ||
314 | .init = bcm63xx_pcmcia_sock_init, | ||
315 | .suspend = bcm63xx_pcmcia_suspend, | ||
316 | .get_status = bcm63xx_pcmcia_get_status, | ||
317 | .set_socket = bcm63xx_pcmcia_set_socket, | ||
318 | .set_io_map = bcm63xx_pcmcia_set_io_map, | ||
319 | .set_mem_map = bcm63xx_pcmcia_set_mem_map, | ||
320 | }; | ||
321 | |||
322 | /* | ||
323 | * register pcmcia socket to core | ||
324 | */ | ||
325 | static int __devinit bcm63xx_drv_pcmcia_probe(struct platform_device *pdev) | ||
326 | { | ||
327 | struct bcm63xx_pcmcia_socket *skt; | ||
328 | struct pcmcia_socket *sock; | ||
329 | struct resource *res, *irq_res; | ||
330 | unsigned int regmem_size = 0, iomem_size = 0; | ||
331 | u32 val; | ||
332 | int ret; | ||
333 | |||
334 | skt = kzalloc(sizeof(*skt), GFP_KERNEL); | ||
335 | if (!skt) | ||
336 | return -ENOMEM; | ||
337 | spin_lock_init(&skt->lock); | ||
338 | sock = &skt->socket; | ||
339 | sock->driver_data = skt; | ||
340 | |||
341 | /* make sure we have all resources we need */ | ||
342 | skt->common_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | ||
343 | skt->attr_res = platform_get_resource(pdev, IORESOURCE_MEM, 2); | ||
344 | irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | ||
345 | skt->pd = pdev->dev.platform_data; | ||
346 | if (!skt->common_res || !skt->attr_res || !irq_res || !skt->pd) { | ||
347 | ret = -EINVAL; | ||
348 | goto err; | ||
349 | } | ||
350 | |||
351 | /* remap pcmcia registers */ | ||
352 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
353 | regmem_size = resource_size(res); | ||
354 | if (!request_mem_region(res->start, regmem_size, "bcm63xx_pcmcia")) { | ||
355 | ret = -EINVAL; | ||
356 | goto err; | ||
357 | } | ||
358 | skt->reg_res = res; | ||
359 | |||
360 | skt->base = ioremap(res->start, regmem_size); | ||
361 | if (!skt->base) { | ||
362 | ret = -ENOMEM; | ||
363 | goto err; | ||
364 | } | ||
365 | |||
366 | /* remap io registers */ | ||
367 | res = platform_get_resource(pdev, IORESOURCE_MEM, 3); | ||
368 | iomem_size = resource_size(res); | ||
369 | skt->io_base = ioremap(res->start, iomem_size); | ||
370 | if (!skt->io_base) { | ||
371 | ret = -ENOMEM; | ||
372 | goto err; | ||
373 | } | ||
374 | |||
375 | /* resources are static */ | ||
376 | sock->resource_ops = &pccard_static_ops; | ||
377 | sock->ops = &bcm63xx_pcmcia_operations; | ||
378 | sock->owner = THIS_MODULE; | ||
379 | sock->dev.parent = &pdev->dev; | ||
380 | sock->features = SS_CAP_STATIC_MAP | SS_CAP_PCCARD; | ||
381 | sock->io_offset = (unsigned long)skt->io_base; | ||
382 | sock->pci_irq = irq_res->start; | ||
383 | |||
384 | #ifdef CONFIG_CARDBUS | ||
385 | sock->cb_dev = bcm63xx_cb_dev; | ||
386 | if (bcm63xx_cb_dev) | ||
387 | sock->features |= SS_CAP_CARDBUS; | ||
388 | #endif | ||
389 | |||
390 | /* assume common & attribute memory have the same size */ | ||
391 | sock->map_size = resource_size(skt->common_res); | ||
392 | |||
393 | /* initialize polling timer */ | ||
394 | setup_timer(&skt->timer, bcm63xx_pcmcia_poll, (unsigned long)skt); | ||
395 | |||
396 | /* initialize pcmcia control register, drive VS[12] to 0, | ||
397 | * leave CB IDSEL to the old value since it is set by the PCI | ||
398 | * layer */ | ||
399 | val = pcmcia_readl(skt, PCMCIA_C1_REG); | ||
400 | val &= PCMCIA_C1_CBIDSEL_MASK; | ||
401 | val |= PCMCIA_C1_EN_PCMCIA_GPIO_MASK; | ||
402 | pcmcia_writel(skt, val, PCMCIA_C1_REG); | ||
403 | |||
404 | /* | ||
405 | * Hardware has only one set of timings registers, not one for | ||
406 | * each memory access type, so we configure them for the | ||
407 | * slowest one: attribute memory. | ||
408 | */ | ||
409 | val = PCMCIA_C2_DATA16_MASK; | ||
410 | val |= 10 << PCMCIA_C2_RWCOUNT_SHIFT; | ||
411 | val |= 6 << PCMCIA_C2_INACTIVE_SHIFT; | ||
412 | val |= 3 << PCMCIA_C2_SETUP_SHIFT; | ||
413 | val |= 3 << PCMCIA_C2_HOLD_SHIFT; | ||
414 | pcmcia_writel(skt, val, PCMCIA_C2_REG); | ||
415 | |||
416 | ret = pcmcia_register_socket(sock); | ||
417 | if (ret) | ||
418 | goto err; | ||
419 | |||
420 | /* start polling socket */ | ||
421 | mod_timer(&skt->timer, | ||
422 | jiffies + msecs_to_jiffies(BCM63XX_PCMCIA_POLL_RATE)); | ||
423 | |||
424 | platform_set_drvdata(pdev, skt); | ||
425 | return 0; | ||
426 | |||
427 | err: | ||
428 | if (skt->io_base) | ||
429 | iounmap(skt->io_base); | ||
430 | if (skt->base) | ||
431 | iounmap(skt->base); | ||
432 | if (skt->reg_res) | ||
433 | release_mem_region(skt->reg_res->start, regmem_size); | ||
434 | kfree(skt); | ||
435 | return ret; | ||
436 | } | ||
437 | |||
438 | static int __devexit bcm63xx_drv_pcmcia_remove(struct platform_device *pdev) | ||
439 | { | ||
440 | struct bcm63xx_pcmcia_socket *skt; | ||
441 | struct resource *res; | ||
442 | |||
443 | skt = platform_get_drvdata(pdev); | ||
444 | del_timer_sync(&skt->timer); | ||
445 | iounmap(skt->base); | ||
446 | iounmap(skt->io_base); | ||
447 | res = skt->reg_res; | ||
448 | release_mem_region(res->start, resource_size(res)); | ||
449 | kfree(skt); | ||
450 | return 0; | ||
451 | } | ||
452 | |||
453 | struct platform_driver bcm63xx_pcmcia_driver = { | ||
454 | .probe = bcm63xx_drv_pcmcia_probe, | ||
455 | .remove = __devexit_p(bcm63xx_drv_pcmcia_remove), | ||
456 | .driver = { | ||
457 | .name = "bcm63xx_pcmcia", | ||
458 | .owner = THIS_MODULE, | ||
459 | }, | ||
460 | }; | ||
461 | |||
462 | #ifdef CONFIG_CARDBUS | ||
463 | static int __devinit bcm63xx_cb_probe(struct pci_dev *dev, | ||
464 | const struct pci_device_id *id) | ||
465 | { | ||
466 | /* keep pci device */ | ||
467 | bcm63xx_cb_dev = dev; | ||
468 | return platform_driver_register(&bcm63xx_pcmcia_driver); | ||
469 | } | ||
470 | |||
471 | static void __devexit bcm63xx_cb_exit(struct pci_dev *dev) | ||
472 | { | ||
473 | platform_driver_unregister(&bcm63xx_pcmcia_driver); | ||
474 | bcm63xx_cb_dev = NULL; | ||
475 | } | ||
476 | |||
477 | static struct pci_device_id bcm63xx_cb_table[] = { | ||
478 | { | ||
479 | .vendor = PCI_VENDOR_ID_BROADCOM, | ||
480 | .device = BCM6348_CPU_ID, | ||
481 | .subvendor = PCI_VENDOR_ID_BROADCOM, | ||
482 | .subdevice = PCI_ANY_ID, | ||
483 | .class = PCI_CLASS_BRIDGE_CARDBUS << 8, | ||
484 | .class_mask = ~0, | ||
485 | }, | ||
486 | |||
487 | { | ||
488 | .vendor = PCI_VENDOR_ID_BROADCOM, | ||
489 | .device = BCM6358_CPU_ID, | ||
490 | .subvendor = PCI_VENDOR_ID_BROADCOM, | ||
491 | .subdevice = PCI_ANY_ID, | ||
492 | .class = PCI_CLASS_BRIDGE_CARDBUS << 8, | ||
493 | .class_mask = ~0, | ||
494 | }, | ||
495 | |||
496 | { }, | ||
497 | }; | ||
498 | |||
499 | MODULE_DEVICE_TABLE(pci, bcm63xx_cb_table); | ||
500 | |||
501 | static struct pci_driver bcm63xx_cardbus_driver = { | ||
502 | .name = "bcm63xx_cardbus", | ||
503 | .id_table = bcm63xx_cb_table, | ||
504 | .probe = bcm63xx_cb_probe, | ||
505 | .remove = __devexit_p(bcm63xx_cb_exit), | ||
506 | }; | ||
507 | #endif | ||
508 | |||
509 | /* | ||
510 | * if cardbus support is enabled, register our platform device after | ||
511 | * our fake cardbus bridge has been registered | ||
512 | */ | ||
513 | static int __init bcm63xx_pcmcia_init(void) | ||
514 | { | ||
515 | #ifdef CONFIG_CARDBUS | ||
516 | return pci_register_driver(&bcm63xx_cardbus_driver); | ||
517 | #else | ||
518 | return platform_driver_register(&bcm63xx_pcmcia_driver); | ||
519 | #endif | ||
520 | } | ||
521 | |||
522 | static void __exit bcm63xx_pcmcia_exit(void) | ||
523 | { | ||
524 | #ifdef CONFIG_CARDBUS | ||
525 | return pci_unregister_driver(&bcm63xx_cardbus_driver); | ||
526 | #else | ||
527 | platform_driver_unregister(&bcm63xx_pcmcia_driver); | ||
528 | #endif | ||
529 | } | ||
530 | |||
531 | module_init(bcm63xx_pcmcia_init); | ||
532 | module_exit(bcm63xx_pcmcia_exit); | ||
533 | |||
534 | MODULE_LICENSE("GPL"); | ||
535 | MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>"); | ||
536 | MODULE_DESCRIPTION("Linux PCMCIA Card Services: bcm63xx Socket Controller"); | ||
diff --git a/drivers/pcmcia/bcm63xx_pcmcia.h b/drivers/pcmcia/bcm63xx_pcmcia.h new file mode 100644 index 000000000000..ed957399d863 --- /dev/null +++ b/drivers/pcmcia/bcm63xx_pcmcia.h | |||
@@ -0,0 +1,60 @@ | |||
1 | #ifndef BCM63XX_PCMCIA_H_ | ||
2 | #define BCM63XX_PCMCIA_H_ | ||
3 | |||
4 | #include <linux/types.h> | ||
5 | #include <linux/timer.h> | ||
6 | #include <pcmcia/ss.h> | ||
7 | #include <bcm63xx_dev_pcmcia.h> | ||
8 | |||
9 | /* socket polling rate in ms */ | ||
10 | #define BCM63XX_PCMCIA_POLL_RATE 500 | ||
11 | |||
12 | enum { | ||
13 | CARD_CARDBUS = (1 << 0), | ||
14 | CARD_PCCARD = (1 << 1), | ||
15 | CARD_5V = (1 << 2), | ||
16 | CARD_3V = (1 << 3), | ||
17 | CARD_XV = (1 << 4), | ||
18 | CARD_YV = (1 << 5), | ||
19 | }; | ||
20 | |||
21 | struct bcm63xx_pcmcia_socket { | ||
22 | struct pcmcia_socket socket; | ||
23 | |||
24 | /* platform specific data */ | ||
25 | struct bcm63xx_pcmcia_platform_data *pd; | ||
26 | |||
27 | /* all regs access are protected by this spinlock */ | ||
28 | spinlock_t lock; | ||
29 | |||
30 | /* pcmcia registers resource */ | ||
31 | struct resource *reg_res; | ||
32 | |||
33 | /* base remapped address of registers */ | ||
34 | void __iomem *base; | ||
35 | |||
36 | /* whether a card is detected at the moment */ | ||
37 | int card_detected; | ||
38 | |||
39 | /* type of detected card (mask of above enum) */ | ||
40 | u8 card_type; | ||
41 | |||
42 | /* keep last socket status to implement event reporting */ | ||
43 | unsigned int old_status; | ||
44 | |||
45 | /* backup of requested socket state */ | ||
46 | socket_state_t requested_state; | ||
47 | |||
48 | /* timer used for socket status polling */ | ||
49 | struct timer_list timer; | ||
50 | |||
51 | /* attribute/common memory resources */ | ||
52 | struct resource *attr_res; | ||
53 | struct resource *common_res; | ||
54 | struct resource *io_res; | ||
55 | |||
56 | /* base address of io memory */ | ||
57 | void __iomem *io_base; | ||
58 | }; | ||
59 | |||
60 | #endif /* BCM63XX_PCMCIA_H_ */ | ||
diff --git a/drivers/pcmcia/bfin_cf_pcmcia.c b/drivers/pcmcia/bfin_cf_pcmcia.c index b59d4115d20f..300b368605c9 100644 --- a/drivers/pcmcia/bfin_cf_pcmcia.c +++ b/drivers/pcmcia/bfin_cf_pcmcia.c | |||
@@ -302,7 +302,7 @@ static int __devexit bfin_cf_remove(struct platform_device *pdev) | |||
302 | 302 | ||
303 | static int bfin_cf_suspend(struct platform_device *pdev, pm_message_t mesg) | 303 | static int bfin_cf_suspend(struct platform_device *pdev, pm_message_t mesg) |
304 | { | 304 | { |
305 | return pcmcia_socket_dev_suspend(&pdev->dev, mesg); | 305 | return pcmcia_socket_dev_suspend(&pdev->dev); |
306 | } | 306 | } |
307 | 307 | ||
308 | static int bfin_cf_resume(struct platform_device *pdev) | 308 | static int bfin_cf_resume(struct platform_device *pdev) |
diff --git a/drivers/pcmcia/cs.c b/drivers/pcmcia/cs.c index 0660ad182589..934d4bee39a0 100644 --- a/drivers/pcmcia/cs.c +++ b/drivers/pcmcia/cs.c | |||
@@ -101,7 +101,7 @@ EXPORT_SYMBOL(pcmcia_socket_list_rwsem); | |||
101 | static int socket_resume(struct pcmcia_socket *skt); | 101 | static int socket_resume(struct pcmcia_socket *skt); |
102 | static int socket_suspend(struct pcmcia_socket *skt); | 102 | static int socket_suspend(struct pcmcia_socket *skt); |
103 | 103 | ||
104 | int pcmcia_socket_dev_suspend(struct device *dev, pm_message_t state) | 104 | int pcmcia_socket_dev_suspend(struct device *dev) |
105 | { | 105 | { |
106 | struct pcmcia_socket *socket; | 106 | struct pcmcia_socket *socket; |
107 | 107 | ||
diff --git a/drivers/pcmcia/i82092.c b/drivers/pcmcia/i82092.c index 46561face128..a04f21c8170f 100644 --- a/drivers/pcmcia/i82092.c +++ b/drivers/pcmcia/i82092.c | |||
@@ -42,7 +42,7 @@ MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids); | |||
42 | #ifdef CONFIG_PM | 42 | #ifdef CONFIG_PM |
43 | static int i82092aa_socket_suspend (struct pci_dev *dev, pm_message_t state) | 43 | static int i82092aa_socket_suspend (struct pci_dev *dev, pm_message_t state) |
44 | { | 44 | { |
45 | return pcmcia_socket_dev_suspend(&dev->dev, state); | 45 | return pcmcia_socket_dev_suspend(&dev->dev); |
46 | } | 46 | } |
47 | 47 | ||
48 | static int i82092aa_socket_resume (struct pci_dev *dev) | 48 | static int i82092aa_socket_resume (struct pci_dev *dev) |
diff --git a/drivers/pcmcia/i82365.c b/drivers/pcmcia/i82365.c index 40d4953e4b12..b906abe26ad0 100644 --- a/drivers/pcmcia/i82365.c +++ b/drivers/pcmcia/i82365.c | |||
@@ -1241,7 +1241,7 @@ static int pcic_init(struct pcmcia_socket *s) | |||
1241 | static int i82365_drv_pcmcia_suspend(struct platform_device *dev, | 1241 | static int i82365_drv_pcmcia_suspend(struct platform_device *dev, |
1242 | pm_message_t state) | 1242 | pm_message_t state) |
1243 | { | 1243 | { |
1244 | return pcmcia_socket_dev_suspend(&dev->dev, state); | 1244 | return pcmcia_socket_dev_suspend(&dev->dev); |
1245 | } | 1245 | } |
1246 | 1246 | ||
1247 | static int i82365_drv_pcmcia_resume(struct platform_device *dev) | 1247 | static int i82365_drv_pcmcia_resume(struct platform_device *dev) |
diff --git a/drivers/pcmcia/m32r_cfc.c b/drivers/pcmcia/m32r_cfc.c index 62b4ecc97c46..d1d89c4491ad 100644 --- a/drivers/pcmcia/m32r_cfc.c +++ b/drivers/pcmcia/m32r_cfc.c | |||
@@ -699,7 +699,7 @@ static struct pccard_operations pcc_operations = { | |||
699 | static int cfc_drv_pcmcia_suspend(struct platform_device *dev, | 699 | static int cfc_drv_pcmcia_suspend(struct platform_device *dev, |
700 | pm_message_t state) | 700 | pm_message_t state) |
701 | { | 701 | { |
702 | return pcmcia_socket_dev_suspend(&dev->dev, state); | 702 | return pcmcia_socket_dev_suspend(&dev->dev); |
703 | } | 703 | } |
704 | 704 | ||
705 | static int cfc_drv_pcmcia_resume(struct platform_device *dev) | 705 | static int cfc_drv_pcmcia_resume(struct platform_device *dev) |
diff --git a/drivers/pcmcia/m32r_pcc.c b/drivers/pcmcia/m32r_pcc.c index 12034b41d196..a0655839c8d3 100644 --- a/drivers/pcmcia/m32r_pcc.c +++ b/drivers/pcmcia/m32r_pcc.c | |||
@@ -675,7 +675,7 @@ static struct pccard_operations pcc_operations = { | |||
675 | static int pcc_drv_pcmcia_suspend(struct platform_device *dev, | 675 | static int pcc_drv_pcmcia_suspend(struct platform_device *dev, |
676 | pm_message_t state) | 676 | pm_message_t state) |
677 | { | 677 | { |
678 | return pcmcia_socket_dev_suspend(&dev->dev, state); | 678 | return pcmcia_socket_dev_suspend(&dev->dev); |
679 | } | 679 | } |
680 | 680 | ||
681 | static int pcc_drv_pcmcia_resume(struct platform_device *dev) | 681 | static int pcc_drv_pcmcia_resume(struct platform_device *dev) |
diff --git a/drivers/pcmcia/m8xx_pcmcia.c b/drivers/pcmcia/m8xx_pcmcia.c index d1ad0966392d..c69f2c4fe520 100644 --- a/drivers/pcmcia/m8xx_pcmcia.c +++ b/drivers/pcmcia/m8xx_pcmcia.c | |||
@@ -1296,7 +1296,7 @@ static int m8xx_remove(struct of_device *ofdev) | |||
1296 | #ifdef CONFIG_PM | 1296 | #ifdef CONFIG_PM |
1297 | static int m8xx_suspend(struct platform_device *pdev, pm_message_t state) | 1297 | static int m8xx_suspend(struct platform_device *pdev, pm_message_t state) |
1298 | { | 1298 | { |
1299 | return pcmcia_socket_dev_suspend(&pdev->dev, state); | 1299 | return pcmcia_socket_dev_suspend(&pdev->dev); |
1300 | } | 1300 | } |
1301 | 1301 | ||
1302 | static int m8xx_resume(struct platform_device *pdev) | 1302 | static int m8xx_resume(struct platform_device *pdev) |
diff --git a/drivers/pcmcia/omap_cf.c b/drivers/pcmcia/omap_cf.c index f3736398900e..68570bc3ac86 100644 --- a/drivers/pcmcia/omap_cf.c +++ b/drivers/pcmcia/omap_cf.c | |||
@@ -334,7 +334,7 @@ static int __exit omap_cf_remove(struct platform_device *pdev) | |||
334 | 334 | ||
335 | static int omap_cf_suspend(struct platform_device *pdev, pm_message_t mesg) | 335 | static int omap_cf_suspend(struct platform_device *pdev, pm_message_t mesg) |
336 | { | 336 | { |
337 | return pcmcia_socket_dev_suspend(&pdev->dev, mesg); | 337 | return pcmcia_socket_dev_suspend(&pdev->dev); |
338 | } | 338 | } |
339 | 339 | ||
340 | static int omap_cf_resume(struct platform_device *pdev) | 340 | static int omap_cf_resume(struct platform_device *pdev) |
diff --git a/drivers/pcmcia/pd6729.c b/drivers/pcmcia/pd6729.c index 8bed1dab9039..1c39d3438f20 100644 --- a/drivers/pcmcia/pd6729.c +++ b/drivers/pcmcia/pd6729.c | |||
@@ -758,7 +758,7 @@ static void __devexit pd6729_pci_remove(struct pci_dev *dev) | |||
758 | #ifdef CONFIG_PM | 758 | #ifdef CONFIG_PM |
759 | static int pd6729_socket_suspend(struct pci_dev *dev, pm_message_t state) | 759 | static int pd6729_socket_suspend(struct pci_dev *dev, pm_message_t state) |
760 | { | 760 | { |
761 | return pcmcia_socket_dev_suspend(&dev->dev, state); | 761 | return pcmcia_socket_dev_suspend(&dev->dev); |
762 | } | 762 | } |
763 | 763 | ||
764 | static int pd6729_socket_resume(struct pci_dev *dev) | 764 | static int pd6729_socket_resume(struct pci_dev *dev) |
diff --git a/drivers/pcmcia/pxa2xx_base.c b/drivers/pcmcia/pxa2xx_base.c index 87e22ef8eb02..0e35acb1366b 100644 --- a/drivers/pcmcia/pxa2xx_base.c +++ b/drivers/pcmcia/pxa2xx_base.c | |||
@@ -302,7 +302,7 @@ static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev) | |||
302 | 302 | ||
303 | static int pxa2xx_drv_pcmcia_suspend(struct device *dev) | 303 | static int pxa2xx_drv_pcmcia_suspend(struct device *dev) |
304 | { | 304 | { |
305 | return pcmcia_socket_dev_suspend(dev, PMSG_SUSPEND); | 305 | return pcmcia_socket_dev_suspend(dev); |
306 | } | 306 | } |
307 | 307 | ||
308 | static int pxa2xx_drv_pcmcia_resume(struct device *dev) | 308 | static int pxa2xx_drv_pcmcia_resume(struct device *dev) |
diff --git a/drivers/pcmcia/sa1100_assabet.c b/drivers/pcmcia/sa1100_assabet.c index f424146a2bc9..ac8aa09ba0da 100644 --- a/drivers/pcmcia/sa1100_assabet.c +++ b/drivers/pcmcia/sa1100_assabet.c | |||
@@ -130,7 +130,7 @@ static struct pcmcia_low_level assabet_pcmcia_ops = { | |||
130 | .socket_suspend = assabet_pcmcia_socket_suspend, | 130 | .socket_suspend = assabet_pcmcia_socket_suspend, |
131 | }; | 131 | }; |
132 | 132 | ||
133 | int __init pcmcia_assabet_init(struct device *dev) | 133 | int pcmcia_assabet_init(struct device *dev) |
134 | { | 134 | { |
135 | int ret = -ENODEV; | 135 | int ret = -ENODEV; |
136 | 136 | ||
diff --git a/drivers/pcmcia/sa1100_generic.c b/drivers/pcmcia/sa1100_generic.c index d8da5ac844e9..2d0e99751530 100644 --- a/drivers/pcmcia/sa1100_generic.c +++ b/drivers/pcmcia/sa1100_generic.c | |||
@@ -89,7 +89,7 @@ static int sa11x0_drv_pcmcia_remove(struct platform_device *dev) | |||
89 | static int sa11x0_drv_pcmcia_suspend(struct platform_device *dev, | 89 | static int sa11x0_drv_pcmcia_suspend(struct platform_device *dev, |
90 | pm_message_t state) | 90 | pm_message_t state) |
91 | { | 91 | { |
92 | return pcmcia_socket_dev_suspend(&dev->dev, state); | 92 | return pcmcia_socket_dev_suspend(&dev->dev); |
93 | } | 93 | } |
94 | 94 | ||
95 | static int sa11x0_drv_pcmcia_resume(struct platform_device *dev) | 95 | static int sa11x0_drv_pcmcia_resume(struct platform_device *dev) |
diff --git a/drivers/pcmcia/sa1100_neponset.c b/drivers/pcmcia/sa1100_neponset.c index 4c41e86ccff9..0c76d337815b 100644 --- a/drivers/pcmcia/sa1100_neponset.c +++ b/drivers/pcmcia/sa1100_neponset.c | |||
@@ -123,7 +123,7 @@ static struct pcmcia_low_level neponset_pcmcia_ops = { | |||
123 | .socket_suspend = sa1111_pcmcia_socket_suspend, | 123 | .socket_suspend = sa1111_pcmcia_socket_suspend, |
124 | }; | 124 | }; |
125 | 125 | ||
126 | int __init pcmcia_neponset_init(struct sa1111_dev *sadev) | 126 | int pcmcia_neponset_init(struct sa1111_dev *sadev) |
127 | { | 127 | { |
128 | int ret = -ENODEV; | 128 | int ret = -ENODEV; |
129 | 129 | ||
diff --git a/drivers/pcmcia/sa1111_generic.c b/drivers/pcmcia/sa1111_generic.c index 401052a21ce8..4be4e172ffa1 100644 --- a/drivers/pcmcia/sa1111_generic.c +++ b/drivers/pcmcia/sa1111_generic.c | |||
@@ -159,7 +159,7 @@ static int __devexit pcmcia_remove(struct sa1111_dev *dev) | |||
159 | 159 | ||
160 | static int pcmcia_suspend(struct sa1111_dev *dev, pm_message_t state) | 160 | static int pcmcia_suspend(struct sa1111_dev *dev, pm_message_t state) |
161 | { | 161 | { |
162 | return pcmcia_socket_dev_suspend(&dev->dev, state); | 162 | return pcmcia_socket_dev_suspend(&dev->dev); |
163 | } | 163 | } |
164 | 164 | ||
165 | static int pcmcia_resume(struct sa1111_dev *dev) | 165 | static int pcmcia_resume(struct sa1111_dev *dev) |
diff --git a/drivers/pcmcia/tcic.c b/drivers/pcmcia/tcic.c index 8eb04230fec7..582413fcb62f 100644 --- a/drivers/pcmcia/tcic.c +++ b/drivers/pcmcia/tcic.c | |||
@@ -366,7 +366,7 @@ static int __init get_tcic_id(void) | |||
366 | static int tcic_drv_pcmcia_suspend(struct platform_device *dev, | 366 | static int tcic_drv_pcmcia_suspend(struct platform_device *dev, |
367 | pm_message_t state) | 367 | pm_message_t state) |
368 | { | 368 | { |
369 | return pcmcia_socket_dev_suspend(&dev->dev, state); | 369 | return pcmcia_socket_dev_suspend(&dev->dev); |
370 | } | 370 | } |
371 | 371 | ||
372 | static int tcic_drv_pcmcia_resume(struct platform_device *dev) | 372 | static int tcic_drv_pcmcia_resume(struct platform_device *dev) |
diff --git a/drivers/pcmcia/vrc4171_card.c b/drivers/pcmcia/vrc4171_card.c index d4ad50d737b0..c9fcbdc164ea 100644 --- a/drivers/pcmcia/vrc4171_card.c +++ b/drivers/pcmcia/vrc4171_card.c | |||
@@ -707,7 +707,7 @@ __setup("vrc4171_card=", vrc4171_card_setup); | |||
707 | static int vrc4171_card_suspend(struct platform_device *dev, | 707 | static int vrc4171_card_suspend(struct platform_device *dev, |
708 | pm_message_t state) | 708 | pm_message_t state) |
709 | { | 709 | { |
710 | return pcmcia_socket_dev_suspend(&dev->dev, state); | 710 | return pcmcia_socket_dev_suspend(&dev->dev); |
711 | } | 711 | } |
712 | 712 | ||
713 | static int vrc4171_card_resume(struct platform_device *dev) | 713 | static int vrc4171_card_resume(struct platform_device *dev) |
diff --git a/drivers/pcmcia/yenta_socket.c b/drivers/pcmcia/yenta_socket.c index b459e87a30ac..abe0e44c6e9e 100644 --- a/drivers/pcmcia/yenta_socket.c +++ b/drivers/pcmcia/yenta_socket.c | |||
@@ -1225,60 +1225,71 @@ static int __devinit yenta_probe (struct pci_dev *dev, const struct pci_device_i | |||
1225 | } | 1225 | } |
1226 | 1226 | ||
1227 | #ifdef CONFIG_PM | 1227 | #ifdef CONFIG_PM |
1228 | static int yenta_dev_suspend (struct pci_dev *dev, pm_message_t state) | 1228 | static int yenta_dev_suspend_noirq(struct device *dev) |
1229 | { | 1229 | { |
1230 | struct yenta_socket *socket = pci_get_drvdata(dev); | 1230 | struct pci_dev *pdev = to_pci_dev(dev); |
1231 | struct yenta_socket *socket = pci_get_drvdata(pdev); | ||
1231 | int ret; | 1232 | int ret; |
1232 | 1233 | ||
1233 | ret = pcmcia_socket_dev_suspend(&dev->dev, state); | 1234 | ret = pcmcia_socket_dev_suspend(dev); |
1234 | 1235 | ||
1235 | if (socket) { | 1236 | if (!socket) |
1236 | if (socket->type && socket->type->save_state) | 1237 | return ret; |
1237 | socket->type->save_state(socket); | ||
1238 | 1238 | ||
1239 | /* FIXME: pci_save_state needs to have a better interface */ | 1239 | if (socket->type && socket->type->save_state) |
1240 | pci_save_state(dev); | 1240 | socket->type->save_state(socket); |
1241 | pci_read_config_dword(dev, 16*4, &socket->saved_state[0]); | ||
1242 | pci_read_config_dword(dev, 17*4, &socket->saved_state[1]); | ||
1243 | pci_disable_device(dev); | ||
1244 | 1241 | ||
1245 | /* | 1242 | pci_save_state(pdev); |
1246 | * Some laptops (IBM T22) do not like us putting the Cardbus | 1243 | pci_read_config_dword(pdev, 16*4, &socket->saved_state[0]); |
1247 | * bridge into D3. At a guess, some other laptop will | 1244 | pci_read_config_dword(pdev, 17*4, &socket->saved_state[1]); |
1248 | * probably require this, so leave it commented out for now. | 1245 | pci_disable_device(pdev); |
1249 | */ | 1246 | |
1250 | /* pci_set_power_state(dev, 3); */ | 1247 | /* |
1251 | } | 1248 | * Some laptops (IBM T22) do not like us putting the Cardbus |
1249 | * bridge into D3. At a guess, some other laptop will | ||
1250 | * probably require this, so leave it commented out for now. | ||
1251 | */ | ||
1252 | /* pci_set_power_state(dev, 3); */ | ||
1252 | 1253 | ||
1253 | return ret; | 1254 | return ret; |
1254 | } | 1255 | } |
1255 | 1256 | ||
1256 | 1257 | static int yenta_dev_resume_noirq(struct device *dev) | |
1257 | static int yenta_dev_resume (struct pci_dev *dev) | ||
1258 | { | 1258 | { |
1259 | struct yenta_socket *socket = pci_get_drvdata(dev); | 1259 | struct pci_dev *pdev = to_pci_dev(dev); |
1260 | struct yenta_socket *socket = pci_get_drvdata(pdev); | ||
1261 | int ret; | ||
1260 | 1262 | ||
1261 | if (socket) { | 1263 | if (!socket) |
1262 | int rc; | 1264 | return 0; |
1263 | 1265 | ||
1264 | pci_set_power_state(dev, 0); | 1266 | pci_write_config_dword(pdev, 16*4, socket->saved_state[0]); |
1265 | /* FIXME: pci_restore_state needs to have a better interface */ | 1267 | pci_write_config_dword(pdev, 17*4, socket->saved_state[1]); |
1266 | pci_restore_state(dev); | ||
1267 | pci_write_config_dword(dev, 16*4, socket->saved_state[0]); | ||
1268 | pci_write_config_dword(dev, 17*4, socket->saved_state[1]); | ||
1269 | 1268 | ||
1270 | rc = pci_enable_device(dev); | 1269 | ret = pci_enable_device(pdev); |
1271 | if (rc) | 1270 | if (ret) |
1272 | return rc; | 1271 | return ret; |
1273 | 1272 | ||
1274 | pci_set_master(dev); | 1273 | pci_set_master(pdev); |
1275 | 1274 | ||
1276 | if (socket->type && socket->type->restore_state) | 1275 | if (socket->type && socket->type->restore_state) |
1277 | socket->type->restore_state(socket); | 1276 | socket->type->restore_state(socket); |
1278 | } | ||
1279 | 1277 | ||
1280 | return pcmcia_socket_dev_resume(&dev->dev); | 1278 | return pcmcia_socket_dev_resume(dev); |
1281 | } | 1279 | } |
1280 | |||
1281 | static struct dev_pm_ops yenta_pm_ops = { | ||
1282 | .suspend_noirq = yenta_dev_suspend_noirq, | ||
1283 | .resume_noirq = yenta_dev_resume_noirq, | ||
1284 | .freeze_noirq = yenta_dev_suspend_noirq, | ||
1285 | .thaw_noirq = yenta_dev_resume_noirq, | ||
1286 | .poweroff_noirq = yenta_dev_suspend_noirq, | ||
1287 | .restore_noirq = yenta_dev_resume_noirq, | ||
1288 | }; | ||
1289 | |||
1290 | #define YENTA_PM_OPS (¥ta_pm_ops) | ||
1291 | #else | ||
1292 | #define YENTA_PM_OPS NULL | ||
1282 | #endif | 1293 | #endif |
1283 | 1294 | ||
1284 | #define CB_ID(vend,dev,type) \ | 1295 | #define CB_ID(vend,dev,type) \ |
@@ -1376,10 +1387,7 @@ static struct pci_driver yenta_cardbus_driver = { | |||
1376 | .id_table = yenta_table, | 1387 | .id_table = yenta_table, |
1377 | .probe = yenta_probe, | 1388 | .probe = yenta_probe, |
1378 | .remove = __devexit_p(yenta_close), | 1389 | .remove = __devexit_p(yenta_close), |
1379 | #ifdef CONFIG_PM | 1390 | .driver.pm = YENTA_PM_OPS, |
1380 | .suspend = yenta_dev_suspend, | ||
1381 | .resume = yenta_dev_resume, | ||
1382 | #endif | ||
1383 | }; | 1391 | }; |
1384 | 1392 | ||
1385 | 1393 | ||
diff --git a/drivers/platform/x86/sony-laptop.c b/drivers/platform/x86/sony-laptop.c index f9f68e0e7344..afdbdaaf80cb 100644 --- a/drivers/platform/x86/sony-laptop.c +++ b/drivers/platform/x86/sony-laptop.c | |||
@@ -1041,6 +1041,9 @@ static int sony_nc_resume(struct acpi_device *device) | |||
1041 | sony_backlight_update_status(sony_backlight_device) < 0) | 1041 | sony_backlight_update_status(sony_backlight_device) < 0) |
1042 | printk(KERN_WARNING DRV_PFX "unable to restore brightness level\n"); | 1042 | printk(KERN_WARNING DRV_PFX "unable to restore brightness level\n"); |
1043 | 1043 | ||
1044 | /* re-read rfkill state */ | ||
1045 | sony_nc_rfkill_update(); | ||
1046 | |||
1044 | return 0; | 1047 | return 0; |
1045 | } | 1048 | } |
1046 | 1049 | ||
@@ -1078,6 +1081,8 @@ static int sony_nc_setup_rfkill(struct acpi_device *device, | |||
1078 | struct rfkill *rfk; | 1081 | struct rfkill *rfk; |
1079 | enum rfkill_type type; | 1082 | enum rfkill_type type; |
1080 | const char *name; | 1083 | const char *name; |
1084 | int result; | ||
1085 | bool hwblock; | ||
1081 | 1086 | ||
1082 | switch (nc_type) { | 1087 | switch (nc_type) { |
1083 | case SONY_WIFI: | 1088 | case SONY_WIFI: |
@@ -1105,6 +1110,10 @@ static int sony_nc_setup_rfkill(struct acpi_device *device, | |||
1105 | if (!rfk) | 1110 | if (!rfk) |
1106 | return -ENOMEM; | 1111 | return -ENOMEM; |
1107 | 1112 | ||
1113 | sony_call_snc_handle(0x124, 0x200, &result); | ||
1114 | hwblock = !(result & 0x1); | ||
1115 | rfkill_set_hw_state(rfk, hwblock); | ||
1116 | |||
1108 | err = rfkill_register(rfk); | 1117 | err = rfkill_register(rfk); |
1109 | if (err) { | 1118 | if (err) { |
1110 | rfkill_destroy(rfk); | 1119 | rfkill_destroy(rfk); |
diff --git a/drivers/s390/cio/qdio_debug.c b/drivers/s390/cio/qdio_debug.c index 1b78f639ead3..76769978285f 100644 --- a/drivers/s390/cio/qdio_debug.c +++ b/drivers/s390/cio/qdio_debug.c | |||
@@ -125,7 +125,7 @@ static int qstat_seq_open(struct inode *inode, struct file *filp) | |||
125 | filp->f_path.dentry->d_inode->i_private); | 125 | filp->f_path.dentry->d_inode->i_private); |
126 | } | 126 | } |
127 | 127 | ||
128 | static struct file_operations debugfs_fops = { | 128 | static const struct file_operations debugfs_fops = { |
129 | .owner = THIS_MODULE, | 129 | .owner = THIS_MODULE, |
130 | .open = qstat_seq_open, | 130 | .open = qstat_seq_open, |
131 | .read = seq_read, | 131 | .read = seq_read, |
diff --git a/drivers/s390/cio/qdio_perf.c b/drivers/s390/cio/qdio_perf.c index eff943923c6f..968e3c7c2632 100644 --- a/drivers/s390/cio/qdio_perf.c +++ b/drivers/s390/cio/qdio_perf.c | |||
@@ -84,7 +84,7 @@ static int qdio_perf_seq_open(struct inode *inode, struct file *filp) | |||
84 | return single_open(filp, qdio_perf_proc_show, NULL); | 84 | return single_open(filp, qdio_perf_proc_show, NULL); |
85 | } | 85 | } |
86 | 86 | ||
87 | static struct file_operations qdio_perf_proc_fops = { | 87 | static const struct file_operations qdio_perf_proc_fops = { |
88 | .owner = THIS_MODULE, | 88 | .owner = THIS_MODULE, |
89 | .open = qdio_perf_seq_open, | 89 | .open = qdio_perf_seq_open, |
90 | .read = seq_read, | 90 | .read = seq_read, |
diff --git a/drivers/scsi/sg.c b/drivers/scsi/sg.c index 0cb049f5cc56..747a5e5c1276 100644 --- a/drivers/scsi/sg.c +++ b/drivers/scsi/sg.c | |||
@@ -1317,7 +1317,7 @@ static void sg_rq_end_io(struct request *rq, int uptodate) | |||
1317 | } | 1317 | } |
1318 | } | 1318 | } |
1319 | 1319 | ||
1320 | static struct file_operations sg_fops = { | 1320 | static const struct file_operations sg_fops = { |
1321 | .owner = THIS_MODULE, | 1321 | .owner = THIS_MODULE, |
1322 | .read = sg_read, | 1322 | .read = sg_read, |
1323 | .write = sg_write, | 1323 | .write = sg_write, |
@@ -2194,9 +2194,11 @@ static int sg_proc_seq_show_int(struct seq_file *s, void *v); | |||
2194 | static int sg_proc_single_open_adio(struct inode *inode, struct file *file); | 2194 | static int sg_proc_single_open_adio(struct inode *inode, struct file *file); |
2195 | static ssize_t sg_proc_write_adio(struct file *filp, const char __user *buffer, | 2195 | static ssize_t sg_proc_write_adio(struct file *filp, const char __user *buffer, |
2196 | size_t count, loff_t *off); | 2196 | size_t count, loff_t *off); |
2197 | static struct file_operations adio_fops = { | 2197 | static const struct file_operations adio_fops = { |
2198 | /* .owner, .read and .llseek added in sg_proc_init() */ | 2198 | .owner = THIS_MODULE, |
2199 | .open = sg_proc_single_open_adio, | 2199 | .open = sg_proc_single_open_adio, |
2200 | .read = seq_read, | ||
2201 | .llseek = seq_lseek, | ||
2200 | .write = sg_proc_write_adio, | 2202 | .write = sg_proc_write_adio, |
2201 | .release = single_release, | 2203 | .release = single_release, |
2202 | }; | 2204 | }; |
@@ -2204,23 +2206,32 @@ static struct file_operations adio_fops = { | |||
2204 | static int sg_proc_single_open_dressz(struct inode *inode, struct file *file); | 2206 | static int sg_proc_single_open_dressz(struct inode *inode, struct file *file); |
2205 | static ssize_t sg_proc_write_dressz(struct file *filp, | 2207 | static ssize_t sg_proc_write_dressz(struct file *filp, |
2206 | const char __user *buffer, size_t count, loff_t *off); | 2208 | const char __user *buffer, size_t count, loff_t *off); |
2207 | static struct file_operations dressz_fops = { | 2209 | static const struct file_operations dressz_fops = { |
2210 | .owner = THIS_MODULE, | ||
2208 | .open = sg_proc_single_open_dressz, | 2211 | .open = sg_proc_single_open_dressz, |
2212 | .read = seq_read, | ||
2213 | .llseek = seq_lseek, | ||
2209 | .write = sg_proc_write_dressz, | 2214 | .write = sg_proc_write_dressz, |
2210 | .release = single_release, | 2215 | .release = single_release, |
2211 | }; | 2216 | }; |
2212 | 2217 | ||
2213 | static int sg_proc_seq_show_version(struct seq_file *s, void *v); | 2218 | static int sg_proc_seq_show_version(struct seq_file *s, void *v); |
2214 | static int sg_proc_single_open_version(struct inode *inode, struct file *file); | 2219 | static int sg_proc_single_open_version(struct inode *inode, struct file *file); |
2215 | static struct file_operations version_fops = { | 2220 | static const struct file_operations version_fops = { |
2221 | .owner = THIS_MODULE, | ||
2216 | .open = sg_proc_single_open_version, | 2222 | .open = sg_proc_single_open_version, |
2223 | .read = seq_read, | ||
2224 | .llseek = seq_lseek, | ||
2217 | .release = single_release, | 2225 | .release = single_release, |
2218 | }; | 2226 | }; |
2219 | 2227 | ||
2220 | static int sg_proc_seq_show_devhdr(struct seq_file *s, void *v); | 2228 | static int sg_proc_seq_show_devhdr(struct seq_file *s, void *v); |
2221 | static int sg_proc_single_open_devhdr(struct inode *inode, struct file *file); | 2229 | static int sg_proc_single_open_devhdr(struct inode *inode, struct file *file); |
2222 | static struct file_operations devhdr_fops = { | 2230 | static const struct file_operations devhdr_fops = { |
2231 | .owner = THIS_MODULE, | ||
2223 | .open = sg_proc_single_open_devhdr, | 2232 | .open = sg_proc_single_open_devhdr, |
2233 | .read = seq_read, | ||
2234 | .llseek = seq_lseek, | ||
2224 | .release = single_release, | 2235 | .release = single_release, |
2225 | }; | 2236 | }; |
2226 | 2237 | ||
@@ -2229,8 +2240,11 @@ static int sg_proc_open_dev(struct inode *inode, struct file *file); | |||
2229 | static void * dev_seq_start(struct seq_file *s, loff_t *pos); | 2240 | static void * dev_seq_start(struct seq_file *s, loff_t *pos); |
2230 | static void * dev_seq_next(struct seq_file *s, void *v, loff_t *pos); | 2241 | static void * dev_seq_next(struct seq_file *s, void *v, loff_t *pos); |
2231 | static void dev_seq_stop(struct seq_file *s, void *v); | 2242 | static void dev_seq_stop(struct seq_file *s, void *v); |
2232 | static struct file_operations dev_fops = { | 2243 | static const struct file_operations dev_fops = { |
2244 | .owner = THIS_MODULE, | ||
2233 | .open = sg_proc_open_dev, | 2245 | .open = sg_proc_open_dev, |
2246 | .read = seq_read, | ||
2247 | .llseek = seq_lseek, | ||
2234 | .release = seq_release, | 2248 | .release = seq_release, |
2235 | }; | 2249 | }; |
2236 | static const struct seq_operations dev_seq_ops = { | 2250 | static const struct seq_operations dev_seq_ops = { |
@@ -2242,8 +2256,11 @@ static const struct seq_operations dev_seq_ops = { | |||
2242 | 2256 | ||
2243 | static int sg_proc_seq_show_devstrs(struct seq_file *s, void *v); | 2257 | static int sg_proc_seq_show_devstrs(struct seq_file *s, void *v); |
2244 | static int sg_proc_open_devstrs(struct inode *inode, struct file *file); | 2258 | static int sg_proc_open_devstrs(struct inode *inode, struct file *file); |
2245 | static struct file_operations devstrs_fops = { | 2259 | static const struct file_operations devstrs_fops = { |
2260 | .owner = THIS_MODULE, | ||
2246 | .open = sg_proc_open_devstrs, | 2261 | .open = sg_proc_open_devstrs, |
2262 | .read = seq_read, | ||
2263 | .llseek = seq_lseek, | ||
2247 | .release = seq_release, | 2264 | .release = seq_release, |
2248 | }; | 2265 | }; |
2249 | static const struct seq_operations devstrs_seq_ops = { | 2266 | static const struct seq_operations devstrs_seq_ops = { |
@@ -2255,8 +2272,11 @@ static const struct seq_operations devstrs_seq_ops = { | |||
2255 | 2272 | ||
2256 | static int sg_proc_seq_show_debug(struct seq_file *s, void *v); | 2273 | static int sg_proc_seq_show_debug(struct seq_file *s, void *v); |
2257 | static int sg_proc_open_debug(struct inode *inode, struct file *file); | 2274 | static int sg_proc_open_debug(struct inode *inode, struct file *file); |
2258 | static struct file_operations debug_fops = { | 2275 | static const struct file_operations debug_fops = { |
2276 | .owner = THIS_MODULE, | ||
2259 | .open = sg_proc_open_debug, | 2277 | .open = sg_proc_open_debug, |
2278 | .read = seq_read, | ||
2279 | .llseek = seq_lseek, | ||
2260 | .release = seq_release, | 2280 | .release = seq_release, |
2261 | }; | 2281 | }; |
2262 | static const struct seq_operations debug_seq_ops = { | 2282 | static const struct seq_operations debug_seq_ops = { |
@@ -2269,7 +2289,7 @@ static const struct seq_operations debug_seq_ops = { | |||
2269 | 2289 | ||
2270 | struct sg_proc_leaf { | 2290 | struct sg_proc_leaf { |
2271 | const char * name; | 2291 | const char * name; |
2272 | struct file_operations * fops; | 2292 | const struct file_operations * fops; |
2273 | }; | 2293 | }; |
2274 | 2294 | ||
2275 | static struct sg_proc_leaf sg_proc_leaf_arr[] = { | 2295 | static struct sg_proc_leaf sg_proc_leaf_arr[] = { |
@@ -2295,9 +2315,6 @@ sg_proc_init(void) | |||
2295 | for (k = 0; k < num_leaves; ++k) { | 2315 | for (k = 0; k < num_leaves; ++k) { |
2296 | leaf = &sg_proc_leaf_arr[k]; | 2316 | leaf = &sg_proc_leaf_arr[k]; |
2297 | mask = leaf->fops->write ? S_IRUGO | S_IWUSR : S_IRUGO; | 2317 | mask = leaf->fops->write ? S_IRUGO | S_IWUSR : S_IRUGO; |
2298 | leaf->fops->owner = THIS_MODULE; | ||
2299 | leaf->fops->read = seq_read; | ||
2300 | leaf->fops->llseek = seq_lseek; | ||
2301 | proc_create(leaf->name, mask, sg_proc_sgp, leaf->fops); | 2318 | proc_create(leaf->name, mask, sg_proc_sgp, leaf->fops); |
2302 | } | 2319 | } |
2303 | return 0; | 2320 | return 0; |
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c index 2209620d2349..b1ae774016f1 100644 --- a/drivers/serial/8250.c +++ b/drivers/serial/8250.c | |||
@@ -64,6 +64,8 @@ static int serial_index(struct uart_port *port) | |||
64 | return (serial8250_reg.minor - 64) + port->line; | 64 | return (serial8250_reg.minor - 64) + port->line; |
65 | } | 65 | } |
66 | 66 | ||
67 | static unsigned int skip_txen_test; /* force skip of txen test at init time */ | ||
68 | |||
67 | /* | 69 | /* |
68 | * Debugging. | 70 | * Debugging. |
69 | */ | 71 | */ |
@@ -2108,7 +2110,7 @@ static int serial8250_startup(struct uart_port *port) | |||
2108 | is variable. So, let's just don't test if we receive | 2110 | is variable. So, let's just don't test if we receive |
2109 | TX irq. This way, we'll never enable UART_BUG_TXEN. | 2111 | TX irq. This way, we'll never enable UART_BUG_TXEN. |
2110 | */ | 2112 | */ |
2111 | if (up->port.flags & UPF_NO_TXEN_TEST) | 2113 | if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST) |
2112 | goto dont_test_tx_en; | 2114 | goto dont_test_tx_en; |
2113 | 2115 | ||
2114 | /* | 2116 | /* |
@@ -3248,6 +3250,9 @@ MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices" | |||
3248 | module_param(nr_uarts, uint, 0644); | 3250 | module_param(nr_uarts, uint, 0644); |
3249 | MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")"); | 3251 | MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")"); |
3250 | 3252 | ||
3253 | module_param(skip_txen_test, uint, 0644); | ||
3254 | MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time"); | ||
3255 | |||
3251 | #ifdef CONFIG_SERIAL_8250_RSA | 3256 | #ifdef CONFIG_SERIAL_8250_RSA |
3252 | module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444); | 3257 | module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444); |
3253 | MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA"); | 3258 | MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA"); |
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 03422ce878cf..e52257257279 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig | |||
@@ -862,7 +862,7 @@ config SERIAL_IMX_CONSOLE | |||
862 | 862 | ||
863 | config SERIAL_UARTLITE | 863 | config SERIAL_UARTLITE |
864 | tristate "Xilinx uartlite serial port support" | 864 | tristate "Xilinx uartlite serial port support" |
865 | depends on PPC32 || MICROBLAZE | 865 | depends on PPC32 || MICROBLAZE || MFD_TIMBERDALE |
866 | select SERIAL_CORE | 866 | select SERIAL_CORE |
867 | help | 867 | help |
868 | Say Y here if you want to use the Xilinx uartlite serial controller. | 868 | Say Y here if you want to use the Xilinx uartlite serial controller. |
@@ -1458,4 +1458,23 @@ config SERIAL_TIMBERDALE | |||
1458 | ---help--- | 1458 | ---help--- |
1459 | Add support for UART controller on timberdale. | 1459 | Add support for UART controller on timberdale. |
1460 | 1460 | ||
1461 | config SERIAL_BCM63XX | ||
1462 | tristate "bcm63xx serial port support" | ||
1463 | select SERIAL_CORE | ||
1464 | depends on BCM63XX | ||
1465 | help | ||
1466 | If you have a bcm63xx CPU, you can enable its onboard | ||
1467 | serial port by enabling this options. | ||
1468 | |||
1469 | To compile this driver as a module, choose M here: the | ||
1470 | module will be called bcm963xx_uart. | ||
1471 | |||
1472 | config SERIAL_BCM63XX_CONSOLE | ||
1473 | bool "Console on bcm63xx serial port" | ||
1474 | depends on SERIAL_BCM63XX=y | ||
1475 | select SERIAL_CORE_CONSOLE | ||
1476 | help | ||
1477 | If you have enabled the serial port on the bcm63xx CPU | ||
1478 | you can make it the console by answering Y to this option. | ||
1479 | |||
1461 | endmenu | 1480 | endmenu |
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 97f6fcc8b432..d21d5dd5d048 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile | |||
@@ -34,6 +34,7 @@ obj-$(CONFIG_SERIAL_CLPS711X) += clps711x.o | |||
34 | obj-$(CONFIG_SERIAL_PXA) += pxa.o | 34 | obj-$(CONFIG_SERIAL_PXA) += pxa.o |
35 | obj-$(CONFIG_SERIAL_PNX8XXX) += pnx8xxx_uart.o | 35 | obj-$(CONFIG_SERIAL_PNX8XXX) += pnx8xxx_uart.o |
36 | obj-$(CONFIG_SERIAL_SA1100) += sa1100.o | 36 | obj-$(CONFIG_SERIAL_SA1100) += sa1100.o |
37 | obj-$(CONFIG_SERIAL_BCM63XX) += bcm63xx_uart.o | ||
37 | obj-$(CONFIG_SERIAL_BFIN) += bfin_5xx.o | 38 | obj-$(CONFIG_SERIAL_BFIN) += bfin_5xx.o |
38 | obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o | 39 | obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o |
39 | obj-$(CONFIG_SERIAL_SAMSUNG) += samsung.o | 40 | obj-$(CONFIG_SERIAL_SAMSUNG) += samsung.o |
diff --git a/drivers/serial/bcm63xx_uart.c b/drivers/serial/bcm63xx_uart.c new file mode 100644 index 000000000000..beddaa6e9069 --- /dev/null +++ b/drivers/serial/bcm63xx_uart.c | |||
@@ -0,0 +1,890 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Derived from many drivers using generic_serial interface. | ||
7 | * | ||
8 | * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> | ||
9 | * | ||
10 | * Serial driver for BCM63xx integrated UART. | ||
11 | * | ||
12 | * Hardware flow control was _not_ tested since I only have RX/TX on | ||
13 | * my board. | ||
14 | */ | ||
15 | |||
16 | #if defined(CONFIG_SERIAL_BCM63XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | ||
17 | #define SUPPORT_SYSRQ | ||
18 | #endif | ||
19 | |||
20 | #include <linux/kernel.h> | ||
21 | #include <linux/platform_device.h> | ||
22 | #include <linux/init.h> | ||
23 | #include <linux/delay.h> | ||
24 | #include <linux/module.h> | ||
25 | #include <linux/console.h> | ||
26 | #include <linux/clk.h> | ||
27 | #include <linux/tty.h> | ||
28 | #include <linux/tty_flip.h> | ||
29 | #include <linux/sysrq.h> | ||
30 | #include <linux/serial.h> | ||
31 | #include <linux/serial_core.h> | ||
32 | |||
33 | #include <bcm63xx_clk.h> | ||
34 | #include <bcm63xx_irq.h> | ||
35 | #include <bcm63xx_regs.h> | ||
36 | #include <bcm63xx_io.h> | ||
37 | |||
38 | #define BCM63XX_NR_UARTS 1 | ||
39 | |||
40 | static struct uart_port ports[BCM63XX_NR_UARTS]; | ||
41 | |||
42 | /* | ||
43 | * rx interrupt mask / stat | ||
44 | * | ||
45 | * mask: | ||
46 | * - rx fifo full | ||
47 | * - rx fifo above threshold | ||
48 | * - rx fifo not empty for too long | ||
49 | */ | ||
50 | #define UART_RX_INT_MASK (UART_IR_MASK(UART_IR_RXOVER) | \ | ||
51 | UART_IR_MASK(UART_IR_RXTHRESH) | \ | ||
52 | UART_IR_MASK(UART_IR_RXTIMEOUT)) | ||
53 | |||
54 | #define UART_RX_INT_STAT (UART_IR_STAT(UART_IR_RXOVER) | \ | ||
55 | UART_IR_STAT(UART_IR_RXTHRESH) | \ | ||
56 | UART_IR_STAT(UART_IR_RXTIMEOUT)) | ||
57 | |||
58 | /* | ||
59 | * tx interrupt mask / stat | ||
60 | * | ||
61 | * mask: | ||
62 | * - tx fifo empty | ||
63 | * - tx fifo below threshold | ||
64 | */ | ||
65 | #define UART_TX_INT_MASK (UART_IR_MASK(UART_IR_TXEMPTY) | \ | ||
66 | UART_IR_MASK(UART_IR_TXTRESH)) | ||
67 | |||
68 | #define UART_TX_INT_STAT (UART_IR_STAT(UART_IR_TXEMPTY) | \ | ||
69 | UART_IR_STAT(UART_IR_TXTRESH)) | ||
70 | |||
71 | /* | ||
72 | * external input interrupt | ||
73 | * | ||
74 | * mask: any edge on CTS, DCD | ||
75 | */ | ||
76 | #define UART_EXTINP_INT_MASK (UART_EXTINP_IRMASK(UART_EXTINP_IR_CTS) | \ | ||
77 | UART_EXTINP_IRMASK(UART_EXTINP_IR_DCD)) | ||
78 | |||
79 | /* | ||
80 | * handy uart register accessor | ||
81 | */ | ||
82 | static inline unsigned int bcm_uart_readl(struct uart_port *port, | ||
83 | unsigned int offset) | ||
84 | { | ||
85 | return bcm_readl(port->membase + offset); | ||
86 | } | ||
87 | |||
88 | static inline void bcm_uart_writel(struct uart_port *port, | ||
89 | unsigned int value, unsigned int offset) | ||
90 | { | ||
91 | bcm_writel(value, port->membase + offset); | ||
92 | } | ||
93 | |||
94 | /* | ||
95 | * serial core request to check if uart tx fifo is empty | ||
96 | */ | ||
97 | static unsigned int bcm_uart_tx_empty(struct uart_port *port) | ||
98 | { | ||
99 | unsigned int val; | ||
100 | |||
101 | val = bcm_uart_readl(port, UART_IR_REG); | ||
102 | return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0; | ||
103 | } | ||
104 | |||
105 | /* | ||
106 | * serial core request to set RTS and DTR pin state and loopback mode | ||
107 | */ | ||
108 | static void bcm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) | ||
109 | { | ||
110 | unsigned int val; | ||
111 | |||
112 | val = bcm_uart_readl(port, UART_MCTL_REG); | ||
113 | val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK); | ||
114 | /* invert of written value is reflected on the pin */ | ||
115 | if (!(mctrl & TIOCM_DTR)) | ||
116 | val |= UART_MCTL_DTR_MASK; | ||
117 | if (!(mctrl & TIOCM_RTS)) | ||
118 | val |= UART_MCTL_RTS_MASK; | ||
119 | bcm_uart_writel(port, val, UART_MCTL_REG); | ||
120 | |||
121 | val = bcm_uart_readl(port, UART_CTL_REG); | ||
122 | if (mctrl & TIOCM_LOOP) | ||
123 | val |= UART_CTL_LOOPBACK_MASK; | ||
124 | else | ||
125 | val &= ~UART_CTL_LOOPBACK_MASK; | ||
126 | bcm_uart_writel(port, val, UART_CTL_REG); | ||
127 | } | ||
128 | |||
129 | /* | ||
130 | * serial core request to return RI, CTS, DCD and DSR pin state | ||
131 | */ | ||
132 | static unsigned int bcm_uart_get_mctrl(struct uart_port *port) | ||
133 | { | ||
134 | unsigned int val, mctrl; | ||
135 | |||
136 | mctrl = 0; | ||
137 | val = bcm_uart_readl(port, UART_EXTINP_REG); | ||
138 | if (val & UART_EXTINP_RI_MASK) | ||
139 | mctrl |= TIOCM_RI; | ||
140 | if (val & UART_EXTINP_CTS_MASK) | ||
141 | mctrl |= TIOCM_CTS; | ||
142 | if (val & UART_EXTINP_DCD_MASK) | ||
143 | mctrl |= TIOCM_CD; | ||
144 | if (val & UART_EXTINP_DSR_MASK) | ||
145 | mctrl |= TIOCM_DSR; | ||
146 | return mctrl; | ||
147 | } | ||
148 | |||
149 | /* | ||
150 | * serial core request to disable tx ASAP (used for flow control) | ||
151 | */ | ||
152 | static void bcm_uart_stop_tx(struct uart_port *port) | ||
153 | { | ||
154 | unsigned int val; | ||
155 | |||
156 | val = bcm_uart_readl(port, UART_CTL_REG); | ||
157 | val &= ~(UART_CTL_TXEN_MASK); | ||
158 | bcm_uart_writel(port, val, UART_CTL_REG); | ||
159 | |||
160 | val = bcm_uart_readl(port, UART_IR_REG); | ||
161 | val &= ~UART_TX_INT_MASK; | ||
162 | bcm_uart_writel(port, val, UART_IR_REG); | ||
163 | } | ||
164 | |||
165 | /* | ||
166 | * serial core request to (re)enable tx | ||
167 | */ | ||
168 | static void bcm_uart_start_tx(struct uart_port *port) | ||
169 | { | ||
170 | unsigned int val; | ||
171 | |||
172 | val = bcm_uart_readl(port, UART_IR_REG); | ||
173 | val |= UART_TX_INT_MASK; | ||
174 | bcm_uart_writel(port, val, UART_IR_REG); | ||
175 | |||
176 | val = bcm_uart_readl(port, UART_CTL_REG); | ||
177 | val |= UART_CTL_TXEN_MASK; | ||
178 | bcm_uart_writel(port, val, UART_CTL_REG); | ||
179 | } | ||
180 | |||
181 | /* | ||
182 | * serial core request to stop rx, called before port shutdown | ||
183 | */ | ||
184 | static void bcm_uart_stop_rx(struct uart_port *port) | ||
185 | { | ||
186 | unsigned int val; | ||
187 | |||
188 | val = bcm_uart_readl(port, UART_IR_REG); | ||
189 | val &= ~UART_RX_INT_MASK; | ||
190 | bcm_uart_writel(port, val, UART_IR_REG); | ||
191 | } | ||
192 | |||
193 | /* | ||
194 | * serial core request to enable modem status interrupt reporting | ||
195 | */ | ||
196 | static void bcm_uart_enable_ms(struct uart_port *port) | ||
197 | { | ||
198 | unsigned int val; | ||
199 | |||
200 | val = bcm_uart_readl(port, UART_IR_REG); | ||
201 | val |= UART_IR_MASK(UART_IR_EXTIP); | ||
202 | bcm_uart_writel(port, val, UART_IR_REG); | ||
203 | } | ||
204 | |||
205 | /* | ||
206 | * serial core request to start/stop emitting break char | ||
207 | */ | ||
208 | static void bcm_uart_break_ctl(struct uart_port *port, int ctl) | ||
209 | { | ||
210 | unsigned long flags; | ||
211 | unsigned int val; | ||
212 | |||
213 | spin_lock_irqsave(&port->lock, flags); | ||
214 | |||
215 | val = bcm_uart_readl(port, UART_CTL_REG); | ||
216 | if (ctl) | ||
217 | val |= UART_CTL_XMITBRK_MASK; | ||
218 | else | ||
219 | val &= ~UART_CTL_XMITBRK_MASK; | ||
220 | bcm_uart_writel(port, val, UART_CTL_REG); | ||
221 | |||
222 | spin_unlock_irqrestore(&port->lock, flags); | ||
223 | } | ||
224 | |||
225 | /* | ||
226 | * return port type in string format | ||
227 | */ | ||
228 | static const char *bcm_uart_type(struct uart_port *port) | ||
229 | { | ||
230 | return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL; | ||
231 | } | ||
232 | |||
233 | /* | ||
234 | * read all chars in rx fifo and send them to core | ||
235 | */ | ||
236 | static void bcm_uart_do_rx(struct uart_port *port) | ||
237 | { | ||
238 | struct tty_struct *tty; | ||
239 | unsigned int max_count; | ||
240 | |||
241 | /* limit number of char read in interrupt, should not be | ||
242 | * higher than fifo size anyway since we're much faster than | ||
243 | * serial port */ | ||
244 | max_count = 32; | ||
245 | tty = port->info->port.tty; | ||
246 | do { | ||
247 | unsigned int iestat, c, cstat; | ||
248 | char flag; | ||
249 | |||
250 | /* get overrun/fifo empty information from ier | ||
251 | * register */ | ||
252 | iestat = bcm_uart_readl(port, UART_IR_REG); | ||
253 | if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY))) | ||
254 | break; | ||
255 | |||
256 | cstat = c = bcm_uart_readl(port, UART_FIFO_REG); | ||
257 | port->icount.rx++; | ||
258 | flag = TTY_NORMAL; | ||
259 | c &= 0xff; | ||
260 | |||
261 | if (unlikely((cstat & UART_FIFO_ANYERR_MASK))) { | ||
262 | /* do stats first */ | ||
263 | if (cstat & UART_FIFO_BRKDET_MASK) { | ||
264 | port->icount.brk++; | ||
265 | if (uart_handle_break(port)) | ||
266 | continue; | ||
267 | } | ||
268 | |||
269 | if (cstat & UART_FIFO_PARERR_MASK) | ||
270 | port->icount.parity++; | ||
271 | if (cstat & UART_FIFO_FRAMEERR_MASK) | ||
272 | port->icount.frame++; | ||
273 | |||
274 | /* update flag wrt read_status_mask */ | ||
275 | cstat &= port->read_status_mask; | ||
276 | if (cstat & UART_FIFO_BRKDET_MASK) | ||
277 | flag = TTY_BREAK; | ||
278 | if (cstat & UART_FIFO_FRAMEERR_MASK) | ||
279 | flag = TTY_FRAME; | ||
280 | if (cstat & UART_FIFO_PARERR_MASK) | ||
281 | flag = TTY_PARITY; | ||
282 | } | ||
283 | |||
284 | if (uart_handle_sysrq_char(port, c)) | ||
285 | continue; | ||
286 | |||
287 | if (unlikely(iestat & UART_IR_STAT(UART_IR_RXOVER))) { | ||
288 | port->icount.overrun++; | ||
289 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | ||
290 | } | ||
291 | |||
292 | if ((cstat & port->ignore_status_mask) == 0) | ||
293 | tty_insert_flip_char(tty, c, flag); | ||
294 | |||
295 | } while (--max_count); | ||
296 | |||
297 | tty_flip_buffer_push(tty); | ||
298 | } | ||
299 | |||
300 | /* | ||
301 | * fill tx fifo with chars to send, stop when fifo is about to be full | ||
302 | * or when all chars have been sent. | ||
303 | */ | ||
304 | static void bcm_uart_do_tx(struct uart_port *port) | ||
305 | { | ||
306 | struct circ_buf *xmit; | ||
307 | unsigned int val, max_count; | ||
308 | |||
309 | if (port->x_char) { | ||
310 | bcm_uart_writel(port, port->x_char, UART_FIFO_REG); | ||
311 | port->icount.tx++; | ||
312 | port->x_char = 0; | ||
313 | return; | ||
314 | } | ||
315 | |||
316 | if (uart_tx_stopped(port)) { | ||
317 | bcm_uart_stop_tx(port); | ||
318 | return; | ||
319 | } | ||
320 | |||
321 | xmit = &port->info->xmit; | ||
322 | if (uart_circ_empty(xmit)) | ||
323 | goto txq_empty; | ||
324 | |||
325 | val = bcm_uart_readl(port, UART_MCTL_REG); | ||
326 | val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT; | ||
327 | max_count = port->fifosize - val; | ||
328 | |||
329 | while (max_count--) { | ||
330 | unsigned int c; | ||
331 | |||
332 | c = xmit->buf[xmit->tail]; | ||
333 | bcm_uart_writel(port, c, UART_FIFO_REG); | ||
334 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | ||
335 | port->icount.tx++; | ||
336 | if (uart_circ_empty(xmit)) | ||
337 | break; | ||
338 | } | ||
339 | |||
340 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | ||
341 | uart_write_wakeup(port); | ||
342 | |||
343 | if (uart_circ_empty(xmit)) | ||
344 | goto txq_empty; | ||
345 | return; | ||
346 | |||
347 | txq_empty: | ||
348 | /* nothing to send, disable transmit interrupt */ | ||
349 | val = bcm_uart_readl(port, UART_IR_REG); | ||
350 | val &= ~UART_TX_INT_MASK; | ||
351 | bcm_uart_writel(port, val, UART_IR_REG); | ||
352 | return; | ||
353 | } | ||
354 | |||
355 | /* | ||
356 | * process uart interrupt | ||
357 | */ | ||
358 | static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id) | ||
359 | { | ||
360 | struct uart_port *port; | ||
361 | unsigned int irqstat; | ||
362 | |||
363 | port = dev_id; | ||
364 | spin_lock(&port->lock); | ||
365 | |||
366 | irqstat = bcm_uart_readl(port, UART_IR_REG); | ||
367 | if (irqstat & UART_RX_INT_STAT) | ||
368 | bcm_uart_do_rx(port); | ||
369 | |||
370 | if (irqstat & UART_TX_INT_STAT) | ||
371 | bcm_uart_do_tx(port); | ||
372 | |||
373 | if (irqstat & UART_IR_MASK(UART_IR_EXTIP)) { | ||
374 | unsigned int estat; | ||
375 | |||
376 | estat = bcm_uart_readl(port, UART_EXTINP_REG); | ||
377 | if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_CTS)) | ||
378 | uart_handle_cts_change(port, | ||
379 | estat & UART_EXTINP_CTS_MASK); | ||
380 | if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_DCD)) | ||
381 | uart_handle_dcd_change(port, | ||
382 | estat & UART_EXTINP_DCD_MASK); | ||
383 | } | ||
384 | |||
385 | spin_unlock(&port->lock); | ||
386 | return IRQ_HANDLED; | ||
387 | } | ||
388 | |||
389 | /* | ||
390 | * enable rx & tx operation on uart | ||
391 | */ | ||
392 | static void bcm_uart_enable(struct uart_port *port) | ||
393 | { | ||
394 | unsigned int val; | ||
395 | |||
396 | val = bcm_uart_readl(port, UART_CTL_REG); | ||
397 | val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK); | ||
398 | bcm_uart_writel(port, val, UART_CTL_REG); | ||
399 | } | ||
400 | |||
401 | /* | ||
402 | * disable rx & tx operation on uart | ||
403 | */ | ||
404 | static void bcm_uart_disable(struct uart_port *port) | ||
405 | { | ||
406 | unsigned int val; | ||
407 | |||
408 | val = bcm_uart_readl(port, UART_CTL_REG); | ||
409 | val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | | ||
410 | UART_CTL_RXEN_MASK); | ||
411 | bcm_uart_writel(port, val, UART_CTL_REG); | ||
412 | } | ||
413 | |||
414 | /* | ||
415 | * clear all unread data in rx fifo and unsent data in tx fifo | ||
416 | */ | ||
417 | static void bcm_uart_flush(struct uart_port *port) | ||
418 | { | ||
419 | unsigned int val; | ||
420 | |||
421 | /* empty rx and tx fifo */ | ||
422 | val = bcm_uart_readl(port, UART_CTL_REG); | ||
423 | val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK; | ||
424 | bcm_uart_writel(port, val, UART_CTL_REG); | ||
425 | |||
426 | /* read any pending char to make sure all irq status are | ||
427 | * cleared */ | ||
428 | (void)bcm_uart_readl(port, UART_FIFO_REG); | ||
429 | } | ||
430 | |||
431 | /* | ||
432 | * serial core request to initialize uart and start rx operation | ||
433 | */ | ||
434 | static int bcm_uart_startup(struct uart_port *port) | ||
435 | { | ||
436 | unsigned int val; | ||
437 | int ret; | ||
438 | |||
439 | /* mask all irq and flush port */ | ||
440 | bcm_uart_disable(port); | ||
441 | bcm_uart_writel(port, 0, UART_IR_REG); | ||
442 | bcm_uart_flush(port); | ||
443 | |||
444 | /* clear any pending external input interrupt */ | ||
445 | (void)bcm_uart_readl(port, UART_EXTINP_REG); | ||
446 | |||
447 | /* set rx/tx fifo thresh to fifo half size */ | ||
448 | val = bcm_uart_readl(port, UART_MCTL_REG); | ||
449 | val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK); | ||
450 | val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT; | ||
451 | val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT; | ||
452 | bcm_uart_writel(port, val, UART_MCTL_REG); | ||
453 | |||
454 | /* set rx fifo timeout to 1 char time */ | ||
455 | val = bcm_uart_readl(port, UART_CTL_REG); | ||
456 | val &= ~UART_CTL_RXTMOUTCNT_MASK; | ||
457 | val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT; | ||
458 | bcm_uart_writel(port, val, UART_CTL_REG); | ||
459 | |||
460 | /* report any edge on dcd and cts */ | ||
461 | val = UART_EXTINP_INT_MASK; | ||
462 | val |= UART_EXTINP_DCD_NOSENSE_MASK; | ||
463 | val |= UART_EXTINP_CTS_NOSENSE_MASK; | ||
464 | bcm_uart_writel(port, val, UART_EXTINP_REG); | ||
465 | |||
466 | /* register irq and enable rx interrupts */ | ||
467 | ret = request_irq(port->irq, bcm_uart_interrupt, 0, | ||
468 | bcm_uart_type(port), port); | ||
469 | if (ret) | ||
470 | return ret; | ||
471 | bcm_uart_writel(port, UART_RX_INT_MASK, UART_IR_REG); | ||
472 | bcm_uart_enable(port); | ||
473 | return 0; | ||
474 | } | ||
475 | |||
476 | /* | ||
477 | * serial core request to flush & disable uart | ||
478 | */ | ||
479 | static void bcm_uart_shutdown(struct uart_port *port) | ||
480 | { | ||
481 | unsigned long flags; | ||
482 | |||
483 | spin_lock_irqsave(&port->lock, flags); | ||
484 | bcm_uart_writel(port, 0, UART_IR_REG); | ||
485 | spin_unlock_irqrestore(&port->lock, flags); | ||
486 | |||
487 | bcm_uart_disable(port); | ||
488 | bcm_uart_flush(port); | ||
489 | free_irq(port->irq, port); | ||
490 | } | ||
491 | |||
492 | /* | ||
493 | * serial core request to change current uart setting | ||
494 | */ | ||
495 | static void bcm_uart_set_termios(struct uart_port *port, | ||
496 | struct ktermios *new, | ||
497 | struct ktermios *old) | ||
498 | { | ||
499 | unsigned int ctl, baud, quot, ier; | ||
500 | unsigned long flags; | ||
501 | |||
502 | spin_lock_irqsave(&port->lock, flags); | ||
503 | |||
504 | /* disable uart while changing speed */ | ||
505 | bcm_uart_disable(port); | ||
506 | bcm_uart_flush(port); | ||
507 | |||
508 | /* update Control register */ | ||
509 | ctl = bcm_uart_readl(port, UART_CTL_REG); | ||
510 | ctl &= ~UART_CTL_BITSPERSYM_MASK; | ||
511 | |||
512 | switch (new->c_cflag & CSIZE) { | ||
513 | case CS5: | ||
514 | ctl |= (0 << UART_CTL_BITSPERSYM_SHIFT); | ||
515 | break; | ||
516 | case CS6: | ||
517 | ctl |= (1 << UART_CTL_BITSPERSYM_SHIFT); | ||
518 | break; | ||
519 | case CS7: | ||
520 | ctl |= (2 << UART_CTL_BITSPERSYM_SHIFT); | ||
521 | break; | ||
522 | default: | ||
523 | ctl |= (3 << UART_CTL_BITSPERSYM_SHIFT); | ||
524 | break; | ||
525 | } | ||
526 | |||
527 | ctl &= ~UART_CTL_STOPBITS_MASK; | ||
528 | if (new->c_cflag & CSTOPB) | ||
529 | ctl |= UART_CTL_STOPBITS_2; | ||
530 | else | ||
531 | ctl |= UART_CTL_STOPBITS_1; | ||
532 | |||
533 | ctl &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK); | ||
534 | if (new->c_cflag & PARENB) | ||
535 | ctl |= (UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK); | ||
536 | ctl &= ~(UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK); | ||
537 | if (new->c_cflag & PARODD) | ||
538 | ctl |= (UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK); | ||
539 | bcm_uart_writel(port, ctl, UART_CTL_REG); | ||
540 | |||
541 | /* update Baudword register */ | ||
542 | baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); | ||
543 | quot = uart_get_divisor(port, baud) - 1; | ||
544 | bcm_uart_writel(port, quot, UART_BAUD_REG); | ||
545 | |||
546 | /* update Interrupt register */ | ||
547 | ier = bcm_uart_readl(port, UART_IR_REG); | ||
548 | |||
549 | ier &= ~UART_IR_MASK(UART_IR_EXTIP); | ||
550 | if (UART_ENABLE_MS(port, new->c_cflag)) | ||
551 | ier |= UART_IR_MASK(UART_IR_EXTIP); | ||
552 | |||
553 | bcm_uart_writel(port, ier, UART_IR_REG); | ||
554 | |||
555 | /* update read/ignore mask */ | ||
556 | port->read_status_mask = UART_FIFO_VALID_MASK; | ||
557 | if (new->c_iflag & INPCK) { | ||
558 | port->read_status_mask |= UART_FIFO_FRAMEERR_MASK; | ||
559 | port->read_status_mask |= UART_FIFO_PARERR_MASK; | ||
560 | } | ||
561 | if (new->c_iflag & (BRKINT)) | ||
562 | port->read_status_mask |= UART_FIFO_BRKDET_MASK; | ||
563 | |||
564 | port->ignore_status_mask = 0; | ||
565 | if (new->c_iflag & IGNPAR) | ||
566 | port->ignore_status_mask |= UART_FIFO_PARERR_MASK; | ||
567 | if (new->c_iflag & IGNBRK) | ||
568 | port->ignore_status_mask |= UART_FIFO_BRKDET_MASK; | ||
569 | if (!(new->c_cflag & CREAD)) | ||
570 | port->ignore_status_mask |= UART_FIFO_VALID_MASK; | ||
571 | |||
572 | uart_update_timeout(port, new->c_cflag, baud); | ||
573 | bcm_uart_enable(port); | ||
574 | spin_unlock_irqrestore(&port->lock, flags); | ||
575 | } | ||
576 | |||
577 | /* | ||
578 | * serial core request to claim uart iomem | ||
579 | */ | ||
580 | static int bcm_uart_request_port(struct uart_port *port) | ||
581 | { | ||
582 | unsigned int size; | ||
583 | |||
584 | size = RSET_UART_SIZE; | ||
585 | if (!request_mem_region(port->mapbase, size, "bcm63xx")) { | ||
586 | dev_err(port->dev, "Memory region busy\n"); | ||
587 | return -EBUSY; | ||
588 | } | ||
589 | |||
590 | port->membase = ioremap(port->mapbase, size); | ||
591 | if (!port->membase) { | ||
592 | dev_err(port->dev, "Unable to map registers\n"); | ||
593 | release_mem_region(port->mapbase, size); | ||
594 | return -EBUSY; | ||
595 | } | ||
596 | return 0; | ||
597 | } | ||
598 | |||
599 | /* | ||
600 | * serial core request to release uart iomem | ||
601 | */ | ||
602 | static void bcm_uart_release_port(struct uart_port *port) | ||
603 | { | ||
604 | release_mem_region(port->mapbase, RSET_UART_SIZE); | ||
605 | iounmap(port->membase); | ||
606 | } | ||
607 | |||
608 | /* | ||
609 | * serial core request to do any port required autoconfiguration | ||
610 | */ | ||
611 | static void bcm_uart_config_port(struct uart_port *port, int flags) | ||
612 | { | ||
613 | if (flags & UART_CONFIG_TYPE) { | ||
614 | if (bcm_uart_request_port(port)) | ||
615 | return; | ||
616 | port->type = PORT_BCM63XX; | ||
617 | } | ||
618 | } | ||
619 | |||
620 | /* | ||
621 | * serial core request to check that port information in serinfo are | ||
622 | * suitable | ||
623 | */ | ||
624 | static int bcm_uart_verify_port(struct uart_port *port, | ||
625 | struct serial_struct *serinfo) | ||
626 | { | ||
627 | if (port->type != PORT_BCM63XX) | ||
628 | return -EINVAL; | ||
629 | if (port->irq != serinfo->irq) | ||
630 | return -EINVAL; | ||
631 | if (port->iotype != serinfo->io_type) | ||
632 | return -EINVAL; | ||
633 | if (port->mapbase != (unsigned long)serinfo->iomem_base) | ||
634 | return -EINVAL; | ||
635 | return 0; | ||
636 | } | ||
637 | |||
638 | /* serial core callbacks */ | ||
639 | static struct uart_ops bcm_uart_ops = { | ||
640 | .tx_empty = bcm_uart_tx_empty, | ||
641 | .get_mctrl = bcm_uart_get_mctrl, | ||
642 | .set_mctrl = bcm_uart_set_mctrl, | ||
643 | .start_tx = bcm_uart_start_tx, | ||
644 | .stop_tx = bcm_uart_stop_tx, | ||
645 | .stop_rx = bcm_uart_stop_rx, | ||
646 | .enable_ms = bcm_uart_enable_ms, | ||
647 | .break_ctl = bcm_uart_break_ctl, | ||
648 | .startup = bcm_uart_startup, | ||
649 | .shutdown = bcm_uart_shutdown, | ||
650 | .set_termios = bcm_uart_set_termios, | ||
651 | .type = bcm_uart_type, | ||
652 | .release_port = bcm_uart_release_port, | ||
653 | .request_port = bcm_uart_request_port, | ||
654 | .config_port = bcm_uart_config_port, | ||
655 | .verify_port = bcm_uart_verify_port, | ||
656 | }; | ||
657 | |||
658 | |||
659 | |||
660 | #ifdef CONFIG_SERIAL_BCM63XX_CONSOLE | ||
661 | static inline void wait_for_xmitr(struct uart_port *port) | ||
662 | { | ||
663 | unsigned int tmout; | ||
664 | |||
665 | /* Wait up to 10ms for the character(s) to be sent. */ | ||
666 | tmout = 10000; | ||
667 | while (--tmout) { | ||
668 | unsigned int val; | ||
669 | |||
670 | val = bcm_uart_readl(port, UART_IR_REG); | ||
671 | if (val & UART_IR_STAT(UART_IR_TXEMPTY)) | ||
672 | break; | ||
673 | udelay(1); | ||
674 | } | ||
675 | |||
676 | /* Wait up to 1s for flow control if necessary */ | ||
677 | if (port->flags & UPF_CONS_FLOW) { | ||
678 | tmout = 1000000; | ||
679 | while (--tmout) { | ||
680 | unsigned int val; | ||
681 | |||
682 | val = bcm_uart_readl(port, UART_EXTINP_REG); | ||
683 | if (val & UART_EXTINP_CTS_MASK) | ||
684 | break; | ||
685 | udelay(1); | ||
686 | } | ||
687 | } | ||
688 | } | ||
689 | |||
690 | /* | ||
691 | * output given char | ||
692 | */ | ||
693 | static void bcm_console_putchar(struct uart_port *port, int ch) | ||
694 | { | ||
695 | wait_for_xmitr(port); | ||
696 | bcm_uart_writel(port, ch, UART_FIFO_REG); | ||
697 | } | ||
698 | |||
699 | /* | ||
700 | * console core request to output given string | ||
701 | */ | ||
702 | static void bcm_console_write(struct console *co, const char *s, | ||
703 | unsigned int count) | ||
704 | { | ||
705 | struct uart_port *port; | ||
706 | unsigned long flags; | ||
707 | int locked; | ||
708 | |||
709 | port = &ports[co->index]; | ||
710 | |||
711 | local_irq_save(flags); | ||
712 | if (port->sysrq) { | ||
713 | /* bcm_uart_interrupt() already took the lock */ | ||
714 | locked = 0; | ||
715 | } else if (oops_in_progress) { | ||
716 | locked = spin_trylock(&port->lock); | ||
717 | } else { | ||
718 | spin_lock(&port->lock); | ||
719 | locked = 1; | ||
720 | } | ||
721 | |||
722 | /* call helper to deal with \r\n */ | ||
723 | uart_console_write(port, s, count, bcm_console_putchar); | ||
724 | |||
725 | /* and wait for char to be transmitted */ | ||
726 | wait_for_xmitr(port); | ||
727 | |||
728 | if (locked) | ||
729 | spin_unlock(&port->lock); | ||
730 | local_irq_restore(flags); | ||
731 | } | ||
732 | |||
733 | /* | ||
734 | * console core request to setup given console, find matching uart | ||
735 | * port and setup it. | ||
736 | */ | ||
737 | static int bcm_console_setup(struct console *co, char *options) | ||
738 | { | ||
739 | struct uart_port *port; | ||
740 | int baud = 9600; | ||
741 | int bits = 8; | ||
742 | int parity = 'n'; | ||
743 | int flow = 'n'; | ||
744 | |||
745 | if (co->index < 0 || co->index >= BCM63XX_NR_UARTS) | ||
746 | return -EINVAL; | ||
747 | port = &ports[co->index]; | ||
748 | if (!port->membase) | ||
749 | return -ENODEV; | ||
750 | if (options) | ||
751 | uart_parse_options(options, &baud, &parity, &bits, &flow); | ||
752 | |||
753 | return uart_set_options(port, co, baud, parity, bits, flow); | ||
754 | } | ||
755 | |||
756 | static struct uart_driver bcm_uart_driver; | ||
757 | |||
758 | static struct console bcm63xx_console = { | ||
759 | .name = "ttyS", | ||
760 | .write = bcm_console_write, | ||
761 | .device = uart_console_device, | ||
762 | .setup = bcm_console_setup, | ||
763 | .flags = CON_PRINTBUFFER, | ||
764 | .index = -1, | ||
765 | .data = &bcm_uart_driver, | ||
766 | }; | ||
767 | |||
768 | static int __init bcm63xx_console_init(void) | ||
769 | { | ||
770 | register_console(&bcm63xx_console); | ||
771 | return 0; | ||
772 | } | ||
773 | |||
774 | console_initcall(bcm63xx_console_init); | ||
775 | |||
776 | #define BCM63XX_CONSOLE (&bcm63xx_console) | ||
777 | #else | ||
778 | #define BCM63XX_CONSOLE NULL | ||
779 | #endif /* CONFIG_SERIAL_BCM63XX_CONSOLE */ | ||
780 | |||
781 | static struct uart_driver bcm_uart_driver = { | ||
782 | .owner = THIS_MODULE, | ||
783 | .driver_name = "bcm63xx_uart", | ||
784 | .dev_name = "ttyS", | ||
785 | .major = TTY_MAJOR, | ||
786 | .minor = 64, | ||
787 | .nr = 1, | ||
788 | .cons = BCM63XX_CONSOLE, | ||
789 | }; | ||
790 | |||
791 | /* | ||
792 | * platform driver probe/remove callback | ||
793 | */ | ||
794 | static int __devinit bcm_uart_probe(struct platform_device *pdev) | ||
795 | { | ||
796 | struct resource *res_mem, *res_irq; | ||
797 | struct uart_port *port; | ||
798 | struct clk *clk; | ||
799 | int ret; | ||
800 | |||
801 | if (pdev->id < 0 || pdev->id >= BCM63XX_NR_UARTS) | ||
802 | return -EINVAL; | ||
803 | |||
804 | if (ports[pdev->id].membase) | ||
805 | return -EBUSY; | ||
806 | |||
807 | res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
808 | if (!res_mem) | ||
809 | return -ENODEV; | ||
810 | |||
811 | res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | ||
812 | if (!res_irq) | ||
813 | return -ENODEV; | ||
814 | |||
815 | clk = clk_get(&pdev->dev, "periph"); | ||
816 | if (IS_ERR(clk)) | ||
817 | return -ENODEV; | ||
818 | |||
819 | port = &ports[pdev->id]; | ||
820 | memset(port, 0, sizeof(*port)); | ||
821 | port->iotype = UPIO_MEM; | ||
822 | port->mapbase = res_mem->start; | ||
823 | port->irq = res_irq->start; | ||
824 | port->ops = &bcm_uart_ops; | ||
825 | port->flags = UPF_BOOT_AUTOCONF; | ||
826 | port->dev = &pdev->dev; | ||
827 | port->fifosize = 16; | ||
828 | port->uartclk = clk_get_rate(clk) / 2; | ||
829 | clk_put(clk); | ||
830 | |||
831 | ret = uart_add_one_port(&bcm_uart_driver, port); | ||
832 | if (ret) { | ||
833 | kfree(port); | ||
834 | return ret; | ||
835 | } | ||
836 | platform_set_drvdata(pdev, port); | ||
837 | return 0; | ||
838 | } | ||
839 | |||
840 | static int __devexit bcm_uart_remove(struct platform_device *pdev) | ||
841 | { | ||
842 | struct uart_port *port; | ||
843 | |||
844 | port = platform_get_drvdata(pdev); | ||
845 | uart_remove_one_port(&bcm_uart_driver, port); | ||
846 | platform_set_drvdata(pdev, NULL); | ||
847 | /* mark port as free */ | ||
848 | ports[pdev->id].membase = 0; | ||
849 | return 0; | ||
850 | } | ||
851 | |||
852 | /* | ||
853 | * platform driver stuff | ||
854 | */ | ||
855 | static struct platform_driver bcm_uart_platform_driver = { | ||
856 | .probe = bcm_uart_probe, | ||
857 | .remove = __devexit_p(bcm_uart_remove), | ||
858 | .driver = { | ||
859 | .owner = THIS_MODULE, | ||
860 | .name = "bcm63xx_uart", | ||
861 | }, | ||
862 | }; | ||
863 | |||
864 | static int __init bcm_uart_init(void) | ||
865 | { | ||
866 | int ret; | ||
867 | |||
868 | ret = uart_register_driver(&bcm_uart_driver); | ||
869 | if (ret) | ||
870 | return ret; | ||
871 | |||
872 | ret = platform_driver_register(&bcm_uart_platform_driver); | ||
873 | if (ret) | ||
874 | uart_unregister_driver(&bcm_uart_driver); | ||
875 | |||
876 | return ret; | ||
877 | } | ||
878 | |||
879 | static void __exit bcm_uart_exit(void) | ||
880 | { | ||
881 | platform_driver_unregister(&bcm_uart_platform_driver); | ||
882 | uart_unregister_driver(&bcm_uart_driver); | ||
883 | } | ||
884 | |||
885 | module_init(bcm_uart_init); | ||
886 | module_exit(bcm_uart_exit); | ||
887 | |||
888 | MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>"); | ||
889 | MODULE_DESCRIPTION("Broadcom 63<xx integrated uart driver"); | ||
890 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/serial/icom.c b/drivers/serial/icom.c index 2d7feecaf492..0028b6f89ce6 100644 --- a/drivers/serial/icom.c +++ b/drivers/serial/icom.c | |||
@@ -307,7 +307,7 @@ static void stop_processor(struct icom_port *icom_port) | |||
307 | if (port < 4) { | 307 | if (port < 4) { |
308 | temp = readl(stop_proc[port].global_control_reg); | 308 | temp = readl(stop_proc[port].global_control_reg); |
309 | temp = | 309 | temp = |
310 | (temp & ~start_proc[port].processor_id) | stop_proc[port].processor_id; | 310 | (temp & ~start_proc[port].processor_id) | stop_proc[port].processor_id; |
311 | writel(temp, stop_proc[port].global_control_reg); | 311 | writel(temp, stop_proc[port].global_control_reg); |
312 | 312 | ||
313 | /* write flush */ | 313 | /* write flush */ |
@@ -336,7 +336,7 @@ static void start_processor(struct icom_port *icom_port) | |||
336 | if (port < 4) { | 336 | if (port < 4) { |
337 | temp = readl(start_proc[port].global_control_reg); | 337 | temp = readl(start_proc[port].global_control_reg); |
338 | temp = | 338 | temp = |
339 | (temp & ~stop_proc[port].processor_id) | start_proc[port].processor_id; | 339 | (temp & ~stop_proc[port].processor_id) | start_proc[port].processor_id; |
340 | writel(temp, start_proc[port].global_control_reg); | 340 | writel(temp, start_proc[port].global_control_reg); |
341 | 341 | ||
342 | /* write flush */ | 342 | /* write flush */ |
@@ -509,8 +509,8 @@ static void load_code(struct icom_port *icom_port) | |||
509 | dev_err(&icom_port->adapter->pci_dev->dev,"Port not opertional\n"); | 509 | dev_err(&icom_port->adapter->pci_dev->dev,"Port not opertional\n"); |
510 | } | 510 | } |
511 | 511 | ||
512 | if (new_page != NULL) | 512 | if (new_page != NULL) |
513 | pci_free_consistent(dev, 4096, new_page, temp_pci); | 513 | pci_free_consistent(dev, 4096, new_page, temp_pci); |
514 | } | 514 | } |
515 | 515 | ||
516 | static int startup(struct icom_port *icom_port) | 516 | static int startup(struct icom_port *icom_port) |
@@ -1493,15 +1493,15 @@ static int __devinit icom_probe(struct pci_dev *dev, | |||
1493 | const struct pci_device_id *ent) | 1493 | const struct pci_device_id *ent) |
1494 | { | 1494 | { |
1495 | int index; | 1495 | int index; |
1496 | unsigned int command_reg; | 1496 | unsigned int command_reg; |
1497 | int retval; | 1497 | int retval; |
1498 | struct icom_adapter *icom_adapter; | 1498 | struct icom_adapter *icom_adapter; |
1499 | struct icom_port *icom_port; | 1499 | struct icom_port *icom_port; |
1500 | 1500 | ||
1501 | retval = pci_enable_device(dev); | 1501 | retval = pci_enable_device(dev); |
1502 | if (retval) { | 1502 | if (retval) { |
1503 | dev_err(&dev->dev, "Device enable FAILED\n"); | 1503 | dev_err(&dev->dev, "Device enable FAILED\n"); |
1504 | return retval; | 1504 | return retval; |
1505 | } | 1505 | } |
1506 | 1506 | ||
1507 | if ( (retval = pci_request_regions(dev, "icom"))) { | 1507 | if ( (retval = pci_request_regions(dev, "icom"))) { |
@@ -1510,23 +1510,23 @@ static int __devinit icom_probe(struct pci_dev *dev, | |||
1510 | return retval; | 1510 | return retval; |
1511 | } | 1511 | } |
1512 | 1512 | ||
1513 | pci_set_master(dev); | 1513 | pci_set_master(dev); |
1514 | 1514 | ||
1515 | if ( (retval = pci_read_config_dword(dev, PCI_COMMAND, &command_reg))) { | 1515 | if ( (retval = pci_read_config_dword(dev, PCI_COMMAND, &command_reg))) { |
1516 | dev_err(&dev->dev, "PCI Config read FAILED\n"); | 1516 | dev_err(&dev->dev, "PCI Config read FAILED\n"); |
1517 | return retval; | 1517 | return retval; |
1518 | } | 1518 | } |
1519 | 1519 | ||
1520 | pci_write_config_dword(dev, PCI_COMMAND, | 1520 | pci_write_config_dword(dev, PCI_COMMAND, |
1521 | command_reg | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 1521 | command_reg | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
1522 | | PCI_COMMAND_PARITY | PCI_COMMAND_SERR); | 1522 | | PCI_COMMAND_PARITY | PCI_COMMAND_SERR); |
1523 | 1523 | ||
1524 | if (ent->driver_data == ADAPTER_V1) { | 1524 | if (ent->driver_data == ADAPTER_V1) { |
1525 | pci_write_config_dword(dev, 0x44, 0x8300830A); | 1525 | pci_write_config_dword(dev, 0x44, 0x8300830A); |
1526 | } else { | 1526 | } else { |
1527 | pci_write_config_dword(dev, 0x44, 0x42004200); | 1527 | pci_write_config_dword(dev, 0x44, 0x42004200); |
1528 | pci_write_config_dword(dev, 0x48, 0x42004200); | 1528 | pci_write_config_dword(dev, 0x48, 0x42004200); |
1529 | } | 1529 | } |
1530 | 1530 | ||
1531 | 1531 | ||
1532 | retval = icom_alloc_adapter(&icom_adapter); | 1532 | retval = icom_alloc_adapter(&icom_adapter); |
@@ -1536,10 +1536,10 @@ static int __devinit icom_probe(struct pci_dev *dev, | |||
1536 | goto probe_exit0; | 1536 | goto probe_exit0; |
1537 | } | 1537 | } |
1538 | 1538 | ||
1539 | icom_adapter->base_addr_pci = pci_resource_start(dev, 0); | 1539 | icom_adapter->base_addr_pci = pci_resource_start(dev, 0); |
1540 | icom_adapter->pci_dev = dev; | 1540 | icom_adapter->pci_dev = dev; |
1541 | icom_adapter->version = ent->driver_data; | 1541 | icom_adapter->version = ent->driver_data; |
1542 | icom_adapter->subsystem_id = ent->subdevice; | 1542 | icom_adapter->subsystem_id = ent->subdevice; |
1543 | 1543 | ||
1544 | 1544 | ||
1545 | retval = icom_init_ports(icom_adapter); | 1545 | retval = icom_init_ports(icom_adapter); |
@@ -1548,7 +1548,7 @@ static int __devinit icom_probe(struct pci_dev *dev, | |||
1548 | goto probe_exit1; | 1548 | goto probe_exit1; |
1549 | } | 1549 | } |
1550 | 1550 | ||
1551 | icom_adapter->base_addr = pci_ioremap_bar(dev, 0); | 1551 | icom_adapter->base_addr = pci_ioremap_bar(dev, 0); |
1552 | 1552 | ||
1553 | if (!icom_adapter->base_addr) | 1553 | if (!icom_adapter->base_addr) |
1554 | goto probe_exit1; | 1554 | goto probe_exit1; |
@@ -1562,7 +1562,7 @@ static int __devinit icom_probe(struct pci_dev *dev, | |||
1562 | 1562 | ||
1563 | retval = icom_load_ports(icom_adapter); | 1563 | retval = icom_load_ports(icom_adapter); |
1564 | 1564 | ||
1565 | for (index = 0; index < icom_adapter->numb_ports; index++) { | 1565 | for (index = 0; index < icom_adapter->numb_ports; index++) { |
1566 | icom_port = &icom_adapter->port_info[index]; | 1566 | icom_port = &icom_adapter->port_info[index]; |
1567 | 1567 | ||
1568 | if (icom_port->status == ICOM_PORT_ACTIVE) { | 1568 | if (icom_port->status == ICOM_PORT_ACTIVE) { |
@@ -1579,7 +1579,7 @@ static int __devinit icom_probe(struct pci_dev *dev, | |||
1579 | icom_port->status = ICOM_PORT_OFF; | 1579 | icom_port->status = ICOM_PORT_OFF; |
1580 | dev_err(&dev->dev, "Device add failed\n"); | 1580 | dev_err(&dev->dev, "Device add failed\n"); |
1581 | } else | 1581 | } else |
1582 | dev_info(&dev->dev, "Device added\n"); | 1582 | dev_info(&dev->dev, "Device added\n"); |
1583 | } | 1583 | } |
1584 | } | 1584 | } |
1585 | 1585 | ||
@@ -1595,9 +1595,7 @@ probe_exit0: | |||
1595 | pci_release_regions(dev); | 1595 | pci_release_regions(dev); |
1596 | pci_disable_device(dev); | 1596 | pci_disable_device(dev); |
1597 | 1597 | ||
1598 | return retval; | 1598 | return retval; |
1599 | |||
1600 | |||
1601 | } | 1599 | } |
1602 | 1600 | ||
1603 | static void __devexit icom_remove(struct pci_dev *dev) | 1601 | static void __devexit icom_remove(struct pci_dev *dev) |
diff --git a/drivers/serial/sa1100.c b/drivers/serial/sa1100.c index 7f5e26873220..2199d819a987 100644 --- a/drivers/serial/sa1100.c +++ b/drivers/serial/sa1100.c | |||
@@ -638,7 +638,7 @@ static void __init sa1100_init_ports(void) | |||
638 | PPSR |= PPC_TXD1 | PPC_TXD3; | 638 | PPSR |= PPC_TXD1 | PPC_TXD3; |
639 | } | 639 | } |
640 | 640 | ||
641 | void __init sa1100_register_uart_fns(struct sa1100_port_fns *fns) | 641 | void __devinit sa1100_register_uart_fns(struct sa1100_port_fns *fns) |
642 | { | 642 | { |
643 | if (fns->get_mctrl) | 643 | if (fns->get_mctrl) |
644 | sa1100_pops.get_mctrl = fns->get_mctrl; | 644 | sa1100_pops.get_mctrl = fns->get_mctrl; |
diff --git a/drivers/serial/serial_txx9.c b/drivers/serial/serial_txx9.c index 0f7cf4c453e6..c50e9fbbf743 100644 --- a/drivers/serial/serial_txx9.c +++ b/drivers/serial/serial_txx9.c | |||
@@ -221,21 +221,26 @@ sio_quot_set(struct uart_txx9_port *up, int quot) | |||
221 | sio_out(up, TXX9_SIBGR, 0xff | TXX9_SIBGR_BCLK_T6); | 221 | sio_out(up, TXX9_SIBGR, 0xff | TXX9_SIBGR_BCLK_T6); |
222 | } | 222 | } |
223 | 223 | ||
224 | static struct uart_txx9_port *to_uart_txx9_port(struct uart_port *port) | ||
225 | { | ||
226 | return container_of(port, struct uart_txx9_port, port); | ||
227 | } | ||
228 | |||
224 | static void serial_txx9_stop_tx(struct uart_port *port) | 229 | static void serial_txx9_stop_tx(struct uart_port *port) |
225 | { | 230 | { |
226 | struct uart_txx9_port *up = (struct uart_txx9_port *)port; | 231 | struct uart_txx9_port *up = to_uart_txx9_port(port); |
227 | sio_mask(up, TXX9_SIDICR, TXX9_SIDICR_TIE); | 232 | sio_mask(up, TXX9_SIDICR, TXX9_SIDICR_TIE); |
228 | } | 233 | } |
229 | 234 | ||
230 | static void serial_txx9_start_tx(struct uart_port *port) | 235 | static void serial_txx9_start_tx(struct uart_port *port) |
231 | { | 236 | { |
232 | struct uart_txx9_port *up = (struct uart_txx9_port *)port; | 237 | struct uart_txx9_port *up = to_uart_txx9_port(port); |
233 | sio_set(up, TXX9_SIDICR, TXX9_SIDICR_TIE); | 238 | sio_set(up, TXX9_SIDICR, TXX9_SIDICR_TIE); |
234 | } | 239 | } |
235 | 240 | ||
236 | static void serial_txx9_stop_rx(struct uart_port *port) | 241 | static void serial_txx9_stop_rx(struct uart_port *port) |
237 | { | 242 | { |
238 | struct uart_txx9_port *up = (struct uart_txx9_port *)port; | 243 | struct uart_txx9_port *up = to_uart_txx9_port(port); |
239 | up->port.read_status_mask &= ~TXX9_SIDISR_RDIS; | 244 | up->port.read_status_mask &= ~TXX9_SIDISR_RDIS; |
240 | } | 245 | } |
241 | 246 | ||
@@ -246,7 +251,7 @@ static void serial_txx9_enable_ms(struct uart_port *port) | |||
246 | 251 | ||
247 | static void serial_txx9_initialize(struct uart_port *port) | 252 | static void serial_txx9_initialize(struct uart_port *port) |
248 | { | 253 | { |
249 | struct uart_txx9_port *up = (struct uart_txx9_port *)port; | 254 | struct uart_txx9_port *up = to_uart_txx9_port(port); |
250 | unsigned int tmout = 10000; | 255 | unsigned int tmout = 10000; |
251 | 256 | ||
252 | sio_out(up, TXX9_SIFCR, TXX9_SIFCR_SWRST); | 257 | sio_out(up, TXX9_SIFCR, TXX9_SIFCR_SWRST); |
@@ -414,7 +419,7 @@ static irqreturn_t serial_txx9_interrupt(int irq, void *dev_id) | |||
414 | 419 | ||
415 | static unsigned int serial_txx9_tx_empty(struct uart_port *port) | 420 | static unsigned int serial_txx9_tx_empty(struct uart_port *port) |
416 | { | 421 | { |
417 | struct uart_txx9_port *up = (struct uart_txx9_port *)port; | 422 | struct uart_txx9_port *up = to_uart_txx9_port(port); |
418 | unsigned long flags; | 423 | unsigned long flags; |
419 | unsigned int ret; | 424 | unsigned int ret; |
420 | 425 | ||
@@ -427,7 +432,7 @@ static unsigned int serial_txx9_tx_empty(struct uart_port *port) | |||
427 | 432 | ||
428 | static unsigned int serial_txx9_get_mctrl(struct uart_port *port) | 433 | static unsigned int serial_txx9_get_mctrl(struct uart_port *port) |
429 | { | 434 | { |
430 | struct uart_txx9_port *up = (struct uart_txx9_port *)port; | 435 | struct uart_txx9_port *up = to_uart_txx9_port(port); |
431 | unsigned int ret; | 436 | unsigned int ret; |
432 | 437 | ||
433 | /* no modem control lines */ | 438 | /* no modem control lines */ |
@@ -440,7 +445,7 @@ static unsigned int serial_txx9_get_mctrl(struct uart_port *port) | |||
440 | 445 | ||
441 | static void serial_txx9_set_mctrl(struct uart_port *port, unsigned int mctrl) | 446 | static void serial_txx9_set_mctrl(struct uart_port *port, unsigned int mctrl) |
442 | { | 447 | { |
443 | struct uart_txx9_port *up = (struct uart_txx9_port *)port; | 448 | struct uart_txx9_port *up = to_uart_txx9_port(port); |
444 | 449 | ||
445 | if (mctrl & TIOCM_RTS) | 450 | if (mctrl & TIOCM_RTS) |
446 | sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC); | 451 | sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC); |
@@ -450,7 +455,7 @@ static void serial_txx9_set_mctrl(struct uart_port *port, unsigned int mctrl) | |||
450 | 455 | ||
451 | static void serial_txx9_break_ctl(struct uart_port *port, int break_state) | 456 | static void serial_txx9_break_ctl(struct uart_port *port, int break_state) |
452 | { | 457 | { |
453 | struct uart_txx9_port *up = (struct uart_txx9_port *)port; | 458 | struct uart_txx9_port *up = to_uart_txx9_port(port); |
454 | unsigned long flags; | 459 | unsigned long flags; |
455 | 460 | ||
456 | spin_lock_irqsave(&up->port.lock, flags); | 461 | spin_lock_irqsave(&up->port.lock, flags); |
@@ -494,7 +499,7 @@ static int serial_txx9_get_poll_char(struct uart_port *port) | |||
494 | { | 499 | { |
495 | unsigned int ier; | 500 | unsigned int ier; |
496 | unsigned char c; | 501 | unsigned char c; |
497 | struct uart_txx9_port *up = (struct uart_txx9_port *)port; | 502 | struct uart_txx9_port *up = to_uart_txx9_port(port); |
498 | 503 | ||
499 | /* | 504 | /* |
500 | * First save the IER then disable the interrupts | 505 | * First save the IER then disable the interrupts |
@@ -520,7 +525,7 @@ static int serial_txx9_get_poll_char(struct uart_port *port) | |||
520 | static void serial_txx9_put_poll_char(struct uart_port *port, unsigned char c) | 525 | static void serial_txx9_put_poll_char(struct uart_port *port, unsigned char c) |
521 | { | 526 | { |
522 | unsigned int ier; | 527 | unsigned int ier; |
523 | struct uart_txx9_port *up = (struct uart_txx9_port *)port; | 528 | struct uart_txx9_port *up = to_uart_txx9_port(port); |
524 | 529 | ||
525 | /* | 530 | /* |
526 | * First save the IER then disable the interrupts | 531 | * First save the IER then disable the interrupts |
@@ -551,7 +556,7 @@ static void serial_txx9_put_poll_char(struct uart_port *port, unsigned char c) | |||
551 | 556 | ||
552 | static int serial_txx9_startup(struct uart_port *port) | 557 | static int serial_txx9_startup(struct uart_port *port) |
553 | { | 558 | { |
554 | struct uart_txx9_port *up = (struct uart_txx9_port *)port; | 559 | struct uart_txx9_port *up = to_uart_txx9_port(port); |
555 | unsigned long flags; | 560 | unsigned long flags; |
556 | int retval; | 561 | int retval; |
557 | 562 | ||
@@ -596,7 +601,7 @@ static int serial_txx9_startup(struct uart_port *port) | |||
596 | 601 | ||
597 | static void serial_txx9_shutdown(struct uart_port *port) | 602 | static void serial_txx9_shutdown(struct uart_port *port) |
598 | { | 603 | { |
599 | struct uart_txx9_port *up = (struct uart_txx9_port *)port; | 604 | struct uart_txx9_port *up = to_uart_txx9_port(port); |
600 | unsigned long flags; | 605 | unsigned long flags; |
601 | 606 | ||
602 | /* | 607 | /* |
@@ -636,7 +641,7 @@ static void | |||
636 | serial_txx9_set_termios(struct uart_port *port, struct ktermios *termios, | 641 | serial_txx9_set_termios(struct uart_port *port, struct ktermios *termios, |
637 | struct ktermios *old) | 642 | struct ktermios *old) |
638 | { | 643 | { |
639 | struct uart_txx9_port *up = (struct uart_txx9_port *)port; | 644 | struct uart_txx9_port *up = to_uart_txx9_port(port); |
640 | unsigned int cval, fcr = 0; | 645 | unsigned int cval, fcr = 0; |
641 | unsigned long flags; | 646 | unsigned long flags; |
642 | unsigned int baud, quot; | 647 | unsigned int baud, quot; |
@@ -814,19 +819,19 @@ static void serial_txx9_release_resource(struct uart_txx9_port *up) | |||
814 | 819 | ||
815 | static void serial_txx9_release_port(struct uart_port *port) | 820 | static void serial_txx9_release_port(struct uart_port *port) |
816 | { | 821 | { |
817 | struct uart_txx9_port *up = (struct uart_txx9_port *)port; | 822 | struct uart_txx9_port *up = to_uart_txx9_port(port); |
818 | serial_txx9_release_resource(up); | 823 | serial_txx9_release_resource(up); |
819 | } | 824 | } |
820 | 825 | ||
821 | static int serial_txx9_request_port(struct uart_port *port) | 826 | static int serial_txx9_request_port(struct uart_port *port) |
822 | { | 827 | { |
823 | struct uart_txx9_port *up = (struct uart_txx9_port *)port; | 828 | struct uart_txx9_port *up = to_uart_txx9_port(port); |
824 | return serial_txx9_request_resource(up); | 829 | return serial_txx9_request_resource(up); |
825 | } | 830 | } |
826 | 831 | ||
827 | static void serial_txx9_config_port(struct uart_port *port, int uflags) | 832 | static void serial_txx9_config_port(struct uart_port *port, int uflags) |
828 | { | 833 | { |
829 | struct uart_txx9_port *up = (struct uart_txx9_port *)port; | 834 | struct uart_txx9_port *up = to_uart_txx9_port(port); |
830 | int ret; | 835 | int ret; |
831 | 836 | ||
832 | /* | 837 | /* |
@@ -897,7 +902,7 @@ static void __init serial_txx9_register_ports(struct uart_driver *drv, | |||
897 | 902 | ||
898 | static void serial_txx9_console_putchar(struct uart_port *port, int ch) | 903 | static void serial_txx9_console_putchar(struct uart_port *port, int ch) |
899 | { | 904 | { |
900 | struct uart_txx9_port *up = (struct uart_txx9_port *)port; | 905 | struct uart_txx9_port *up = to_uart_txx9_port(port); |
901 | 906 | ||
902 | wait_for_xmitr(up); | 907 | wait_for_xmitr(up); |
903 | sio_out(up, TXX9_SITFIFO, ch); | 908 | sio_out(up, TXX9_SITFIFO, ch); |
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 6d7a3f82c54b..21a118269cac 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile | |||
@@ -17,7 +17,7 @@ obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o | |||
17 | obj-$(CONFIG_SPI_AU1550) += au1550_spi.o | 17 | obj-$(CONFIG_SPI_AU1550) += au1550_spi.o |
18 | obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o | 18 | obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o |
19 | obj-$(CONFIG_SPI_GPIO) += spi_gpio.o | 19 | obj-$(CONFIG_SPI_GPIO) += spi_gpio.o |
20 | obj-$(CONFIG_SPI_IMX) += mxc_spi.o | 20 | obj-$(CONFIG_SPI_IMX) += spi_imx.o |
21 | obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o | 21 | obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o |
22 | obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o | 22 | obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o |
23 | obj-$(CONFIG_SPI_OMAP_UWIRE) += omap_uwire.o | 23 | obj-$(CONFIG_SPI_OMAP_UWIRE) += omap_uwire.o |
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/spi_imx.c index b1447236ae81..89c22efedfb0 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/spi_imx.c | |||
@@ -48,14 +48,14 @@ | |||
48 | #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ | 48 | #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ |
49 | #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ | 49 | #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ |
50 | 50 | ||
51 | struct mxc_spi_config { | 51 | struct spi_imx_config { |
52 | unsigned int speed_hz; | 52 | unsigned int speed_hz; |
53 | unsigned int bpw; | 53 | unsigned int bpw; |
54 | unsigned int mode; | 54 | unsigned int mode; |
55 | int cs; | 55 | int cs; |
56 | }; | 56 | }; |
57 | 57 | ||
58 | struct mxc_spi_data { | 58 | struct spi_imx_data { |
59 | struct spi_bitbang bitbang; | 59 | struct spi_bitbang bitbang; |
60 | 60 | ||
61 | struct completion xfer_done; | 61 | struct completion xfer_done; |
@@ -66,43 +66,43 @@ struct mxc_spi_data { | |||
66 | int *chipselect; | 66 | int *chipselect; |
67 | 67 | ||
68 | unsigned int count; | 68 | unsigned int count; |
69 | void (*tx)(struct mxc_spi_data *); | 69 | void (*tx)(struct spi_imx_data *); |
70 | void (*rx)(struct mxc_spi_data *); | 70 | void (*rx)(struct spi_imx_data *); |
71 | void *rx_buf; | 71 | void *rx_buf; |
72 | const void *tx_buf; | 72 | const void *tx_buf; |
73 | unsigned int txfifo; /* number of words pushed in tx FIFO */ | 73 | unsigned int txfifo; /* number of words pushed in tx FIFO */ |
74 | 74 | ||
75 | /* SoC specific functions */ | 75 | /* SoC specific functions */ |
76 | void (*intctrl)(struct mxc_spi_data *, int); | 76 | void (*intctrl)(struct spi_imx_data *, int); |
77 | int (*config)(struct mxc_spi_data *, struct mxc_spi_config *); | 77 | int (*config)(struct spi_imx_data *, struct spi_imx_config *); |
78 | void (*trigger)(struct mxc_spi_data *); | 78 | void (*trigger)(struct spi_imx_data *); |
79 | int (*rx_available)(struct mxc_spi_data *); | 79 | int (*rx_available)(struct spi_imx_data *); |
80 | }; | 80 | }; |
81 | 81 | ||
82 | #define MXC_SPI_BUF_RX(type) \ | 82 | #define MXC_SPI_BUF_RX(type) \ |
83 | static void mxc_spi_buf_rx_##type(struct mxc_spi_data *mxc_spi) \ | 83 | static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ |
84 | { \ | 84 | { \ |
85 | unsigned int val = readl(mxc_spi->base + MXC_CSPIRXDATA); \ | 85 | unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ |
86 | \ | 86 | \ |
87 | if (mxc_spi->rx_buf) { \ | 87 | if (spi_imx->rx_buf) { \ |
88 | *(type *)mxc_spi->rx_buf = val; \ | 88 | *(type *)spi_imx->rx_buf = val; \ |
89 | mxc_spi->rx_buf += sizeof(type); \ | 89 | spi_imx->rx_buf += sizeof(type); \ |
90 | } \ | 90 | } \ |
91 | } | 91 | } |
92 | 92 | ||
93 | #define MXC_SPI_BUF_TX(type) \ | 93 | #define MXC_SPI_BUF_TX(type) \ |
94 | static void mxc_spi_buf_tx_##type(struct mxc_spi_data *mxc_spi) \ | 94 | static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ |
95 | { \ | 95 | { \ |
96 | type val = 0; \ | 96 | type val = 0; \ |
97 | \ | 97 | \ |
98 | if (mxc_spi->tx_buf) { \ | 98 | if (spi_imx->tx_buf) { \ |
99 | val = *(type *)mxc_spi->tx_buf; \ | 99 | val = *(type *)spi_imx->tx_buf; \ |
100 | mxc_spi->tx_buf += sizeof(type); \ | 100 | spi_imx->tx_buf += sizeof(type); \ |
101 | } \ | 101 | } \ |
102 | \ | 102 | \ |
103 | mxc_spi->count -= sizeof(type); \ | 103 | spi_imx->count -= sizeof(type); \ |
104 | \ | 104 | \ |
105 | writel(val, mxc_spi->base + MXC_CSPITXDATA); \ | 105 | writel(val, spi_imx->base + MXC_CSPITXDATA); \ |
106 | } | 106 | } |
107 | 107 | ||
108 | MXC_SPI_BUF_RX(u8) | 108 | MXC_SPI_BUF_RX(u8) |
@@ -119,7 +119,7 @@ static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, | |||
119 | 256, 384, 512, 768, 1024}; | 119 | 256, 384, 512, 768, 1024}; |
120 | 120 | ||
121 | /* MX21, MX27 */ | 121 | /* MX21, MX27 */ |
122 | static unsigned int mxc_spi_clkdiv_1(unsigned int fin, | 122 | static unsigned int spi_imx_clkdiv_1(unsigned int fin, |
123 | unsigned int fspi) | 123 | unsigned int fspi) |
124 | { | 124 | { |
125 | int i, max; | 125 | int i, max; |
@@ -137,7 +137,7 @@ static unsigned int mxc_spi_clkdiv_1(unsigned int fin, | |||
137 | } | 137 | } |
138 | 138 | ||
139 | /* MX1, MX31, MX35 */ | 139 | /* MX1, MX31, MX35 */ |
140 | static unsigned int mxc_spi_clkdiv_2(unsigned int fin, | 140 | static unsigned int spi_imx_clkdiv_2(unsigned int fin, |
141 | unsigned int fspi) | 141 | unsigned int fspi) |
142 | { | 142 | { |
143 | int i, div = 4; | 143 | int i, div = 4; |
@@ -174,7 +174,7 @@ static unsigned int mxc_spi_clkdiv_2(unsigned int fin, | |||
174 | * the i.MX35 has a slightly different register layout for bits | 174 | * the i.MX35 has a slightly different register layout for bits |
175 | * we do not use here. | 175 | * we do not use here. |
176 | */ | 176 | */ |
177 | static void mx31_intctrl(struct mxc_spi_data *mxc_spi, int enable) | 177 | static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) |
178 | { | 178 | { |
179 | unsigned int val = 0; | 179 | unsigned int val = 0; |
180 | 180 | ||
@@ -183,24 +183,24 @@ static void mx31_intctrl(struct mxc_spi_data *mxc_spi, int enable) | |||
183 | if (enable & MXC_INT_RR) | 183 | if (enable & MXC_INT_RR) |
184 | val |= MX31_INTREG_RREN; | 184 | val |= MX31_INTREG_RREN; |
185 | 185 | ||
186 | writel(val, mxc_spi->base + MXC_CSPIINT); | 186 | writel(val, spi_imx->base + MXC_CSPIINT); |
187 | } | 187 | } |
188 | 188 | ||
189 | static void mx31_trigger(struct mxc_spi_data *mxc_spi) | 189 | static void mx31_trigger(struct spi_imx_data *spi_imx) |
190 | { | 190 | { |
191 | unsigned int reg; | 191 | unsigned int reg; |
192 | 192 | ||
193 | reg = readl(mxc_spi->base + MXC_CSPICTRL); | 193 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
194 | reg |= MX31_CSPICTRL_XCH; | 194 | reg |= MX31_CSPICTRL_XCH; |
195 | writel(reg, mxc_spi->base + MXC_CSPICTRL); | 195 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
196 | } | 196 | } |
197 | 197 | ||
198 | static int mx31_config(struct mxc_spi_data *mxc_spi, | 198 | static int mx31_config(struct spi_imx_data *spi_imx, |
199 | struct mxc_spi_config *config) | 199 | struct spi_imx_config *config) |
200 | { | 200 | { |
201 | unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; | 201 | unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; |
202 | 202 | ||
203 | reg |= mxc_spi_clkdiv_2(mxc_spi->spi_clk, config->speed_hz) << | 203 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << |
204 | MX31_CSPICTRL_DR_SHIFT; | 204 | MX31_CSPICTRL_DR_SHIFT; |
205 | 205 | ||
206 | if (cpu_is_mx31()) | 206 | if (cpu_is_mx31()) |
@@ -223,14 +223,14 @@ static int mx31_config(struct mxc_spi_data *mxc_spi, | |||
223 | reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT; | 223 | reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT; |
224 | } | 224 | } |
225 | 225 | ||
226 | writel(reg, mxc_spi->base + MXC_CSPICTRL); | 226 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
227 | 227 | ||
228 | return 0; | 228 | return 0; |
229 | } | 229 | } |
230 | 230 | ||
231 | static int mx31_rx_available(struct mxc_spi_data *mxc_spi) | 231 | static int mx31_rx_available(struct spi_imx_data *spi_imx) |
232 | { | 232 | { |
233 | return readl(mxc_spi->base + MX31_CSPISTATUS) & MX31_STATUS_RR; | 233 | return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; |
234 | } | 234 | } |
235 | 235 | ||
236 | #define MX27_INTREG_RR (1 << 4) | 236 | #define MX27_INTREG_RR (1 << 4) |
@@ -246,7 +246,7 @@ static int mx31_rx_available(struct mxc_spi_data *mxc_spi) | |||
246 | #define MX27_CSPICTRL_DR_SHIFT 14 | 246 | #define MX27_CSPICTRL_DR_SHIFT 14 |
247 | #define MX27_CSPICTRL_CS_SHIFT 19 | 247 | #define MX27_CSPICTRL_CS_SHIFT 19 |
248 | 248 | ||
249 | static void mx27_intctrl(struct mxc_spi_data *mxc_spi, int enable) | 249 | static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable) |
250 | { | 250 | { |
251 | unsigned int val = 0; | 251 | unsigned int val = 0; |
252 | 252 | ||
@@ -255,24 +255,24 @@ static void mx27_intctrl(struct mxc_spi_data *mxc_spi, int enable) | |||
255 | if (enable & MXC_INT_RR) | 255 | if (enable & MXC_INT_RR) |
256 | val |= MX27_INTREG_RREN; | 256 | val |= MX27_INTREG_RREN; |
257 | 257 | ||
258 | writel(val, mxc_spi->base + MXC_CSPIINT); | 258 | writel(val, spi_imx->base + MXC_CSPIINT); |
259 | } | 259 | } |
260 | 260 | ||
261 | static void mx27_trigger(struct mxc_spi_data *mxc_spi) | 261 | static void mx27_trigger(struct spi_imx_data *spi_imx) |
262 | { | 262 | { |
263 | unsigned int reg; | 263 | unsigned int reg; |
264 | 264 | ||
265 | reg = readl(mxc_spi->base + MXC_CSPICTRL); | 265 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
266 | reg |= MX27_CSPICTRL_XCH; | 266 | reg |= MX27_CSPICTRL_XCH; |
267 | writel(reg, mxc_spi->base + MXC_CSPICTRL); | 267 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
268 | } | 268 | } |
269 | 269 | ||
270 | static int mx27_config(struct mxc_spi_data *mxc_spi, | 270 | static int mx27_config(struct spi_imx_data *spi_imx, |
271 | struct mxc_spi_config *config) | 271 | struct spi_imx_config *config) |
272 | { | 272 | { |
273 | unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER; | 273 | unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER; |
274 | 274 | ||
275 | reg |= mxc_spi_clkdiv_1(mxc_spi->spi_clk, config->speed_hz) << | 275 | reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) << |
276 | MX27_CSPICTRL_DR_SHIFT; | 276 | MX27_CSPICTRL_DR_SHIFT; |
277 | reg |= config->bpw - 1; | 277 | reg |= config->bpw - 1; |
278 | 278 | ||
@@ -285,14 +285,14 @@ static int mx27_config(struct mxc_spi_data *mxc_spi, | |||
285 | if (config->cs < 0) | 285 | if (config->cs < 0) |
286 | reg |= (config->cs + 32) << MX27_CSPICTRL_CS_SHIFT; | 286 | reg |= (config->cs + 32) << MX27_CSPICTRL_CS_SHIFT; |
287 | 287 | ||
288 | writel(reg, mxc_spi->base + MXC_CSPICTRL); | 288 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
289 | 289 | ||
290 | return 0; | 290 | return 0; |
291 | } | 291 | } |
292 | 292 | ||
293 | static int mx27_rx_available(struct mxc_spi_data *mxc_spi) | 293 | static int mx27_rx_available(struct spi_imx_data *spi_imx) |
294 | { | 294 | { |
295 | return readl(mxc_spi->base + MXC_CSPIINT) & MX27_INTREG_RR; | 295 | return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR; |
296 | } | 296 | } |
297 | 297 | ||
298 | #define MX1_INTREG_RR (1 << 3) | 298 | #define MX1_INTREG_RR (1 << 3) |
@@ -306,7 +306,7 @@ static int mx27_rx_available(struct mxc_spi_data *mxc_spi) | |||
306 | #define MX1_CSPICTRL_MASTER (1 << 10) | 306 | #define MX1_CSPICTRL_MASTER (1 << 10) |
307 | #define MX1_CSPICTRL_DR_SHIFT 13 | 307 | #define MX1_CSPICTRL_DR_SHIFT 13 |
308 | 308 | ||
309 | static void mx1_intctrl(struct mxc_spi_data *mxc_spi, int enable) | 309 | static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) |
310 | { | 310 | { |
311 | unsigned int val = 0; | 311 | unsigned int val = 0; |
312 | 312 | ||
@@ -315,24 +315,24 @@ static void mx1_intctrl(struct mxc_spi_data *mxc_spi, int enable) | |||
315 | if (enable & MXC_INT_RR) | 315 | if (enable & MXC_INT_RR) |
316 | val |= MX1_INTREG_RREN; | 316 | val |= MX1_INTREG_RREN; |
317 | 317 | ||
318 | writel(val, mxc_spi->base + MXC_CSPIINT); | 318 | writel(val, spi_imx->base + MXC_CSPIINT); |
319 | } | 319 | } |
320 | 320 | ||
321 | static void mx1_trigger(struct mxc_spi_data *mxc_spi) | 321 | static void mx1_trigger(struct spi_imx_data *spi_imx) |
322 | { | 322 | { |
323 | unsigned int reg; | 323 | unsigned int reg; |
324 | 324 | ||
325 | reg = readl(mxc_spi->base + MXC_CSPICTRL); | 325 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
326 | reg |= MX1_CSPICTRL_XCH; | 326 | reg |= MX1_CSPICTRL_XCH; |
327 | writel(reg, mxc_spi->base + MXC_CSPICTRL); | 327 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
328 | } | 328 | } |
329 | 329 | ||
330 | static int mx1_config(struct mxc_spi_data *mxc_spi, | 330 | static int mx1_config(struct spi_imx_data *spi_imx, |
331 | struct mxc_spi_config *config) | 331 | struct spi_imx_config *config) |
332 | { | 332 | { |
333 | unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; | 333 | unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; |
334 | 334 | ||
335 | reg |= mxc_spi_clkdiv_2(mxc_spi->spi_clk, config->speed_hz) << | 335 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << |
336 | MX1_CSPICTRL_DR_SHIFT; | 336 | MX1_CSPICTRL_DR_SHIFT; |
337 | reg |= config->bpw - 1; | 337 | reg |= config->bpw - 1; |
338 | 338 | ||
@@ -341,156 +341,151 @@ static int mx1_config(struct mxc_spi_data *mxc_spi, | |||
341 | if (config->mode & SPI_CPOL) | 341 | if (config->mode & SPI_CPOL) |
342 | reg |= MX1_CSPICTRL_POL; | 342 | reg |= MX1_CSPICTRL_POL; |
343 | 343 | ||
344 | writel(reg, mxc_spi->base + MXC_CSPICTRL); | 344 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
345 | 345 | ||
346 | return 0; | 346 | return 0; |
347 | } | 347 | } |
348 | 348 | ||
349 | static int mx1_rx_available(struct mxc_spi_data *mxc_spi) | 349 | static int mx1_rx_available(struct spi_imx_data *spi_imx) |
350 | { | 350 | { |
351 | return readl(mxc_spi->base + MXC_CSPIINT) & MX1_INTREG_RR; | 351 | return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; |
352 | } | 352 | } |
353 | 353 | ||
354 | static void mxc_spi_chipselect(struct spi_device *spi, int is_active) | 354 | static void spi_imx_chipselect(struct spi_device *spi, int is_active) |
355 | { | 355 | { |
356 | struct mxc_spi_data *mxc_spi = spi_master_get_devdata(spi->master); | 356 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
357 | unsigned int cs = 0; | 357 | int gpio = spi_imx->chipselect[spi->chip_select]; |
358 | int gpio = mxc_spi->chipselect[spi->chip_select]; | 358 | int active = is_active != BITBANG_CS_INACTIVE; |
359 | struct mxc_spi_config config; | 359 | int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); |
360 | 360 | ||
361 | if (spi->mode & SPI_CS_HIGH) | 361 | if (gpio < 0) |
362 | cs = 1; | ||
363 | |||
364 | if (is_active == BITBANG_CS_INACTIVE) { | ||
365 | if (gpio >= 0) | ||
366 | gpio_set_value(gpio, !cs); | ||
367 | return; | 362 | return; |
368 | } | ||
369 | |||
370 | config.bpw = spi->bits_per_word; | ||
371 | config.speed_hz = spi->max_speed_hz; | ||
372 | config.mode = spi->mode; | ||
373 | config.cs = mxc_spi->chipselect[spi->chip_select]; | ||
374 | |||
375 | mxc_spi->config(mxc_spi, &config); | ||
376 | |||
377 | /* Initialize the functions for transfer */ | ||
378 | if (config.bpw <= 8) { | ||
379 | mxc_spi->rx = mxc_spi_buf_rx_u8; | ||
380 | mxc_spi->tx = mxc_spi_buf_tx_u8; | ||
381 | } else if (config.bpw <= 16) { | ||
382 | mxc_spi->rx = mxc_spi_buf_rx_u16; | ||
383 | mxc_spi->tx = mxc_spi_buf_tx_u16; | ||
384 | } else if (config.bpw <= 32) { | ||
385 | mxc_spi->rx = mxc_spi_buf_rx_u32; | ||
386 | mxc_spi->tx = mxc_spi_buf_tx_u32; | ||
387 | } else | ||
388 | BUG(); | ||
389 | 363 | ||
390 | if (gpio >= 0) | 364 | gpio_set_value(gpio, dev_is_lowactive ^ active); |
391 | gpio_set_value(gpio, cs); | ||
392 | |||
393 | return; | ||
394 | } | 365 | } |
395 | 366 | ||
396 | static void mxc_spi_push(struct mxc_spi_data *mxc_spi) | 367 | static void spi_imx_push(struct spi_imx_data *spi_imx) |
397 | { | 368 | { |
398 | while (mxc_spi->txfifo < 8) { | 369 | while (spi_imx->txfifo < 8) { |
399 | if (!mxc_spi->count) | 370 | if (!spi_imx->count) |
400 | break; | 371 | break; |
401 | mxc_spi->tx(mxc_spi); | 372 | spi_imx->tx(spi_imx); |
402 | mxc_spi->txfifo++; | 373 | spi_imx->txfifo++; |
403 | } | 374 | } |
404 | 375 | ||
405 | mxc_spi->trigger(mxc_spi); | 376 | spi_imx->trigger(spi_imx); |
406 | } | 377 | } |
407 | 378 | ||
408 | static irqreturn_t mxc_spi_isr(int irq, void *dev_id) | 379 | static irqreturn_t spi_imx_isr(int irq, void *dev_id) |
409 | { | 380 | { |
410 | struct mxc_spi_data *mxc_spi = dev_id; | 381 | struct spi_imx_data *spi_imx = dev_id; |
411 | 382 | ||
412 | while (mxc_spi->rx_available(mxc_spi)) { | 383 | while (spi_imx->rx_available(spi_imx)) { |
413 | mxc_spi->rx(mxc_spi); | 384 | spi_imx->rx(spi_imx); |
414 | mxc_spi->txfifo--; | 385 | spi_imx->txfifo--; |
415 | } | 386 | } |
416 | 387 | ||
417 | if (mxc_spi->count) { | 388 | if (spi_imx->count) { |
418 | mxc_spi_push(mxc_spi); | 389 | spi_imx_push(spi_imx); |
419 | return IRQ_HANDLED; | 390 | return IRQ_HANDLED; |
420 | } | 391 | } |
421 | 392 | ||
422 | if (mxc_spi->txfifo) { | 393 | if (spi_imx->txfifo) { |
423 | /* No data left to push, but still waiting for rx data, | 394 | /* No data left to push, but still waiting for rx data, |
424 | * enable receive data available interrupt. | 395 | * enable receive data available interrupt. |
425 | */ | 396 | */ |
426 | mxc_spi->intctrl(mxc_spi, MXC_INT_RR); | 397 | spi_imx->intctrl(spi_imx, MXC_INT_RR); |
427 | return IRQ_HANDLED; | 398 | return IRQ_HANDLED; |
428 | } | 399 | } |
429 | 400 | ||
430 | mxc_spi->intctrl(mxc_spi, 0); | 401 | spi_imx->intctrl(spi_imx, 0); |
431 | complete(&mxc_spi->xfer_done); | 402 | complete(&spi_imx->xfer_done); |
432 | 403 | ||
433 | return IRQ_HANDLED; | 404 | return IRQ_HANDLED; |
434 | } | 405 | } |
435 | 406 | ||
436 | static int mxc_spi_setupxfer(struct spi_device *spi, | 407 | static int spi_imx_setupxfer(struct spi_device *spi, |
437 | struct spi_transfer *t) | 408 | struct spi_transfer *t) |
438 | { | 409 | { |
439 | struct mxc_spi_data *mxc_spi = spi_master_get_devdata(spi->master); | 410 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
440 | struct mxc_spi_config config; | 411 | struct spi_imx_config config; |
441 | 412 | ||
442 | config.bpw = t ? t->bits_per_word : spi->bits_per_word; | 413 | config.bpw = t ? t->bits_per_word : spi->bits_per_word; |
443 | config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; | 414 | config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; |
444 | config.mode = spi->mode; | 415 | config.mode = spi->mode; |
416 | config.cs = spi_imx->chipselect[spi->chip_select]; | ||
417 | |||
418 | if (!config.speed_hz) | ||
419 | config.speed_hz = spi->max_speed_hz; | ||
420 | if (!config.bpw) | ||
421 | config.bpw = spi->bits_per_word; | ||
422 | if (!config.speed_hz) | ||
423 | config.speed_hz = spi->max_speed_hz; | ||
424 | |||
425 | /* Initialize the functions for transfer */ | ||
426 | if (config.bpw <= 8) { | ||
427 | spi_imx->rx = spi_imx_buf_rx_u8; | ||
428 | spi_imx->tx = spi_imx_buf_tx_u8; | ||
429 | } else if (config.bpw <= 16) { | ||
430 | spi_imx->rx = spi_imx_buf_rx_u16; | ||
431 | spi_imx->tx = spi_imx_buf_tx_u16; | ||
432 | } else if (config.bpw <= 32) { | ||
433 | spi_imx->rx = spi_imx_buf_rx_u32; | ||
434 | spi_imx->tx = spi_imx_buf_tx_u32; | ||
435 | } else | ||
436 | BUG(); | ||
445 | 437 | ||
446 | mxc_spi->config(mxc_spi, &config); | 438 | spi_imx->config(spi_imx, &config); |
447 | 439 | ||
448 | return 0; | 440 | return 0; |
449 | } | 441 | } |
450 | 442 | ||
451 | static int mxc_spi_transfer(struct spi_device *spi, | 443 | static int spi_imx_transfer(struct spi_device *spi, |
452 | struct spi_transfer *transfer) | 444 | struct spi_transfer *transfer) |
453 | { | 445 | { |
454 | struct mxc_spi_data *mxc_spi = spi_master_get_devdata(spi->master); | 446 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
455 | 447 | ||
456 | mxc_spi->tx_buf = transfer->tx_buf; | 448 | spi_imx->tx_buf = transfer->tx_buf; |
457 | mxc_spi->rx_buf = transfer->rx_buf; | 449 | spi_imx->rx_buf = transfer->rx_buf; |
458 | mxc_spi->count = transfer->len; | 450 | spi_imx->count = transfer->len; |
459 | mxc_spi->txfifo = 0; | 451 | spi_imx->txfifo = 0; |
460 | 452 | ||
461 | init_completion(&mxc_spi->xfer_done); | 453 | init_completion(&spi_imx->xfer_done); |
462 | 454 | ||
463 | mxc_spi_push(mxc_spi); | 455 | spi_imx_push(spi_imx); |
464 | 456 | ||
465 | mxc_spi->intctrl(mxc_spi, MXC_INT_TE); | 457 | spi_imx->intctrl(spi_imx, MXC_INT_TE); |
466 | 458 | ||
467 | wait_for_completion(&mxc_spi->xfer_done); | 459 | wait_for_completion(&spi_imx->xfer_done); |
468 | 460 | ||
469 | return transfer->len; | 461 | return transfer->len; |
470 | } | 462 | } |
471 | 463 | ||
472 | static int mxc_spi_setup(struct spi_device *spi) | 464 | static int spi_imx_setup(struct spi_device *spi) |
473 | { | 465 | { |
474 | if (!spi->bits_per_word) | 466 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
475 | spi->bits_per_word = 8; | 467 | int gpio = spi_imx->chipselect[spi->chip_select]; |
476 | 468 | ||
477 | pr_debug("%s: mode %d, %u bpw, %d hz\n", __func__, | 469 | pr_debug("%s: mode %d, %u bpw, %d hz\n", __func__, |
478 | spi->mode, spi->bits_per_word, spi->max_speed_hz); | 470 | spi->mode, spi->bits_per_word, spi->max_speed_hz); |
479 | 471 | ||
480 | mxc_spi_chipselect(spi, BITBANG_CS_INACTIVE); | 472 | if (gpio >= 0) |
473 | gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); | ||
474 | |||
475 | spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); | ||
481 | 476 | ||
482 | return 0; | 477 | return 0; |
483 | } | 478 | } |
484 | 479 | ||
485 | static void mxc_spi_cleanup(struct spi_device *spi) | 480 | static void spi_imx_cleanup(struct spi_device *spi) |
486 | { | 481 | { |
487 | } | 482 | } |
488 | 483 | ||
489 | static int __init mxc_spi_probe(struct platform_device *pdev) | 484 | static int __init spi_imx_probe(struct platform_device *pdev) |
490 | { | 485 | { |
491 | struct spi_imx_master *mxc_platform_info; | 486 | struct spi_imx_master *mxc_platform_info; |
492 | struct spi_master *master; | 487 | struct spi_master *master; |
493 | struct mxc_spi_data *mxc_spi; | 488 | struct spi_imx_data *spi_imx; |
494 | struct resource *res; | 489 | struct resource *res; |
495 | int i, ret; | 490 | int i, ret; |
496 | 491 | ||
@@ -500,7 +495,7 @@ static int __init mxc_spi_probe(struct platform_device *pdev) | |||
500 | return -EINVAL; | 495 | return -EINVAL; |
501 | } | 496 | } |
502 | 497 | ||
503 | master = spi_alloc_master(&pdev->dev, sizeof(struct mxc_spi_data)); | 498 | master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data)); |
504 | if (!master) | 499 | if (!master) |
505 | return -ENOMEM; | 500 | return -ENOMEM; |
506 | 501 | ||
@@ -509,32 +504,32 @@ static int __init mxc_spi_probe(struct platform_device *pdev) | |||
509 | master->bus_num = pdev->id; | 504 | master->bus_num = pdev->id; |
510 | master->num_chipselect = mxc_platform_info->num_chipselect; | 505 | master->num_chipselect = mxc_platform_info->num_chipselect; |
511 | 506 | ||
512 | mxc_spi = spi_master_get_devdata(master); | 507 | spi_imx = spi_master_get_devdata(master); |
513 | mxc_spi->bitbang.master = spi_master_get(master); | 508 | spi_imx->bitbang.master = spi_master_get(master); |
514 | mxc_spi->chipselect = mxc_platform_info->chipselect; | 509 | spi_imx->chipselect = mxc_platform_info->chipselect; |
515 | 510 | ||
516 | for (i = 0; i < master->num_chipselect; i++) { | 511 | for (i = 0; i < master->num_chipselect; i++) { |
517 | if (mxc_spi->chipselect[i] < 0) | 512 | if (spi_imx->chipselect[i] < 0) |
518 | continue; | 513 | continue; |
519 | ret = gpio_request(mxc_spi->chipselect[i], DRIVER_NAME); | 514 | ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME); |
520 | if (ret) { | 515 | if (ret) { |
521 | i--; | 516 | i--; |
522 | while (i > 0) | 517 | while (i > 0) |
523 | if (mxc_spi->chipselect[i] >= 0) | 518 | if (spi_imx->chipselect[i] >= 0) |
524 | gpio_free(mxc_spi->chipselect[i--]); | 519 | gpio_free(spi_imx->chipselect[i--]); |
525 | dev_err(&pdev->dev, "can't get cs gpios"); | 520 | dev_err(&pdev->dev, "can't get cs gpios"); |
526 | goto out_master_put; | 521 | goto out_master_put; |
527 | } | 522 | } |
528 | gpio_direction_output(mxc_spi->chipselect[i], 1); | ||
529 | } | 523 | } |
530 | 524 | ||
531 | mxc_spi->bitbang.chipselect = mxc_spi_chipselect; | 525 | spi_imx->bitbang.chipselect = spi_imx_chipselect; |
532 | mxc_spi->bitbang.setup_transfer = mxc_spi_setupxfer; | 526 | spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; |
533 | mxc_spi->bitbang.txrx_bufs = mxc_spi_transfer; | 527 | spi_imx->bitbang.txrx_bufs = spi_imx_transfer; |
534 | mxc_spi->bitbang.master->setup = mxc_spi_setup; | 528 | spi_imx->bitbang.master->setup = spi_imx_setup; |
535 | mxc_spi->bitbang.master->cleanup = mxc_spi_cleanup; | 529 | spi_imx->bitbang.master->cleanup = spi_imx_cleanup; |
530 | spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | ||
536 | 531 | ||
537 | init_completion(&mxc_spi->xfer_done); | 532 | init_completion(&spi_imx->xfer_done); |
538 | 533 | ||
539 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 534 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
540 | if (!res) { | 535 | if (!res) { |
@@ -549,58 +544,58 @@ static int __init mxc_spi_probe(struct platform_device *pdev) | |||
549 | goto out_gpio_free; | 544 | goto out_gpio_free; |
550 | } | 545 | } |
551 | 546 | ||
552 | mxc_spi->base = ioremap(res->start, resource_size(res)); | 547 | spi_imx->base = ioremap(res->start, resource_size(res)); |
553 | if (!mxc_spi->base) { | 548 | if (!spi_imx->base) { |
554 | ret = -EINVAL; | 549 | ret = -EINVAL; |
555 | goto out_release_mem; | 550 | goto out_release_mem; |
556 | } | 551 | } |
557 | 552 | ||
558 | mxc_spi->irq = platform_get_irq(pdev, 0); | 553 | spi_imx->irq = platform_get_irq(pdev, 0); |
559 | if (!mxc_spi->irq) { | 554 | if (!spi_imx->irq) { |
560 | ret = -EINVAL; | 555 | ret = -EINVAL; |
561 | goto out_iounmap; | 556 | goto out_iounmap; |
562 | } | 557 | } |
563 | 558 | ||
564 | ret = request_irq(mxc_spi->irq, mxc_spi_isr, 0, DRIVER_NAME, mxc_spi); | 559 | ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx); |
565 | if (ret) { | 560 | if (ret) { |
566 | dev_err(&pdev->dev, "can't get irq%d: %d\n", mxc_spi->irq, ret); | 561 | dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret); |
567 | goto out_iounmap; | 562 | goto out_iounmap; |
568 | } | 563 | } |
569 | 564 | ||
570 | if (cpu_is_mx31() || cpu_is_mx35()) { | 565 | if (cpu_is_mx31() || cpu_is_mx35()) { |
571 | mxc_spi->intctrl = mx31_intctrl; | 566 | spi_imx->intctrl = mx31_intctrl; |
572 | mxc_spi->config = mx31_config; | 567 | spi_imx->config = mx31_config; |
573 | mxc_spi->trigger = mx31_trigger; | 568 | spi_imx->trigger = mx31_trigger; |
574 | mxc_spi->rx_available = mx31_rx_available; | 569 | spi_imx->rx_available = mx31_rx_available; |
575 | } else if (cpu_is_mx27() || cpu_is_mx21()) { | 570 | } else if (cpu_is_mx27() || cpu_is_mx21()) { |
576 | mxc_spi->intctrl = mx27_intctrl; | 571 | spi_imx->intctrl = mx27_intctrl; |
577 | mxc_spi->config = mx27_config; | 572 | spi_imx->config = mx27_config; |
578 | mxc_spi->trigger = mx27_trigger; | 573 | spi_imx->trigger = mx27_trigger; |
579 | mxc_spi->rx_available = mx27_rx_available; | 574 | spi_imx->rx_available = mx27_rx_available; |
580 | } else if (cpu_is_mx1()) { | 575 | } else if (cpu_is_mx1()) { |
581 | mxc_spi->intctrl = mx1_intctrl; | 576 | spi_imx->intctrl = mx1_intctrl; |
582 | mxc_spi->config = mx1_config; | 577 | spi_imx->config = mx1_config; |
583 | mxc_spi->trigger = mx1_trigger; | 578 | spi_imx->trigger = mx1_trigger; |
584 | mxc_spi->rx_available = mx1_rx_available; | 579 | spi_imx->rx_available = mx1_rx_available; |
585 | } else | 580 | } else |
586 | BUG(); | 581 | BUG(); |
587 | 582 | ||
588 | mxc_spi->clk = clk_get(&pdev->dev, NULL); | 583 | spi_imx->clk = clk_get(&pdev->dev, NULL); |
589 | if (IS_ERR(mxc_spi->clk)) { | 584 | if (IS_ERR(spi_imx->clk)) { |
590 | dev_err(&pdev->dev, "unable to get clock\n"); | 585 | dev_err(&pdev->dev, "unable to get clock\n"); |
591 | ret = PTR_ERR(mxc_spi->clk); | 586 | ret = PTR_ERR(spi_imx->clk); |
592 | goto out_free_irq; | 587 | goto out_free_irq; |
593 | } | 588 | } |
594 | 589 | ||
595 | clk_enable(mxc_spi->clk); | 590 | clk_enable(spi_imx->clk); |
596 | mxc_spi->spi_clk = clk_get_rate(mxc_spi->clk); | 591 | spi_imx->spi_clk = clk_get_rate(spi_imx->clk); |
597 | 592 | ||
598 | if (!cpu_is_mx31() || !cpu_is_mx35()) | 593 | if (!cpu_is_mx31() || !cpu_is_mx35()) |
599 | writel(1, mxc_spi->base + MXC_RESET); | 594 | writel(1, spi_imx->base + MXC_RESET); |
600 | 595 | ||
601 | mxc_spi->intctrl(mxc_spi, 0); | 596 | spi_imx->intctrl(spi_imx, 0); |
602 | 597 | ||
603 | ret = spi_bitbang_start(&mxc_spi->bitbang); | 598 | ret = spi_bitbang_start(&spi_imx->bitbang); |
604 | if (ret) { | 599 | if (ret) { |
605 | dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); | 600 | dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); |
606 | goto out_clk_put; | 601 | goto out_clk_put; |
@@ -611,18 +606,18 @@ static int __init mxc_spi_probe(struct platform_device *pdev) | |||
611 | return ret; | 606 | return ret; |
612 | 607 | ||
613 | out_clk_put: | 608 | out_clk_put: |
614 | clk_disable(mxc_spi->clk); | 609 | clk_disable(spi_imx->clk); |
615 | clk_put(mxc_spi->clk); | 610 | clk_put(spi_imx->clk); |
616 | out_free_irq: | 611 | out_free_irq: |
617 | free_irq(mxc_spi->irq, mxc_spi); | 612 | free_irq(spi_imx->irq, spi_imx); |
618 | out_iounmap: | 613 | out_iounmap: |
619 | iounmap(mxc_spi->base); | 614 | iounmap(spi_imx->base); |
620 | out_release_mem: | 615 | out_release_mem: |
621 | release_mem_region(res->start, resource_size(res)); | 616 | release_mem_region(res->start, resource_size(res)); |
622 | out_gpio_free: | 617 | out_gpio_free: |
623 | for (i = 0; i < master->num_chipselect; i++) | 618 | for (i = 0; i < master->num_chipselect; i++) |
624 | if (mxc_spi->chipselect[i] >= 0) | 619 | if (spi_imx->chipselect[i] >= 0) |
625 | gpio_free(mxc_spi->chipselect[i]); | 620 | gpio_free(spi_imx->chipselect[i]); |
626 | out_master_put: | 621 | out_master_put: |
627 | spi_master_put(master); | 622 | spi_master_put(master); |
628 | kfree(master); | 623 | kfree(master); |
@@ -630,24 +625,24 @@ out_master_put: | |||
630 | return ret; | 625 | return ret; |
631 | } | 626 | } |
632 | 627 | ||
633 | static int __exit mxc_spi_remove(struct platform_device *pdev) | 628 | static int __exit spi_imx_remove(struct platform_device *pdev) |
634 | { | 629 | { |
635 | struct spi_master *master = platform_get_drvdata(pdev); | 630 | struct spi_master *master = platform_get_drvdata(pdev); |
636 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 631 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
637 | struct mxc_spi_data *mxc_spi = spi_master_get_devdata(master); | 632 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); |
638 | int i; | 633 | int i; |
639 | 634 | ||
640 | spi_bitbang_stop(&mxc_spi->bitbang); | 635 | spi_bitbang_stop(&spi_imx->bitbang); |
641 | 636 | ||
642 | writel(0, mxc_spi->base + MXC_CSPICTRL); | 637 | writel(0, spi_imx->base + MXC_CSPICTRL); |
643 | clk_disable(mxc_spi->clk); | 638 | clk_disable(spi_imx->clk); |
644 | clk_put(mxc_spi->clk); | 639 | clk_put(spi_imx->clk); |
645 | free_irq(mxc_spi->irq, mxc_spi); | 640 | free_irq(spi_imx->irq, spi_imx); |
646 | iounmap(mxc_spi->base); | 641 | iounmap(spi_imx->base); |
647 | 642 | ||
648 | for (i = 0; i < master->num_chipselect; i++) | 643 | for (i = 0; i < master->num_chipselect; i++) |
649 | if (mxc_spi->chipselect[i] >= 0) | 644 | if (spi_imx->chipselect[i] >= 0) |
650 | gpio_free(mxc_spi->chipselect[i]); | 645 | gpio_free(spi_imx->chipselect[i]); |
651 | 646 | ||
652 | spi_master_put(master); | 647 | spi_master_put(master); |
653 | 648 | ||
@@ -658,27 +653,27 @@ static int __exit mxc_spi_remove(struct platform_device *pdev) | |||
658 | return 0; | 653 | return 0; |
659 | } | 654 | } |
660 | 655 | ||
661 | static struct platform_driver mxc_spi_driver = { | 656 | static struct platform_driver spi_imx_driver = { |
662 | .driver = { | 657 | .driver = { |
663 | .name = DRIVER_NAME, | 658 | .name = DRIVER_NAME, |
664 | .owner = THIS_MODULE, | 659 | .owner = THIS_MODULE, |
665 | }, | 660 | }, |
666 | .probe = mxc_spi_probe, | 661 | .probe = spi_imx_probe, |
667 | .remove = __exit_p(mxc_spi_remove), | 662 | .remove = __exit_p(spi_imx_remove), |
668 | }; | 663 | }; |
669 | 664 | ||
670 | static int __init mxc_spi_init(void) | 665 | static int __init spi_imx_init(void) |
671 | { | 666 | { |
672 | return platform_driver_register(&mxc_spi_driver); | 667 | return platform_driver_register(&spi_imx_driver); |
673 | } | 668 | } |
674 | 669 | ||
675 | static void __exit mxc_spi_exit(void) | 670 | static void __exit spi_imx_exit(void) |
676 | { | 671 | { |
677 | platform_driver_unregister(&mxc_spi_driver); | 672 | platform_driver_unregister(&spi_imx_driver); |
678 | } | 673 | } |
679 | 674 | ||
680 | module_init(mxc_spi_init); | 675 | module_init(spi_imx_init); |
681 | module_exit(mxc_spi_exit); | 676 | module_exit(spi_imx_exit); |
682 | 677 | ||
683 | MODULE_DESCRIPTION("SPI Master Controller driver"); | 678 | MODULE_DESCRIPTION("SPI Master Controller driver"); |
684 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | 679 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); |
diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c index f921bd1109e1..5d23983f02fc 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c | |||
@@ -537,7 +537,7 @@ static int spidev_release(struct inode *inode, struct file *filp) | |||
537 | return status; | 537 | return status; |
538 | } | 538 | } |
539 | 539 | ||
540 | static struct file_operations spidev_fops = { | 540 | static const struct file_operations spidev_fops = { |
541 | .owner = THIS_MODULE, | 541 | .owner = THIS_MODULE, |
542 | /* REVISIT switch to aio primitives, so that userspace | 542 | /* REVISIT switch to aio primitives, so that userspace |
543 | * gets more complete API coverage. It'll simplify things | 543 | * gets more complete API coverage. It'll simplify things |
diff --git a/drivers/staging/dst/dcore.c b/drivers/staging/dst/dcore.c index 5e8db0677582..c24e4e0367a2 100644 --- a/drivers/staging/dst/dcore.c +++ b/drivers/staging/dst/dcore.c | |||
@@ -847,7 +847,7 @@ static dst_command_func dst_commands[] = { | |||
847 | /* | 847 | /* |
848 | * Configuration parser. | 848 | * Configuration parser. |
849 | */ | 849 | */ |
850 | static void cn_dst_callback(struct cn_msg *msg) | 850 | static void cn_dst_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp) |
851 | { | 851 | { |
852 | struct dst_ctl *ctl; | 852 | struct dst_ctl *ctl; |
853 | int err; | 853 | int err; |
@@ -855,6 +855,11 @@ static void cn_dst_callback(struct cn_msg *msg) | |||
855 | struct dst_node *n = NULL, *tmp; | 855 | struct dst_node *n = NULL, *tmp; |
856 | unsigned int hash; | 856 | unsigned int hash; |
857 | 857 | ||
858 | if (!cap_raised(nsp->eff_cap, CAP_SYS_ADMIN)) { | ||
859 | err = -EPERM; | ||
860 | goto out; | ||
861 | } | ||
862 | |||
858 | if (msg->len < sizeof(struct dst_ctl)) { | 863 | if (msg->len < sizeof(struct dst_ctl)) { |
859 | err = -EBADMSG; | 864 | err = -EBADMSG; |
860 | goto out; | 865 | goto out; |
diff --git a/drivers/staging/pohmelfs/config.c b/drivers/staging/pohmelfs/config.c index 90f962ee5fd8..5d04bf5b021a 100644 --- a/drivers/staging/pohmelfs/config.c +++ b/drivers/staging/pohmelfs/config.c | |||
@@ -527,10 +527,13 @@ out_unlock: | |||
527 | return err; | 527 | return err; |
528 | } | 528 | } |
529 | 529 | ||
530 | static void pohmelfs_cn_callback(struct cn_msg *msg) | 530 | static void pohmelfs_cn_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp) |
531 | { | 531 | { |
532 | int err; | 532 | int err; |
533 | 533 | ||
534 | if (!cap_raised(nsp->eff_cap, CAP_SYS_ADMIN)) | ||
535 | return; | ||
536 | |||
534 | switch (msg->flags) { | 537 | switch (msg->flags) { |
535 | case POHMELFS_FLAGS_ADD: | 538 | case POHMELFS_FLAGS_ADD: |
536 | case POHMELFS_FLAGS_DEL: | 539 | case POHMELFS_FLAGS_DEL: |
diff --git a/drivers/usb/class/usbtmc.c b/drivers/usb/class/usbtmc.c index 333ee02e7b2b..864f0ba6a344 100644 --- a/drivers/usb/class/usbtmc.c +++ b/drivers/usb/class/usbtmc.c | |||
@@ -993,7 +993,7 @@ skip_io_on_zombie: | |||
993 | return retval; | 993 | return retval; |
994 | } | 994 | } |
995 | 995 | ||
996 | static struct file_operations fops = { | 996 | static const struct file_operations fops = { |
997 | .owner = THIS_MODULE, | 997 | .owner = THIS_MODULE, |
998 | .read = usbtmc_read, | 998 | .read = usbtmc_read, |
999 | .write = usbtmc_write, | 999 | .write = usbtmc_write, |
diff --git a/drivers/usb/gadget/printer.c b/drivers/usb/gadget/printer.c index 29500154d00c..2d867fd22413 100644 --- a/drivers/usb/gadget/printer.c +++ b/drivers/usb/gadget/printer.c | |||
@@ -875,7 +875,7 @@ printer_ioctl(struct file *fd, unsigned int code, unsigned long arg) | |||
875 | } | 875 | } |
876 | 876 | ||
877 | /* used after endpoint configuration */ | 877 | /* used after endpoint configuration */ |
878 | static struct file_operations printer_io_operations = { | 878 | static const struct file_operations printer_io_operations = { |
879 | .owner = THIS_MODULE, | 879 | .owner = THIS_MODULE, |
880 | .open = printer_open, | 880 | .open = printer_open, |
881 | .read = printer_read, | 881 | .read = printer_read, |
diff --git a/drivers/usb/host/whci/debug.c b/drivers/usb/host/whci/debug.c index cf2d45946c57..2273c815941f 100644 --- a/drivers/usb/host/whci/debug.c +++ b/drivers/usb/host/whci/debug.c | |||
@@ -134,7 +134,7 @@ static int pzl_open(struct inode *inode, struct file *file) | |||
134 | return single_open(file, pzl_print, inode->i_private); | 134 | return single_open(file, pzl_print, inode->i_private); |
135 | } | 135 | } |
136 | 136 | ||
137 | static struct file_operations di_fops = { | 137 | static const struct file_operations di_fops = { |
138 | .open = di_open, | 138 | .open = di_open, |
139 | .read = seq_read, | 139 | .read = seq_read, |
140 | .llseek = seq_lseek, | 140 | .llseek = seq_lseek, |
@@ -142,7 +142,7 @@ static struct file_operations di_fops = { | |||
142 | .owner = THIS_MODULE, | 142 | .owner = THIS_MODULE, |
143 | }; | 143 | }; |
144 | 144 | ||
145 | static struct file_operations asl_fops = { | 145 | static const struct file_operations asl_fops = { |
146 | .open = asl_open, | 146 | .open = asl_open, |
147 | .read = seq_read, | 147 | .read = seq_read, |
148 | .llseek = seq_lseek, | 148 | .llseek = seq_lseek, |
@@ -150,7 +150,7 @@ static struct file_operations asl_fops = { | |||
150 | .owner = THIS_MODULE, | 150 | .owner = THIS_MODULE, |
151 | }; | 151 | }; |
152 | 152 | ||
153 | static struct file_operations pzl_fops = { | 153 | static const struct file_operations pzl_fops = { |
154 | .open = pzl_open, | 154 | .open = pzl_open, |
155 | .read = seq_read, | 155 | .read = seq_read, |
156 | .llseek = seq_lseek, | 156 | .llseek = seq_lseek, |
diff --git a/drivers/usb/misc/rio500.c b/drivers/usb/misc/rio500.c index d645f3899fe1..32d0199d0c32 100644 --- a/drivers/usb/misc/rio500.c +++ b/drivers/usb/misc/rio500.c | |||
@@ -429,8 +429,7 @@ read_rio(struct file *file, char __user *buffer, size_t count, loff_t * ppos) | |||
429 | return read_count; | 429 | return read_count; |
430 | } | 430 | } |
431 | 431 | ||
432 | static struct | 432 | static const struct file_operations usb_rio_fops = { |
433 | file_operations usb_rio_fops = { | ||
434 | .owner = THIS_MODULE, | 433 | .owner = THIS_MODULE, |
435 | .read = read_rio, | 434 | .read = read_rio, |
436 | .write = write_rio, | 435 | .write = write_rio, |
diff --git a/drivers/uwb/uwb-debug.c b/drivers/uwb/uwb-debug.c index 4a42993700c1..2eecec0c13c9 100644 --- a/drivers/uwb/uwb-debug.c +++ b/drivers/uwb/uwb-debug.c | |||
@@ -205,7 +205,7 @@ static ssize_t command_write(struct file *file, const char __user *buf, | |||
205 | return ret < 0 ? ret : len; | 205 | return ret < 0 ? ret : len; |
206 | } | 206 | } |
207 | 207 | ||
208 | static struct file_operations command_fops = { | 208 | static const struct file_operations command_fops = { |
209 | .open = command_open, | 209 | .open = command_open, |
210 | .write = command_write, | 210 | .write = command_write, |
211 | .read = NULL, | 211 | .read = NULL, |
@@ -255,7 +255,7 @@ static int reservations_open(struct inode *inode, struct file *file) | |||
255 | return single_open(file, reservations_print, inode->i_private); | 255 | return single_open(file, reservations_print, inode->i_private); |
256 | } | 256 | } |
257 | 257 | ||
258 | static struct file_operations reservations_fops = { | 258 | static const struct file_operations reservations_fops = { |
259 | .open = reservations_open, | 259 | .open = reservations_open, |
260 | .read = seq_read, | 260 | .read = seq_read, |
261 | .llseek = seq_lseek, | 261 | .llseek = seq_lseek, |
@@ -283,7 +283,7 @@ static int drp_avail_open(struct inode *inode, struct file *file) | |||
283 | return single_open(file, drp_avail_print, inode->i_private); | 283 | return single_open(file, drp_avail_print, inode->i_private); |
284 | } | 284 | } |
285 | 285 | ||
286 | static struct file_operations drp_avail_fops = { | 286 | static const struct file_operations drp_avail_fops = { |
287 | .open = drp_avail_open, | 287 | .open = drp_avail_open, |
288 | .read = seq_read, | 288 | .read = seq_read, |
289 | .llseek = seq_lseek, | 289 | .llseek = seq_lseek, |
diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c index a1f2e7ce730b..99bbd282ce63 100644 --- a/drivers/video/fbmem.c +++ b/drivers/video/fbmem.c | |||
@@ -1800,7 +1800,7 @@ static int __init video_setup(char *options) | |||
1800 | global = 1; | 1800 | global = 1; |
1801 | } | 1801 | } |
1802 | 1802 | ||
1803 | if (!global && !strstr(options, "fb:")) { | 1803 | if (!global && !strchr(options, ':')) { |
1804 | fb_mode_option = options; | 1804 | fb_mode_option = options; |
1805 | global = 1; | 1805 | global = 1; |
1806 | } | 1806 | } |
diff --git a/drivers/video/uvesafb.c b/drivers/video/uvesafb.c index e98baf6916b8..e35232a18571 100644 --- a/drivers/video/uvesafb.c +++ b/drivers/video/uvesafb.c | |||
@@ -67,11 +67,14 @@ static DEFINE_MUTEX(uvfb_lock); | |||
67 | * find the kernel part of the task struct, copy the registers and | 67 | * find the kernel part of the task struct, copy the registers and |
68 | * the buffer contents and then complete the task. | 68 | * the buffer contents and then complete the task. |
69 | */ | 69 | */ |
70 | static void uvesafb_cn_callback(struct cn_msg *msg) | 70 | static void uvesafb_cn_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp) |
71 | { | 71 | { |
72 | struct uvesafb_task *utask; | 72 | struct uvesafb_task *utask; |
73 | struct uvesafb_ktask *task; | 73 | struct uvesafb_ktask *task; |
74 | 74 | ||
75 | if (!cap_raised(nsp->eff_cap, CAP_SYS_ADMIN)) | ||
76 | return; | ||
77 | |||
75 | if (msg->seq >= UVESAFB_TASKS_MAX) | 78 | if (msg->seq >= UVESAFB_TASKS_MAX) |
76 | return; | 79 | return; |
77 | 80 | ||
diff --git a/drivers/w1/w1_netlink.c b/drivers/w1/w1_netlink.c index 52ccb3d3a963..45c126fea31d 100644 --- a/drivers/w1/w1_netlink.c +++ b/drivers/w1/w1_netlink.c | |||
@@ -306,7 +306,7 @@ static int w1_netlink_send_error(struct cn_msg *rcmsg, struct w1_netlink_msg *rm | |||
306 | return error; | 306 | return error; |
307 | } | 307 | } |
308 | 308 | ||
309 | static void w1_cn_callback(struct cn_msg *msg) | 309 | static void w1_cn_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp) |
310 | { | 310 | { |
311 | struct w1_netlink_msg *m = (struct w1_netlink_msg *)(msg + 1); | 311 | struct w1_netlink_msg *m = (struct w1_netlink_msg *)(msg + 1); |
312 | struct w1_netlink_cmd *cmd; | 312 | struct w1_netlink_cmd *cmd; |