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-rw-r--r--drivers/serial/imx.c15
1 files changed, 13 insertions, 2 deletions
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c
index 20189c447e92..312653e2f715 100644
--- a/drivers/serial/imx.c
+++ b/drivers/serial/imx.c
@@ -127,8 +127,13 @@
127#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ 127#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
128#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ 128#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
129#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ 129#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
130#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ 130#ifdef CONFIG_ARCH_IMX
131#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ 131#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz, only on mx1 */
132#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz, only on mx1 */
133#endif
134#if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3
135#define UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select, on mx2/mx3 */
136#endif
132#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ 137#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
133#define UCR3_BPEN (1<<0) /* Preset registers enable */ 138#define UCR3_BPEN (1<<0) /* Preset registers enable */
134#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ 139#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
@@ -598,6 +603,12 @@ static int imx_startup(struct uart_port *port)
598 temp |= (UCR2_RXEN | UCR2_TXEN); 603 temp |= (UCR2_RXEN | UCR2_TXEN);
599 writel(temp, sport->port.membase + UCR2); 604 writel(temp, sport->port.membase + UCR2);
600 605
606#if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3
607 temp = readl(sport->port.membase + UCR3);
608 temp |= UCR3_RXDMUXSEL;
609 writel(temp, sport->port.membase + UCR3);
610#endif
611
601 /* 612 /*
602 * Enable modem status interrupts 613 * Enable modem status interrupts
603 */ 614 */