4 files changed, 101 insertions, 21 deletions

diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index f72a4f57905a..bf776125ca38 100644
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -260,15 +260,17 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
 #define RPC_LSA_DEFAULT         RPC_LED_TX_RX
 #define RPC_LSB_DEFAULT         RPC_LED_100_10
 
-#elif   defined(CONFIG_MACH_LPD7A400) || defined(CONFIG_MACH_LPD7A404)
+#elif   defined(CONFIG_MACH_LPD79520) \
+     || defined(CONFIG_MACH_LPD7A400) \
+     || defined(CONFIG_MACH_LPD7A404)
 
-/* The LPD7A40X_IOBARRIER is necessary to overcome a mismatch between
- * the way that the CPU handles chip selects and the way that the SMC
- * chip expects the chip select to operate.  Refer to
+/* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
+ * way that the CPU handles chip selects and the way that the SMC chip
+ * expects the chip select to operate.  Refer to
  * Documentation/arm/Sharp-LH/IOBarrier for details.  The read from
- * IOBARRIER is a byte as a least-common denominator of possible
- * regions to use as the barrier.  It would be wasteful to read 32
- * bits from a byte oriented region.
+ * IOBARRIER is a byte, in order that we read the least-common
+ * denominator.  It would be wasteful to read 32 bits from an 8-bit
+ * accessible region.
  *
  * There is no explicit protection against interrupts intervening
  * between the writew and the IOBARRIER.  In SMC ISR there is a
@@ -287,25 +289,35 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
 #define SMC_CAN_USE_16BIT       1
 #define SMC_CAN_USE_32BIT       0
 #define SMC_NOWAIT              0
-#define LPD7A40X_IOBARRIER      readb (IOBARRIER_VIRT)
+#define LPD7X_IOBARRIER         readb (IOBARRIER_VIRT)
 
-#define SMC_inw(a,r)            readw ((void*) ((a) + (r)))
-#define SMC_insw(a,r,p,l)       readsw ((void*) ((a) + (r)), p, l)
-#define SMC_outw(v,a,r)      ({ writew ((v), (a) + (r)); LPD7A40X_IOBARRIER; })
+#define SMC_inw(a,r)\
+   ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
+#define SMC_outw(v,a,r)   ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
 
-#define SMC_outsw               LPD7A40X_SMC_outsw
+#define SMC_insw                LPD7_SMC_insw
+static inline void LPD7_SMC_insw (unsigned char* a, int r,
+                                  unsigned char* p, int l)
+{
+        unsigned short* ps = (unsigned short*) p;
+        while (l-- > 0) {
+                *ps++ = readw (a + r);
+                LPD7X_IOBARRIER;
+        }
+}
 
-static inline void LPD7A40X_SMC_outsw(unsigned long a, int r,
-                                     unsigned char* p, int l)
+#define SMC_outsw               LPD7_SMC_outsw
+static inline void LPD7_SMC_outsw (unsigned char* a, int r,
+                                   unsigned char* p, int l)
 {
         unsigned short* ps = (unsigned short*) p;
         while (l-- > 0) {
                 writew (*ps++, a + r);
-                LPD7A40X_IOBARRIER;
+                LPD7X_IOBARRIER;
         }
 }
 
-#define SMC_INTERRUPT_PREAMBLE  LPD7A40X_IOBARRIER
+#define SMC_INTERRUPT_PREAMBLE  LPD7X_IOBARRIER
 
 #define RPC_LSA_DEFAULT         RPC_LED_TX_RX
 #define RPC_LSB_DEFAULT         RPC_LED_100_10
diff --git a/drivers/serial/s3c2410.c b/drivers/serial/s3c2410.c
index f5aac92fb798..53c2465bad2d 100644
--- a/drivers/serial/s3c2410.c
+++ b/drivers/serial/s3c2410.c
@@ -1365,7 +1365,7 @@ static inline void s3c2410_serial_exit(void)
 
 #endif /* CONFIG_CPU_S3C2410 */
 
-#ifdef CONFIG_CPU_S3C2440
+#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
 
 static int s3c2440_serial_setsource(struct uart_port *port,
                                      struct s3c24xx_uart_clksrc *clk)
diff --git a/drivers/serial/serial_lh7a40x.c b/drivers/serial/serial_lh7a40x.c
index aa521b8e0d4e..776d4ff06084 100644
--- a/drivers/serial/serial_lh7a40x.c
+++ b/drivers/serial/serial_lh7a40x.c
@@ -145,14 +145,15 @@ lh7a40xuart_rx_chars (struct uart_port* port)
 {
         struct tty_struct* tty = port->info->tty;
         int cbRxMax = 256;      /* (Gross) limit on receive */
-        unsigned int data, flag;/* Received data and status */
+        unsigned int data;      /* Received data and status */
+        unsigned int flag;
 
         while (!(UR (port, UART_R_STATUS) & nRxRdy) && --cbRxMax) {
                 data = UR (port, UART_R_DATA);
                 flag = TTY_NORMAL;
                 ++port->icount.rx;
 
-                if (unlikely(data & RxError)) { /* Quick check, short-circuit */
+                if (unlikely(data & RxError)) {
                         if (data & RxBreak) {
                                 data &= ~(RxFramingError | RxParityError);
                                 ++port->icount.brk;
@@ -303,7 +304,7 @@ static void lh7a40xuart_set_mctrl (struct uart_port* port, unsigned int mctrl)
         /* Note, kernel appears to be setting DTR and RTS on console. */
 
         /* *** FIXME: this deserves more work.  There's some work in
-               tracing all of the IO pins. */
+               tracing all of the IO pins. */
 #if 0
         if( port->mapbase == UART1_PHYS) {
                 gpioRegs_t *gpio = (gpioRegs_t *)IO_ADDRESS(GPIO_PHYS);
@@ -662,9 +663,13 @@ static int __init lh7a40xuart_init(void)
         if (ret == 0) {
                 int i;
 
-                for (i = 0; i < DEV_NR; i++)
+                for (i = 0; i < DEV_NR; i++) {
+                        /* UART3, when used, requires GPIO pin reallocation */
+                        if (lh7a40x_ports[i].port.mapbase == UART3_PHYS)
+                                GPIO_PINMUX |= 1<<3;
                         uart_add_one_port (&lh7a40x_reg,
                                            &lh7a40x_ports[i].port);
+                }
         }
         return ret;
 }
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 5641498725d0..5a2840aeb547 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -167,6 +167,69 @@ config FB_ARMCLCD
           here and read <file:Documentation/modules.txt>.  The module
           will be called amba-clcd.
 
+choice
+
+        depends on FB_ARMCLCD && (ARCH_LH7A40X || ARCH_LH7952X)
+        prompt "LCD Panel"
+        default FB_ARMCLCD_SHARP_LQ035Q7DB02
+
+config FB_ARMCLCD_SHARP_LQ035Q7DB02_HRTFT
+        bool "LogicPD LCD 3.5\" QVGA w/HRTFT IC"
+        help
+          This is an implementation of the Sharp LQ035Q7DB02, a 3.5"
+          color QVGA, HRTFT panel.  The LogicPD device includes an
+          an integrated HRTFT controller IC.
+          The native resolution is 240x320.
+
+config FB_ARMCLCD_SHARP_LQ057Q3DC02
+        bool "LogicPD LCD 5.7\" QVGA"
+        help
+          This is an implementation of the Sharp LQ057Q3DC02, a 5.7"
+          color QVGA, TFT panel.  The LogicPD device includes an
+          The native resolution is 320x240.
+
+config FB_ARMCLCD_SHARP_LQ64D343
+        bool "LogicPD LCD 6.4\" VGA"
+        help
+          This is an implementation of the Sharp LQ64D343, a 6.4"
+          color VGA, TFT panel.  The LogicPD device includes an
+          The native resolution is 640x480.
+
+config FB_ARMCLCD_SHARP_LQ10D368
+        bool "LogicPD LCD 10.4\" VGA"
+        help
+          This is an implementation of the Sharp LQ10D368, a 10.4"
+          color VGA, TFT panel.  The LogicPD device includes an
+          The native resolution is 640x480.
+
+
+config FB_ARMCLCD_SHARP_LQ121S1DG41
+        bool "LogicPD LCD 12.1\" SVGA"
+        help
+          This is an implementation of the Sharp LQ121S1DG41, a 12.1"
+          color SVGA, TFT panel.  The LogicPD device includes an
+          The native resolution is 800x600.
+
+          This panel requires a clock rate may be an integer fraction
+          of the base LCDCLK frequency.  The driver will select the
+          highest frequency available that is lower than the maximum
+          allowed.  The panel may flicker if the clock rate is
+          slower than the recommended minimum.
+
+config FB_ARMCLCD_AUO_A070VW01_WIDE
+        bool "AU Optronics A070VW01 LCD 7.0\" WIDE"
+        help
+          This is an implementation of the AU Optronics, a 7.0"
+          WIDE Color.  The native resolution is 234x480.
+
+config FB_ARMCLCD_HITACHI
+        bool "Hitachi Wide Screen 800x480"
+        help
+          This is an implementation of the Hitachi 800x480.
+
+endchoice
+
+
 config FB_ACORN
         bool "Acorn VIDC support"
         depends on (FB = y) && ARM && (ARCH_ACORN || ARCH_CLPS7500)