2 files changed, 47 insertions, 47 deletions

diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index 30e8d589d167..2d15ed358a0a 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -170,7 +170,7 @@ static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
         struct skge_port *skge = netdev_priv(dev);
         struct skge_hw *hw = skge->hw;
 
-        if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
+        if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
                 return -EOPNOTSUPP;
 
         if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
@@ -247,7 +247,7 @@ static u32 skge_modes(const struct skge_hw *hw)
 
         if (iscopper(hw)) {
                 modes |= ADVERTISED_TP;
-                switch(hw->chip_id) {
+                switch (hw->chip_id) {
                 case CHIP_ID_GENESIS:
                         modes &= ~(ADVERTISED_100baseT_Full
                                    | ADVERTISED_100baseT_Half
@@ -279,7 +279,7 @@ static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
                 if (ecmd->advertising & skge_modes(hw))
                         return -EINVAL;
         } else {
-                switch(ecmd->speed) {
+                switch (ecmd->speed) {
                 case SPEED_1000:
                         if (hw->chip_id == CHIP_ID_YUKON_FE)
                                 return -EINVAL;
@@ -393,7 +393,7 @@ static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
 {
         int i;
 
-        switch(stringset) {
+        switch (stringset) {
         case ETH_SS_STATS:
                 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
                         memcpy(data + i * ETH_GSTRING_LEN,
@@ -540,9 +540,9 @@ static int skge_set_pauseparam(struct net_device *dev,
         skge->autoneg = ecmd->autoneg;
         if (ecmd->rx_pause && ecmd->tx_pause)
                 skge->flow_control = FLOW_MODE_SYMMETRIC;
-        else if(ecmd->rx_pause && !ecmd->tx_pause)
+        else if (ecmd->rx_pause && !ecmd->tx_pause)
                 skge->flow_control = FLOW_MODE_REM_SEND;
-        else if(!ecmd->rx_pause && ecmd->tx_pause)
+        else if (!ecmd->rx_pause && ecmd->tx_pause)
                 skge->flow_control = FLOW_MODE_LOC_SEND;
         else
                 skge->flow_control = FLOW_MODE_NONE;
@@ -730,7 +730,7 @@ static int skge_phys_id(struct net_device *dev, u32 data)
 {
         struct skge_port *skge = netdev_priv(dev);
 
-        if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
+        if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
                 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
 
         /* start blinking */
@@ -1960,7 +1960,7 @@ static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
         if (hw->chip_id == CHIP_ID_YUKON_FE)
                 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
 
-        switch(aux & PHY_M_PS_SPEED_MSK) {
+        switch (aux & PHY_M_PS_SPEED_MSK) {
         case PHY_M_PS_SPEED_1000:
                 return SPEED_1000;
         case PHY_M_PS_SPEED_100:
@@ -2299,10 +2299,10 @@ static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
 
         local_irq_save(flags);
         if (!spin_trylock(&skge->tx_lock)) {
-                /* Collision - tell upper layer to requeue */ 
-                local_irq_restore(flags); 
-                return NETDEV_TX_LOCKED; 
-        } 
+                /* Collision - tell upper layer to requeue */
+                local_irq_restore(flags);
+                return NETDEV_TX_LOCKED;
+        }
 
         if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
                 netif_stop_queue(dev);
@@ -2439,7 +2439,7 @@ static int skge_change_mtu(struct net_device *dev, int new_mtu)
 {
         int err = 0;
 
-        if(new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
+        if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
                 return -EINVAL;
 
         dev->mtu = new_mtu;
@@ -2473,7 +2473,7 @@ static void genesis_set_multicast(struct net_device *dev)
                 memset(filter, 0xff, sizeof(filter));
         else {
                 memset(filter, 0, sizeof(filter));
-                for(i = 0; list && i < count; i++, list = list->next) {
+                for (i = 0; list && i < count; i++, list = list->next) {
                         u32 crc = crc32_le(~0, list->dmi_addr, ETH_ALEN);
                         u8 bit = 63 - (crc & 63);
 
@@ -2510,7 +2510,7 @@ static void yukon_set_multicast(struct net_device *dev)
                 int i;
                 reg |= GM_RXCR_MCF_ENA;
 
-                for(i = 0; list && i < dev->mc_count; i++, list = list->next) {
+                for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
                         u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
                         filter[bit/8] |= 1 << (bit%8);
                 }
@@ -2657,7 +2657,7 @@ static inline void skge_tx_intr(struct net_device *dev)
         struct skge_element *e;
 
         spin_lock(&skge->tx_lock);
-        for(e = ring->to_clean; e != ring->to_use; e = e->next) {
+        for (e = ring->to_clean; e != ring->to_use; e = e->next) {
                 struct skge_tx_desc *td = e->desc;
                 u32 control;
 
@@ -2712,7 +2712,7 @@ static void skge_pci_clear(struct skge_hw *hw)
 
 static void skge_mac_intr(struct skge_hw *hw, int port)
 {
-        if (hw->chip_id == CHIP_ID_GENESIS) 
+        if (hw->chip_id == CHIP_ID_GENESIS)
                 genesis_mac_intr(hw, port);
         else
                 yukon_mac_intr(hw, port);
@@ -2847,7 +2847,7 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
 
         if (status & IS_MAC1)
                 skge_mac_intr(hw, 0);
-        
+
         if (status & IS_MAC2)
                 skge_mac_intr(hw, 1);
 
@@ -2952,7 +2952,7 @@ static int skge_reset(struct skge_hw *hw)
         hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
         hw->pmd_type = skge_read8(hw, B2_PMD_TYP);
 
-        switch(hw->chip_id) {
+        switch (hw->chip_id) {
         case CHIP_ID_GENESIS:
                 switch (hw->phy_type) {
                 case SK_PHY_XMAC:
@@ -3288,7 +3288,7 @@ static void __devexit skge_remove(struct pci_dev *pdev)
         struct skge_hw *hw  = pci_get_drvdata(pdev);
         struct net_device *dev0, *dev1;
 
-        if(!hw)
+        if (!hw)
                 return;
 
         if ((dev1 = hw->dev[1]))
@@ -3316,7 +3316,7 @@ static int skge_suspend(struct pci_dev *pdev, u32 state)
         struct skge_hw *hw  = pci_get_drvdata(pdev);
         int i, wol = 0;
 
-        for(i = 0; i < 2; i++) {
+        for (i = 0; i < 2; i++) {
                 struct net_device *dev = hw->dev[i];
 
                 if (dev) {
@@ -3349,11 +3349,11 @@ static int skge_resume(struct pci_dev *pdev)
 
         skge_reset(hw);
 
-        for(i = 0; i < 2; i++) {
+        for (i = 0; i < 2; i++) {
                 struct net_device *dev = hw->dev[i];
                 if (dev) {
                         netif_device_attach(dev);
-                        if(netif_running(dev))
+                        if (netif_running(dev))
                                 skge_up(dev);
                 }
         }
diff --git a/drivers/net/skge.h b/drivers/net/skge.h
index 36c62b68fab4..aad3aece30b5 100644
--- a/drivers/net/skge.h
+++ b/drivers/net/skge.h
@@ -537,7 +537,7 @@ enum {
 
 /* Queue Register Offsets, use Q_ADDR() to access */
 enum {
-        B8_Q_REGS = 0x0400, /* base of Queue registers */       
+        B8_Q_REGS = 0x0400, /* base of Queue registers */
         Q_D     = 0x00, /* 8*32 bit     Current Descriptor */
         Q_DA_L  = 0x20, /* 32 bit       Current Descriptor Address Low dWord */
         Q_DA_H  = 0x24, /* 32 bit       Current Descriptor Address High dWord */
@@ -986,7 +986,7 @@ enum {
         LINKLED_BLINK_OFF    = 0x10,
         LINKLED_BLINK_ON     = 0x20,
 };
-        
+
 /* GMAC and GPHY Control Registers (YUKON only) */
 enum {
         GMAC_CTRL       = 0x0f00,/* 32 bit      GMAC Control Reg */
@@ -1306,7 +1306,7 @@ enum {
 enum {
         PHY_ANE_PAR_DF  = 1<<4, /* Bit  4:      Parallel Detection Fault */
 
-        PHY_ANE_LP_CAP  = 1<<0, /* Bit  0:      Link Partner Auto-Neg. Cap. */  
+        PHY_ANE_LP_CAP  = 1<<0, /* Bit  0:      Link Partner Auto-Neg. Cap. */
 };
 
 enum {
@@ -1718,7 +1718,7 @@ enum {
         PHY_M_PC_EN_DET_PLUS    = 3<<8, /* Energy Detect Plus (Mode 2) */
 };
 
-#define PHY_M_PC_MDI_XMODE(x)   (((x)<<5) & PHY_M_PC_MDIX_MSK)  
+#define PHY_M_PC_MDI_XMODE(x)   (((x)<<5) & PHY_M_PC_MDIX_MSK)
 
 enum {
         PHY_M_PC_MAN_MDI        = 0, /* 00 = Manual MDI configuration */
@@ -2105,7 +2105,7 @@ enum {
         GM_GPSR_FC_RX_DIS       = 1<<2, /* Bit  2:      Rx Flow-Control Mode Disabled */
         GM_GPSR_PROM_EN         = 1<<1, /* Bit  1:      Promiscuous Mode Enabled */
 };
-        
+
 /*      GM_GP_CTRL      16 bit r/w      General Purpose Control Register */
 enum {
         GM_GPCR_PROM_ENA        = 1<<14,        /* Bit 14:      Enable Promiscuous Mode */
@@ -2127,7 +2127,7 @@ enum {
 
 #define GM_GPCR_SPEED_1000      (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
 #define GM_GPCR_AU_ALL_DIS      (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
-        
+
 /*      GM_TX_CTRL                      16 bit r/w      Transmit Control Register */
 enum {
         GM_TXCR_FORCE_JAM       = 1<<15, /* Bit 15:     Force Jam / Flow-Control */
@@ -2138,7 +2138,7 @@ enum {
 
 #define TX_COL_THR(x)           (((x)<<10) & GM_TXCR_COL_THR_MSK)
 #define TX_COL_DEF              0x04
-        
+
 /*      GM_RX_CTRL                      16 bit r/w      Receive Control Register */
 enum {
         GM_RXCR_UCF_ENA = 1<<15, /* Bit 15:     Enable Unicast filtering */
@@ -2146,7 +2146,7 @@ enum {
         GM_RXCR_CRC_DIS = 1<<13, /* Bit 13:     Remove 4-byte CRC */
         GM_RXCR_PASS_FC = 1<<12, /* Bit 12:     Pass FC packets to FIFO */
 };
-        
+
 /*      GM_TX_PARAM             16 bit r/w      Transmit Parameter Register */
 enum {
         GM_TXPA_JAMLEN_MSK      = 0x03<<14,     /* Bit 15..14:  Jam Length */
@@ -2171,7 +2171,7 @@ enum {
         GM_SMOD_JUMBO_ENA       = 1<<8, /* Bit  8:      Enable Jumbo (Max. Frame Len) */
          GM_SMOD_IPG_MSK        = 0x1f  /* Bit 4..0:    Inter-Packet Gap (IPG) */
 };
-        
+
 #define DATA_BLIND_VAL(x)       (((x)<<11) & GM_SMOD_DATABL_MSK)
 #define DATA_BLIND_DEF          0x04
 
@@ -2186,7 +2186,7 @@ enum {
         GM_SMI_CT_RD_VAL        = 1<<4, /* Bit  4:      Read Valid (Read completed) */
         GM_SMI_CT_BUSY          = 1<<3, /* Bit  3:      Busy (Operation in progress) */
 };
-        
+
 #define GM_SMI_CT_PHY_AD(x)     (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
 #define GM_SMI_CT_REG_AD(x)     (((x)<<6) & GM_SMI_CT_REG_A_MSK)
 
@@ -2195,7 +2195,7 @@ enum {
         GM_PAR_MIB_CLR  = 1<<5, /* Bit  5:      Set MIB Clear Counter Mode */
         GM_PAR_MIB_TST  = 1<<4, /* Bit  4:      MIB Load Counter (Test Mode) */
 };
-        
+
 /* Receive Frame Status Encoding */
 enum {
         GMR_FS_LEN      = 0xffff<<16, /* Bit 31..16:    Rx Frame Length */
@@ -2217,12 +2217,12 @@ enum {
 /*
  * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
  */
-        GMR_FS_ANY_ERR  = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR | 
-                          GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC | 
+        GMR_FS_ANY_ERR  = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR |
+                          GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
                           GMR_FS_JABBER,
 /* Rx GMAC FIFO Flush Mask (default) */
         RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR |
-                           GMR_FS_BAD_FC | GMR_FS_GOOD_FC | GMR_FS_UN_SIZE | 
+                           GMR_FS_BAD_FC | GMR_FS_GOOD_FC | GMR_FS_UN_SIZE |
                            GMR_FS_JABBER,
 };
 
@@ -2801,7 +2801,7 @@ struct skge_hw {
 
         u32                  ram_size;
         u32                  ram_offset;
-        
+
         struct tasklet_struct ext_tasklet;
         spinlock_t           phy_lock;
 };
@@ -2827,7 +2827,7 @@ enum {
         FLOW_MODE_REM_SEND      = 2, /* Symmetric or just remote */
         FLOW_MODE_SYMMETRIC     = 3, /* Both stations may send PAUSE */
 };
-        
+
 struct skge_port {
         u32                  msg_enable;
         struct skge_hw       *hw;
@@ -2933,24 +2933,24 @@ static inline void skge_xm_write8(const struct skge_hw *hw, int port, int r, u8
 static inline void skge_xm_outhash(const struct skge_hw *hw, int port, int reg,
                                    const u8 *hash)
 {
-        skge_xm_write16(hw, port, reg, 
+        skge_xm_write16(hw, port, reg,
                         (u16)hash[0] | ((u16)hash[1] << 8));
-        skge_xm_write16(hw, port, reg+2, 
+        skge_xm_write16(hw, port, reg+2,
                         (u16)hash[2] | ((u16)hash[3] << 8));
-        skge_xm_write16(hw, port, reg+4, 
+        skge_xm_write16(hw, port, reg+4,
                         (u16)hash[4] | ((u16)hash[5] << 8));
-        skge_xm_write16(hw, port, reg+6, 
+        skge_xm_write16(hw, port, reg+6,
                         (u16)hash[6] | ((u16)hash[7] << 8));
 }
 
 static inline void skge_xm_outaddr(const struct skge_hw *hw, int port, int reg,
                                    const u8 *addr)
 {
-        skge_xm_write16(hw, port, reg, 
+        skge_xm_write16(hw, port, reg,
                         (u16)addr[0] | ((u16)addr[1] << 8));
-        skge_xm_write16(hw, port, reg, 
+        skge_xm_write16(hw, port, reg,
                         (u16)addr[2] | ((u16)addr[3] << 8));
-        skge_xm_write16(hw, port, reg, 
+        skge_xm_write16(hw, port, reg,
                         (u16)addr[4] | ((u16)addr[5] << 8));
 }
 
@@ -3001,5 +3001,5 @@ static inline void skge_gm_set_addr(struct skge_hw *hw, int port, int reg,
         skge_gma_write16(hw, port, reg+8,
                          (u16) addr[4] | ((u16) addr[5] << 8));
 }
-                
+
 #endif