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-rw-r--r--drivers/mmc/host/imxmmc.c459
-rw-r--r--drivers/mmc/host/imxmmc.h37
-rw-r--r--drivers/mtd/nand/Kconfig2
-rw-r--r--drivers/serial/imx.c6
4 files changed, 262 insertions, 242 deletions
diff --git a/drivers/mmc/host/imxmmc.c b/drivers/mmc/host/imxmmc.c
index 2f0fcdb869b7..eb29b1d933ac 100644
--- a/drivers/mmc/host/imxmmc.c
+++ b/drivers/mmc/host/imxmmc.c
@@ -10,20 +10,6 @@
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 * 12 *
13 * 2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz>
14 * Changed to conform redesigned i.MX scatter gather DMA interface
15 *
16 * 2005-11-04 Pavel Pisa <pisa@cmp.felk.cvut.cz>
17 * Updated for 2.6.14 kernel
18 *
19 * 2005-12-13 Jay Monkman <jtm@smoothsmoothie.com>
20 * Found and corrected problems in the write path
21 *
22 * 2005-12-30 Pavel Pisa <pisa@cmp.felk.cvut.cz>
23 * The event handling rewritten right way in softirq.
24 * Added many ugly hacks and delays to overcome SDHC
25 * deficiencies
26 *
27 */ 13 */
28 14
29#include <linux/module.h> 15#include <linux/module.h>
@@ -37,9 +23,9 @@
37#include <linux/mmc/card.h> 23#include <linux/mmc/card.h>
38#include <linux/delay.h> 24#include <linux/delay.h>
39#include <linux/clk.h> 25#include <linux/clk.h>
26#include <linux/io.h>
40 27
41#include <asm/dma.h> 28#include <asm/dma.h>
42#include <asm/io.h>
43#include <asm/irq.h> 29#include <asm/irq.h>
44#include <asm/sizes.h> 30#include <asm/sizes.h>
45#include <mach/mmc.h> 31#include <mach/mmc.h>
@@ -50,17 +36,16 @@
50#define DRIVER_NAME "imx-mmc" 36#define DRIVER_NAME "imx-mmc"
51 37
52#define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \ 38#define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \
53 INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \ 39 INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
54 INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO) 40 INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
55 41
56struct imxmci_host { 42struct imxmci_host {
57 struct mmc_host *mmc; 43 struct mmc_host *mmc;
58 spinlock_t lock; 44 spinlock_t lock;
59 struct resource *res; 45 struct resource *res;
46 void __iomem *base;
60 int irq; 47 int irq;
61 imx_dmach_t dma; 48 imx_dmach_t dma;
62 unsigned int clkrt;
63 unsigned int cmdat;
64 volatile unsigned int imask; 49 volatile unsigned int imask;
65 unsigned int power_mode; 50 unsigned int power_mode;
66 unsigned int present; 51 unsigned int present;
@@ -74,7 +59,7 @@ struct imxmci_host {
74 struct tasklet_struct tasklet; 59 struct tasklet_struct tasklet;
75 unsigned int status_reg; 60 unsigned int status_reg;
76 unsigned long pending_events; 61 unsigned long pending_events;
77 /* Next to fields are there for CPU driven transfers to overcome SDHC deficiencies */ 62 /* Next two fields are there for CPU driven transfers to overcome SDHC deficiencies */
78 u16 *data_ptr; 63 u16 *data_ptr;
79 unsigned int data_cnt; 64 unsigned int data_cnt;
80 atomic_t stuck_timeout; 65 atomic_t stuck_timeout;
@@ -114,14 +99,22 @@ struct imxmci_host {
114static void imxmci_stop_clock(struct imxmci_host *host) 99static void imxmci_stop_clock(struct imxmci_host *host)
115{ 100{
116 int i = 0; 101 int i = 0;
117 MMC_STR_STP_CLK &= ~STR_STP_CLK_START_CLK; 102 u16 reg;
118 while(i < 0x1000) { 103
119 if(!(i & 0x7f)) 104 reg = readw(host->base + MMC_REG_STR_STP_CLK);
120 MMC_STR_STP_CLK |= STR_STP_CLK_STOP_CLK; 105 writew(reg & ~STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
106 while (i < 0x1000) {
107 if (!(i & 0x7f)) {
108 reg = readw(host->base + MMC_REG_STR_STP_CLK);
109 writew(reg | STR_STP_CLK_STOP_CLK,
110 host->base + MMC_REG_STR_STP_CLK);
111 }
121 112
122 if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) { 113 reg = readw(host->base + MMC_REG_STATUS);
114 if (!(reg & STATUS_CARD_BUS_CLK_RUN)) {
123 /* Check twice before cut */ 115 /* Check twice before cut */
124 if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) 116 reg = readw(host->base + MMC_REG_STATUS);
117 if (!(reg & STATUS_CARD_BUS_CLK_RUN))
125 return; 118 return;
126 } 119 }
127 120
@@ -135,8 +128,10 @@ static int imxmci_start_clock(struct imxmci_host *host)
135 unsigned int trials = 0; 128 unsigned int trials = 0;
136 unsigned int delay_limit = 128; 129 unsigned int delay_limit = 128;
137 unsigned long flags; 130 unsigned long flags;
131 u16 reg;
138 132
139 MMC_STR_STP_CLK &= ~STR_STP_CLK_STOP_CLK; 133 reg = readw(host->base + MMC_REG_STR_STP_CLK);
134 writew(reg & ~STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
140 135
141 clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events); 136 clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
142 137
@@ -145,18 +140,21 @@ static int imxmci_start_clock(struct imxmci_host *host)
145 * then 6 delay loops, but during card detection (low clockrate) 140 * then 6 delay loops, but during card detection (low clockrate)
146 * it takes up to 5000 delay loops and sometimes fails for the first time 141 * it takes up to 5000 delay loops and sometimes fails for the first time
147 */ 142 */
148 MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK; 143 reg = readw(host->base + MMC_REG_STR_STP_CLK);
144 writew(reg | STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
149 145
150 do { 146 do {
151 unsigned int delay = delay_limit; 147 unsigned int delay = delay_limit;
152 148
153 while(delay--){ 149 while (delay--) {
154 if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN) 150 reg = readw(host->base + MMC_REG_STATUS);
151 if (reg & STATUS_CARD_BUS_CLK_RUN)
155 /* Check twice before cut */ 152 /* Check twice before cut */
156 if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN) 153 reg = readw(host->base + MMC_REG_STATUS);
154 if (reg & STATUS_CARD_BUS_CLK_RUN)
157 return 0; 155 return 0;
158 156
159 if(test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) 157 if (test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
160 return 0; 158 return 0;
161 } 159 }
162 160
@@ -167,58 +165,59 @@ static int imxmci_start_clock(struct imxmci_host *host)
167 * IRQ or schedule delays this function execution and the clocks has 165 * IRQ or schedule delays this function execution and the clocks has
168 * been already stopped by other means (response processing, SDHC HW) 166 * been already stopped by other means (response processing, SDHC HW)
169 */ 167 */
170 if(!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) 168 if (!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) {
171 MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK; 169 reg = readw(host->base + MMC_REG_STR_STP_CLK);
170 writew(reg | STR_STP_CLK_START_CLK,
171 host->base + MMC_REG_STR_STP_CLK);
172 }
172 local_irq_restore(flags); 173 local_irq_restore(flags);
173 174
174 } while(++trials<256); 175 } while (++trials < 256);
175 176
176 dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n"); 177 dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n");
177 178
178 return -1; 179 return -1;
179} 180}
180 181
181static void imxmci_softreset(void) 182static void imxmci_softreset(struct imxmci_host *host)
182{ 183{
184 int i;
185
183 /* reset sequence */ 186 /* reset sequence */
184 MMC_STR_STP_CLK = 0x8; 187 writew(0x08, host->base + MMC_REG_STR_STP_CLK);
185 MMC_STR_STP_CLK = 0xD; 188 writew(0x0D, host->base + MMC_REG_STR_STP_CLK);
186 MMC_STR_STP_CLK = 0x5; 189
187 MMC_STR_STP_CLK = 0x5; 190 for (i = 0; i < 8; i++)
188 MMC_STR_STP_CLK = 0x5; 191 writew(0x05, host->base + MMC_REG_STR_STP_CLK);
189 MMC_STR_STP_CLK = 0x5; 192
190 MMC_STR_STP_CLK = 0x5; 193 writew(0xff, host->base + MMC_REG_RES_TO);
191 MMC_STR_STP_CLK = 0x5; 194 writew(512, host->base + MMC_REG_BLK_LEN);
192 MMC_STR_STP_CLK = 0x5; 195 writew(1, host->base + MMC_REG_NOB);
193 MMC_STR_STP_CLK = 0x5;
194
195 MMC_RES_TO = 0xff;
196 MMC_BLK_LEN = 512;
197 MMC_NOB = 1;
198} 196}
199 197
200static int imxmci_busy_wait_for_status(struct imxmci_host *host, 198static int imxmci_busy_wait_for_status(struct imxmci_host *host,
201 unsigned int *pstat, unsigned int stat_mask, 199 unsigned int *pstat, unsigned int stat_mask,
202 int timeout, const char *where) 200 int timeout, const char *where)
203{ 201{
204 int loops=0; 202 int loops = 0;
205 while(!(*pstat & stat_mask)) { 203
206 loops+=2; 204 while (!(*pstat & stat_mask)) {
207 if(loops >= timeout) { 205 loops += 2;
206 if (loops >= timeout) {
208 dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n", 207 dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n",
209 where, *pstat, stat_mask); 208 where, *pstat, stat_mask);
210 return -1; 209 return -1;
211 } 210 }
212 udelay(2); 211 udelay(2);
213 *pstat |= MMC_STATUS; 212 *pstat |= readw(host->base + MMC_REG_STATUS);
214 } 213 }
215 if(!loops) 214 if (!loops)
216 return 0; 215 return 0;
217 216
218 /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */ 217 /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
219 if(!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock>=8000000)) 218 if (!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock >= 8000000))
220 dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n", 219 dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
221 loops, where, *pstat, stat_mask); 220 loops, where, *pstat, stat_mask);
222 return loops; 221 return loops;
223} 222}
224 223
@@ -235,8 +234,8 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
235 host->data = data; 234 host->data = data;
236 data->bytes_xfered = 0; 235 data->bytes_xfered = 0;
237 236
238 MMC_NOB = nob; 237 writew(nob, host->base + MMC_REG_NOB);
239 MMC_BLK_LEN = blksz; 238 writew(blksz, host->base + MMC_REG_BLK_LEN);
240 239
241 /* 240 /*
242 * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise. 241 * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise.
@@ -252,14 +251,14 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
252 host->dma_dir = DMA_FROM_DEVICE; 251 host->dma_dir = DMA_FROM_DEVICE;
253 252
254 /* Hack to enable read SCR */ 253 /* Hack to enable read SCR */
255 MMC_NOB = 1; 254 writew(1, host->base + MMC_REG_NOB);
256 MMC_BLK_LEN = 512; 255 writew(512, host->base + MMC_REG_BLK_LEN);
257 } else { 256 } else {
258 host->dma_dir = DMA_TO_DEVICE; 257 host->dma_dir = DMA_TO_DEVICE;
259 } 258 }
260 259
261 /* Convert back to virtual address */ 260 /* Convert back to virtual address */
262 host->data_ptr = (u16*)sg_virt(data->sg); 261 host->data_ptr = (u16 *)sg_virt(data->sg);
263 host->data_cnt = 0; 262 host->data_cnt = 0;
264 263
265 clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events); 264 clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
@@ -271,10 +270,11 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
271 if (data->flags & MMC_DATA_READ) { 270 if (data->flags & MMC_DATA_READ) {
272 host->dma_dir = DMA_FROM_DEVICE; 271 host->dma_dir = DMA_FROM_DEVICE;
273 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, 272 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
274 data->sg_len, host->dma_dir); 273 data->sg_len, host->dma_dir);
275 274
276 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz, 275 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
277 host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_READ); 276 host->res->start + MMC_REG_BUFFER_ACCESS,
277 DMA_MODE_READ);
278 278
279 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/ 279 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
280 CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN; 280 CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN;
@@ -282,10 +282,11 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
282 host->dma_dir = DMA_TO_DEVICE; 282 host->dma_dir = DMA_TO_DEVICE;
283 283
284 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, 284 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
285 data->sg_len, host->dma_dir); 285 data->sg_len, host->dma_dir);
286 286
287 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz, 287 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
288 host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_WRITE); 288 host->res->start + MMC_REG_BUFFER_ACCESS,
289 DMA_MODE_WRITE);
289 290
290 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/ 291 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
291 CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN; 292 CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN;
@@ -293,12 +294,12 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
293 294
294#if 1 /* This code is there only for consistency checking and can be disabled in future */ 295#if 1 /* This code is there only for consistency checking and can be disabled in future */
295 host->dma_size = 0; 296 host->dma_size = 0;
296 for(i=0; i<host->dma_nents; i++) 297 for (i = 0; i < host->dma_nents; i++)
297 host->dma_size+=data->sg[i].length; 298 host->dma_size += data->sg[i].length;
298 299
299 if (datasz > host->dma_size) { 300 if (datasz > host->dma_size) {
300 dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n", 301 dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n",
301 datasz, host->dma_size); 302 datasz, host->dma_size);
302 } 303 }
303#endif 304#endif
304 305
@@ -306,7 +307,7 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
306 307
307 wmb(); 308 wmb();
308 309
309 if(host->actual_bus_width == MMC_BUS_WIDTH_4) 310 if (host->actual_bus_width == MMC_BUS_WIDTH_4)
310 BLR(host->dma) = 0; /* burst 64 byte read / 64 bytes write */ 311 BLR(host->dma) = 0; /* burst 64 byte read / 64 bytes write */
311 else 312 else
312 BLR(host->dma) = 16; /* burst 16 byte read / 16 bytes write */ 313 BLR(host->dma) = 16; /* burst 16 byte read / 16 bytes write */
@@ -317,9 +318,8 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
317 clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events); 318 clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
318 319
319 /* start DMA engine for read, write is delayed after initial response */ 320 /* start DMA engine for read, write is delayed after initial response */
320 if (host->dma_dir == DMA_FROM_DEVICE) { 321 if (host->dma_dir == DMA_FROM_DEVICE)
321 imx_dma_enable(host->dma); 322 imx_dma_enable(host->dma);
322 }
323} 323}
324 324
325static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat) 325static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat)
@@ -351,16 +351,16 @@ static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd,
351 break; 351 break;
352 } 352 }
353 353
354 if ( test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events) ) 354 if (test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events))
355 cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */ 355 cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */
356 356
357 if ( host->actual_bus_width == MMC_BUS_WIDTH_4 ) 357 if (host->actual_bus_width == MMC_BUS_WIDTH_4)
358 cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; 358 cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
359 359
360 MMC_CMD = cmd->opcode; 360 writew(cmd->opcode, host->base + MMC_REG_CMD);
361 MMC_ARGH = cmd->arg >> 16; 361 writew(cmd->arg >> 16, host->base + MMC_REG_ARGH);
362 MMC_ARGL = cmd->arg & 0xffff; 362 writew(cmd->arg & 0xffff, host->base + MMC_REG_ARGL);
363 MMC_CMD_DAT_CONT = cmdat; 363 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
364 364
365 atomic_set(&host->stuck_timeout, 0); 365 atomic_set(&host->stuck_timeout, 0);
366 set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events); 366 set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events);
@@ -368,18 +368,18 @@ static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd,
368 368
369 imask = IMXMCI_INT_MASK_DEFAULT; 369 imask = IMXMCI_INT_MASK_DEFAULT;
370 imask &= ~INT_MASK_END_CMD_RES; 370 imask &= ~INT_MASK_END_CMD_RES;
371 if ( cmdat & CMD_DAT_CONT_DATA_ENABLE ) { 371 if (cmdat & CMD_DAT_CONT_DATA_ENABLE) {
372 /*imask &= ~INT_MASK_BUF_READY;*/ 372 /* imask &= ~INT_MASK_BUF_READY; */
373 imask &= ~INT_MASK_DATA_TRAN; 373 imask &= ~INT_MASK_DATA_TRAN;
374 if ( cmdat & CMD_DAT_CONT_WRITE ) 374 if (cmdat & CMD_DAT_CONT_WRITE)
375 imask &= ~INT_MASK_WRITE_OP_DONE; 375 imask &= ~INT_MASK_WRITE_OP_DONE;
376 if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) 376 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
377 imask &= ~INT_MASK_BUF_READY; 377 imask &= ~INT_MASK_BUF_READY;
378 } 378 }
379 379
380 spin_lock_irqsave(&host->lock, flags); 380 spin_lock_irqsave(&host->lock, flags);
381 host->imask = imask; 381 host->imask = imask;
382 MMC_INT_MASK = host->imask; 382 writew(host->imask, host->base + MMC_REG_INT_MASK);
383 spin_unlock_irqrestore(&host->lock, flags); 383 spin_unlock_irqrestore(&host->lock, flags);
384 384
385 dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n", 385 dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n",
@@ -395,14 +395,14 @@ static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *
395 spin_lock_irqsave(&host->lock, flags); 395 spin_lock_irqsave(&host->lock, flags);
396 396
397 host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m | 397 host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m |
398 IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m); 398 IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
399 399
400 host->imask = IMXMCI_INT_MASK_DEFAULT; 400 host->imask = IMXMCI_INT_MASK_DEFAULT;
401 MMC_INT_MASK = host->imask; 401 writew(host->imask, host->base + MMC_REG_INT_MASK);
402 402
403 spin_unlock_irqrestore(&host->lock, flags); 403 spin_unlock_irqrestore(&host->lock, flags);
404 404
405 if(req && req->cmd) 405 if (req && req->cmd)
406 host->prev_cmd_code = req->cmd->opcode; 406 host->prev_cmd_code = req->cmd->opcode;
407 407
408 host->req = NULL; 408 host->req = NULL;
@@ -416,17 +416,17 @@ static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat)
416 struct mmc_data *data = host->data; 416 struct mmc_data *data = host->data;
417 int data_error; 417 int data_error;
418 418
419 if(test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)){ 419 if (test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
420 imx_dma_disable(host->dma); 420 imx_dma_disable(host->dma);
421 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents, 421 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
422 host->dma_dir); 422 host->dma_dir);
423 } 423 }
424 424
425 if ( stat & STATUS_ERR_MASK ) { 425 if (stat & STATUS_ERR_MASK) {
426 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",stat); 426 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", stat);
427 if(stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR)) 427 if (stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
428 data->error = -EILSEQ; 428 data->error = -EILSEQ;
429 else if(stat & STATUS_TIME_OUT_READ) 429 else if (stat & STATUS_TIME_OUT_READ)
430 data->error = -ETIMEDOUT; 430 data->error = -ETIMEDOUT;
431 else 431 else
432 data->error = -EIO; 432 data->error = -EIO;
@@ -445,7 +445,7 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
445{ 445{
446 struct mmc_command *cmd = host->cmd; 446 struct mmc_command *cmd = host->cmd;
447 int i; 447 int i;
448 u32 a,b,c; 448 u32 a, b, c;
449 struct mmc_data *data = host->data; 449 struct mmc_data *data = host->data;
450 450
451 if (!cmd) 451 if (!cmd)
@@ -461,18 +461,18 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
461 cmd->error = -EILSEQ; 461 cmd->error = -EILSEQ;
462 } 462 }
463 463
464 if(cmd->flags & MMC_RSP_PRESENT) { 464 if (cmd->flags & MMC_RSP_PRESENT) {
465 if(cmd->flags & MMC_RSP_136) { 465 if (cmd->flags & MMC_RSP_136) {
466 for (i = 0; i < 4; i++) { 466 for (i = 0; i < 4; i++) {
467 u32 a = MMC_RES_FIFO & 0xffff; 467 a = readw(host->base + MMC_REG_RES_FIFO);
468 u32 b = MMC_RES_FIFO & 0xffff; 468 b = readw(host->base + MMC_REG_RES_FIFO);
469 cmd->resp[i] = a<<16 | b; 469 cmd->resp[i] = a << 16 | b;
470 } 470 }
471 } else { 471 } else {
472 a = MMC_RES_FIFO & 0xffff; 472 a = readw(host->base + MMC_REG_RES_FIFO);
473 b = MMC_RES_FIFO & 0xffff; 473 b = readw(host->base + MMC_REG_RES_FIFO);
474 c = MMC_RES_FIFO & 0xffff; 474 c = readw(host->base + MMC_REG_RES_FIFO);
475 cmd->resp[0] = a<<24 | b<<8 | c>>8; 475 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
476 } 476 }
477 } 477 }
478 478
@@ -484,36 +484,34 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
484 484
485 /* Wait for FIFO to be empty before starting DMA write */ 485 /* Wait for FIFO to be empty before starting DMA write */
486 486
487 stat = MMC_STATUS; 487 stat = readw(host->base + MMC_REG_STATUS);
488 if(imxmci_busy_wait_for_status(host, &stat, 488 if (imxmci_busy_wait_for_status(host, &stat,
489 STATUS_APPL_BUFF_FE, 489 STATUS_APPL_BUFF_FE,
490 40, "imxmci_cmd_done DMA WR") < 0) { 490 40, "imxmci_cmd_done DMA WR") < 0) {
491 cmd->error = -EIO; 491 cmd->error = -EIO;
492 imxmci_finish_data(host, stat); 492 imxmci_finish_data(host, stat);
493 if(host->req) 493 if (host->req)
494 imxmci_finish_request(host, host->req); 494 imxmci_finish_request(host, host->req);
495 dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n", 495 dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n",
496 stat); 496 stat);
497 return 0; 497 return 0;
498 } 498 }
499 499
500 if(test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) { 500 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
501 imx_dma_enable(host->dma); 501 imx_dma_enable(host->dma);
502 }
503 } 502 }
504 } else { 503 } else {
505 struct mmc_request *req; 504 struct mmc_request *req;
506 imxmci_stop_clock(host); 505 imxmci_stop_clock(host);
507 req = host->req; 506 req = host->req;
508 507
509 if(data) 508 if (data)
510 imxmci_finish_data(host, stat); 509 imxmci_finish_data(host, stat);
511 510
512 if( req ) { 511 if (req)
513 imxmci_finish_request(host, req); 512 imxmci_finish_request(host, req);
514 } else { 513 else
515 dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n"); 514 dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n");
516 }
517 } 515 }
518 516
519 return 1; 517 return 1;
@@ -535,11 +533,10 @@ static int imxmci_data_done(struct imxmci_host *host, unsigned int stat)
535 } else { 533 } else {
536 struct mmc_request *req; 534 struct mmc_request *req;
537 req = host->req; 535 req = host->req;
538 if( req ) { 536 if (req)
539 imxmci_finish_request(host, req); 537 imxmci_finish_request(host, req);
540 } else { 538 else
541 dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n"); 539 dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n");
542 }
543 } 540 }
544 541
545 return 1; 542 return 1;
@@ -552,7 +549,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
552 int trans_done = 0; 549 int trans_done = 0;
553 unsigned int stat = *pstat; 550 unsigned int stat = *pstat;
554 551
555 if(host->actual_bus_width != MMC_BUS_WIDTH_4) 552 if (host->actual_bus_width != MMC_BUS_WIDTH_4)
556 burst_len = 16; 553 burst_len = 16;
557 else 554 else
558 burst_len = 64; 555 burst_len = 64;
@@ -563,44 +560,44 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
563 560
564 udelay(20); /* required for clocks < 8MHz*/ 561 udelay(20); /* required for clocks < 8MHz*/
565 562
566 if(host->dma_dir == DMA_FROM_DEVICE) { 563 if (host->dma_dir == DMA_FROM_DEVICE) {
567 imxmci_busy_wait_for_status(host, &stat, 564 imxmci_busy_wait_for_status(host, &stat,
568 STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE | 565 STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE |
569 STATUS_TIME_OUT_READ, 566 STATUS_TIME_OUT_READ,
570 50, "imxmci_cpu_driven_data read"); 567 50, "imxmci_cpu_driven_data read");
571 568
572 while((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) && 569 while ((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) &&
573 !(stat & STATUS_TIME_OUT_READ) && 570 !(stat & STATUS_TIME_OUT_READ) &&
574 (host->data_cnt < 512)) { 571 (host->data_cnt < 512)) {
575 572
576 udelay(20); /* required for clocks < 8MHz*/ 573 udelay(20); /* required for clocks < 8MHz*/
577 574
578 for(i = burst_len; i>=2 ; i-=2) { 575 for (i = burst_len; i >= 2 ; i -= 2) {
579 u16 data; 576 u16 data;
580 data = MMC_BUFFER_ACCESS; 577 data = readw(host->base + MMC_REG_BUFFER_ACCESS);
581 udelay(10); /* required for clocks < 8MHz*/ 578 udelay(10); /* required for clocks < 8MHz*/
582 if(host->data_cnt+2 <= host->dma_size) { 579 if (host->data_cnt+2 <= host->dma_size) {
583 *(host->data_ptr++) = data; 580 *(host->data_ptr++) = data;
584 } else { 581 } else {
585 if(host->data_cnt < host->dma_size) 582 if (host->data_cnt < host->dma_size)
586 *(u8*)(host->data_ptr) = data; 583 *(u8 *)(host->data_ptr) = data;
587 } 584 }
588 host->data_cnt += 2; 585 host->data_cnt += 2;
589 } 586 }
590 587
591 stat = MMC_STATUS; 588 stat = readw(host->base + MMC_REG_STATUS);
592 589
593 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n", 590 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n",
594 host->data_cnt, burst_len, stat); 591 host->data_cnt, burst_len, stat);
595 } 592 }
596 593
597 if((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512)) 594 if ((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
598 trans_done = 1; 595 trans_done = 1;
599 596
600 if(host->dma_size & 0x1ff) 597 if (host->dma_size & 0x1ff)
601 stat &= ~STATUS_CRC_READ_ERR; 598 stat &= ~STATUS_CRC_READ_ERR;
602 599
603 if(stat & STATUS_TIME_OUT_READ) { 600 if (stat & STATUS_TIME_OUT_READ) {
604 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n", 601 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n",
605 stat); 602 stat);
606 trans_done = -1; 603 trans_done = -1;
@@ -608,12 +605,12 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
608 605
609 } else { 606 } else {
610 imxmci_busy_wait_for_status(host, &stat, 607 imxmci_busy_wait_for_status(host, &stat,
611 STATUS_APPL_BUFF_FE, 608 STATUS_APPL_BUFF_FE,
612 20, "imxmci_cpu_driven_data write"); 609 20, "imxmci_cpu_driven_data write");
613 610
614 while((stat & STATUS_APPL_BUFF_FE) && 611 while ((stat & STATUS_APPL_BUFF_FE) &&
615 (host->data_cnt < host->dma_size)) { 612 (host->data_cnt < host->dma_size)) {
616 if(burst_len >= host->dma_size - host->data_cnt) { 613 if (burst_len >= host->dma_size - host->data_cnt) {
617 burst_len = host->dma_size - host->data_cnt; 614 burst_len = host->dma_size - host->data_cnt;
618 host->data_cnt = host->dma_size; 615 host->data_cnt = host->dma_size;
619 trans_done = 1; 616 trans_done = 1;
@@ -621,10 +618,10 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
621 host->data_cnt += burst_len; 618 host->data_cnt += burst_len;
622 } 619 }
623 620
624 for(i = burst_len; i>0 ; i-=2) 621 for (i = burst_len; i > 0 ; i -= 2)
625 MMC_BUFFER_ACCESS = *(host->data_ptr++); 622 writew(*(host->data_ptr++), host->base + MMC_REG_BUFFER_ACCESS);
626 623
627 stat = MMC_STATUS; 624 stat = readw(host->base + MMC_REG_STATUS);
628 625
629 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n", 626 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n",
630 burst_len, stat); 627 burst_len, stat);
@@ -639,7 +636,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
639static void imxmci_dma_irq(int dma, void *devid) 636static void imxmci_dma_irq(int dma, void *devid)
640{ 637{
641 struct imxmci_host *host = devid; 638 struct imxmci_host *host = devid;
642 uint32_t stat = MMC_STATUS; 639 u32 stat = readw(host->base + MMC_REG_STATUS);
643 640
644 atomic_set(&host->stuck_timeout, 0); 641 atomic_set(&host->stuck_timeout, 0);
645 host->status_reg = stat; 642 host->status_reg = stat;
@@ -650,10 +647,11 @@ static void imxmci_dma_irq(int dma, void *devid)
650static irqreturn_t imxmci_irq(int irq, void *devid) 647static irqreturn_t imxmci_irq(int irq, void *devid)
651{ 648{
652 struct imxmci_host *host = devid; 649 struct imxmci_host *host = devid;
653 uint32_t stat = MMC_STATUS; 650 u32 stat = readw(host->base + MMC_REG_STATUS);
654 int handled = 1; 651 int handled = 1;
655 652
656 MMC_INT_MASK = host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT; 653 writew(host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT,
654 host->base + MMC_REG_INT_MASK);
657 655
658 atomic_set(&host->stuck_timeout, 0); 656 atomic_set(&host->stuck_timeout, 0);
659 host->status_reg = stat; 657 host->status_reg = stat;
@@ -671,10 +669,10 @@ static void imxmci_tasklet_fnc(unsigned long data)
671 unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */ 669 unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */
672 int timeout = 0; 670 int timeout = 0;
673 671
674 if(atomic_read(&host->stuck_timeout) > 4) { 672 if (atomic_read(&host->stuck_timeout) > 4) {
675 char *what; 673 char *what;
676 timeout = 1; 674 timeout = 1;
677 stat = MMC_STATUS; 675 stat = readw(host->base + MMC_REG_STATUS);
678 host->status_reg = stat; 676 host->status_reg = stat;
679 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) 677 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
680 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) 678 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
@@ -683,29 +681,37 @@ static void imxmci_tasklet_fnc(unsigned long data)
683 what = "RESP"; 681 what = "RESP";
684 else 682 else
685 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) 683 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
686 if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events)) 684 if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
687 what = "DATA"; 685 what = "DATA";
688 else 686 else
689 what = "DMA"; 687 what = "DMA";
690 else 688 else
691 what = "???"; 689 what = "???";
692 690
693 dev_err(mmc_dev(host->mmc), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n", 691 dev_err(mmc_dev(host->mmc),
694 what, stat, MMC_INT_MASK); 692 "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
695 dev_err(mmc_dev(host->mmc), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n", 693 what, stat,
696 MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma)); 694 readw(host->base + MMC_REG_INT_MASK));
695 dev_err(mmc_dev(host->mmc),
696 "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
697 readw(host->base + MMC_REG_CMD_DAT_CONT),
698 readw(host->base + MMC_REG_BLK_LEN),
699 readw(host->base + MMC_REG_NOB),
700 CCR(host->dma));
697 dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n", 701 dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n",
698 host->cmd?host->cmd->opcode:0, host->prev_cmd_code, 1<<host->actual_bus_width, host->dma_size); 702 host->cmd ? host->cmd->opcode : 0,
703 host->prev_cmd_code,
704 1 << host->actual_bus_width, host->dma_size);
699 } 705 }
700 706
701 if(!host->present || timeout) 707 if (!host->present || timeout)
702 host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ | 708 host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ |
703 STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR; 709 STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
704 710
705 if(test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) { 711 if (test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
706 clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events); 712 clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
707 713
708 stat = MMC_STATUS; 714 stat = readw(host->base + MMC_REG_STATUS);
709 /* 715 /*
710 * This is not required in theory, but there is chance to miss some flag 716 * This is not required in theory, but there is chance to miss some flag
711 * which clears automatically by mask write, FreeScale original code keeps 717 * which clears automatically by mask write, FreeScale original code keeps
@@ -713,63 +719,62 @@ static void imxmci_tasklet_fnc(unsigned long data)
713 */ 719 */
714 stat |= host->status_reg; 720 stat |= host->status_reg;
715 721
716 if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) 722 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
717 stat &= ~STATUS_CRC_READ_ERR; 723 stat &= ~STATUS_CRC_READ_ERR;
718 724
719 if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) { 725 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
720 imxmci_busy_wait_for_status(host, &stat, 726 imxmci_busy_wait_for_status(host, &stat,
721 STATUS_END_CMD_RESP | STATUS_ERR_MASK, 727 STATUS_END_CMD_RESP | STATUS_ERR_MASK,
722 20, "imxmci_tasklet_fnc resp (ERRATUM #4)"); 728 20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
723 } 729 }
724 730
725 if(stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) { 731 if (stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
726 if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) 732 if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
727 imxmci_cmd_done(host, stat); 733 imxmci_cmd_done(host, stat);
728 if(host->data && (stat & STATUS_ERR_MASK)) 734 if (host->data && (stat & STATUS_ERR_MASK))
729 imxmci_data_done(host, stat); 735 imxmci_data_done(host, stat);
730 } 736 }
731 737
732 if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) { 738 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
733 stat |= MMC_STATUS; 739 stat |= readw(host->base + MMC_REG_STATUS);
734 if(imxmci_cpu_driven_data(host, &stat)){ 740 if (imxmci_cpu_driven_data(host, &stat)) {
735 if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) 741 if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
736 imxmci_cmd_done(host, stat); 742 imxmci_cmd_done(host, stat);
737 atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m, 743 atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m,
738 &host->pending_events); 744 &host->pending_events);
739 imxmci_data_done(host, stat); 745 imxmci_data_done(host, stat);
740 } 746 }
741 } 747 }
742 } 748 }
743 749
744 if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) && 750 if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
745 !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) { 751 !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
746 752
747 stat = MMC_STATUS; 753 stat = readw(host->base + MMC_REG_STATUS);
748 /* Same as above */ 754 /* Same as above */
749 stat |= host->status_reg; 755 stat |= host->status_reg;
750 756
751 if(host->dma_dir == DMA_TO_DEVICE) { 757 if (host->dma_dir == DMA_TO_DEVICE)
752 data_dir_mask = STATUS_WRITE_OP_DONE; 758 data_dir_mask = STATUS_WRITE_OP_DONE;
753 } else { 759 else
754 data_dir_mask = STATUS_DATA_TRANS_DONE; 760 data_dir_mask = STATUS_DATA_TRANS_DONE;
755 }
756 761
757 if(stat & data_dir_mask) { 762 if (stat & data_dir_mask) {
758 clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events); 763 clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
759 imxmci_data_done(host, stat); 764 imxmci_data_done(host, stat);
760 } 765 }
761 } 766 }
762 767
763 if(test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) { 768 if (test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
764 769
765 if(host->cmd) 770 if (host->cmd)
766 imxmci_cmd_done(host, STATUS_TIME_OUT_RESP); 771 imxmci_cmd_done(host, STATUS_TIME_OUT_RESP);
767 772
768 if(host->data) 773 if (host->data)
769 imxmci_data_done(host, STATUS_TIME_OUT_READ | 774 imxmci_data_done(host, STATUS_TIME_OUT_READ |
770 STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR); 775 STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR);
771 776
772 if(host->req) 777 if (host->req)
773 imxmci_finish_request(host, host->req); 778 imxmci_finish_request(host, host->req);
774 779
775 mmc_detect_change(host->mmc, msecs_to_jiffies(100)); 780 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
@@ -796,9 +801,8 @@ static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req)
796 if (req->data->flags & MMC_DATA_WRITE) 801 if (req->data->flags & MMC_DATA_WRITE)
797 cmdat |= CMD_DAT_CONT_WRITE; 802 cmdat |= CMD_DAT_CONT_WRITE;
798 803
799 if (req->data->flags & MMC_DATA_STREAM) { 804 if (req->data->flags & MMC_DATA_STREAM)
800 cmdat |= CMD_DAT_CONT_STREAM_BLOCK; 805 cmdat |= CMD_DAT_CONT_STREAM_BLOCK;
801 }
802 } 806 }
803 807
804 imxmci_start_cmd(host, req->cmd, cmdat); 808 imxmci_start_cmd(host, req->cmd, cmdat);
@@ -811,36 +815,37 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
811 struct imxmci_host *host = mmc_priv(mmc); 815 struct imxmci_host *host = mmc_priv(mmc);
812 int prescaler; 816 int prescaler;
813 817
814 if( ios->bus_width==MMC_BUS_WIDTH_4 ) { 818 if (ios->bus_width == MMC_BUS_WIDTH_4) {
815 host->actual_bus_width = MMC_BUS_WIDTH_4; 819 host->actual_bus_width = MMC_BUS_WIDTH_4;
816 imx_gpio_mode(PB11_PF_SD_DAT3); 820 imx_gpio_mode(PB11_PF_SD_DAT3);
817 }else{ 821 } else {
818 host->actual_bus_width = MMC_BUS_WIDTH_1; 822 host->actual_bus_width = MMC_BUS_WIDTH_1;
819 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11); 823 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
820 } 824 }
821 825
822 if ( host->power_mode != ios->power_mode ) { 826 if (host->power_mode != ios->power_mode) {
823 switch (ios->power_mode) { 827 switch (ios->power_mode) {
824 case MMC_POWER_OFF: 828 case MMC_POWER_OFF:
825 break; 829 break;
826 case MMC_POWER_UP: 830 case MMC_POWER_UP:
827 set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events); 831 set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
828 break; 832 break;
829 case MMC_POWER_ON: 833 case MMC_POWER_ON:
830 break; 834 break;
831 } 835 }
832 host->power_mode = ios->power_mode; 836 host->power_mode = ios->power_mode;
833 } 837 }
834 838
835 if ( ios->clock ) { 839 if (ios->clock) {
836 unsigned int clk; 840 unsigned int clk;
841 u16 reg;
837 842
838 /* The prescaler is 5 for PERCLK2 equal to 96MHz 843 /* The prescaler is 5 for PERCLK2 equal to 96MHz
839 * then 96MHz / 5 = 19.2 MHz 844 * then 96MHz / 5 = 19.2 MHz
840 */ 845 */
841 clk = clk_get_rate(host->clk); 846 clk = clk_get_rate(host->clk);
842 prescaler=(clk+(CLK_RATE*7)/8)/CLK_RATE; 847 prescaler = (clk + (CLK_RATE * 7) / 8) / CLK_RATE;
843 switch(prescaler) { 848 switch (prescaler) {
844 case 0: 849 case 0:
845 case 1: prescaler = 0; 850 case 1: prescaler = 0;
846 break; 851 break;
@@ -858,24 +863,29 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
858 dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n", 863 dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n",
859 clk, prescaler); 864 clk, prescaler);
860 865
861 for(clk=0; clk<8; clk++) { 866 for (clk = 0; clk < 8; clk++) {
862 int x; 867 int x;
863 x = CLK_RATE / (1<<clk); 868 x = CLK_RATE / (1 << clk);
864 if( x <= ios->clock) 869 if (x <= ios->clock)
865 break; 870 break;
866 } 871 }
867 872
868 MMC_STR_STP_CLK |= STR_STP_CLK_ENABLE; /* enable controller */ 873 /* enable controller */
874 reg = readw(host->base + MMC_REG_STR_STP_CLK);
875 writew(reg | STR_STP_CLK_ENABLE,
876 host->base + MMC_REG_STR_STP_CLK);
869 877
870 imxmci_stop_clock(host); 878 imxmci_stop_clock(host);
871 MMC_CLK_RATE = (prescaler<<3) | clk; 879 writew((prescaler << 3) | clk, host->base + MMC_REG_CLK_RATE);
872 /* 880 /*
873 * Under my understanding, clock should not be started there, because it would 881 * Under my understanding, clock should not be started there, because it would
874 * initiate SDHC sequencer and send last or random command into card 882 * initiate SDHC sequencer and send last or random command into card
875 */ 883 */
876 /*imxmci_start_clock(host);*/ 884 /* imxmci_start_clock(host); */
877 885
878 dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE); 886 dev_dbg(mmc_dev(host->mmc),
887 "MMC_CLK_RATE: 0x%08x\n",
888 readw(host->base + MMC_REG_CLK_RATE));
879 } else { 889 } else {
880 imxmci_stop_clock(host); 890 imxmci_stop_clock(host);
881 } 891 }
@@ -915,10 +925,10 @@ static void imxmci_check_status(unsigned long data)
915 tasklet_schedule(&host->tasklet); 925 tasklet_schedule(&host->tasklet);
916 } 926 }
917 927
918 if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) || 928 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
919 test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) { 929 test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
920 atomic_inc(&host->stuck_timeout); 930 atomic_inc(&host->stuck_timeout);
921 if(atomic_read(&host->stuck_timeout) > 4) 931 if (atomic_read(&host->stuck_timeout) > 4)
922 tasklet_schedule(&host->tasklet); 932 tasklet_schedule(&host->tasklet);
923 } else { 933 } else {
924 atomic_set(&host->stuck_timeout, 0); 934 atomic_set(&host->stuck_timeout, 0);
@@ -934,6 +944,7 @@ static int imxmci_probe(struct platform_device *pdev)
934 struct imxmci_host *host = NULL; 944 struct imxmci_host *host = NULL;
935 struct resource *r; 945 struct resource *r;
936 int ret = 0, irq; 946 int ret = 0, irq;
947 u16 rev_no;
937 948
938 printk(KERN_INFO "i.MX mmc driver\n"); 949 printk(KERN_INFO "i.MX mmc driver\n");
939 950
@@ -942,7 +953,8 @@ static int imxmci_probe(struct platform_device *pdev)
942 if (!r || irq < 0) 953 if (!r || irq < 0)
943 return -ENXIO; 954 return -ENXIO;
944 955
945 if (!request_mem_region(r->start, 0x100, pdev->name)) 956 r = request_mem_region(r->start, resource_size(r), pdev->name);
957 if (!r)
946 return -EBUSY; 958 return -EBUSY;
947 959
948 mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev); 960 mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev);
@@ -966,6 +978,12 @@ static int imxmci_probe(struct platform_device *pdev)
966 mmc->max_blk_count = 65535; 978 mmc->max_blk_count = 65535;
967 979
968 host = mmc_priv(mmc); 980 host = mmc_priv(mmc);
981 host->base = ioremap(r->start, resource_size(r));
982 if (!host->base) {
983 ret = -ENOMEM;
984 goto out;
985 }
986
969 host->mmc = mmc; 987 host->mmc = mmc;
970 host->dma_allocated = 0; 988 host->dma_allocated = 0;
971 host->pdata = pdev->dev.platform_data; 989 host->pdata = pdev->dev.platform_data;
@@ -993,18 +1011,20 @@ static int imxmci_probe(struct platform_device *pdev)
993 imx_gpio_mode(PB12_PF_SD_CLK); 1011 imx_gpio_mode(PB12_PF_SD_CLK);
994 imx_gpio_mode(PB13_PF_SD_CMD); 1012 imx_gpio_mode(PB13_PF_SD_CMD);
995 1013
996 imxmci_softreset(); 1014 imxmci_softreset(host);
997 1015
998 if ( MMC_REV_NO != 0x390 ) { 1016 rev_no = readw(host->base + MMC_REG_REV_NO);
1017 if (rev_no != 0x390) {
999 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n", 1018 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1000 MMC_REV_NO); 1019 readw(host->base + MMC_REG_REV_NO));
1001 goto out; 1020 goto out;
1002 } 1021 }
1003 1022
1004 MMC_READ_TO = 0x2db4; /* recommended in data sheet */ 1023 /* recommended in data sheet */
1024 writew(0x2db4, host->base + MMC_REG_READ_TO);
1005 1025
1006 host->imask = IMXMCI_INT_MASK_DEFAULT; 1026 host->imask = IMXMCI_INT_MASK_DEFAULT;
1007 MMC_INT_MASK = host->imask; 1027 writew(host->imask, host->base + MMC_REG_INT_MASK);
1008 1028
1009 host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW); 1029 host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
1010 if(host->dma < 0) { 1030 if(host->dma < 0) {
@@ -1012,7 +1032,7 @@ static int imxmci_probe(struct platform_device *pdev)
1012 ret = -EBUSY; 1032 ret = -EBUSY;
1013 goto out; 1033 goto out;
1014 } 1034 }
1015 host->dma_allocated=1; 1035 host->dma_allocated = 1;
1016 imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host); 1036 imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host);
1017 1037
1018 tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host); 1038 tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host);
@@ -1032,7 +1052,7 @@ static int imxmci_probe(struct platform_device *pdev)
1032 host->timer.data = (unsigned long)host; 1052 host->timer.data = (unsigned long)host;
1033 host->timer.function = imxmci_check_status; 1053 host->timer.function = imxmci_check_status;
1034 add_timer(&host->timer); 1054 add_timer(&host->timer);
1035 mod_timer(&host->timer, jiffies + (HZ>>1)); 1055 mod_timer(&host->timer, jiffies + (HZ >> 1));
1036 1056
1037 platform_set_drvdata(pdev, mmc); 1057 platform_set_drvdata(pdev, mmc);
1038 1058
@@ -1042,18 +1062,20 @@ static int imxmci_probe(struct platform_device *pdev)
1042 1062
1043out: 1063out:
1044 if (host) { 1064 if (host) {
1045 if(host->dma_allocated){ 1065 if (host->dma_allocated) {
1046 imx_dma_free(host->dma); 1066 imx_dma_free(host->dma);
1047 host->dma_allocated=0; 1067 host->dma_allocated = 0;
1048 } 1068 }
1049 if (host->clk) { 1069 if (host->clk) {
1050 clk_disable(host->clk); 1070 clk_disable(host->clk);
1051 clk_put(host->clk); 1071 clk_put(host->clk);
1052 } 1072 }
1073 if (host->base)
1074 iounmap(host->base);
1053 } 1075 }
1054 if (mmc) 1076 if (mmc)
1055 mmc_free_host(mmc); 1077 mmc_free_host(mmc);
1056 release_mem_region(r->start, 0x100); 1078 release_mem_region(r->start, resource_size(r));
1057 return ret; 1079 return ret;
1058} 1080}
1059 1081
@@ -1072,9 +1094,10 @@ static int imxmci_remove(struct platform_device *pdev)
1072 mmc_remove_host(mmc); 1094 mmc_remove_host(mmc);
1073 1095
1074 free_irq(host->irq, host); 1096 free_irq(host->irq, host);
1075 if(host->dma_allocated){ 1097 iounmap(host->base);
1098 if (host->dma_allocated) {
1076 imx_dma_free(host->dma); 1099 imx_dma_free(host->dma);
1077 host->dma_allocated=0; 1100 host->dma_allocated = 0;
1078 } 1101 }
1079 1102
1080 tasklet_kill(&host->tasklet); 1103 tasklet_kill(&host->tasklet);
@@ -1082,7 +1105,7 @@ static int imxmci_remove(struct platform_device *pdev)
1082 clk_disable(host->clk); 1105 clk_disable(host->clk);
1083 clk_put(host->clk); 1106 clk_put(host->clk);
1084 1107
1085 release_mem_region(host->res->start, 0x100); 1108 release_mem_region(host->res->start, resource_size(host->res));
1086 1109
1087 mmc_free_host(mmc); 1110 mmc_free_host(mmc);
1088 } 1111 }
@@ -1109,7 +1132,7 @@ static int imxmci_resume(struct platform_device *dev)
1109 1132
1110 if (mmc) { 1133 if (mmc) {
1111 host = mmc_priv(mmc); 1134 host = mmc_priv(mmc);
1112 if(host) 1135 if (host)
1113 set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events); 1136 set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
1114 ret = mmc_resume_host(mmc); 1137 ret = mmc_resume_host(mmc);
1115 } 1138 }
diff --git a/drivers/mmc/host/imxmmc.h b/drivers/mmc/host/imxmmc.h
index e5339e334dbb..09d5d4ee3a77 100644
--- a/drivers/mmc/host/imxmmc.h
+++ b/drivers/mmc/host/imxmmc.h
@@ -1,24 +1,21 @@
1#define MMC_REG_STR_STP_CLK 0x00
2#define MMC_REG_STATUS 0x04
3#define MMC_REG_CLK_RATE 0x08
4#define MMC_REG_CMD_DAT_CONT 0x0C
5#define MMC_REG_RES_TO 0x10
6#define MMC_REG_READ_TO 0x14
7#define MMC_REG_BLK_LEN 0x18
8#define MMC_REG_NOB 0x1C
9#define MMC_REG_REV_NO 0x20
10#define MMC_REG_INT_MASK 0x24
11#define MMC_REG_CMD 0x28
12#define MMC_REG_ARGH 0x2C
13#define MMC_REG_ARGL 0x30
14#define MMC_REG_RES_FIFO 0x34
15#define MMC_REG_BUFFER_ACCESS 0x38
1 16
2# define __REG16(x) (*((volatile u16 *)IO_ADDRESS(x))) 17#define STR_STP_CLK_IPG_CLK_GATE_DIS (1<<15)
3 18#define STR_STP_CLK_IPG_PERCLK_GATE_DIS (1<<14)
4#define MMC_STR_STP_CLK __REG16(IMX_MMC_BASE + 0x00)
5#define MMC_STATUS __REG16(IMX_MMC_BASE + 0x04)
6#define MMC_CLK_RATE __REG16(IMX_MMC_BASE + 0x08)
7#define MMC_CMD_DAT_CONT __REG16(IMX_MMC_BASE + 0x0C)
8#define MMC_RES_TO __REG16(IMX_MMC_BASE + 0x10)
9#define MMC_READ_TO __REG16(IMX_MMC_BASE + 0x14)
10#define MMC_BLK_LEN __REG16(IMX_MMC_BASE + 0x18)
11#define MMC_NOB __REG16(IMX_MMC_BASE + 0x1C)
12#define MMC_REV_NO __REG16(IMX_MMC_BASE + 0x20)
13#define MMC_INT_MASK __REG16(IMX_MMC_BASE + 0x24)
14#define MMC_CMD __REG16(IMX_MMC_BASE + 0x28)
15#define MMC_ARGH __REG16(IMX_MMC_BASE + 0x2C)
16#define MMC_ARGL __REG16(IMX_MMC_BASE + 0x30)
17#define MMC_RES_FIFO __REG16(IMX_MMC_BASE + 0x34)
18#define MMC_BUFFER_ACCESS __REG16(IMX_MMC_BASE + 0x38)
19#define MMC_BUFFER_ACCESS_OFS 0x38
20
21
22#define STR_STP_CLK_ENDIAN (1<<5) 19#define STR_STP_CLK_ENDIAN (1<<5)
23#define STR_STP_CLK_RESET (1<<3) 20#define STR_STP_CLK_RESET (1<<3)
24#define STR_STP_CLK_ENABLE (1<<2) 21#define STR_STP_CLK_ENABLE (1<<2)
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 1c2e9450d663..f8ae0400c49c 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -408,7 +408,7 @@ config MTD_NAND_FSL_UPM
408 408
409config MTD_NAND_MXC 409config MTD_NAND_MXC
410 tristate "MXC NAND support" 410 tristate "MXC NAND support"
411 depends on ARCH_MX2 411 depends on ARCH_MX2 || ARCH_MX3
412 help 412 help
413 This enables the driver for the NAND flash controller on the 413 This enables the driver for the NAND flash controller on the
414 MXC processors. 414 MXC processors.
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c
index 3f90f1bbbbcd..73dea88cceb3 100644
--- a/drivers/serial/imx.c
+++ b/drivers/serial/imx.c
@@ -66,7 +66,7 @@
66#define ONEMS 0xb0 /* One Millisecond register */ 66#define ONEMS 0xb0 /* One Millisecond register */
67#define UTS 0xb4 /* UART Test Register */ 67#define UTS 0xb4 /* UART Test Register */
68#endif 68#endif
69#ifdef CONFIG_ARCH_IMX 69#if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1)
70#define BIPR1 0xb0 /* Incremental Preset Register 1 */ 70#define BIPR1 0xb0 /* Incremental Preset Register 1 */
71#define BIPR2 0xb4 /* Incremental Preset Register 2 */ 71#define BIPR2 0xb4 /* Incremental Preset Register 2 */
72#define BIPR3 0xb8 /* Incremental Preset Register 3 */ 72#define BIPR3 0xb8 /* Incremental Preset Register 3 */
@@ -96,7 +96,7 @@
96#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 96#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
97#define UCR1_SNDBRK (1<<4) /* Send break */ 97#define UCR1_SNDBRK (1<<4) /* Send break */
98#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 98#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
99#ifdef CONFIG_ARCH_IMX 99#if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1)
100#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ 100#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
101#endif 101#endif
102#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2 102#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
@@ -187,7 +187,7 @@
187#define MAX_INTERNAL_IRQ IMX_IRQS 187#define MAX_INTERNAL_IRQ IMX_IRQS
188#endif 188#endif
189 189
190#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2 190#ifdef CONFIG_ARCH_MXC
191#define SERIAL_IMX_MAJOR 207 191#define SERIAL_IMX_MAJOR 207
192#define MINOR_START 16 192#define MINOR_START 16
193#define DEV_NAME "ttymxc" 193#define DEV_NAME "ttymxc"
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-22 06:59:23 -0500