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-rw-r--r--drivers/char/drm/radeon_drm.h7
-rw-r--r--drivers/char/drm/radeon_drv.h8
-rw-r--r--drivers/char/drm/radeon_state.c36
3 files changed, 48 insertions, 3 deletions
diff --git a/drivers/char/drm/radeon_drm.h b/drivers/char/drm/radeon_drm.h
index c8e279e89c2e..8d6350dd5360 100644
--- a/drivers/char/drm/radeon_drm.h
+++ b/drivers/char/drm/radeon_drm.h
@@ -161,7 +161,8 @@
161#define R200_EMIT_PP_TXCTLALL_3 91 161#define R200_EMIT_PP_TXCTLALL_3 91
162#define R200_EMIT_PP_TXCTLALL_4 92 162#define R200_EMIT_PP_TXCTLALL_4 92
163#define R200_EMIT_PP_TXCTLALL_5 93 163#define R200_EMIT_PP_TXCTLALL_5 93
164#define RADEON_MAX_STATE_PACKETS 94 164#define R200_EMIT_VAP_PVS_CNTL 94
165#define RADEON_MAX_STATE_PACKETS 95
165 166
166/* Commands understood by cmd_buffer ioctl. More can be added but 167/* Commands understood by cmd_buffer ioctl. More can be added but
167 * obviously these can't be removed or changed: 168 * obviously these can't be removed or changed:
@@ -176,6 +177,7 @@
176#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: 177#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
177 * doesn't make the cpu wait, just 178 * doesn't make the cpu wait, just
178 * the graphics hardware */ 179 * the graphics hardware */
180#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */
179 181
180typedef union { 182typedef union {
181 int i; 183 int i;
@@ -192,6 +194,9 @@ typedef union {
192 unsigned char cmd_type, offset, stride, count; 194 unsigned char cmd_type, offset, stride, count;
193 } vectors; 195 } vectors;
194 struct { 196 struct {
197 unsigned char cmd_type, addr_lo, addr_hi, count;
198 } veclinear;
199 struct {
195 unsigned char cmd_type, buf_idx, pad0, pad1; 200 unsigned char cmd_type, buf_idx, pad0, pad1;
196 } dma; 201 } dma;
197 struct { 202 struct {
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index b2a6f92d1f0f..e5a256f5429c 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -38,7 +38,7 @@
38 38
39#define DRIVER_NAME "radeon" 39#define DRIVER_NAME "radeon"
40#define DRIVER_DESC "ATI Radeon" 40#define DRIVER_DESC "ATI Radeon"
41#define DRIVER_DATE "20060519" 41#define DRIVER_DATE "20060524"
42 42
43/* Interface history: 43/* Interface history:
44 * 44 *
@@ -93,9 +93,11 @@
93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL) 93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
94 * 1.23- Add new radeon memory map work from benh 94 * 1.23- Add new radeon memory map work from benh
95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300) 95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
97 * new packet type)
96 */ 98 */
97#define DRIVER_MAJOR 1 99#define DRIVER_MAJOR 1
98#define DRIVER_MINOR 24 100#define DRIVER_MINOR 25
99#define DRIVER_PATCHLEVEL 0 101#define DRIVER_PATCHLEVEL 0
100 102
101/* 103/*
@@ -907,6 +909,8 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
907#define R200_PP_AFS_0 0x2f80 909#define R200_PP_AFS_0 0x2f80
908#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ 910#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
909 911
912#define R200_VAP_PVS_CNTL_1 0x22D0
913
910/* Constants */ 914/* Constants */
911#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 915#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
912 916
diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c
index 4ca6bd13d589..5bb2234a9094 100644
--- a/drivers/char/drm/radeon_state.c
+++ b/drivers/char/drm/radeon_state.c
@@ -249,6 +249,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
249 case R200_EMIT_PP_TXCTLALL_3: 249 case R200_EMIT_PP_TXCTLALL_3:
250 case R200_EMIT_PP_TXCTLALL_4: 250 case R200_EMIT_PP_TXCTLALL_4:
251 case R200_EMIT_PP_TXCTLALL_5: 251 case R200_EMIT_PP_TXCTLALL_5:
252 case R200_EMIT_VAP_PVS_CNTL:
252 /* These packets don't contain memory offsets */ 253 /* These packets don't contain memory offsets */
253 break; 254 break;
254 255
@@ -626,6 +627,7 @@ static struct {
626 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, 627 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
627 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, 628 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
628 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, 629 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
630 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
629}; 631};
630 632
631/* ================================================================ 633/* ================================================================
@@ -2608,6 +2610,32 @@ static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv,
2608 return 0; 2610 return 0;
2609} 2611}
2610 2612
2613static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv,
2614 drm_radeon_cmd_header_t header,
2615 drm_radeon_kcmd_buffer_t *cmdbuf)
2616{
2617 int sz = header.veclinear.count * 4;
2618 int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8);
2619 RING_LOCALS;
2620
2621 if (!sz)
2622 return 0;
2623 if (sz * 4 > cmdbuf->bufsz)
2624 return DRM_ERR(EINVAL);
2625
2626 BEGIN_RING(5 + sz);
2627 OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
2628 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
2629 OUT_RING(start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
2630 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
2631 OUT_RING_TABLE(cmdbuf->buf, sz);
2632 ADVANCE_RING();
2633
2634 cmdbuf->buf += sz * sizeof(int);
2635 cmdbuf->bufsz -= sz * sizeof(int);
2636 return 0;
2637}
2638
2611static int radeon_emit_packet3(drm_device_t * dev, 2639static int radeon_emit_packet3(drm_device_t * dev,
2612 drm_file_t * filp_priv, 2640 drm_file_t * filp_priv,
2613 drm_radeon_kcmd_buffer_t *cmdbuf) 2641 drm_radeon_kcmd_buffer_t *cmdbuf)
@@ -2866,6 +2894,14 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS)
2866 goto err; 2894 goto err;
2867 } 2895 }
2868 break; 2896 break;
2897 case RADEON_CMD_VECLINEAR:
2898 DRM_DEBUG("RADEON_CMD_VECLINEAR\n");
2899 if (radeon_emit_veclinear(dev_priv, header, &cmdbuf)) {
2900 DRM_ERROR("radeon_emit_veclinear failed\n");
2901 goto err;
2902 }
2903 break;
2904
2869 default: 2905 default:
2870 DRM_ERROR("bad cmd_type %d at %p\n", 2906 DRM_ERROR("bad cmd_type %d at %p\n",
2871 header.header.cmd_type, 2907 header.header.cmd_type,