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-rw-r--r--drivers/ata/Kconfig9
-rw-r--r--drivers/ata/Makefile1
-rw-r--r--drivers/ata/ata_piix.c35
-rw-r--r--drivers/ata/libata-core.c9
-rw-r--r--drivers/ata/libata-scsi.c5
-rw-r--r--drivers/ata/pata_cs5536.c346
-rw-r--r--drivers/ata/pata_pcmcia.c2
-rw-r--r--drivers/ata/pata_sil680.c61
-rw-r--r--drivers/ata/sata_nv.c851
9 files changed, 1298 insertions, 21 deletions
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 4672066167e3..33f5eb038773 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -272,6 +272,15 @@ config PATA_CS5535
272 272
273 If unsure, say N. 273 If unsure, say N.
274 274
275config PATA_CS5536
276 tristate "CS5536 PATA support (Experimental)"
277 depends on PCI && X86 && !X86_64 && EXPERIMENTAL
278 help
279 This option enables support for the AMD CS5536
280 companion chip used with the Geode LX processor family.
281
282 If unsure, say N.
283
275config PATA_CYPRESS 284config PATA_CYPRESS
276 tristate "Cypress CY82C693 PATA support (Very Experimental)" 285 tristate "Cypress CY82C693 PATA support (Very Experimental)"
277 depends on PCI && EXPERIMENTAL 286 depends on PCI && EXPERIMENTAL
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 2a63645003eb..6bdc307649e6 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_PATA_CMD64X) += pata_cmd64x.o
28obj-$(CONFIG_PATA_CS5520) += pata_cs5520.o 28obj-$(CONFIG_PATA_CS5520) += pata_cs5520.o
29obj-$(CONFIG_PATA_CS5530) += pata_cs5530.o 29obj-$(CONFIG_PATA_CS5530) += pata_cs5530.o
30obj-$(CONFIG_PATA_CS5535) += pata_cs5535.o 30obj-$(CONFIG_PATA_CS5535) += pata_cs5535.o
31obj-$(CONFIG_PATA_CS5536) += pata_cs5536.o
31obj-$(CONFIG_PATA_CYPRESS) += pata_cypress.o 32obj-$(CONFIG_PATA_CYPRESS) += pata_cypress.o
32obj-$(CONFIG_PATA_EFAR) += pata_efar.o 33obj-$(CONFIG_PATA_EFAR) += pata_efar.o
33obj-$(CONFIG_PATA_HPT366) += pata_hpt366.o 34obj-$(CONFIG_PATA_HPT366) += pata_hpt366.o
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
index 9ce4aa9c2f25..3c6f43e381f4 100644
--- a/drivers/ata/ata_piix.c
+++ b/drivers/ata/ata_piix.c
@@ -130,6 +130,7 @@ enum {
130 ich8_sata_ahci = 9, 130 ich8_sata_ahci = 9,
131 piix_pata_mwdma = 10, /* PIIX3 MWDMA only */ 131 piix_pata_mwdma = 10, /* PIIX3 MWDMA only */
132 tolapai_sata_ahci = 11, 132 tolapai_sata_ahci = 11,
133 ich9_2port_sata = 12,
133 134
134 /* constants for mapping table */ 135 /* constants for mapping table */
135 P0 = 0, /* port 0 */ 136 P0 = 0, /* port 0 */
@@ -238,19 +239,19 @@ static const struct pci_device_id piix_pci_tbl[] = {
238 /* SATA Controller 1 IDE (ICH8) */ 239 /* SATA Controller 1 IDE (ICH8) */
239 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 240 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
240 /* SATA Controller 2 IDE (ICH8) */ 241 /* SATA Controller 2 IDE (ICH8) */
241 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 242 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata },
242 /* Mobile SATA Controller IDE (ICH8M) */ 243 /* Mobile SATA Controller IDE (ICH8M) */
243 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 244 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
244 /* SATA Controller IDE (ICH9) */ 245 /* SATA Controller IDE (ICH9) */
245 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 246 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
246 /* SATA Controller IDE (ICH9) */ 247 /* SATA Controller IDE (ICH9) */
247 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 248 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata },
248 /* SATA Controller IDE (ICH9) */ 249 /* SATA Controller IDE (ICH9) */
249 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 250 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata },
250 /* SATA Controller IDE (ICH9M) */ 251 /* SATA Controller IDE (ICH9M) */
251 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 252 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata },
252 /* SATA Controller IDE (ICH9M) */ 253 /* SATA Controller IDE (ICH9M) */
253 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 254 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata },
254 /* SATA Controller IDE (ICH9M) */ 255 /* SATA Controller IDE (ICH9M) */
255 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 256 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
256 /* SATA Controller IDE (Tolapai) */ 257 /* SATA Controller IDE (Tolapai) */
@@ -448,6 +449,18 @@ static const struct piix_map_db tolapai_map_db = {
448 }, 449 },
449}; 450};
450 451
452static const struct piix_map_db ich9_2port_map_db = {
453 .mask = 0x3,
454 .port_enable = 0x3,
455 .map = {
456 /* PM PS SM SS MAP */
457 { P0, NA, P1, NA }, /* 00b */
458 { RV, RV, RV, RV }, /* 01b */
459 { RV, RV, RV, RV }, /* 10b */
460 { RV, RV, RV, RV },
461 },
462};
463
451static const struct piix_map_db *piix_map_db_table[] = { 464static const struct piix_map_db *piix_map_db_table[] = {
452 [ich5_sata] = &ich5_map_db, 465 [ich5_sata] = &ich5_map_db,
453 [ich6_sata] = &ich6_map_db, 466 [ich6_sata] = &ich6_map_db,
@@ -455,6 +468,7 @@ static const struct piix_map_db *piix_map_db_table[] = {
455 [ich6m_sata_ahci] = &ich6m_map_db, 468 [ich6m_sata_ahci] = &ich6m_map_db,
456 [ich8_sata_ahci] = &ich8_map_db, 469 [ich8_sata_ahci] = &ich8_map_db,
457 [tolapai_sata_ahci] = &tolapai_map_db, 470 [tolapai_sata_ahci] = &tolapai_map_db,
471 [ich9_2port_sata] = &ich9_2port_map_db,
458}; 472};
459 473
460static struct ata_port_info piix_port_info[] = { 474static struct ata_port_info piix_port_info[] = {
@@ -570,6 +584,17 @@ static struct ata_port_info piix_port_info[] = {
570 .udma_mask = ATA_UDMA6, 584 .udma_mask = ATA_UDMA6,
571 .port_ops = &piix_sata_ops, 585 .port_ops = &piix_sata_ops,
572 }, 586 },
587
588 [ich9_2port_sata] =
589 {
590 .sht = &piix_sht,
591 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
592 PIIX_FLAG_AHCI,
593 .pio_mask = 0x1f, /* pio0-4 */
594 .mwdma_mask = 0x07, /* mwdma0-2 */
595 .udma_mask = ATA_UDMA6,
596 .port_ops = &piix_sata_ops,
597 },
573}; 598};
574 599
575static struct pci_bits piix_enable_bits[] = { 600static struct pci_bits piix_enable_bits[] = {
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index b05384a8c326..68699b3e7998 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -3984,6 +3984,7 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
3984 { "ST9120822AS", "3.CLF", ATA_HORKAGE_NONCQ, }, 3984 { "ST9120822AS", "3.CLF", ATA_HORKAGE_NONCQ, },
3985 { "ST9160821AS", "3.CLF", ATA_HORKAGE_NONCQ, }, 3985 { "ST9160821AS", "3.CLF", ATA_HORKAGE_NONCQ, },
3986 { "ST9160821AS", "3.ALD", ATA_HORKAGE_NONCQ, }, 3986 { "ST9160821AS", "3.ALD", ATA_HORKAGE_NONCQ, },
3987 { "ST9160821AS", "3.CCD", ATA_HORKAGE_NONCQ, },
3987 { "ST3160812AS", "3.ADJ", ATA_HORKAGE_NONCQ, }, 3988 { "ST3160812AS", "3.ADJ", ATA_HORKAGE_NONCQ, },
3988 { "ST980813AS", "3.ADB", ATA_HORKAGE_NONCQ, }, 3989 { "ST980813AS", "3.ADB", ATA_HORKAGE_NONCQ, },
3989 { "SAMSUNG HD401LJ", "ZZ100-15", ATA_HORKAGE_NONCQ, }, 3990 { "SAMSUNG HD401LJ", "ZZ100-15", ATA_HORKAGE_NONCQ, },
@@ -4013,8 +4014,14 @@ int strn_pattern_cmp(const char *patt, const char *name, int wildchar)
4013 p = strchr(patt, wildchar); 4014 p = strchr(patt, wildchar);
4014 if (p && ((*(p + 1)) == 0)) 4015 if (p && ((*(p + 1)) == 0))
4015 len = p - patt; 4016 len = p - patt;
4016 else 4017 else {
4017 len = strlen(name); 4018 len = strlen(name);
4019 if (!len) {
4020 if (!*patt)
4021 return 0;
4022 return -1;
4023 }
4024 }
4018 4025
4019 return strncmp(patt, name, len); 4026 return strncmp(patt, name, len);
4020} 4027}
diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c
index ea53e6a570b4..d63c81ed084f 100644
--- a/drivers/ata/libata-scsi.c
+++ b/drivers/ata/libata-scsi.c
@@ -1363,6 +1363,7 @@ nothing_to_do:
1363static void ata_scsi_qc_complete(struct ata_queued_cmd *qc) 1363static void ata_scsi_qc_complete(struct ata_queued_cmd *qc)
1364{ 1364{
1365 struct ata_port *ap = qc->ap; 1365 struct ata_port *ap = qc->ap;
1366 struct ata_eh_info *ehi = &qc->dev->link->eh_info;
1366 struct scsi_cmnd *cmd = qc->scsicmd; 1367 struct scsi_cmnd *cmd = qc->scsicmd;
1367 u8 *cdb = cmd->cmnd; 1368 u8 *cdb = cmd->cmnd;
1368 int need_sense = (qc->err_mask != 0); 1369 int need_sense = (qc->err_mask != 0);
@@ -1376,14 +1377,14 @@ static void ata_scsi_qc_complete(struct ata_queued_cmd *qc)
1376 case ATA_CMD_SET_FEATURES: 1377 case ATA_CMD_SET_FEATURES:
1377 if ((qc->tf.feature == SETFEATURES_WC_ON) || 1378 if ((qc->tf.feature == SETFEATURES_WC_ON) ||
1378 (qc->tf.feature == SETFEATURES_WC_OFF)) { 1379 (qc->tf.feature == SETFEATURES_WC_OFF)) {
1379 ap->link.eh_info.action |= ATA_EH_REVALIDATE; 1380 ehi->action |= ATA_EH_REVALIDATE;
1380 ata_port_schedule_eh(ap); 1381 ata_port_schedule_eh(ap);
1381 } 1382 }
1382 break; 1383 break;
1383 1384
1384 case ATA_CMD_INIT_DEV_PARAMS: /* CHS translation changed */ 1385 case ATA_CMD_INIT_DEV_PARAMS: /* CHS translation changed */
1385 case ATA_CMD_SET_MULTI: /* multi_count changed */ 1386 case ATA_CMD_SET_MULTI: /* multi_count changed */
1386 ap->link.eh_info.action |= ATA_EH_REVALIDATE; 1387 ehi->action |= ATA_EH_REVALIDATE;
1387 ata_port_schedule_eh(ap); 1388 ata_port_schedule_eh(ap);
1388 break; 1389 break;
1389 } 1390 }
diff --git a/drivers/ata/pata_cs5536.c b/drivers/ata/pata_cs5536.c
new file mode 100644
index 000000000000..21405bf14837
--- /dev/null
+++ b/drivers/ata/pata_cs5536.c
@@ -0,0 +1,346 @@
1/*
2 * pata_cs5536.c - CS5536 PATA for new ATA layer
3 * (C) 2007 Martin K. Petersen <mkp@mkp.net>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * Documentation:
19 * Available from AMD web site.
20 *
21 * The IDE timing registers for the CS5536 live in the Geode Machine
22 * Specific Register file and not PCI config space. Most BIOSes
23 * virtualize the PCI registers so the chip looks like a standard IDE
24 * controller. Unfortunately not all implementations get this right.
25 * In particular some have problems with unaligned accesses to the
26 * virtualized PCI registers. This driver always does full dword
27 * writes to work around the issue. Also, in case of a bad BIOS this
28 * driver can be loaded with the "msr=1" parameter which forces using
29 * the Machine Specific Registers to configure the device.
30 */
31
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/pci.h>
35#include <linux/init.h>
36#include <linux/blkdev.h>
37#include <linux/delay.h>
38#include <linux/libata.h>
39#include <scsi/scsi_host.h>
40#include <asm/msr.h>
41
42#define DRV_NAME "pata_cs5536"
43#define DRV_VERSION "0.0.5"
44
45enum {
46 CFG = 0,
47 DTC = 1,
48 CAST = 2,
49 ETC = 3,
50
51 MSR_IDE_BASE = 0x51300000,
52 MSR_IDE_CFG = (MSR_IDE_BASE + 0x10),
53 MSR_IDE_DTC = (MSR_IDE_BASE + 0x12),
54 MSR_IDE_CAST = (MSR_IDE_BASE + 0x13),
55 MSR_IDE_ETC = (MSR_IDE_BASE + 0x14),
56
57 PCI_IDE_CFG = 0x40,
58 PCI_IDE_DTC = 0x48,
59 PCI_IDE_CAST = 0x4c,
60 PCI_IDE_ETC = 0x50,
61
62 IDE_CFG_CHANEN = 0x2,
63 IDE_CFG_CABLE = 0x10000,
64
65 IDE_D0_SHIFT = 24,
66 IDE_D1_SHIFT = 16,
67 IDE_DRV_MASK = 0xff,
68
69 IDE_CAST_D0_SHIFT = 6,
70 IDE_CAST_D1_SHIFT = 4,
71 IDE_CAST_DRV_MASK = 0x3,
72 IDE_CAST_CMD_MASK = 0xff,
73 IDE_CAST_CMD_SHIFT = 24,
74
75 IDE_ETC_NODMA = 0x03,
76};
77
78static int use_msr;
79
80static const u32 msr_reg[4] = {
81 MSR_IDE_CFG, MSR_IDE_DTC, MSR_IDE_CAST, MSR_IDE_ETC,
82};
83
84static const u8 pci_reg[4] = {
85 PCI_IDE_CFG, PCI_IDE_DTC, PCI_IDE_CAST, PCI_IDE_ETC,
86};
87
88static inline int cs5536_read(struct pci_dev *pdev, int reg, int *val)
89{
90 if (unlikely(use_msr)) {
91 u32 dummy;
92
93 rdmsr(msr_reg[reg], *val, dummy);
94 return 0;
95 }
96
97 return pci_read_config_dword(pdev, pci_reg[reg], val);
98}
99
100static inline int cs5536_write(struct pci_dev *pdev, int reg, int val)
101{
102 if (unlikely(use_msr)) {
103 wrmsr(msr_reg[reg], val, 0);
104 return 0;
105 }
106
107 return pci_write_config_dword(pdev, pci_reg[reg], val);
108}
109
110/**
111 * cs5536_cable_detect - detect cable type
112 * @ap: Port to detect on
113 * @deadline: deadline jiffies for the operation
114 *
115 * Perform cable detection for ATA66 capable cable. Return a libata
116 * cable type.
117 */
118
119static int cs5536_cable_detect(struct ata_port *ap)
120{
121 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
122 u32 cfg;
123
124 cs5536_read(pdev, CFG, &cfg);
125
126 if (cfg & (IDE_CFG_CABLE << ap->port_no))
127 return ATA_CBL_PATA80;
128 else
129 return ATA_CBL_PATA40;
130}
131
132/**
133 * cs5536_set_piomode - PIO setup
134 * @ap: ATA interface
135 * @adev: device on the interface
136 */
137
138static void cs5536_set_piomode(struct ata_port *ap, struct ata_device *adev)
139{
140 static const u8 drv_timings[5] = {
141 0x98, 0x55, 0x32, 0x21, 0x20,
142 };
143
144 static const u8 addr_timings[5] = {
145 0x2, 0x1, 0x0, 0x0, 0x0,
146 };
147
148 static const u8 cmd_timings[5] = {
149 0x99, 0x92, 0x90, 0x22, 0x20,
150 };
151
152 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
153 struct ata_device *pair = ata_dev_pair(adev);
154 int mode = adev->pio_mode - XFER_PIO_0;
155 int cmdmode = mode;
156 int dshift = ap->port_no ? IDE_D1_SHIFT : IDE_D0_SHIFT;
157 int cshift = ap->port_no ? IDE_CAST_D1_SHIFT : IDE_CAST_D0_SHIFT;
158 u32 dtc, cast, etc;
159
160 if (pair)
161 cmdmode = min(mode, pair->pio_mode - XFER_PIO_0);
162
163 cs5536_read(pdev, DTC, &dtc);
164 cs5536_read(pdev, CAST, &cast);
165 cs5536_read(pdev, ETC, &etc);
166
167 dtc &= ~(IDE_DRV_MASK << dshift);
168 dtc |= drv_timings[mode] << dshift;
169
170 cast &= ~(IDE_CAST_DRV_MASK << cshift);
171 cast |= addr_timings[mode] << cshift;
172
173 cast &= ~(IDE_CAST_CMD_MASK << IDE_CAST_CMD_SHIFT);
174 cast |= cmd_timings[cmdmode] << IDE_CAST_CMD_SHIFT;
175
176 etc &= ~(IDE_DRV_MASK << dshift);
177 etc |= IDE_ETC_NODMA << dshift;
178
179 cs5536_write(pdev, DTC, dtc);
180 cs5536_write(pdev, CAST, cast);
181 cs5536_write(pdev, ETC, etc);
182}
183
184/**
185 * cs5536_set_dmamode - DMA timing setup
186 * @ap: ATA interface
187 * @adev: Device being configured
188 *
189 */
190
191static void cs5536_set_dmamode(struct ata_port *ap, struct ata_device *adev)
192{
193 static const u8 udma_timings[6] = {
194 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6,
195 };
196
197 static const u8 mwdma_timings[3] = {
198 0x67, 0x21, 0x20,
199 };
200
201 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
202 u32 dtc, etc;
203 int mode = adev->dma_mode;
204 int dshift = ap->port_no ? IDE_D1_SHIFT : IDE_D0_SHIFT;
205
206 if (mode >= XFER_UDMA_0) {
207 cs5536_read(pdev, ETC, &etc);
208
209 etc &= ~(IDE_DRV_MASK << dshift);
210 etc |= udma_timings[mode - XFER_UDMA_0] << dshift;
211
212 cs5536_write(pdev, ETC, etc);
213 } else { /* MWDMA */
214 cs5536_read(pdev, DTC, &dtc);
215
216 dtc &= ~(IDE_DRV_MASK << dshift);
217 dtc |= mwdma_timings[mode] << dshift;
218
219 cs5536_write(pdev, DTC, dtc);
220 }
221}
222
223static struct scsi_host_template cs5536_sht = {
224 .module = THIS_MODULE,
225 .name = DRV_NAME,
226 .ioctl = ata_scsi_ioctl,
227 .queuecommand = ata_scsi_queuecmd,
228 .can_queue = ATA_DEF_QUEUE,
229 .this_id = ATA_SHT_THIS_ID,
230 .sg_tablesize = LIBATA_MAX_PRD,
231 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
232 .emulated = ATA_SHT_EMULATED,
233 .use_clustering = ATA_SHT_USE_CLUSTERING,
234 .proc_name = DRV_NAME,
235 .dma_boundary = ATA_DMA_BOUNDARY,
236 .slave_configure = ata_scsi_slave_config,
237 .slave_destroy = ata_scsi_slave_destroy,
238 .bios_param = ata_std_bios_param,
239};
240
241static struct ata_port_operations cs5536_port_ops = {
242 .port_disable = ata_port_disable,
243 .set_piomode = cs5536_set_piomode,
244 .set_dmamode = cs5536_set_dmamode,
245 .mode_filter = ata_pci_default_filter,
246
247 .tf_load = ata_tf_load,
248 .tf_read = ata_tf_read,
249 .check_status = ata_check_status,
250 .exec_command = ata_exec_command,
251 .dev_select = ata_std_dev_select,
252
253 .freeze = ata_bmdma_freeze,
254 .thaw = ata_bmdma_thaw,
255 .error_handler = ata_bmdma_error_handler,
256 .post_internal_cmd = ata_bmdma_post_internal_cmd,
257 .cable_detect = cs5536_cable_detect,
258
259 .bmdma_setup = ata_bmdma_setup,
260 .bmdma_start = ata_bmdma_start,
261 .bmdma_stop = ata_bmdma_stop,
262 .bmdma_status = ata_bmdma_status,
263
264 .qc_prep = ata_qc_prep,
265 .qc_issue = ata_qc_issue_prot,
266
267 .data_xfer = ata_data_xfer,
268
269 .irq_handler = ata_interrupt,
270 .irq_clear = ata_bmdma_irq_clear,
271 .irq_on = ata_irq_on,
272 .irq_ack = ata_irq_ack,
273
274 .port_start = ata_port_start,
275};
276
277/**
278 * cs5536_init_one
279 * @dev: PCI device
280 * @id: Entry in match table
281 *
282 */
283
284static int cs5536_init_one(struct pci_dev *dev, const struct pci_device_id *id)
285{
286 static const struct ata_port_info info = {
287 .sht = &cs5536_sht,
288 .flags = ATA_FLAG_SLAVE_POSS,
289 .pio_mask = 0x1f,
290 .mwdma_mask = 0x07,
291 .udma_mask = ATA_UDMA5,
292 .port_ops = &cs5536_port_ops,
293 };
294
295 const struct ata_port_info *ppi[] = { &info, &ata_dummy_port_info };
296 u32 cfg;
297
298 if (use_msr)
299 printk(KERN_ERR DRV_NAME ": Using MSR regs instead of PCI\n");
300
301 cs5536_read(dev, CFG, &cfg);
302
303 if ((cfg & IDE_CFG_CHANEN) == 0) {
304 printk(KERN_ERR DRV_NAME ": disabled by BIOS\n");
305 return -ENODEV;
306 }
307
308 return ata_pci_init_one(dev, ppi);
309}
310
311static const struct pci_device_id cs5536[] = {
312 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), },
313 { },
314};
315
316static struct pci_driver cs5536_pci_driver = {
317 .name = DRV_NAME,
318 .id_table = cs5536,
319 .probe = cs5536_init_one,
320 .remove = ata_pci_remove_one,
321#ifdef CONFIG_PM
322 .suspend = ata_pci_device_suspend,
323 .resume = ata_pci_device_resume,
324#endif
325};
326
327static int __init cs5536_init(void)
328{
329 return pci_register_driver(&cs5536_pci_driver);
330}
331
332static void __exit cs5536_exit(void)
333{
334 pci_unregister_driver(&cs5536_pci_driver);
335}
336
337MODULE_AUTHOR("Martin K. Petersen");
338MODULE_DESCRIPTION("low-level driver for the CS5536 IDE controller");
339MODULE_LICENSE("GPL");
340MODULE_DEVICE_TABLE(pci, cs5536);
341MODULE_VERSION(DRV_VERSION);
342module_param_named(msr, use_msr, int, 0644);
343MODULE_PARM_DESC(msr, "Force using MSR to configure IDE function (Default: 0)");
344
345module_init(cs5536_init);
346module_exit(cs5536_exit);
diff --git a/drivers/ata/pata_pcmcia.c b/drivers/ata/pata_pcmcia.c
index 782ff4ada9d1..5db2013230b3 100644
--- a/drivers/ata/pata_pcmcia.c
+++ b/drivers/ata/pata_pcmcia.c
@@ -353,6 +353,7 @@ static void pcmcia_remove_one(struct pcmcia_device *pdev)
353 353
354static struct pcmcia_device_id pcmcia_devices[] = { 354static struct pcmcia_device_id pcmcia_devices[] = {
355 PCMCIA_DEVICE_FUNC_ID(4), 355 PCMCIA_DEVICE_FUNC_ID(4),
356 PCMCIA_DEVICE_MANF_CARD(0x0000, 0x0000), /* Corsair */
356 PCMCIA_DEVICE_MANF_CARD(0x0007, 0x0000), /* Hitachi */ 357 PCMCIA_DEVICE_MANF_CARD(0x0007, 0x0000), /* Hitachi */
357 PCMCIA_DEVICE_MANF_CARD(0x000a, 0x0000), /* I-O Data CFA */ 358 PCMCIA_DEVICE_MANF_CARD(0x000a, 0x0000), /* I-O Data CFA */
358 PCMCIA_DEVICE_MANF_CARD(0x001c, 0x0001), /* Mitsubishi CFA */ 359 PCMCIA_DEVICE_MANF_CARD(0x001c, 0x0001), /* Mitsubishi CFA */
@@ -378,6 +379,7 @@ static struct pcmcia_device_id pcmcia_devices[] = {
378 PCMCIA_DEVICE_PROD_ID12("EXP ", "CD-ROM", 0x0a5c52fd, 0x66536591), 379 PCMCIA_DEVICE_PROD_ID12("EXP ", "CD-ROM", 0x0a5c52fd, 0x66536591),
379 PCMCIA_DEVICE_PROD_ID12("EXP ", "PnPIDE", 0x0a5c52fd, 0x0c694728), 380 PCMCIA_DEVICE_PROD_ID12("EXP ", "PnPIDE", 0x0a5c52fd, 0x0c694728),
380 PCMCIA_DEVICE_PROD_ID12("FREECOM", "PCCARD-IDE", 0x5714cbf7, 0x48e0ab8e), 381 PCMCIA_DEVICE_PROD_ID12("FREECOM", "PCCARD-IDE", 0x5714cbf7, 0x48e0ab8e),
382 PCMCIA_DEVICE_PROD_ID12("Hyperstone", "Model1", 0x3d5b9ef5, 0xca6ab420),
381 PCMCIA_DEVICE_PROD_ID12("HITACHI", "FLASH", 0xf4f43949, 0x9eb86aae), 383 PCMCIA_DEVICE_PROD_ID12("HITACHI", "FLASH", 0xf4f43949, 0x9eb86aae),
382 PCMCIA_DEVICE_PROD_ID12("HITACHI", "microdrive", 0xf4f43949, 0xa6d76178), 384 PCMCIA_DEVICE_PROD_ID12("HITACHI", "microdrive", 0xf4f43949, 0xa6d76178),
383 PCMCIA_DEVICE_PROD_ID12("IBM", "microdrive", 0xb569a6e5, 0xa6d76178), 385 PCMCIA_DEVICE_PROD_ID12("IBM", "microdrive", 0xb569a6e5, 0xa6d76178),
diff --git a/drivers/ata/pata_sil680.c b/drivers/ata/pata_sil680.c
index 2eb75cd74a96..4dc2e73298fd 100644
--- a/drivers/ata/pata_sil680.c
+++ b/drivers/ata/pata_sil680.c
@@ -279,7 +279,7 @@ static struct ata_port_operations sil680_port_ops = {
279 * Returns the final clock settings. 279 * Returns the final clock settings.
280 */ 280 */
281 281
282static u8 sil680_init_chip(struct pci_dev *pdev) 282static u8 sil680_init_chip(struct pci_dev *pdev, int *try_mmio)
283{ 283{
284 u32 class_rev = 0; 284 u32 class_rev = 0;
285 u8 tmpbyte = 0; 285 u8 tmpbyte = 0;
@@ -297,6 +297,8 @@ static u8 sil680_init_chip(struct pci_dev *pdev)
297 dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n", 297 dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
298 tmpbyte & 1, tmpbyte & 0x30); 298 tmpbyte & 1, tmpbyte & 0x30);
299 299
300 *try_mmio = (tmpbyte & 1) || pci_resource_start(pdev, 5);
301
300 switch(tmpbyte & 0x30) { 302 switch(tmpbyte & 0x30) {
301 case 0x00: 303 case 0x00:
302 /* 133 clock attempt to force it on */ 304 /* 133 clock attempt to force it on */
@@ -361,25 +363,76 @@ static int __devinit sil680_init_one(struct pci_dev *pdev,
361 }; 363 };
362 const struct ata_port_info *ppi[] = { &info, NULL }; 364 const struct ata_port_info *ppi[] = { &info, NULL };
363 static int printed_version; 365 static int printed_version;
366 struct ata_host *host;
367 void __iomem *mmio_base;
368 int rc, try_mmio;
364 369
365 if (!printed_version++) 370 if (!printed_version++)
366 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 371 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
367 372
368 switch(sil680_init_chip(pdev)) 373 switch (sil680_init_chip(pdev, &try_mmio)) {
369 {
370 case 0: 374 case 0:
371 ppi[0] = &info_slow; 375 ppi[0] = &info_slow;
372 break; 376 break;
373 case 0x30: 377 case 0x30:
374 return -ENODEV; 378 return -ENODEV;
375 } 379 }
380
381 if (!try_mmio)
382 goto use_ioports;
383
384 /* Try to acquire MMIO resources and fallback to PIO if
385 * that fails
386 */
387 rc = pcim_enable_device(pdev);
388 if (rc)
389 return rc;
390 rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME);
391 if (rc)
392 goto use_ioports;
393
394 /* Allocate host and set it up */
395 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
396 if (!host)
397 return -ENOMEM;
398 host->iomap = pcim_iomap_table(pdev);
399
400 /* Setup DMA masks */
401 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
402 if (rc)
403 return rc;
404 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
405 if (rc)
406 return rc;
407 pci_set_master(pdev);
408
409 /* Get MMIO base and initialize port addresses */
410 mmio_base = host->iomap[SIL680_MMIO_BAR];
411 host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00;
412 host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80;
413 host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a;
414 host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a;
415 ata_std_ports(&host->ports[0]->ioaddr);
416 host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08;
417 host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0;
418 host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca;
419 host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca;
420 ata_std_ports(&host->ports[1]->ioaddr);
421
422 /* Register & activate */
423 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
424 &sil680_sht);
425
426use_ioports:
376 return ata_pci_init_one(pdev, ppi); 427 return ata_pci_init_one(pdev, ppi);
377} 428}
378 429
379#ifdef CONFIG_PM 430#ifdef CONFIG_PM
380static int sil680_reinit_one(struct pci_dev *pdev) 431static int sil680_reinit_one(struct pci_dev *pdev)
381{ 432{
382 sil680_init_chip(pdev); 433 int try_mmio;
434
435 sil680_init_chip(pdev, &try_mmio);
383 return ata_pci_device_resume(pdev); 436 return ata_pci_device_resume(pdev);
384} 437}
385#endif 438#endif
diff --git a/drivers/ata/sata_nv.c b/drivers/ata/sata_nv.c
index 40557fe2ffdf..240a8920d0bd 100644
--- a/drivers/ata/sata_nv.c
+++ b/drivers/ata/sata_nv.c
@@ -169,6 +169,35 @@ enum {
169 NV_ADMA_PORT_REGISTER_MODE = (1 << 0), 169 NV_ADMA_PORT_REGISTER_MODE = (1 << 0),
170 NV_ADMA_ATAPI_SETUP_COMPLETE = (1 << 1), 170 NV_ADMA_ATAPI_SETUP_COMPLETE = (1 << 1),
171 171
172 /* MCP55 reg offset */
173 NV_CTL_MCP55 = 0x400,
174 NV_INT_STATUS_MCP55 = 0x440,
175 NV_INT_ENABLE_MCP55 = 0x444,
176 NV_NCQ_REG_MCP55 = 0x448,
177
178 /* MCP55 */
179 NV_INT_ALL_MCP55 = 0xffff,
180 NV_INT_PORT_SHIFT_MCP55 = 16, /* each port occupies 16 bits */
181 NV_INT_MASK_MCP55 = NV_INT_ALL_MCP55 & 0xfffd,
182
183 /* SWNCQ ENABLE BITS*/
184 NV_CTL_PRI_SWNCQ = 0x02,
185 NV_CTL_SEC_SWNCQ = 0x04,
186
187 /* SW NCQ status bits*/
188 NV_SWNCQ_IRQ_DEV = (1 << 0),
189 NV_SWNCQ_IRQ_PM = (1 << 1),
190 NV_SWNCQ_IRQ_ADDED = (1 << 2),
191 NV_SWNCQ_IRQ_REMOVED = (1 << 3),
192
193 NV_SWNCQ_IRQ_BACKOUT = (1 << 4),
194 NV_SWNCQ_IRQ_SDBFIS = (1 << 5),
195 NV_SWNCQ_IRQ_DHREGFIS = (1 << 6),
196 NV_SWNCQ_IRQ_DMASETUP = (1 << 7),
197
198 NV_SWNCQ_IRQ_HOTPLUG = NV_SWNCQ_IRQ_ADDED |
199 NV_SWNCQ_IRQ_REMOVED,
200
172}; 201};
173 202
174/* ADMA Physical Region Descriptor - one SG segment */ 203/* ADMA Physical Region Descriptor - one SG segment */
@@ -226,6 +255,42 @@ struct nv_host_priv {
226 unsigned long type; 255 unsigned long type;
227}; 256};
228 257
258struct defer_queue {
259 u32 defer_bits;
260 unsigned int head;
261 unsigned int tail;
262 unsigned int tag[ATA_MAX_QUEUE];
263};
264
265enum ncq_saw_flag_list {
266 ncq_saw_d2h = (1U << 0),
267 ncq_saw_dmas = (1U << 1),
268 ncq_saw_sdb = (1U << 2),
269 ncq_saw_backout = (1U << 3),
270};
271
272struct nv_swncq_port_priv {
273 struct ata_prd *prd; /* our SG list */
274 dma_addr_t prd_dma; /* and its DMA mapping */
275 void __iomem *sactive_block;
276 void __iomem *irq_block;
277 void __iomem *tag_block;
278 u32 qc_active;
279
280 unsigned int last_issue_tag;
281
282 /* fifo circular queue to store deferral command */
283 struct defer_queue defer_queue;
284
285 /* for NCQ interrupt analysis */
286 u32 dhfis_bits;
287 u32 dmafis_bits;
288 u32 sdbfis_bits;
289
290 unsigned int ncq_flags;
291};
292
293
229#define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & ( 1 << (19 + (12 * (PORT))))) 294#define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & ( 1 << (19 + (12 * (PORT)))))
230 295
231static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 296static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
@@ -263,13 +328,29 @@ static void nv_adma_host_stop(struct ata_host *host);
263static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc); 328static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc);
264static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf); 329static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
265 330
331static void nv_mcp55_thaw(struct ata_port *ap);
332static void nv_mcp55_freeze(struct ata_port *ap);
333static void nv_swncq_error_handler(struct ata_port *ap);
334static int nv_swncq_slave_config(struct scsi_device *sdev);
335static int nv_swncq_port_start(struct ata_port *ap);
336static void nv_swncq_qc_prep(struct ata_queued_cmd *qc);
337static void nv_swncq_fill_sg(struct ata_queued_cmd *qc);
338static unsigned int nv_swncq_qc_issue(struct ata_queued_cmd *qc);
339static void nv_swncq_irq_clear(struct ata_port *ap, u16 fis);
340static irqreturn_t nv_swncq_interrupt(int irq, void *dev_instance);
341#ifdef CONFIG_PM
342static int nv_swncq_port_suspend(struct ata_port *ap, pm_message_t mesg);
343static int nv_swncq_port_resume(struct ata_port *ap);
344#endif
345
266enum nv_host_type 346enum nv_host_type
267{ 347{
268 GENERIC, 348 GENERIC,
269 NFORCE2, 349 NFORCE2,
270 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */ 350 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
271 CK804, 351 CK804,
272 ADMA 352 ADMA,
353 SWNCQ,
273}; 354};
274 355
275static const struct pci_device_id nv_pci_tbl[] = { 356static const struct pci_device_id nv_pci_tbl[] = {
@@ -280,13 +361,13 @@ static const struct pci_device_id nv_pci_tbl[] = {
280 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 }, 361 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 },
281 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 }, 362 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 },
282 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 }, 363 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 },
283 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), GENERIC }, 364 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), SWNCQ },
284 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), GENERIC }, 365 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), SWNCQ },
285 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), GENERIC }, 366 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), SWNCQ },
286 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), GENERIC }, 367 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), SWNCQ },
287 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC }, 368 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), SWNCQ },
288 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC }, 369 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), SWNCQ },
289 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC }, 370 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), SWNCQ },
290 371
291 { } /* terminate list */ 372 { } /* terminate list */
292}; 373};
@@ -339,6 +420,25 @@ static struct scsi_host_template nv_adma_sht = {
339 .bios_param = ata_std_bios_param, 420 .bios_param = ata_std_bios_param,
340}; 421};
341 422
423static struct scsi_host_template nv_swncq_sht = {
424 .module = THIS_MODULE,
425 .name = DRV_NAME,
426 .ioctl = ata_scsi_ioctl,
427 .queuecommand = ata_scsi_queuecmd,
428 .change_queue_depth = ata_scsi_change_queue_depth,
429 .can_queue = ATA_MAX_QUEUE,
430 .this_id = ATA_SHT_THIS_ID,
431 .sg_tablesize = LIBATA_MAX_PRD,
432 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
433 .emulated = ATA_SHT_EMULATED,
434 .use_clustering = ATA_SHT_USE_CLUSTERING,
435 .proc_name = DRV_NAME,
436 .dma_boundary = ATA_DMA_BOUNDARY,
437 .slave_configure = nv_swncq_slave_config,
438 .slave_destroy = ata_scsi_slave_destroy,
439 .bios_param = ata_std_bios_param,
440};
441
342static const struct ata_port_operations nv_generic_ops = { 442static const struct ata_port_operations nv_generic_ops = {
343 .tf_load = ata_tf_load, 443 .tf_load = ata_tf_load,
344 .tf_read = ata_tf_read, 444 .tf_read = ata_tf_read,
@@ -444,6 +544,35 @@ static const struct ata_port_operations nv_adma_ops = {
444 .host_stop = nv_adma_host_stop, 544 .host_stop = nv_adma_host_stop,
445}; 545};
446 546
547static const struct ata_port_operations nv_swncq_ops = {
548 .tf_load = ata_tf_load,
549 .tf_read = ata_tf_read,
550 .exec_command = ata_exec_command,
551 .check_status = ata_check_status,
552 .dev_select = ata_std_dev_select,
553 .bmdma_setup = ata_bmdma_setup,
554 .bmdma_start = ata_bmdma_start,
555 .bmdma_stop = ata_bmdma_stop,
556 .bmdma_status = ata_bmdma_status,
557 .qc_defer = ata_std_qc_defer,
558 .qc_prep = nv_swncq_qc_prep,
559 .qc_issue = nv_swncq_qc_issue,
560 .freeze = nv_mcp55_freeze,
561 .thaw = nv_mcp55_thaw,
562 .error_handler = nv_swncq_error_handler,
563 .post_internal_cmd = ata_bmdma_post_internal_cmd,
564 .data_xfer = ata_data_xfer,
565 .irq_clear = ata_bmdma_irq_clear,
566 .irq_on = ata_irq_on,
567 .scr_read = nv_scr_read,
568 .scr_write = nv_scr_write,
569#ifdef CONFIG_PM
570 .port_suspend = nv_swncq_port_suspend,
571 .port_resume = nv_swncq_port_resume,
572#endif
573 .port_start = nv_swncq_port_start,
574};
575
447static const struct ata_port_info nv_port_info[] = { 576static const struct ata_port_info nv_port_info[] = {
448 /* generic */ 577 /* generic */
449 { 578 {
@@ -490,6 +619,18 @@ static const struct ata_port_info nv_port_info[] = {
490 .port_ops = &nv_adma_ops, 619 .port_ops = &nv_adma_ops,
491 .irq_handler = nv_adma_interrupt, 620 .irq_handler = nv_adma_interrupt,
492 }, 621 },
622 /* SWNCQ */
623 {
624 .sht = &nv_swncq_sht,
625 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
626 ATA_FLAG_NCQ,
627 .link_flags = ATA_LFLAG_HRST_TO_RESUME,
628 .pio_mask = NV_PIO_MASK,
629 .mwdma_mask = NV_MWDMA_MASK,
630 .udma_mask = NV_UDMA_MASK,
631 .port_ops = &nv_swncq_ops,
632 .irq_handler = nv_swncq_interrupt,
633 },
493}; 634};
494 635
495MODULE_AUTHOR("NVIDIA"); 636MODULE_AUTHOR("NVIDIA");
@@ -499,6 +640,7 @@ MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
499MODULE_VERSION(DRV_VERSION); 640MODULE_VERSION(DRV_VERSION);
500 641
501static int adma_enabled = 1; 642static int adma_enabled = 1;
643static int swncq_enabled;
502 644
503static void nv_adma_register_mode(struct ata_port *ap) 645static void nv_adma_register_mode(struct ata_port *ap)
504{ 646{
@@ -1452,6 +1594,34 @@ static void nv_ck804_thaw(struct ata_port *ap)
1452 writeb(mask, mmio_base + NV_INT_ENABLE_CK804); 1594 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
1453} 1595}
1454 1596
1597static void nv_mcp55_freeze(struct ata_port *ap)
1598{
1599 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
1600 int shift = ap->port_no * NV_INT_PORT_SHIFT_MCP55;
1601 u32 mask;
1602
1603 writel(NV_INT_ALL_MCP55 << shift, mmio_base + NV_INT_STATUS_MCP55);
1604
1605 mask = readl(mmio_base + NV_INT_ENABLE_MCP55);
1606 mask &= ~(NV_INT_ALL_MCP55 << shift);
1607 writel(mask, mmio_base + NV_INT_ENABLE_MCP55);
1608 ata_bmdma_freeze(ap);
1609}
1610
1611static void nv_mcp55_thaw(struct ata_port *ap)
1612{
1613 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
1614 int shift = ap->port_no * NV_INT_PORT_SHIFT_MCP55;
1615 u32 mask;
1616
1617 writel(NV_INT_ALL_MCP55 << shift, mmio_base + NV_INT_STATUS_MCP55);
1618
1619 mask = readl(mmio_base + NV_INT_ENABLE_MCP55);
1620 mask |= (NV_INT_MASK_MCP55 << shift);
1621 writel(mask, mmio_base + NV_INT_ENABLE_MCP55);
1622 ata_bmdma_thaw(ap);
1623}
1624
1455static int nv_hardreset(struct ata_link *link, unsigned int *class, 1625static int nv_hardreset(struct ata_link *link, unsigned int *class,
1456 unsigned long deadline) 1626 unsigned long deadline)
1457{ 1627{
@@ -1525,6 +1695,663 @@ static void nv_adma_error_handler(struct ata_port *ap)
1525 nv_hardreset, ata_std_postreset); 1695 nv_hardreset, ata_std_postreset);
1526} 1696}
1527 1697
1698static void nv_swncq_qc_to_dq(struct ata_port *ap, struct ata_queued_cmd *qc)
1699{
1700 struct nv_swncq_port_priv *pp = ap->private_data;
1701 struct defer_queue *dq = &pp->defer_queue;
1702
1703 /* queue is full */
1704 WARN_ON(dq->tail - dq->head == ATA_MAX_QUEUE);
1705 dq->defer_bits |= (1 << qc->tag);
1706 dq->tag[dq->tail++ & (ATA_MAX_QUEUE - 1)] = qc->tag;
1707}
1708
1709static struct ata_queued_cmd *nv_swncq_qc_from_dq(struct ata_port *ap)
1710{
1711 struct nv_swncq_port_priv *pp = ap->private_data;
1712 struct defer_queue *dq = &pp->defer_queue;
1713 unsigned int tag;
1714
1715 if (dq->head == dq->tail) /* null queue */
1716 return NULL;
1717
1718 tag = dq->tag[dq->head & (ATA_MAX_QUEUE - 1)];
1719 dq->tag[dq->head++ & (ATA_MAX_QUEUE - 1)] = ATA_TAG_POISON;
1720 WARN_ON(!(dq->defer_bits & (1 << tag)));
1721 dq->defer_bits &= ~(1 << tag);
1722
1723 return ata_qc_from_tag(ap, tag);
1724}
1725
1726static void nv_swncq_fis_reinit(struct ata_port *ap)
1727{
1728 struct nv_swncq_port_priv *pp = ap->private_data;
1729
1730 pp->dhfis_bits = 0;
1731 pp->dmafis_bits = 0;
1732 pp->sdbfis_bits = 0;
1733 pp->ncq_flags = 0;
1734}
1735
1736static void nv_swncq_pp_reinit(struct ata_port *ap)
1737{
1738 struct nv_swncq_port_priv *pp = ap->private_data;
1739 struct defer_queue *dq = &pp->defer_queue;
1740
1741 dq->head = 0;
1742 dq->tail = 0;
1743 dq->defer_bits = 0;
1744 pp->qc_active = 0;
1745 pp->last_issue_tag = ATA_TAG_POISON;
1746 nv_swncq_fis_reinit(ap);
1747}
1748
1749static void nv_swncq_irq_clear(struct ata_port *ap, u16 fis)
1750{
1751 struct nv_swncq_port_priv *pp = ap->private_data;
1752
1753 writew(fis, pp->irq_block);
1754}
1755
1756static void __ata_bmdma_stop(struct ata_port *ap)
1757{
1758 struct ata_queued_cmd qc;
1759
1760 qc.ap = ap;
1761 ata_bmdma_stop(&qc);
1762}
1763
1764static void nv_swncq_ncq_stop(struct ata_port *ap)
1765{
1766 struct nv_swncq_port_priv *pp = ap->private_data;
1767 unsigned int i;
1768 u32 sactive;
1769 u32 done_mask;
1770
1771 ata_port_printk(ap, KERN_ERR,
1772 "EH in SWNCQ mode,QC:qc_active 0x%X sactive 0x%X\n",
1773 ap->qc_active, ap->link.sactive);
1774 ata_port_printk(ap, KERN_ERR,
1775 "SWNCQ:qc_active 0x%X defer_bits 0x%X last_issue_tag 0x%x\n "
1776 "dhfis 0x%X dmafis 0x%X sdbfis 0x%X\n",
1777 pp->qc_active, pp->defer_queue.defer_bits, pp->last_issue_tag,
1778 pp->dhfis_bits, pp->dmafis_bits, pp->sdbfis_bits);
1779
1780 ata_port_printk(ap, KERN_ERR, "ATA_REG 0x%X ERR_REG 0x%X\n",
1781 ap->ops->check_status(ap),
1782 ioread8(ap->ioaddr.error_addr));
1783
1784 sactive = readl(pp->sactive_block);
1785 done_mask = pp->qc_active ^ sactive;
1786
1787 ata_port_printk(ap, KERN_ERR, "tag : dhfis dmafis sdbfis sacitve\n");
1788 for (i = 0; i < ATA_MAX_QUEUE; i++) {
1789 u8 err = 0;
1790 if (pp->qc_active & (1 << i))
1791 err = 0;
1792 else if (done_mask & (1 << i))
1793 err = 1;
1794 else
1795 continue;
1796
1797 ata_port_printk(ap, KERN_ERR,
1798 "tag 0x%x: %01x %01x %01x %01x %s\n", i,
1799 (pp->dhfis_bits >> i) & 0x1,
1800 (pp->dmafis_bits >> i) & 0x1,
1801 (pp->sdbfis_bits >> i) & 0x1,
1802 (sactive >> i) & 0x1,
1803 (err ? "error! tag doesn't exit" : " "));
1804 }
1805
1806 nv_swncq_pp_reinit(ap);
1807 ap->ops->irq_clear(ap);
1808 __ata_bmdma_stop(ap);
1809 nv_swncq_irq_clear(ap, 0xffff);
1810}
1811
1812static void nv_swncq_error_handler(struct ata_port *ap)
1813{
1814 struct ata_eh_context *ehc = &ap->link.eh_context;
1815
1816 if (ap->link.sactive) {
1817 nv_swncq_ncq_stop(ap);
1818 ehc->i.action |= ATA_EH_HARDRESET;
1819 }
1820
1821 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
1822 nv_hardreset, ata_std_postreset);
1823}
1824
1825#ifdef CONFIG_PM
1826static int nv_swncq_port_suspend(struct ata_port *ap, pm_message_t mesg)
1827{
1828 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
1829 u32 tmp;
1830
1831 /* clear irq */
1832 writel(~0, mmio + NV_INT_STATUS_MCP55);
1833
1834 /* disable irq */
1835 writel(0, mmio + NV_INT_ENABLE_MCP55);
1836
1837 /* disable swncq */
1838 tmp = readl(mmio + NV_CTL_MCP55);
1839 tmp &= ~(NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ);
1840 writel(tmp, mmio + NV_CTL_MCP55);
1841
1842 return 0;
1843}
1844
1845static int nv_swncq_port_resume(struct ata_port *ap)
1846{
1847 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
1848 u32 tmp;
1849
1850 /* clear irq */
1851 writel(~0, mmio + NV_INT_STATUS_MCP55);
1852
1853 /* enable irq */
1854 writel(0x00fd00fd, mmio + NV_INT_ENABLE_MCP55);
1855
1856 /* enable swncq */
1857 tmp = readl(mmio + NV_CTL_MCP55);
1858 writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55);
1859
1860 return 0;
1861}
1862#endif
1863
1864static void nv_swncq_host_init(struct ata_host *host)
1865{
1866 u32 tmp;
1867 void __iomem *mmio = host->iomap[NV_MMIO_BAR];
1868 struct pci_dev *pdev = to_pci_dev(host->dev);
1869 u8 regval;
1870
1871 /* disable ECO 398 */
1872 pci_read_config_byte(pdev, 0x7f, &regval);
1873 regval &= ~(1 << 7);
1874 pci_write_config_byte(pdev, 0x7f, regval);
1875
1876 /* enable swncq */
1877 tmp = readl(mmio + NV_CTL_MCP55);
1878 VPRINTK("HOST_CTL:0x%X\n", tmp);
1879 writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55);
1880
1881 /* enable irq intr */
1882 tmp = readl(mmio + NV_INT_ENABLE_MCP55);
1883 VPRINTK("HOST_ENABLE:0x%X\n", tmp);
1884 writel(tmp | 0x00fd00fd, mmio + NV_INT_ENABLE_MCP55);
1885
1886 /* clear port irq */
1887 writel(~0x0, mmio + NV_INT_STATUS_MCP55);
1888}
1889
1890static int nv_swncq_slave_config(struct scsi_device *sdev)
1891{
1892 struct ata_port *ap = ata_shost_to_port(sdev->host);
1893 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1894 struct ata_device *dev;
1895 int rc;
1896 u8 rev;
1897 u8 check_maxtor = 0;
1898 unsigned char model_num[ATA_ID_PROD_LEN + 1];
1899
1900 rc = ata_scsi_slave_config(sdev);
1901 if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun)
1902 /* Not a proper libata device, ignore */
1903 return rc;
1904
1905 dev = &ap->link.device[sdev->id];
1906 if (!(ap->flags & ATA_FLAG_NCQ) || dev->class == ATA_DEV_ATAPI)
1907 return rc;
1908
1909 /* if MCP51 and Maxtor, then disable ncq */
1910 if (pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA ||
1911 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2)
1912 check_maxtor = 1;
1913
1914 /* if MCP55 and rev <= a2 and Maxtor, then disable ncq */
1915 if (pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA ||
1916 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2) {
1917 pci_read_config_byte(pdev, 0x8, &rev);
1918 if (rev <= 0xa2)
1919 check_maxtor = 1;
1920 }
1921
1922 if (!check_maxtor)
1923 return rc;
1924
1925 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
1926
1927 if (strncmp(model_num, "Maxtor", 6) == 0) {
1928 ata_scsi_change_queue_depth(sdev, 1);
1929 ata_dev_printk(dev, KERN_NOTICE,
1930 "Disabling SWNCQ mode (depth %x)\n", sdev->queue_depth);
1931 }
1932
1933 return rc;
1934}
1935
1936static int nv_swncq_port_start(struct ata_port *ap)
1937{
1938 struct device *dev = ap->host->dev;
1939 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
1940 struct nv_swncq_port_priv *pp;
1941 int rc;
1942
1943 rc = ata_port_start(ap);
1944 if (rc)
1945 return rc;
1946
1947 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1948 if (!pp)
1949 return -ENOMEM;
1950
1951 pp->prd = dmam_alloc_coherent(dev, ATA_PRD_TBL_SZ * ATA_MAX_QUEUE,
1952 &pp->prd_dma, GFP_KERNEL);
1953 if (!pp->prd)
1954 return -ENOMEM;
1955 memset(pp->prd, 0, ATA_PRD_TBL_SZ * ATA_MAX_QUEUE);
1956
1957 ap->private_data = pp;
1958 pp->sactive_block = ap->ioaddr.scr_addr + 4 * SCR_ACTIVE;
1959 pp->irq_block = mmio + NV_INT_STATUS_MCP55 + ap->port_no * 2;
1960 pp->tag_block = mmio + NV_NCQ_REG_MCP55 + ap->port_no * 2;
1961
1962 return 0;
1963}
1964
1965static void nv_swncq_qc_prep(struct ata_queued_cmd *qc)
1966{
1967 if (qc->tf.protocol != ATA_PROT_NCQ) {
1968 ata_qc_prep(qc);
1969 return;
1970 }
1971
1972 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1973 return;
1974
1975 nv_swncq_fill_sg(qc);
1976}
1977
1978static void nv_swncq_fill_sg(struct ata_queued_cmd *qc)
1979{
1980 struct ata_port *ap = qc->ap;
1981 struct scatterlist *sg;
1982 unsigned int idx;
1983 struct nv_swncq_port_priv *pp = ap->private_data;
1984 struct ata_prd *prd;
1985
1986 WARN_ON(qc->__sg == NULL);
1987 WARN_ON(qc->n_elem == 0 && qc->pad_len == 0);
1988
1989 prd = pp->prd + ATA_MAX_PRD * qc->tag;
1990
1991 idx = 0;
1992 ata_for_each_sg(sg, qc) {
1993 u32 addr, offset;
1994 u32 sg_len, len;
1995
1996 addr = (u32)sg_dma_address(sg);
1997 sg_len = sg_dma_len(sg);
1998
1999 while (sg_len) {
2000 offset = addr & 0xffff;
2001 len = sg_len;
2002 if ((offset + sg_len) > 0x10000)
2003 len = 0x10000 - offset;
2004
2005 prd[idx].addr = cpu_to_le32(addr);
2006 prd[idx].flags_len = cpu_to_le32(len & 0xffff);
2007
2008 idx++;
2009 sg_len -= len;
2010 addr += len;
2011 }
2012 }
2013
2014 if (idx)
2015 prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2016}
2017
2018static unsigned int nv_swncq_issue_atacmd(struct ata_port *ap,
2019 struct ata_queued_cmd *qc)
2020{
2021 struct nv_swncq_port_priv *pp = ap->private_data;
2022
2023 if (qc == NULL)
2024 return 0;
2025
2026 DPRINTK("Enter\n");
2027
2028 writel((1 << qc->tag), pp->sactive_block);
2029 pp->last_issue_tag = qc->tag;
2030 pp->dhfis_bits &= ~(1 << qc->tag);
2031 pp->dmafis_bits &= ~(1 << qc->tag);
2032 pp->qc_active |= (0x1 << qc->tag);
2033
2034 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
2035 ap->ops->exec_command(ap, &qc->tf);
2036
2037 DPRINTK("Issued tag %u\n", qc->tag);
2038
2039 return 0;
2040}
2041
2042static unsigned int nv_swncq_qc_issue(struct ata_queued_cmd *qc)
2043{
2044 struct ata_port *ap = qc->ap;
2045 struct nv_swncq_port_priv *pp = ap->private_data;
2046
2047 if (qc->tf.protocol != ATA_PROT_NCQ)
2048 return ata_qc_issue_prot(qc);
2049
2050 DPRINTK("Enter\n");
2051
2052 if (!pp->qc_active)
2053 nv_swncq_issue_atacmd(ap, qc);
2054 else
2055 nv_swncq_qc_to_dq(ap, qc); /* add qc to defer queue */
2056
2057 return 0;
2058}
2059
2060static void nv_swncq_hotplug(struct ata_port *ap, u32 fis)
2061{
2062 u32 serror;
2063 struct ata_eh_info *ehi = &ap->link.eh_info;
2064
2065 ata_ehi_clear_desc(ehi);
2066
2067 /* AHCI needs SError cleared; otherwise, it might lock up */
2068 sata_scr_read(&ap->link, SCR_ERROR, &serror);
2069 sata_scr_write(&ap->link, SCR_ERROR, serror);
2070
2071 /* analyze @irq_stat */
2072 if (fis & NV_SWNCQ_IRQ_ADDED)
2073 ata_ehi_push_desc(ehi, "hot plug");
2074 else if (fis & NV_SWNCQ_IRQ_REMOVED)
2075 ata_ehi_push_desc(ehi, "hot unplug");
2076
2077 ata_ehi_hotplugged(ehi);
2078
2079 /* okay, let's hand over to EH */
2080 ehi->serror |= serror;
2081
2082 ata_port_freeze(ap);
2083}
2084
2085static int nv_swncq_sdbfis(struct ata_port *ap)
2086{
2087 struct ata_queued_cmd *qc;
2088 struct nv_swncq_port_priv *pp = ap->private_data;
2089 struct ata_eh_info *ehi = &ap->link.eh_info;
2090 u32 sactive;
2091 int nr_done = 0;
2092 u32 done_mask;
2093 int i;
2094 u8 host_stat;
2095 u8 lack_dhfis = 0;
2096
2097 host_stat = ap->ops->bmdma_status(ap);
2098 if (unlikely(host_stat & ATA_DMA_ERR)) {
2099 /* error when transfering data to/from memory */
2100 ata_ehi_clear_desc(ehi);
2101 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
2102 ehi->err_mask |= AC_ERR_HOST_BUS;
2103 ehi->action |= ATA_EH_SOFTRESET;
2104 return -EINVAL;
2105 }
2106
2107 ap->ops->irq_clear(ap);
2108 __ata_bmdma_stop(ap);
2109
2110 sactive = readl(pp->sactive_block);
2111 done_mask = pp->qc_active ^ sactive;
2112
2113 if (unlikely(done_mask & sactive)) {
2114 ata_ehi_clear_desc(ehi);
2115 ata_ehi_push_desc(ehi, "illegal SWNCQ:qc_active transition"
2116 "(%08x->%08x)", pp->qc_active, sactive);
2117 ehi->err_mask |= AC_ERR_HSM;
2118 ehi->action |= ATA_EH_HARDRESET;
2119 return -EINVAL;
2120 }
2121 for (i = 0; i < ATA_MAX_QUEUE; i++) {
2122 if (!(done_mask & (1 << i)))
2123 continue;
2124
2125 qc = ata_qc_from_tag(ap, i);
2126 if (qc) {
2127 ata_qc_complete(qc);
2128 pp->qc_active &= ~(1 << i);
2129 pp->dhfis_bits &= ~(1 << i);
2130 pp->dmafis_bits &= ~(1 << i);
2131 pp->sdbfis_bits |= (1 << i);
2132 nr_done++;
2133 }
2134 }
2135
2136 if (!ap->qc_active) {
2137 DPRINTK("over\n");
2138 nv_swncq_pp_reinit(ap);
2139 return nr_done;
2140 }
2141
2142 if (pp->qc_active & pp->dhfis_bits)
2143 return nr_done;
2144
2145 if ((pp->ncq_flags & ncq_saw_backout) ||
2146 (pp->qc_active ^ pp->dhfis_bits))
2147 /* if the controller cann't get a device to host register FIS,
2148 * The driver needs to reissue the new command.
2149 */
2150 lack_dhfis = 1;
2151
2152 DPRINTK("id 0x%x QC: qc_active 0x%x,"
2153 "SWNCQ:qc_active 0x%X defer_bits %X "
2154 "dhfis 0x%X dmafis 0x%X last_issue_tag %x\n",
2155 ap->print_id, ap->qc_active, pp->qc_active,
2156 pp->defer_queue.defer_bits, pp->dhfis_bits,
2157 pp->dmafis_bits, pp->last_issue_tag);
2158
2159 nv_swncq_fis_reinit(ap);
2160
2161 if (lack_dhfis) {
2162 qc = ata_qc_from_tag(ap, pp->last_issue_tag);
2163 nv_swncq_issue_atacmd(ap, qc);
2164 return nr_done;
2165 }
2166
2167 if (pp->defer_queue.defer_bits) {
2168 /* send deferral queue command */
2169 qc = nv_swncq_qc_from_dq(ap);
2170 WARN_ON(qc == NULL);
2171 nv_swncq_issue_atacmd(ap, qc);
2172 }
2173
2174 return nr_done;
2175}
2176
2177static inline u32 nv_swncq_tag(struct ata_port *ap)
2178{
2179 struct nv_swncq_port_priv *pp = ap->private_data;
2180 u32 tag;
2181
2182 tag = readb(pp->tag_block) >> 2;
2183 return (tag & 0x1f);
2184}
2185
2186static int nv_swncq_dmafis(struct ata_port *ap)
2187{
2188 struct ata_queued_cmd *qc;
2189 unsigned int rw;
2190 u8 dmactl;
2191 u32 tag;
2192 struct nv_swncq_port_priv *pp = ap->private_data;
2193
2194 __ata_bmdma_stop(ap);
2195 tag = nv_swncq_tag(ap);
2196
2197 DPRINTK("dma setup tag 0x%x\n", tag);
2198 qc = ata_qc_from_tag(ap, tag);
2199
2200 if (unlikely(!qc))
2201 return 0;
2202
2203 rw = qc->tf.flags & ATA_TFLAG_WRITE;
2204
2205 /* load PRD table addr. */
2206 iowrite32(pp->prd_dma + ATA_PRD_TBL_SZ * qc->tag,
2207 ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2208
2209 /* specify data direction, triple-check start bit is clear */
2210 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2211 dmactl &= ~ATA_DMA_WR;
2212 if (!rw)
2213 dmactl |= ATA_DMA_WR;
2214
2215 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2216
2217 return 1;
2218}
2219
2220static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
2221{
2222 struct nv_swncq_port_priv *pp = ap->private_data;
2223 struct ata_queued_cmd *qc;
2224 struct ata_eh_info *ehi = &ap->link.eh_info;
2225 u32 serror;
2226 u8 ata_stat;
2227 int rc = 0;
2228
2229 ata_stat = ap->ops->check_status(ap);
2230 nv_swncq_irq_clear(ap, fis);
2231 if (!fis)
2232 return;
2233
2234 if (ap->pflags & ATA_PFLAG_FROZEN)
2235 return;
2236
2237 if (fis & NV_SWNCQ_IRQ_HOTPLUG) {
2238 nv_swncq_hotplug(ap, fis);
2239 return;
2240 }
2241
2242 if (!pp->qc_active)
2243 return;
2244
2245 if (ap->ops->scr_read(ap, SCR_ERROR, &serror))
2246 return;
2247 ap->ops->scr_write(ap, SCR_ERROR, serror);
2248
2249 if (ata_stat & ATA_ERR) {
2250 ata_ehi_clear_desc(ehi);
2251 ata_ehi_push_desc(ehi, "Ata error. fis:0x%X", fis);
2252 ehi->err_mask |= AC_ERR_DEV;
2253 ehi->serror |= serror;
2254 ehi->action |= ATA_EH_SOFTRESET;
2255 ata_port_freeze(ap);
2256 return;
2257 }
2258
2259 if (fis & NV_SWNCQ_IRQ_BACKOUT) {
2260 /* If the IRQ is backout, driver must issue
2261 * the new command again some time later.
2262 */
2263 pp->ncq_flags |= ncq_saw_backout;
2264 }
2265
2266 if (fis & NV_SWNCQ_IRQ_SDBFIS) {
2267 pp->ncq_flags |= ncq_saw_sdb;
2268 DPRINTK("id 0x%x SWNCQ: qc_active 0x%X "
2269 "dhfis 0x%X dmafis 0x%X sactive 0x%X\n",
2270 ap->print_id, pp->qc_active, pp->dhfis_bits,
2271 pp->dmafis_bits, readl(pp->sactive_block));
2272 rc = nv_swncq_sdbfis(ap);
2273 if (rc < 0)
2274 goto irq_error;
2275 }
2276
2277 if (fis & NV_SWNCQ_IRQ_DHREGFIS) {
2278 /* The interrupt indicates the new command
2279 * was transmitted correctly to the drive.
2280 */
2281 pp->dhfis_bits |= (0x1 << pp->last_issue_tag);
2282 pp->ncq_flags |= ncq_saw_d2h;
2283 if (pp->ncq_flags & (ncq_saw_sdb | ncq_saw_backout)) {
2284 ata_ehi_push_desc(ehi, "illegal fis transaction");
2285 ehi->err_mask |= AC_ERR_HSM;
2286 ehi->action |= ATA_EH_HARDRESET;
2287 goto irq_error;
2288 }
2289
2290 if (!(fis & NV_SWNCQ_IRQ_DMASETUP) &&
2291 !(pp->ncq_flags & ncq_saw_dmas)) {
2292 ata_stat = ap->ops->check_status(ap);
2293 if (ata_stat & ATA_BUSY)
2294 goto irq_exit;
2295
2296 if (pp->defer_queue.defer_bits) {
2297 DPRINTK("send next command\n");
2298 qc = nv_swncq_qc_from_dq(ap);
2299 nv_swncq_issue_atacmd(ap, qc);
2300 }
2301 }
2302 }
2303
2304 if (fis & NV_SWNCQ_IRQ_DMASETUP) {
2305 /* program the dma controller with appropriate PRD buffers
2306 * and start the DMA transfer for requested command.
2307 */
2308 pp->dmafis_bits |= (0x1 << nv_swncq_tag(ap));
2309 pp->ncq_flags |= ncq_saw_dmas;
2310 rc = nv_swncq_dmafis(ap);
2311 }
2312
2313irq_exit:
2314 return;
2315irq_error:
2316 ata_ehi_push_desc(ehi, "fis:0x%x", fis);
2317 ata_port_freeze(ap);
2318 return;
2319}
2320
2321static irqreturn_t nv_swncq_interrupt(int irq, void *dev_instance)
2322{
2323 struct ata_host *host = dev_instance;
2324 unsigned int i;
2325 unsigned int handled = 0;
2326 unsigned long flags;
2327 u32 irq_stat;
2328
2329 spin_lock_irqsave(&host->lock, flags);
2330
2331 irq_stat = readl(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_MCP55);
2332
2333 for (i = 0; i < host->n_ports; i++) {
2334 struct ata_port *ap = host->ports[i];
2335
2336 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
2337 if (ap->link.sactive) {
2338 nv_swncq_host_interrupt(ap, (u16)irq_stat);
2339 handled = 1;
2340 } else {
2341 if (irq_stat) /* reserve Hotplug */
2342 nv_swncq_irq_clear(ap, 0xfff0);
2343
2344 handled += nv_host_intr(ap, (u8)irq_stat);
2345 }
2346 }
2347 irq_stat >>= NV_INT_PORT_SHIFT_MCP55;
2348 }
2349
2350 spin_unlock_irqrestore(&host->lock, flags);
2351
2352 return IRQ_RETVAL(handled);
2353}
2354
1528static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 2355static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1529{ 2356{
1530 static int printed_version = 0; 2357 static int printed_version = 0;
@@ -1551,7 +2378,7 @@ static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1551 return rc; 2378 return rc;
1552 2379
1553 /* determine type and allocate host */ 2380 /* determine type and allocate host */
1554 if (type >= CK804 && adma_enabled) { 2381 if (type == CK804 && adma_enabled) {
1555 dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n"); 2382 dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n");
1556 type = ADMA; 2383 type = ADMA;
1557 } 2384 }
@@ -1597,6 +2424,9 @@ static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1597 rc = nv_adma_host_init(host); 2424 rc = nv_adma_host_init(host);
1598 if (rc) 2425 if (rc)
1599 return rc; 2426 return rc;
2427 } else if (type == SWNCQ && swncq_enabled) {
2428 dev_printk(KERN_NOTICE, &pdev->dev, "Using SWNCQ mode\n");
2429 nv_swncq_host_init(host);
1600 } 2430 }
1601 2431
1602 pci_set_master(pdev); 2432 pci_set_master(pdev);
@@ -1696,3 +2526,6 @@ module_init(nv_init);
1696module_exit(nv_exit); 2526module_exit(nv_exit);
1697module_param_named(adma, adma_enabled, bool, 0444); 2527module_param_named(adma, adma_enabled, bool, 0444);
1698MODULE_PARM_DESC(adma, "Enable use of ADMA (Default: true)"); 2528MODULE_PARM_DESC(adma, "Enable use of ADMA (Default: true)");
2529module_param_named(swncq, swncq_enabled, bool, 0444);
2530MODULE_PARM_DESC(swncq, "Enable use of SWNCQ (Default: false)");
2531
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 09:35:13 -0500