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-rw-r--r--drivers/acpi/osl.c4
-rw-r--r--drivers/atm/lanai.c2
-rw-r--r--drivers/base/sys.c7
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c11
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c27
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h1
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c72
-rw-r--r--drivers/gpu/drm/i915/intel_display.c1
-rw-r--r--drivers/i2c/busses/i2c-acorn.c5
-rw-r--r--drivers/i2c/busses/i2c-amd8111.c4
-rw-r--r--drivers/i2c/busses/i2c-ixp2000.c2
-rw-r--r--drivers/i2c/busses/i2c-pxa.c2
-rw-r--r--drivers/i2c/busses/scx200_i2c.c2
-rw-r--r--drivers/i2c/i2c-core.c3
-rw-r--r--drivers/i2c/i2c-dev.c6
-rw-r--r--drivers/ieee1394/dma.h1
-rw-r--r--drivers/ieee1394/ieee1394_core.c1
-rw-r--r--drivers/ieee1394/ieee1394_transactions.c31
-rw-r--r--drivers/ieee1394/ieee1394_transactions.h2
-rw-r--r--drivers/ieee1394/iso.h1
-rw-r--r--drivers/ieee1394/nodemgr.c10
-rw-r--r--drivers/ieee1394/nodemgr.h18
-rw-r--r--drivers/isdn/sc/shmem.c2
-rw-r--r--drivers/media/dvb/Kconfig4
-rw-r--r--drivers/media/dvb/Makefile2
-rw-r--r--drivers/media/dvb/firewire/Kconfig22
-rw-r--r--drivers/media/dvb/firewire/Makefile8
-rw-r--r--drivers/media/dvb/firewire/firedtv-1394.c285
-rw-r--r--drivers/media/dvb/firewire/firedtv-avc.c1315
-rw-r--r--drivers/media/dvb/firewire/firedtv-ci.c260
-rw-r--r--drivers/media/dvb/firewire/firedtv-dvb.c364
-rw-r--r--drivers/media/dvb/firewire/firedtv-fe.c247
-rw-r--r--drivers/media/dvb/firewire/firedtv-rc.c190
-rw-r--r--drivers/media/dvb/firewire/firedtv.h182
-rw-r--r--drivers/net/Kconfig11
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/atl1c/Makefile2
-rw-r--r--drivers/net/atl1c/atl1c.h606
-rw-r--r--drivers/net/atl1c/atl1c_ethtool.c317
-rw-r--r--drivers/net/atl1c/atl1c_hw.c527
-rw-r--r--drivers/net/atl1c/atl1c_hw.h859
-rw-r--r--drivers/net/atl1c/atl1c_main.c2797
-rw-r--r--drivers/net/cxgb3/cxgb3_main.c1
-rw-r--r--drivers/net/cxgb3/t3_hw.c7
-rw-r--r--drivers/net/forcedeth.c13
-rw-r--r--drivers/net/mv643xx_eth.c9
-rw-r--r--drivers/net/smsc911x.c2
-rw-r--r--drivers/net/smsc9420.c6
-rw-r--r--drivers/net/smsc9420.h1
-rw-r--r--drivers/net/sundance.c2
-rw-r--r--drivers/net/sungem.c2
-rw-r--r--drivers/net/sunlance.c4
-rw-r--r--drivers/net/tg3.c4
-rw-r--r--drivers/net/veth.c9
-rw-r--r--drivers/net/wimax/i2400m/i2400m.h2
55 files changed, 8203 insertions, 73 deletions
diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c
index d1dd5160daa9..2b6c59028254 100644
--- a/drivers/acpi/osl.c
+++ b/drivers/acpi/osl.c
@@ -272,7 +272,7 @@ acpi_os_map_memory(acpi_physical_address phys, acpi_size size)
272} 272}
273EXPORT_SYMBOL_GPL(acpi_os_map_memory); 273EXPORT_SYMBOL_GPL(acpi_os_map_memory);
274 274
275void acpi_os_unmap_memory(void __iomem * virt, acpi_size size) 275void __ref acpi_os_unmap_memory(void __iomem *virt, acpi_size size)
276{ 276{
277 if (acpi_gbl_permanent_mmap) 277 if (acpi_gbl_permanent_mmap)
278 iounmap(virt); 278 iounmap(virt);
@@ -281,7 +281,7 @@ void acpi_os_unmap_memory(void __iomem * virt, acpi_size size)
281} 281}
282EXPORT_SYMBOL_GPL(acpi_os_unmap_memory); 282EXPORT_SYMBOL_GPL(acpi_os_unmap_memory);
283 283
284void early_acpi_os_unmap_memory(void __iomem * virt, acpi_size size) 284void __init early_acpi_os_unmap_memory(void __iomem *virt, acpi_size size)
285{ 285{
286 if (!acpi_gbl_permanent_mmap) 286 if (!acpi_gbl_permanent_mmap)
287 __acpi_unmap_table(virt, size); 287 __acpi_unmap_table(virt, size);
diff --git a/drivers/atm/lanai.c b/drivers/atm/lanai.c
index 144a49f15220..8733a2ea04c2 100644
--- a/drivers/atm/lanai.c
+++ b/drivers/atm/lanai.c
@@ -901,7 +901,7 @@ static int __devinit eeprom_read(struct lanai_dev *lanai)
901 clock_l(); udelay(5); 901 clock_l(); udelay(5);
902 for (i = 128; i != 0; i >>= 1) { /* write command out */ 902 for (i = 128; i != 0; i >>= 1) { /* write command out */
903 tmp = (lanai->conf1 & ~CONFIG1_PROMDATA) | 903 tmp = (lanai->conf1 & ~CONFIG1_PROMDATA) |
904 (data & i) ? CONFIG1_PROMDATA : 0; 904 ((data & i) ? CONFIG1_PROMDATA : 0);
905 if (lanai->conf1 != tmp) { 905 if (lanai->conf1 != tmp) {
906 set_config1(tmp); 906 set_config1(tmp);
907 udelay(5); /* Let new data settle */ 907 udelay(5); /* Let new data settle */
diff --git a/drivers/base/sys.c b/drivers/base/sys.c
index c98c31ec2f75..b428c8c4bc64 100644
--- a/drivers/base/sys.c
+++ b/drivers/base/sys.c
@@ -303,7 +303,6 @@ void sysdev_unregister(struct sys_device * sysdev)
303 * is guaranteed by virtue of the fact that child devices are registered 303 * is guaranteed by virtue of the fact that child devices are registered
304 * after their parents. 304 * after their parents.
305 */ 305 */
306
307void sysdev_shutdown(void) 306void sysdev_shutdown(void)
308{ 307{
309 struct sysdev_class * cls; 308 struct sysdev_class * cls;
@@ -363,7 +362,6 @@ static void __sysdev_resume(struct sys_device *dev)
363 * This is only called by the device PM core, so we let them handle 362 * This is only called by the device PM core, so we let them handle
364 * all synchronization. 363 * all synchronization.
365 */ 364 */
366
367int sysdev_suspend(pm_message_t state) 365int sysdev_suspend(pm_message_t state)
368{ 366{
369 struct sysdev_class * cls; 367 struct sysdev_class * cls;
@@ -432,7 +430,7 @@ aux_driver:
432 } 430 }
433 return ret; 431 return ret;
434} 432}
435 433EXPORT_SYMBOL_GPL(sysdev_suspend);
436 434
437/** 435/**
438 * sysdev_resume - Bring system devices back to life. 436 * sysdev_resume - Bring system devices back to life.
@@ -442,7 +440,6 @@ aux_driver:
442 * 440 *
443 * Note: Interrupts are disabled when called. 441 * Note: Interrupts are disabled when called.
444 */ 442 */
445
446int sysdev_resume(void) 443int sysdev_resume(void)
447{ 444{
448 struct sysdev_class * cls; 445 struct sysdev_class * cls;
@@ -463,7 +460,7 @@ int sysdev_resume(void)
463 } 460 }
464 return 0; 461 return 0;
465} 462}
466 463EXPORT_SYMBOL_GPL(sysdev_resume);
467 464
468int __init system_bus_init(void) 465int __init system_bus_init(void)
469{ 466{
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 81f1cff56fd5..6949c2d58f1d 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -202,7 +202,7 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
202 dev_priv->ring.map.flags = 0; 202 dev_priv->ring.map.flags = 0;
203 dev_priv->ring.map.mtrr = 0; 203 dev_priv->ring.map.mtrr = 0;
204 204
205 drm_core_ioremap(&dev_priv->ring.map, dev); 205 drm_core_ioremap_wc(&dev_priv->ring.map, dev);
206 206
207 if (dev_priv->ring.map.handle == NULL) { 207 if (dev_priv->ring.map.handle == NULL) {
208 i915_dma_cleanup(dev); 208 i915_dma_cleanup(dev);
@@ -1090,6 +1090,11 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1090 dev_priv->mm.gtt_mapping = 1090 dev_priv->mm.gtt_mapping =
1091 io_mapping_create_wc(dev->agp->base, 1091 io_mapping_create_wc(dev->agp->base,
1092 dev->agp->agp_info.aper_size * 1024*1024); 1092 dev->agp->agp_info.aper_size * 1024*1024);
1093 if (dev_priv->mm.gtt_mapping == NULL) {
1094 ret = -EIO;
1095 goto out_rmmap;
1096 }
1097
1093 /* Set up a WC MTRR for non-PAT systems. This is more common than 1098 /* Set up a WC MTRR for non-PAT systems. This is more common than
1094 * one would think, because the kernel disables PAT on first 1099 * one would think, because the kernel disables PAT on first
1095 * generation Core chips because WC PAT gets overridden by a UC 1100 * generation Core chips because WC PAT gets overridden by a UC
@@ -1122,7 +1127,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1122 if (!I915_NEED_GFX_HWS(dev)) { 1127 if (!I915_NEED_GFX_HWS(dev)) {
1123 ret = i915_init_phys_hws(dev); 1128 ret = i915_init_phys_hws(dev);
1124 if (ret != 0) 1129 if (ret != 0)
1125 goto out_rmmap; 1130 goto out_iomapfree;
1126 } 1131 }
1127 1132
1128 /* On the 945G/GM, the chipset reports the MSI capability on the 1133 /* On the 945G/GM, the chipset reports the MSI capability on the
@@ -1161,6 +1166,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1161 1166
1162 return 0; 1167 return 0;
1163 1168
1169out_iomapfree:
1170 io_mapping_free(dev_priv->mm.gtt_mapping);
1164out_rmmap: 1171out_rmmap:
1165 iounmap(dev_priv->regs); 1172 iounmap(dev_priv->regs);
1166free_priv: 1173free_priv:
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a31cbdbc3c54..b293ef0bae71 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -27,6 +27,7 @@
27 * 27 *
28 */ 28 */
29 29
30#include <linux/device.h>
30#include "drmP.h" 31#include "drmP.h"
31#include "drm.h" 32#include "drm.h"
32#include "i915_drm.h" 33#include "i915_drm.h"
@@ -66,6 +67,14 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
66 67
67 i915_save_state(dev); 68 i915_save_state(dev);
68 69
70 /* If KMS is active, we do the leavevt stuff here */
71 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
72 if (i915_gem_idle(dev))
73 dev_err(&dev->pdev->dev,
74 "GEM idle failed, resume may fail\n");
75 drm_irq_uninstall(dev);
76 }
77
69 intel_opregion_free(dev); 78 intel_opregion_free(dev);
70 79
71 if (state.event == PM_EVENT_SUSPEND) { 80 if (state.event == PM_EVENT_SUSPEND) {
@@ -79,6 +88,9 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
79 88
80static int i915_resume(struct drm_device *dev) 89static int i915_resume(struct drm_device *dev)
81{ 90{
91 struct drm_i915_private *dev_priv = dev->dev_private;
92 int ret = 0;
93
82 pci_set_power_state(dev->pdev, PCI_D0); 94 pci_set_power_state(dev->pdev, PCI_D0);
83 pci_restore_state(dev->pdev); 95 pci_restore_state(dev->pdev);
84 if (pci_enable_device(dev->pdev)) 96 if (pci_enable_device(dev->pdev))
@@ -89,7 +101,20 @@ static int i915_resume(struct drm_device *dev)
89 101
90 intel_opregion_init(dev); 102 intel_opregion_init(dev);
91 103
92 return 0; 104 /* KMS EnterVT equivalent */
105 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
106 mutex_lock(&dev->struct_mutex);
107 dev_priv->mm.suspended = 0;
108
109 ret = i915_gem_init_ringbuffer(dev);
110 if (ret != 0)
111 ret = -1;
112 mutex_unlock(&dev->struct_mutex);
113
114 drm_irq_install(dev);
115 }
116
117 return ret;
93} 118}
94 119
95static struct vm_operations_struct i915_gem_vm_ops = { 120static struct vm_operations_struct i915_gem_vm_ops = {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 135a08f615cd..17fa40858d26 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -618,6 +618,7 @@ int i915_gem_init_ringbuffer(struct drm_device *dev);
618void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 618void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
619int i915_gem_do_init(struct drm_device *dev, unsigned long start, 619int i915_gem_do_init(struct drm_device *dev, unsigned long start,
620 unsigned long end); 620 unsigned long end);
621int i915_gem_idle(struct drm_device *dev);
621int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 622int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
622int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, 623int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
623 int write); 624 int write);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ac534c9a2f81..e9882d0c2473 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -34,10 +34,6 @@
34 34
35#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 35#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
36 36
37static void
38i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
39 uint32_t read_domains,
40 uint32_t write_domain);
41static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); 37static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
42static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); 38static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
43static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); 39static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
@@ -215,7 +211,7 @@ fast_user_write(struct io_mapping *mapping,
215 211
216 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); 212 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
217 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, 213 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
218 user_data, length); 214 user_data, length, length);
219 io_mapping_unmap_atomic(vaddr_atomic); 215 io_mapping_unmap_atomic(vaddr_atomic);
220 if (unwritten) 216 if (unwritten)
221 return -EFAULT; 217 return -EFAULT;
@@ -1055,6 +1051,9 @@ i915_gem_retire_requests(struct drm_device *dev)
1055 drm_i915_private_t *dev_priv = dev->dev_private; 1051 drm_i915_private_t *dev_priv = dev->dev_private;
1056 uint32_t seqno; 1052 uint32_t seqno;
1057 1053
1054 if (!dev_priv->hw_status_page)
1055 return;
1056
1058 seqno = i915_get_gem_seqno(dev); 1057 seqno = i915_get_gem_seqno(dev);
1059 1058
1060 while (!list_empty(&dev_priv->mm.request_list)) { 1059 while (!list_empty(&dev_priv->mm.request_list)) {
@@ -2021,30 +2020,28 @@ i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2021 * drm_agp_chipset_flush 2020 * drm_agp_chipset_flush
2022 */ 2021 */
2023static void 2022static void
2024i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, 2023i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2025 uint32_t read_domains,
2026 uint32_t write_domain)
2027{ 2024{
2028 struct drm_device *dev = obj->dev; 2025 struct drm_device *dev = obj->dev;
2029 struct drm_i915_gem_object *obj_priv = obj->driver_private; 2026 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2030 uint32_t invalidate_domains = 0; 2027 uint32_t invalidate_domains = 0;
2031 uint32_t flush_domains = 0; 2028 uint32_t flush_domains = 0;
2032 2029
2033 BUG_ON(read_domains & I915_GEM_DOMAIN_CPU); 2030 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2034 BUG_ON(write_domain == I915_GEM_DOMAIN_CPU); 2031 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2035 2032
2036#if WATCH_BUF 2033#if WATCH_BUF
2037 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", 2034 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2038 __func__, obj, 2035 __func__, obj,
2039 obj->read_domains, read_domains, 2036 obj->read_domains, obj->pending_read_domains,
2040 obj->write_domain, write_domain); 2037 obj->write_domain, obj->pending_write_domain);
2041#endif 2038#endif
2042 /* 2039 /*
2043 * If the object isn't moving to a new write domain, 2040 * If the object isn't moving to a new write domain,
2044 * let the object stay in multiple read domains 2041 * let the object stay in multiple read domains
2045 */ 2042 */
2046 if (write_domain == 0) 2043 if (obj->pending_write_domain == 0)
2047 read_domains |= obj->read_domains; 2044 obj->pending_read_domains |= obj->read_domains;
2048 else 2045 else
2049 obj_priv->dirty = 1; 2046 obj_priv->dirty = 1;
2050 2047
@@ -2054,15 +2051,17 @@ i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
2054 * any read domains which differ from the old 2051 * any read domains which differ from the old
2055 * write domain 2052 * write domain
2056 */ 2053 */
2057 if (obj->write_domain && obj->write_domain != read_domains) { 2054 if (obj->write_domain &&
2055 obj->write_domain != obj->pending_read_domains) {
2058 flush_domains |= obj->write_domain; 2056 flush_domains |= obj->write_domain;
2059 invalidate_domains |= read_domains & ~obj->write_domain; 2057 invalidate_domains |=
2058 obj->pending_read_domains & ~obj->write_domain;
2060 } 2059 }
2061 /* 2060 /*
2062 * Invalidate any read caches which may have 2061 * Invalidate any read caches which may have
2063 * stale data. That is, any new read domains. 2062 * stale data. That is, any new read domains.
2064 */ 2063 */
2065 invalidate_domains |= read_domains & ~obj->read_domains; 2064 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
2066 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) { 2065 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2067#if WATCH_BUF 2066#if WATCH_BUF
2068 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n", 2067 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
@@ -2071,9 +2070,15 @@ i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
2071 i915_gem_clflush_object(obj); 2070 i915_gem_clflush_object(obj);
2072 } 2071 }
2073 2072
2074 if ((write_domain | flush_domains) != 0) 2073 /* The actual obj->write_domain will be updated with
2075 obj->write_domain = write_domain; 2074 * pending_write_domain after we emit the accumulated flush for all
2076 obj->read_domains = read_domains; 2075 * of our domain changes in execbuffers (which clears objects'
2076 * write_domains). So if we have a current write domain that we
2077 * aren't changing, set pending_write_domain to that.
2078 */
2079 if (flush_domains == 0 && obj->pending_write_domain == 0)
2080 obj->pending_write_domain = obj->write_domain;
2081 obj->read_domains = obj->pending_read_domains;
2077 2082
2078 dev->invalidate_domains |= invalidate_domains; 2083 dev->invalidate_domains |= invalidate_domains;
2079 dev->flush_domains |= flush_domains; 2084 dev->flush_domains |= flush_domains;
@@ -2583,9 +2588,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
2583 struct drm_gem_object *obj = object_list[i]; 2588 struct drm_gem_object *obj = object_list[i];
2584 2589
2585 /* Compute new gpu domains and update invalidate/flush */ 2590 /* Compute new gpu domains and update invalidate/flush */
2586 i915_gem_object_set_to_gpu_domain(obj, 2591 i915_gem_object_set_to_gpu_domain(obj);
2587 obj->pending_read_domains,
2588 obj->pending_write_domain);
2589 } 2592 }
2590 2593
2591 i915_verify_inactive(dev, __FILE__, __LINE__); 2594 i915_verify_inactive(dev, __FILE__, __LINE__);
@@ -2604,6 +2607,12 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
2604 (void)i915_add_request(dev, dev->flush_domains); 2607 (void)i915_add_request(dev, dev->flush_domains);
2605 } 2608 }
2606 2609
2610 for (i = 0; i < args->buffer_count; i++) {
2611 struct drm_gem_object *obj = object_list[i];
2612
2613 obj->write_domain = obj->pending_write_domain;
2614 }
2615
2607 i915_verify_inactive(dev, __FILE__, __LINE__); 2616 i915_verify_inactive(dev, __FILE__, __LINE__);
2608 2617
2609#if WATCH_COHERENCY 2618#if WATCH_COHERENCY
@@ -2866,6 +2875,13 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2866 return -EBADF; 2875 return -EBADF;
2867 } 2876 }
2868 2877
2878 /* Update the active list for the hardware's current position.
2879 * Otherwise this only updates on a delayed timer or when irqs are
2880 * actually unmasked, and our working set ends up being larger than
2881 * required.
2882 */
2883 i915_gem_retire_requests(dev);
2884
2869 obj_priv = obj->driver_private; 2885 obj_priv = obj->driver_private;
2870 /* Don't count being on the flushing list against the object being 2886 /* Don't count being on the flushing list against the object being
2871 * done. Otherwise, a buffer left on the flushing list but not getting 2887 * done. Otherwise, a buffer left on the flushing list but not getting
@@ -2967,7 +2983,7 @@ i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
2967 return 0; 2983 return 0;
2968} 2984}
2969 2985
2970static int 2986int
2971i915_gem_idle(struct drm_device *dev) 2987i915_gem_idle(struct drm_device *dev)
2972{ 2988{
2973 drm_i915_private_t *dev_priv = dev->dev_private; 2989 drm_i915_private_t *dev_priv = dev->dev_private;
@@ -3130,16 +3146,20 @@ static void
3130i915_gem_cleanup_hws(struct drm_device *dev) 3146i915_gem_cleanup_hws(struct drm_device *dev)
3131{ 3147{
3132 drm_i915_private_t *dev_priv = dev->dev_private; 3148 drm_i915_private_t *dev_priv = dev->dev_private;
3133 struct drm_gem_object *obj = dev_priv->hws_obj; 3149 struct drm_gem_object *obj;
3134 struct drm_i915_gem_object *obj_priv = obj->driver_private; 3150 struct drm_i915_gem_object *obj_priv;
3135 3151
3136 if (dev_priv->hws_obj == NULL) 3152 if (dev_priv->hws_obj == NULL)
3137 return; 3153 return;
3138 3154
3155 obj = dev_priv->hws_obj;
3156 obj_priv = obj->driver_private;
3157
3139 kunmap(obj_priv->page_list[0]); 3158 kunmap(obj_priv->page_list[0]);
3140 i915_gem_object_unpin(obj); 3159 i915_gem_object_unpin(obj);
3141 drm_gem_object_unreference(obj); 3160 drm_gem_object_unreference(obj);
3142 dev_priv->hws_obj = NULL; 3161 dev_priv->hws_obj = NULL;
3162
3143 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); 3163 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3144 dev_priv->hw_status_page = NULL; 3164 dev_priv->hw_status_page = NULL;
3145 3165
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4d2baf7b00be..65b635ce28c8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1008,6 +1008,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
1008 temp = CURSOR_MODE_DISABLE; 1008 temp = CURSOR_MODE_DISABLE;
1009 addr = 0; 1009 addr = 0;
1010 bo = NULL; 1010 bo = NULL;
1011 mutex_lock(&dev->struct_mutex);
1011 goto finish; 1012 goto finish;
1012 } 1013 }
1013 1014
diff --git a/drivers/i2c/busses/i2c-acorn.c b/drivers/i2c/busses/i2c-acorn.c
index 9fee3ca17344..9aefb5e5864d 100644
--- a/drivers/i2c/busses/i2c-acorn.c
+++ b/drivers/i2c/busses/i2c-acorn.c
@@ -79,10 +79,11 @@ static struct i2c_algo_bit_data ioc_data = {
79 .getsda = ioc_getsda, 79 .getsda = ioc_getsda,
80 .getscl = ioc_getscl, 80 .getscl = ioc_getscl,
81 .udelay = 80, 81 .udelay = 80,
82 .timeout = 100 82 .timeout = HZ,
83}; 83};
84 84
85static struct i2c_adapter ioc_ops = { 85static struct i2c_adapter ioc_ops = {
86 .nr = 0,
86 .algo_data = &ioc_data, 87 .algo_data = &ioc_data,
87}; 88};
88 89
@@ -90,7 +91,7 @@ static int __init i2c_ioc_init(void)
90{ 91{
91 force_ones = FORCE_ONES | SCL | SDA; 92 force_ones = FORCE_ONES | SCL | SDA;
92 93
93 return i2c_bit_add_bus(&ioc_ops); 94 return i2c_bit_add_numbered_bus(&ioc_ops);
94} 95}
95 96
96module_init(i2c_ioc_init); 97module_init(i2c_ioc_init);
diff --git a/drivers/i2c/busses/i2c-amd8111.c b/drivers/i2c/busses/i2c-amd8111.c
index edab51973bf5..a7c59908c457 100644
--- a/drivers/i2c/busses/i2c-amd8111.c
+++ b/drivers/i2c/busses/i2c-amd8111.c
@@ -72,7 +72,7 @@ static unsigned int amd_ec_wait_write(struct amd_smbus *smbus)
72{ 72{
73 int timeout = 500; 73 int timeout = 500;
74 74
75 while (timeout-- && (inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF)) 75 while ((inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF) && --timeout)
76 udelay(1); 76 udelay(1);
77 77
78 if (!timeout) { 78 if (!timeout) {
@@ -88,7 +88,7 @@ static unsigned int amd_ec_wait_read(struct amd_smbus *smbus)
88{ 88{
89 int timeout = 500; 89 int timeout = 500;
90 90
91 while (timeout-- && (~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF)) 91 while ((~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF) && --timeout)
92 udelay(1); 92 udelay(1);
93 93
94 if (!timeout) { 94 if (!timeout) {
diff --git a/drivers/i2c/busses/i2c-ixp2000.c b/drivers/i2c/busses/i2c-ixp2000.c
index 8e8467970481..c016f7a2c5fc 100644
--- a/drivers/i2c/busses/i2c-ixp2000.c
+++ b/drivers/i2c/busses/i2c-ixp2000.c
@@ -114,7 +114,7 @@ static int ixp2000_i2c_probe(struct platform_device *plat_dev)
114 drv_data->algo_data.getsda = ixp2000_bit_getsda; 114 drv_data->algo_data.getsda = ixp2000_bit_getsda;
115 drv_data->algo_data.getscl = ixp2000_bit_getscl; 115 drv_data->algo_data.getscl = ixp2000_bit_getscl;
116 drv_data->algo_data.udelay = 6; 116 drv_data->algo_data.udelay = 6;
117 drv_data->algo_data.timeout = 100; 117 drv_data->algo_data.timeout = HZ;
118 118
119 strlcpy(drv_data->adapter.name, plat_dev->dev.driver->name, 119 strlcpy(drv_data->adapter.name, plat_dev->dev.driver->name,
120 sizeof(drv_data->adapter.name)); 120 sizeof(drv_data->adapter.name));
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index 6af68146c342..bdb1f7510e91 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -644,7 +644,7 @@ static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
644 644
645 i2c_pxa_start_message(i2c); 645 i2c_pxa_start_message(i2c);
646 646
647 while (timeout-- && i2c->msg_num > 0) { 647 while (i2c->msg_num > 0 && --timeout) {
648 i2c_pxa_handler(0, i2c); 648 i2c_pxa_handler(0, i2c);
649 udelay(10); 649 udelay(10);
650 } 650 }
diff --git a/drivers/i2c/busses/scx200_i2c.c b/drivers/i2c/busses/scx200_i2c.c
index 162b74a04886..42df0eca43d5 100644
--- a/drivers/i2c/busses/scx200_i2c.c
+++ b/drivers/i2c/busses/scx200_i2c.c
@@ -76,7 +76,7 @@ static struct i2c_algo_bit_data scx200_i2c_data = {
76 .getsda = scx200_i2c_getsda, 76 .getsda = scx200_i2c_getsda,
77 .getscl = scx200_i2c_getscl, 77 .getscl = scx200_i2c_getscl,
78 .udelay = 10, 78 .udelay = 10,
79 .timeout = 100, 79 .timeout = HZ,
80}; 80};
81 81
82static struct i2c_adapter scx200_i2c_ops = { 82static struct i2c_adapter scx200_i2c_ops = {
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index b1c9abe24c7b..e7d984866de0 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -1831,7 +1831,8 @@ static s32 i2c_smbus_xfer_emulated(struct i2c_adapter * adapter, u16 addr,
1831 case I2C_SMBUS_QUICK: 1831 case I2C_SMBUS_QUICK:
1832 msg[0].len = 0; 1832 msg[0].len = 0;
1833 /* Special case: The read/write field is used as data */ 1833 /* Special case: The read/write field is used as data */
1834 msg[0].flags = flags | (read_write==I2C_SMBUS_READ)?I2C_M_RD:0; 1834 msg[0].flags = flags | (read_write == I2C_SMBUS_READ ?
1835 I2C_M_RD : 0);
1835 num = 1; 1836 num = 1;
1836 break; 1837 break;
1837 case I2C_SMBUS_BYTE: 1838 case I2C_SMBUS_BYTE:
diff --git a/drivers/i2c/i2c-dev.c b/drivers/i2c/i2c-dev.c
index c171988a9f51..7e13d2df9af3 100644
--- a/drivers/i2c/i2c-dev.c
+++ b/drivers/i2c/i2c-dev.c
@@ -35,6 +35,7 @@
35#include <linux/i2c.h> 35#include <linux/i2c.h>
36#include <linux/i2c-dev.h> 36#include <linux/i2c-dev.h>
37#include <linux/smp_lock.h> 37#include <linux/smp_lock.h>
38#include <linux/jiffies.h>
38#include <asm/uaccess.h> 39#include <asm/uaccess.h>
39 40
40static struct i2c_driver i2cdev_driver; 41static struct i2c_driver i2cdev_driver;
@@ -422,7 +423,10 @@ static long i2cdev_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
422 client->adapter->retries = arg; 423 client->adapter->retries = arg;
423 break; 424 break;
424 case I2C_TIMEOUT: 425 case I2C_TIMEOUT:
425 client->adapter->timeout = arg; 426 /* For historical reasons, user-space sets the timeout
427 * value in units of 10 ms.
428 */
429 client->adapter->timeout = msecs_to_jiffies(arg * 10);
426 break; 430 break;
427 default: 431 default:
428 /* NOTE: returning a fault code here could cause trouble 432 /* NOTE: returning a fault code here could cause trouble
diff --git a/drivers/ieee1394/dma.h b/drivers/ieee1394/dma.h
index 2727bcd24194..467373cab8e5 100644
--- a/drivers/ieee1394/dma.h
+++ b/drivers/ieee1394/dma.h
@@ -12,6 +12,7 @@
12 12
13#include <asm/types.h> 13#include <asm/types.h>
14 14
15struct file;
15struct pci_dev; 16struct pci_dev;
16struct scatterlist; 17struct scatterlist;
17struct vm_area_struct; 18struct vm_area_struct;
diff --git a/drivers/ieee1394/ieee1394_core.c b/drivers/ieee1394/ieee1394_core.c
index 2beb8d94f7bd..1028e725a27e 100644
--- a/drivers/ieee1394/ieee1394_core.c
+++ b/drivers/ieee1394/ieee1394_core.c
@@ -1314,6 +1314,7 @@ EXPORT_SYMBOL(hpsb_make_lock64packet);
1314EXPORT_SYMBOL(hpsb_make_phypacket); 1314EXPORT_SYMBOL(hpsb_make_phypacket);
1315EXPORT_SYMBOL(hpsb_read); 1315EXPORT_SYMBOL(hpsb_read);
1316EXPORT_SYMBOL(hpsb_write); 1316EXPORT_SYMBOL(hpsb_write);
1317EXPORT_SYMBOL(hpsb_lock);
1317EXPORT_SYMBOL(hpsb_packet_success); 1318EXPORT_SYMBOL(hpsb_packet_success);
1318 1319
1319/** highlevel.c **/ 1320/** highlevel.c **/
diff --git a/drivers/ieee1394/ieee1394_transactions.c b/drivers/ieee1394/ieee1394_transactions.c
index 10c3d9f8c038..675b3135d5f1 100644
--- a/drivers/ieee1394/ieee1394_transactions.c
+++ b/drivers/ieee1394/ieee1394_transactions.c
@@ -501,8 +501,6 @@ int hpsb_read(struct hpsb_host *host, nodeid_t node, unsigned int generation,
501 if (length == 0) 501 if (length == 0)
502 return -EINVAL; 502 return -EINVAL;
503 503
504 BUG_ON(in_interrupt()); // We can't be called in an interrupt, yet
505
506 packet = hpsb_make_readpacket(host, node, addr, length); 504 packet = hpsb_make_readpacket(host, node, addr, length);
507 505
508 if (!packet) { 506 if (!packet) {
@@ -550,8 +548,6 @@ int hpsb_write(struct hpsb_host *host, nodeid_t node, unsigned int generation,
550 if (length == 0) 548 if (length == 0)
551 return -EINVAL; 549 return -EINVAL;
552 550
553 BUG_ON(in_interrupt()); // We can't be called in an interrupt, yet
554
555 packet = hpsb_make_writepacket(host, node, addr, buffer, length); 551 packet = hpsb_make_writepacket(host, node, addr, buffer, length);
556 552
557 if (!packet) 553 if (!packet)
@@ -570,3 +566,30 @@ int hpsb_write(struct hpsb_host *host, nodeid_t node, unsigned int generation,
570 566
571 return retval; 567 return retval;
572} 568}
569
570int hpsb_lock(struct hpsb_host *host, nodeid_t node, unsigned int generation,
571 u64 addr, int extcode, quadlet_t *data, quadlet_t arg)
572{
573 struct hpsb_packet *packet;
574 int retval = 0;
575
576 packet = hpsb_make_lockpacket(host, node, addr, extcode, data, arg);
577 if (!packet)
578 return -ENOMEM;
579
580 packet->generation = generation;
581 retval = hpsb_send_packet_and_wait(packet);
582 if (retval < 0)
583 goto hpsb_lock_fail;
584
585 retval = hpsb_packet_success(packet);
586
587 if (retval == 0)
588 *data = packet->data[0];
589
590hpsb_lock_fail:
591 hpsb_free_tlabel(packet);
592 hpsb_free_packet(packet);
593
594 return retval;
595}
diff --git a/drivers/ieee1394/ieee1394_transactions.h b/drivers/ieee1394/ieee1394_transactions.h
index d2d5bc3546d7..20b693be14b2 100644
--- a/drivers/ieee1394/ieee1394_transactions.h
+++ b/drivers/ieee1394/ieee1394_transactions.h
@@ -30,6 +30,8 @@ int hpsb_read(struct hpsb_host *host, nodeid_t node, unsigned int generation,
30 u64 addr, quadlet_t *buffer, size_t length); 30 u64 addr, quadlet_t *buffer, size_t length);
31int hpsb_write(struct hpsb_host *host, nodeid_t node, unsigned int generation, 31int hpsb_write(struct hpsb_host *host, nodeid_t node, unsigned int generation,
32 u64 addr, quadlet_t *buffer, size_t length); 32 u64 addr, quadlet_t *buffer, size_t length);
33int hpsb_lock(struct hpsb_host *host, nodeid_t node, unsigned int generation,
34 u64 addr, int extcode, quadlet_t *data, quadlet_t arg);
33 35
34#ifdef HPSB_DEBUG_TLABELS 36#ifdef HPSB_DEBUG_TLABELS
35extern spinlock_t hpsb_tlabel_lock; 37extern spinlock_t hpsb_tlabel_lock;
diff --git a/drivers/ieee1394/iso.h b/drivers/ieee1394/iso.h
index b5de5f21ef78..c2089c093aa7 100644
--- a/drivers/ieee1394/iso.h
+++ b/drivers/ieee1394/iso.h
@@ -13,6 +13,7 @@
13#define IEEE1394_ISO_H 13#define IEEE1394_ISO_H
14 14
15#include <linux/spinlock_types.h> 15#include <linux/spinlock_types.h>
16#include <linux/wait.h>
16#include <asm/atomic.h> 17#include <asm/atomic.h>
17#include <asm/types.h> 18#include <asm/types.h>
18 19
diff --git a/drivers/ieee1394/nodemgr.c b/drivers/ieee1394/nodemgr.c
index 906c5a98d814..53aada5bbe1e 100644
--- a/drivers/ieee1394/nodemgr.c
+++ b/drivers/ieee1394/nodemgr.c
@@ -971,6 +971,9 @@ static struct unit_directory *nodemgr_process_unit_directory
971 ud->ud_kv = ud_kv; 971 ud->ud_kv = ud_kv;
972 ud->id = (*id)++; 972 ud->id = (*id)++;
973 973
974 /* inherit vendor_id from root directory if none exists in unit dir */
975 ud->vendor_id = ne->vendor_id;
976
974 csr1212_for_each_dir_entry(ne->csr, kv, ud_kv, dentry) { 977 csr1212_for_each_dir_entry(ne->csr, kv, ud_kv, dentry) {
975 switch (kv->key.id) { 978 switch (kv->key.id) {
976 case CSR1212_KV_ID_VENDOR: 979 case CSR1212_KV_ID_VENDOR:
@@ -1265,7 +1268,8 @@ static void nodemgr_update_node(struct node_entry *ne, struct csr1212_csr *csr,
1265 csr1212_destroy_csr(csr); 1268 csr1212_destroy_csr(csr);
1266 } 1269 }
1267 1270
1268 /* Mark the node current */ 1271 /* Finally, mark the node current */
1272 smp_wmb();
1269 ne->generation = generation; 1273 ne->generation = generation;
1270 1274
1271 if (ne->in_limbo) { 1275 if (ne->in_limbo) {
@@ -1798,7 +1802,7 @@ void hpsb_node_fill_packet(struct node_entry *ne, struct hpsb_packet *packet)
1798{ 1802{
1799 packet->host = ne->host; 1803 packet->host = ne->host;
1800 packet->generation = ne->generation; 1804 packet->generation = ne->generation;
1801 barrier(); 1805 smp_rmb();
1802 packet->node_id = ne->nodeid; 1806 packet->node_id = ne->nodeid;
1803} 1807}
1804 1808
@@ -1807,7 +1811,7 @@ int hpsb_node_write(struct node_entry *ne, u64 addr,
1807{ 1811{
1808 unsigned int generation = ne->generation; 1812 unsigned int generation = ne->generation;
1809 1813
1810 barrier(); 1814 smp_rmb();
1811 return hpsb_write(ne->host, ne->nodeid, generation, 1815 return hpsb_write(ne->host, ne->nodeid, generation,
1812 addr, buffer, length); 1816 addr, buffer, length);
1813} 1817}
diff --git a/drivers/ieee1394/nodemgr.h b/drivers/ieee1394/nodemgr.h
index 15ea09733e84..ee5acdbd114a 100644
--- a/drivers/ieee1394/nodemgr.h
+++ b/drivers/ieee1394/nodemgr.h
@@ -21,9 +21,11 @@
21#define _IEEE1394_NODEMGR_H 21#define _IEEE1394_NODEMGR_H
22 22
23#include <linux/device.h> 23#include <linux/device.h>
24#include <asm/system.h>
24#include <asm/types.h> 25#include <asm/types.h>
25 26
26#include "ieee1394_core.h" 27#include "ieee1394_core.h"
28#include "ieee1394_transactions.h"
27#include "ieee1394_types.h" 29#include "ieee1394_types.h"
28 30
29struct csr1212_csr; 31struct csr1212_csr;
@@ -154,6 +156,22 @@ static inline int hpsb_node_entry_valid(struct node_entry *ne)
154void hpsb_node_fill_packet(struct node_entry *ne, struct hpsb_packet *packet); 156void hpsb_node_fill_packet(struct node_entry *ne, struct hpsb_packet *packet);
155int hpsb_node_write(struct node_entry *ne, u64 addr, 157int hpsb_node_write(struct node_entry *ne, u64 addr,
156 quadlet_t *buffer, size_t length); 158 quadlet_t *buffer, size_t length);
159static inline int hpsb_node_read(struct node_entry *ne, u64 addr,
160 quadlet_t *buffer, size_t length)
161{
162 unsigned int g = ne->generation;
163
164 smp_rmb();
165 return hpsb_read(ne->host, ne->nodeid, g, addr, buffer, length);
166}
167static inline int hpsb_node_lock(struct node_entry *ne, u64 addr, int extcode,
168 quadlet_t *buffer, quadlet_t arg)
169{
170 unsigned int g = ne->generation;
171
172 smp_rmb();
173 return hpsb_lock(ne->host, ne->nodeid, g, addr, extcode, buffer, arg);
174}
157int nodemgr_for_each_host(void *data, int (*cb)(struct hpsb_host *, void *)); 175int nodemgr_for_each_host(void *data, int (*cb)(struct hpsb_host *, void *));
158 176
159int init_ieee1394_nodemgr(void); 177int init_ieee1394_nodemgr(void);
diff --git a/drivers/isdn/sc/shmem.c b/drivers/isdn/sc/shmem.c
index 712220cef139..7f16d75d2d89 100644
--- a/drivers/isdn/sc/shmem.c
+++ b/drivers/isdn/sc/shmem.c
@@ -54,7 +54,7 @@ void memcpy_toshmem(int card, void *dest, const void *src, size_t n)
54 spin_unlock_irqrestore(&sc_adapter[card]->lock, flags); 54 spin_unlock_irqrestore(&sc_adapter[card]->lock, flags);
55 pr_debug("%s: set page to %#x\n",sc_adapter[card]->devicename, 55 pr_debug("%s: set page to %#x\n",sc_adapter[card]->devicename,
56 ((sc_adapter[card]->shmem_magic + ch * SRAM_PAGESIZE)>>14)|0x80); 56 ((sc_adapter[card]->shmem_magic + ch * SRAM_PAGESIZE)>>14)|0x80);
57 pr_debug("%s: copying %d bytes from %#lx to %#lx\n", 57 pr_debug("%s: copying %zu bytes from %#lx to %#lx\n",
58 sc_adapter[card]->devicename, n, 58 sc_adapter[card]->devicename, n,
59 (unsigned long) src, 59 (unsigned long) src,
60 sc_adapter[card]->rambase + ((unsigned long) dest %0x4000)); 60 sc_adapter[card]->rambase + ((unsigned long) dest %0x4000));
diff --git a/drivers/media/dvb/Kconfig b/drivers/media/dvb/Kconfig
index 40ebde53b3ce..b0198691892a 100644
--- a/drivers/media/dvb/Kconfig
+++ b/drivers/media/dvb/Kconfig
@@ -51,6 +51,10 @@ comment "Supported SDMC DM1105 Adapters"
51 depends on DVB_CORE && PCI && I2C 51 depends on DVB_CORE && PCI && I2C
52source "drivers/media/dvb/dm1105/Kconfig" 52source "drivers/media/dvb/dm1105/Kconfig"
53 53
54comment "Supported FireWire (IEEE 1394) Adapters"
55 depends on DVB_CORE && IEEE1394
56source "drivers/media/dvb/firewire/Kconfig"
57
54comment "Supported DVB Frontends" 58comment "Supported DVB Frontends"
55 depends on DVB_CORE 59 depends on DVB_CORE
56source "drivers/media/dvb/frontends/Kconfig" 60source "drivers/media/dvb/frontends/Kconfig"
diff --git a/drivers/media/dvb/Makefile b/drivers/media/dvb/Makefile
index f91e9eb15e52..6092a5bb5a7d 100644
--- a/drivers/media/dvb/Makefile
+++ b/drivers/media/dvb/Makefile
@@ -3,3 +3,5 @@
3# 3#
4 4
5obj-y := dvb-core/ frontends/ ttpci/ ttusb-dec/ ttusb-budget/ b2c2/ bt8xx/ dvb-usb/ pluto2/ siano/ dm1105/ 5obj-y := dvb-core/ frontends/ ttpci/ ttusb-dec/ ttusb-budget/ b2c2/ bt8xx/ dvb-usb/ pluto2/ siano/ dm1105/
6
7obj-$(CONFIG_DVB_FIREDTV) += firewire/
diff --git a/drivers/media/dvb/firewire/Kconfig b/drivers/media/dvb/firewire/Kconfig
new file mode 100644
index 000000000000..69028253e984
--- /dev/null
+++ b/drivers/media/dvb/firewire/Kconfig
@@ -0,0 +1,22 @@
1config DVB_FIREDTV
2 tristate "FireDTV and FloppyDTV"
3 depends on DVB_CORE && IEEE1394
4 help
5 Support for DVB receivers from Digital Everywhere
6 which are connected via IEEE 1394 (FireWire).
7
8 These devices don't have an MPEG decoder built in,
9 so you need an external software decoder to watch TV.
10
11 To compile this driver as a module, say M here:
12 the module will be called firedtv.
13
14if DVB_FIREDTV
15
16config DVB_FIREDTV_IEEE1394
17 def_bool IEEE1394
18
19config DVB_FIREDTV_INPUT
20 def_bool INPUT = y || (INPUT = m && DVB_FIREDTV = m)
21
22endif # DVB_FIREDTV
diff --git a/drivers/media/dvb/firewire/Makefile b/drivers/media/dvb/firewire/Makefile
new file mode 100644
index 000000000000..2034695ba194
--- /dev/null
+++ b/drivers/media/dvb/firewire/Makefile
@@ -0,0 +1,8 @@
1obj-$(CONFIG_DVB_FIREDTV) += firedtv.o
2
3firedtv-y := firedtv-avc.o firedtv-ci.o firedtv-dvb.o firedtv-fe.o
4firedtv-$(CONFIG_DVB_FIREDTV_IEEE1394) += firedtv-1394.o
5firedtv-$(CONFIG_DVB_FIREDTV_INPUT) += firedtv-rc.o
6
7ccflags-y += -Idrivers/media/dvb/dvb-core
8ccflags-$(CONFIG_DVB_FIREDTV_IEEE1394) += -Idrivers/ieee1394
diff --git a/drivers/media/dvb/firewire/firedtv-1394.c b/drivers/media/dvb/firewire/firedtv-1394.c
new file mode 100644
index 000000000000..4e207658c5d9
--- /dev/null
+++ b/drivers/media/dvb/firewire/firedtv-1394.c
@@ -0,0 +1,285 @@
1/*
2 * FireDTV driver (formerly known as FireSAT)
3 *
4 * Copyright (C) 2004 Andreas Monitzer <andy@monitzer.com>
5 * Copyright (C) 2007-2008 Ben Backx <ben@bbackx.com>
6 * Copyright (C) 2008 Henrik Kurelid <henrik@kurelid.se>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 */
13
14#include <linux/device.h>
15#include <linux/errno.h>
16#include <linux/kernel.h>
17#include <linux/list.h>
18#include <linux/spinlock.h>
19#include <linux/types.h>
20
21#include <dma.h>
22#include <csr1212.h>
23#include <highlevel.h>
24#include <hosts.h>
25#include <ieee1394.h>
26#include <iso.h>
27#include <nodemgr.h>
28
29#include "firedtv.h"
30
31static LIST_HEAD(node_list);
32static DEFINE_SPINLOCK(node_list_lock);
33
34#define FIREWIRE_HEADER_SIZE 4
35#define CIP_HEADER_SIZE 8
36
37static void rawiso_activity_cb(struct hpsb_iso *iso)
38{
39 struct firedtv *f, *fdtv = NULL;
40 unsigned int i, num, packet;
41 unsigned char *buf;
42 unsigned long flags;
43 int count;
44
45 spin_lock_irqsave(&node_list_lock, flags);
46 list_for_each_entry(f, &node_list, list)
47 if (f->backend_data == iso) {
48 fdtv = f;
49 break;
50 }
51 spin_unlock_irqrestore(&node_list_lock, flags);
52
53 packet = iso->first_packet;
54 num = hpsb_iso_n_ready(iso);
55
56 if (!fdtv) {
57 dev_err(fdtv->device, "received at unknown iso channel\n");
58 goto out;
59 }
60
61 for (i = 0; i < num; i++, packet = (packet + 1) % iso->buf_packets) {
62 buf = dma_region_i(&iso->data_buf, unsigned char,
63 iso->infos[packet].offset + CIP_HEADER_SIZE);
64 count = (iso->infos[packet].len - CIP_HEADER_SIZE) /
65 (188 + FIREWIRE_HEADER_SIZE);
66
67 /* ignore empty packet */
68 if (iso->infos[packet].len <= CIP_HEADER_SIZE)
69 continue;
70
71 while (count--) {
72 if (buf[FIREWIRE_HEADER_SIZE] == 0x47)
73 dvb_dmx_swfilter_packets(&fdtv->demux,
74 &buf[FIREWIRE_HEADER_SIZE], 1);
75 else
76 dev_err(fdtv->device,
77 "skipping invalid packet\n");
78 buf += 188 + FIREWIRE_HEADER_SIZE;
79 }
80 }
81out:
82 hpsb_iso_recv_release_packets(iso, num);
83}
84
85static inline struct node_entry *node_of(struct firedtv *fdtv)
86{
87 return container_of(fdtv->device, struct unit_directory, device)->ne;
88}
89
90static int node_lock(struct firedtv *fdtv, u64 addr, void *data, __be32 arg)
91{
92 return hpsb_node_lock(node_of(fdtv), addr, EXTCODE_COMPARE_SWAP, data,
93 (__force quadlet_t)arg);
94}
95
96static int node_read(struct firedtv *fdtv, u64 addr, void *data, size_t len)
97{
98 return hpsb_node_read(node_of(fdtv), addr, data, len);
99}
100
101static int node_write(struct firedtv *fdtv, u64 addr, void *data, size_t len)
102{
103 return hpsb_node_write(node_of(fdtv), addr, data, len);
104}
105
106#define FDTV_ISO_BUFFER_PACKETS 256
107#define FDTV_ISO_BUFFER_SIZE (FDTV_ISO_BUFFER_PACKETS * 200)
108
109static int start_iso(struct firedtv *fdtv)
110{
111 struct hpsb_iso *iso_handle;
112 int ret;
113
114 iso_handle = hpsb_iso_recv_init(node_of(fdtv)->host,
115 FDTV_ISO_BUFFER_SIZE, FDTV_ISO_BUFFER_PACKETS,
116 fdtv->isochannel, HPSB_ISO_DMA_DEFAULT,
117 -1, /* stat.config.irq_interval */
118 rawiso_activity_cb);
119 if (iso_handle == NULL) {
120 dev_err(fdtv->device, "cannot initialize iso receive\n");
121 return -ENOMEM;
122 }
123 fdtv->backend_data = iso_handle;
124
125 ret = hpsb_iso_recv_start(iso_handle, -1, -1, 0);
126 if (ret != 0) {
127 dev_err(fdtv->device, "cannot start iso receive\n");
128 hpsb_iso_shutdown(iso_handle);
129 fdtv->backend_data = NULL;
130 }
131 return ret;
132}
133
134static void stop_iso(struct firedtv *fdtv)
135{
136 struct hpsb_iso *iso_handle = fdtv->backend_data;
137
138 if (iso_handle != NULL) {
139 hpsb_iso_stop(iso_handle);
140 hpsb_iso_shutdown(iso_handle);
141 }
142 fdtv->backend_data = NULL;
143}
144
145static const struct firedtv_backend fdtv_1394_backend = {
146 .lock = node_lock,
147 .read = node_read,
148 .write = node_write,
149 .start_iso = start_iso,
150 .stop_iso = stop_iso,
151};
152
153static void fcp_request(struct hpsb_host *host, int nodeid, int direction,
154 int cts, u8 *data, size_t length)
155{
156 struct firedtv *f, *fdtv = NULL;
157 unsigned long flags;
158 int su;
159
160 if (length == 0 || (data[0] & 0xf0) != 0)
161 return;
162
163 su = data[1] & 0x7;
164
165 spin_lock_irqsave(&node_list_lock, flags);
166 list_for_each_entry(f, &node_list, list)
167 if (node_of(f)->host == host &&
168 node_of(f)->nodeid == nodeid &&
169 (f->subunit == su || (f->subunit == 0 && su == 0x7))) {
170 fdtv = f;
171 break;
172 }
173 spin_unlock_irqrestore(&node_list_lock, flags);
174
175 if (fdtv)
176 avc_recv(fdtv, data, length);
177}
178
179static int node_probe(struct device *dev)
180{
181 struct unit_directory *ud =
182 container_of(dev, struct unit_directory, device);
183 struct firedtv *fdtv;
184 int kv_len, err;
185 void *kv_str;
186
187 kv_len = (ud->model_name_kv->value.leaf.len - 2) * sizeof(quadlet_t);
188 kv_str = CSR1212_TEXTUAL_DESCRIPTOR_LEAF_DATA(ud->model_name_kv);
189
190 fdtv = fdtv_alloc(dev, &fdtv_1394_backend, kv_str, kv_len);
191 if (!fdtv)
192 return -ENOMEM;
193
194 /*
195 * Work around a bug in udev's path_id script: Use the fw-host's dev
196 * instead of the unit directory's dev as parent of the input device.
197 */
198 err = fdtv_register_rc(fdtv, dev->parent->parent);
199 if (err)
200 goto fail_free;
201
202 spin_lock_irq(&node_list_lock);
203 list_add_tail(&fdtv->list, &node_list);
204 spin_unlock_irq(&node_list_lock);
205
206 err = avc_identify_subunit(fdtv);
207 if (err)
208 goto fail;
209
210 err = fdtv_dvb_register(fdtv);
211 if (err)
212 goto fail;
213
214 avc_register_remote_control(fdtv);
215 return 0;
216fail:
217 spin_lock_irq(&node_list_lock);
218 list_del(&fdtv->list);
219 spin_unlock_irq(&node_list_lock);
220 fdtv_unregister_rc(fdtv);
221fail_free:
222 kfree(fdtv);
223 return err;
224}
225
226static int node_remove(struct device *dev)
227{
228 struct firedtv *fdtv = dev->driver_data;
229
230 fdtv_dvb_unregister(fdtv);
231
232 spin_lock_irq(&node_list_lock);
233 list_del(&fdtv->list);
234 spin_unlock_irq(&node_list_lock);
235
236 cancel_work_sync(&fdtv->remote_ctrl_work);
237 fdtv_unregister_rc(fdtv);
238
239 kfree(fdtv);
240 return 0;
241}
242
243static int node_update(struct unit_directory *ud)
244{
245 struct firedtv *fdtv = ud->device.driver_data;
246
247 if (fdtv->isochannel >= 0)
248 cmp_establish_pp_connection(fdtv, fdtv->subunit,
249 fdtv->isochannel);
250 return 0;
251}
252
253static struct hpsb_protocol_driver fdtv_driver = {
254 .name = "firedtv",
255 .update = node_update,
256 .driver = {
257 .probe = node_probe,
258 .remove = node_remove,
259 },
260};
261
262static struct hpsb_highlevel fdtv_highlevel = {
263 .name = "firedtv",
264 .fcp_request = fcp_request,
265};
266
267int __init fdtv_1394_init(struct ieee1394_device_id id_table[])
268{
269 int ret;
270
271 hpsb_register_highlevel(&fdtv_highlevel);
272 fdtv_driver.id_table = id_table;
273 ret = hpsb_register_protocol(&fdtv_driver);
274 if (ret) {
275 printk(KERN_ERR "firedtv: failed to register protocol\n");
276 hpsb_unregister_highlevel(&fdtv_highlevel);
277 }
278 return ret;
279}
280
281void __exit fdtv_1394_exit(void)
282{
283 hpsb_unregister_protocol(&fdtv_driver);
284 hpsb_unregister_highlevel(&fdtv_highlevel);
285}
diff --git a/drivers/media/dvb/firewire/firedtv-avc.c b/drivers/media/dvb/firewire/firedtv-avc.c
new file mode 100644
index 000000000000..b55d9ccaf33e
--- /dev/null
+++ b/drivers/media/dvb/firewire/firedtv-avc.c
@@ -0,0 +1,1315 @@
1/*
2 * FireDTV driver (formerly known as FireSAT)
3 *
4 * Copyright (C) 2004 Andreas Monitzer <andy@monitzer.com>
5 * Copyright (C) 2008 Ben Backx <ben@bbackx.com>
6 * Copyright (C) 2008 Henrik Kurelid <henrik@kurelid.se>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 */
13
14#include <linux/bug.h>
15#include <linux/crc32.h>
16#include <linux/delay.h>
17#include <linux/device.h>
18#include <linux/jiffies.h>
19#include <linux/kernel.h>
20#include <linux/moduleparam.h>
21#include <linux/mutex.h>
22#include <linux/string.h>
23#include <linux/stringify.h>
24#include <linux/wait.h>
25#include <linux/workqueue.h>
26
27#include "firedtv.h"
28
29#define FCP_COMMAND_REGISTER 0xfffff0000b00ULL
30
31#define AVC_CTYPE_CONTROL 0x0
32#define AVC_CTYPE_STATUS 0x1
33#define AVC_CTYPE_NOTIFY 0x3
34
35#define AVC_RESPONSE_ACCEPTED 0x9
36#define AVC_RESPONSE_STABLE 0xc
37#define AVC_RESPONSE_CHANGED 0xd
38#define AVC_RESPONSE_INTERIM 0xf
39
40#define AVC_SUBUNIT_TYPE_TUNER (0x05 << 3)
41#define AVC_SUBUNIT_TYPE_UNIT (0x1f << 3)
42
43#define AVC_OPCODE_VENDOR 0x00
44#define AVC_OPCODE_READ_DESCRIPTOR 0x09
45#define AVC_OPCODE_DSIT 0xc8
46#define AVC_OPCODE_DSD 0xcb
47
48#define DESCRIPTOR_TUNER_STATUS 0x80
49#define DESCRIPTOR_SUBUNIT_IDENTIFIER 0x00
50
51#define SFE_VENDOR_DE_COMPANYID_0 0x00 /* OUI of Digital Everywhere */
52#define SFE_VENDOR_DE_COMPANYID_1 0x12
53#define SFE_VENDOR_DE_COMPANYID_2 0x87
54
55#define SFE_VENDOR_OPCODE_REGISTER_REMOTE_CONTROL 0x0a
56#define SFE_VENDOR_OPCODE_LNB_CONTROL 0x52
57#define SFE_VENDOR_OPCODE_TUNE_QPSK 0x58 /* for DVB-S */
58
59#define SFE_VENDOR_OPCODE_GET_FIRMWARE_VERSION 0x00
60#define SFE_VENDOR_OPCODE_HOST2CA 0x56
61#define SFE_VENDOR_OPCODE_CA2HOST 0x57
62#define SFE_VENDOR_OPCODE_CISTATUS 0x59
63#define SFE_VENDOR_OPCODE_TUNE_QPSK2 0x60 /* for DVB-S2 */
64
65#define SFE_VENDOR_TAG_CA_RESET 0x00
66#define SFE_VENDOR_TAG_CA_APPLICATION_INFO 0x01
67#define SFE_VENDOR_TAG_CA_PMT 0x02
68#define SFE_VENDOR_TAG_CA_DATE_TIME 0x04
69#define SFE_VENDOR_TAG_CA_MMI 0x05
70#define SFE_VENDOR_TAG_CA_ENTER_MENU 0x07
71
72#define EN50221_LIST_MANAGEMENT_ONLY 0x03
73#define EN50221_TAG_APP_INFO 0x9f8021
74#define EN50221_TAG_CA_INFO 0x9f8031
75
76struct avc_command_frame {
77 int length;
78 u8 ctype;
79 u8 subunit;
80 u8 opcode;
81 u8 operand[509];
82};
83
84struct avc_response_frame {
85 int length;
86 u8 response;
87 u8 subunit;
88 u8 opcode;
89 u8 operand[509];
90};
91
92#define AVC_DEBUG_FCP_SUBACTIONS 1
93#define AVC_DEBUG_FCP_PAYLOADS 2
94
95static int avc_debug;
96module_param_named(debug, avc_debug, int, 0644);
97MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
98 ", FCP subactions = " __stringify(AVC_DEBUG_FCP_SUBACTIONS)
99 ", FCP payloads = " __stringify(AVC_DEBUG_FCP_PAYLOADS)
100 ", or all = -1)");
101
102static const char *debug_fcp_ctype(unsigned int ctype)
103{
104 static const char *ctypes[] = {
105 [0x0] = "CONTROL", [0x1] = "STATUS",
106 [0x2] = "SPECIFIC INQUIRY", [0x3] = "NOTIFY",
107 [0x4] = "GENERAL INQUIRY", [0x8] = "NOT IMPLEMENTED",
108 [0x9] = "ACCEPTED", [0xa] = "REJECTED",
109 [0xb] = "IN TRANSITION", [0xc] = "IMPLEMENTED/STABLE",
110 [0xd] = "CHANGED", [0xf] = "INTERIM",
111 };
112 const char *ret = ctype < ARRAY_SIZE(ctypes) ? ctypes[ctype] : NULL;
113
114 return ret ? ret : "?";
115}
116
117static const char *debug_fcp_opcode(unsigned int opcode,
118 const u8 *data, size_t length)
119{
120 switch (opcode) {
121 case AVC_OPCODE_VENDOR: break;
122 case AVC_OPCODE_READ_DESCRIPTOR: return "ReadDescriptor";
123 case AVC_OPCODE_DSIT: return "DirectSelectInfo.Type";
124 case AVC_OPCODE_DSD: return "DirectSelectData";
125 default: return "?";
126 }
127
128 if (length < 7 ||
129 data[3] != SFE_VENDOR_DE_COMPANYID_0 ||
130 data[4] != SFE_VENDOR_DE_COMPANYID_1 ||
131 data[5] != SFE_VENDOR_DE_COMPANYID_2)
132 return "Vendor";
133
134 switch (data[6]) {
135 case SFE_VENDOR_OPCODE_REGISTER_REMOTE_CONTROL: return "RegisterRC";
136 case SFE_VENDOR_OPCODE_LNB_CONTROL: return "LNBControl";
137 case SFE_VENDOR_OPCODE_TUNE_QPSK: return "TuneQPSK";
138 case SFE_VENDOR_OPCODE_HOST2CA: return "Host2CA";
139 case SFE_VENDOR_OPCODE_CA2HOST: return "CA2Host";
140 }
141 return "Vendor";
142}
143
144static void debug_fcp(const u8 *data, size_t length)
145{
146 unsigned int subunit_type, subunit_id, op;
147 const char *prefix = data[0] > 7 ? "FCP <- " : "FCP -> ";
148
149 if (avc_debug & AVC_DEBUG_FCP_SUBACTIONS) {
150 subunit_type = data[1] >> 3;
151 subunit_id = data[1] & 7;
152 op = subunit_type == 0x1e || subunit_id == 5 ? ~0 : data[2];
153 printk(KERN_INFO "%ssu=%x.%x l=%d: %-8s - %s\n",
154 prefix, subunit_type, subunit_id, length,
155 debug_fcp_ctype(data[0]),
156 debug_fcp_opcode(op, data, length));
157 }
158
159 if (avc_debug & AVC_DEBUG_FCP_PAYLOADS)
160 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_NONE, 16, 1,
161 data, length, false);
162}
163
164static int __avc_write(struct firedtv *fdtv,
165 const struct avc_command_frame *c, struct avc_response_frame *r)
166{
167 int err, retry;
168
169 if (r)
170 fdtv->avc_reply_received = false;
171
172 for (retry = 0; retry < 6; retry++) {
173 if (unlikely(avc_debug))
174 debug_fcp(&c->ctype, c->length);
175
176 err = fdtv->backend->write(fdtv, FCP_COMMAND_REGISTER,
177 (void *)&c->ctype, c->length);
178 if (err) {
179 fdtv->avc_reply_received = true;
180 dev_err(fdtv->device, "FCP command write failed\n");
181 return err;
182 }
183
184 if (!r)
185 return 0;
186
187 /*
188 * AV/C specs say that answers should be sent within 150 ms.
189 * Time out after 200 ms.
190 */
191 if (wait_event_timeout(fdtv->avc_wait,
192 fdtv->avc_reply_received,
193 msecs_to_jiffies(200)) != 0) {
194 r->length = fdtv->response_length;
195 memcpy(&r->response, fdtv->response, r->length);
196
197 return 0;
198 }
199 }
200 dev_err(fdtv->device, "FCP response timed out\n");
201 return -ETIMEDOUT;
202}
203
204static int avc_write(struct firedtv *fdtv,
205 const struct avc_command_frame *c, struct avc_response_frame *r)
206{
207 int ret;
208
209 if (mutex_lock_interruptible(&fdtv->avc_mutex))
210 return -EINTR;
211
212 ret = __avc_write(fdtv, c, r);
213
214 mutex_unlock(&fdtv->avc_mutex);
215 return ret;
216}
217
218int avc_recv(struct firedtv *fdtv, void *data, size_t length)
219{
220 struct avc_response_frame *r =
221 data - offsetof(struct avc_response_frame, response);
222
223 if (unlikely(avc_debug))
224 debug_fcp(data, length);
225
226 if (length >= 8 &&
227 r->operand[0] == SFE_VENDOR_DE_COMPANYID_0 &&
228 r->operand[1] == SFE_VENDOR_DE_COMPANYID_1 &&
229 r->operand[2] == SFE_VENDOR_DE_COMPANYID_2 &&
230 r->operand[3] == SFE_VENDOR_OPCODE_REGISTER_REMOTE_CONTROL) {
231 if (r->response == AVC_RESPONSE_CHANGED) {
232 fdtv_handle_rc(fdtv,
233 r->operand[4] << 8 | r->operand[5]);
234 schedule_work(&fdtv->remote_ctrl_work);
235 } else if (r->response != AVC_RESPONSE_INTERIM) {
236 dev_info(fdtv->device,
237 "remote control result = %d\n", r->response);
238 }
239 return 0;
240 }
241
242 if (fdtv->avc_reply_received) {
243 dev_err(fdtv->device, "out-of-order AVC response, ignored\n");
244 return -EIO;
245 }
246
247 memcpy(fdtv->response, data, length);
248 fdtv->response_length = length;
249
250 fdtv->avc_reply_received = true;
251 wake_up(&fdtv->avc_wait);
252
253 return 0;
254}
255
256/*
257 * tuning command for setting the relative LNB frequency
258 * (not supported by the AVC standard)
259 */
260static void avc_tuner_tuneqpsk(struct firedtv *fdtv,
261 struct dvb_frontend_parameters *params,
262 struct avc_command_frame *c)
263{
264 c->opcode = AVC_OPCODE_VENDOR;
265
266 c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
267 c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
268 c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
269 c->operand[3] = SFE_VENDOR_OPCODE_TUNE_QPSK;
270
271 c->operand[4] = (params->frequency >> 24) & 0xff;
272 c->operand[5] = (params->frequency >> 16) & 0xff;
273 c->operand[6] = (params->frequency >> 8) & 0xff;
274 c->operand[7] = params->frequency & 0xff;
275
276 c->operand[8] = ((params->u.qpsk.symbol_rate / 1000) >> 8) & 0xff;
277 c->operand[9] = (params->u.qpsk.symbol_rate / 1000) & 0xff;
278
279 switch (params->u.qpsk.fec_inner) {
280 case FEC_1_2: c->operand[10] = 0x1; break;
281 case FEC_2_3: c->operand[10] = 0x2; break;
282 case FEC_3_4: c->operand[10] = 0x3; break;
283 case FEC_5_6: c->operand[10] = 0x4; break;
284 case FEC_7_8: c->operand[10] = 0x5; break;
285 case FEC_4_5:
286 case FEC_8_9:
287 case FEC_AUTO:
288 default: c->operand[10] = 0x0;
289 }
290
291 if (fdtv->voltage == 0xff)
292 c->operand[11] = 0xff;
293 else if (fdtv->voltage == SEC_VOLTAGE_18) /* polarisation */
294 c->operand[11] = 0;
295 else
296 c->operand[11] = 1;
297
298 if (fdtv->tone == 0xff)
299 c->operand[12] = 0xff;
300 else if (fdtv->tone == SEC_TONE_ON) /* band */
301 c->operand[12] = 1;
302 else
303 c->operand[12] = 0;
304
305 if (fdtv->type == FIREDTV_DVB_S2) {
306 c->operand[13] = 0x1;
307 c->operand[14] = 0xff;
308 c->operand[15] = 0xff;
309 c->length = 20;
310 } else {
311 c->length = 16;
312 }
313}
314
315static void avc_tuner_dsd_dvb_c(struct dvb_frontend_parameters *params,
316 struct avc_command_frame *c)
317{
318 c->opcode = AVC_OPCODE_DSD;
319
320 c->operand[0] = 0; /* source plug */
321 c->operand[1] = 0xd2; /* subfunction replace */
322 c->operand[2] = 0x20; /* system id = DVB */
323 c->operand[3] = 0x00; /* antenna number */
324 c->operand[4] = 0x11; /* system_specific_multiplex selection_length */
325
326 /* multiplex_valid_flags, high byte */
327 c->operand[5] = 0 << 7 /* reserved */
328 | 0 << 6 /* Polarisation */
329 | 0 << 5 /* Orbital_Pos */
330 | 1 << 4 /* Frequency */
331 | 1 << 3 /* Symbol_Rate */
332 | 0 << 2 /* FEC_outer */
333 | (params->u.qam.fec_inner != FEC_AUTO ? 1 << 1 : 0)
334 | (params->u.qam.modulation != QAM_AUTO ? 1 << 0 : 0);
335
336 /* multiplex_valid_flags, low byte */
337 c->operand[6] = 0 << 7 /* NetworkID */
338 | 0 << 0 /* reserved */ ;
339
340 c->operand[7] = 0x00;
341 c->operand[8] = 0x00;
342 c->operand[9] = 0x00;
343 c->operand[10] = 0x00;
344
345 c->operand[11] = (((params->frequency / 4000) >> 16) & 0xff) | (2 << 6);
346 c->operand[12] = ((params->frequency / 4000) >> 8) & 0xff;
347 c->operand[13] = (params->frequency / 4000) & 0xff;
348 c->operand[14] = ((params->u.qpsk.symbol_rate / 1000) >> 12) & 0xff;
349 c->operand[15] = ((params->u.qpsk.symbol_rate / 1000) >> 4) & 0xff;
350 c->operand[16] = ((params->u.qpsk.symbol_rate / 1000) << 4) & 0xf0;
351 c->operand[17] = 0x00;
352
353 switch (params->u.qpsk.fec_inner) {
354 case FEC_1_2: c->operand[18] = 0x1; break;
355 case FEC_2_3: c->operand[18] = 0x2; break;
356 case FEC_3_4: c->operand[18] = 0x3; break;
357 case FEC_5_6: c->operand[18] = 0x4; break;
358 case FEC_7_8: c->operand[18] = 0x5; break;
359 case FEC_8_9: c->operand[18] = 0x6; break;
360 case FEC_4_5: c->operand[18] = 0x8; break;
361 case FEC_AUTO:
362 default: c->operand[18] = 0x0;
363 }
364
365 switch (params->u.qam.modulation) {
366 case QAM_16: c->operand[19] = 0x08; break;
367 case QAM_32: c->operand[19] = 0x10; break;
368 case QAM_64: c->operand[19] = 0x18; break;
369 case QAM_128: c->operand[19] = 0x20; break;
370 case QAM_256: c->operand[19] = 0x28; break;
371 case QAM_AUTO:
372 default: c->operand[19] = 0x00;
373 }
374
375 c->operand[20] = 0x00;
376 c->operand[21] = 0x00;
377 /* Nr_of_dsd_sel_specs = 0 -> no PIDs are transmitted */
378 c->operand[22] = 0x00;
379
380 c->length = 28;
381}
382
383static void avc_tuner_dsd_dvb_t(struct dvb_frontend_parameters *params,
384 struct avc_command_frame *c)
385{
386 struct dvb_ofdm_parameters *ofdm = &params->u.ofdm;
387
388 c->opcode = AVC_OPCODE_DSD;
389
390 c->operand[0] = 0; /* source plug */
391 c->operand[1] = 0xd2; /* subfunction replace */
392 c->operand[2] = 0x20; /* system id = DVB */
393 c->operand[3] = 0x00; /* antenna number */
394 c->operand[4] = 0x0c; /* system_specific_multiplex selection_length */
395
396 /* multiplex_valid_flags, high byte */
397 c->operand[5] =
398 0 << 7 /* reserved */
399 | 1 << 6 /* CenterFrequency */
400 | (ofdm->bandwidth != BANDWIDTH_AUTO ? 1 << 5 : 0)
401 | (ofdm->constellation != QAM_AUTO ? 1 << 4 : 0)
402 | (ofdm->hierarchy_information != HIERARCHY_AUTO ? 1 << 3 : 0)
403 | (ofdm->code_rate_HP != FEC_AUTO ? 1 << 2 : 0)
404 | (ofdm->code_rate_LP != FEC_AUTO ? 1 << 1 : 0)
405 | (ofdm->guard_interval != GUARD_INTERVAL_AUTO ? 1 << 0 : 0);
406
407 /* multiplex_valid_flags, low byte */
408 c->operand[6] =
409 0 << 7 /* NetworkID */
410 | (ofdm->transmission_mode != TRANSMISSION_MODE_AUTO ? 1 << 6 : 0)
411 | 0 << 5 /* OtherFrequencyFlag */
412 | 0 << 0 /* reserved */ ;
413
414 c->operand[7] = 0x0;
415 c->operand[8] = (params->frequency / 10) >> 24;
416 c->operand[9] = ((params->frequency / 10) >> 16) & 0xff;
417 c->operand[10] = ((params->frequency / 10) >> 8) & 0xff;
418 c->operand[11] = (params->frequency / 10) & 0xff;
419
420 switch (ofdm->bandwidth) {
421 case BANDWIDTH_7_MHZ: c->operand[12] = 0x20; break;
422 case BANDWIDTH_8_MHZ:
423 case BANDWIDTH_6_MHZ: /* not defined by AVC spec */
424 case BANDWIDTH_AUTO:
425 default: c->operand[12] = 0x00;
426 }
427
428 switch (ofdm->constellation) {
429 case QAM_16: c->operand[13] = 1 << 6; break;
430 case QAM_64: c->operand[13] = 2 << 6; break;
431 case QPSK:
432 default: c->operand[13] = 0x00;
433 }
434
435 switch (ofdm->hierarchy_information) {
436 case HIERARCHY_1: c->operand[13] |= 1 << 3; break;
437 case HIERARCHY_2: c->operand[13] |= 2 << 3; break;
438 case HIERARCHY_4: c->operand[13] |= 3 << 3; break;
439 case HIERARCHY_AUTO:
440 case HIERARCHY_NONE:
441 default: break;
442 }
443
444 switch (ofdm->code_rate_HP) {
445 case FEC_2_3: c->operand[13] |= 1; break;
446 case FEC_3_4: c->operand[13] |= 2; break;
447 case FEC_5_6: c->operand[13] |= 3; break;
448 case FEC_7_8: c->operand[13] |= 4; break;
449 case FEC_1_2:
450 default: break;
451 }
452
453 switch (ofdm->code_rate_LP) {
454 case FEC_2_3: c->operand[14] = 1 << 5; break;
455 case FEC_3_4: c->operand[14] = 2 << 5; break;
456 case FEC_5_6: c->operand[14] = 3 << 5; break;
457 case FEC_7_8: c->operand[14] = 4 << 5; break;
458 case FEC_1_2:
459 default: c->operand[14] = 0x00; break;
460 }
461
462 switch (ofdm->guard_interval) {
463 case GUARD_INTERVAL_1_16: c->operand[14] |= 1 << 3; break;
464 case GUARD_INTERVAL_1_8: c->operand[14] |= 2 << 3; break;
465 case GUARD_INTERVAL_1_4: c->operand[14] |= 3 << 3; break;
466 case GUARD_INTERVAL_1_32:
467 case GUARD_INTERVAL_AUTO:
468 default: break;
469 }
470
471 switch (ofdm->transmission_mode) {
472 case TRANSMISSION_MODE_8K: c->operand[14] |= 1 << 1; break;
473 case TRANSMISSION_MODE_2K:
474 case TRANSMISSION_MODE_AUTO:
475 default: break;
476 }
477
478 c->operand[15] = 0x00; /* network_ID[0] */
479 c->operand[16] = 0x00; /* network_ID[1] */
480 /* Nr_of_dsd_sel_specs = 0 -> no PIDs are transmitted */
481 c->operand[17] = 0x00;
482
483 c->length = 24;
484}
485
486int avc_tuner_dsd(struct firedtv *fdtv,
487 struct dvb_frontend_parameters *params)
488{
489 char buffer[sizeof(struct avc_command_frame)];
490 struct avc_command_frame *c = (void *)buffer;
491 struct avc_response_frame *r = (void *)buffer; /* FIXME: unused */
492
493 memset(c, 0, sizeof(*c));
494
495 c->ctype = AVC_CTYPE_CONTROL;
496 c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
497
498 switch (fdtv->type) {
499 case FIREDTV_DVB_S:
500 case FIREDTV_DVB_S2: avc_tuner_tuneqpsk(fdtv, params, c); break;
501 case FIREDTV_DVB_C: avc_tuner_dsd_dvb_c(params, c); break;
502 case FIREDTV_DVB_T: avc_tuner_dsd_dvb_t(params, c); break;
503 default:
504 BUG();
505 }
506
507 if (avc_write(fdtv, c, r) < 0)
508 return -EIO;
509
510 msleep(500);
511#if 0
512 /* FIXME: */
513 /* u8 *status was an out-parameter of avc_tuner_dsd, unused by caller */
514 if (status)
515 *status = r->operand[2];
516#endif
517 return 0;
518}
519
520int avc_tuner_set_pids(struct firedtv *fdtv, unsigned char pidc, u16 pid[])
521{
522 char buffer[sizeof(struct avc_command_frame)];
523 struct avc_command_frame *c = (void *)buffer;
524 struct avc_response_frame *r = (void *)buffer; /* FIXME: unused */
525 int pos, k;
526
527 if (pidc > 16 && pidc != 0xff)
528 return -EINVAL;
529
530 memset(c, 0, sizeof(*c));
531
532 c->ctype = AVC_CTYPE_CONTROL;
533 c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
534 c->opcode = AVC_OPCODE_DSD;
535
536 c->operand[0] = 0; /* source plug */
537 c->operand[1] = 0xd2; /* subfunction replace */
538 c->operand[2] = 0x20; /* system id = DVB */
539 c->operand[3] = 0x00; /* antenna number */
540 c->operand[4] = 0x00; /* system_specific_multiplex selection_length */
541 c->operand[5] = pidc; /* Nr_of_dsd_sel_specs */
542
543 pos = 6;
544 if (pidc != 0xff)
545 for (k = 0; k < pidc; k++) {
546 c->operand[pos++] = 0x13; /* flowfunction relay */
547 c->operand[pos++] = 0x80; /* dsd_sel_spec_valid_flags -> PID */
548 c->operand[pos++] = (pid[k] >> 8) & 0x1f;
549 c->operand[pos++] = pid[k] & 0xff;
550 c->operand[pos++] = 0x00; /* tableID */
551 c->operand[pos++] = 0x00; /* filter_length */
552 }
553
554 c->length = ALIGN(3 + pos, 4);
555
556 if (avc_write(fdtv, c, r) < 0)
557 return -EIO;
558
559 msleep(50);
560 return 0;
561}
562
563int avc_tuner_get_ts(struct firedtv *fdtv)
564{
565 char buffer[sizeof(struct avc_command_frame)];
566 struct avc_command_frame *c = (void *)buffer;
567 struct avc_response_frame *r = (void *)buffer; /* FIXME: unused */
568 int sl;
569
570 memset(c, 0, sizeof(*c));
571
572 c->ctype = AVC_CTYPE_CONTROL;
573 c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
574 c->opcode = AVC_OPCODE_DSIT;
575
576 sl = fdtv->type == FIREDTV_DVB_T ? 0x0c : 0x11;
577
578 c->operand[0] = 0; /* source plug */
579 c->operand[1] = 0xd2; /* subfunction replace */
580 c->operand[2] = 0xff; /* status */
581 c->operand[3] = 0x20; /* system id = DVB */
582 c->operand[4] = 0x00; /* antenna number */
583 c->operand[5] = 0x0; /* system_specific_search_flags */
584 c->operand[6] = sl; /* system_specific_multiplex selection_length */
585 c->operand[7] = 0x00; /* valid_flags [0] */
586 c->operand[8] = 0x00; /* valid_flags [1] */
587 c->operand[7 + sl] = 0x00; /* nr_of_dsit_sel_specs (always 0) */
588
589 c->length = fdtv->type == FIREDTV_DVB_T ? 24 : 28;
590
591 if (avc_write(fdtv, c, r) < 0)
592 return -EIO;
593
594 msleep(250);
595 return 0;
596}
597
598int avc_identify_subunit(struct firedtv *fdtv)
599{
600 char buffer[sizeof(struct avc_command_frame)];
601 struct avc_command_frame *c = (void *)buffer;
602 struct avc_response_frame *r = (void *)buffer;
603
604 memset(c, 0, sizeof(*c));
605
606 c->ctype = AVC_CTYPE_CONTROL;
607 c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
608 c->opcode = AVC_OPCODE_READ_DESCRIPTOR;
609
610 c->operand[0] = DESCRIPTOR_SUBUNIT_IDENTIFIER;
611 c->operand[1] = 0xff;
612 c->operand[2] = 0x00;
613 c->operand[3] = 0x00; /* length highbyte */
614 c->operand[4] = 0x08; /* length lowbyte */
615 c->operand[5] = 0x00; /* offset highbyte */
616 c->operand[6] = 0x0d; /* offset lowbyte */
617
618 c->length = 12;
619
620 if (avc_write(fdtv, c, r) < 0)
621 return -EIO;
622
623 if ((r->response != AVC_RESPONSE_STABLE &&
624 r->response != AVC_RESPONSE_ACCEPTED) ||
625 (r->operand[3] << 8) + r->operand[4] != 8) {
626 dev_err(fdtv->device, "cannot read subunit identifier\n");
627 return -EINVAL;
628 }
629 return 0;
630}
631
632#define SIZEOF_ANTENNA_INPUT_INFO 22
633
634int avc_tuner_status(struct firedtv *fdtv, struct firedtv_tuner_status *stat)
635{
636 char buffer[sizeof(struct avc_command_frame)];
637 struct avc_command_frame *c = (void *)buffer;
638 struct avc_response_frame *r = (void *)buffer;
639 int length;
640
641 memset(c, 0, sizeof(*c));
642
643 c->ctype = AVC_CTYPE_CONTROL;
644 c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
645 c->opcode = AVC_OPCODE_READ_DESCRIPTOR;
646
647 c->operand[0] = DESCRIPTOR_TUNER_STATUS;
648 c->operand[1] = 0xff; /* read_result_status */
649 c->operand[2] = 0x00; /* reserved */
650 c->operand[3] = 0; /* SIZEOF_ANTENNA_INPUT_INFO >> 8; */
651 c->operand[4] = 0; /* SIZEOF_ANTENNA_INPUT_INFO & 0xff; */
652 c->operand[5] = 0x00;
653 c->operand[6] = 0x00;
654
655 c->length = 12;
656
657 if (avc_write(fdtv, c, r) < 0)
658 return -EIO;
659
660 if (r->response != AVC_RESPONSE_STABLE &&
661 r->response != AVC_RESPONSE_ACCEPTED) {
662 dev_err(fdtv->device, "cannot read tuner status\n");
663 return -EINVAL;
664 }
665
666 length = r->operand[9];
667 if (r->operand[1] != 0x10 || length != SIZEOF_ANTENNA_INPUT_INFO) {
668 dev_err(fdtv->device, "got invalid tuner status\n");
669 return -EINVAL;
670 }
671
672 stat->active_system = r->operand[10];
673 stat->searching = r->operand[11] >> 7 & 1;
674 stat->moving = r->operand[11] >> 6 & 1;
675 stat->no_rf = r->operand[11] >> 5 & 1;
676 stat->input = r->operand[12] >> 7 & 1;
677 stat->selected_antenna = r->operand[12] & 0x7f;
678 stat->ber = r->operand[13] << 24 |
679 r->operand[14] << 16 |
680 r->operand[15] << 8 |
681 r->operand[16];
682 stat->signal_strength = r->operand[17];
683 stat->raster_frequency = r->operand[18] >> 6 & 2;
684 stat->rf_frequency = (r->operand[18] & 0x3f) << 16 |
685 r->operand[19] << 8 |
686 r->operand[20];
687 stat->man_dep_info_length = r->operand[21];
688 stat->front_end_error = r->operand[22] >> 4 & 1;
689 stat->antenna_error = r->operand[22] >> 3 & 1;
690 stat->front_end_power_status = r->operand[22] >> 1 & 1;
691 stat->power_supply = r->operand[22] & 1;
692 stat->carrier_noise_ratio = r->operand[23] << 8 |
693 r->operand[24];
694 stat->power_supply_voltage = r->operand[27];
695 stat->antenna_voltage = r->operand[28];
696 stat->firewire_bus_voltage = r->operand[29];
697 stat->ca_mmi = r->operand[30] & 1;
698 stat->ca_pmt_reply = r->operand[31] >> 7 & 1;
699 stat->ca_date_time_request = r->operand[31] >> 6 & 1;
700 stat->ca_application_info = r->operand[31] >> 5 & 1;
701 stat->ca_module_present_status = r->operand[31] >> 4 & 1;
702 stat->ca_dvb_flag = r->operand[31] >> 3 & 1;
703 stat->ca_error_flag = r->operand[31] >> 2 & 1;
704 stat->ca_initialization_status = r->operand[31] >> 1 & 1;
705
706 return 0;
707}
708
709int avc_lnb_control(struct firedtv *fdtv, char voltage, char burst,
710 char conttone, char nrdiseq,
711 struct dvb_diseqc_master_cmd *diseqcmd)
712{
713 char buffer[sizeof(struct avc_command_frame)];
714 struct avc_command_frame *c = (void *)buffer;
715 struct avc_response_frame *r = (void *)buffer;
716 int i, j, k;
717
718 memset(c, 0, sizeof(*c));
719
720 c->ctype = AVC_CTYPE_CONTROL;
721 c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
722 c->opcode = AVC_OPCODE_VENDOR;
723
724 c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
725 c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
726 c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
727 c->operand[3] = SFE_VENDOR_OPCODE_LNB_CONTROL;
728
729 c->operand[4] = voltage;
730 c->operand[5] = nrdiseq;
731
732 i = 6;
733
734 for (j = 0; j < nrdiseq; j++) {
735 c->operand[i++] = diseqcmd[j].msg_len;
736
737 for (k = 0; k < diseqcmd[j].msg_len; k++)
738 c->operand[i++] = diseqcmd[j].msg[k];
739 }
740
741 c->operand[i++] = burst;
742 c->operand[i++] = conttone;
743
744 c->length = ALIGN(3 + i, 4);
745
746 if (avc_write(fdtv, c, r) < 0)
747 return -EIO;
748
749 if (r->response != AVC_RESPONSE_ACCEPTED) {
750 dev_err(fdtv->device, "LNB control failed\n");
751 return -EINVAL;
752 }
753
754 return 0;
755}
756
757int avc_register_remote_control(struct firedtv *fdtv)
758{
759 char buffer[sizeof(struct avc_command_frame)];
760 struct avc_command_frame *c = (void *)buffer;
761
762 memset(c, 0, sizeof(*c));
763
764 c->ctype = AVC_CTYPE_NOTIFY;
765 c->subunit = AVC_SUBUNIT_TYPE_UNIT | 7;
766 c->opcode = AVC_OPCODE_VENDOR;
767
768 c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
769 c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
770 c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
771 c->operand[3] = SFE_VENDOR_OPCODE_REGISTER_REMOTE_CONTROL;
772
773 c->length = 8;
774
775 return avc_write(fdtv, c, NULL);
776}
777
778void avc_remote_ctrl_work(struct work_struct *work)
779{
780 struct firedtv *fdtv =
781 container_of(work, struct firedtv, remote_ctrl_work);
782
783 /* Should it be rescheduled in failure cases? */
784 avc_register_remote_control(fdtv);
785}
786
787#if 0 /* FIXME: unused */
788int avc_tuner_host2ca(struct firedtv *fdtv)
789{
790 char buffer[sizeof(struct avc_command_frame)];
791 struct avc_command_frame *c = (void *)buffer;
792 struct avc_response_frame *r = (void *)buffer; /* FIXME: unused */
793
794 memset(c, 0, sizeof(*c));
795
796 c->ctype = AVC_CTYPE_CONTROL;
797 c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
798 c->opcode = AVC_OPCODE_VENDOR;
799
800 c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
801 c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
802 c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
803 c->operand[3] = SFE_VENDOR_OPCODE_HOST2CA;
804 c->operand[4] = 0; /* slot */
805 c->operand[5] = SFE_VENDOR_TAG_CA_APPLICATION_INFO; /* ca tag */
806 c->operand[6] = 0; /* more/last */
807 c->operand[7] = 0; /* length */
808
809 c->length = 12;
810
811 if (avc_write(fdtv, c, r) < 0)
812 return -EIO;
813
814 return 0;
815}
816#endif
817
818static int get_ca_object_pos(struct avc_response_frame *r)
819{
820 int length = 1;
821
822 /* Check length of length field */
823 if (r->operand[7] & 0x80)
824 length = (r->operand[7] & 0x7f) + 1;
825 return length + 7;
826}
827
828static int get_ca_object_length(struct avc_response_frame *r)
829{
830#if 0 /* FIXME: unused */
831 int size = 0;
832 int i;
833
834 if (r->operand[7] & 0x80)
835 for (i = 0; i < (r->operand[7] & 0x7f); i++) {
836 size <<= 8;
837 size += r->operand[8 + i];
838 }
839#endif
840 return r->operand[7];
841}
842
843int avc_ca_app_info(struct firedtv *fdtv, char *app_info, unsigned int *len)
844{
845 char buffer[sizeof(struct avc_command_frame)];
846 struct avc_command_frame *c = (void *)buffer;
847 struct avc_response_frame *r = (void *)buffer;
848 int pos;
849
850 memset(c, 0, sizeof(*c));
851
852 c->ctype = AVC_CTYPE_STATUS;
853 c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
854 c->opcode = AVC_OPCODE_VENDOR;
855
856 c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
857 c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
858 c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
859 c->operand[3] = SFE_VENDOR_OPCODE_CA2HOST;
860 c->operand[4] = 0; /* slot */
861 c->operand[5] = SFE_VENDOR_TAG_CA_APPLICATION_INFO; /* ca tag */
862
863 c->length = 12;
864
865 if (avc_write(fdtv, c, r) < 0)
866 return -EIO;
867
868 /* FIXME: check response code and validate response data */
869
870 pos = get_ca_object_pos(r);
871 app_info[0] = (EN50221_TAG_APP_INFO >> 16) & 0xff;
872 app_info[1] = (EN50221_TAG_APP_INFO >> 8) & 0xff;
873 app_info[2] = (EN50221_TAG_APP_INFO >> 0) & 0xff;
874 app_info[3] = 6 + r->operand[pos + 4];
875 app_info[4] = 0x01;
876 memcpy(&app_info[5], &r->operand[pos], 5 + r->operand[pos + 4]);
877 *len = app_info[3] + 4;
878
879 return 0;
880}
881
882int avc_ca_info(struct firedtv *fdtv, char *app_info, unsigned int *len)
883{
884 char buffer[sizeof(struct avc_command_frame)];
885 struct avc_command_frame *c = (void *)buffer;
886 struct avc_response_frame *r = (void *)buffer;
887 int pos;
888
889 memset(c, 0, sizeof(*c));
890
891 c->ctype = AVC_CTYPE_STATUS;
892 c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
893 c->opcode = AVC_OPCODE_VENDOR;
894
895 c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
896 c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
897 c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
898 c->operand[3] = SFE_VENDOR_OPCODE_CA2HOST;
899 c->operand[4] = 0; /* slot */
900 c->operand[5] = SFE_VENDOR_TAG_CA_APPLICATION_INFO; /* ca tag */
901
902 c->length = 12;
903
904 if (avc_write(fdtv, c, r) < 0)
905 return -EIO;
906
907 pos = get_ca_object_pos(r);
908 app_info[0] = (EN50221_TAG_CA_INFO >> 16) & 0xff;
909 app_info[1] = (EN50221_TAG_CA_INFO >> 8) & 0xff;
910 app_info[2] = (EN50221_TAG_CA_INFO >> 0) & 0xff;
911 app_info[3] = 2;
912 app_info[4] = r->operand[pos + 0];
913 app_info[5] = r->operand[pos + 1];
914 *len = app_info[3] + 4;
915
916 return 0;
917}
918
919int avc_ca_reset(struct firedtv *fdtv)
920{
921 char buffer[sizeof(struct avc_command_frame)];
922 struct avc_command_frame *c = (void *)buffer;
923 struct avc_response_frame *r = (void *)buffer; /* FIXME: unused */
924
925 memset(c, 0, sizeof(*c));
926
927 c->ctype = AVC_CTYPE_CONTROL;
928 c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
929 c->opcode = AVC_OPCODE_VENDOR;
930
931 c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
932 c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
933 c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
934 c->operand[3] = SFE_VENDOR_OPCODE_HOST2CA;
935 c->operand[4] = 0; /* slot */
936 c->operand[5] = SFE_VENDOR_TAG_CA_RESET; /* ca tag */
937 c->operand[6] = 0; /* more/last */
938 c->operand[7] = 1; /* length */
939 c->operand[8] = 0; /* force hardware reset */
940
941 c->length = 12;
942
943 if (avc_write(fdtv, c, r) < 0)
944 return -EIO;
945
946 return 0;
947}
948
949int avc_ca_pmt(struct firedtv *fdtv, char *msg, int length)
950{
951 char buffer[sizeof(struct avc_command_frame)];
952 struct avc_command_frame *c = (void *)buffer;
953 struct avc_response_frame *r = (void *)buffer;
954 int list_management;
955 int program_info_length;
956 int pmt_cmd_id;
957 int read_pos;
958 int write_pos;
959 int es_info_length;
960 int crc32_csum;
961
962 memset(c, 0, sizeof(*c));
963
964 c->ctype = AVC_CTYPE_CONTROL;
965 c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
966 c->opcode = AVC_OPCODE_VENDOR;
967
968 if (msg[0] != EN50221_LIST_MANAGEMENT_ONLY) {
969 dev_info(fdtv->device, "forcing list_management to ONLY\n");
970 msg[0] = EN50221_LIST_MANAGEMENT_ONLY;
971 }
972 /* We take the cmd_id from the programme level only! */
973 list_management = msg[0];
974 program_info_length = ((msg[4] & 0x0f) << 8) + msg[5];
975 if (program_info_length > 0)
976 program_info_length--; /* Remove pmt_cmd_id */
977 pmt_cmd_id = msg[6];
978
979 c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
980 c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
981 c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
982 c->operand[3] = SFE_VENDOR_OPCODE_HOST2CA;
983 c->operand[4] = 0; /* slot */
984 c->operand[5] = SFE_VENDOR_TAG_CA_PMT; /* ca tag */
985 c->operand[6] = 0; /* more/last */
986 /* c->operand[7] = XXXprogram_info_length + 17; */ /* length */
987 c->operand[8] = list_management;
988 c->operand[9] = 0x01; /* pmt_cmd=OK_descramble */
989
990 /* TS program map table */
991
992 c->operand[10] = 0x02; /* Table id=2 */
993 c->operand[11] = 0x80; /* Section syntax + length */
994 /* c->operand[12] = XXXprogram_info_length + 12; */
995 c->operand[13] = msg[1]; /* Program number */
996 c->operand[14] = msg[2];
997 c->operand[15] = 0x01; /* Version number=0 + current/next=1 */
998 c->operand[16] = 0x00; /* Section number=0 */
999 c->operand[17] = 0x00; /* Last section number=0 */
1000 c->operand[18] = 0x1f; /* PCR_PID=1FFF */
1001 c->operand[19] = 0xff;
1002 c->operand[20] = (program_info_length >> 8); /* Program info length */
1003 c->operand[21] = (program_info_length & 0xff);
1004
1005 /* CA descriptors at programme level */
1006 read_pos = 6;
1007 write_pos = 22;
1008 if (program_info_length > 0) {
1009 pmt_cmd_id = msg[read_pos++];
1010 if (pmt_cmd_id != 1 && pmt_cmd_id != 4)
1011 dev_err(fdtv->device,
1012 "invalid pmt_cmd_id %d\n", pmt_cmd_id);
1013
1014 memcpy(&c->operand[write_pos], &msg[read_pos],
1015 program_info_length);
1016 read_pos += program_info_length;
1017 write_pos += program_info_length;
1018 }
1019 while (read_pos < length) {
1020 c->operand[write_pos++] = msg[read_pos++];
1021 c->operand[write_pos++] = msg[read_pos++];
1022 c->operand[write_pos++] = msg[read_pos++];
1023 es_info_length =
1024 ((msg[read_pos] & 0x0f) << 8) + msg[read_pos + 1];
1025 read_pos += 2;
1026 if (es_info_length > 0)
1027 es_info_length--; /* Remove pmt_cmd_id */
1028 c->operand[write_pos++] = es_info_length >> 8;
1029 c->operand[write_pos++] = es_info_length & 0xff;
1030 if (es_info_length > 0) {
1031 pmt_cmd_id = msg[read_pos++];
1032 if (pmt_cmd_id != 1 && pmt_cmd_id != 4)
1033 dev_err(fdtv->device, "invalid pmt_cmd_id %d "
1034 "at stream level\n", pmt_cmd_id);
1035
1036 memcpy(&c->operand[write_pos], &msg[read_pos],
1037 es_info_length);
1038 read_pos += es_info_length;
1039 write_pos += es_info_length;
1040 }
1041 }
1042
1043 /* CRC */
1044 c->operand[write_pos++] = 0x00;
1045 c->operand[write_pos++] = 0x00;
1046 c->operand[write_pos++] = 0x00;
1047 c->operand[write_pos++] = 0x00;
1048
1049 c->operand[7] = write_pos - 8;
1050 c->operand[12] = write_pos - 13;
1051
1052 crc32_csum = crc32_be(0, &c->operand[10], c->operand[12] - 1);
1053 c->operand[write_pos - 4] = (crc32_csum >> 24) & 0xff;
1054 c->operand[write_pos - 3] = (crc32_csum >> 16) & 0xff;
1055 c->operand[write_pos - 2] = (crc32_csum >> 8) & 0xff;
1056 c->operand[write_pos - 1] = (crc32_csum >> 0) & 0xff;
1057
1058 c->length = ALIGN(3 + write_pos, 4);
1059
1060 if (avc_write(fdtv, c, r) < 0)
1061 return -EIO;
1062
1063 if (r->response != AVC_RESPONSE_ACCEPTED) {
1064 dev_err(fdtv->device,
1065 "CA PMT failed with response 0x%x\n", r->response);
1066 return -EFAULT;
1067 }
1068
1069 return 0;
1070}
1071
1072int avc_ca_get_time_date(struct firedtv *fdtv, int *interval)
1073{
1074 char buffer[sizeof(struct avc_command_frame)];
1075 struct avc_command_frame *c = (void *)buffer;
1076 struct avc_response_frame *r = (void *)buffer;
1077
1078 memset(c, 0, sizeof(*c));
1079
1080 c->ctype = AVC_CTYPE_STATUS;
1081 c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
1082 c->opcode = AVC_OPCODE_VENDOR;
1083
1084 c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
1085 c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
1086 c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
1087 c->operand[3] = SFE_VENDOR_OPCODE_CA2HOST;
1088 c->operand[4] = 0; /* slot */
1089 c->operand[5] = SFE_VENDOR_TAG_CA_DATE_TIME; /* ca tag */
1090 c->operand[6] = 0; /* more/last */
1091 c->operand[7] = 0; /* length */
1092
1093 c->length = 12;
1094
1095 if (avc_write(fdtv, c, r) < 0)
1096 return -EIO;
1097
1098 /* FIXME: check response code and validate response data */
1099
1100 *interval = r->operand[get_ca_object_pos(r)];
1101
1102 return 0;
1103}
1104
1105int avc_ca_enter_menu(struct firedtv *fdtv)
1106{
1107 char buffer[sizeof(struct avc_command_frame)];
1108 struct avc_command_frame *c = (void *)buffer;
1109 struct avc_response_frame *r = (void *)buffer; /* FIXME: unused */
1110
1111 memset(c, 0, sizeof(*c));
1112
1113 c->ctype = AVC_CTYPE_STATUS;
1114 c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
1115 c->opcode = AVC_OPCODE_VENDOR;
1116
1117 c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
1118 c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
1119 c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
1120 c->operand[3] = SFE_VENDOR_OPCODE_HOST2CA;
1121 c->operand[4] = 0; /* slot */
1122 c->operand[5] = SFE_VENDOR_TAG_CA_ENTER_MENU;
1123 c->operand[6] = 0; /* more/last */
1124 c->operand[7] = 0; /* length */
1125
1126 c->length = 12;
1127
1128 if (avc_write(fdtv, c, r) < 0)
1129 return -EIO;
1130
1131 return 0;
1132}
1133
1134int avc_ca_get_mmi(struct firedtv *fdtv, char *mmi_object, unsigned int *len)
1135{
1136 char buffer[sizeof(struct avc_command_frame)];
1137 struct avc_command_frame *c = (void *)buffer;
1138 struct avc_response_frame *r = (void *)buffer;
1139
1140 memset(c, 0, sizeof(*c));
1141
1142 c->ctype = AVC_CTYPE_STATUS;
1143 c->subunit = AVC_SUBUNIT_TYPE_TUNER | fdtv->subunit;
1144 c->opcode = AVC_OPCODE_VENDOR;
1145
1146 c->operand[0] = SFE_VENDOR_DE_COMPANYID_0;
1147 c->operand[1] = SFE_VENDOR_DE_COMPANYID_1;
1148 c->operand[2] = SFE_VENDOR_DE_COMPANYID_2;
1149 c->operand[3] = SFE_VENDOR_OPCODE_CA2HOST;
1150 c->operand[4] = 0; /* slot */
1151 c->operand[5] = SFE_VENDOR_TAG_CA_MMI;
1152 c->operand[6] = 0; /* more/last */
1153 c->operand[7] = 0; /* length */
1154
1155 c->length = 12;
1156
1157 if (avc_write(fdtv, c, r) < 0)
1158 return -EIO;
1159
1160 /* FIXME: check response code and validate response data */
1161
1162 *len = get_ca_object_length(r);
1163 memcpy(mmi_object, &r->operand[get_ca_object_pos(r)], *len);
1164
1165 return 0;
1166}
1167
1168#define CMP_OUTPUT_PLUG_CONTROL_REG_0 0xfffff0000904ULL
1169
1170static int cmp_read(struct firedtv *fdtv, void *buf, u64 addr, size_t len)
1171{
1172 int ret;
1173
1174 if (mutex_lock_interruptible(&fdtv->avc_mutex))
1175 return -EINTR;
1176
1177 ret = fdtv->backend->read(fdtv, addr, buf, len);
1178 if (ret < 0)
1179 dev_err(fdtv->device, "CMP: read I/O error\n");
1180
1181 mutex_unlock(&fdtv->avc_mutex);
1182 return ret;
1183}
1184
1185static int cmp_lock(struct firedtv *fdtv, void *data, u64 addr, __be32 arg)
1186{
1187 int ret;
1188
1189 if (mutex_lock_interruptible(&fdtv->avc_mutex))
1190 return -EINTR;
1191
1192 ret = fdtv->backend->lock(fdtv, addr, data, arg);
1193 if (ret < 0)
1194 dev_err(fdtv->device, "CMP: lock I/O error\n");
1195
1196 mutex_unlock(&fdtv->avc_mutex);
1197 return ret;
1198}
1199
1200static inline u32 get_opcr(__be32 opcr, u32 mask, u32 shift)
1201{
1202 return (be32_to_cpu(opcr) >> shift) & mask;
1203}
1204
1205static inline void set_opcr(__be32 *opcr, u32 value, u32 mask, u32 shift)
1206{
1207 *opcr &= ~cpu_to_be32(mask << shift);
1208 *opcr |= cpu_to_be32((value & mask) << shift);
1209}
1210
1211#define get_opcr_online(v) get_opcr((v), 0x1, 31)
1212#define get_opcr_p2p_connections(v) get_opcr((v), 0x3f, 24)
1213#define get_opcr_channel(v) get_opcr((v), 0x3f, 16)
1214
1215#define set_opcr_p2p_connections(p, v) set_opcr((p), (v), 0x3f, 24)
1216#define set_opcr_channel(p, v) set_opcr((p), (v), 0x3f, 16)
1217#define set_opcr_data_rate(p, v) set_opcr((p), (v), 0x3, 14)
1218#define set_opcr_overhead_id(p, v) set_opcr((p), (v), 0xf, 10)
1219
1220int cmp_establish_pp_connection(struct firedtv *fdtv, int plug, int channel)
1221{
1222 __be32 old_opcr, opcr;
1223 u64 opcr_address = CMP_OUTPUT_PLUG_CONTROL_REG_0 + (plug << 2);
1224 int attempts = 0;
1225 int ret;
1226
1227 ret = cmp_read(fdtv, &opcr, opcr_address, 4);
1228 if (ret < 0)
1229 return ret;
1230
1231repeat:
1232 if (!get_opcr_online(opcr)) {
1233 dev_err(fdtv->device, "CMP: output offline\n");
1234 return -EBUSY;
1235 }
1236
1237 old_opcr = opcr;
1238
1239 if (get_opcr_p2p_connections(opcr)) {
1240 if (get_opcr_channel(opcr) != channel) {
1241 dev_err(fdtv->device, "CMP: cannot change channel\n");
1242 return -EBUSY;
1243 }
1244 dev_info(fdtv->device, "CMP: overlaying connection\n");
1245
1246 /* We don't allocate isochronous resources. */
1247 } else {
1248 set_opcr_channel(&opcr, channel);
1249 set_opcr_data_rate(&opcr, 2); /* S400 */
1250
1251 /* FIXME: this is for the worst case - optimize */
1252 set_opcr_overhead_id(&opcr, 0);
1253
1254 /*
1255 * FIXME: allocate isochronous channel and bandwidth at IRM
1256 * fdtv->backend->alloc_resources(fdtv, channels_mask, bw);
1257 */
1258 }
1259
1260 set_opcr_p2p_connections(&opcr, get_opcr_p2p_connections(opcr) + 1);
1261
1262 ret = cmp_lock(fdtv, &opcr, opcr_address, old_opcr);
1263 if (ret < 0)
1264 return ret;
1265
1266 if (old_opcr != opcr) {
1267 /*
1268 * FIXME: if old_opcr.P2P_Connections > 0,
1269 * deallocate isochronous channel and bandwidth at IRM
1270 * if (...)
1271 * fdtv->backend->dealloc_resources(fdtv, channel, bw);
1272 */
1273
1274 if (++attempts < 6) /* arbitrary limit */
1275 goto repeat;
1276 return -EBUSY;
1277 }
1278
1279 return 0;
1280}
1281
1282void cmp_break_pp_connection(struct firedtv *fdtv, int plug, int channel)
1283{
1284 __be32 old_opcr, opcr;
1285 u64 opcr_address = CMP_OUTPUT_PLUG_CONTROL_REG_0 + (plug << 2);
1286 int attempts = 0;
1287
1288 if (cmp_read(fdtv, &opcr, opcr_address, 4) < 0)
1289 return;
1290
1291repeat:
1292 if (!get_opcr_online(opcr) || !get_opcr_p2p_connections(opcr) ||
1293 get_opcr_channel(opcr) != channel) {
1294 dev_err(fdtv->device, "CMP: no connection to break\n");
1295 return;
1296 }
1297
1298 old_opcr = opcr;
1299 set_opcr_p2p_connections(&opcr, get_opcr_p2p_connections(opcr) - 1);
1300
1301 if (cmp_lock(fdtv, &opcr, opcr_address, old_opcr) < 0)
1302 return;
1303
1304 if (old_opcr != opcr) {
1305 /*
1306 * FIXME: if old_opcr.P2P_Connections == 1, i.e. we were last
1307 * owner, deallocate isochronous channel and bandwidth at IRM
1308 * if (...)
1309 * fdtv->backend->dealloc_resources(fdtv, channel, bw);
1310 */
1311
1312 if (++attempts < 6) /* arbitrary limit */
1313 goto repeat;
1314 }
1315}
diff --git a/drivers/media/dvb/firewire/firedtv-ci.c b/drivers/media/dvb/firewire/firedtv-ci.c
new file mode 100644
index 000000000000..eeb80d0ea3ff
--- /dev/null
+++ b/drivers/media/dvb/firewire/firedtv-ci.c
@@ -0,0 +1,260 @@
1/*
2 * FireDTV driver (formerly known as FireSAT)
3 *
4 * Copyright (C) 2004 Andreas Monitzer <andy@monitzer.com>
5 * Copyright (C) 2008 Henrik Kurelid <henrik@kurelid.se>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 */
12
13#include <linux/device.h>
14#include <linux/dvb/ca.h>
15#include <linux/fs.h>
16#include <linux/module.h>
17
18#include <dvbdev.h>
19
20#include "firedtv.h"
21
22#define EN50221_TAG_APP_INFO_ENQUIRY 0x9f8020
23#define EN50221_TAG_CA_INFO_ENQUIRY 0x9f8030
24#define EN50221_TAG_CA_PMT 0x9f8032
25#define EN50221_TAG_ENTER_MENU 0x9f8022
26
27static int fdtv_ca_ready(struct firedtv_tuner_status *stat)
28{
29 return stat->ca_initialization_status == 1 &&
30 stat->ca_error_flag == 0 &&
31 stat->ca_dvb_flag == 1 &&
32 stat->ca_module_present_status == 1;
33}
34
35static int fdtv_get_ca_flags(struct firedtv_tuner_status *stat)
36{
37 int flags = 0;
38
39 if (stat->ca_module_present_status == 1)
40 flags |= CA_CI_MODULE_PRESENT;
41 if (stat->ca_initialization_status == 1 &&
42 stat->ca_error_flag == 0 &&
43 stat->ca_dvb_flag == 1)
44 flags |= CA_CI_MODULE_READY;
45 return flags;
46}
47
48static int fdtv_ca_reset(struct firedtv *fdtv)
49{
50 return avc_ca_reset(fdtv) ? -EFAULT : 0;
51}
52
53static int fdtv_ca_get_caps(void *arg)
54{
55 struct ca_caps *cap = arg;
56
57 cap->slot_num = 1;
58 cap->slot_type = CA_CI;
59 cap->descr_num = 1;
60 cap->descr_type = CA_ECD;
61 return 0;
62}
63
64static int fdtv_ca_get_slot_info(struct firedtv *fdtv, void *arg)
65{
66 struct firedtv_tuner_status stat;
67 struct ca_slot_info *slot = arg;
68
69 if (avc_tuner_status(fdtv, &stat))
70 return -EFAULT;
71
72 if (slot->num != 0)
73 return -EFAULT;
74
75 slot->type = CA_CI;
76 slot->flags = fdtv_get_ca_flags(&stat);
77 return 0;
78}
79
80static int fdtv_ca_app_info(struct firedtv *fdtv, void *arg)
81{
82 struct ca_msg *reply = arg;
83
84 return avc_ca_app_info(fdtv, reply->msg, &reply->length) ? -EFAULT : 0;
85}
86
87static int fdtv_ca_info(struct firedtv *fdtv, void *arg)
88{
89 struct ca_msg *reply = arg;
90
91 return avc_ca_info(fdtv, reply->msg, &reply->length) ? -EFAULT : 0;
92}
93
94static int fdtv_ca_get_mmi(struct firedtv *fdtv, void *arg)
95{
96 struct ca_msg *reply = arg;
97
98 return avc_ca_get_mmi(fdtv, reply->msg, &reply->length) ? -EFAULT : 0;
99}
100
101static int fdtv_ca_get_msg(struct firedtv *fdtv, void *arg)
102{
103 struct firedtv_tuner_status stat;
104 int err;
105
106 switch (fdtv->ca_last_command) {
107 case EN50221_TAG_APP_INFO_ENQUIRY:
108 err = fdtv_ca_app_info(fdtv, arg);
109 break;
110 case EN50221_TAG_CA_INFO_ENQUIRY:
111 err = fdtv_ca_info(fdtv, arg);
112 break;
113 default:
114 if (avc_tuner_status(fdtv, &stat))
115 err = -EFAULT;
116 else if (stat.ca_mmi == 1)
117 err = fdtv_ca_get_mmi(fdtv, arg);
118 else {
119 dev_info(fdtv->device, "unhandled CA message 0x%08x\n",
120 fdtv->ca_last_command);
121 err = -EFAULT;
122 }
123 }
124 fdtv->ca_last_command = 0;
125 return err;
126}
127
128static int fdtv_ca_pmt(struct firedtv *fdtv, void *arg)
129{
130 struct ca_msg *msg = arg;
131 int data_pos;
132 int data_length;
133 int i;
134
135 data_pos = 4;
136 if (msg->msg[3] & 0x80) {
137 data_length = 0;
138 for (i = 0; i < (msg->msg[3] & 0x7f); i++)
139 data_length = (data_length << 8) + msg->msg[data_pos++];
140 } else {
141 data_length = msg->msg[3];
142 }
143
144 return avc_ca_pmt(fdtv, &msg->msg[data_pos], data_length) ? -EFAULT : 0;
145}
146
147static int fdtv_ca_send_msg(struct firedtv *fdtv, void *arg)
148{
149 struct ca_msg *msg = arg;
150 int err;
151
152 /* Do we need a semaphore for this? */
153 fdtv->ca_last_command =
154 (msg->msg[0] << 16) + (msg->msg[1] << 8) + msg->msg[2];
155 switch (fdtv->ca_last_command) {
156 case EN50221_TAG_CA_PMT:
157 err = fdtv_ca_pmt(fdtv, arg);
158 break;
159 case EN50221_TAG_APP_INFO_ENQUIRY:
160 /* handled in ca_get_msg */
161 err = 0;
162 break;
163 case EN50221_TAG_CA_INFO_ENQUIRY:
164 /* handled in ca_get_msg */
165 err = 0;
166 break;
167 case EN50221_TAG_ENTER_MENU:
168 err = avc_ca_enter_menu(fdtv);
169 break;
170 default:
171 dev_err(fdtv->device, "unhandled CA message 0x%08x\n",
172 fdtv->ca_last_command);
173 err = -EFAULT;
174 }
175 return err;
176}
177
178static int fdtv_ca_ioctl(struct inode *inode, struct file *file,
179 unsigned int cmd, void *arg)
180{
181 struct dvb_device *dvbdev = file->private_data;
182 struct firedtv *fdtv = dvbdev->priv;
183 struct firedtv_tuner_status stat;
184 int err;
185
186 switch (cmd) {
187 case CA_RESET:
188 err = fdtv_ca_reset(fdtv);
189 break;
190 case CA_GET_CAP:
191 err = fdtv_ca_get_caps(arg);
192 break;
193 case CA_GET_SLOT_INFO:
194 err = fdtv_ca_get_slot_info(fdtv, arg);
195 break;
196 case CA_GET_MSG:
197 err = fdtv_ca_get_msg(fdtv, arg);
198 break;
199 case CA_SEND_MSG:
200 err = fdtv_ca_send_msg(fdtv, arg);
201 break;
202 default:
203 dev_info(fdtv->device, "unhandled CA ioctl %u\n", cmd);
204 err = -EOPNOTSUPP;
205 }
206
207 /* FIXME Is this necessary? */
208 avc_tuner_status(fdtv, &stat);
209
210 return err;
211}
212
213static unsigned int fdtv_ca_io_poll(struct file *file, poll_table *wait)
214{
215 return POLLIN;
216}
217
218static struct file_operations fdtv_ca_fops = {
219 .owner = THIS_MODULE,
220 .ioctl = dvb_generic_ioctl,
221 .open = dvb_generic_open,
222 .release = dvb_generic_release,
223 .poll = fdtv_ca_io_poll,
224};
225
226static struct dvb_device fdtv_ca = {
227 .users = 1,
228 .readers = 1,
229 .writers = 1,
230 .fops = &fdtv_ca_fops,
231 .kernel_ioctl = fdtv_ca_ioctl,
232};
233
234int fdtv_ca_register(struct firedtv *fdtv)
235{
236 struct firedtv_tuner_status stat;
237 int err;
238
239 if (avc_tuner_status(fdtv, &stat))
240 return -EINVAL;
241
242 if (!fdtv_ca_ready(&stat))
243 return -EFAULT;
244
245 err = dvb_register_device(&fdtv->adapter, &fdtv->cadev,
246 &fdtv_ca, fdtv, DVB_DEVICE_CA);
247
248 if (stat.ca_application_info == 0)
249 dev_err(fdtv->device, "CaApplicationInfo is not set\n");
250 if (stat.ca_date_time_request == 1)
251 avc_ca_get_time_date(fdtv, &fdtv->ca_time_interval);
252
253 return err;
254}
255
256void fdtv_ca_release(struct firedtv *fdtv)
257{
258 if (fdtv->cadev)
259 dvb_unregister_device(fdtv->cadev);
260}
diff --git a/drivers/media/dvb/firewire/firedtv-dvb.c b/drivers/media/dvb/firewire/firedtv-dvb.c
new file mode 100644
index 000000000000..9d308dd32a5c
--- /dev/null
+++ b/drivers/media/dvb/firewire/firedtv-dvb.c
@@ -0,0 +1,364 @@
1/*
2 * FireDTV driver (formerly known as FireSAT)
3 *
4 * Copyright (C) 2004 Andreas Monitzer <andy@monitzer.com>
5 * Copyright (C) 2008 Henrik Kurelid <henrik@kurelid.se>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 */
12
13#include <linux/bitops.h>
14#include <linux/device.h>
15#include <linux/errno.h>
16#include <linux/kernel.h>
17#include <linux/mod_devicetable.h>
18#include <linux/module.h>
19#include <linux/mutex.h>
20#include <linux/slab.h>
21#include <linux/string.h>
22#include <linux/types.h>
23#include <linux/wait.h>
24#include <linux/workqueue.h>
25
26#include <dmxdev.h>
27#include <dvb_demux.h>
28#include <dvbdev.h>
29#include <dvb_frontend.h>
30
31#include "firedtv.h"
32
33static int alloc_channel(struct firedtv *fdtv)
34{
35 int i;
36
37 for (i = 0; i < 16; i++)
38 if (!__test_and_set_bit(i, &fdtv->channel_active))
39 break;
40 return i;
41}
42
43static void collect_channels(struct firedtv *fdtv, int *pidc, u16 pid[])
44{
45 int i, n;
46
47 for (i = 0, n = 0; i < 16; i++)
48 if (test_bit(i, &fdtv->channel_active))
49 pid[n++] = fdtv->channel_pid[i];
50 *pidc = n;
51}
52
53static inline void dealloc_channel(struct firedtv *fdtv, int i)
54{
55 __clear_bit(i, &fdtv->channel_active);
56}
57
58int fdtv_start_feed(struct dvb_demux_feed *dvbdmxfeed)
59{
60 struct firedtv *fdtv = dvbdmxfeed->demux->priv;
61 int pidc, c, ret;
62 u16 pids[16];
63
64 switch (dvbdmxfeed->type) {
65 case DMX_TYPE_TS:
66 case DMX_TYPE_SEC:
67 break;
68 default:
69 dev_err(fdtv->device, "can't start dmx feed: invalid type %u\n",
70 dvbdmxfeed->type);
71 return -EINVAL;
72 }
73
74 if (mutex_lock_interruptible(&fdtv->demux_mutex))
75 return -EINTR;
76
77 if (dvbdmxfeed->type == DMX_TYPE_TS) {
78 switch (dvbdmxfeed->pes_type) {
79 case DMX_TS_PES_VIDEO:
80 case DMX_TS_PES_AUDIO:
81 case DMX_TS_PES_TELETEXT:
82 case DMX_TS_PES_PCR:
83 case DMX_TS_PES_OTHER:
84 c = alloc_channel(fdtv);
85 break;
86 default:
87 dev_err(fdtv->device,
88 "can't start dmx feed: invalid pes type %u\n",
89 dvbdmxfeed->pes_type);
90 ret = -EINVAL;
91 goto out;
92 }
93 } else {
94 c = alloc_channel(fdtv);
95 }
96
97 if (c > 15) {
98 dev_err(fdtv->device, "can't start dmx feed: busy\n");
99 ret = -EBUSY;
100 goto out;
101 }
102
103 dvbdmxfeed->priv = (typeof(dvbdmxfeed->priv))(unsigned long)c;
104 fdtv->channel_pid[c] = dvbdmxfeed->pid;
105 collect_channels(fdtv, &pidc, pids);
106
107 if (dvbdmxfeed->pid == 8192) {
108 ret = avc_tuner_get_ts(fdtv);
109 if (ret) {
110 dealloc_channel(fdtv, c);
111 dev_err(fdtv->device, "can't get TS\n");
112 goto out;
113 }
114 } else {
115 ret = avc_tuner_set_pids(fdtv, pidc, pids);
116 if (ret) {
117 dealloc_channel(fdtv, c);
118 dev_err(fdtv->device, "can't set PIDs\n");
119 goto out;
120 }
121 }
122out:
123 mutex_unlock(&fdtv->demux_mutex);
124
125 return ret;
126}
127
128int fdtv_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
129{
130 struct dvb_demux *demux = dvbdmxfeed->demux;
131 struct firedtv *fdtv = demux->priv;
132 int pidc, c, ret;
133 u16 pids[16];
134
135 if (dvbdmxfeed->type == DMX_TYPE_TS &&
136 !((dvbdmxfeed->ts_type & TS_PACKET) &&
137 (demux->dmx.frontend->source != DMX_MEMORY_FE))) {
138
139 if (dvbdmxfeed->ts_type & TS_DECODER) {
140 if (dvbdmxfeed->pes_type >= DMX_TS_PES_OTHER ||
141 !demux->pesfilter[dvbdmxfeed->pes_type])
142 return -EINVAL;
143
144 demux->pids[dvbdmxfeed->pes_type] |= 0x8000;
145 demux->pesfilter[dvbdmxfeed->pes_type] = NULL;
146 }
147
148 if (!(dvbdmxfeed->ts_type & TS_DECODER &&
149 dvbdmxfeed->pes_type < DMX_TS_PES_OTHER))
150 return 0;
151 }
152
153 if (mutex_lock_interruptible(&fdtv->demux_mutex))
154 return -EINTR;
155
156 c = (unsigned long)dvbdmxfeed->priv;
157 dealloc_channel(fdtv, c);
158 collect_channels(fdtv, &pidc, pids);
159
160 ret = avc_tuner_set_pids(fdtv, pidc, pids);
161
162 mutex_unlock(&fdtv->demux_mutex);
163
164 return ret;
165}
166
167DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
168
169int fdtv_dvb_register(struct firedtv *fdtv)
170{
171 int err;
172
173 err = dvb_register_adapter(&fdtv->adapter, fdtv_model_names[fdtv->type],
174 THIS_MODULE, fdtv->device, adapter_nr);
175 if (err < 0)
176 goto fail_log;
177
178 /*DMX_TS_FILTERING | DMX_SECTION_FILTERING*/
179 fdtv->demux.dmx.capabilities = 0;
180
181 fdtv->demux.priv = fdtv;
182 fdtv->demux.filternum = 16;
183 fdtv->demux.feednum = 16;
184 fdtv->demux.start_feed = fdtv_start_feed;
185 fdtv->demux.stop_feed = fdtv_stop_feed;
186 fdtv->demux.write_to_decoder = NULL;
187
188 err = dvb_dmx_init(&fdtv->demux);
189 if (err)
190 goto fail_unreg_adapter;
191
192 fdtv->dmxdev.filternum = 16;
193 fdtv->dmxdev.demux = &fdtv->demux.dmx;
194 fdtv->dmxdev.capabilities = 0;
195
196 err = dvb_dmxdev_init(&fdtv->dmxdev, &fdtv->adapter);
197 if (err)
198 goto fail_dmx_release;
199
200 fdtv->frontend.source = DMX_FRONTEND_0;
201
202 err = fdtv->demux.dmx.add_frontend(&fdtv->demux.dmx, &fdtv->frontend);
203 if (err)
204 goto fail_dmxdev_release;
205
206 err = fdtv->demux.dmx.connect_frontend(&fdtv->demux.dmx,
207 &fdtv->frontend);
208 if (err)
209 goto fail_rem_frontend;
210
211 dvb_net_init(&fdtv->adapter, &fdtv->dvbnet, &fdtv->demux.dmx);
212
213 fdtv_frontend_init(fdtv);
214 err = dvb_register_frontend(&fdtv->adapter, &fdtv->fe);
215 if (err)
216 goto fail_net_release;
217
218 err = fdtv_ca_register(fdtv);
219 if (err)
220 dev_info(fdtv->device,
221 "Conditional Access Module not enabled\n");
222 return 0;
223
224fail_net_release:
225 dvb_net_release(&fdtv->dvbnet);
226 fdtv->demux.dmx.close(&fdtv->demux.dmx);
227fail_rem_frontend:
228 fdtv->demux.dmx.remove_frontend(&fdtv->demux.dmx, &fdtv->frontend);
229fail_dmxdev_release:
230 dvb_dmxdev_release(&fdtv->dmxdev);
231fail_dmx_release:
232 dvb_dmx_release(&fdtv->demux);
233fail_unreg_adapter:
234 dvb_unregister_adapter(&fdtv->adapter);
235fail_log:
236 dev_err(fdtv->device, "DVB initialization failed\n");
237 return err;
238}
239
240void fdtv_dvb_unregister(struct firedtv *fdtv)
241{
242 fdtv_ca_release(fdtv);
243 dvb_unregister_frontend(&fdtv->fe);
244 dvb_net_release(&fdtv->dvbnet);
245 fdtv->demux.dmx.close(&fdtv->demux.dmx);
246 fdtv->demux.dmx.remove_frontend(&fdtv->demux.dmx, &fdtv->frontend);
247 dvb_dmxdev_release(&fdtv->dmxdev);
248 dvb_dmx_release(&fdtv->demux);
249 dvb_unregister_adapter(&fdtv->adapter);
250}
251
252const char *fdtv_model_names[] = {
253 [FIREDTV_UNKNOWN] = "unknown type",
254 [FIREDTV_DVB_S] = "FireDTV S/CI",
255 [FIREDTV_DVB_C] = "FireDTV C/CI",
256 [FIREDTV_DVB_T] = "FireDTV T/CI",
257 [FIREDTV_DVB_S2] = "FireDTV S2 ",
258};
259
260struct firedtv *fdtv_alloc(struct device *dev,
261 const struct firedtv_backend *backend,
262 const char *name, size_t name_len)
263{
264 struct firedtv *fdtv;
265 int i;
266
267 fdtv = kzalloc(sizeof(*fdtv), GFP_KERNEL);
268 if (!fdtv)
269 return NULL;
270
271 dev->driver_data = fdtv;
272 fdtv->device = dev;
273 fdtv->isochannel = -1;
274 fdtv->voltage = 0xff;
275 fdtv->tone = 0xff;
276 fdtv->backend = backend;
277
278 mutex_init(&fdtv->avc_mutex);
279 init_waitqueue_head(&fdtv->avc_wait);
280 fdtv->avc_reply_received = true;
281 mutex_init(&fdtv->demux_mutex);
282 INIT_WORK(&fdtv->remote_ctrl_work, avc_remote_ctrl_work);
283
284 for (i = ARRAY_SIZE(fdtv_model_names); --i; )
285 if (strlen(fdtv_model_names[i]) <= name_len &&
286 strncmp(name, fdtv_model_names[i], name_len) == 0)
287 break;
288 fdtv->type = i;
289
290 return fdtv;
291}
292
293#define MATCH_FLAGS (IEEE1394_MATCH_VENDOR_ID | IEEE1394_MATCH_MODEL_ID | \
294 IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION)
295
296#define DIGITAL_EVERYWHERE_OUI 0x001287
297#define AVC_UNIT_SPEC_ID_ENTRY 0x00a02d
298#define AVC_SW_VERSION_ENTRY 0x010001
299
300static struct ieee1394_device_id fdtv_id_table[] = {
301 {
302 /* FloppyDTV S/CI and FloppyDTV S2 */
303 .match_flags = MATCH_FLAGS,
304 .vendor_id = DIGITAL_EVERYWHERE_OUI,
305 .model_id = 0x000024,
306 .specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
307 .version = AVC_SW_VERSION_ENTRY,
308 }, {
309 /* FloppyDTV T/CI */
310 .match_flags = MATCH_FLAGS,
311 .vendor_id = DIGITAL_EVERYWHERE_OUI,
312 .model_id = 0x000025,
313 .specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
314 .version = AVC_SW_VERSION_ENTRY,
315 }, {
316 /* FloppyDTV C/CI */
317 .match_flags = MATCH_FLAGS,
318 .vendor_id = DIGITAL_EVERYWHERE_OUI,
319 .model_id = 0x000026,
320 .specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
321 .version = AVC_SW_VERSION_ENTRY,
322 }, {
323 /* FireDTV S/CI and FloppyDTV S2 */
324 .match_flags = MATCH_FLAGS,
325 .vendor_id = DIGITAL_EVERYWHERE_OUI,
326 .model_id = 0x000034,
327 .specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
328 .version = AVC_SW_VERSION_ENTRY,
329 }, {
330 /* FireDTV T/CI */
331 .match_flags = MATCH_FLAGS,
332 .vendor_id = DIGITAL_EVERYWHERE_OUI,
333 .model_id = 0x000035,
334 .specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
335 .version = AVC_SW_VERSION_ENTRY,
336 }, {
337 /* FireDTV C/CI */
338 .match_flags = MATCH_FLAGS,
339 .vendor_id = DIGITAL_EVERYWHERE_OUI,
340 .model_id = 0x000036,
341 .specifier_id = AVC_UNIT_SPEC_ID_ENTRY,
342 .version = AVC_SW_VERSION_ENTRY,
343 }, {}
344};
345MODULE_DEVICE_TABLE(ieee1394, fdtv_id_table);
346
347static int __init fdtv_init(void)
348{
349 return fdtv_1394_init(fdtv_id_table);
350}
351
352static void __exit fdtv_exit(void)
353{
354 fdtv_1394_exit();
355}
356
357module_init(fdtv_init);
358module_exit(fdtv_exit);
359
360MODULE_AUTHOR("Andreas Monitzer <andy@monitzer.com>");
361MODULE_AUTHOR("Ben Backx <ben@bbackx.com>");
362MODULE_DESCRIPTION("FireDTV DVB Driver");
363MODULE_LICENSE("GPL");
364MODULE_SUPPORTED_DEVICE("FireDTV DVB");
diff --git a/drivers/media/dvb/firewire/firedtv-fe.c b/drivers/media/dvb/firewire/firedtv-fe.c
new file mode 100644
index 000000000000..7ba43630a25d
--- /dev/null
+++ b/drivers/media/dvb/firewire/firedtv-fe.c
@@ -0,0 +1,247 @@
1/*
2 * FireDTV driver (formerly known as FireSAT)
3 *
4 * Copyright (C) 2004 Andreas Monitzer <andy@monitzer.com>
5 * Copyright (C) 2008 Henrik Kurelid <henrik@kurelid.se>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 */
12
13#include <linux/device.h>
14#include <linux/errno.h>
15#include <linux/kernel.h>
16#include <linux/string.h>
17#include <linux/types.h>
18
19#include <dvb_frontend.h>
20
21#include "firedtv.h"
22
23static int fdtv_dvb_init(struct dvb_frontend *fe)
24{
25 struct firedtv *fdtv = fe->sec_priv;
26 int err;
27
28 /* FIXME - allocate free channel at IRM */
29 fdtv->isochannel = fdtv->adapter.num;
30
31 err = cmp_establish_pp_connection(fdtv, fdtv->subunit,
32 fdtv->isochannel);
33 if (err) {
34 dev_err(fdtv->device,
35 "could not establish point to point connection\n");
36 return err;
37 }
38
39 return fdtv->backend->start_iso(fdtv);
40}
41
42static int fdtv_sleep(struct dvb_frontend *fe)
43{
44 struct firedtv *fdtv = fe->sec_priv;
45
46 fdtv->backend->stop_iso(fdtv);
47 cmp_break_pp_connection(fdtv, fdtv->subunit, fdtv->isochannel);
48 fdtv->isochannel = -1;
49 return 0;
50}
51
52#define LNBCONTROL_DONTCARE 0xff
53
54static int fdtv_diseqc_send_master_cmd(struct dvb_frontend *fe,
55 struct dvb_diseqc_master_cmd *cmd)
56{
57 struct firedtv *fdtv = fe->sec_priv;
58
59 return avc_lnb_control(fdtv, LNBCONTROL_DONTCARE, LNBCONTROL_DONTCARE,
60 LNBCONTROL_DONTCARE, 1, cmd);
61}
62
63static int fdtv_diseqc_send_burst(struct dvb_frontend *fe,
64 fe_sec_mini_cmd_t minicmd)
65{
66 return 0;
67}
68
69static int fdtv_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
70{
71 struct firedtv *fdtv = fe->sec_priv;
72
73 fdtv->tone = tone;
74 return 0;
75}
76
77static int fdtv_set_voltage(struct dvb_frontend *fe,
78 fe_sec_voltage_t voltage)
79{
80 struct firedtv *fdtv = fe->sec_priv;
81
82 fdtv->voltage = voltage;
83 return 0;
84}
85
86static int fdtv_read_status(struct dvb_frontend *fe, fe_status_t *status)
87{
88 struct firedtv *fdtv = fe->sec_priv;
89 struct firedtv_tuner_status stat;
90
91 if (avc_tuner_status(fdtv, &stat))
92 return -EINVAL;
93
94 if (stat.no_rf)
95 *status = 0;
96 else
97 *status = FE_HAS_SIGNAL | FE_HAS_VITERBI | FE_HAS_SYNC |
98 FE_HAS_CARRIER | FE_HAS_LOCK;
99 return 0;
100}
101
102static int fdtv_read_ber(struct dvb_frontend *fe, u32 *ber)
103{
104 struct firedtv *fdtv = fe->sec_priv;
105 struct firedtv_tuner_status stat;
106
107 if (avc_tuner_status(fdtv, &stat))
108 return -EINVAL;
109
110 *ber = stat.ber;
111 return 0;
112}
113
114static int fdtv_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
115{
116 struct firedtv *fdtv = fe->sec_priv;
117 struct firedtv_tuner_status stat;
118
119 if (avc_tuner_status(fdtv, &stat))
120 return -EINVAL;
121
122 *strength = stat.signal_strength << 8;
123 return 0;
124}
125
126static int fdtv_read_snr(struct dvb_frontend *fe, u16 *snr)
127{
128 struct firedtv *fdtv = fe->sec_priv;
129 struct firedtv_tuner_status stat;
130
131 if (avc_tuner_status(fdtv, &stat))
132 return -EINVAL;
133
134 /* C/N[dB] = -10 * log10(snr / 65535) */
135 *snr = stat.carrier_noise_ratio * 257;
136 return 0;
137}
138
139static int fdtv_read_uncorrected_blocks(struct dvb_frontend *fe, u32 *ucblocks)
140{
141 return -EOPNOTSUPP;
142}
143
144#define ACCEPTED 0x9
145
146static int fdtv_set_frontend(struct dvb_frontend *fe,
147 struct dvb_frontend_parameters *params)
148{
149 struct firedtv *fdtv = fe->sec_priv;
150
151 /* FIXME: avc_tuner_dsd never returns ACCEPTED. Check status? */
152 if (avc_tuner_dsd(fdtv, params) != ACCEPTED)
153 return -EINVAL;
154 else
155 return 0; /* not sure of this... */
156}
157
158static int fdtv_get_frontend(struct dvb_frontend *fe,
159 struct dvb_frontend_parameters *params)
160{
161 return -EOPNOTSUPP;
162}
163
164void fdtv_frontend_init(struct firedtv *fdtv)
165{
166 struct dvb_frontend_ops *ops = &fdtv->fe.ops;
167 struct dvb_frontend_info *fi = &ops->info;
168
169 ops->init = fdtv_dvb_init;
170 ops->sleep = fdtv_sleep;
171
172 ops->set_frontend = fdtv_set_frontend;
173 ops->get_frontend = fdtv_get_frontend;
174
175 ops->read_status = fdtv_read_status;
176 ops->read_ber = fdtv_read_ber;
177 ops->read_signal_strength = fdtv_read_signal_strength;
178 ops->read_snr = fdtv_read_snr;
179 ops->read_ucblocks = fdtv_read_uncorrected_blocks;
180
181 ops->diseqc_send_master_cmd = fdtv_diseqc_send_master_cmd;
182 ops->diseqc_send_burst = fdtv_diseqc_send_burst;
183 ops->set_tone = fdtv_set_tone;
184 ops->set_voltage = fdtv_set_voltage;
185
186 switch (fdtv->type) {
187 case FIREDTV_DVB_S:
188 case FIREDTV_DVB_S2:
189 fi->type = FE_QPSK;
190
191 fi->frequency_min = 950000;
192 fi->frequency_max = 2150000;
193 fi->frequency_stepsize = 125;
194 fi->symbol_rate_min = 1000000;
195 fi->symbol_rate_max = 40000000;
196
197 fi->caps = FE_CAN_INVERSION_AUTO |
198 FE_CAN_FEC_1_2 |
199 FE_CAN_FEC_2_3 |
200 FE_CAN_FEC_3_4 |
201 FE_CAN_FEC_5_6 |
202 FE_CAN_FEC_7_8 |
203 FE_CAN_FEC_AUTO |
204 FE_CAN_QPSK;
205 break;
206
207 case FIREDTV_DVB_C:
208 fi->type = FE_QAM;
209
210 fi->frequency_min = 47000000;
211 fi->frequency_max = 866000000;
212 fi->frequency_stepsize = 62500;
213 fi->symbol_rate_min = 870000;
214 fi->symbol_rate_max = 6900000;
215
216 fi->caps = FE_CAN_INVERSION_AUTO |
217 FE_CAN_QAM_16 |
218 FE_CAN_QAM_32 |
219 FE_CAN_QAM_64 |
220 FE_CAN_QAM_128 |
221 FE_CAN_QAM_256 |
222 FE_CAN_QAM_AUTO;
223 break;
224
225 case FIREDTV_DVB_T:
226 fi->type = FE_OFDM;
227
228 fi->frequency_min = 49000000;
229 fi->frequency_max = 861000000;
230 fi->frequency_stepsize = 62500;
231
232 fi->caps = FE_CAN_INVERSION_AUTO |
233 FE_CAN_FEC_2_3 |
234 FE_CAN_TRANSMISSION_MODE_AUTO |
235 FE_CAN_GUARD_INTERVAL_AUTO |
236 FE_CAN_HIERARCHY_AUTO;
237 break;
238
239 default:
240 dev_err(fdtv->device, "no frontend for model type %d\n",
241 fdtv->type);
242 }
243 strcpy(fi->name, fdtv_model_names[fdtv->type]);
244
245 fdtv->fe.dvb = &fdtv->adapter;
246 fdtv->fe.sec_priv = fdtv;
247}
diff --git a/drivers/media/dvb/firewire/firedtv-rc.c b/drivers/media/dvb/firewire/firedtv-rc.c
new file mode 100644
index 000000000000..46a6324d7b73
--- /dev/null
+++ b/drivers/media/dvb/firewire/firedtv-rc.c
@@ -0,0 +1,190 @@
1/*
2 * FireDTV driver (formerly known as FireSAT)
3 *
4 * Copyright (C) 2004 Andreas Monitzer <andy@monitzer.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 */
11
12#include <linux/bitops.h>
13#include <linux/input.h>
14#include <linux/kernel.h>
15#include <linux/string.h>
16#include <linux/types.h>
17
18#include "firedtv.h"
19
20/* fixed table with older keycodes, geared towards MythTV */
21const static u16 oldtable[] = {
22
23 /* code from device: 0x4501...0x451f */
24
25 KEY_ESC,
26 KEY_F9,
27 KEY_1,
28 KEY_2,
29 KEY_3,
30 KEY_4,
31 KEY_5,
32 KEY_6,
33 KEY_7,
34 KEY_8,
35 KEY_9,
36 KEY_I,
37 KEY_0,
38 KEY_ENTER,
39 KEY_RED,
40 KEY_UP,
41 KEY_GREEN,
42 KEY_F10,
43 KEY_SPACE,
44 KEY_F11,
45 KEY_YELLOW,
46 KEY_DOWN,
47 KEY_BLUE,
48 KEY_Z,
49 KEY_P,
50 KEY_PAGEDOWN,
51 KEY_LEFT,
52 KEY_W,
53 KEY_RIGHT,
54 KEY_P,
55 KEY_M,
56
57 /* code from device: 0x4540...0x4542 */
58
59 KEY_R,
60 KEY_V,
61 KEY_C,
62};
63
64/* user-modifiable table for a remote as sold in 2008 */
65const static u16 keytable[] = {
66
67 /* code from device: 0x0300...0x031f */
68
69 [0x00] = KEY_POWER,
70 [0x01] = KEY_SLEEP,
71 [0x02] = KEY_STOP,
72 [0x03] = KEY_OK,
73 [0x04] = KEY_RIGHT,
74 [0x05] = KEY_1,
75 [0x06] = KEY_2,
76 [0x07] = KEY_3,
77 [0x08] = KEY_LEFT,
78 [0x09] = KEY_4,
79 [0x0a] = KEY_5,
80 [0x0b] = KEY_6,
81 [0x0c] = KEY_UP,
82 [0x0d] = KEY_7,
83 [0x0e] = KEY_8,
84 [0x0f] = KEY_9,
85 [0x10] = KEY_DOWN,
86 [0x11] = KEY_TITLE, /* "OSD" - fixme */
87 [0x12] = KEY_0,
88 [0x13] = KEY_F20, /* "16:9" - fixme */
89 [0x14] = KEY_SCREEN, /* "FULL" - fixme */
90 [0x15] = KEY_MUTE,
91 [0x16] = KEY_SUBTITLE,
92 [0x17] = KEY_RECORD,
93 [0x18] = KEY_TEXT,
94 [0x19] = KEY_AUDIO,
95 [0x1a] = KEY_RED,
96 [0x1b] = KEY_PREVIOUS,
97 [0x1c] = KEY_REWIND,
98 [0x1d] = KEY_PLAYPAUSE,
99 [0x1e] = KEY_NEXT,
100 [0x1f] = KEY_VOLUMEUP,
101
102 /* code from device: 0x0340...0x0354 */
103
104 [0x20] = KEY_CHANNELUP,
105 [0x21] = KEY_F21, /* "4:3" - fixme */
106 [0x22] = KEY_TV,
107 [0x23] = KEY_DVD,
108 [0x24] = KEY_VCR,
109 [0x25] = KEY_AUX,
110 [0x26] = KEY_GREEN,
111 [0x27] = KEY_YELLOW,
112 [0x28] = KEY_BLUE,
113 [0x29] = KEY_CHANNEL, /* "CH.LIST" */
114 [0x2a] = KEY_VENDOR, /* "CI" - fixme */
115 [0x2b] = KEY_VOLUMEDOWN,
116 [0x2c] = KEY_CHANNELDOWN,
117 [0x2d] = KEY_LAST,
118 [0x2e] = KEY_INFO,
119 [0x2f] = KEY_FORWARD,
120 [0x30] = KEY_LIST,
121 [0x31] = KEY_FAVORITES,
122 [0x32] = KEY_MENU,
123 [0x33] = KEY_EPG,
124 [0x34] = KEY_EXIT,
125};
126
127int fdtv_register_rc(struct firedtv *fdtv, struct device *dev)
128{
129 struct input_dev *idev;
130 int i, err;
131
132 idev = input_allocate_device();
133 if (!idev)
134 return -ENOMEM;
135
136 fdtv->remote_ctrl_dev = idev;
137 idev->name = "FireDTV remote control";
138 idev->dev.parent = dev;
139 idev->evbit[0] = BIT_MASK(EV_KEY);
140 idev->keycode = kmemdup(keytable, sizeof(keytable), GFP_KERNEL);
141 if (!idev->keycode) {
142 err = -ENOMEM;
143 goto fail;
144 }
145 idev->keycodesize = sizeof(keytable[0]);
146 idev->keycodemax = ARRAY_SIZE(keytable);
147
148 for (i = 0; i < ARRAY_SIZE(keytable); i++)
149 set_bit(keytable[i], idev->keybit);
150
151 err = input_register_device(idev);
152 if (err)
153 goto fail_free_keymap;
154
155 return 0;
156
157fail_free_keymap:
158 kfree(idev->keycode);
159fail:
160 input_free_device(idev);
161 return err;
162}
163
164void fdtv_unregister_rc(struct firedtv *fdtv)
165{
166 kfree(fdtv->remote_ctrl_dev->keycode);
167 input_unregister_device(fdtv->remote_ctrl_dev);
168}
169
170void fdtv_handle_rc(struct firedtv *fdtv, unsigned int code)
171{
172 u16 *keycode = fdtv->remote_ctrl_dev->keycode;
173
174 if (code >= 0x0300 && code <= 0x031f)
175 code = keycode[code - 0x0300];
176 else if (code >= 0x0340 && code <= 0x0354)
177 code = keycode[code - 0x0320];
178 else if (code >= 0x4501 && code <= 0x451f)
179 code = oldtable[code - 0x4501];
180 else if (code >= 0x4540 && code <= 0x4542)
181 code = oldtable[code - 0x4521];
182 else {
183 printk(KERN_DEBUG "firedtv: invalid key code 0x%04x "
184 "from remote control\n", code);
185 return;
186 }
187
188 input_report_key(fdtv->remote_ctrl_dev, code, 1);
189 input_report_key(fdtv->remote_ctrl_dev, code, 0);
190}
diff --git a/drivers/media/dvb/firewire/firedtv.h b/drivers/media/dvb/firewire/firedtv.h
new file mode 100644
index 000000000000..d48530b81e61
--- /dev/null
+++ b/drivers/media/dvb/firewire/firedtv.h
@@ -0,0 +1,182 @@
1/*
2 * FireDTV driver (formerly known as FireSAT)
3 *
4 * Copyright (C) 2004 Andreas Monitzer <andy@monitzer.com>
5 * Copyright (C) 2008 Henrik Kurelid <henrik@kurelid.se>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 */
12
13#ifndef _FIREDTV_H
14#define _FIREDTV_H
15
16#include <linux/dvb/dmx.h>
17#include <linux/dvb/frontend.h>
18#include <linux/list.h>
19#include <linux/mutex.h>
20#include <linux/spinlock_types.h>
21#include <linux/types.h>
22#include <linux/wait.h>
23#include <linux/workqueue.h>
24
25#include <demux.h>
26#include <dmxdev.h>
27#include <dvb_demux.h>
28#include <dvb_frontend.h>
29#include <dvb_net.h>
30#include <dvbdev.h>
31
32struct firedtv_tuner_status {
33 unsigned active_system:8;
34 unsigned searching:1;
35 unsigned moving:1;
36 unsigned no_rf:1;
37 unsigned input:1;
38 unsigned selected_antenna:7;
39 unsigned ber:32;
40 unsigned signal_strength:8;
41 unsigned raster_frequency:2;
42 unsigned rf_frequency:22;
43 unsigned man_dep_info_length:8;
44 unsigned front_end_error:1;
45 unsigned antenna_error:1;
46 unsigned front_end_power_status:1;
47 unsigned power_supply:1;
48 unsigned carrier_noise_ratio:16;
49 unsigned power_supply_voltage:8;
50 unsigned antenna_voltage:8;
51 unsigned firewire_bus_voltage:8;
52 unsigned ca_mmi:1;
53 unsigned ca_pmt_reply:1;
54 unsigned ca_date_time_request:1;
55 unsigned ca_application_info:1;
56 unsigned ca_module_present_status:1;
57 unsigned ca_dvb_flag:1;
58 unsigned ca_error_flag:1;
59 unsigned ca_initialization_status:1;
60};
61
62enum model_type {
63 FIREDTV_UNKNOWN = 0,
64 FIREDTV_DVB_S = 1,
65 FIREDTV_DVB_C = 2,
66 FIREDTV_DVB_T = 3,
67 FIREDTV_DVB_S2 = 4,
68};
69
70struct device;
71struct input_dev;
72struct firedtv;
73
74struct firedtv_backend {
75 int (*lock)(struct firedtv *fdtv, u64 addr, void *data, __be32 arg);
76 int (*read)(struct firedtv *fdtv, u64 addr, void *data, size_t len);
77 int (*write)(struct firedtv *fdtv, u64 addr, void *data, size_t len);
78 int (*start_iso)(struct firedtv *fdtv);
79 void (*stop_iso)(struct firedtv *fdtv);
80};
81
82struct firedtv {
83 struct device *device;
84 struct list_head list;
85
86 struct dvb_adapter adapter;
87 struct dmxdev dmxdev;
88 struct dvb_demux demux;
89 struct dmx_frontend frontend;
90 struct dvb_net dvbnet;
91 struct dvb_frontend fe;
92
93 struct dvb_device *cadev;
94 int ca_last_command;
95 int ca_time_interval;
96
97 struct mutex avc_mutex;
98 wait_queue_head_t avc_wait;
99 bool avc_reply_received;
100 struct work_struct remote_ctrl_work;
101 struct input_dev *remote_ctrl_dev;
102
103 enum model_type type;
104 char subunit;
105 char isochannel;
106 fe_sec_voltage_t voltage;
107 fe_sec_tone_mode_t tone;
108
109 const struct firedtv_backend *backend;
110 void *backend_data;
111
112 struct mutex demux_mutex;
113 unsigned long channel_active;
114 u16 channel_pid[16];
115
116 size_t response_length;
117 u8 response[512];
118};
119
120/* firedtv-1394.c */
121#ifdef CONFIG_DVB_FIREDTV_IEEE1394
122int fdtv_1394_init(struct ieee1394_device_id id_table[]);
123void fdtv_1394_exit(void);
124#else
125static inline int fdtv_1394_init(struct ieee1394_device_id it[]) { return 0; }
126static inline void fdtv_1394_exit(void) {}
127#endif
128
129/* firedtv-avc.c */
130int avc_recv(struct firedtv *fdtv, void *data, size_t length);
131int avc_tuner_status(struct firedtv *fdtv, struct firedtv_tuner_status *stat);
132struct dvb_frontend_parameters;
133int avc_tuner_dsd(struct firedtv *fdtv, struct dvb_frontend_parameters *params);
134int avc_tuner_set_pids(struct firedtv *fdtv, unsigned char pidc, u16 pid[]);
135int avc_tuner_get_ts(struct firedtv *fdtv);
136int avc_identify_subunit(struct firedtv *fdtv);
137struct dvb_diseqc_master_cmd;
138int avc_lnb_control(struct firedtv *fdtv, char voltage, char burst,
139 char conttone, char nrdiseq,
140 struct dvb_diseqc_master_cmd *diseqcmd);
141void avc_remote_ctrl_work(struct work_struct *work);
142int avc_register_remote_control(struct firedtv *fdtv);
143int avc_ca_app_info(struct firedtv *fdtv, char *app_info, unsigned int *len);
144int avc_ca_info(struct firedtv *fdtv, char *app_info, unsigned int *len);
145int avc_ca_reset(struct firedtv *fdtv);
146int avc_ca_pmt(struct firedtv *fdtv, char *app_info, int length);
147int avc_ca_get_time_date(struct firedtv *fdtv, int *interval);
148int avc_ca_enter_menu(struct firedtv *fdtv);
149int avc_ca_get_mmi(struct firedtv *fdtv, char *mmi_object, unsigned int *len);
150int cmp_establish_pp_connection(struct firedtv *fdtv, int plug, int channel);
151void cmp_break_pp_connection(struct firedtv *fdtv, int plug, int channel);
152
153/* firedtv-ci.c */
154int fdtv_ca_register(struct firedtv *fdtv);
155void fdtv_ca_release(struct firedtv *fdtv);
156
157/* firedtv-dvb.c */
158int fdtv_start_feed(struct dvb_demux_feed *dvbdmxfeed);
159int fdtv_stop_feed(struct dvb_demux_feed *dvbdmxfeed);
160int fdtv_dvb_register(struct firedtv *fdtv);
161void fdtv_dvb_unregister(struct firedtv *fdtv);
162struct firedtv *fdtv_alloc(struct device *dev,
163 const struct firedtv_backend *backend,
164 const char *name, size_t name_len);
165extern const char *fdtv_model_names[];
166
167/* firedtv-fe.c */
168void fdtv_frontend_init(struct firedtv *fdtv);
169
170/* firedtv-rc.c */
171#ifdef CONFIG_DVB_FIREDTV_INPUT
172int fdtv_register_rc(struct firedtv *fdtv, struct device *dev);
173void fdtv_unregister_rc(struct firedtv *fdtv);
174void fdtv_handle_rc(struct firedtv *fdtv, unsigned int code);
175#else
176static inline int fdtv_register_rc(struct firedtv *fdtv,
177 struct device *dev) { return 0; }
178static inline void fdtv_unregister_rc(struct firedtv *fdtv) {}
179static inline void fdtv_handle_rc(struct firedtv *fdtv, unsigned int code) {}
180#endif
181
182#endif /* _FIREDTV_H */
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 6bdfd47d679d..a2f185fd7072 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2342,6 +2342,17 @@ config ATL1E
2342 To compile this driver as a module, choose M here. The module 2342 To compile this driver as a module, choose M here. The module
2343 will be called atl1e. 2343 will be called atl1e.
2344 2344
2345config ATL1C
2346 tristate "Atheros L1C Gigabit Ethernet support (EXPERIMENTAL)"
2347 depends on PCI && EXPERIMENTAL
2348 select CRC32
2349 select MII
2350 help
2351 This driver supports the Atheros L1C gigabit ethernet adapter.
2352
2353 To compile this driver as a module, choose M here. The module
2354 will be called atl1c.
2355
2345config JME 2356config JME
2346 tristate "JMicron(R) PCI-Express Gigabit Ethernet support" 2357 tristate "JMicron(R) PCI-Express Gigabit Ethernet support"
2347 depends on PCI 2358 depends on PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index a3c5c002f224..aca8492db654 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_BONDING) += bonding/
17obj-$(CONFIG_ATL1) += atlx/ 17obj-$(CONFIG_ATL1) += atlx/
18obj-$(CONFIG_ATL2) += atlx/ 18obj-$(CONFIG_ATL2) += atlx/
19obj-$(CONFIG_ATL1E) += atl1e/ 19obj-$(CONFIG_ATL1E) += atl1e/
20obj-$(CONFIG_ATL1C) += atl1c/
20obj-$(CONFIG_GIANFAR) += gianfar_driver.o 21obj-$(CONFIG_GIANFAR) += gianfar_driver.o
21obj-$(CONFIG_TEHUTI) += tehuti.o 22obj-$(CONFIG_TEHUTI) += tehuti.o
22obj-$(CONFIG_ENIC) += enic/ 23obj-$(CONFIG_ENIC) += enic/
diff --git a/drivers/net/atl1c/Makefile b/drivers/net/atl1c/Makefile
new file mode 100644
index 000000000000..c37d966952ee
--- /dev/null
+++ b/drivers/net/atl1c/Makefile
@@ -0,0 +1,2 @@
1obj-$(CONFIG_ATL1C) += atl1c.o
2atl1c-objs := atl1c_main.o atl1c_hw.o atl1c_ethtool.o
diff --git a/drivers/net/atl1c/atl1c.h b/drivers/net/atl1c/atl1c.h
new file mode 100644
index 000000000000..ac11b84b8377
--- /dev/null
+++ b/drivers/net/atl1c/atl1c.h
@@ -0,0 +1,606 @@
1/*
2 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef _ATL1C_H_
23#define _ATL1C_H_
24
25#include <linux/version.h>
26#include <linux/init.h>
27#include <linux/types.h>
28#include <linux/errno.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/ioport.h>
35#include <linux/slab.h>
36#include <linux/list.h>
37#include <linux/delay.h>
38#include <linux/sched.h>
39#include <linux/in.h>
40#include <linux/ip.h>
41#include <linux/ipv6.h>
42#include <linux/udp.h>
43#include <linux/mii.h>
44#include <linux/io.h>
45#include <linux/vmalloc.h>
46#include <linux/pagemap.h>
47#include <linux/tcp.h>
48#include <linux/mii.h>
49#include <linux/ethtool.h>
50#include <linux/if_vlan.h>
51#include <linux/workqueue.h>
52#include <net/checksum.h>
53#include <net/ip6_checksum.h>
54
55#include "atl1c_hw.h"
56
57/* Wake Up Filter Control */
58#define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
59#define AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
60#define AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
61#define AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
62#define AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
63
64#define AT_VLAN_TO_TAG(_vlan, _tag) \
65 _tag = ((((_vlan) >> 8) & 0xFF) |\
66 (((_vlan) & 0xFF) << 8))
67
68#define AT_TAG_TO_VLAN(_tag, _vlan) \
69 _vlan = ((((_tag) >> 8) & 0xFF) |\
70 (((_tag) & 0xFF) << 8))
71
72#define SPEED_0 0xffff
73#define HALF_DUPLEX 1
74#define FULL_DUPLEX 2
75
76#define AT_RX_BUF_SIZE (ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN)
77#define MAX_JUMBO_FRAME_SIZE (9*1024)
78#define MAX_TX_OFFLOAD_THRESH (9*1024)
79
80#define AT_MAX_RECEIVE_QUEUE 4
81#define AT_DEF_RECEIVE_QUEUE 1
82#define AT_MAX_TRANSMIT_QUEUE 2
83
84#define AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL
85#define AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL
86
87#define AT_TX_WATCHDOG (5 * HZ)
88#define AT_MAX_INT_WORK 5
89#define AT_TWSI_EEPROM_TIMEOUT 100
90#define AT_HW_MAX_IDLE_DELAY 10
91#define AT_SUSPEND_LINK_TIMEOUT 28
92
93#define AT_ASPM_L0S_TIMER 6
94#define AT_ASPM_L1_TIMER 12
95
96#define ATL1C_PCIE_L0S_L1_DISABLE 0x01
97#define ATL1C_PCIE_PHY_RESET 0x02
98
99#define ATL1C_ASPM_L0s_ENABLE 0x0001
100#define ATL1C_ASPM_L1_ENABLE 0x0002
101
102#define AT_REGS_LEN (75 * sizeof(u32))
103#define AT_EEPROM_LEN 512
104
105#define ATL1C_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
106#define ATL1C_RFD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_rx_free_desc)
107#define ATL1C_TPD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_tpd_desc)
108#define ATL1C_RRD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_recv_ret_status)
109
110/* tpd word 1 bit 0:7 General Checksum task offload */
111#define TPD_L4HDR_OFFSET_MASK 0x00FF
112#define TPD_L4HDR_OFFSET_SHIFT 0
113
114/* tpd word 1 bit 0:7 Large Send task offload (IPv4/IPV6) */
115#define TPD_TCPHDR_OFFSET_MASK 0x00FF
116#define TPD_TCPHDR_OFFSET_SHIFT 0
117
118/* tpd word 1 bit 0:7 Custom Checksum task offload */
119#define TPD_PLOADOFFSET_MASK 0x00FF
120#define TPD_PLOADOFFSET_SHIFT 0
121
122/* tpd word 1 bit 8:17 */
123#define TPD_CCSUM_EN_MASK 0x0001
124#define TPD_CCSUM_EN_SHIFT 8
125#define TPD_IP_CSUM_MASK 0x0001
126#define TPD_IP_CSUM_SHIFT 9
127#define TPD_TCP_CSUM_MASK 0x0001
128#define TPD_TCP_CSUM_SHIFT 10
129#define TPD_UDP_CSUM_MASK 0x0001
130#define TPD_UDP_CSUM_SHIFT 11
131#define TPD_LSO_EN_MASK 0x0001 /* TCP Large Send Offload */
132#define TPD_LSO_EN_SHIFT 12
133#define TPD_LSO_VER_MASK 0x0001
134#define TPD_LSO_VER_SHIFT 13 /* 0 : ipv4; 1 : ipv4/ipv6 */
135#define TPD_CON_VTAG_MASK 0x0001
136#define TPD_CON_VTAG_SHIFT 14
137#define TPD_INS_VTAG_MASK 0x0001
138#define TPD_INS_VTAG_SHIFT 15
139#define TPD_IPV4_PACKET_MASK 0x0001 /* valid when LSO VER is 1 */
140#define TPD_IPV4_PACKET_SHIFT 16
141#define TPD_ETH_TYPE_MASK 0x0001
142#define TPD_ETH_TYPE_SHIFT 17 /* 0 : 802.3 frame; 1 : Ethernet */
143
144/* tpd word 18:25 Custom Checksum task offload */
145#define TPD_CCSUM_OFFSET_MASK 0x00FF
146#define TPD_CCSUM_OFFSET_SHIFT 18
147#define TPD_CCSUM_EPAD_MASK 0x0001
148#define TPD_CCSUM_EPAD_SHIFT 30
149
150/* tpd word 18:30 Large Send task offload (IPv4/IPV6) */
151#define TPD_MSS_MASK 0x1FFF
152#define TPD_MSS_SHIFT 18
153
154#define TPD_EOP_MASK 0x0001
155#define TPD_EOP_SHIFT 31
156
157struct atl1c_tpd_desc {
158 __le16 buffer_len; /* include 4-byte CRC */
159 __le16 vlan_tag;
160 __le32 word1;
161 __le64 buffer_addr;
162};
163
164struct atl1c_tpd_ext_desc {
165 u32 reservd_0;
166 __le32 word1;
167 __le32 pkt_len;
168 u32 reservd_1;
169};
170/* rrs word 0 bit 0:31 */
171#define RRS_RX_CSUM_MASK 0xFFFF
172#define RRS_RX_CSUM_SHIFT 0
173#define RRS_RX_RFD_CNT_MASK 0x000F
174#define RRS_RX_RFD_CNT_SHIFT 16
175#define RRS_RX_RFD_INDEX_MASK 0x0FFF
176#define RRS_RX_RFD_INDEX_SHIFT 20
177
178/* rrs flag bit 0:16 */
179#define RRS_HEAD_LEN_MASK 0x00FF
180#define RRS_HEAD_LEN_SHIFT 0
181#define RRS_HDS_TYPE_MASK 0x0003
182#define RRS_HDS_TYPE_SHIFT 8
183#define RRS_CPU_NUM_MASK 0x0003
184#define RRS_CPU_NUM_SHIFT 10
185#define RRS_HASH_FLG_MASK 0x000F
186#define RRS_HASH_FLG_SHIFT 12
187
188#define RRS_HDS_TYPE_HEAD 1
189#define RRS_HDS_TYPE_DATA 2
190
191#define RRS_IS_NO_HDS_TYPE(flag) \
192 (((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK == 0)
193
194#define RRS_IS_HDS_HEAD(flag) \
195 (((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK == \
196 RRS_HDS_TYPE_HEAD)
197
198#define RRS_IS_HDS_DATA(flag) \
199 (((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK == \
200 RRS_HDS_TYPE_DATA)
201
202/* rrs word 3 bit 0:31 */
203#define RRS_PKT_SIZE_MASK 0x3FFF
204#define RRS_PKT_SIZE_SHIFT 0
205#define RRS_ERR_L4_CSUM_MASK 0x0001
206#define RRS_ERR_L4_CSUM_SHIFT 14
207#define RRS_ERR_IP_CSUM_MASK 0x0001
208#define RRS_ERR_IP_CSUM_SHIFT 15
209#define RRS_VLAN_INS_MASK 0x0001
210#define RRS_VLAN_INS_SHIFT 16
211#define RRS_PROT_ID_MASK 0x0007
212#define RRS_PROT_ID_SHIFT 17
213#define RRS_RX_ERR_SUM_MASK 0x0001
214#define RRS_RX_ERR_SUM_SHIFT 20
215#define RRS_RX_ERR_CRC_MASK 0x0001
216#define RRS_RX_ERR_CRC_SHIFT 21
217#define RRS_RX_ERR_FAE_MASK 0x0001
218#define RRS_RX_ERR_FAE_SHIFT 22
219#define RRS_RX_ERR_TRUNC_MASK 0x0001
220#define RRS_RX_ERR_TRUNC_SHIFT 23
221#define RRS_RX_ERR_RUNC_MASK 0x0001
222#define RRS_RX_ERR_RUNC_SHIFT 24
223#define RRS_RX_ERR_ICMP_MASK 0x0001
224#define RRS_RX_ERR_ICMP_SHIFT 25
225#define RRS_PACKET_BCAST_MASK 0x0001
226#define RRS_PACKET_BCAST_SHIFT 26
227#define RRS_PACKET_MCAST_MASK 0x0001
228#define RRS_PACKET_MCAST_SHIFT 27
229#define RRS_PACKET_TYPE_MASK 0x0001
230#define RRS_PACKET_TYPE_SHIFT 28
231#define RRS_FIFO_FULL_MASK 0x0001
232#define RRS_FIFO_FULL_SHIFT 29
233#define RRS_802_3_LEN_ERR_MASK 0x0001
234#define RRS_802_3_LEN_ERR_SHIFT 30
235#define RRS_RXD_UPDATED_MASK 0x0001
236#define RRS_RXD_UPDATED_SHIFT 31
237
238#define RRS_ERR_L4_CSUM 0x00004000
239#define RRS_ERR_IP_CSUM 0x00008000
240#define RRS_VLAN_INS 0x00010000
241#define RRS_RX_ERR_SUM 0x00100000
242#define RRS_RX_ERR_CRC 0x00200000
243#define RRS_802_3_LEN_ERR 0x40000000
244#define RRS_RXD_UPDATED 0x80000000
245
246#define RRS_PACKET_TYPE_802_3 1
247#define RRS_PACKET_TYPE_ETH 0
248#define RRS_PACKET_IS_ETH(word) \
249 (((word) >> RRS_PACKET_TYPE_SHIFT) & RRS_PACKET_TYPE_MASK == \
250 RRS_PACKET_TYPE_ETH)
251#define RRS_RXD_IS_VALID(word) \
252 ((((word) >> RRS_RXD_UPDATED_SHIFT) & RRS_RXD_UPDATED_MASK) == 1)
253
254#define RRS_PACKET_PROT_IS_IPV4_ONLY(word) \
255 ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 1)
256#define RRS_PACKET_PROT_IS_IPV6_ONLY(word) \
257 ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 6)
258
259struct atl1c_recv_ret_status {
260 __le32 word0;
261 __le32 rss_hash;
262 __le16 vlan_tag;
263 __le16 flag;
264 __le32 word3;
265};
266
267/* RFD desciptor */
268struct atl1c_rx_free_desc {
269 __le64 buffer_addr;
270};
271
272/* DMA Order Settings */
273enum atl1c_dma_order {
274 atl1c_dma_ord_in = 1,
275 atl1c_dma_ord_enh = 2,
276 atl1c_dma_ord_out = 4
277};
278
279enum atl1c_dma_rcb {
280 atl1c_rcb_64 = 0,
281 atl1c_rcb_128 = 1
282};
283
284enum atl1c_mac_speed {
285 atl1c_mac_speed_0 = 0,
286 atl1c_mac_speed_10_100 = 1,
287 atl1c_mac_speed_1000 = 2
288};
289
290enum atl1c_dma_req_block {
291 atl1c_dma_req_128 = 0,
292 atl1c_dma_req_256 = 1,
293 atl1c_dma_req_512 = 2,
294 atl1c_dma_req_1024 = 3,
295 atl1c_dma_req_2048 = 4,
296 atl1c_dma_req_4096 = 5
297};
298
299enum atl1c_rss_mode {
300 atl1c_rss_mode_disable = 0,
301 atl1c_rss_sig_que = 1,
302 atl1c_rss_mul_que_sig_int = 2,
303 atl1c_rss_mul_que_mul_int = 4,
304};
305
306enum atl1c_rss_type {
307 atl1c_rss_disable = 0,
308 atl1c_rss_ipv4 = 1,
309 atl1c_rss_ipv4_tcp = 2,
310 atl1c_rss_ipv6 = 4,
311 atl1c_rss_ipv6_tcp = 8
312};
313
314enum atl1c_nic_type {
315 athr_l1c = 0,
316 athr_l2c = 1,
317};
318
319enum atl1c_trans_queue {
320 atl1c_trans_normal = 0,
321 atl1c_trans_high = 1
322};
323
324struct atl1c_hw_stats {
325 /* rx */
326 unsigned long rx_ok; /* The number of good packet received. */
327 unsigned long rx_bcast; /* The number of good broadcast packet received. */
328 unsigned long rx_mcast; /* The number of good multicast packet received. */
329 unsigned long rx_pause; /* The number of Pause packet received. */
330 unsigned long rx_ctrl; /* The number of Control packet received other than Pause frame. */
331 unsigned long rx_fcs_err; /* The number of packets with bad FCS. */
332 unsigned long rx_len_err; /* The number of packets with mismatch of length field and actual size. */
333 unsigned long rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */
334 unsigned long rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */
335 unsigned long rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */
336 unsigned long rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */
337 unsigned long rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */
338 unsigned long rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */
339 unsigned long rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */
340 unsigned long rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */
341 unsigned long rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
342 unsigned long rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */
343 unsigned long rx_sz_ov; /* The number of good and bad packets received that are more than MTU size truncated by Selene. */
344 unsigned long rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */
345 unsigned long rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */
346 unsigned long rx_align_err; /* Alignment Error */
347 unsigned long rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */
348 unsigned long rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */
349 unsigned long rx_err_addr; /* The number of packets dropped due to address filtering. */
350
351 /* tx */
352 unsigned long tx_ok; /* The number of good packet transmitted. */
353 unsigned long tx_bcast; /* The number of good broadcast packet transmitted. */
354 unsigned long tx_mcast; /* The number of good multicast packet transmitted. */
355 unsigned long tx_pause; /* The number of Pause packet transmitted. */
356 unsigned long tx_exc_defer; /* The number of packets transmitted with excessive deferral. */
357 unsigned long tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */
358 unsigned long tx_defer; /* The number of packets transmitted that is deferred. */
359 unsigned long tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */
360 unsigned long tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */
361 unsigned long tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
362 unsigned long tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
363 unsigned long tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
364 unsigned long tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
365 unsigned long tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
366 unsigned long tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
367 unsigned long tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */
368 unsigned long tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
369 unsigned long tx_late_col; /* The number of packets transmitted with late collisions. */
370 unsigned long tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */
371 unsigned long tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
372 unsigned long tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
373 unsigned long tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */
374 unsigned long tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */
375 unsigned long tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */
376 unsigned long tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */
377};
378
379struct atl1c_hw {
380 u8 __iomem *hw_addr; /* inner register address */
381 struct atl1c_adapter *adapter;
382 enum atl1c_nic_type nic_type;
383 enum atl1c_dma_order dma_order;
384 enum atl1c_dma_rcb rcb_value;
385 enum atl1c_dma_req_block dmar_block;
386 enum atl1c_dma_req_block dmaw_block;
387
388 u16 device_id;
389 u16 vendor_id;
390 u16 subsystem_id;
391 u16 subsystem_vendor_id;
392 u8 revision_id;
393
394 u32 intr_mask;
395 u8 dmaw_dly_cnt;
396 u8 dmar_dly_cnt;
397
398 u8 preamble_len;
399 u16 max_frame_size;
400 u16 min_frame_size;
401
402 enum atl1c_mac_speed mac_speed;
403 bool mac_duplex;
404 bool hibernate;
405 u16 media_type;
406#define MEDIA_TYPE_AUTO_SENSOR 0
407#define MEDIA_TYPE_100M_FULL 1
408#define MEDIA_TYPE_100M_HALF 2
409#define MEDIA_TYPE_10M_FULL 3
410#define MEDIA_TYPE_10M_HALF 4
411
412 u16 autoneg_advertised;
413 u16 mii_autoneg_adv_reg;
414 u16 mii_1000t_ctrl_reg;
415
416 u16 tx_imt; /* TX Interrupt Moderator timer ( 2us resolution) */
417 u16 rx_imt; /* RX Interrupt Moderator timer ( 2us resolution) */
418 u16 ict; /* Interrupt Clear timer (2us resolution) */
419 u16 ctrl_flags;
420#define ATL1C_INTR_CLEAR_ON_READ 0x0001
421#define ATL1C_INTR_MODRT_ENABLE 0x0002
422#define ATL1C_CMB_ENABLE 0x0004
423#define ATL1C_SMB_ENABLE 0x0010
424#define ATL1C_TXQ_MODE_ENHANCE 0x0020
425#define ATL1C_RX_IPV6_CHKSUM 0x0040
426#define ATL1C_ASPM_L0S_SUPPORT 0x0080
427#define ATL1C_ASPM_L1_SUPPORT 0x0100
428#define ATL1C_ASPM_CTRL_MON 0x0200
429#define ATL1C_HIB_DISABLE 0x0400
430#define ATL1C_LINK_CAP_1000M 0x0800
431#define ATL1C_FPGA_VERSION 0x8000
432 u16 cmb_tpd;
433 u16 cmb_rrd;
434 u16 cmb_rx_timer; /* 2us resolution */
435 u16 cmb_tx_timer;
436 u32 smb_timer;
437
438 u16 rrd_thresh; /* Threshold of number of RRD produced to trigger
439 interrupt request */
440 u16 tpd_thresh;
441 u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned burst. */
442 u8 rfd_burst;
443 enum atl1c_rss_type rss_type;
444 enum atl1c_rss_mode rss_mode;
445 u8 rss_hash_bits;
446 u32 base_cpu;
447 u32 indirect_tab;
448 u8 mac_addr[ETH_ALEN];
449 u8 perm_mac_addr[ETH_ALEN];
450
451 bool phy_configured;
452 bool re_autoneg;
453 bool emi_ca;
454};
455
456/*
457 * atl1c_ring_header represents a single, contiguous block of DMA space
458 * mapped for the three descriptor rings (tpd, rfd, rrd) and the two
459 * message blocks (cmb, smb) described below
460 */
461struct atl1c_ring_header {
462 void *desc; /* virtual address */
463 dma_addr_t dma; /* physical address*/
464 unsigned int size; /* length in bytes */
465};
466
467/*
468 * atl1c_buffer is wrapper around a pointer to a socket buffer
469 * so a DMA handle can be stored along with the skb
470 */
471struct atl1c_buffer {
472 struct sk_buff *skb; /* socket buffer */
473 u16 length; /* rx buffer length */
474 u16 state; /* state of buffer */
475#define ATL1_BUFFER_FREE 0
476#define ATL1_BUFFER_BUSY 1
477 dma_addr_t dma;
478};
479
480/* transimit packet descriptor (tpd) ring */
481struct atl1c_tpd_ring {
482 void *desc; /* descriptor ring virtual address */
483 dma_addr_t dma; /* descriptor ring physical address */
484 u16 size; /* descriptor ring length in bytes */
485 u16 count; /* number of descriptors in the ring */
486 u16 next_to_use; /* this is protectd by adapter->tx_lock */
487 atomic_t next_to_clean;
488 struct atl1c_buffer *buffer_info;
489};
490
491/* receive free descriptor (rfd) ring */
492struct atl1c_rfd_ring {
493 void *desc; /* descriptor ring virtual address */
494 dma_addr_t dma; /* descriptor ring physical address */
495 u16 size; /* descriptor ring length in bytes */
496 u16 count; /* number of descriptors in the ring */
497 u16 next_to_use;
498 u16 next_to_clean;
499 struct atl1c_buffer *buffer_info;
500};
501
502/* receive return desciptor (rrd) ring */
503struct atl1c_rrd_ring {
504 void *desc; /* descriptor ring virtual address */
505 dma_addr_t dma; /* descriptor ring physical address */
506 u16 size; /* descriptor ring length in bytes */
507 u16 count; /* number of descriptors in the ring */
508 u16 next_to_use;
509 u16 next_to_clean;
510};
511
512struct atl1c_cmb {
513 void *cmb;
514 dma_addr_t dma;
515};
516
517struct atl1c_smb {
518 void *smb;
519 dma_addr_t dma;
520};
521
522/* board specific private data structure */
523struct atl1c_adapter {
524 struct net_device *netdev;
525 struct pci_dev *pdev;
526 struct vlan_group *vlgrp;
527 struct napi_struct napi;
528 struct atl1c_hw hw;
529 struct atl1c_hw_stats hw_stats;
530 struct net_device_stats net_stats;
531 struct mii_if_info mii; /* MII interface info */
532 u16 rx_buffer_len;
533
534 unsigned long flags;
535#define __AT_TESTING 0x0001
536#define __AT_RESETTING 0x0002
537#define __AT_DOWN 0x0003
538 u32 msg_enable;
539
540 bool have_msi;
541 u32 wol;
542 u16 link_speed;
543 u16 link_duplex;
544
545 spinlock_t mdio_lock;
546 spinlock_t tx_lock;
547 atomic_t irq_sem;
548
549 struct work_struct reset_task;
550 struct work_struct link_chg_task;
551 struct timer_list watchdog_timer;
552 struct timer_list phy_config_timer;
553
554 /* All Descriptor memory */
555 struct atl1c_ring_header ring_header;
556 struct atl1c_tpd_ring tpd_ring[AT_MAX_TRANSMIT_QUEUE];
557 struct atl1c_rfd_ring rfd_ring[AT_MAX_RECEIVE_QUEUE];
558 struct atl1c_rrd_ring rrd_ring[AT_MAX_RECEIVE_QUEUE];
559 struct atl1c_cmb cmb;
560 struct atl1c_smb smb;
561 int num_rx_queues;
562 u32 bd_number; /* board number;*/
563};
564
565#define AT_WRITE_REG(a, reg, value) ( \
566 writel((value), ((a)->hw_addr + reg)))
567
568#define AT_WRITE_FLUSH(a) (\
569 readl((a)->hw_addr))
570
571#define AT_READ_REG(a, reg, pdata) do { \
572 if (unlikely((a)->hibernate)) { \
573 readl((a)->hw_addr + reg); \
574 *(u32 *)pdata = readl((a)->hw_addr + reg); \
575 } else { \
576 *(u32 *)pdata = readl((a)->hw_addr + reg); \
577 } \
578 } while (0)
579
580#define AT_WRITE_REGB(a, reg, value) (\
581 writeb((value), ((a)->hw_addr + reg)))
582
583#define AT_READ_REGB(a, reg) (\
584 readb((a)->hw_addr + reg))
585
586#define AT_WRITE_REGW(a, reg, value) (\
587 writew((value), ((a)->hw_addr + reg)))
588
589#define AT_READ_REGW(a, reg) (\
590 readw((a)->hw_addr + reg))
591
592#define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \
593 writel((value), (((a)->hw_addr + reg) + ((offset) << 2))))
594
595#define AT_READ_REG_ARRAY(a, reg, offset) ( \
596 readl(((a)->hw_addr + reg) + ((offset) << 2)))
597
598extern char atl1c_driver_name[];
599extern char atl1c_driver_version[];
600
601extern int atl1c_up(struct atl1c_adapter *adapter);
602extern void atl1c_down(struct atl1c_adapter *adapter);
603extern void atl1c_reinit_locked(struct atl1c_adapter *adapter);
604extern s32 atl1c_reset_hw(struct atl1c_hw *hw);
605extern void atl1c_set_ethtool_ops(struct net_device *netdev);
606#endif /* _ATL1C_H_ */
diff --git a/drivers/net/atl1c/atl1c_ethtool.c b/drivers/net/atl1c/atl1c_ethtool.c
new file mode 100644
index 000000000000..45c5b7332cd3
--- /dev/null
+++ b/drivers/net/atl1c/atl1c_ethtool.c
@@ -0,0 +1,317 @@
1/*
2 * Copyright(c) 2009 - 2009 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 *
21 */
22
23#include <linux/netdevice.h>
24#include <linux/ethtool.h>
25
26#include "atl1c.h"
27
28static int atl1c_get_settings(struct net_device *netdev,
29 struct ethtool_cmd *ecmd)
30{
31 struct atl1c_adapter *adapter = netdev_priv(netdev);
32 struct atl1c_hw *hw = &adapter->hw;
33
34 ecmd->supported = (SUPPORTED_10baseT_Half |
35 SUPPORTED_10baseT_Full |
36 SUPPORTED_100baseT_Half |
37 SUPPORTED_100baseT_Full |
38 SUPPORTED_Autoneg |
39 SUPPORTED_TP);
40 if (hw->ctrl_flags & ATL1C_LINK_CAP_1000M)
41 ecmd->supported |= SUPPORTED_1000baseT_Full;
42
43 ecmd->advertising = ADVERTISED_TP;
44
45 ecmd->advertising |= hw->autoneg_advertised;
46
47 ecmd->port = PORT_TP;
48 ecmd->phy_address = 0;
49 ecmd->transceiver = XCVR_INTERNAL;
50
51 if (adapter->link_speed != SPEED_0) {
52 ecmd->speed = adapter->link_speed;
53 if (adapter->link_duplex == FULL_DUPLEX)
54 ecmd->duplex = DUPLEX_FULL;
55 else
56 ecmd->duplex = DUPLEX_HALF;
57 } else {
58 ecmd->speed = -1;
59 ecmd->duplex = -1;
60 }
61
62 ecmd->autoneg = AUTONEG_ENABLE;
63 return 0;
64}
65
66static int atl1c_set_settings(struct net_device *netdev,
67 struct ethtool_cmd *ecmd)
68{
69 struct atl1c_adapter *adapter = netdev_priv(netdev);
70 struct atl1c_hw *hw = &adapter->hw;
71 u16 autoneg_advertised;
72
73 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
74 msleep(1);
75
76 if (ecmd->autoneg == AUTONEG_ENABLE) {
77 autoneg_advertised = ADVERTISED_Autoneg;
78 } else {
79 if (ecmd->speed == SPEED_1000) {
80 if (ecmd->duplex != DUPLEX_FULL) {
81 if (netif_msg_link(adapter))
82 dev_warn(&adapter->pdev->dev,
83 "1000M half is invalid\n");
84 clear_bit(__AT_RESETTING, &adapter->flags);
85 return -EINVAL;
86 }
87 autoneg_advertised = ADVERTISED_1000baseT_Full;
88 } else if (ecmd->speed == SPEED_100) {
89 if (ecmd->duplex == DUPLEX_FULL)
90 autoneg_advertised = ADVERTISED_100baseT_Full;
91 else
92 autoneg_advertised = ADVERTISED_100baseT_Half;
93 } else {
94 if (ecmd->duplex == DUPLEX_FULL)
95 autoneg_advertised = ADVERTISED_10baseT_Full;
96 else
97 autoneg_advertised = ADVERTISED_10baseT_Half;
98 }
99 }
100
101 if (hw->autoneg_advertised != autoneg_advertised) {
102 hw->autoneg_advertised = autoneg_advertised;
103 if (atl1c_restart_autoneg(hw) != 0) {
104 if (netif_msg_link(adapter))
105 dev_warn(&adapter->pdev->dev,
106 "ethtool speed/duplex setting failed\n");
107 clear_bit(__AT_RESETTING, &adapter->flags);
108 return -EINVAL;
109 }
110 }
111 clear_bit(__AT_RESETTING, &adapter->flags);
112 return 0;
113}
114
115static u32 atl1c_get_tx_csum(struct net_device *netdev)
116{
117 return (netdev->features & NETIF_F_HW_CSUM) != 0;
118}
119
120static u32 atl1c_get_msglevel(struct net_device *netdev)
121{
122 struct atl1c_adapter *adapter = netdev_priv(netdev);
123 return adapter->msg_enable;
124}
125
126static void atl1c_set_msglevel(struct net_device *netdev, u32 data)
127{
128 struct atl1c_adapter *adapter = netdev_priv(netdev);
129 adapter->msg_enable = data;
130}
131
132static int atl1c_get_regs_len(struct net_device *netdev)
133{
134 return AT_REGS_LEN;
135}
136
137static void atl1c_get_regs(struct net_device *netdev,
138 struct ethtool_regs *regs, void *p)
139{
140 struct atl1c_adapter *adapter = netdev_priv(netdev);
141 struct atl1c_hw *hw = &adapter->hw;
142 u32 *regs_buff = p;
143 u16 phy_data;
144
145 memset(p, 0, AT_REGS_LEN);
146
147 regs->version = 0;
148 AT_READ_REG(hw, REG_VPD_CAP, p++);
149 AT_READ_REG(hw, REG_PM_CTRL, p++);
150 AT_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL, p++);
151 AT_READ_REG(hw, REG_TWSI_CTRL, p++);
152 AT_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL, p++);
153 AT_READ_REG(hw, REG_MASTER_CTRL, p++);
154 AT_READ_REG(hw, REG_MANUAL_TIMER_INIT, p++);
155 AT_READ_REG(hw, REG_IRQ_MODRT_TIMER_INIT, p++);
156 AT_READ_REG(hw, REG_GPHY_CTRL, p++);
157 AT_READ_REG(hw, REG_LINK_CTRL, p++);
158 AT_READ_REG(hw, REG_IDLE_STATUS, p++);
159 AT_READ_REG(hw, REG_MDIO_CTRL, p++);
160 AT_READ_REG(hw, REG_SERDES_LOCK, p++);
161 AT_READ_REG(hw, REG_MAC_CTRL, p++);
162 AT_READ_REG(hw, REG_MAC_IPG_IFG, p++);
163 AT_READ_REG(hw, REG_MAC_STA_ADDR, p++);
164 AT_READ_REG(hw, REG_MAC_STA_ADDR+4, p++);
165 AT_READ_REG(hw, REG_RX_HASH_TABLE, p++);
166 AT_READ_REG(hw, REG_RX_HASH_TABLE+4, p++);
167 AT_READ_REG(hw, REG_RXQ_CTRL, p++);
168 AT_READ_REG(hw, REG_TXQ_CTRL, p++);
169 AT_READ_REG(hw, REG_MTU, p++);
170 AT_READ_REG(hw, REG_WOL_CTRL, p++);
171
172 atl1c_read_phy_reg(hw, MII_BMCR, &phy_data);
173 regs_buff[73] = (u32) phy_data;
174 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
175 regs_buff[74] = (u32) phy_data;
176}
177
178static int atl1c_get_eeprom_len(struct net_device *netdev)
179{
180 struct atl1c_adapter *adapter = netdev_priv(netdev);
181
182 if (atl1c_check_eeprom_exist(&adapter->hw))
183 return AT_EEPROM_LEN;
184 else
185 return 0;
186}
187
188static int atl1c_get_eeprom(struct net_device *netdev,
189 struct ethtool_eeprom *eeprom, u8 *bytes)
190{
191 struct atl1c_adapter *adapter = netdev_priv(netdev);
192 struct atl1c_hw *hw = &adapter->hw;
193 u32 *eeprom_buff;
194 int first_dword, last_dword;
195 int ret_val = 0;
196 int i;
197
198 if (eeprom->len == 0)
199 return -EINVAL;
200
201 if (!atl1c_check_eeprom_exist(hw)) /* not exist */
202 return -EINVAL;
203
204 eeprom->magic = adapter->pdev->vendor |
205 (adapter->pdev->device << 16);
206
207 first_dword = eeprom->offset >> 2;
208 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
209
210 eeprom_buff = kmalloc(sizeof(u32) *
211 (last_dword - first_dword + 1), GFP_KERNEL);
212 if (eeprom_buff == NULL)
213 return -ENOMEM;
214
215 for (i = first_dword; i < last_dword; i++) {
216 if (!atl1c_read_eeprom(hw, i * 4, &(eeprom_buff[i-first_dword]))) {
217 kfree(eeprom_buff);
218 return -EIO;
219 }
220 }
221
222 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
223 eeprom->len);
224 kfree(eeprom_buff);
225
226 return ret_val;
227 return 0;
228}
229
230static void atl1c_get_drvinfo(struct net_device *netdev,
231 struct ethtool_drvinfo *drvinfo)
232{
233 struct atl1c_adapter *adapter = netdev_priv(netdev);
234
235 strncpy(drvinfo->driver, atl1c_driver_name, sizeof(drvinfo->driver));
236 strncpy(drvinfo->version, atl1c_driver_version,
237 sizeof(drvinfo->version));
238 strncpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
239 strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
240 sizeof(drvinfo->bus_info));
241 drvinfo->n_stats = 0;
242 drvinfo->testinfo_len = 0;
243 drvinfo->regdump_len = atl1c_get_regs_len(netdev);
244 drvinfo->eedump_len = atl1c_get_eeprom_len(netdev);
245}
246
247static void atl1c_get_wol(struct net_device *netdev,
248 struct ethtool_wolinfo *wol)
249{
250 struct atl1c_adapter *adapter = netdev_priv(netdev);
251
252 wol->supported = WAKE_MAGIC | WAKE_PHY;
253 wol->wolopts = 0;
254
255 if (adapter->wol & AT_WUFC_EX)
256 wol->wolopts |= WAKE_UCAST;
257 if (adapter->wol & AT_WUFC_MC)
258 wol->wolopts |= WAKE_MCAST;
259 if (adapter->wol & AT_WUFC_BC)
260 wol->wolopts |= WAKE_BCAST;
261 if (adapter->wol & AT_WUFC_MAG)
262 wol->wolopts |= WAKE_MAGIC;
263 if (adapter->wol & AT_WUFC_LNKC)
264 wol->wolopts |= WAKE_PHY;
265
266 return;
267}
268
269static int atl1c_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
270{
271 struct atl1c_adapter *adapter = netdev_priv(netdev);
272
273 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE |
274 WAKE_MCAST | WAKE_BCAST | WAKE_MCAST))
275 return -EOPNOTSUPP;
276 /* these settings will always override what we currently have */
277 adapter->wol = 0;
278
279 if (wol->wolopts & WAKE_MAGIC)
280 adapter->wol |= AT_WUFC_MAG;
281 if (wol->wolopts & WAKE_PHY)
282 adapter->wol |= AT_WUFC_LNKC;
283
284 return 0;
285}
286
287static int atl1c_nway_reset(struct net_device *netdev)
288{
289 struct atl1c_adapter *adapter = netdev_priv(netdev);
290 if (netif_running(netdev))
291 atl1c_reinit_locked(adapter);
292 return 0;
293}
294
295static struct ethtool_ops atl1c_ethtool_ops = {
296 .get_settings = atl1c_get_settings,
297 .set_settings = atl1c_set_settings,
298 .get_drvinfo = atl1c_get_drvinfo,
299 .get_regs_len = atl1c_get_regs_len,
300 .get_regs = atl1c_get_regs,
301 .get_wol = atl1c_get_wol,
302 .set_wol = atl1c_set_wol,
303 .get_msglevel = atl1c_get_msglevel,
304 .set_msglevel = atl1c_set_msglevel,
305 .nway_reset = atl1c_nway_reset,
306 .get_link = ethtool_op_get_link,
307 .get_eeprom_len = atl1c_get_eeprom_len,
308 .get_eeprom = atl1c_get_eeprom,
309 .get_tx_csum = atl1c_get_tx_csum,
310 .get_sg = ethtool_op_get_sg,
311 .set_sg = ethtool_op_set_sg,
312};
313
314void atl1c_set_ethtool_ops(struct net_device *netdev)
315{
316 SET_ETHTOOL_OPS(netdev, &atl1c_ethtool_ops);
317}
diff --git a/drivers/net/atl1c/atl1c_hw.c b/drivers/net/atl1c/atl1c_hw.c
new file mode 100644
index 000000000000..3e69b940b8f7
--- /dev/null
+++ b/drivers/net/atl1c/atl1c_hw.c
@@ -0,0 +1,527 @@
1/*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21#include <linux/pci.h>
22#include <linux/delay.h>
23#include <linux/mii.h>
24#include <linux/crc32.h>
25
26#include "atl1c.h"
27
28/*
29 * check_eeprom_exist
30 * return 1 if eeprom exist
31 */
32int atl1c_check_eeprom_exist(struct atl1c_hw *hw)
33{
34 u32 data;
35
36 AT_READ_REG(hw, REG_TWSI_DEBUG, &data);
37 if (data & TWSI_DEBUG_DEV_EXIST)
38 return 1;
39
40 return 0;
41}
42
43void atl1c_hw_set_mac_addr(struct atl1c_hw *hw)
44{
45 u32 value;
46 /*
47 * 00-0B-6A-F6-00-DC
48 * 0: 6AF600DC 1: 000B
49 * low dword
50 */
51 value = (((u32)hw->mac_addr[2]) << 24) |
52 (((u32)hw->mac_addr[3]) << 16) |
53 (((u32)hw->mac_addr[4]) << 8) |
54 (((u32)hw->mac_addr[5])) ;
55 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
56 /* hight dword */
57 value = (((u32)hw->mac_addr[0]) << 8) |
58 (((u32)hw->mac_addr[1])) ;
59 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
60}
61
62/*
63 * atl1c_get_permanent_address
64 * return 0 if get valid mac address,
65 */
66static int atl1c_get_permanent_address(struct atl1c_hw *hw)
67{
68 u32 addr[2];
69 u32 i;
70 u32 otp_ctrl_data;
71 u32 twsi_ctrl_data;
72 u8 eth_addr[ETH_ALEN];
73
74 /* init */
75 addr[0] = addr[1] = 0;
76 AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data);
77 if (atl1c_check_eeprom_exist(hw)) {
78 /* Enable OTP CLK */
79 if (!(otp_ctrl_data & OTP_CTRL_CLK_EN)) {
80 otp_ctrl_data |= OTP_CTRL_CLK_EN;
81 AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
82 AT_WRITE_FLUSH(hw);
83 msleep(1);
84 }
85
86 AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
87 twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART;
88 AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data);
89 for (i = 0; i < AT_TWSI_EEPROM_TIMEOUT; i++) {
90 msleep(10);
91 AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
92 if ((twsi_ctrl_data & TWSI_CTRL_SW_LDSTART) == 0)
93 break;
94 }
95 if (i >= AT_TWSI_EEPROM_TIMEOUT)
96 return -1;
97 }
98 /* Disable OTP_CLK */
99 if (otp_ctrl_data & OTP_CTRL_CLK_EN) {
100 otp_ctrl_data &= ~OTP_CTRL_CLK_EN;
101 AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
102 AT_WRITE_FLUSH(hw);
103 msleep(1);
104 }
105
106 /* maybe MAC-address is from BIOS */
107 AT_READ_REG(hw, REG_MAC_STA_ADDR, &addr[0]);
108 AT_READ_REG(hw, REG_MAC_STA_ADDR + 4, &addr[1]);
109 *(u32 *) &eth_addr[2] = swab32(addr[0]);
110 *(u16 *) &eth_addr[0] = swab16(*(u16 *)&addr[1]);
111
112 if (is_valid_ether_addr(eth_addr)) {
113 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
114 return 0;
115 }
116
117 return -1;
118}
119
120bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value)
121{
122 int i;
123 int ret = false;
124 u32 otp_ctrl_data;
125 u32 control;
126 u32 data;
127
128 if (offset & 3)
129 return ret; /* address do not align */
130
131 AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data);
132 if (!(otp_ctrl_data & OTP_CTRL_CLK_EN))
133 AT_WRITE_REG(hw, REG_OTP_CTRL,
134 (otp_ctrl_data | OTP_CTRL_CLK_EN));
135
136 AT_WRITE_REG(hw, REG_EEPROM_DATA_LO, 0);
137 control = (offset & EEPROM_CTRL_ADDR_MASK) << EEPROM_CTRL_ADDR_SHIFT;
138 AT_WRITE_REG(hw, REG_EEPROM_CTRL, control);
139
140 for (i = 0; i < 10; i++) {
141 udelay(100);
142 AT_READ_REG(hw, REG_EEPROM_CTRL, &control);
143 if (control & EEPROM_CTRL_RW)
144 break;
145 }
146 if (control & EEPROM_CTRL_RW) {
147 AT_READ_REG(hw, REG_EEPROM_CTRL, &data);
148 AT_READ_REG(hw, REG_EEPROM_DATA_LO, p_value);
149 data = data & 0xFFFF;
150 *p_value = swab32((data << 16) | (*p_value >> 16));
151 ret = true;
152 }
153 if (!(otp_ctrl_data & OTP_CTRL_CLK_EN))
154 AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
155
156 return ret;
157}
158/*
159 * Reads the adapter's MAC address from the EEPROM
160 *
161 * hw - Struct containing variables accessed by shared code
162 */
163int atl1c_read_mac_addr(struct atl1c_hw *hw)
164{
165 int err = 0;
166
167 err = atl1c_get_permanent_address(hw);
168 if (err)
169 random_ether_addr(hw->perm_mac_addr);
170
171 memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr));
172 return 0;
173}
174
175/*
176 * atl1c_hash_mc_addr
177 * purpose
178 * set hash value for a multicast address
179 * hash calcu processing :
180 * 1. calcu 32bit CRC for multicast address
181 * 2. reverse crc with MSB to LSB
182 */
183u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr)
184{
185 u32 crc32;
186 u32 value = 0;
187 int i;
188
189 crc32 = ether_crc_le(6, mc_addr);
190 for (i = 0; i < 32; i++)
191 value |= (((crc32 >> i) & 1) << (31 - i));
192
193 return value;
194}
195
196/*
197 * Sets the bit in the multicast table corresponding to the hash value.
198 * hw - Struct containing variables accessed by shared code
199 * hash_value - Multicast address hash value
200 */
201void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value)
202{
203 u32 hash_bit, hash_reg;
204 u32 mta;
205
206 /*
207 * The HASH Table is a register array of 2 32-bit registers.
208 * It is treated like an array of 64 bits. We want to set
209 * bit BitArray[hash_value]. So we figure out what register
210 * the bit is in, read it, OR in the new bit, then write
211 * back the new value. The register is determined by the
212 * upper bit of the hash value and the bit within that
213 * register are determined by the lower 5 bits of the value.
214 */
215 hash_reg = (hash_value >> 31) & 0x1;
216 hash_bit = (hash_value >> 26) & 0x1F;
217
218 mta = AT_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
219
220 mta |= (1 << hash_bit);
221
222 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
223}
224
225/*
226 * Reads the value from a PHY register
227 * hw - Struct containing variables accessed by shared code
228 * reg_addr - address of the PHY register to read
229 */
230int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data)
231{
232 u32 val;
233 int i;
234
235 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
236 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW |
237 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
238
239 AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
240
241 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
242 udelay(2);
243 AT_READ_REG(hw, REG_MDIO_CTRL, &val);
244 if (!(val & (MDIO_START | MDIO_BUSY)))
245 break;
246 }
247 if (!(val & (MDIO_START | MDIO_BUSY))) {
248 *phy_data = (u16)val;
249 return 0;
250 }
251
252 return -1;
253}
254
255/*
256 * Writes a value to a PHY register
257 * hw - Struct containing variables accessed by shared code
258 * reg_addr - address of the PHY register to write
259 * data - data to write to the PHY
260 */
261int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data)
262{
263 int i;
264 u32 val;
265
266 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
267 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
268 MDIO_SUP_PREAMBLE | MDIO_START |
269 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
270
271 AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
272
273 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
274 udelay(2);
275 AT_READ_REG(hw, REG_MDIO_CTRL, &val);
276 if (!(val & (MDIO_START | MDIO_BUSY)))
277 break;
278 }
279
280 if (!(val & (MDIO_START | MDIO_BUSY)))
281 return 0;
282
283 return -1;
284}
285
286/*
287 * Configures PHY autoneg and flow control advertisement settings
288 *
289 * hw - Struct containing variables accessed by shared code
290 */
291static int atl1c_phy_setup_adv(struct atl1c_hw *hw)
292{
293 u16 mii_adv_data = ADVERTISE_DEFAULT_CAP & ~ADVERTISE_SPEED_MASK;
294 u16 mii_giga_ctrl_data = GIGA_CR_1000T_DEFAULT_CAP &
295 ~GIGA_CR_1000T_SPEED_MASK;
296
297 if (hw->autoneg_advertised & ADVERTISED_10baseT_Half)
298 mii_adv_data |= ADVERTISE_10HALF;
299 if (hw->autoneg_advertised & ADVERTISED_10baseT_Full)
300 mii_adv_data |= ADVERTISE_10FULL;
301 if (hw->autoneg_advertised & ADVERTISED_100baseT_Half)
302 mii_adv_data |= ADVERTISE_100HALF;
303 if (hw->autoneg_advertised & ADVERTISED_100baseT_Full)
304 mii_adv_data |= ADVERTISE_100FULL;
305
306 if (hw->autoneg_advertised & ADVERTISED_Autoneg)
307 mii_adv_data |= ADVERTISE_10HALF | ADVERTISE_10FULL |
308 ADVERTISE_100HALF | ADVERTISE_100FULL;
309
310 if (hw->ctrl_flags & ATL1C_LINK_CAP_1000M) {
311 if (hw->autoneg_advertised & ADVERTISED_1000baseT_Half)
312 mii_giga_ctrl_data |= ADVERTISE_1000HALF;
313 if (hw->autoneg_advertised & ADVERTISED_1000baseT_Full)
314 mii_giga_ctrl_data |= ADVERTISE_1000FULL;
315 if (hw->autoneg_advertised & ADVERTISED_Autoneg)
316 mii_giga_ctrl_data |= ADVERTISE_1000HALF |
317 ADVERTISE_1000FULL;
318 }
319
320 if (atl1c_write_phy_reg(hw, MII_ADVERTISE, mii_adv_data) != 0 ||
321 atl1c_write_phy_reg(hw, MII_GIGA_CR, mii_giga_ctrl_data) != 0)
322 return -1;
323 return 0;
324}
325
326void atl1c_phy_disable(struct atl1c_hw *hw)
327{
328 AT_WRITE_REGW(hw, REG_GPHY_CTRL,
329 GPHY_CTRL_PW_WOL_DIS | GPHY_CTRL_EXT_RESET);
330}
331
332static void atl1c_phy_magic_data(struct atl1c_hw *hw)
333{
334 u16 data;
335
336 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
337 ((1 & ANA_INTERVAL_SEL_TIMER_MASK) <<
338 ANA_INTERVAL_SEL_TIMER_SHIFT);
339
340 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_18);
341 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
342
343 data = (2 & ANA_SERDES_CDR_BW_MASK) | ANA_MS_PAD_DBG |
344 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL |
345 ANA_SERDES_EN_LCKDT;
346
347 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_5);
348 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
349
350 data = (44 & ANA_LONG_CABLE_TH_100_MASK) |
351 ((33 & ANA_SHORT_CABLE_TH_100_MASK) <<
352 ANA_SHORT_CABLE_TH_100_SHIFT) | ANA_BP_BAD_LINK_ACCUM |
353 ANA_BP_SMALL_BW;
354
355 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_54);
356 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
357
358 data = (11 & ANA_IECHO_ADJ_MASK) | ((11 & ANA_IECHO_ADJ_MASK) <<
359 ANA_IECHO_ADJ_2_SHIFT) | ((8 & ANA_IECHO_ADJ_MASK) <<
360 ANA_IECHO_ADJ_1_SHIFT) | ((8 & ANA_IECHO_ADJ_MASK) <<
361 ANA_IECHO_ADJ_0_SHIFT);
362
363 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_4);
364 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
365
366 data = ANA_RESTART_CAL | ((7 & ANA_MANUL_SWICH_ON_MASK) <<
367 ANA_MANUL_SWICH_ON_SHIFT) | ANA_MAN_ENABLE |
368 ANA_SEL_HSP | ANA_EN_HB | ANA_OEN_125M;
369
370 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_0);
371 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
372
373 if (hw->ctrl_flags & ATL1C_HIB_DISABLE) {
374 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_41);
375 if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &data) != 0)
376 return;
377 data &= ~ANA_TOP_PS_EN;
378 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
379
380 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_11);
381 if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &data) != 0)
382 return;
383 data &= ~ANA_PS_HIB_EN;
384 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
385 }
386}
387
388int atl1c_phy_reset(struct atl1c_hw *hw)
389{
390 struct atl1c_adapter *adapter = hw->adapter;
391 struct pci_dev *pdev = adapter->pdev;
392 u32 phy_ctrl_data = GPHY_CTRL_DEFAULT;
393 u32 mii_ier_data = IER_LINK_UP | IER_LINK_DOWN;
394 int err;
395
396 if (hw->ctrl_flags & ATL1C_HIB_DISABLE)
397 phy_ctrl_data &= ~GPHY_CTRL_HIB_EN;
398
399 AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
400 AT_WRITE_FLUSH(hw);
401 msleep(40);
402 phy_ctrl_data |= GPHY_CTRL_EXT_RESET;
403 AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
404 AT_WRITE_FLUSH(hw);
405 msleep(10);
406
407 /*Enable PHY LinkChange Interrupt */
408 err = atl1c_write_phy_reg(hw, MII_IER, mii_ier_data);
409 if (err) {
410 if (netif_msg_hw(adapter))
411 dev_err(&pdev->dev,
412 "Error enable PHY linkChange Interrupt\n");
413 return err;
414 }
415 if (!(hw->ctrl_flags & ATL1C_FPGA_VERSION))
416 atl1c_phy_magic_data(hw);
417 return 0;
418}
419
420int atl1c_phy_init(struct atl1c_hw *hw)
421{
422 struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
423 struct pci_dev *pdev = adapter->pdev;
424 int ret_val;
425 u16 mii_bmcr_data = BMCR_RESET;
426 u16 phy_id1, phy_id2;
427
428 if ((atl1c_read_phy_reg(hw, MII_PHYSID1, &phy_id1) != 0) ||
429 (atl1c_read_phy_reg(hw, MII_PHYSID2, &phy_id2) != 0)) {
430 if (netif_msg_link(adapter))
431 dev_err(&pdev->dev, "Error get phy ID\n");
432 return -1;
433 }
434 switch (hw->media_type) {
435 case MEDIA_TYPE_AUTO_SENSOR:
436 ret_val = atl1c_phy_setup_adv(hw);
437 if (ret_val) {
438 if (netif_msg_link(adapter))
439 dev_err(&pdev->dev,
440 "Error Setting up Auto-Negotiation\n");
441 return ret_val;
442 }
443 mii_bmcr_data |= BMCR_AUTO_NEG_EN | BMCR_RESTART_AUTO_NEG;
444 break;
445 case MEDIA_TYPE_100M_FULL:
446 mii_bmcr_data |= BMCR_SPEED_100 | BMCR_FULL_DUPLEX;
447 break;
448 case MEDIA_TYPE_100M_HALF:
449 mii_bmcr_data |= BMCR_SPEED_100;
450 break;
451 case MEDIA_TYPE_10M_FULL:
452 mii_bmcr_data |= BMCR_SPEED_10 | BMCR_FULL_DUPLEX;
453 break;
454 case MEDIA_TYPE_10M_HALF:
455 mii_bmcr_data |= BMCR_SPEED_10;
456 break;
457 default:
458 if (netif_msg_link(adapter))
459 dev_err(&pdev->dev, "Wrong Media type %d\n",
460 hw->media_type);
461 return -1;
462 break;
463 }
464
465 ret_val = atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data);
466 if (ret_val)
467 return ret_val;
468 hw->phy_configured = true;
469
470 return 0;
471}
472
473/*
474 * Detects the current speed and duplex settings of the hardware.
475 *
476 * hw - Struct containing variables accessed by shared code
477 * speed - Speed of the connection
478 * duplex - Duplex setting of the connection
479 */
480int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex)
481{
482 int err;
483 u16 phy_data;
484
485 /* Read PHY Specific Status Register (17) */
486 err = atl1c_read_phy_reg(hw, MII_GIGA_PSSR, &phy_data);
487 if (err)
488 return err;
489
490 if (!(phy_data & GIGA_PSSR_SPD_DPLX_RESOLVED))
491 return -1;
492
493 switch (phy_data & GIGA_PSSR_SPEED) {
494 case GIGA_PSSR_1000MBS:
495 *speed = SPEED_1000;
496 break;
497 case GIGA_PSSR_100MBS:
498 *speed = SPEED_100;
499 break;
500 case GIGA_PSSR_10MBS:
501 *speed = SPEED_10;
502 break;
503 default:
504 return -1;
505 break;
506 }
507
508 if (phy_data & GIGA_PSSR_DPLX)
509 *duplex = FULL_DUPLEX;
510 else
511 *duplex = HALF_DUPLEX;
512
513 return 0;
514}
515
516int atl1c_restart_autoneg(struct atl1c_hw *hw)
517{
518 int err = 0;
519 u16 mii_bmcr_data = BMCR_RESET;
520
521 err = atl1c_phy_setup_adv(hw);
522 if (err)
523 return err;
524 mii_bmcr_data |= BMCR_AUTO_NEG_EN | BMCR_RESTART_AUTO_NEG;
525
526 return atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data);
527}
diff --git a/drivers/net/atl1c/atl1c_hw.h b/drivers/net/atl1c/atl1c_hw.h
new file mode 100644
index 000000000000..c2c738df5c63
--- /dev/null
+++ b/drivers/net/atl1c/atl1c_hw.h
@@ -0,0 +1,859 @@
1/*
2 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef _ATL1C_HW_H_
23#define _ATL1C_HW_H_
24
25#include <linux/types.h>
26#include <linux/mii.h>
27
28struct atl1c_adapter;
29struct atl1c_hw;
30
31/* function prototype */
32void atl1c_phy_disable(struct atl1c_hw *hw);
33void atl1c_hw_set_mac_addr(struct atl1c_hw *hw);
34int atl1c_phy_reset(struct atl1c_hw *hw);
35int atl1c_read_mac_addr(struct atl1c_hw *hw);
36int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex);
37u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr);
38void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value);
39int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data);
40int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data);
41bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value);
42int atl1c_phy_init(struct atl1c_hw *hw);
43int atl1c_check_eeprom_exist(struct atl1c_hw *hw);
44int atl1c_restart_autoneg(struct atl1c_hw *hw);
45
46/* register definition */
47#define REG_DEVICE_CAP 0x5C
48#define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
49#define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0
50
51#define REG_DEVICE_CTRL 0x60
52#define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7
53#define DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5
54#define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7
55#define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12
56
57#define REG_LINK_CTRL 0x68
58#define LINK_CTRL_L0S_EN 0x01
59#define LINK_CTRL_L1_EN 0x02
60
61#define REG_VPD_CAP 0x6C
62#define VPD_CAP_ID_MASK 0xff
63#define VPD_CAP_ID_SHIFT 0
64#define VPD_CAP_NEXT_PTR_MASK 0xFF
65#define VPD_CAP_NEXT_PTR_SHIFT 8
66#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
67#define VPD_CAP_VPD_ADDR_SHIFT 16
68#define VPD_CAP_VPD_FLAG 0x80000000
69
70#define REG_VPD_DATA 0x70
71
72#define REG_PCIE_UC_SEVERITY 0x10C
73#define PCIE_UC_SERVRITY_TRN 0x00000001
74#define PCIE_UC_SERVRITY_DLP 0x00000010
75#define PCIE_UC_SERVRITY_PSN_TLP 0x00001000
76#define PCIE_UC_SERVRITY_FCP 0x00002000
77#define PCIE_UC_SERVRITY_CPL_TO 0x00004000
78#define PCIE_UC_SERVRITY_CA 0x00008000
79#define PCIE_UC_SERVRITY_UC 0x00010000
80#define PCIE_UC_SERVRITY_ROV 0x00020000
81#define PCIE_UC_SERVRITY_MLFP 0x00040000
82#define PCIE_UC_SERVRITY_ECRC 0x00080000
83#define PCIE_UC_SERVRITY_UR 0x00100000
84
85#define REG_DEV_SERIALNUM_CTRL 0x200
86#define REG_DEV_MAC_SEL_MASK 0x0 /* 0:EUI; 1:MAC */
87#define REG_DEV_MAC_SEL_SHIFT 0
88#define REG_DEV_SERIAL_NUM_EN_MASK 0x1
89#define REG_DEV_SERIAL_NUM_EN_SHIFT 1
90
91#define REG_TWSI_CTRL 0x218
92#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
93#define TWSI_CTRL_LD_OFFSET_SHIFT 0
94#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
95#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
96#define TWSI_CTRL_SW_LDSTART 0x800
97#define TWSI_CTRL_HW_LDSTART 0x1000
98#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
99#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
100#define TWSI_CTRL_LD_EXIST 0x400000
101#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
102#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
103#define TWSI_CTRL_FREQ_SEL_100K 0
104#define TWSI_CTRL_FREQ_SEL_200K 1
105#define TWSI_CTRL_FREQ_SEL_300K 2
106#define TWSI_CTRL_FREQ_SEL_400K 3
107#define TWSI_CTRL_SMB_SLV_ADDR
108#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
109#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
110
111
112#define REG_PCIE_DEV_MISC_CTRL 0x21C
113#define PCIE_DEV_MISC_EXT_PIPE 0x2
114#define PCIE_DEV_MISC_RETRY_BUFDIS 0x1
115#define PCIE_DEV_MISC_SPIROM_EXIST 0x4
116#define PCIE_DEV_MISC_SERDES_ENDIAN 0x8
117#define PCIE_DEV_MISC_SERDES_SEL_DIN 0x10
118
119#define REG_PCIE_PHYMISC 0x1000
120#define PCIE_PHYMISC_FORCE_RCV_DET 0x4
121
122#define REG_TWSI_DEBUG 0x1108
123#define TWSI_DEBUG_DEV_EXIST 0x20000000
124
125#define REG_EEPROM_CTRL 0x12C0
126#define EEPROM_CTRL_DATA_HI_MASK 0xFFFF
127#define EEPROM_CTRL_DATA_HI_SHIFT 0
128#define EEPROM_CTRL_ADDR_MASK 0x3FF
129#define EEPROM_CTRL_ADDR_SHIFT 16
130#define EEPROM_CTRL_ACK 0x40000000
131#define EEPROM_CTRL_RW 0x80000000
132
133#define REG_EEPROM_DATA_LO 0x12C4
134
135#define REG_OTP_CTRL 0x12F0
136#define OTP_CTRL_CLK_EN 0x0002
137
138#define REG_PM_CTRL 0x12F8
139#define PM_CTRL_SDES_EN 0x00000001
140#define PM_CTRL_RBER_EN 0x00000002
141#define PM_CTRL_CLK_REQ_EN 0x00000004
142#define PM_CTRL_ASPM_L1_EN 0x00000008
143#define PM_CTRL_SERDES_L1_EN 0x00000010
144#define PM_CTRL_SERDES_PLL_L1_EN 0x00000020
145#define PM_CTRL_SERDES_PD_EX_L1 0x00000040
146#define PM_CTRL_SERDES_BUDS_RX_L1_EN 0x00000080
147#define PM_CTRL_L0S_ENTRY_TIMER_MASK 0xF
148#define PM_CTRL_L0S_ENTRY_TIMER_SHIFT 8
149#define PM_CTRL_ASPM_L0S_EN 0x00001000
150#define PM_CTRL_CLK_SWH_L1 0x00002000
151#define PM_CTRL_CLK_PWM_VER1_1 0x00004000
152#define PM_CTRL_PCIE_RECV 0x00008000
153#define PM_CTRL_L1_ENTRY_TIMER_MASK 0xF
154#define PM_CTRL_L1_ENTRY_TIMER_SHIFT 16
155#define PM_CTRL_PM_REQ_TIMER_MASK 0xF
156#define PM_CTRL_PM_REQ_TIMER_SHIFT 20
157#define PM_CTRL_LCKDET_TIMER_MASK 0x3F
158#define PM_CTRL_LCKDET_TIMER_SHIFT 24
159#define PM_CTRL_MAC_ASPM_CHK 0x40000000
160#define PM_CTRL_HOTRST 0x80000000
161
162/* Selene Master Control Register */
163#define REG_MASTER_CTRL 0x1400
164#define MASTER_CTRL_SOFT_RST 0x1
165#define MASTER_CTRL_TEST_MODE_MASK 0x3
166#define MASTER_CTRL_TEST_MODE_SHIFT 2
167#define MASTER_CTRL_BERT_START 0x10
168#define MASTER_CTRL_MTIMER_EN 0x100
169#define MASTER_CTRL_MANUAL_INT 0x200
170#define MASTER_CTRL_TX_ITIMER_EN 0x400
171#define MASTER_CTRL_RX_ITIMER_EN 0x800
172#define MASTER_CTRL_CLK_SEL_DIS 0x1000
173#define MASTER_CTRL_CLK_SWH_MODE 0x2000
174#define MASTER_CTRL_INT_RDCLR 0x4000
175#define MASTER_CTRL_REV_NUM_SHIFT 16
176#define MASTER_CTRL_REV_NUM_MASK 0xff
177#define MASTER_CTRL_DEV_ID_SHIFT 24
178#define MASTER_CTRL_DEV_ID_MASK 0x7f
179#define MASTER_CTRL_OTP_SEL 0x80000000
180
181/* Timer Initial Value Register */
182#define REG_MANUAL_TIMER_INIT 0x1404
183
184/* IRQ ModeratorTimer Initial Value Register */
185#define REG_IRQ_MODRT_TIMER_INIT 0x1408
186#define IRQ_MODRT_TIMER_MASK 0xffff
187#define IRQ_MODRT_TX_TIMER_SHIFT 0
188#define IRQ_MODRT_RX_TIMER_SHIFT 16
189
190#define REG_GPHY_CTRL 0x140C
191#define GPHY_CTRL_EXT_RESET 0x1
192#define GPHY_CTRL_RTL_MODE 0x2
193#define GPHY_CTRL_LED_MODE 0x4
194#define GPHY_CTRL_ANEG_NOW 0x8
195#define GPHY_CTRL_REV_ANEG 0x10
196#define GPHY_CTRL_GATE_25M_EN 0x20
197#define GPHY_CTRL_LPW_EXIT 0x40
198#define GPHY_CTRL_PHY_IDDQ 0x80
199#define GPHY_CTRL_PHY_IDDQ_DIS 0x100
200#define GPHY_CTRL_GIGA_DIS 0x200
201#define GPHY_CTRL_HIB_EN 0x400
202#define GPHY_CTRL_HIB_PULSE 0x800
203#define GPHY_CTRL_SEL_ANA_RST 0x1000
204#define GPHY_CTRL_PHY_PLL_ON 0x2000
205#define GPHY_CTRL_PWDOWN_HW 0x4000
206#define GPHY_CTRL_PHY_PLL_BYPASS 0x8000
207
208#define GPHY_CTRL_DEFAULT ( \
209 GPHY_CTRL_SEL_ANA_RST |\
210 GPHY_CTRL_HIB_PULSE |\
211 GPHY_CTRL_HIB_EN)
212
213#define GPHY_CTRL_PW_WOL_DIS ( \
214 GPHY_CTRL_SEL_ANA_RST |\
215 GPHY_CTRL_HIB_PULSE |\
216 GPHY_CTRL_HIB_EN |\
217 GPHY_CTRL_PWDOWN_HW |\
218 GPHY_CTRL_PHY_IDDQ)
219
220/* Block IDLE Status Register */
221#define REG_IDLE_STATUS 0x1410
222#define IDLE_STATUS_MASK 0x00FF
223#define IDLE_STATUS_RXMAC_NO_IDLE 0x1
224#define IDLE_STATUS_TXMAC_NO_IDLE 0x2
225#define IDLE_STATUS_RXQ_NO_IDLE 0x4
226#define IDLE_STATUS_TXQ_NO_IDLE 0x8
227#define IDLE_STATUS_DMAR_NO_IDLE 0x10
228#define IDLE_STATUS_DMAW_NO_IDLE 0x20
229#define IDLE_STATUS_SMB_NO_IDLE 0x40
230#define IDLE_STATUS_CMB_NO_IDLE 0x80
231
232/* MDIO Control Register */
233#define REG_MDIO_CTRL 0x1414
234#define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit
235 * control data to write to PHY
236 * MII management register */
237#define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit
238 * status data that was read
239 * from the PHY MII management register */
240#define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */
241#define MDIO_REG_ADDR_SHIFT 16
242#define MDIO_RW 0x200000 /* 1: read, 0: write */
243#define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */
244#define MDIO_START 0x800000 /* Write 1 to initiate the MDIO
245 * master. And this bit is self
246 * cleared after one cycle */
247#define MDIO_CLK_SEL_SHIFT 24
248#define MDIO_CLK_25_4 0
249#define MDIO_CLK_25_6 2
250#define MDIO_CLK_25_8 3
251#define MDIO_CLK_25_10 4
252#define MDIO_CLK_25_14 5
253#define MDIO_CLK_25_20 6
254#define MDIO_CLK_25_28 7
255#define MDIO_BUSY 0x8000000
256#define MDIO_AP_EN 0x10000000
257#define MDIO_WAIT_TIMES 10
258
259/* MII PHY Status Register */
260#define REG_PHY_STATUS 0x1418
261#define PHY_GENERAL_STATUS_MASK 0xFFFF
262#define PHY_STATUS_RECV_ENABLE 0x0001
263#define PHY_OE_PWSP_STATUS_MASK 0x07FF
264#define PHY_OE_PWSP_STATUS_SHIFT 16
265#define PHY_STATUS_LPW_STATE 0x80000000
266/* BIST Control and Status Register0 (for the Packet Memory) */
267#define REG_BIST0_CTRL 0x141c
268#define BIST0_NOW 0x1
269#define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is
270 * un-repairable because
271 * it has address decoder
272 * failure or more than 1 cell
273 * stuck-to-x failure */
274#define BIST0_FUSE_FLAG 0x4
275
276/* BIST Control and Status Register1(for the retry buffer of PCI Express) */
277#define REG_BIST1_CTRL 0x1420
278#define BIST1_NOW 0x1
279#define BIST1_SRAM_FAIL 0x2
280#define BIST1_FUSE_FLAG 0x4
281
282/* SerDes Lock Detect Control and Status Register */
283#define REG_SERDES_LOCK 0x1424
284#define SERDES_LOCK_DETECT 0x1 /* SerDes lock detected. This signal
285 * comes from Analog SerDes */
286#define SERDES_LOCK_DETECT_EN 0x2 /* 1: Enable SerDes Lock detect function */
287
288/* MAC Control Register */
289#define REG_MAC_CTRL 0x1480
290#define MAC_CTRL_TX_EN 0x1
291#define MAC_CTRL_RX_EN 0x2
292#define MAC_CTRL_TX_FLOW 0x4
293#define MAC_CTRL_RX_FLOW 0x8
294#define MAC_CTRL_LOOPBACK 0x10
295#define MAC_CTRL_DUPLX 0x20
296#define MAC_CTRL_ADD_CRC 0x40
297#define MAC_CTRL_PAD 0x80
298#define MAC_CTRL_LENCHK 0x100
299#define MAC_CTRL_HUGE_EN 0x200
300#define MAC_CTRL_PRMLEN_SHIFT 10
301#define MAC_CTRL_PRMLEN_MASK 0xf
302#define MAC_CTRL_RMV_VLAN 0x4000
303#define MAC_CTRL_PROMIS_EN 0x8000
304#define MAC_CTRL_TX_PAUSE 0x10000
305#define MAC_CTRL_SCNT 0x20000
306#define MAC_CTRL_SRST_TX 0x40000
307#define MAC_CTRL_TX_SIMURST 0x80000
308#define MAC_CTRL_SPEED_SHIFT 20
309#define MAC_CTRL_SPEED_MASK 0x3
310#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
311#define MAC_CTRL_TX_HUGE 0x800000
312#define MAC_CTRL_RX_CHKSUM_EN 0x1000000
313#define MAC_CTRL_MC_ALL_EN 0x2000000
314#define MAC_CTRL_BC_EN 0x4000000
315#define MAC_CTRL_DBG 0x8000000
316#define MAC_CTRL_SINGLE_PAUSE_EN 0x10000000
317
318/* MAC IPG/IFG Control Register */
319#define REG_MAC_IPG_IFG 0x1484
320#define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back
321 * inter-packet gap. The
322 * default is 96-bit time */
323#define MAC_IPG_IFG_IPGT_MASK 0x7f
324#define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to
325 * enforce in between RX frames */
326#define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */
327#define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */
328#define MAC_IPG_IFG_IPGR1_MASK 0x7f
329#define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */
330#define MAC_IPG_IFG_IPGR2_MASK 0x7f
331
332/* MAC STATION ADDRESS */
333#define REG_MAC_STA_ADDR 0x1488
334
335/* Hash table for multicast address */
336#define REG_RX_HASH_TABLE 0x1490
337
338/* MAC Half-Duplex Control Register */
339#define REG_MAC_HALF_DUPLX_CTRL 0x1498
340#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */
341#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
342#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
343#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
344#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
345#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
346#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* No back-off on backpressure,
347 * immediately start the
348 * transmission after back pressure */
349#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */
350#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */
351#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
352#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */
353#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */
354
355/* Maximum Frame Length Control Register */
356#define REG_MTU 0x149c
357
358/* Wake-On-Lan control register */
359#define REG_WOL_CTRL 0x14a0
360#define WOL_PATTERN_EN 0x00000001
361#define WOL_PATTERN_PME_EN 0x00000002
362#define WOL_MAGIC_EN 0x00000004
363#define WOL_MAGIC_PME_EN 0x00000008
364#define WOL_LINK_CHG_EN 0x00000010
365#define WOL_LINK_CHG_PME_EN 0x00000020
366#define WOL_PATTERN_ST 0x00000100
367#define WOL_MAGIC_ST 0x00000200
368#define WOL_LINKCHG_ST 0x00000400
369#define WOL_CLK_SWITCH_EN 0x00008000
370#define WOL_PT0_EN 0x00010000
371#define WOL_PT1_EN 0x00020000
372#define WOL_PT2_EN 0x00040000
373#define WOL_PT3_EN 0x00080000
374#define WOL_PT4_EN 0x00100000
375#define WOL_PT5_EN 0x00200000
376#define WOL_PT6_EN 0x00400000
377
378/* WOL Length ( 2 DWORD ) */
379#define REG_WOL_PATTERN_LEN 0x14a4
380#define WOL_PT_LEN_MASK 0x7f
381#define WOL_PT0_LEN_SHIFT 0
382#define WOL_PT1_LEN_SHIFT 8
383#define WOL_PT2_LEN_SHIFT 16
384#define WOL_PT3_LEN_SHIFT 24
385#define WOL_PT4_LEN_SHIFT 0
386#define WOL_PT5_LEN_SHIFT 8
387#define WOL_PT6_LEN_SHIFT 16
388
389/* Internal SRAM Partition Register */
390#define RFDX_HEAD_ADDR_MASK 0x03FF
391#define RFDX_HARD_ADDR_SHIFT 0
392#define RFDX_TAIL_ADDR_MASK 0x03FF
393#define RFDX_TAIL_ADDR_SHIFT 16
394
395#define REG_SRAM_RFD0_INFO 0x1500
396#define REG_SRAM_RFD1_INFO 0x1504
397#define REG_SRAM_RFD2_INFO 0x1508
398#define REG_SRAM_RFD3_INFO 0x150C
399
400#define REG_RFD_NIC_LEN 0x1510 /* In 8-bytes */
401#define RFD_NIC_LEN_MASK 0x03FF
402
403#define REG_SRAM_TRD_ADDR 0x1518
404#define TPD_HEAD_ADDR_MASK 0x03FF
405#define TPD_HEAD_ADDR_SHIFT 0
406#define TPD_TAIL_ADDR_MASK 0x03FF
407#define TPD_TAIL_ADDR_SHIFT 16
408
409#define REG_SRAM_TRD_LEN 0x151C /* In 8-bytes */
410#define TPD_NIC_LEN_MASK 0x03FF
411
412#define REG_SRAM_RXF_ADDR 0x1520
413#define REG_SRAM_RXF_LEN 0x1524
414#define REG_SRAM_TXF_ADDR 0x1528
415#define REG_SRAM_TXF_LEN 0x152C
416#define REG_SRAM_TCPH_ADDR 0x1530
417#define REG_SRAM_PKTH_ADDR 0x1532
418
419/*
420 * Load Ptr Register
421 * Software sets this bit after the initialization of the head and tail */
422#define REG_LOAD_PTR 0x1534
423
424/*
425 * addresses of all descriptors, as well as the following descriptor
426 * control register, which triggers each function block to load the head
427 * pointer to prepare for the operation. This bit is then self-cleared
428 * after one cycle.
429 */
430#define REG_RX_BASE_ADDR_HI 0x1540
431#define REG_TX_BASE_ADDR_HI 0x1544
432#define REG_SMB_BASE_ADDR_HI 0x1548
433#define REG_SMB_BASE_ADDR_LO 0x154C
434#define REG_RFD0_HEAD_ADDR_LO 0x1550
435#define REG_RFD1_HEAD_ADDR_LO 0x1554
436#define REG_RFD2_HEAD_ADDR_LO 0x1558
437#define REG_RFD3_HEAD_ADDR_LO 0x155C
438#define REG_RFD_RING_SIZE 0x1560
439#define RFD_RING_SIZE_MASK 0x0FFF
440#define REG_RX_BUF_SIZE 0x1564
441#define RX_BUF_SIZE_MASK 0xFFFF
442#define REG_RRD0_HEAD_ADDR_LO 0x1568
443#define REG_RRD1_HEAD_ADDR_LO 0x156C
444#define REG_RRD2_HEAD_ADDR_LO 0x1570
445#define REG_RRD3_HEAD_ADDR_LO 0x1574
446#define REG_RRD_RING_SIZE 0x1578
447#define RRD_RING_SIZE_MASK 0x0FFF
448#define REG_HTPD_HEAD_ADDR_LO 0x157C
449#define REG_NTPD_HEAD_ADDR_LO 0x1580
450#define REG_TPD_RING_SIZE 0x1584
451#define TPD_RING_SIZE_MASK 0xFFFF
452#define REG_CMB_BASE_ADDR_LO 0x1588
453
454/* RSS about */
455#define REG_RSS_KEY0 0x14B0
456#define REG_RSS_KEY1 0x14B4
457#define REG_RSS_KEY2 0x14B8
458#define REG_RSS_KEY3 0x14BC
459#define REG_RSS_KEY4 0x14C0
460#define REG_RSS_KEY5 0x14C4
461#define REG_RSS_KEY6 0x14C8
462#define REG_RSS_KEY7 0x14CC
463#define REG_RSS_KEY8 0x14D0
464#define REG_RSS_KEY9 0x14D4
465#define REG_IDT_TABLE0 0x14E0
466#define REG_IDT_TABLE1 0x14E4
467#define REG_IDT_TABLE2 0x14E8
468#define REG_IDT_TABLE3 0x14EC
469#define REG_IDT_TABLE4 0x14F0
470#define REG_IDT_TABLE5 0x14F4
471#define REG_IDT_TABLE6 0x14F8
472#define REG_IDT_TABLE7 0x14FC
473#define REG_IDT_TABLE REG_IDT_TABLE0
474#define REG_RSS_HASH_VALUE 0x15B0
475#define REG_RSS_HASH_FLAG 0x15B4
476#define REG_BASE_CPU_NUMBER 0x15B8
477
478/* TXQ Control Register */
479#define REG_TXQ_CTRL 0x1590
480#define TXQ_NUM_TPD_BURST_MASK 0xF
481#define TXQ_NUM_TPD_BURST_SHIFT 0
482#define TXQ_CTRL_IP_OPTION_EN 0x10
483#define TXQ_CTRL_EN 0x20
484#define TXQ_CTRL_ENH_MODE 0x40
485#define TXQ_CTRL_LS_8023_EN 0x80
486#define TXQ_TXF_BURST_NUM_SHIFT 16
487#define TXQ_TXF_BURST_NUM_MASK 0xFFFF
488
489/* Jumbo packet Threshold for task offload */
490#define REG_TX_TSO_OFFLOAD_THRESH 0x1594 /* In 8-bytes */
491#define TX_TSO_OFFLOAD_THRESH_MASK 0x07FF
492
493#define REG_TXF_WATER_MARK 0x1598 /* In 8-bytes */
494#define TXF_WATER_MARK_MASK 0x0FFF
495#define TXF_LOW_WATER_MARK_SHIFT 0
496#define TXF_HIGH_WATER_MARK_SHIFT 16
497#define TXQ_CTRL_BURST_MODE_EN 0x80000000
498
499#define REG_THRUPUT_MON_CTRL 0x159C
500#define THRUPUT_MON_RATE_MASK 0x3
501#define THRUPUT_MON_RATE_SHIFT 0
502#define THRUPUT_MON_EN 0x80
503
504/* RXQ Control Register */
505#define REG_RXQ_CTRL 0x15A0
506#define ASPM_THRUPUT_LIMIT_MASK 0x3
507#define ASPM_THRUPUT_LIMIT_SHIFT 0
508#define ASPM_THRUPUT_LIMIT_NO 0x00
509#define ASPM_THRUPUT_LIMIT_1M 0x01
510#define ASPM_THRUPUT_LIMIT_10M 0x02
511#define ASPM_THRUPUT_LIMIT_100M 0x04
512#define RXQ1_CTRL_EN 0x10
513#define RXQ2_CTRL_EN 0x20
514#define RXQ3_CTRL_EN 0x40
515#define IPV6_CHKSUM_CTRL_EN 0x80
516#define RSS_HASH_BITS_MASK 0x00FF
517#define RSS_HASH_BITS_SHIFT 8
518#define RSS_HASH_IPV4 0x10000
519#define RSS_HASH_IPV4_TCP 0x20000
520#define RSS_HASH_IPV6 0x40000
521#define RSS_HASH_IPV6_TCP 0x80000
522#define RXQ_RFD_BURST_NUM_MASK 0x003F
523#define RXQ_RFD_BURST_NUM_SHIFT 20
524#define RSS_MODE_MASK 0x0003
525#define RSS_MODE_SHIFT 26
526#define RSS_NIP_QUEUE_SEL_MASK 0x1
527#define RSS_NIP_QUEUE_SEL_SHIFT 28
528#define RRS_HASH_CTRL_EN 0x20000000
529#define RX_CUT_THRU_EN 0x40000000
530#define RXQ_CTRL_EN 0x80000000
531
532#define REG_RFD_FREE_THRESH 0x15A4
533#define RFD_FREE_THRESH_MASK 0x003F
534#define RFD_FREE_HI_THRESH_SHIFT 0
535#define RFD_FREE_LO_THRESH_SHIFT 6
536
537/* RXF flow control register */
538#define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
539#define RXQ_RXF_PAUSE_TH_HI_SHIFT 0
540#define RXQ_RXF_PAUSE_TH_HI_MASK 0x0FFF
541#define RXQ_RXF_PAUSE_TH_LO_SHIFT 16
542#define RXQ_RXF_PAUSE_TH_LO_MASK 0x0FFF
543
544#define REG_RXD_DMA_CTRL 0x15AC
545#define RXD_DMA_THRESH_MASK 0x0FFF /* In 8-bytes */
546#define RXD_DMA_THRESH_SHIFT 0
547#define RXD_DMA_DOWN_TIMER_MASK 0xFFFF
548#define RXD_DMA_DOWN_TIMER_SHIFT 16
549
550/* DMA Engine Control Register */
551#define REG_DMA_CTRL 0x15C0
552#define DMA_CTRL_DMAR_IN_ORDER 0x1
553#define DMA_CTRL_DMAR_ENH_ORDER 0x2
554#define DMA_CTRL_DMAR_OUT_ORDER 0x4
555#define DMA_CTRL_RCB_VALUE 0x8
556#define DMA_CTRL_DMAR_BURST_LEN_MASK 0x0007
557#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
558#define DMA_CTRL_DMAW_BURST_LEN_MASK 0x0007
559#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
560#define DMA_CTRL_DMAR_REQ_PRI 0x400
561#define DMA_CTRL_DMAR_DLY_CNT_MASK 0x001F
562#define DMA_CTRL_DMAR_DLY_CNT_SHIFT 11
563#define DMA_CTRL_DMAW_DLY_CNT_MASK 0x000F
564#define DMA_CTRL_DMAW_DLY_CNT_SHIFT 16
565#define DMA_CTRL_CMB_EN 0x100000
566#define DMA_CTRL_SMB_EN 0x200000
567#define DMA_CTRL_CMB_NOW 0x400000
568#define MAC_CTRL_SMB_DIS 0x1000000
569#define DMA_CTRL_SMB_NOW 0x80000000
570
571/* CMB/SMB Control Register */
572#define REG_SMB_STAT_TIMER 0x15C4 /* 2us resolution */
573#define SMB_STAT_TIMER_MASK 0xFFFFFF
574#define REG_CMB_TPD_THRESH 0x15C8
575#define CMB_TPD_THRESH_MASK 0xFFFF
576#define REG_CMB_TX_TIMER 0x15CC /* 2us resolution */
577#define CMB_TX_TIMER_MASK 0xFFFF
578
579/* Mail box */
580#define MB_RFDX_PROD_IDX_MASK 0xFFFF
581#define REG_MB_RFD0_PROD_IDX 0x15E0
582#define REG_MB_RFD1_PROD_IDX 0x15E4
583#define REG_MB_RFD2_PROD_IDX 0x15E8
584#define REG_MB_RFD3_PROD_IDX 0x15EC
585
586#define MB_PRIO_PROD_IDX_MASK 0xFFFF
587#define REG_MB_PRIO_PROD_IDX 0x15F0
588#define MB_HTPD_PROD_IDX_SHIFT 0
589#define MB_NTPD_PROD_IDX_SHIFT 16
590
591#define MB_PRIO_CONS_IDX_MASK 0xFFFF
592#define REG_MB_PRIO_CONS_IDX 0x15F4
593#define MB_HTPD_CONS_IDX_SHIFT 0
594#define MB_NTPD_CONS_IDX_SHIFT 16
595
596#define REG_MB_RFD01_CONS_IDX 0x15F8
597#define MB_RFD0_CONS_IDX_MASK 0x0000FFFF
598#define MB_RFD1_CONS_IDX_MASK 0xFFFF0000
599#define REG_MB_RFD23_CONS_IDX 0x15FC
600#define MB_RFD2_CONS_IDX_MASK 0x0000FFFF
601#define MB_RFD3_CONS_IDX_MASK 0xFFFF0000
602
603/* Interrupt Status Register */
604#define REG_ISR 0x1600
605#define ISR_SMB 0x00000001
606#define ISR_TIMER 0x00000002
607/*
608 * Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set
609 * in Table 51 Selene Master Control Register (Offset 0x1400).
610 */
611#define ISR_MANUAL 0x00000004
612#define ISR_HW_RXF_OV 0x00000008 /* RXF overflow interrupt */
613#define ISR_RFD0_UR 0x00000010 /* RFD0 under run */
614#define ISR_RFD1_UR 0x00000020
615#define ISR_RFD2_UR 0x00000040
616#define ISR_RFD3_UR 0x00000080
617#define ISR_TXF_UR 0x00000100
618#define ISR_DMAR_TO_RST 0x00000200
619#define ISR_DMAW_TO_RST 0x00000400
620#define ISR_TX_CREDIT 0x00000800
621#define ISR_GPHY 0x00001000
622/* GPHY low power state interrupt */
623#define ISR_GPHY_LPW 0x00002000
624#define ISR_TXQ_TO_RST 0x00004000
625#define ISR_TX_PKT 0x00008000
626#define ISR_RX_PKT_0 0x00010000
627#define ISR_RX_PKT_1 0x00020000
628#define ISR_RX_PKT_2 0x00040000
629#define ISR_RX_PKT_3 0x00080000
630#define ISR_MAC_RX 0x00100000
631#define ISR_MAC_TX 0x00200000
632#define ISR_UR_DETECTED 0x00400000
633#define ISR_FERR_DETECTED 0x00800000
634#define ISR_NFERR_DETECTED 0x01000000
635#define ISR_CERR_DETECTED 0x02000000
636#define ISR_PHY_LINKDOWN 0x04000000
637#define ISR_DIS_INT 0x80000000
638
639/* Interrupt Mask Register */
640#define REG_IMR 0x1604
641
642#define IMR_NORMAL_MASK (\
643 ISR_MANUAL |\
644 ISR_HW_RXF_OV |\
645 ISR_RFD0_UR |\
646 ISR_TXF_UR |\
647 ISR_DMAR_TO_RST |\
648 ISR_TXQ_TO_RST |\
649 ISR_DMAW_TO_RST |\
650 ISR_GPHY |\
651 ISR_TX_PKT |\
652 ISR_RX_PKT_0 |\
653 ISR_GPHY_LPW |\
654 ISR_PHY_LINKDOWN)
655
656#define ISR_RX_PKT (\
657 ISR_RX_PKT_0 |\
658 ISR_RX_PKT_1 |\
659 ISR_RX_PKT_2 |\
660 ISR_RX_PKT_3)
661
662#define ISR_OVER (\
663 ISR_RFD0_UR |\
664 ISR_RFD1_UR |\
665 ISR_RFD2_UR |\
666 ISR_RFD3_UR |\
667 ISR_HW_RXF_OV |\
668 ISR_TXF_UR)
669
670#define ISR_ERROR (\
671 ISR_DMAR_TO_RST |\
672 ISR_TXQ_TO_RST |\
673 ISR_DMAW_TO_RST |\
674 ISR_PHY_LINKDOWN)
675
676#define REG_INT_RETRIG_TIMER 0x1608
677#define INT_RETRIG_TIMER_MASK 0xFFFF
678
679#define REG_HDS_CTRL 0x160C
680#define HDS_CTRL_EN 0x0001
681#define HDS_CTRL_BACKFILLSIZE_SHIFT 8
682#define HDS_CTRL_BACKFILLSIZE_MASK 0x0FFF
683#define HDS_CTRL_MAX_HDRSIZE_SHIFT 20
684#define HDS_CTRL_MAC_HDRSIZE_MASK 0x0FFF
685
686#define REG_MAC_RX_STATUS_BIN 0x1700
687#define REG_MAC_RX_STATUS_END 0x175c
688#define REG_MAC_TX_STATUS_BIN 0x1760
689#define REG_MAC_TX_STATUS_END 0x17c0
690
691/* DEBUG ADDR */
692#define REG_DEBUG_DATA0 0x1900
693#define REG_DEBUG_DATA1 0x1904
694
695/* PHY Control Register */
696#define MII_BMCR 0x00
697#define BMCR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
698#define BMCR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
699#define BMCR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
700#define BMCR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
701#define BMCR_ISOLATE 0x0400 /* Isolate PHY from MII */
702#define BMCR_POWER_DOWN 0x0800 /* Power down */
703#define BMCR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
704#define BMCR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
705#define BMCR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
706#define BMCR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
707#define BMCR_SPEED_MASK 0x2040
708#define BMCR_SPEED_1000 0x0040
709#define BMCR_SPEED_100 0x2000
710#define BMCR_SPEED_10 0x0000
711
712/* PHY Status Register */
713#define MII_BMSR 0x01
714#define BMMSR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
715#define BMSR_JABBER_DETECT 0x0002 /* Jabber Detected */
716#define BMSR_LINK_STATUS 0x0004 /* Link Status 1 = link */
717#define BMSR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
718#define BMSR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
719#define BMSR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
720#define BMSR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
721#define BMSR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
722#define BMSR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
723#define BMSR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
724#define BMSR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
725#define BMSR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
726#define BMSR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
727#define BMMII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
728#define BMMII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
729
730#define MII_PHYSID1 0x02
731#define MII_PHYSID2 0x03
732
733/* Autoneg Advertisement Register */
734#define MII_ADVERTISE 0x04
735#define ADVERTISE_SPEED_MASK 0x01E0
736#define ADVERTISE_DEFAULT_CAP 0x0DE0
737
738/* 1000BASE-T Control Register */
739#define MII_GIGA_CR 0x09
740#define GIGA_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port 0=DTE device */
741
742#define GIGA_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master 0=Configure PHY as Slave */
743#define GIGA_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
744#define GIGA_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
745#define GIGA_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
746#define GIGA_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
747#define GIGA_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
748#define GIGA_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
749#define GIGA_CR_1000T_SPEED_MASK 0x0300
750#define GIGA_CR_1000T_DEFAULT_CAP 0x0300
751
752/* PHY Specific Status Register */
753#define MII_GIGA_PSSR 0x11
754#define GIGA_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
755#define GIGA_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
756#define GIGA_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
757#define GIGA_PSSR_10MBS 0x0000 /* 00=10Mbs */
758#define GIGA_PSSR_100MBS 0x4000 /* 01=100Mbs */
759#define GIGA_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
760
761/* PHY Interrupt Enable Register */
762#define MII_IER 0x12
763#define IER_LINK_UP 0x0400
764#define IER_LINK_DOWN 0x0800
765
766/* PHY Interrupt Status Register */
767#define MII_ISR 0x13
768#define ISR_LINK_UP 0x0400
769#define ISR_LINK_DOWN 0x0800
770
771/* Cable-Detect-Test Control Register */
772#define MII_CDTC 0x16
773#define CDTC_EN_OFF 0 /* sc */
774#define CDTC_EN_BITS 1
775#define CDTC_PAIR_OFF 8
776#define CDTC_PAIR_BIT 2
777
778/* Cable-Detect-Test Status Register */
779#define MII_CDTS 0x1C
780#define CDTS_STATUS_OFF 8
781#define CDTS_STATUS_BITS 2
782#define CDTS_STATUS_NORMAL 0
783#define CDTS_STATUS_SHORT 1
784#define CDTS_STATUS_OPEN 2
785#define CDTS_STATUS_INVALID 3
786
787#define MII_DBG_ADDR 0x1D
788#define MII_DBG_DATA 0x1E
789
790#define MII_ANA_CTRL_0 0x0
791#define ANA_RESTART_CAL 0x0001
792#define ANA_MANUL_SWICH_ON_SHIFT 0x1
793#define ANA_MANUL_SWICH_ON_MASK 0xF
794#define ANA_MAN_ENABLE 0x0020
795#define ANA_SEL_HSP 0x0040
796#define ANA_EN_HB 0x0080
797#define ANA_EN_HBIAS 0x0100
798#define ANA_OEN_125M 0x0200
799#define ANA_EN_LCKDT 0x0400
800#define ANA_LCKDT_PHY 0x0800
801#define ANA_AFE_MODE 0x1000
802#define ANA_VCO_SLOW 0x2000
803#define ANA_VCO_FAST 0x4000
804#define ANA_SEL_CLK125M_DSP 0x8000
805
806#define MII_ANA_CTRL_4 0x4
807#define ANA_IECHO_ADJ_MASK 0xF
808#define ANA_IECHO_ADJ_3_SHIFT 0
809#define ANA_IECHO_ADJ_2_SHIFT 4
810#define ANA_IECHO_ADJ_1_SHIFT 8
811#define ANA_IECHO_ADJ_0_SHIFT 12
812
813#define MII_ANA_CTRL_5 0x5
814#define ANA_SERDES_CDR_BW_SHIFT 0
815#define ANA_SERDES_CDR_BW_MASK 0x3
816#define ANA_MS_PAD_DBG 0x0004
817#define ANA_SPEEDUP_DBG 0x0008
818#define ANA_SERDES_TH_LOS_SHIFT 4
819#define ANA_SERDES_TH_LOS_MASK 0x3
820#define ANA_SERDES_EN_DEEM 0x0040
821#define ANA_SERDES_TXELECIDLE 0x0080
822#define ANA_SERDES_BEACON 0x0100
823#define ANA_SERDES_HALFTXDR 0x0200
824#define ANA_SERDES_SEL_HSP 0x0400
825#define ANA_SERDES_EN_PLL 0x0800
826#define ANA_SERDES_EN 0x1000
827#define ANA_SERDES_EN_LCKDT 0x2000
828
829#define MII_ANA_CTRL_11 0xB
830#define ANA_PS_HIB_EN 0x8000
831
832#define MII_ANA_CTRL_18 0x12
833#define ANA_TEST_MODE_10BT_01SHIFT 0
834#define ANA_TEST_MODE_10BT_01MASK 0x3
835#define ANA_LOOP_SEL_10BT 0x0004
836#define ANA_RGMII_MODE_SW 0x0008
837#define ANA_EN_LONGECABLE 0x0010
838#define ANA_TEST_MODE_10BT_2 0x0020
839#define ANA_EN_10BT_IDLE 0x0400
840#define ANA_EN_MASK_TB 0x0800
841#define ANA_TRIGGER_SEL_TIMER_SHIFT 12
842#define ANA_TRIGGER_SEL_TIMER_MASK 0x3
843#define ANA_INTERVAL_SEL_TIMER_SHIFT 14
844#define ANA_INTERVAL_SEL_TIMER_MASK 0x3
845
846#define MII_ANA_CTRL_41 0x29
847#define ANA_TOP_PS_EN 0x8000
848
849#define MII_ANA_CTRL_54 0x36
850#define ANA_LONG_CABLE_TH_100_SHIFT 0
851#define ANA_LONG_CABLE_TH_100_MASK 0x3F
852#define ANA_DESERVED 0x0040
853#define ANA_EN_LIT_CH 0x0080
854#define ANA_SHORT_CABLE_TH_100_SHIFT 8
855#define ANA_SHORT_CABLE_TH_100_MASK 0x3F
856#define ANA_BP_BAD_LINK_ACCUM 0x4000
857#define ANA_BP_SMALL_BW 0x8000
858
859#endif /*_ATL1C_HW_H_*/
diff --git a/drivers/net/atl1c/atl1c_main.c b/drivers/net/atl1c/atl1c_main.c
new file mode 100644
index 000000000000..deb7b53167ee
--- /dev/null
+++ b/drivers/net/atl1c/atl1c_main.c
@@ -0,0 +1,2797 @@
1/*
2 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "atl1c.h"
23
24#define ATL1C_DRV_VERSION "1.0.0.1-NAPI"
25char atl1c_driver_name[] = "atl1c";
26char atl1c_driver_version[] = ATL1C_DRV_VERSION;
27#define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062
28#define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063
29/*
30 * atl1c_pci_tbl - PCI Device ID Table
31 *
32 * Wildcard entries (PCI_ANY_ID) should come last
33 * Last entry must be all 0s
34 *
35 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
36 * Class, Class Mask, private data (not used) }
37 */
38static struct pci_device_id atl1c_pci_tbl[] = {
39 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1C)},
40 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2C)},
41 /* required last entry */
42 { 0 }
43};
44MODULE_DEVICE_TABLE(pci, atl1c_pci_tbl);
45
46MODULE_AUTHOR("Jie Yang <jie.yang@atheros.com>");
47MODULE_DESCRIPTION("Atheros 1000M Ethernet Network Driver");
48MODULE_LICENSE("GPL");
49MODULE_VERSION(ATL1C_DRV_VERSION);
50
51static int atl1c_stop_mac(struct atl1c_hw *hw);
52static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw);
53static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw);
54static void atl1c_disable_l0s_l1(struct atl1c_hw *hw);
55static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup);
56static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter);
57static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter, u8 que,
58 int *work_done, int work_to_do);
59
60static const u16 atl1c_pay_load_size[] = {
61 128, 256, 512, 1024, 2048, 4096,
62};
63
64static const u16 atl1c_rfd_prod_idx_regs[AT_MAX_RECEIVE_QUEUE] =
65{
66 REG_MB_RFD0_PROD_IDX,
67 REG_MB_RFD1_PROD_IDX,
68 REG_MB_RFD2_PROD_IDX,
69 REG_MB_RFD3_PROD_IDX
70};
71
72static const u16 atl1c_rfd_addr_lo_regs[AT_MAX_RECEIVE_QUEUE] =
73{
74 REG_RFD0_HEAD_ADDR_LO,
75 REG_RFD1_HEAD_ADDR_LO,
76 REG_RFD2_HEAD_ADDR_LO,
77 REG_RFD3_HEAD_ADDR_LO
78};
79
80static const u16 atl1c_rrd_addr_lo_regs[AT_MAX_RECEIVE_QUEUE] =
81{
82 REG_RRD0_HEAD_ADDR_LO,
83 REG_RRD1_HEAD_ADDR_LO,
84 REG_RRD2_HEAD_ADDR_LO,
85 REG_RRD3_HEAD_ADDR_LO
86};
87
88static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
89 NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
90
91/*
92 * atl1c_init_pcie - init PCIE module
93 */
94static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
95{
96 u32 data;
97 u32 pci_cmd;
98 struct pci_dev *pdev = hw->adapter->pdev;
99
100 AT_READ_REG(hw, PCI_COMMAND, &pci_cmd);
101 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
102 pci_cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
103 PCI_COMMAND_IO);
104 AT_WRITE_REG(hw, PCI_COMMAND, pci_cmd);
105
106 /*
107 * Clear any PowerSaveing Settings
108 */
109 pci_enable_wake(pdev, PCI_D3hot, 0);
110 pci_enable_wake(pdev, PCI_D3cold, 0);
111
112 /*
113 * Mask some pcie error bits
114 */
115 AT_READ_REG(hw, REG_PCIE_UC_SEVERITY, &data);
116 data &= ~PCIE_UC_SERVRITY_DLP;
117 data &= ~PCIE_UC_SERVRITY_FCP;
118 AT_WRITE_REG(hw, REG_PCIE_UC_SEVERITY, data);
119
120 if (flag & ATL1C_PCIE_L0S_L1_DISABLE)
121 atl1c_disable_l0s_l1(hw);
122 if (flag & ATL1C_PCIE_PHY_RESET)
123 AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT);
124 else
125 AT_WRITE_REG(hw, REG_GPHY_CTRL,
126 GPHY_CTRL_DEFAULT | GPHY_CTRL_EXT_RESET);
127
128 msleep(1);
129}
130
131/*
132 * atl1c_irq_enable - Enable default interrupt generation settings
133 * @adapter: board private structure
134 */
135static inline void atl1c_irq_enable(struct atl1c_adapter *adapter)
136{
137 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
138 AT_WRITE_REG(&adapter->hw, REG_ISR, 0x7FFFFFFF);
139 AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
140 AT_WRITE_FLUSH(&adapter->hw);
141 }
142}
143
144/*
145 * atl1c_irq_disable - Mask off interrupt generation on the NIC
146 * @adapter: board private structure
147 */
148static inline void atl1c_irq_disable(struct atl1c_adapter *adapter)
149{
150 atomic_inc(&adapter->irq_sem);
151 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
152 AT_WRITE_FLUSH(&adapter->hw);
153 synchronize_irq(adapter->pdev->irq);
154}
155
156/*
157 * atl1c_irq_reset - reset interrupt confiure on the NIC
158 * @adapter: board private structure
159 */
160static inline void atl1c_irq_reset(struct atl1c_adapter *adapter)
161{
162 atomic_set(&adapter->irq_sem, 1);
163 atl1c_irq_enable(adapter);
164}
165
166/*
167 * atl1c_phy_config - Timer Call-back
168 * @data: pointer to netdev cast into an unsigned long
169 */
170static void atl1c_phy_config(unsigned long data)
171{
172 struct atl1c_adapter *adapter = (struct atl1c_adapter *) data;
173 struct atl1c_hw *hw = &adapter->hw;
174 unsigned long flags;
175
176 spin_lock_irqsave(&adapter->mdio_lock, flags);
177 atl1c_restart_autoneg(hw);
178 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
179}
180
181void atl1c_reinit_locked(struct atl1c_adapter *adapter)
182{
183
184 WARN_ON(in_interrupt());
185 atl1c_down(adapter);
186 atl1c_up(adapter);
187 clear_bit(__AT_RESETTING, &adapter->flags);
188}
189
190static void atl1c_reset_task(struct work_struct *work)
191{
192 struct atl1c_adapter *adapter;
193 struct net_device *netdev;
194
195 adapter = container_of(work, struct atl1c_adapter, reset_task);
196 netdev = adapter->netdev;
197
198 netif_device_detach(netdev);
199 atl1c_down(adapter);
200 atl1c_up(adapter);
201 netif_device_attach(netdev);
202}
203
204static void atl1c_check_link_status(struct atl1c_adapter *adapter)
205{
206 struct atl1c_hw *hw = &adapter->hw;
207 struct net_device *netdev = adapter->netdev;
208 struct pci_dev *pdev = adapter->pdev;
209 int err;
210 unsigned long flags;
211 u16 speed, duplex, phy_data;
212
213 spin_lock_irqsave(&adapter->mdio_lock, flags);
214 /* MII_BMSR must read twise */
215 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
216 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
217 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
218
219 if ((phy_data & BMSR_LSTATUS) == 0) {
220 /* link down */
221 if (netif_carrier_ok(netdev)) {
222 hw->hibernate = true;
223 atl1c_set_aspm(hw, false);
224 if (atl1c_stop_mac(hw) != 0)
225 if (netif_msg_hw(adapter))
226 dev_warn(&pdev->dev,
227 "stop mac failed\n");
228 }
229 netif_carrier_off(netdev);
230 } else {
231 /* Link Up */
232 hw->hibernate = false;
233 spin_lock_irqsave(&adapter->mdio_lock, flags);
234 err = atl1c_get_speed_and_duplex(hw, &speed, &duplex);
235 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
236 if (unlikely(err))
237 return;
238 /* link result is our setting */
239 if (adapter->link_speed != speed ||
240 adapter->link_duplex != duplex) {
241 adapter->link_speed = speed;
242 adapter->link_duplex = duplex;
243 atl1c_enable_tx_ctrl(hw);
244 atl1c_enable_rx_ctrl(hw);
245 atl1c_setup_mac_ctrl(adapter);
246 atl1c_set_aspm(hw, true);
247 if (netif_msg_link(adapter))
248 dev_info(&pdev->dev,
249 "%s: %s NIC Link is Up<%d Mbps %s>\n",
250 atl1c_driver_name, netdev->name,
251 adapter->link_speed,
252 adapter->link_duplex == FULL_DUPLEX ?
253 "Full Duplex" : "Half Duplex");
254 }
255 if (!netif_carrier_ok(netdev))
256 netif_carrier_on(netdev);
257 }
258}
259
260/*
261 * atl1c_link_chg_task - deal with link change event Out of interrupt context
262 * @netdev: network interface device structure
263 */
264static void atl1c_link_chg_task(struct work_struct *work)
265{
266 struct atl1c_adapter *adapter;
267
268 adapter = container_of(work, struct atl1c_adapter, link_chg_task);
269 atl1c_check_link_status(adapter);
270}
271
272static void atl1c_link_chg_event(struct atl1c_adapter *adapter)
273{
274 struct net_device *netdev = adapter->netdev;
275 struct pci_dev *pdev = adapter->pdev;
276 u16 phy_data;
277 u16 link_up;
278
279 spin_lock(&adapter->mdio_lock);
280 atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
281 atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
282 spin_unlock(&adapter->mdio_lock);
283 link_up = phy_data & BMSR_LSTATUS;
284 /* notify upper layer link down ASAP */
285 if (!link_up) {
286 if (netif_carrier_ok(netdev)) {
287 /* old link state: Up */
288 netif_carrier_off(netdev);
289 if (netif_msg_link(adapter))
290 dev_info(&pdev->dev,
291 "%s: %s NIC Link is Down\n",
292 atl1c_driver_name, netdev->name);
293 adapter->link_speed = SPEED_0;
294 }
295 }
296 schedule_work(&adapter->link_chg_task);
297}
298
299static void atl1c_del_timer(struct atl1c_adapter *adapter)
300{
301 del_timer_sync(&adapter->phy_config_timer);
302}
303
304static void atl1c_cancel_work(struct atl1c_adapter *adapter)
305{
306 cancel_work_sync(&adapter->reset_task);
307 cancel_work_sync(&adapter->link_chg_task);
308}
309
310/*
311 * atl1c_tx_timeout - Respond to a Tx Hang
312 * @netdev: network interface device structure
313 */
314static void atl1c_tx_timeout(struct net_device *netdev)
315{
316 struct atl1c_adapter *adapter = netdev_priv(netdev);
317
318 /* Do the reset outside of interrupt context */
319 schedule_work(&adapter->reset_task);
320}
321
322/*
323 * atl1c_set_multi - Multicast and Promiscuous mode set
324 * @netdev: network interface device structure
325 *
326 * The set_multi entry point is called whenever the multicast address
327 * list or the network interface flags are updated. This routine is
328 * responsible for configuring the hardware for proper multicast,
329 * promiscuous mode, and all-multi behavior.
330 */
331static void atl1c_set_multi(struct net_device *netdev)
332{
333 struct atl1c_adapter *adapter = netdev_priv(netdev);
334 struct atl1c_hw *hw = &adapter->hw;
335 struct dev_mc_list *mc_ptr;
336 u32 mac_ctrl_data;
337 u32 hash_value;
338
339 /* Check for Promiscuous and All Multicast modes */
340 AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
341
342 if (netdev->flags & IFF_PROMISC) {
343 mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
344 } else if (netdev->flags & IFF_ALLMULTI) {
345 mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
346 mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
347 } else {
348 mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
349 }
350
351 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
352
353 /* clear the old settings from the multicast hash table */
354 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
355 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
356
357 /* comoute mc addresses' hash value ,and put it into hash table */
358 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
359 hash_value = atl1c_hash_mc_addr(hw, mc_ptr->dmi_addr);
360 atl1c_hash_set(hw, hash_value);
361 }
362}
363
364static void atl1c_vlan_rx_register(struct net_device *netdev,
365 struct vlan_group *grp)
366{
367 struct atl1c_adapter *adapter = netdev_priv(netdev);
368 struct pci_dev *pdev = adapter->pdev;
369 u32 mac_ctrl_data = 0;
370
371 if (netif_msg_pktdata(adapter))
372 dev_dbg(&pdev->dev, "atl1c_vlan_rx_register\n");
373
374 atl1c_irq_disable(adapter);
375
376 adapter->vlgrp = grp;
377 AT_READ_REG(&adapter->hw, REG_MAC_CTRL, &mac_ctrl_data);
378
379 if (grp) {
380 /* enable VLAN tag insert/strip */
381 mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
382 } else {
383 /* disable VLAN tag insert/strip */
384 mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
385 }
386
387 AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
388 atl1c_irq_enable(adapter);
389}
390
391static void atl1c_restore_vlan(struct atl1c_adapter *adapter)
392{
393 struct pci_dev *pdev = adapter->pdev;
394
395 if (netif_msg_pktdata(adapter))
396 dev_dbg(&pdev->dev, "atl1c_restore_vlan !");
397 atl1c_vlan_rx_register(adapter->netdev, adapter->vlgrp);
398}
399/*
400 * atl1c_set_mac - Change the Ethernet Address of the NIC
401 * @netdev: network interface device structure
402 * @p: pointer to an address structure
403 *
404 * Returns 0 on success, negative on failure
405 */
406static int atl1c_set_mac_addr(struct net_device *netdev, void *p)
407{
408 struct atl1c_adapter *adapter = netdev_priv(netdev);
409 struct sockaddr *addr = p;
410
411 if (!is_valid_ether_addr(addr->sa_data))
412 return -EADDRNOTAVAIL;
413
414 if (netif_running(netdev))
415 return -EBUSY;
416
417 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
418 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
419
420 atl1c_hw_set_mac_addr(&adapter->hw);
421
422 return 0;
423}
424
425static void atl1c_set_rxbufsize(struct atl1c_adapter *adapter,
426 struct net_device *dev)
427{
428 int mtu = dev->mtu;
429
430 adapter->rx_buffer_len = mtu > AT_RX_BUF_SIZE ?
431 roundup(mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN, 8) : AT_RX_BUF_SIZE;
432}
433/*
434 * atl1c_change_mtu - Change the Maximum Transfer Unit
435 * @netdev: network interface device structure
436 * @new_mtu: new value for maximum frame size
437 *
438 * Returns 0 on success, negative on failure
439 */
440static int atl1c_change_mtu(struct net_device *netdev, int new_mtu)
441{
442 struct atl1c_adapter *adapter = netdev_priv(netdev);
443 int old_mtu = netdev->mtu;
444 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
445
446 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
447 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
448 if (netif_msg_link(adapter))
449 dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
450 return -EINVAL;
451 }
452 /* set MTU */
453 if (old_mtu != new_mtu && netif_running(netdev)) {
454 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
455 msleep(1);
456 netdev->mtu = new_mtu;
457 adapter->hw.max_frame_size = new_mtu;
458 atl1c_set_rxbufsize(adapter, netdev);
459 atl1c_down(adapter);
460 atl1c_up(adapter);
461 clear_bit(__AT_RESETTING, &adapter->flags);
462 if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) {
463 u32 phy_data;
464
465 AT_READ_REG(&adapter->hw, 0x1414, &phy_data);
466 phy_data |= 0x10000000;
467 AT_WRITE_REG(&adapter->hw, 0x1414, phy_data);
468 }
469
470 }
471 return 0;
472}
473
474/*
475 * caller should hold mdio_lock
476 */
477static int atl1c_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
478{
479 struct atl1c_adapter *adapter = netdev_priv(netdev);
480 u16 result;
481
482 atl1c_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);
483 return result;
484}
485
486static void atl1c_mdio_write(struct net_device *netdev, int phy_id,
487 int reg_num, int val)
488{
489 struct atl1c_adapter *adapter = netdev_priv(netdev);
490
491 atl1c_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val);
492}
493
494/*
495 * atl1c_mii_ioctl -
496 * @netdev:
497 * @ifreq:
498 * @cmd:
499 */
500static int atl1c_mii_ioctl(struct net_device *netdev,
501 struct ifreq *ifr, int cmd)
502{
503 struct atl1c_adapter *adapter = netdev_priv(netdev);
504 struct pci_dev *pdev = adapter->pdev;
505 struct mii_ioctl_data *data = if_mii(ifr);
506 unsigned long flags;
507 int retval = 0;
508
509 if (!netif_running(netdev))
510 return -EINVAL;
511
512 spin_lock_irqsave(&adapter->mdio_lock, flags);
513 switch (cmd) {
514 case SIOCGMIIPHY:
515 data->phy_id = 0;
516 break;
517
518 case SIOCGMIIREG:
519 if (!capable(CAP_NET_ADMIN)) {
520 retval = -EPERM;
521 goto out;
522 }
523 if (atl1c_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
524 &data->val_out)) {
525 retval = -EIO;
526 goto out;
527 }
528 break;
529
530 case SIOCSMIIREG:
531 if (!capable(CAP_NET_ADMIN)) {
532 retval = -EPERM;
533 goto out;
534 }
535 if (data->reg_num & ~(0x1F)) {
536 retval = -EFAULT;
537 goto out;
538 }
539
540 dev_dbg(&pdev->dev, "<atl1c_mii_ioctl> write %x %x",
541 data->reg_num, data->val_in);
542 if (atl1c_write_phy_reg(&adapter->hw,
543 data->reg_num, data->val_in)) {
544 retval = -EIO;
545 goto out;
546 }
547 break;
548
549 default:
550 retval = -EOPNOTSUPP;
551 break;
552 }
553out:
554 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
555 return retval;
556}
557
558/*
559 * atl1c_ioctl -
560 * @netdev:
561 * @ifreq:
562 * @cmd:
563 */
564static int atl1c_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
565{
566 switch (cmd) {
567 case SIOCGMIIPHY:
568 case SIOCGMIIREG:
569 case SIOCSMIIREG:
570 return atl1c_mii_ioctl(netdev, ifr, cmd);
571 default:
572 return -EOPNOTSUPP;
573 }
574}
575
576/*
577 * atl1c_alloc_queues - Allocate memory for all rings
578 * @adapter: board private structure to initialize
579 *
580 */
581static int __devinit atl1c_alloc_queues(struct atl1c_adapter *adapter)
582{
583 return 0;
584}
585
586static void atl1c_set_mac_type(struct atl1c_hw *hw)
587{
588 switch (hw->device_id) {
589 case PCI_DEVICE_ID_ATTANSIC_L2C:
590 hw->nic_type = athr_l2c;
591 break;
592
593 case PCI_DEVICE_ID_ATTANSIC_L1C:
594 hw->nic_type = athr_l1c;
595 break;
596
597 default:
598 break;
599 }
600}
601
602static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
603{
604 u32 phy_status_data;
605 u32 link_ctrl_data;
606
607 atl1c_set_mac_type(hw);
608 AT_READ_REG(hw, REG_PHY_STATUS, &phy_status_data);
609 AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
610
611 hw->ctrl_flags = ATL1C_INTR_CLEAR_ON_READ |
612 ATL1C_INTR_MODRT_ENABLE |
613 ATL1C_RX_IPV6_CHKSUM |
614 ATL1C_TXQ_MODE_ENHANCE;
615 if (link_ctrl_data & LINK_CTRL_L0S_EN)
616 hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT;
617 if (link_ctrl_data & LINK_CTRL_L1_EN)
618 hw->ctrl_flags |= ATL1C_ASPM_L1_SUPPORT;
619
620 if (hw->nic_type == athr_l1c) {
621 hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON;
622 hw->ctrl_flags |= ATL1C_LINK_CAP_1000M;
623 }
624 return 0;
625}
626/*
627 * atl1c_sw_init - Initialize general software structures (struct atl1c_adapter)
628 * @adapter: board private structure to initialize
629 *
630 * atl1c_sw_init initializes the Adapter private data structure.
631 * Fields are initialized based on PCI device information and
632 * OS network device settings (MTU size).
633 */
634static int __devinit atl1c_sw_init(struct atl1c_adapter *adapter)
635{
636 struct atl1c_hw *hw = &adapter->hw;
637 struct pci_dev *pdev = adapter->pdev;
638
639 adapter->wol = 0;
640 adapter->link_speed = SPEED_0;
641 adapter->link_duplex = FULL_DUPLEX;
642 adapter->num_rx_queues = AT_DEF_RECEIVE_QUEUE;
643 adapter->tpd_ring[0].count = 1024;
644 adapter->rfd_ring[0].count = 512;
645
646 hw->vendor_id = pdev->vendor;
647 hw->device_id = pdev->device;
648 hw->subsystem_vendor_id = pdev->subsystem_vendor;
649 hw->subsystem_id = pdev->subsystem_device;
650
651 /* before link up, we assume hibernate is true */
652 hw->hibernate = true;
653 hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
654 if (atl1c_setup_mac_funcs(hw) != 0) {
655 dev_err(&pdev->dev, "set mac function pointers failed\n");
656 return -1;
657 }
658 hw->intr_mask = IMR_NORMAL_MASK;
659 hw->phy_configured = false;
660 hw->preamble_len = 7;
661 hw->max_frame_size = adapter->netdev->mtu;
662 if (adapter->num_rx_queues < 2) {
663 hw->rss_type = atl1c_rss_disable;
664 hw->rss_mode = atl1c_rss_mode_disable;
665 } else {
666 hw->rss_type = atl1c_rss_ipv4;
667 hw->rss_mode = atl1c_rss_mul_que_mul_int;
668 hw->rss_hash_bits = 16;
669 }
670 hw->autoneg_advertised = ADVERTISED_Autoneg;
671 hw->indirect_tab = 0xE4E4E4E4;
672 hw->base_cpu = 0;
673
674 hw->ict = 50000; /* 100ms */
675 hw->smb_timer = 200000; /* 400ms */
676 hw->cmb_tpd = 4;
677 hw->cmb_tx_timer = 1; /* 2 us */
678 hw->rx_imt = 200;
679 hw->tx_imt = 1000;
680
681 hw->tpd_burst = 5;
682 hw->rfd_burst = 8;
683 hw->dma_order = atl1c_dma_ord_out;
684 hw->dmar_block = atl1c_dma_req_1024;
685 hw->dmaw_block = atl1c_dma_req_1024;
686 hw->dmar_dly_cnt = 15;
687 hw->dmaw_dly_cnt = 4;
688
689 if (atl1c_alloc_queues(adapter)) {
690 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
691 return -ENOMEM;
692 }
693 /* TODO */
694 atl1c_set_rxbufsize(adapter, adapter->netdev);
695 atomic_set(&adapter->irq_sem, 1);
696 spin_lock_init(&adapter->mdio_lock);
697 spin_lock_init(&adapter->tx_lock);
698 set_bit(__AT_DOWN, &adapter->flags);
699
700 return 0;
701}
702
703/*
704 * atl1c_clean_tx_ring - Free Tx-skb
705 * @adapter: board private structure
706 */
707static void atl1c_clean_tx_ring(struct atl1c_adapter *adapter,
708 enum atl1c_trans_queue type)
709{
710 struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
711 struct atl1c_buffer *buffer_info;
712 struct pci_dev *pdev = adapter->pdev;
713 u16 index, ring_count;
714
715 ring_count = tpd_ring->count;
716 for (index = 0; index < ring_count; index++) {
717 buffer_info = &tpd_ring->buffer_info[index];
718 if (buffer_info->state == ATL1_BUFFER_FREE)
719 continue;
720 if (buffer_info->dma)
721 pci_unmap_single(pdev, buffer_info->dma,
722 buffer_info->length,
723 PCI_DMA_TODEVICE);
724 if (buffer_info->skb)
725 dev_kfree_skb(buffer_info->skb);
726 buffer_info->dma = 0;
727 buffer_info->skb = NULL;
728 buffer_info->state = ATL1_BUFFER_FREE;
729 }
730
731 /* Zero out Tx-buffers */
732 memset(tpd_ring->desc, 0, sizeof(struct atl1c_tpd_desc) *
733 ring_count);
734 atomic_set(&tpd_ring->next_to_clean, 0);
735 tpd_ring->next_to_use = 0;
736}
737
738/*
739 * atl1c_clean_rx_ring - Free rx-reservation skbs
740 * @adapter: board private structure
741 */
742static void atl1c_clean_rx_ring(struct atl1c_adapter *adapter)
743{
744 struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring;
745 struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring;
746 struct atl1c_buffer *buffer_info;
747 struct pci_dev *pdev = adapter->pdev;
748 int i, j;
749
750 for (i = 0; i < adapter->num_rx_queues; i++) {
751 for (j = 0; j < rfd_ring[i].count; j++) {
752 buffer_info = &rfd_ring[i].buffer_info[j];
753 if (buffer_info->state == ATL1_BUFFER_FREE)
754 continue;
755 if (buffer_info->dma)
756 pci_unmap_single(pdev, buffer_info->dma,
757 buffer_info->length,
758 PCI_DMA_FROMDEVICE);
759 if (buffer_info->skb)
760 dev_kfree_skb(buffer_info->skb);
761 buffer_info->state = ATL1_BUFFER_FREE;
762 buffer_info->skb = NULL;
763 }
764 /* zero out the descriptor ring */
765 memset(rfd_ring[i].desc, 0, rfd_ring[i].size);
766 rfd_ring[i].next_to_clean = 0;
767 rfd_ring[i].next_to_use = 0;
768 rrd_ring[i].next_to_use = 0;
769 rrd_ring[i].next_to_clean = 0;
770 }
771}
772
773/*
774 * Read / Write Ptr Initialize:
775 */
776static void atl1c_init_ring_ptrs(struct atl1c_adapter *adapter)
777{
778 struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
779 struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring;
780 struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring;
781 struct atl1c_buffer *buffer_info;
782 int i, j;
783
784 for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
785 tpd_ring[i].next_to_use = 0;
786 atomic_set(&tpd_ring[i].next_to_clean, 0);
787 buffer_info = tpd_ring[i].buffer_info;
788 for (j = 0; j < tpd_ring->count; j++)
789 buffer_info[i].state = ATL1_BUFFER_FREE;
790 }
791 for (i = 0; i < adapter->num_rx_queues; i++) {
792 rfd_ring[i].next_to_use = 0;
793 rfd_ring[i].next_to_clean = 0;
794 rrd_ring[i].next_to_use = 0;
795 rrd_ring[i].next_to_clean = 0;
796 for (j = 0; j < rfd_ring[i].count; j++) {
797 buffer_info = &rfd_ring[i].buffer_info[j];
798 buffer_info->state = ATL1_BUFFER_FREE;
799 }
800 }
801}
802
803/*
804 * atl1c_free_ring_resources - Free Tx / RX descriptor Resources
805 * @adapter: board private structure
806 *
807 * Free all transmit software resources
808 */
809static void atl1c_free_ring_resources(struct atl1c_adapter *adapter)
810{
811 struct pci_dev *pdev = adapter->pdev;
812
813 pci_free_consistent(pdev, adapter->ring_header.size,
814 adapter->ring_header.desc,
815 adapter->ring_header.dma);
816 adapter->ring_header.desc = NULL;
817
818 /* Note: just free tdp_ring.buffer_info,
819 * it contain rfd_ring.buffer_info, do not double free */
820 if (adapter->tpd_ring[0].buffer_info) {
821 kfree(adapter->tpd_ring[0].buffer_info);
822 adapter->tpd_ring[0].buffer_info = NULL;
823 }
824}
825
826/*
827 * atl1c_setup_mem_resources - allocate Tx / RX descriptor resources
828 * @adapter: board private structure
829 *
830 * Return 0 on success, negative on failure
831 */
832static int atl1c_setup_ring_resources(struct atl1c_adapter *adapter)
833{
834 struct pci_dev *pdev = adapter->pdev;
835 struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
836 struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring;
837 struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring;
838 struct atl1c_ring_header *ring_header = &adapter->ring_header;
839 int num_rx_queues = adapter->num_rx_queues;
840 int size;
841 int i;
842 int count = 0;
843 int rx_desc_count = 0;
844 u32 offset = 0;
845
846 rrd_ring[0].count = rfd_ring[0].count;
847 for (i = 1; i < AT_MAX_TRANSMIT_QUEUE; i++)
848 tpd_ring[i].count = tpd_ring[0].count;
849
850 for (i = 1; i < adapter->num_rx_queues; i++)
851 rfd_ring[i].count = rrd_ring[i].count = rfd_ring[0].count;
852
853 /* 2 tpd queue, one high priority queue,
854 * another normal priority queue */
855 size = sizeof(struct atl1c_buffer) * (tpd_ring->count * 2 +
856 rfd_ring->count * num_rx_queues);
857 tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
858 if (unlikely(!tpd_ring->buffer_info)) {
859 dev_err(&pdev->dev, "kzalloc failed, size = %d\n",
860 size);
861 goto err_nomem;
862 }
863 for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
864 tpd_ring[i].buffer_info =
865 (struct atl1c_buffer *) (tpd_ring->buffer_info + count);
866 count += tpd_ring[i].count;
867 }
868
869 for (i = 0; i < num_rx_queues; i++) {
870 rfd_ring[i].buffer_info =
871 (struct atl1c_buffer *) (tpd_ring->buffer_info + count);
872 count += rfd_ring[i].count;
873 rx_desc_count += rfd_ring[i].count;
874 }
875 /*
876 * real ring DMA buffer
877 * each ring/block may need up to 8 bytes for alignment, hence the
878 * additional bytes tacked onto the end.
879 */
880 ring_header->size = size =
881 sizeof(struct atl1c_tpd_desc) * tpd_ring->count * 2 +
882 sizeof(struct atl1c_rx_free_desc) * rx_desc_count +
883 sizeof(struct atl1c_recv_ret_status) * rx_desc_count +
884 sizeof(struct atl1c_hw_stats) +
885 8 * 4 + 8 * 2 * num_rx_queues;
886
887 ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
888 &ring_header->dma);
889 if (unlikely(!ring_header->desc)) {
890 dev_err(&pdev->dev, "pci_alloc_consistend failed\n");
891 goto err_nomem;
892 }
893 memset(ring_header->desc, 0, ring_header->size);
894 /* init TPD ring */
895
896 tpd_ring[0].dma = roundup(ring_header->dma, 8);
897 offset = tpd_ring[0].dma - ring_header->dma;
898 for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
899 tpd_ring[i].dma = ring_header->dma + offset;
900 tpd_ring[i].desc = (u8 *) ring_header->desc + offset;
901 tpd_ring[i].size =
902 sizeof(struct atl1c_tpd_desc) * tpd_ring[i].count;
903 offset += roundup(tpd_ring[i].size, 8);
904 }
905 /* init RFD ring */
906 for (i = 0; i < num_rx_queues; i++) {
907 rfd_ring[i].dma = ring_header->dma + offset;
908 rfd_ring[i].desc = (u8 *) ring_header->desc + offset;
909 rfd_ring[i].size = sizeof(struct atl1c_rx_free_desc) *
910 rfd_ring[i].count;
911 offset += roundup(rfd_ring[i].size, 8);
912 }
913
914 /* init RRD ring */
915 for (i = 0; i < num_rx_queues; i++) {
916 rrd_ring[i].dma = ring_header->dma + offset;
917 rrd_ring[i].desc = (u8 *) ring_header->desc + offset;
918 rrd_ring[i].size = sizeof(struct atl1c_recv_ret_status) *
919 rrd_ring[i].count;
920 offset += roundup(rrd_ring[i].size, 8);
921 }
922
923 adapter->smb.dma = ring_header->dma + offset;
924 adapter->smb.smb = (u8 *)ring_header->desc + offset;
925 return 0;
926
927err_nomem:
928 kfree(tpd_ring->buffer_info);
929 return -ENOMEM;
930}
931
932static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
933{
934 struct atl1c_hw *hw = &adapter->hw;
935 struct atl1c_rfd_ring *rfd_ring = (struct atl1c_rfd_ring *)
936 adapter->rfd_ring;
937 struct atl1c_rrd_ring *rrd_ring = (struct atl1c_rrd_ring *)
938 adapter->rrd_ring;
939 struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
940 adapter->tpd_ring;
941 struct atl1c_cmb *cmb = (struct atl1c_cmb *) &adapter->cmb;
942 struct atl1c_smb *smb = (struct atl1c_smb *) &adapter->smb;
943 int i;
944
945 /* TPD */
946 AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI,
947 (u32)((tpd_ring[atl1c_trans_normal].dma &
948 AT_DMA_HI_ADDR_MASK) >> 32));
949 /* just enable normal priority TX queue */
950 AT_WRITE_REG(hw, REG_NTPD_HEAD_ADDR_LO,
951 (u32)(tpd_ring[atl1c_trans_normal].dma &
952 AT_DMA_LO_ADDR_MASK));
953 AT_WRITE_REG(hw, REG_HTPD_HEAD_ADDR_LO,
954 (u32)(tpd_ring[atl1c_trans_high].dma &
955 AT_DMA_LO_ADDR_MASK));
956 AT_WRITE_REG(hw, REG_TPD_RING_SIZE,
957 (u32)(tpd_ring[0].count & TPD_RING_SIZE_MASK));
958
959
960 /* RFD */
961 AT_WRITE_REG(hw, REG_RX_BASE_ADDR_HI,
962 (u32)((rfd_ring[0].dma & AT_DMA_HI_ADDR_MASK) >> 32));
963 for (i = 0; i < adapter->num_rx_queues; i++)
964 AT_WRITE_REG(hw, atl1c_rfd_addr_lo_regs[i],
965 (u32)(rfd_ring[i].dma & AT_DMA_LO_ADDR_MASK));
966
967 AT_WRITE_REG(hw, REG_RFD_RING_SIZE,
968 rfd_ring[0].count & RFD_RING_SIZE_MASK);
969 AT_WRITE_REG(hw, REG_RX_BUF_SIZE,
970 adapter->rx_buffer_len & RX_BUF_SIZE_MASK);
971
972 /* RRD */
973 for (i = 0; i < adapter->num_rx_queues; i++)
974 AT_WRITE_REG(hw, atl1c_rrd_addr_lo_regs[i],
975 (u32)(rrd_ring[i].dma & AT_DMA_LO_ADDR_MASK));
976 AT_WRITE_REG(hw, REG_RRD_RING_SIZE,
977 (rrd_ring[0].count & RRD_RING_SIZE_MASK));
978
979 /* CMB */
980 AT_WRITE_REG(hw, REG_CMB_BASE_ADDR_LO, cmb->dma & AT_DMA_LO_ADDR_MASK);
981
982 /* SMB */
983 AT_WRITE_REG(hw, REG_SMB_BASE_ADDR_HI,
984 (u32)((smb->dma & AT_DMA_HI_ADDR_MASK) >> 32));
985 AT_WRITE_REG(hw, REG_SMB_BASE_ADDR_LO,
986 (u32)(smb->dma & AT_DMA_LO_ADDR_MASK));
987 /* Load all of base address above */
988 AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
989}
990
991static void atl1c_configure_tx(struct atl1c_adapter *adapter)
992{
993 struct atl1c_hw *hw = &adapter->hw;
994 u32 dev_ctrl_data;
995 u32 max_pay_load;
996 u16 tx_offload_thresh;
997 u32 txq_ctrl_data;
998 u32 extra_size = 0; /* Jumbo frame threshold in QWORD unit */
999
1000 extra_size = ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN;
1001 tx_offload_thresh = MAX_TX_OFFLOAD_THRESH;
1002 AT_WRITE_REG(hw, REG_TX_TSO_OFFLOAD_THRESH,
1003 (tx_offload_thresh >> 3) & TX_TSO_OFFLOAD_THRESH_MASK);
1004 AT_READ_REG(hw, REG_DEVICE_CTRL, &dev_ctrl_data);
1005 max_pay_load = (dev_ctrl_data >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT) &
1006 DEVICE_CTRL_MAX_PAYLOAD_MASK;
1007 hw->dmaw_block = min(max_pay_load, hw->dmaw_block);
1008 max_pay_load = (dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT) &
1009 DEVICE_CTRL_MAX_RREQ_SZ_MASK;
1010 hw->dmar_block = min(max_pay_load, hw->dmar_block);
1011
1012 txq_ctrl_data = (hw->tpd_burst & TXQ_NUM_TPD_BURST_MASK) <<
1013 TXQ_NUM_TPD_BURST_SHIFT;
1014 if (hw->ctrl_flags & ATL1C_TXQ_MODE_ENHANCE)
1015 txq_ctrl_data |= TXQ_CTRL_ENH_MODE;
1016 txq_ctrl_data |= (atl1c_pay_load_size[hw->dmar_block] &
1017 TXQ_TXF_BURST_NUM_MASK) << TXQ_TXF_BURST_NUM_SHIFT;
1018
1019 AT_WRITE_REG(hw, REG_TXQ_CTRL, txq_ctrl_data);
1020}
1021
1022static void atl1c_configure_rx(struct atl1c_adapter *adapter)
1023{
1024 struct atl1c_hw *hw = &adapter->hw;
1025 u32 rxq_ctrl_data;
1026
1027 rxq_ctrl_data = (hw->rfd_burst & RXQ_RFD_BURST_NUM_MASK) <<
1028 RXQ_RFD_BURST_NUM_SHIFT;
1029
1030 if (hw->ctrl_flags & ATL1C_RX_IPV6_CHKSUM)
1031 rxq_ctrl_data |= IPV6_CHKSUM_CTRL_EN;
1032 if (hw->rss_type == atl1c_rss_ipv4)
1033 rxq_ctrl_data |= RSS_HASH_IPV4;
1034 if (hw->rss_type == atl1c_rss_ipv4_tcp)
1035 rxq_ctrl_data |= RSS_HASH_IPV4_TCP;
1036 if (hw->rss_type == atl1c_rss_ipv6)
1037 rxq_ctrl_data |= RSS_HASH_IPV6;
1038 if (hw->rss_type == atl1c_rss_ipv6_tcp)
1039 rxq_ctrl_data |= RSS_HASH_IPV6_TCP;
1040 if (hw->rss_type != atl1c_rss_disable)
1041 rxq_ctrl_data |= RRS_HASH_CTRL_EN;
1042
1043 rxq_ctrl_data |= (hw->rss_mode & RSS_MODE_MASK) <<
1044 RSS_MODE_SHIFT;
1045 rxq_ctrl_data |= (hw->rss_hash_bits & RSS_HASH_BITS_MASK) <<
1046 RSS_HASH_BITS_SHIFT;
1047 if (hw->ctrl_flags & ATL1C_ASPM_CTRL_MON)
1048 rxq_ctrl_data |= (ASPM_THRUPUT_LIMIT_100M &
1049 ASPM_THRUPUT_LIMIT_MASK) << ASPM_THRUPUT_LIMIT_SHIFT;
1050
1051 AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
1052}
1053
1054static void atl1c_configure_rss(struct atl1c_adapter *adapter)
1055{
1056 struct atl1c_hw *hw = &adapter->hw;
1057
1058 AT_WRITE_REG(hw, REG_IDT_TABLE, hw->indirect_tab);
1059 AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, hw->base_cpu);
1060}
1061
1062static void atl1c_configure_dma(struct atl1c_adapter *adapter)
1063{
1064 struct atl1c_hw *hw = &adapter->hw;
1065 u32 dma_ctrl_data;
1066
1067 dma_ctrl_data = DMA_CTRL_DMAR_REQ_PRI;
1068 if (hw->ctrl_flags & ATL1C_CMB_ENABLE)
1069 dma_ctrl_data |= DMA_CTRL_CMB_EN;
1070 if (hw->ctrl_flags & ATL1C_SMB_ENABLE)
1071 dma_ctrl_data |= DMA_CTRL_SMB_EN;
1072 else
1073 dma_ctrl_data |= MAC_CTRL_SMB_DIS;
1074
1075 switch (hw->dma_order) {
1076 case atl1c_dma_ord_in:
1077 dma_ctrl_data |= DMA_CTRL_DMAR_IN_ORDER;
1078 break;
1079 case atl1c_dma_ord_enh:
1080 dma_ctrl_data |= DMA_CTRL_DMAR_ENH_ORDER;
1081 break;
1082 case atl1c_dma_ord_out:
1083 dma_ctrl_data |= DMA_CTRL_DMAR_OUT_ORDER;
1084 break;
1085 default:
1086 break;
1087 }
1088
1089 dma_ctrl_data |= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1090 << DMA_CTRL_DMAR_BURST_LEN_SHIFT;
1091 dma_ctrl_data |= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1092 << DMA_CTRL_DMAW_BURST_LEN_SHIFT;
1093 dma_ctrl_data |= (((u32)hw->dmar_dly_cnt) & DMA_CTRL_DMAR_DLY_CNT_MASK)
1094 << DMA_CTRL_DMAR_DLY_CNT_SHIFT;
1095 dma_ctrl_data |= (((u32)hw->dmaw_dly_cnt) & DMA_CTRL_DMAW_DLY_CNT_MASK)
1096 << DMA_CTRL_DMAW_DLY_CNT_SHIFT;
1097
1098 AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
1099}
1100
1101/*
1102 * Stop the mac, transmit and receive units
1103 * hw - Struct containing variables accessed by shared code
1104 * return : 0 or idle status (if error)
1105 */
1106static int atl1c_stop_mac(struct atl1c_hw *hw)
1107{
1108 u32 data;
1109 int timeout;
1110
1111 AT_READ_REG(hw, REG_RXQ_CTRL, &data);
1112 data &= ~(RXQ1_CTRL_EN | RXQ2_CTRL_EN |
1113 RXQ3_CTRL_EN | RXQ_CTRL_EN);
1114 AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
1115
1116 AT_READ_REG(hw, REG_TXQ_CTRL, &data);
1117 data &= ~TXQ_CTRL_EN;
1118 AT_WRITE_REG(hw, REG_TWSI_CTRL, data);
1119
1120 for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
1121 AT_READ_REG(hw, REG_IDLE_STATUS, &data);
1122 if ((data & (IDLE_STATUS_RXQ_NO_IDLE |
1123 IDLE_STATUS_TXQ_NO_IDLE)) == 0)
1124 break;
1125 msleep(1);
1126 }
1127
1128 AT_READ_REG(hw, REG_MAC_CTRL, &data);
1129 data &= ~(MAC_CTRL_TX_EN | MAC_CTRL_RX_EN);
1130 AT_WRITE_REG(hw, REG_MAC_CTRL, data);
1131
1132 for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
1133 AT_READ_REG(hw, REG_IDLE_STATUS, &data);
1134 if ((data & IDLE_STATUS_MASK) == 0)
1135 return 0;
1136 msleep(1);
1137 }
1138 return data;
1139}
1140
1141static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw)
1142{
1143 u32 data;
1144
1145 AT_READ_REG(hw, REG_RXQ_CTRL, &data);
1146 switch (hw->adapter->num_rx_queues) {
1147 case 4:
1148 data |= (RXQ3_CTRL_EN | RXQ2_CTRL_EN | RXQ1_CTRL_EN);
1149 break;
1150 case 3:
1151 data |= (RXQ2_CTRL_EN | RXQ1_CTRL_EN);
1152 break;
1153 case 2:
1154 data |= RXQ1_CTRL_EN;
1155 break;
1156 default:
1157 break;
1158 }
1159 data |= RXQ_CTRL_EN;
1160 AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
1161}
1162
1163static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw)
1164{
1165 u32 data;
1166
1167 AT_READ_REG(hw, REG_TXQ_CTRL, &data);
1168 data |= TXQ_CTRL_EN;
1169 AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
1170}
1171
1172/*
1173 * Reset the transmit and receive units; mask and clear all interrupts.
1174 * hw - Struct containing variables accessed by shared code
1175 * return : 0 or idle status (if error)
1176 */
1177static int atl1c_reset_mac(struct atl1c_hw *hw)
1178{
1179 struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
1180 struct pci_dev *pdev = adapter->pdev;
1181 u32 idle_status_data = 0;
1182 int timeout = 0;
1183 int ret;
1184
1185 AT_WRITE_REG(hw, REG_IMR, 0);
1186 AT_WRITE_REG(hw, REG_ISR, ISR_DIS_INT);
1187
1188 ret = atl1c_stop_mac(hw);
1189 if (ret)
1190 return ret;
1191 /*
1192 * Issue Soft Reset to the MAC. This will reset the chip's
1193 * transmit, receive, DMA. It will not effect
1194 * the current PCI configuration. The global reset bit is self-
1195 * clearing, and should clear within a microsecond.
1196 */
1197 AT_WRITE_REGW(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
1198 AT_WRITE_FLUSH(hw);
1199 msleep(10);
1200 /* Wait at least 10ms for All module to be Idle */
1201 for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
1202 AT_READ_REG(hw, REG_IDLE_STATUS, &idle_status_data);
1203 if ((idle_status_data & IDLE_STATUS_MASK) == 0)
1204 break;
1205 msleep(1);
1206 }
1207 if (timeout >= AT_HW_MAX_IDLE_DELAY) {
1208 dev_err(&pdev->dev,
1209 "MAC state machine cann't be idle since"
1210 " disabled for 10ms second\n");
1211 return -1;
1212 }
1213 return 0;
1214}
1215
1216static void atl1c_disable_l0s_l1(struct atl1c_hw *hw)
1217{
1218 u32 pm_ctrl_data;
1219
1220 AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
1221 pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
1222 PM_CTRL_L1_ENTRY_TIMER_SHIFT);
1223 pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1;
1224 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1225 pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
1226 pm_ctrl_data &= ~PM_CTRL_MAC_ASPM_CHK;
1227 pm_ctrl_data &= ~PM_CTRL_SERDES_PD_EX_L1;
1228
1229 pm_ctrl_data |= PM_CTRL_SERDES_BUDS_RX_L1_EN;
1230 pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN;
1231 pm_ctrl_data |= PM_CTRL_SERDES_L1_EN;
1232 AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
1233}
1234
1235/*
1236 * Set ASPM state.
1237 * Enable/disable L0s/L1 depend on link state.
1238 */
1239static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup)
1240{
1241 u32 pm_ctrl_data;
1242
1243 AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
1244
1245 pm_ctrl_data &= PM_CTRL_SERDES_PD_EX_L1;
1246 pm_ctrl_data |= ~PM_CTRL_SERDES_BUDS_RX_L1_EN;
1247 pm_ctrl_data |= ~PM_CTRL_SERDES_L1_EN;
1248 pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
1249 PM_CTRL_L1_ENTRY_TIMER_SHIFT);
1250
1251 pm_ctrl_data |= PM_CTRL_MAC_ASPM_CHK;
1252
1253 if (linkup) {
1254 pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN;
1255 pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1;
1256
1257 if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT) {
1258 pm_ctrl_data |= AT_ASPM_L1_TIMER <<
1259 PM_CTRL_L1_ENTRY_TIMER_SHIFT;
1260 pm_ctrl_data |= PM_CTRL_ASPM_L1_EN;
1261 } else
1262 pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
1263
1264 if (hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT)
1265 pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN;
1266 else
1267 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1268
1269 } else {
1270 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1271 pm_ctrl_data &= ~PM_CTRL_SERDES_PLL_L1_EN;
1272
1273 pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
1274
1275 if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
1276 pm_ctrl_data |= PM_CTRL_ASPM_L1_EN;
1277 else
1278 pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
1279 }
1280
1281 AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
1282}
1283
1284static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter)
1285{
1286 struct atl1c_hw *hw = &adapter->hw;
1287 struct net_device *netdev = adapter->netdev;
1288 u32 mac_ctrl_data;
1289
1290 mac_ctrl_data = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
1291 mac_ctrl_data |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1292
1293 if (adapter->link_duplex == FULL_DUPLEX) {
1294 hw->mac_duplex = true;
1295 mac_ctrl_data |= MAC_CTRL_DUPLX;
1296 }
1297
1298 if (adapter->link_speed == SPEED_1000)
1299 hw->mac_speed = atl1c_mac_speed_1000;
1300 else
1301 hw->mac_speed = atl1c_mac_speed_10_100;
1302
1303 mac_ctrl_data |= (hw->mac_speed & MAC_CTRL_SPEED_MASK) <<
1304 MAC_CTRL_SPEED_SHIFT;
1305
1306 mac_ctrl_data |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1307 mac_ctrl_data |= ((hw->preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1308 MAC_CTRL_PRMLEN_SHIFT);
1309
1310 if (adapter->vlgrp)
1311 mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
1312
1313 mac_ctrl_data |= MAC_CTRL_BC_EN;
1314 if (netdev->flags & IFF_PROMISC)
1315 mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
1316 if (netdev->flags & IFF_ALLMULTI)
1317 mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
1318
1319 mac_ctrl_data |= MAC_CTRL_SINGLE_PAUSE_EN;
1320 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
1321}
1322
1323/*
1324 * atl1c_configure - Configure Transmit&Receive Unit after Reset
1325 * @adapter: board private structure
1326 *
1327 * Configure the Tx /Rx unit of the MAC after a reset.
1328 */
1329static int atl1c_configure(struct atl1c_adapter *adapter)
1330{
1331 struct atl1c_hw *hw = &adapter->hw;
1332 u32 master_ctrl_data = 0;
1333 u32 intr_modrt_data;
1334
1335 /* clear interrupt status */
1336 AT_WRITE_REG(hw, REG_ISR, 0xFFFFFFFF);
1337 /* Clear any WOL status */
1338 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
1339 /* set Interrupt Clear Timer
1340 * HW will enable self to assert interrupt event to system after
1341 * waiting x-time for software to notify it accept interrupt.
1342 */
1343 AT_WRITE_REG(hw, REG_INT_RETRIG_TIMER,
1344 hw->ict & INT_RETRIG_TIMER_MASK);
1345
1346 atl1c_configure_des_ring(adapter);
1347
1348 if (hw->ctrl_flags & ATL1C_INTR_MODRT_ENABLE) {
1349 intr_modrt_data = (hw->tx_imt & IRQ_MODRT_TIMER_MASK) <<
1350 IRQ_MODRT_TX_TIMER_SHIFT;
1351 intr_modrt_data |= (hw->rx_imt & IRQ_MODRT_TIMER_MASK) <<
1352 IRQ_MODRT_RX_TIMER_SHIFT;
1353 AT_WRITE_REG(hw, REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data);
1354 master_ctrl_data |=
1355 MASTER_CTRL_TX_ITIMER_EN | MASTER_CTRL_RX_ITIMER_EN;
1356 }
1357
1358 if (hw->ctrl_flags & ATL1C_INTR_CLEAR_ON_READ)
1359 master_ctrl_data |= MASTER_CTRL_INT_RDCLR;
1360
1361 AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
1362
1363 if (hw->ctrl_flags & ATL1C_CMB_ENABLE) {
1364 AT_WRITE_REG(hw, REG_CMB_TPD_THRESH,
1365 hw->cmb_tpd & CMB_TPD_THRESH_MASK);
1366 AT_WRITE_REG(hw, REG_CMB_TX_TIMER,
1367 hw->cmb_tx_timer & CMB_TX_TIMER_MASK);
1368 }
1369
1370 if (hw->ctrl_flags & ATL1C_SMB_ENABLE)
1371 AT_WRITE_REG(hw, REG_SMB_STAT_TIMER,
1372 hw->smb_timer & SMB_STAT_TIMER_MASK);
1373 /* set MTU */
1374 AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
1375 VLAN_HLEN + ETH_FCS_LEN);
1376 /* HDS, disable */
1377 AT_WRITE_REG(hw, REG_HDS_CTRL, 0);
1378
1379 atl1c_configure_tx(adapter);
1380 atl1c_configure_rx(adapter);
1381 atl1c_configure_rss(adapter);
1382 atl1c_configure_dma(adapter);
1383
1384 return 0;
1385}
1386
1387static void atl1c_update_hw_stats(struct atl1c_adapter *adapter)
1388{
1389 u16 hw_reg_addr = 0;
1390 unsigned long *stats_item = NULL;
1391 u32 data;
1392
1393 /* update rx status */
1394 hw_reg_addr = REG_MAC_RX_STATUS_BIN;
1395 stats_item = &adapter->hw_stats.rx_ok;
1396 while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
1397 AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
1398 *stats_item += data;
1399 stats_item++;
1400 hw_reg_addr += 4;
1401 }
1402/* update tx status */
1403 hw_reg_addr = REG_MAC_TX_STATUS_BIN;
1404 stats_item = &adapter->hw_stats.tx_ok;
1405 while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
1406 AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
1407 *stats_item += data;
1408 stats_item++;
1409 hw_reg_addr += 4;
1410 }
1411}
1412
1413/*
1414 * atl1c_get_stats - Get System Network Statistics
1415 * @netdev: network interface device structure
1416 *
1417 * Returns the address of the device statistics structure.
1418 * The statistics are actually updated from the timer callback.
1419 */
1420static struct net_device_stats *atl1c_get_stats(struct net_device *netdev)
1421{
1422 struct atl1c_adapter *adapter = netdev_priv(netdev);
1423 struct atl1c_hw_stats *hw_stats = &adapter->hw_stats;
1424 struct net_device_stats *net_stats = &adapter->net_stats;
1425
1426 atl1c_update_hw_stats(adapter);
1427 net_stats->rx_packets = hw_stats->rx_ok;
1428 net_stats->tx_packets = hw_stats->tx_ok;
1429 net_stats->rx_bytes = hw_stats->rx_byte_cnt;
1430 net_stats->tx_bytes = hw_stats->tx_byte_cnt;
1431 net_stats->multicast = hw_stats->rx_mcast;
1432 net_stats->collisions = hw_stats->tx_1_col +
1433 hw_stats->tx_2_col * 2 +
1434 hw_stats->tx_late_col + hw_stats->tx_abort_col;
1435 net_stats->rx_errors = hw_stats->rx_frag + hw_stats->rx_fcs_err +
1436 hw_stats->rx_len_err + hw_stats->rx_sz_ov +
1437 hw_stats->rx_rrd_ov + hw_stats->rx_align_err;
1438 net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
1439 net_stats->rx_length_errors = hw_stats->rx_len_err;
1440 net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
1441 net_stats->rx_frame_errors = hw_stats->rx_align_err;
1442 net_stats->rx_over_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1443
1444 net_stats->rx_missed_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1445
1446 net_stats->tx_errors = hw_stats->tx_late_col + hw_stats->tx_abort_col +
1447 hw_stats->tx_underrun + hw_stats->tx_trunc;
1448 net_stats->tx_fifo_errors = hw_stats->tx_underrun;
1449 net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
1450 net_stats->tx_window_errors = hw_stats->tx_late_col;
1451
1452 return &adapter->net_stats;
1453}
1454
1455static inline void atl1c_clear_phy_int(struct atl1c_adapter *adapter)
1456{
1457 u16 phy_data;
1458
1459 spin_lock(&adapter->mdio_lock);
1460 atl1c_read_phy_reg(&adapter->hw, MII_ISR, &phy_data);
1461 spin_unlock(&adapter->mdio_lock);
1462}
1463
1464static bool atl1c_clean_tx_irq(struct atl1c_adapter *adapter,
1465 enum atl1c_trans_queue type)
1466{
1467 struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
1468 &adapter->tpd_ring[type];
1469 struct atl1c_buffer *buffer_info;
1470 u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
1471 u16 hw_next_to_clean;
1472 u16 shift;
1473 u32 data;
1474
1475 if (type == atl1c_trans_high)
1476 shift = MB_HTPD_CONS_IDX_SHIFT;
1477 else
1478 shift = MB_NTPD_CONS_IDX_SHIFT;
1479
1480 AT_READ_REG(&adapter->hw, REG_MB_PRIO_CONS_IDX, &data);
1481 hw_next_to_clean = (data >> shift) & MB_PRIO_PROD_IDX_MASK;
1482
1483 while (next_to_clean != hw_next_to_clean) {
1484 buffer_info = &tpd_ring->buffer_info[next_to_clean];
1485 if (buffer_info->state == ATL1_BUFFER_BUSY) {
1486 pci_unmap_page(adapter->pdev, buffer_info->dma,
1487 buffer_info->length, PCI_DMA_TODEVICE);
1488 buffer_info->dma = 0;
1489 if (buffer_info->skb) {
1490 dev_kfree_skb_irq(buffer_info->skb);
1491 buffer_info->skb = NULL;
1492 }
1493 buffer_info->state = ATL1_BUFFER_FREE;
1494 }
1495 if (++next_to_clean == tpd_ring->count)
1496 next_to_clean = 0;
1497 atomic_set(&tpd_ring->next_to_clean, next_to_clean);
1498 }
1499
1500 if (netif_queue_stopped(adapter->netdev) &&
1501 netif_carrier_ok(adapter->netdev)) {
1502 netif_wake_queue(adapter->netdev);
1503 }
1504
1505 return true;
1506}
1507
1508/*
1509 * atl1c_intr - Interrupt Handler
1510 * @irq: interrupt number
1511 * @data: pointer to a network interface device structure
1512 * @pt_regs: CPU registers structure
1513 */
1514static irqreturn_t atl1c_intr(int irq, void *data)
1515{
1516 struct net_device *netdev = data;
1517 struct atl1c_adapter *adapter = netdev_priv(netdev);
1518 struct pci_dev *pdev = adapter->pdev;
1519 struct atl1c_hw *hw = &adapter->hw;
1520 int max_ints = AT_MAX_INT_WORK;
1521 int handled = IRQ_NONE;
1522 u32 status;
1523 u32 reg_data;
1524
1525 do {
1526 AT_READ_REG(hw, REG_ISR, &reg_data);
1527 status = reg_data & hw->intr_mask;
1528
1529 if (status == 0 || (status & ISR_DIS_INT) != 0) {
1530 if (max_ints != AT_MAX_INT_WORK)
1531 handled = IRQ_HANDLED;
1532 break;
1533 }
1534 /* link event */
1535 if (status & ISR_GPHY)
1536 atl1c_clear_phy_int(adapter);
1537 /* Ack ISR */
1538 AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
1539 if (status & ISR_RX_PKT) {
1540 if (likely(napi_schedule_prep(&adapter->napi))) {
1541 hw->intr_mask &= ~ISR_RX_PKT;
1542 AT_WRITE_REG(hw, REG_IMR, hw->intr_mask);
1543 __napi_schedule(&adapter->napi);
1544 }
1545 }
1546 if (status & ISR_TX_PKT)
1547 atl1c_clean_tx_irq(adapter, atl1c_trans_normal);
1548
1549 handled = IRQ_HANDLED;
1550 /* check if PCIE PHY Link down */
1551 if (status & ISR_ERROR) {
1552 if (netif_msg_hw(adapter))
1553 dev_err(&pdev->dev,
1554 "atl1c hardware error (status = 0x%x)\n",
1555 status & ISR_ERROR);
1556 /* reset MAC */
1557 hw->intr_mask &= ~ISR_ERROR;
1558 AT_WRITE_REG(hw, REG_IMR, hw->intr_mask);
1559 schedule_work(&adapter->reset_task);
1560 break;
1561 }
1562
1563 if (status & ISR_OVER)
1564 if (netif_msg_intr(adapter))
1565 dev_warn(&pdev->dev,
1566 "TX/RX over flow (status = 0x%x)\n",
1567 status & ISR_OVER);
1568
1569 /* link event */
1570 if (status & (ISR_GPHY | ISR_MANUAL)) {
1571 adapter->net_stats.tx_carrier_errors++;
1572 atl1c_link_chg_event(adapter);
1573 break;
1574 }
1575
1576 } while (--max_ints > 0);
1577 /* re-enable Interrupt*/
1578 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
1579 return handled;
1580}
1581
1582static inline void atl1c_rx_checksum(struct atl1c_adapter *adapter,
1583 struct sk_buff *skb, struct atl1c_recv_ret_status *prrs)
1584{
1585 /*
1586 * The pid field in RRS in not correct sometimes, so we
1587 * cannot figure out if the packet is fragmented or not,
1588 * so we tell the KERNEL CHECKSUM_NONE
1589 */
1590 skb->ip_summed = CHECKSUM_NONE;
1591}
1592
1593static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter, const int ringid)
1594{
1595 struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring[ringid];
1596 struct pci_dev *pdev = adapter->pdev;
1597 struct atl1c_buffer *buffer_info, *next_info;
1598 struct sk_buff *skb;
1599 void *vir_addr = NULL;
1600 u16 num_alloc = 0;
1601 u16 rfd_next_to_use, next_next;
1602 struct atl1c_rx_free_desc *rfd_desc;
1603
1604 next_next = rfd_next_to_use = rfd_ring->next_to_use;
1605 if (++next_next == rfd_ring->count)
1606 next_next = 0;
1607 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1608 next_info = &rfd_ring->buffer_info[next_next];
1609
1610 while (next_info->state == ATL1_BUFFER_FREE) {
1611 rfd_desc = ATL1C_RFD_DESC(rfd_ring, rfd_next_to_use);
1612
1613 skb = dev_alloc_skb(adapter->rx_buffer_len);
1614 if (unlikely(!skb)) {
1615 if (netif_msg_rx_err(adapter))
1616 dev_warn(&pdev->dev, "alloc rx buffer failed\n");
1617 break;
1618 }
1619
1620 /*
1621 * Make buffer alignment 2 beyond a 16 byte boundary
1622 * this will result in a 16 byte aligned IP header after
1623 * the 14 byte MAC header is removed
1624 */
1625 vir_addr = skb->data;
1626 buffer_info->state = ATL1_BUFFER_BUSY;
1627 buffer_info->skb = skb;
1628 buffer_info->length = adapter->rx_buffer_len;
1629 buffer_info->dma = pci_map_single(pdev, vir_addr,
1630 buffer_info->length,
1631 PCI_DMA_FROMDEVICE);
1632 rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
1633 rfd_next_to_use = next_next;
1634 if (++next_next == rfd_ring->count)
1635 next_next = 0;
1636 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1637 next_info = &rfd_ring->buffer_info[next_next];
1638 num_alloc++;
1639 }
1640
1641 if (num_alloc) {
1642 /* TODO: update mailbox here */
1643 wmb();
1644 rfd_ring->next_to_use = rfd_next_to_use;
1645 AT_WRITE_REG(&adapter->hw, atl1c_rfd_prod_idx_regs[ringid],
1646 rfd_ring->next_to_use & MB_RFDX_PROD_IDX_MASK);
1647 }
1648
1649 return num_alloc;
1650}
1651
1652static void atl1c_clean_rrd(struct atl1c_rrd_ring *rrd_ring,
1653 struct atl1c_recv_ret_status *rrs, u16 num)
1654{
1655 u16 i;
1656 /* the relationship between rrd and rfd is one map one */
1657 for (i = 0; i < num; i++, rrs = ATL1C_RRD_DESC(rrd_ring,
1658 rrd_ring->next_to_clean)) {
1659 rrs->word3 &= ~RRS_RXD_UPDATED;
1660 if (++rrd_ring->next_to_clean == rrd_ring->count)
1661 rrd_ring->next_to_clean = 0;
1662 }
1663}
1664
1665static void atl1c_clean_rfd(struct atl1c_rfd_ring *rfd_ring,
1666 struct atl1c_recv_ret_status *rrs, u16 num)
1667{
1668 u16 i;
1669 u16 rfd_index;
1670 struct atl1c_buffer *buffer_info = rfd_ring->buffer_info;
1671
1672 rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
1673 RRS_RX_RFD_INDEX_MASK;
1674 for (i = 0; i < num; i++) {
1675 buffer_info[rfd_index].skb = NULL;
1676 buffer_info[rfd_index].state = ATL1_BUFFER_FREE;
1677 if (++rfd_index == rfd_ring->count)
1678 rfd_index = 0;
1679 }
1680 rfd_ring->next_to_clean = rfd_index;
1681}
1682
1683static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter, u8 que,
1684 int *work_done, int work_to_do)
1685{
1686 u16 rfd_num, rfd_index;
1687 u16 count = 0;
1688 u16 length;
1689 struct pci_dev *pdev = adapter->pdev;
1690 struct net_device *netdev = adapter->netdev;
1691 struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring[que];
1692 struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring[que];
1693 struct sk_buff *skb;
1694 struct atl1c_recv_ret_status *rrs;
1695 struct atl1c_buffer *buffer_info;
1696
1697 while (1) {
1698 if (*work_done >= work_to_do)
1699 break;
1700 rrs = ATL1C_RRD_DESC(rrd_ring, rrd_ring->next_to_clean);
1701 if (likely(RRS_RXD_IS_VALID(rrs->word3))) {
1702 rfd_num = (rrs->word0 >> RRS_RX_RFD_CNT_SHIFT) &
1703 RRS_RX_RFD_CNT_MASK;
1704 if (unlikely(rfd_num) != 1)
1705 /* TODO support mul rfd*/
1706 if (netif_msg_rx_err(adapter))
1707 dev_warn(&pdev->dev,
1708 "Multi rfd not support yet!\n");
1709 goto rrs_checked;
1710 } else {
1711 break;
1712 }
1713rrs_checked:
1714 atl1c_clean_rrd(rrd_ring, rrs, rfd_num);
1715 if (rrs->word3 & (RRS_RX_ERR_SUM | RRS_802_3_LEN_ERR)) {
1716 atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
1717 if (netif_msg_rx_err(adapter))
1718 dev_warn(&pdev->dev,
1719 "wrong packet! rrs word3 is %x\n",
1720 rrs->word3);
1721 continue;
1722 }
1723
1724 length = le16_to_cpu((rrs->word3 >> RRS_PKT_SIZE_SHIFT) &
1725 RRS_PKT_SIZE_MASK);
1726 /* Good Receive */
1727 if (likely(rfd_num == 1)) {
1728 rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
1729 RRS_RX_RFD_INDEX_MASK;
1730 buffer_info = &rfd_ring->buffer_info[rfd_index];
1731 pci_unmap_single(pdev, buffer_info->dma,
1732 buffer_info->length, PCI_DMA_FROMDEVICE);
1733 skb = buffer_info->skb;
1734 } else {
1735 /* TODO */
1736 if (netif_msg_rx_err(adapter))
1737 dev_warn(&pdev->dev,
1738 "Multi rfd not support yet!\n");
1739 break;
1740 }
1741 atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
1742 skb_put(skb, length - ETH_FCS_LEN);
1743 skb->protocol = eth_type_trans(skb, netdev);
1744 skb->dev = netdev;
1745 atl1c_rx_checksum(adapter, skb, rrs);
1746 if (unlikely(adapter->vlgrp) && rrs->word3 & RRS_VLAN_INS) {
1747 u16 vlan;
1748
1749 AT_TAG_TO_VLAN(rrs->vlan_tag, vlan);
1750 vlan = le16_to_cpu(vlan);
1751 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, vlan);
1752 } else
1753 netif_receive_skb(skb);
1754
1755 netdev->last_rx = jiffies;
1756 (*work_done)++;
1757 count++;
1758 }
1759 if (count)
1760 atl1c_alloc_rx_buffer(adapter, que);
1761}
1762
1763/*
1764 * atl1c_clean - NAPI Rx polling callback
1765 * @adapter: board private structure
1766 */
1767static int atl1c_clean(struct napi_struct *napi, int budget)
1768{
1769 struct atl1c_adapter *adapter =
1770 container_of(napi, struct atl1c_adapter, napi);
1771 int work_done = 0;
1772
1773 /* Keep link state information with original netdev */
1774 if (!netif_carrier_ok(adapter->netdev))
1775 goto quit_polling;
1776 /* just enable one RXQ */
1777 atl1c_clean_rx_irq(adapter, 0, &work_done, budget);
1778
1779 if (work_done < budget) {
1780quit_polling:
1781 napi_complete(napi);
1782 adapter->hw.intr_mask |= ISR_RX_PKT;
1783 AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
1784 }
1785 return work_done;
1786}
1787
1788#ifdef CONFIG_NET_POLL_CONTROLLER
1789
1790/*
1791 * Polling 'interrupt' - used by things like netconsole to send skbs
1792 * without having to re-enable interrupts. It's not called while
1793 * the interrupt routine is executing.
1794 */
1795static void atl1c_netpoll(struct net_device *netdev)
1796{
1797 struct atl1c_adapter *adapter = netdev_priv(netdev);
1798
1799 disable_irq(adapter->pdev->irq);
1800 atl1c_intr(adapter->pdev->irq, netdev);
1801 enable_irq(adapter->pdev->irq);
1802}
1803#endif
1804
1805static inline u16 atl1c_tpd_avail(struct atl1c_adapter *adapter, enum atl1c_trans_queue type)
1806{
1807 struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
1808 u16 next_to_use = 0;
1809 u16 next_to_clean = 0;
1810
1811 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
1812 next_to_use = tpd_ring->next_to_use;
1813
1814 return (u16)(next_to_clean > next_to_use) ?
1815 (next_to_clean - next_to_use - 1) :
1816 (tpd_ring->count + next_to_clean - next_to_use - 1);
1817}
1818
1819/*
1820 * get next usable tpd
1821 * Note: should call atl1c_tdp_avail to make sure
1822 * there is enough tpd to use
1823 */
1824static struct atl1c_tpd_desc *atl1c_get_tpd(struct atl1c_adapter *adapter,
1825 enum atl1c_trans_queue type)
1826{
1827 struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
1828 struct atl1c_tpd_desc *tpd_desc;
1829 u16 next_to_use = 0;
1830
1831 next_to_use = tpd_ring->next_to_use;
1832 if (++tpd_ring->next_to_use == tpd_ring->count)
1833 tpd_ring->next_to_use = 0;
1834 tpd_desc = ATL1C_TPD_DESC(tpd_ring, next_to_use);
1835 memset(tpd_desc, 0, sizeof(struct atl1c_tpd_desc));
1836 return tpd_desc;
1837}
1838
1839static struct atl1c_buffer *
1840atl1c_get_tx_buffer(struct atl1c_adapter *adapter, struct atl1c_tpd_desc *tpd)
1841{
1842 struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
1843
1844 return &tpd_ring->buffer_info[tpd -
1845 (struct atl1c_tpd_desc *)tpd_ring->desc];
1846}
1847
1848/* Calculate the transmit packet descript needed*/
1849static u16 atl1c_cal_tpd_req(const struct sk_buff *skb)
1850{
1851 u16 tpd_req;
1852 u16 proto_hdr_len = 0;
1853
1854 tpd_req = skb_shinfo(skb)->nr_frags + 1;
1855
1856 if (skb_is_gso(skb)) {
1857 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1858 if (proto_hdr_len < skb_headlen(skb))
1859 tpd_req++;
1860 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
1861 tpd_req++;
1862 }
1863 return tpd_req;
1864}
1865
1866static int atl1c_tso_csum(struct atl1c_adapter *adapter,
1867 struct sk_buff *skb,
1868 struct atl1c_tpd_desc **tpd,
1869 enum atl1c_trans_queue type)
1870{
1871 struct pci_dev *pdev = adapter->pdev;
1872 u8 hdr_len;
1873 u32 real_len;
1874 unsigned short offload_type;
1875 int err;
1876
1877 if (skb_is_gso(skb)) {
1878 if (skb_header_cloned(skb)) {
1879 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1880 if (unlikely(err))
1881 return -1;
1882 }
1883 offload_type = skb_shinfo(skb)->gso_type;
1884
1885 if (offload_type & SKB_GSO_TCPV4) {
1886 real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
1887 + ntohs(ip_hdr(skb)->tot_len));
1888
1889 if (real_len < skb->len)
1890 pskb_trim(skb, real_len);
1891
1892 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
1893 if (unlikely(skb->len == hdr_len)) {
1894 /* only xsum need */
1895 if (netif_msg_tx_queued(adapter))
1896 dev_warn(&pdev->dev,
1897 "IPV4 tso with zero data??\n");
1898 goto check_sum;
1899 } else {
1900 ip_hdr(skb)->check = 0;
1901 tcp_hdr(skb)->check = ~csum_tcpudp_magic(
1902 ip_hdr(skb)->saddr,
1903 ip_hdr(skb)->daddr,
1904 0, IPPROTO_TCP, 0);
1905 (*tpd)->word1 |= 1 << TPD_IPV4_PACKET_SHIFT;
1906 }
1907 }
1908
1909 if (offload_type & SKB_GSO_TCPV6) {
1910 struct atl1c_tpd_ext_desc *etpd =
1911 *(struct atl1c_tpd_ext_desc **)(tpd);
1912
1913 memset(etpd, 0, sizeof(struct atl1c_tpd_ext_desc));
1914 *tpd = atl1c_get_tpd(adapter, type);
1915 ipv6_hdr(skb)->payload_len = 0;
1916 /* check payload == 0 byte ? */
1917 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
1918 if (unlikely(skb->len == hdr_len)) {
1919 /* only xsum need */
1920 if (netif_msg_tx_queued(adapter))
1921 dev_warn(&pdev->dev,
1922 "IPV6 tso with zero data??\n");
1923 goto check_sum;
1924 } else
1925 tcp_hdr(skb)->check = ~csum_ipv6_magic(
1926 &ipv6_hdr(skb)->saddr,
1927 &ipv6_hdr(skb)->daddr,
1928 0, IPPROTO_TCP, 0);
1929 etpd->word1 |= 1 << TPD_LSO_EN_SHIFT;
1930 etpd->word1 |= 1 << TPD_LSO_VER_SHIFT;
1931 etpd->pkt_len = cpu_to_le32(skb->len);
1932 (*tpd)->word1 |= 1 << TPD_LSO_VER_SHIFT;
1933 }
1934
1935 (*tpd)->word1 |= 1 << TPD_LSO_EN_SHIFT;
1936 (*tpd)->word1 |= (skb_transport_offset(skb) & TPD_TCPHDR_OFFSET_MASK) <<
1937 TPD_TCPHDR_OFFSET_SHIFT;
1938 (*tpd)->word1 |= (skb_shinfo(skb)->gso_size & TPD_MSS_MASK) <<
1939 TPD_MSS_SHIFT;
1940 return 0;
1941 }
1942
1943check_sum:
1944 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1945 u8 css, cso;
1946 cso = skb_transport_offset(skb);
1947
1948 if (unlikely(cso & 0x1)) {
1949 if (netif_msg_tx_err(adapter))
1950 dev_err(&adapter->pdev->dev,
1951 "payload offset should not an event number\n");
1952 return -1;
1953 } else {
1954 css = cso + skb->csum_offset;
1955
1956 (*tpd)->word1 |= ((cso >> 1) & TPD_PLOADOFFSET_MASK) <<
1957 TPD_PLOADOFFSET_SHIFT;
1958 (*tpd)->word1 |= ((css >> 1) & TPD_CCSUM_OFFSET_MASK) <<
1959 TPD_CCSUM_OFFSET_SHIFT;
1960 (*tpd)->word1 |= 1 << TPD_CCSUM_EN_SHIFT;
1961 }
1962 }
1963 return 0;
1964}
1965
1966static void atl1c_tx_map(struct atl1c_adapter *adapter,
1967 struct sk_buff *skb, struct atl1c_tpd_desc *tpd,
1968 enum atl1c_trans_queue type)
1969{
1970 struct atl1c_tpd_desc *use_tpd = NULL;
1971 struct atl1c_buffer *buffer_info = NULL;
1972 u16 buf_len = skb_headlen(skb);
1973 u16 map_len = 0;
1974 u16 mapped_len = 0;
1975 u16 hdr_len = 0;
1976 u16 nr_frags;
1977 u16 f;
1978 int tso;
1979
1980 nr_frags = skb_shinfo(skb)->nr_frags;
1981 tso = (tpd->word1 >> TPD_LSO_EN_SHIFT) & TPD_LSO_EN_MASK;
1982 if (tso) {
1983 /* TSO */
1984 map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1985 use_tpd = tpd;
1986
1987 buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
1988 buffer_info->length = map_len;
1989 buffer_info->dma = pci_map_single(adapter->pdev,
1990 skb->data, hdr_len, PCI_DMA_TODEVICE);
1991 buffer_info->state = ATL1_BUFFER_BUSY;
1992 mapped_len += map_len;
1993 use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
1994 use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
1995 }
1996
1997 if (mapped_len < buf_len) {
1998 /* mapped_len == 0, means we should use the first tpd,
1999 which is given by caller */
2000 if (mapped_len == 0)
2001 use_tpd = tpd;
2002 else {
2003 use_tpd = atl1c_get_tpd(adapter, type);
2004 memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
2005 use_tpd = atl1c_get_tpd(adapter, type);
2006 memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
2007 }
2008 buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
2009 buffer_info->length = buf_len - mapped_len;
2010 buffer_info->dma =
2011 pci_map_single(adapter->pdev, skb->data + mapped_len,
2012 buffer_info->length, PCI_DMA_TODEVICE);
2013 buffer_info->state = ATL1_BUFFER_BUSY;
2014
2015 use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
2016 use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
2017 }
2018
2019 for (f = 0; f < nr_frags; f++) {
2020 struct skb_frag_struct *frag;
2021
2022 frag = &skb_shinfo(skb)->frags[f];
2023
2024 use_tpd = atl1c_get_tpd(adapter, type);
2025 memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
2026
2027 buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
2028 buffer_info->length = frag->size;
2029 buffer_info->dma =
2030 pci_map_page(adapter->pdev, frag->page,
2031 frag->page_offset,
2032 buffer_info->length,
2033 PCI_DMA_TODEVICE);
2034 buffer_info->state = ATL1_BUFFER_BUSY;
2035
2036 use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
2037 use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
2038 }
2039
2040 /* The last tpd */
2041 use_tpd->word1 |= 1 << TPD_EOP_SHIFT;
2042 /* The last buffer info contain the skb address,
2043 so it will be free after unmap */
2044 buffer_info->skb = skb;
2045}
2046
2047static void atl1c_tx_queue(struct atl1c_adapter *adapter, struct sk_buff *skb,
2048 struct atl1c_tpd_desc *tpd, enum atl1c_trans_queue type)
2049{
2050 struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
2051 u32 prod_data;
2052
2053 AT_READ_REG(&adapter->hw, REG_MB_PRIO_PROD_IDX, &prod_data);
2054 switch (type) {
2055 case atl1c_trans_high:
2056 prod_data &= 0xFFFF0000;
2057 prod_data |= tpd_ring->next_to_use & 0xFFFF;
2058 break;
2059 case atl1c_trans_normal:
2060 prod_data &= 0x0000FFFF;
2061 prod_data |= (tpd_ring->next_to_use & 0xFFFF) << 16;
2062 break;
2063 default:
2064 break;
2065 }
2066 wmb();
2067 AT_WRITE_REG(&adapter->hw, REG_MB_PRIO_PROD_IDX, prod_data);
2068}
2069
2070static int atl1c_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2071{
2072 struct atl1c_adapter *adapter = netdev_priv(netdev);
2073 unsigned long flags;
2074 u16 tpd_req = 1;
2075 struct atl1c_tpd_desc *tpd;
2076 enum atl1c_trans_queue type = atl1c_trans_normal;
2077
2078 if (test_bit(__AT_DOWN, &adapter->flags)) {
2079 dev_kfree_skb_any(skb);
2080 return NETDEV_TX_OK;
2081 }
2082
2083 tpd_req = atl1c_cal_tpd_req(skb);
2084 if (!spin_trylock_irqsave(&adapter->tx_lock, flags)) {
2085 if (netif_msg_pktdata(adapter))
2086 dev_info(&adapter->pdev->dev, "tx locked\n");
2087 return NETDEV_TX_LOCKED;
2088 }
2089 if (skb->mark == 0x01)
2090 type = atl1c_trans_high;
2091 else
2092 type = atl1c_trans_normal;
2093
2094 if (atl1c_tpd_avail(adapter, type) < tpd_req) {
2095 /* no enough descriptor, just stop queue */
2096 netif_stop_queue(netdev);
2097 spin_unlock_irqrestore(&adapter->tx_lock, flags);
2098 return NETDEV_TX_BUSY;
2099 }
2100
2101 tpd = atl1c_get_tpd(adapter, type);
2102
2103 /* do TSO and check sum */
2104 if (atl1c_tso_csum(adapter, skb, &tpd, type) != 0) {
2105 spin_unlock_irqrestore(&adapter->tx_lock, flags);
2106 dev_kfree_skb_any(skb);
2107 return NETDEV_TX_OK;
2108 }
2109
2110 if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
2111 u16 vlan = vlan_tx_tag_get(skb);
2112 __le16 tag;
2113
2114 vlan = cpu_to_le16(vlan);
2115 AT_VLAN_TO_TAG(vlan, tag);
2116 tpd->word1 |= 1 << TPD_INS_VTAG_SHIFT;
2117 tpd->vlan_tag = tag;
2118 }
2119
2120 if (skb_network_offset(skb) != ETH_HLEN)
2121 tpd->word1 |= 1 << TPD_ETH_TYPE_SHIFT; /* Ethernet frame */
2122
2123 atl1c_tx_map(adapter, skb, tpd, type);
2124 atl1c_tx_queue(adapter, skb, tpd, type);
2125
2126 netdev->trans_start = jiffies;
2127 spin_unlock_irqrestore(&adapter->tx_lock, flags);
2128 return NETDEV_TX_OK;
2129}
2130
2131static void atl1c_free_irq(struct atl1c_adapter *adapter)
2132{
2133 struct net_device *netdev = adapter->netdev;
2134
2135 free_irq(adapter->pdev->irq, netdev);
2136
2137 if (adapter->have_msi)
2138 pci_disable_msi(adapter->pdev);
2139}
2140
2141static int atl1c_request_irq(struct atl1c_adapter *adapter)
2142{
2143 struct pci_dev *pdev = adapter->pdev;
2144 struct net_device *netdev = adapter->netdev;
2145 int flags = 0;
2146 int err = 0;
2147
2148 adapter->have_msi = true;
2149 err = pci_enable_msi(adapter->pdev);
2150 if (err) {
2151 if (netif_msg_ifup(adapter))
2152 dev_err(&pdev->dev,
2153 "Unable to allocate MSI interrupt Error: %d\n",
2154 err);
2155 adapter->have_msi = false;
2156 } else
2157 netdev->irq = pdev->irq;
2158
2159 if (!adapter->have_msi)
2160 flags |= IRQF_SHARED;
2161 err = request_irq(adapter->pdev->irq, &atl1c_intr, flags,
2162 netdev->name, netdev);
2163 if (err) {
2164 if (netif_msg_ifup(adapter))
2165 dev_err(&pdev->dev,
2166 "Unable to allocate interrupt Error: %d\n",
2167 err);
2168 if (adapter->have_msi)
2169 pci_disable_msi(adapter->pdev);
2170 return err;
2171 }
2172 if (netif_msg_ifup(adapter))
2173 dev_dbg(&pdev->dev, "atl1c_request_irq OK\n");
2174 return err;
2175}
2176
2177int atl1c_up(struct atl1c_adapter *adapter)
2178{
2179 struct net_device *netdev = adapter->netdev;
2180 int num;
2181 int err;
2182 int i;
2183
2184 netif_carrier_off(netdev);
2185 atl1c_init_ring_ptrs(adapter);
2186 atl1c_set_multi(netdev);
2187 atl1c_restore_vlan(adapter);
2188
2189 for (i = 0; i < adapter->num_rx_queues; i++) {
2190 num = atl1c_alloc_rx_buffer(adapter, i);
2191 if (unlikely(num == 0)) {
2192 err = -ENOMEM;
2193 goto err_alloc_rx;
2194 }
2195 }
2196
2197 if (atl1c_configure(adapter)) {
2198 err = -EIO;
2199 goto err_up;
2200 }
2201
2202 err = atl1c_request_irq(adapter);
2203 if (unlikely(err))
2204 goto err_up;
2205
2206 clear_bit(__AT_DOWN, &adapter->flags);
2207 napi_enable(&adapter->napi);
2208 atl1c_irq_enable(adapter);
2209 atl1c_check_link_status(adapter);
2210 netif_start_queue(netdev);
2211 return err;
2212
2213err_up:
2214err_alloc_rx:
2215 atl1c_clean_rx_ring(adapter);
2216 return err;
2217}
2218
2219void atl1c_down(struct atl1c_adapter *adapter)
2220{
2221 struct net_device *netdev = adapter->netdev;
2222
2223 atl1c_del_timer(adapter);
2224 atl1c_cancel_work(adapter);
2225
2226 /* signal that we're down so the interrupt handler does not
2227 * reschedule our watchdog timer */
2228 set_bit(__AT_DOWN, &adapter->flags);
2229 netif_carrier_off(netdev);
2230 napi_disable(&adapter->napi);
2231 atl1c_irq_disable(adapter);
2232 atl1c_free_irq(adapter);
2233 AT_WRITE_REG(&adapter->hw, REG_ISR, ISR_DIS_INT);
2234 /* reset MAC to disable all RX/TX */
2235 atl1c_reset_mac(&adapter->hw);
2236 msleep(1);
2237
2238 adapter->link_speed = SPEED_0;
2239 adapter->link_duplex = -1;
2240 atl1c_clean_tx_ring(adapter, atl1c_trans_normal);
2241 atl1c_clean_tx_ring(adapter, atl1c_trans_high);
2242 atl1c_clean_rx_ring(adapter);
2243}
2244
2245/*
2246 * atl1c_open - Called when a network interface is made active
2247 * @netdev: network interface device structure
2248 *
2249 * Returns 0 on success, negative value on failure
2250 *
2251 * The open entry point is called when a network interface is made
2252 * active by the system (IFF_UP). At this point all resources needed
2253 * for transmit and receive operations are allocated, the interrupt
2254 * handler is registered with the OS, the watchdog timer is started,
2255 * and the stack is notified that the interface is ready.
2256 */
2257static int atl1c_open(struct net_device *netdev)
2258{
2259 struct atl1c_adapter *adapter = netdev_priv(netdev);
2260 int err;
2261
2262 /* disallow open during test */
2263 if (test_bit(__AT_TESTING, &adapter->flags))
2264 return -EBUSY;
2265
2266 /* allocate rx/tx dma buffer & descriptors */
2267 err = atl1c_setup_ring_resources(adapter);
2268 if (unlikely(err))
2269 return err;
2270
2271 err = atl1c_up(adapter);
2272 if (unlikely(err))
2273 goto err_up;
2274
2275 if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) {
2276 u32 phy_data;
2277
2278 AT_READ_REG(&adapter->hw, REG_MDIO_CTRL, &phy_data);
2279 phy_data |= MDIO_AP_EN;
2280 AT_WRITE_REG(&adapter->hw, REG_MDIO_CTRL, phy_data);
2281 }
2282 return 0;
2283
2284err_up:
2285 atl1c_free_irq(adapter);
2286 atl1c_free_ring_resources(adapter);
2287 atl1c_reset_mac(&adapter->hw);
2288 return err;
2289}
2290
2291/*
2292 * atl1c_close - Disables a network interface
2293 * @netdev: network interface device structure
2294 *
2295 * Returns 0, this is not allowed to fail
2296 *
2297 * The close entry point is called when an interface is de-activated
2298 * by the OS. The hardware is still under the drivers control, but
2299 * needs to be disabled. A global MAC reset is issued to stop the
2300 * hardware, and all transmit and receive resources are freed.
2301 */
2302static int atl1c_close(struct net_device *netdev)
2303{
2304 struct atl1c_adapter *adapter = netdev_priv(netdev);
2305
2306 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2307 atl1c_down(adapter);
2308 atl1c_free_ring_resources(adapter);
2309 return 0;
2310}
2311
2312static int atl1c_suspend(struct pci_dev *pdev, pm_message_t state)
2313{
2314 struct net_device *netdev = pci_get_drvdata(pdev);
2315 struct atl1c_adapter *adapter = netdev_priv(netdev);
2316 struct atl1c_hw *hw = &adapter->hw;
2317 u32 ctrl;
2318 u32 mac_ctrl_data;
2319 u32 master_ctrl_data;
2320 u32 wol_ctrl_data;
2321 u16 mii_bmsr_data;
2322 u16 save_autoneg_advertised;
2323 u16 mii_intr_status_data;
2324 u32 wufc = adapter->wol;
2325 u32 i;
2326 int retval = 0;
2327
2328 if (netif_running(netdev)) {
2329 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2330 atl1c_down(adapter);
2331 }
2332 netif_device_detach(netdev);
2333 atl1c_disable_l0s_l1(hw);
2334 retval = pci_save_state(pdev);
2335 if (retval)
2336 return retval;
2337 if (wufc) {
2338 AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
2339 master_ctrl_data &= ~MASTER_CTRL_CLK_SEL_DIS;
2340
2341 /* get link status */
2342 atl1c_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data);
2343 atl1c_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data);
2344 save_autoneg_advertised = hw->autoneg_advertised;
2345 hw->autoneg_advertised = ADVERTISED_10baseT_Half;
2346 if (atl1c_restart_autoneg(hw) != 0)
2347 if (netif_msg_link(adapter))
2348 dev_warn(&pdev->dev, "phy autoneg failed\n");
2349 hw->phy_configured = false; /* re-init PHY when resume */
2350 hw->autoneg_advertised = save_autoneg_advertised;
2351 /* turn on magic packet wol */
2352 if (wufc & AT_WUFC_MAG)
2353 wol_ctrl_data = WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
2354
2355 if (wufc & AT_WUFC_LNKC) {
2356 for (i = 0; i < AT_SUSPEND_LINK_TIMEOUT; i++) {
2357 msleep(100);
2358 atl1c_read_phy_reg(hw, MII_BMSR,
2359 (u16 *)&mii_bmsr_data);
2360 if (mii_bmsr_data & BMSR_LSTATUS)
2361 break;
2362 }
2363 if ((mii_bmsr_data & BMSR_LSTATUS) == 0)
2364 if (netif_msg_link(adapter))
2365 dev_warn(&pdev->dev,
2366 "%s: Link may change"
2367 "when suspend\n",
2368 atl1c_driver_name);
2369 wol_ctrl_data |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
2370 /* only link up can wake up */
2371 if (atl1c_write_phy_reg(hw, MII_IER, IER_LINK_UP) != 0) {
2372 if (netif_msg_link(adapter))
2373 dev_err(&pdev->dev,
2374 "%s: read write phy "
2375 "register failed.\n",
2376 atl1c_driver_name);
2377 goto wol_dis;
2378 }
2379 }
2380 /* clear phy interrupt */
2381 atl1c_read_phy_reg(hw, MII_ISR, &mii_intr_status_data);
2382 /* Config MAC Ctrl register */
2383 mac_ctrl_data = MAC_CTRL_RX_EN;
2384 /* set to 10/100M halt duplex */
2385 mac_ctrl_data |= atl1c_mac_speed_10_100 << MAC_CTRL_SPEED_SHIFT;
2386 mac_ctrl_data |= (((u32)adapter->hw.preamble_len &
2387 MAC_CTRL_PRMLEN_MASK) <<
2388 MAC_CTRL_PRMLEN_SHIFT);
2389
2390 if (adapter->vlgrp)
2391 mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
2392
2393 /* magic packet maybe Broadcast&multicast&Unicast frame */
2394 if (wufc & AT_WUFC_MAG)
2395 mac_ctrl_data |= MAC_CTRL_BC_EN;
2396
2397 if (netif_msg_hw(adapter))
2398 dev_dbg(&pdev->dev,
2399 "%s: suspend MAC=0x%x\n",
2400 atl1c_driver_name, mac_ctrl_data);
2401 AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
2402 AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
2403 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
2404
2405 /* pcie patch */
2406 AT_READ_REG(hw, REG_PCIE_PHYMISC, &ctrl);
2407 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2408 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
2409
2410 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
2411 goto suspend_exit;
2412 }
2413wol_dis:
2414
2415 /* WOL disabled */
2416 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
2417
2418 /* pcie patch */
2419 AT_READ_REG(hw, REG_PCIE_PHYMISC, &ctrl);
2420 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2421 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
2422
2423 atl1c_phy_disable(hw);
2424 hw->phy_configured = false; /* re-init PHY when resume */
2425
2426 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
2427suspend_exit:
2428
2429 pci_disable_device(pdev);
2430 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2431
2432 return 0;
2433}
2434
2435static int atl1c_resume(struct pci_dev *pdev)
2436{
2437 struct net_device *netdev = pci_get_drvdata(pdev);
2438 struct atl1c_adapter *adapter = netdev_priv(netdev);
2439
2440 pci_set_power_state(pdev, PCI_D0);
2441 pci_restore_state(pdev);
2442 pci_enable_wake(pdev, PCI_D3hot, 0);
2443 pci_enable_wake(pdev, PCI_D3cold, 0);
2444
2445 AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
2446
2447 atl1c_phy_reset(&adapter->hw);
2448 atl1c_reset_mac(&adapter->hw);
2449 netif_device_attach(netdev);
2450 if (netif_running(netdev))
2451 atl1c_up(adapter);
2452
2453 return 0;
2454}
2455
2456static void atl1c_shutdown(struct pci_dev *pdev)
2457{
2458 atl1c_suspend(pdev, PMSG_SUSPEND);
2459}
2460
2461static const struct net_device_ops atl1c_netdev_ops = {
2462 .ndo_open = atl1c_open,
2463 .ndo_stop = atl1c_close,
2464 .ndo_validate_addr = eth_validate_addr,
2465 .ndo_start_xmit = atl1c_xmit_frame,
2466 .ndo_set_mac_address = atl1c_set_mac_addr,
2467 .ndo_set_multicast_list = atl1c_set_multi,
2468 .ndo_change_mtu = atl1c_change_mtu,
2469 .ndo_do_ioctl = atl1c_ioctl,
2470 .ndo_tx_timeout = atl1c_tx_timeout,
2471 .ndo_get_stats = atl1c_get_stats,
2472 .ndo_vlan_rx_register = atl1c_vlan_rx_register,
2473#ifdef CONFIG_NET_POLL_CONTROLLER
2474 .ndo_poll_controller = atl1c_netpoll,
2475#endif
2476};
2477
2478static int atl1c_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
2479{
2480 SET_NETDEV_DEV(netdev, &pdev->dev);
2481 pci_set_drvdata(pdev, netdev);
2482
2483 netdev->irq = pdev->irq;
2484 netdev->netdev_ops = &atl1c_netdev_ops;
2485 netdev->watchdog_timeo = AT_TX_WATCHDOG;
2486 atl1c_set_ethtool_ops(netdev);
2487
2488 /* TODO: add when ready */
2489 netdev->features = NETIF_F_SG |
2490 NETIF_F_HW_CSUM |
2491 NETIF_F_HW_VLAN_TX |
2492 NETIF_F_HW_VLAN_RX |
2493 NETIF_F_TSO |
2494 NETIF_F_TSO6;
2495 return 0;
2496}
2497
2498/*
2499 * atl1c_probe - Device Initialization Routine
2500 * @pdev: PCI device information struct
2501 * @ent: entry in atl1c_pci_tbl
2502 *
2503 * Returns 0 on success, negative on failure
2504 *
2505 * atl1c_probe initializes an adapter identified by a pci_dev structure.
2506 * The OS initialization, configuring of the adapter private structure,
2507 * and a hardware reset occur.
2508 */
2509static int __devinit atl1c_probe(struct pci_dev *pdev,
2510 const struct pci_device_id *ent)
2511{
2512 struct net_device *netdev;
2513 struct atl1c_adapter *adapter;
2514 static int cards_found;
2515
2516 int err = 0;
2517
2518 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2519 err = pci_enable_device_mem(pdev);
2520 if (err) {
2521 dev_err(&pdev->dev, "cannot enable PCI device\n");
2522 return err;
2523 }
2524
2525 /*
2526 * The atl1c chip can DMA to 64-bit addresses, but it uses a single
2527 * shared register for the high 32 bits, so only a single, aligned,
2528 * 4 GB physical address range can be used at a time.
2529 *
2530 * Supporting 64-bit DMA on this hardware is more trouble than it's
2531 * worth. It is far easier to limit to 32-bit DMA than update
2532 * various kernel subsystems to support the mechanics required by a
2533 * fixed-high-32-bit system.
2534 */
2535 if ((pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) ||
2536 (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK) != 0)) {
2537 dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
2538 goto err_dma;
2539 }
2540
2541 err = pci_request_regions(pdev, atl1c_driver_name);
2542 if (err) {
2543 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
2544 goto err_pci_reg;
2545 }
2546
2547 pci_set_master(pdev);
2548
2549 netdev = alloc_etherdev(sizeof(struct atl1c_adapter));
2550 if (netdev == NULL) {
2551 err = -ENOMEM;
2552 dev_err(&pdev->dev, "etherdev alloc failed\n");
2553 goto err_alloc_etherdev;
2554 }
2555
2556 err = atl1c_init_netdev(netdev, pdev);
2557 if (err) {
2558 dev_err(&pdev->dev, "init netdevice failed\n");
2559 goto err_init_netdev;
2560 }
2561 adapter = netdev_priv(netdev);
2562 adapter->bd_number = cards_found;
2563 adapter->netdev = netdev;
2564 adapter->pdev = pdev;
2565 adapter->hw.adapter = adapter;
2566 adapter->msg_enable = netif_msg_init(-1, atl1c_default_msg);
2567 adapter->hw.hw_addr = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
2568 if (!adapter->hw.hw_addr) {
2569 err = -EIO;
2570 dev_err(&pdev->dev, "cannot map device registers\n");
2571 goto err_ioremap;
2572 }
2573 netdev->base_addr = (unsigned long)adapter->hw.hw_addr;
2574
2575 /* init mii data */
2576 adapter->mii.dev = netdev;
2577 adapter->mii.mdio_read = atl1c_mdio_read;
2578 adapter->mii.mdio_write = atl1c_mdio_write;
2579 adapter->mii.phy_id_mask = 0x1f;
2580 adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK;
2581 netif_napi_add(netdev, &adapter->napi, atl1c_clean, 64);
2582 setup_timer(&adapter->phy_config_timer, atl1c_phy_config,
2583 (unsigned long)adapter);
2584 /* setup the private structure */
2585 err = atl1c_sw_init(adapter);
2586 if (err) {
2587 dev_err(&pdev->dev, "net device private data init failed\n");
2588 goto err_sw_init;
2589 }
2590 atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE |
2591 ATL1C_PCIE_PHY_RESET);
2592
2593 /* Init GPHY as early as possible due to power saving issue */
2594 atl1c_phy_reset(&adapter->hw);
2595
2596 err = atl1c_reset_mac(&adapter->hw);
2597 if (err) {
2598 err = -EIO;
2599 goto err_reset;
2600 }
2601
2602 device_init_wakeup(&pdev->dev, 1);
2603 /* reset the controller to
2604 * put the device in a known good starting state */
2605 err = atl1c_phy_init(&adapter->hw);
2606 if (err) {
2607 err = -EIO;
2608 goto err_reset;
2609 }
2610 if (atl1c_read_mac_addr(&adapter->hw) != 0) {
2611 err = -EIO;
2612 dev_err(&pdev->dev, "get mac address failed\n");
2613 goto err_eeprom;
2614 }
2615 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
2616 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
2617 if (netif_msg_probe(adapter))
2618 dev_dbg(&pdev->dev,
2619 "mac address : %02x-%02x-%02x-%02x-%02x-%02x\n",
2620 adapter->hw.mac_addr[0], adapter->hw.mac_addr[1],
2621 adapter->hw.mac_addr[2], adapter->hw.mac_addr[3],
2622 adapter->hw.mac_addr[4], adapter->hw.mac_addr[5]);
2623
2624 atl1c_hw_set_mac_addr(&adapter->hw);
2625 INIT_WORK(&adapter->reset_task, atl1c_reset_task);
2626 INIT_WORK(&adapter->link_chg_task, atl1c_link_chg_task);
2627 err = register_netdev(netdev);
2628 if (err) {
2629 dev_err(&pdev->dev, "register netdevice failed\n");
2630 goto err_register;
2631 }
2632
2633 if (netif_msg_probe(adapter))
2634 dev_info(&pdev->dev, "version %s\n", ATL1C_DRV_VERSION);
2635 cards_found++;
2636 return 0;
2637
2638err_reset:
2639err_register:
2640err_sw_init:
2641err_eeprom:
2642 iounmap(adapter->hw.hw_addr);
2643err_init_netdev:
2644err_ioremap:
2645 free_netdev(netdev);
2646err_alloc_etherdev:
2647 pci_release_regions(pdev);
2648err_pci_reg:
2649err_dma:
2650 pci_disable_device(pdev);
2651 return err;
2652}
2653
2654/*
2655 * atl1c_remove - Device Removal Routine
2656 * @pdev: PCI device information struct
2657 *
2658 * atl1c_remove is called by the PCI subsystem to alert the driver
2659 * that it should release a PCI device. The could be caused by a
2660 * Hot-Plug event, or because the driver is going to be removed from
2661 * memory.
2662 */
2663static void __devexit atl1c_remove(struct pci_dev *pdev)
2664{
2665 struct net_device *netdev = pci_get_drvdata(pdev);
2666 struct atl1c_adapter *adapter = netdev_priv(netdev);
2667
2668 unregister_netdev(netdev);
2669 atl1c_phy_disable(&adapter->hw);
2670
2671 iounmap(adapter->hw.hw_addr);
2672
2673 pci_release_regions(pdev);
2674 pci_disable_device(pdev);
2675 free_netdev(netdev);
2676}
2677
2678/*
2679 * atl1c_io_error_detected - called when PCI error is detected
2680 * @pdev: Pointer to PCI device
2681 * @state: The current pci connection state
2682 *
2683 * This function is called after a PCI bus error affecting
2684 * this device has been detected.
2685 */
2686static pci_ers_result_t atl1c_io_error_detected(struct pci_dev *pdev,
2687 pci_channel_state_t state)
2688{
2689 struct net_device *netdev = pci_get_drvdata(pdev);
2690 struct atl1c_adapter *adapter = netdev_priv(netdev);
2691
2692 netif_device_detach(netdev);
2693
2694 if (netif_running(netdev))
2695 atl1c_down(adapter);
2696
2697 pci_disable_device(pdev);
2698
2699 /* Request a slot slot reset. */
2700 return PCI_ERS_RESULT_NEED_RESET;
2701}
2702
2703/*
2704 * atl1c_io_slot_reset - called after the pci bus has been reset.
2705 * @pdev: Pointer to PCI device
2706 *
2707 * Restart the card from scratch, as if from a cold-boot. Implementation
2708 * resembles the first-half of the e1000_resume routine.
2709 */
2710static pci_ers_result_t atl1c_io_slot_reset(struct pci_dev *pdev)
2711{
2712 struct net_device *netdev = pci_get_drvdata(pdev);
2713 struct atl1c_adapter *adapter = netdev_priv(netdev);
2714
2715 if (pci_enable_device(pdev)) {
2716 if (netif_msg_hw(adapter))
2717 dev_err(&pdev->dev,
2718 "Cannot re-enable PCI device after reset\n");
2719 return PCI_ERS_RESULT_DISCONNECT;
2720 }
2721 pci_set_master(pdev);
2722
2723 pci_enable_wake(pdev, PCI_D3hot, 0);
2724 pci_enable_wake(pdev, PCI_D3cold, 0);
2725
2726 atl1c_reset_mac(&adapter->hw);
2727
2728 return PCI_ERS_RESULT_RECOVERED;
2729}
2730
2731/*
2732 * atl1c_io_resume - called when traffic can start flowing again.
2733 * @pdev: Pointer to PCI device
2734 *
2735 * This callback is called when the error recovery driver tells us that
2736 * its OK to resume normal operation. Implementation resembles the
2737 * second-half of the atl1c_resume routine.
2738 */
2739static void atl1c_io_resume(struct pci_dev *pdev)
2740{
2741 struct net_device *netdev = pci_get_drvdata(pdev);
2742 struct atl1c_adapter *adapter = netdev_priv(netdev);
2743
2744 if (netif_running(netdev)) {
2745 if (atl1c_up(adapter)) {
2746 if (netif_msg_hw(adapter))
2747 dev_err(&pdev->dev,
2748 "Cannot bring device back up after reset\n");
2749 return;
2750 }
2751 }
2752
2753 netif_device_attach(netdev);
2754}
2755
2756static struct pci_error_handlers atl1c_err_handler = {
2757 .error_detected = atl1c_io_error_detected,
2758 .slot_reset = atl1c_io_slot_reset,
2759 .resume = atl1c_io_resume,
2760};
2761
2762static struct pci_driver atl1c_driver = {
2763 .name = atl1c_driver_name,
2764 .id_table = atl1c_pci_tbl,
2765 .probe = atl1c_probe,
2766 .remove = __devexit_p(atl1c_remove),
2767 /* Power Managment Hooks */
2768 .suspend = atl1c_suspend,
2769 .resume = atl1c_resume,
2770 .shutdown = atl1c_shutdown,
2771 .err_handler = &atl1c_err_handler
2772};
2773
2774/*
2775 * atl1c_init_module - Driver Registration Routine
2776 *
2777 * atl1c_init_module is the first routine called when the driver is
2778 * loaded. All it does is register with the PCI subsystem.
2779 */
2780static int __init atl1c_init_module(void)
2781{
2782 return pci_register_driver(&atl1c_driver);
2783}
2784
2785/*
2786 * atl1c_exit_module - Driver Exit Cleanup Routine
2787 *
2788 * atl1c_exit_module is called just before the driver is removed
2789 * from memory.
2790 */
2791static void __exit atl1c_exit_module(void)
2792{
2793 pci_unregister_driver(&atl1c_driver);
2794}
2795
2796module_init(atl1c_init_module);
2797module_exit(atl1c_exit_module);
diff --git a/drivers/net/cxgb3/cxgb3_main.c b/drivers/net/cxgb3/cxgb3_main.c
index 0089746b8d02..bab8a934c33d 100644
--- a/drivers/net/cxgb3/cxgb3_main.c
+++ b/drivers/net/cxgb3/cxgb3_main.c
@@ -90,6 +90,7 @@ static const struct pci_device_id cxgb3_pci_tbl[] = {
90 CH_DEVICE(0x30, 2), /* T3B10 */ 90 CH_DEVICE(0x30, 2), /* T3B10 */
91 CH_DEVICE(0x31, 3), /* T3B20 */ 91 CH_DEVICE(0x31, 3), /* T3B20 */
92 CH_DEVICE(0x32, 1), /* T3B02 */ 92 CH_DEVICE(0x32, 1), /* T3B02 */
93 CH_DEVICE(0x35, 6), /* T3C20-derived T3C10 */
93 {0,} 94 {0,}
94}; 95};
95 96
diff --git a/drivers/net/cxgb3/t3_hw.c b/drivers/net/cxgb3/t3_hw.c
index 2d1433077a8e..ac2a974dfe37 100644
--- a/drivers/net/cxgb3/t3_hw.c
+++ b/drivers/net/cxgb3/t3_hw.c
@@ -512,6 +512,13 @@ static const struct adapter_info t3_adap_info[] = {
512 F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL, 512 F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
513 { S_GPIO9, S_GPIO3 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI, 513 { S_GPIO9, S_GPIO3 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
514 &mi1_mdio_ext_ops, "Chelsio T320"}, 514 &mi1_mdio_ext_ops, "Chelsio T320"},
515 {},
516 {},
517 {1, 0,
518 F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO6_OEN | F_GPIO7_OEN |
519 F_GPIO10_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
520 { S_GPIO9 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
521 &mi1_mdio_ext_ops, "Chelsio T310" },
515}; 522};
516 523
517/* 524/*
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 5b910cf63740..b8251e827059 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -6011,9 +6011,20 @@ static void nv_shutdown(struct pci_dev *pdev)
6011 if (netif_running(dev)) 6011 if (netif_running(dev))
6012 nv_close(dev); 6012 nv_close(dev);
6013 6013
6014 nv_restore_mac_addr(pdev); 6014 /*
6015 * Restore the MAC so a kernel started by kexec won't get confused.
6016 * If we really go for poweroff, we must not restore the MAC,
6017 * otherwise the MAC for WOL will be reversed at least on some boards.
6018 */
6019 if (system_state != SYSTEM_POWER_OFF) {
6020 nv_restore_mac_addr(pdev);
6021 }
6015 6022
6016 pci_disable_device(pdev); 6023 pci_disable_device(pdev);
6024 /*
6025 * Apparently it is not possible to reinitialise from D3 hot,
6026 * only put the device into D3 if we really go for poweroff.
6027 */
6017 if (system_state == SYSTEM_POWER_OFF) { 6028 if (system_state == SYSTEM_POWER_OFF) {
6018 if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled)) 6029 if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
6019 pci_enable_wake(pdev, PCI_D3hot, np->wolenabled); 6030 pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index 5f31bbb614af..13f11f402a99 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -1175,7 +1175,7 @@ static void mib_counters_update(struct mv643xx_eth_private *mp)
1175{ 1175{
1176 struct mib_counters *p = &mp->mib_counters; 1176 struct mib_counters *p = &mp->mib_counters;
1177 1177
1178 spin_lock(&mp->mib_counters_lock); 1178 spin_lock_bh(&mp->mib_counters_lock);
1179 p->good_octets_received += mib_read(mp, 0x00); 1179 p->good_octets_received += mib_read(mp, 0x00);
1180 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32; 1180 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1181 p->bad_octets_received += mib_read(mp, 0x08); 1181 p->bad_octets_received += mib_read(mp, 0x08);
@@ -1208,7 +1208,7 @@ static void mib_counters_update(struct mv643xx_eth_private *mp)
1208 p->bad_crc_event += mib_read(mp, 0x74); 1208 p->bad_crc_event += mib_read(mp, 0x74);
1209 p->collision += mib_read(mp, 0x78); 1209 p->collision += mib_read(mp, 0x78);
1210 p->late_collision += mib_read(mp, 0x7c); 1210 p->late_collision += mib_read(mp, 0x7c);
1211 spin_unlock(&mp->mib_counters_lock); 1211 spin_unlock_bh(&mp->mib_counters_lock);
1212 1212
1213 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ); 1213 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1214} 1214}
@@ -1575,7 +1575,7 @@ oom:
1575 return; 1575 return;
1576 } 1576 }
1577 1577
1578 mc_spec = kmalloc(0x200, GFP_KERNEL); 1578 mc_spec = kmalloc(0x200, GFP_ATOMIC);
1579 if (mc_spec == NULL) 1579 if (mc_spec == NULL)
1580 goto oom; 1580 goto oom;
1581 mc_other = mc_spec + (0x100 >> 2); 1581 mc_other = mc_spec + (0x100 >> 2);
@@ -2216,8 +2216,6 @@ static int mv643xx_eth_stop(struct net_device *dev)
2216 wrlp(mp, INT_MASK, 0x00000000); 2216 wrlp(mp, INT_MASK, 0x00000000);
2217 rdlp(mp, INT_MASK); 2217 rdlp(mp, INT_MASK);
2218 2218
2219 del_timer_sync(&mp->mib_counters_timer);
2220
2221 napi_disable(&mp->napi); 2219 napi_disable(&mp->napi);
2222 2220
2223 del_timer_sync(&mp->rx_oom); 2221 del_timer_sync(&mp->rx_oom);
@@ -2229,6 +2227,7 @@ static int mv643xx_eth_stop(struct net_device *dev)
2229 port_reset(mp); 2227 port_reset(mp);
2230 mv643xx_eth_get_stats(dev); 2228 mv643xx_eth_get_stats(dev);
2231 mib_counters_update(mp); 2229 mib_counters_update(mp);
2230 del_timer_sync(&mp->mib_counters_timer);
2232 2231
2233 skb_queue_purge(&mp->rx_recycle); 2232 skb_queue_purge(&mp->rx_recycle);
2234 2233
diff --git a/drivers/net/smsc911x.c b/drivers/net/smsc911x.c
index 783c1a7b869e..9a78daec2fe9 100644
--- a/drivers/net/smsc911x.c
+++ b/drivers/net/smsc911x.c
@@ -1624,7 +1624,7 @@ static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
1624 do { 1624 do {
1625 msleep(1); 1625 msleep(1);
1626 e2cmd = smsc911x_reg_read(pdata, E2P_CMD); 1626 e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
1627 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (timeout--)); 1627 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
1628 1628
1629 if (!timeout) { 1629 if (!timeout) {
1630 SMSC_TRACE(DRV, "TIMED OUT"); 1630 SMSC_TRACE(DRV, "TIMED OUT");
diff --git a/drivers/net/smsc9420.c b/drivers/net/smsc9420.c
index a1e4b3895b33..4e15ae068b3f 100644
--- a/drivers/net/smsc9420.c
+++ b/drivers/net/smsc9420.c
@@ -341,7 +341,7 @@ static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)
341 do { 341 do {
342 msleep(1); 342 msleep(1);
343 e2cmd = smsc9420_reg_read(pd, E2P_CMD); 343 e2cmd = smsc9420_reg_read(pd, E2P_CMD);
344 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (timeout--)); 344 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
345 345
346 if (!timeout) { 346 if (!timeout) {
347 smsc_info(HW, "TIMED OUT"); 347 smsc_info(HW, "TIMED OUT");
@@ -413,6 +413,7 @@ static int smsc9420_ethtool_get_eeprom(struct net_device *dev,
413 } 413 }
414 414
415 memcpy(data, &eeprom_data[eeprom->offset], len); 415 memcpy(data, &eeprom_data[eeprom->offset], len);
416 eeprom->magic = SMSC9420_EEPROM_MAGIC;
416 eeprom->len = len; 417 eeprom->len = len;
417 return 0; 418 return 0;
418} 419}
@@ -423,6 +424,9 @@ static int smsc9420_ethtool_set_eeprom(struct net_device *dev,
423 struct smsc9420_pdata *pd = netdev_priv(dev); 424 struct smsc9420_pdata *pd = netdev_priv(dev);
424 int ret; 425 int ret;
425 426
427 if (eeprom->magic != SMSC9420_EEPROM_MAGIC)
428 return -EINVAL;
429
426 smsc9420_eeprom_enable_access(pd); 430 smsc9420_eeprom_enable_access(pd);
427 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_); 431 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);
428 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data); 432 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);
diff --git a/drivers/net/smsc9420.h b/drivers/net/smsc9420.h
index 69c351f93f86..e441402f77a2 100644
--- a/drivers/net/smsc9420.h
+++ b/drivers/net/smsc9420.h
@@ -44,6 +44,7 @@
44#define LAN_REGISTER_EXTENT (0x400) 44#define LAN_REGISTER_EXTENT (0x400)
45 45
46#define SMSC9420_EEPROM_SIZE ((u32)11) 46#define SMSC9420_EEPROM_SIZE ((u32)11)
47#define SMSC9420_EEPROM_MAGIC (0x9420)
47 48
48#define PKT_BUF_SZ (VLAN_ETH_FRAME_LEN + NET_IP_ALIGN + 4) 49#define PKT_BUF_SZ (VLAN_ETH_FRAME_LEN + NET_IP_ALIGN + 4)
49 50
diff --git a/drivers/net/sundance.c b/drivers/net/sundance.c
index feaf0e0577d7..43695b76606f 100644
--- a/drivers/net/sundance.c
+++ b/drivers/net/sundance.c
@@ -909,7 +909,7 @@ static void check_duplex(struct net_device *dev)
909 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d " 909 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d "
910 "negotiated capability %4.4x.\n", dev->name, 910 "negotiated capability %4.4x.\n", dev->name,
911 duplex ? "full" : "half", np->phys[0], negotiated); 911 duplex ? "full" : "half", np->phys[0], negotiated);
912 iowrite16(ioread16(ioaddr + MACCtrl0) | duplex ? 0x20 : 0, ioaddr + MACCtrl0); 912 iowrite16(ioread16(ioaddr + MACCtrl0) | (duplex ? 0x20 : 0), ioaddr + MACCtrl0);
913 } 913 }
914} 914}
915 915
diff --git a/drivers/net/sungem.c b/drivers/net/sungem.c
index 491876341068..8d64b1da0465 100644
--- a/drivers/net/sungem.c
+++ b/drivers/net/sungem.c
@@ -1157,7 +1157,7 @@ static void gem_pcs_reset(struct gem *gp)
1157 if (limit-- <= 0) 1157 if (limit-- <= 0)
1158 break; 1158 break;
1159 } 1159 }
1160 if (limit <= 0) 1160 if (limit < 0)
1161 printk(KERN_WARNING "%s: PCS reset bit would not clear.\n", 1161 printk(KERN_WARNING "%s: PCS reset bit would not clear.\n",
1162 gp->dev->name); 1162 gp->dev->name);
1163} 1163}
diff --git a/drivers/net/sunlance.c b/drivers/net/sunlance.c
index 281373281756..16c528db7251 100644
--- a/drivers/net/sunlance.c
+++ b/drivers/net/sunlance.c
@@ -343,7 +343,7 @@ static void lance_init_ring_dvma(struct net_device *dev)
343 ib->phys_addr [5] = dev->dev_addr [4]; 343 ib->phys_addr [5] = dev->dev_addr [4];
344 344
345 /* Setup the Tx ring entries */ 345 /* Setup the Tx ring entries */
346 for (i = 0; i <= TX_RING_SIZE; i++) { 346 for (i = 0; i < TX_RING_SIZE; i++) {
347 leptr = LANCE_ADDR(aib + libbuff_offset(tx_buf, i)); 347 leptr = LANCE_ADDR(aib + libbuff_offset(tx_buf, i));
348 ib->btx_ring [i].tmd0 = leptr; 348 ib->btx_ring [i].tmd0 = leptr;
349 ib->btx_ring [i].tmd1_hadr = leptr >> 16; 349 ib->btx_ring [i].tmd1_hadr = leptr >> 16;
@@ -399,7 +399,7 @@ static void lance_init_ring_pio(struct net_device *dev)
399 sbus_writeb(dev->dev_addr[4], &ib->phys_addr[5]); 399 sbus_writeb(dev->dev_addr[4], &ib->phys_addr[5]);
400 400
401 /* Setup the Tx ring entries */ 401 /* Setup the Tx ring entries */
402 for (i = 0; i <= TX_RING_SIZE; i++) { 402 for (i = 0; i < TX_RING_SIZE; i++) {
403 leptr = libbuff_offset(tx_buf, i); 403 leptr = libbuff_offset(tx_buf, i);
404 sbus_writew(leptr, &ib->btx_ring [i].tmd0); 404 sbus_writew(leptr, &ib->btx_ring [i].tmd0);
405 sbus_writeb(leptr >> 16,&ib->btx_ring [i].tmd1_hadr); 405 sbus_writeb(leptr >> 16,&ib->btx_ring [i].tmd1_hadr);
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 4595962fb8e1..b080f9493d83 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -2237,8 +2237,8 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2237 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; 2237 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2238 if (phyid != TG3_PHY_ID_BCMAC131) { 2238 if (phyid != TG3_PHY_ID_BCMAC131) {
2239 phyid &= TG3_PHY_OUI_MASK; 2239 phyid &= TG3_PHY_OUI_MASK;
2240 if (phyid == TG3_PHY_OUI_1 && 2240 if (phyid == TG3_PHY_OUI_1 ||
2241 phyid == TG3_PHY_OUI_2 && 2241 phyid == TG3_PHY_OUI_2 ||
2242 phyid == TG3_PHY_OUI_3) 2242 phyid == TG3_PHY_OUI_3)
2243 do_low_power = true; 2243 do_low_power = true;
2244 } 2244 }
diff --git a/drivers/net/veth.c b/drivers/net/veth.c
index 852d0e7c4e62..108bbbeacfb6 100644
--- a/drivers/net/veth.c
+++ b/drivers/net/veth.c
@@ -263,10 +263,11 @@ static void veth_dev_free(struct net_device *dev)
263} 263}
264 264
265static const struct net_device_ops veth_netdev_ops = { 265static const struct net_device_ops veth_netdev_ops = {
266 .ndo_init = veth_dev_init, 266 .ndo_init = veth_dev_init,
267 .ndo_open = veth_open, 267 .ndo_open = veth_open,
268 .ndo_start_xmit = veth_xmit, 268 .ndo_start_xmit = veth_xmit,
269 .ndo_get_stats = veth_get_stats, 269 .ndo_get_stats = veth_get_stats,
270 .ndo_set_mac_address = eth_mac_addr,
270}; 271};
271 272
272static void veth_setup(struct net_device *dev) 273static void veth_setup(struct net_device *dev)
diff --git a/drivers/net/wimax/i2400m/i2400m.h b/drivers/net/wimax/i2400m/i2400m.h
index 067c871cc226..3b9d27ea2950 100644
--- a/drivers/net/wimax/i2400m/i2400m.h
+++ b/drivers/net/wimax/i2400m/i2400m.h
@@ -157,7 +157,7 @@ enum {
157 157
158 158
159/* Firmware version we request when pulling the fw image file */ 159/* Firmware version we request when pulling the fw image file */
160#define I2400M_FW_VERSION "1.3" 160#define I2400M_FW_VERSION "1.4"
161 161
162 162
163/** 163/**
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-21 21:17:25 -0500