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-rw-r--r--drivers/bluetooth/hci_vhci.c2
-rw-r--r--drivers/char/drm/Kconfig7
-rw-r--r--drivers/char/drm/Makefile5
-rw-r--r--drivers/char/drm/ati_pcigart.c2
-rw-r--r--drivers/char/drm/drm.h2
-rw-r--r--drivers/char/drm/drmP.h30
-rw-r--r--drivers/char/drm/drm_auth.c4
-rw-r--r--drivers/char/drm/drm_bufs.c12
-rw-r--r--drivers/char/drm/drm_context.c4
-rw-r--r--drivers/char/drm/drm_drv.c9
-rw-r--r--drivers/char/drm/drm_fops.c14
-rw-r--r--drivers/char/drm/drm_irq.c2
-rw-r--r--drivers/char/drm/drm_lock.c12
-rw-r--r--drivers/char/drm/drm_memory.c13
-rw-r--r--drivers/char/drm/drm_pciids.h7
-rw-r--r--drivers/char/drm/drm_proc.c2
-rw-r--r--drivers/char/drm/drm_stub.c92
-rw-r--r--drivers/char/drm/drm_vm.c10
-rw-r--r--drivers/char/drm/i810_dma.c24
-rw-r--r--drivers/char/drm/i810_drv.h1
-rw-r--r--drivers/char/drm/i830_dma.c20
-rw-r--r--drivers/char/drm/i830_drv.c2
-rw-r--r--drivers/char/drm/i830_drv.h2
-rw-r--r--drivers/char/drm/i830_irq.c5
-rw-r--r--drivers/char/drm/i915_dma.c60
-rw-r--r--drivers/char/drm/i915_drv.c5
-rw-r--r--drivers/char/drm/i915_drv.h14
-rw-r--r--drivers/char/drm/i915_ioc32.c221
-rw-r--r--drivers/char/drm/i915_irq.c4
-rw-r--r--drivers/char/drm/mga_drv.c3
-rw-r--r--drivers/char/drm/mga_drv.h2
-rw-r--r--drivers/char/drm/mga_ioc32.c167
-rw-r--r--drivers/char/drm/r128_drv.c3
-rw-r--r--drivers/char/drm/r128_drv.h3
-rw-r--r--drivers/char/drm/r128_ioc32.c219
-rw-r--r--drivers/char/drm/r128_state.c2
-rw-r--r--drivers/char/drm/via_3d_reg.h1651
-rw-r--r--drivers/char/drm/via_dma.c741
-rw-r--r--drivers/char/drm/via_drm.h243
-rw-r--r--drivers/char/drm/via_drv.c126
-rw-r--r--drivers/char/drm/via_drv.h118
-rw-r--r--drivers/char/drm/via_ds.c280
-rw-r--r--drivers/char/drm/via_ds.h104
-rw-r--r--drivers/char/drm/via_irq.c339
-rw-r--r--drivers/char/drm/via_map.c110
-rw-r--r--drivers/char/drm/via_mm.c358
-rw-r--r--drivers/char/drm/via_mm.h40
-rw-r--r--drivers/char/drm/via_verifier.c1061
-rw-r--r--drivers/char/drm/via_verifier.h61
-rw-r--r--drivers/char/drm/via_video.c97
-rw-r--r--drivers/ieee1394/Kconfig12
-rw-r--r--drivers/ieee1394/csr.c3
-rw-r--r--drivers/ieee1394/csr1212.c37
-rw-r--r--drivers/ieee1394/dma.c2
-rw-r--r--drivers/ieee1394/eth1394.c6
-rw-r--r--drivers/ieee1394/ieee1394_core.c35
-rw-r--r--drivers/ieee1394/iso.c27
-rw-r--r--drivers/ieee1394/iso.h13
-rw-r--r--drivers/ieee1394/nodemgr.c2
-rw-r--r--drivers/ieee1394/ohci1394.c40
-rw-r--r--drivers/ieee1394/pcilynx.c4
-rw-r--r--drivers/ieee1394/raw1394.c7
-rw-r--r--drivers/ieee1394/sbp2.c135
-rw-r--r--drivers/isdn/hisax/isdnl1.c3
-rw-r--r--drivers/isdn/hisax/isdnl2.c17
-rw-r--r--drivers/isdn/hisax/isdnl3.c2
-rw-r--r--drivers/isdn/i4l/isdn_tty.c4
-rw-r--r--drivers/isdn/icn/icn.c4
-rw-r--r--drivers/net/hamradio/scc.c5
-rw-r--r--drivers/net/ppp_async.c2
-rw-r--r--drivers/net/ppp_generic.c12
-rw-r--r--drivers/net/ppp_synctty.c2
-rw-r--r--drivers/net/tun.c2
-rw-r--r--drivers/net/wireless/airo.c4
-rw-r--r--drivers/s390/net/claw.c4
-rw-r--r--drivers/s390/net/ctctty.c6
-rw-r--r--drivers/usb/net/usbnet.c6
77 files changed, 6417 insertions, 294 deletions
diff --git a/drivers/bluetooth/hci_vhci.c b/drivers/bluetooth/hci_vhci.c
index 3256192dcde8..f9b956fb2b8b 100644
--- a/drivers/bluetooth/hci_vhci.c
+++ b/drivers/bluetooth/hci_vhci.c
@@ -120,7 +120,7 @@ static unsigned int hci_vhci_chr_poll(struct file *file, poll_table * wait)
120 120
121 poll_wait(file, &hci_vhci->read_wait, wait); 121 poll_wait(file, &hci_vhci->read_wait, wait);
122 122
123 if (skb_queue_len(&hci_vhci->readq)) 123 if (!skb_queue_empty(&hci_vhci->readq))
124 return POLLIN | POLLRDNORM; 124 return POLLIN | POLLRDNORM;
125 125
126 return POLLOUT | POLLWRNORM; 126 return POLLOUT | POLLWRNORM;
diff --git a/drivers/char/drm/Kconfig b/drivers/char/drm/Kconfig
index c2b12eab67c9..123417e43040 100644
--- a/drivers/char/drm/Kconfig
+++ b/drivers/char/drm/Kconfig
@@ -96,3 +96,10 @@ config DRM_SIS
96 chipset. If M is selected the module will be called sis. AGP 96 chipset. If M is selected the module will be called sis. AGP
97 support is required for this driver to work. 97 support is required for this driver to work.
98 98
99config DRM_VIA
100 tristate "Via unichrome video cards"
101 depends on DRM
102 help
103 Choose this option if you have a Via unichrome or compatible video
104 chipset. If M is selected the module will be called via.
105
diff --git a/drivers/char/drm/Makefile b/drivers/char/drm/Makefile
index 7444dec40b94..ddd941045b1f 100644
--- a/drivers/char/drm/Makefile
+++ b/drivers/char/drm/Makefile
@@ -18,10 +18,14 @@ i915-objs := i915_drv.o i915_dma.o i915_irq.o i915_mem.o
18radeon-objs := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o 18radeon-objs := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o
19ffb-objs := ffb_drv.o ffb_context.o 19ffb-objs := ffb_drv.o ffb_context.o
20sis-objs := sis_drv.o sis_ds.o sis_mm.o 20sis-objs := sis_drv.o sis_ds.o sis_mm.o
21via-objs := via_irq.o via_drv.o via_ds.o via_map.o via_mm.o via_dma.o via_verifier.o via_video.o
21 22
22ifeq ($(CONFIG_COMPAT),y) 23ifeq ($(CONFIG_COMPAT),y)
23drm-objs += drm_ioc32.o 24drm-objs += drm_ioc32.o
24radeon-objs += radeon_ioc32.o 25radeon-objs += radeon_ioc32.o
26mga-objs += mga_ioc32.o
27r128-objs += r128_ioc32.o
28i915-objs += i915_ioc32.o
25endif 29endif
26 30
27obj-$(CONFIG_DRM) += drm.o 31obj-$(CONFIG_DRM) += drm.o
@@ -35,4 +39,5 @@ obj-$(CONFIG_DRM_I830) += i830.o
35obj-$(CONFIG_DRM_I915) += i915.o 39obj-$(CONFIG_DRM_I915) += i915.o
36obj-$(CONFIG_DRM_FFB) += ffb.o 40obj-$(CONFIG_DRM_FFB) += ffb.o
37obj-$(CONFIG_DRM_SIS) += sis.o 41obj-$(CONFIG_DRM_SIS) += sis.o
42obj-$(CONFIG_DRM_VIA) +=via.o
38 43
diff --git a/drivers/char/drm/ati_pcigart.c b/drivers/char/drm/ati_pcigart.c
index fdca1876ecd5..0aec5ef481b8 100644
--- a/drivers/char/drm/ati_pcigart.c
+++ b/drivers/char/drm/ati_pcigart.c
@@ -52,7 +52,7 @@
52# define ATI_MAX_PCIGART_PAGES 8192 /**< 32 MB aperture, 4K pages */ 52# define ATI_MAX_PCIGART_PAGES 8192 /**< 32 MB aperture, 4K pages */
53# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ 53# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
54 54
55unsigned long drm_ati_alloc_pcigart_table( void ) 55static unsigned long drm_ati_alloc_pcigart_table( void )
56{ 56{
57 unsigned long address; 57 unsigned long address;
58 struct page *page; 58 struct page *page;
diff --git a/drivers/char/drm/drm.h b/drivers/char/drm/drm.h
index 587305282ea8..e8371dd87fbc 100644
--- a/drivers/char/drm/drm.h
+++ b/drivers/char/drm/drm.h
@@ -38,7 +38,9 @@
38#define _DRM_H_ 38#define _DRM_H_
39 39
40#if defined(__linux__) 40#if defined(__linux__)
41#if defined(__KERNEL__)
41#include <linux/config.h> 42#include <linux/config.h>
43#endif
42#include <asm/ioctl.h> /* For _IO* macros */ 44#include <asm/ioctl.h> /* For _IO* macros */
43#define DRM_IOCTL_NR(n) _IOC_NR(n) 45#define DRM_IOCTL_NR(n) _IOC_NR(n)
44#define DRM_IOC_VOID _IOC_NONE 46#define DRM_IOC_VOID _IOC_NONE
diff --git a/drivers/char/drm/drmP.h b/drivers/char/drm/drmP.h
index b04ddf12a0ff..5df09cc8c6db 100644
--- a/drivers/char/drm/drmP.h
+++ b/drivers/char/drm/drmP.h
@@ -774,8 +774,6 @@ extern int drm_cpu_valid( void );
774 /* Driver support (drm_drv.h) */ 774 /* Driver support (drm_drv.h) */
775extern int drm_init(struct drm_driver *driver); 775extern int drm_init(struct drm_driver *driver);
776extern void drm_exit(struct drm_driver *driver); 776extern void drm_exit(struct drm_driver *driver);
777extern int drm_version(struct inode *inode, struct file *filp,
778 unsigned int cmd, unsigned long arg);
779extern int drm_ioctl(struct inode *inode, struct file *filp, 777extern int drm_ioctl(struct inode *inode, struct file *filp,
780 unsigned int cmd, unsigned long arg); 778 unsigned int cmd, unsigned long arg);
781extern long drm_compat_ioctl(struct file *filp, 779extern long drm_compat_ioctl(struct file *filp,
@@ -785,28 +783,19 @@ extern int drm_takedown(drm_device_t * dev);
785 /* Device support (drm_fops.h) */ 783 /* Device support (drm_fops.h) */
786extern int drm_open(struct inode *inode, struct file *filp); 784extern int drm_open(struct inode *inode, struct file *filp);
787extern int drm_stub_open(struct inode *inode, struct file *filp); 785extern int drm_stub_open(struct inode *inode, struct file *filp);
788extern int drm_open_helper(struct inode *inode, struct file *filp,
789 drm_device_t *dev);
790extern int drm_flush(struct file *filp); 786extern int drm_flush(struct file *filp);
791extern int drm_fasync(int fd, struct file *filp, int on); 787extern int drm_fasync(int fd, struct file *filp, int on);
792extern int drm_release(struct inode *inode, struct file *filp); 788extern int drm_release(struct inode *inode, struct file *filp);
793 789
794 /* Mapping support (drm_vm.h) */ 790 /* Mapping support (drm_vm.h) */
795extern void drm_vm_open(struct vm_area_struct *vma);
796extern void drm_vm_close(struct vm_area_struct *vma);
797extern void drm_vm_shm_close(struct vm_area_struct *vma);
798extern int drm_mmap_dma(struct file *filp,
799 struct vm_area_struct *vma);
800extern int drm_mmap(struct file *filp, struct vm_area_struct *vma); 791extern int drm_mmap(struct file *filp, struct vm_area_struct *vma);
801extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait); 792extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait);
802extern ssize_t drm_read(struct file *filp, char __user *buf, size_t count, loff_t *off);
803 793
804 /* Memory management support (drm_memory.h) */ 794 /* Memory management support (drm_memory.h) */
805#include "drm_memory.h" 795#include "drm_memory.h"
806extern void drm_mem_init(void); 796extern void drm_mem_init(void);
807extern int drm_mem_info(char *buf, char **start, off_t offset, 797extern int drm_mem_info(char *buf, char **start, off_t offset,
808 int request, int *eof, void *data); 798 int request, int *eof, void *data);
809extern void *drm_calloc(size_t nmemb, size_t size, int area);
810extern void *drm_realloc(void *oldpt, size_t oldsize, size_t size, 799extern void *drm_realloc(void *oldpt, size_t oldsize, size_t size,
811 int area); 800 int area);
812extern unsigned long drm_alloc_pages(int order, int area); 801extern unsigned long drm_alloc_pages(int order, int area);
@@ -854,9 +843,6 @@ extern int drm_newctx( struct inode *inode, struct file *filp,
854extern int drm_rmctx( struct inode *inode, struct file *filp, 843extern int drm_rmctx( struct inode *inode, struct file *filp,
855 unsigned int cmd, unsigned long arg ); 844 unsigned int cmd, unsigned long arg );
856 845
857extern int drm_context_switch(drm_device_t *dev, int old, int new);
858extern int drm_context_switch_complete(drm_device_t *dev, int new);
859
860extern int drm_ctxbitmap_init( drm_device_t *dev ); 846extern int drm_ctxbitmap_init( drm_device_t *dev );
861extern void drm_ctxbitmap_cleanup( drm_device_t *dev ); 847extern void drm_ctxbitmap_cleanup( drm_device_t *dev );
862extern void drm_ctxbitmap_free( drm_device_t *dev, int ctx_handle ); 848extern void drm_ctxbitmap_free( drm_device_t *dev, int ctx_handle );
@@ -874,9 +860,6 @@ extern int drm_rmdraw(struct inode *inode, struct file *filp,
874 860
875 861
876 /* Authentication IOCTL support (drm_auth.h) */ 862 /* Authentication IOCTL support (drm_auth.h) */
877extern int drm_add_magic(drm_device_t *dev, drm_file_t *priv,
878 drm_magic_t magic);
879extern int drm_remove_magic(drm_device_t *dev, drm_magic_t magic);
880extern int drm_getmagic(struct inode *inode, struct file *filp, 863extern int drm_getmagic(struct inode *inode, struct file *filp,
881 unsigned int cmd, unsigned long arg); 864 unsigned int cmd, unsigned long arg);
882extern int drm_authmagic(struct inode *inode, struct file *filp, 865extern int drm_authmagic(struct inode *inode, struct file *filp,
@@ -893,13 +876,9 @@ extern int drm_unlock(struct inode *inode, struct file *filp,
893 unsigned int cmd, unsigned long arg); 876 unsigned int cmd, unsigned long arg);
894extern int drm_lock_take(__volatile__ unsigned int *lock, 877extern int drm_lock_take(__volatile__ unsigned int *lock,
895 unsigned int context); 878 unsigned int context);
896extern int drm_lock_transfer(drm_device_t *dev,
897 __volatile__ unsigned int *lock,
898 unsigned int context);
899extern int drm_lock_free(drm_device_t *dev, 879extern int drm_lock_free(drm_device_t *dev,
900 __volatile__ unsigned int *lock, 880 __volatile__ unsigned int *lock,
901 unsigned int context); 881 unsigned int context);
902extern int drm_notifier(void *priv);
903 882
904 /* Buffer management support (drm_bufs.h) */ 883 /* Buffer management support (drm_bufs.h) */
905extern int drm_order( unsigned long size ); 884extern int drm_order( unsigned long size );
@@ -927,7 +906,6 @@ extern void drm_core_reclaim_buffers(drm_device_t *dev, struct file *filp);
927 /* IRQ support (drm_irq.h) */ 906 /* IRQ support (drm_irq.h) */
928extern int drm_control( struct inode *inode, struct file *filp, 907extern int drm_control( struct inode *inode, struct file *filp,
929 unsigned int cmd, unsigned long arg ); 908 unsigned int cmd, unsigned long arg );
930extern int drm_irq_install( drm_device_t *dev );
931extern int drm_irq_uninstall( drm_device_t *dev ); 909extern int drm_irq_uninstall( drm_device_t *dev );
932extern irqreturn_t drm_irq_handler( DRM_IRQ_ARGS ); 910extern irqreturn_t drm_irq_handler( DRM_IRQ_ARGS );
933extern void drm_driver_irq_preinstall( drm_device_t *dev ); 911extern void drm_driver_irq_preinstall( drm_device_t *dev );
@@ -967,7 +945,6 @@ extern int drm_agp_unbind_memory(DRM_AGP_MEM *handle);
967extern int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent, 945extern int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
968 struct drm_driver *driver); 946 struct drm_driver *driver);
969extern int drm_put_dev(drm_device_t * dev); 947extern int drm_put_dev(drm_device_t * dev);
970extern int drm_get_head(drm_device_t * dev, drm_head_t *head);
971extern int drm_put_head(drm_head_t * head); 948extern int drm_put_head(drm_head_t * head);
972extern unsigned int drm_debug; 949extern unsigned int drm_debug;
973extern unsigned int drm_cards_limit; 950extern unsigned int drm_cards_limit;
@@ -1064,9 +1041,16 @@ static __inline__ void drm_free(void *pt, size_t size, int area)
1064{ 1041{
1065 kfree(pt); 1042 kfree(pt);
1066} 1043}
1044
1045/** Wrapper around kcalloc() */
1046static __inline__ void *drm_calloc(size_t nmemb, size_t size, int area)
1047{
1048 return kcalloc(nmemb, size, GFP_KERNEL);
1049}
1067#else 1050#else
1068extern void *drm_alloc(size_t size, int area); 1051extern void *drm_alloc(size_t size, int area);
1069extern void drm_free(void *pt, size_t size, int area); 1052extern void drm_free(void *pt, size_t size, int area);
1053extern void *drm_calloc(size_t nmemb, size_t size, int area);
1070#endif 1054#endif
1071 1055
1072/*@}*/ 1056/*@}*/
diff --git a/drivers/char/drm/drm_auth.c b/drivers/char/drm/drm_auth.c
index b428761c4e91..dd140bca8f71 100644
--- a/drivers/char/drm/drm_auth.c
+++ b/drivers/char/drm/drm_auth.c
@@ -87,7 +87,7 @@ static drm_file_t *drm_find_file(drm_device_t *dev, drm_magic_t magic)
87 * associated the magic number hash key in drm_device::magiclist, while holding 87 * associated the magic number hash key in drm_device::magiclist, while holding
88 * the drm_device::struct_sem lock. 88 * the drm_device::struct_sem lock.
89 */ 89 */
90int drm_add_magic(drm_device_t *dev, drm_file_t *priv, drm_magic_t magic) 90static int drm_add_magic(drm_device_t *dev, drm_file_t *priv, drm_magic_t magic)
91{ 91{
92 int hash; 92 int hash;
93 drm_magic_entry_t *entry; 93 drm_magic_entry_t *entry;
@@ -124,7 +124,7 @@ int drm_add_magic(drm_device_t *dev, drm_file_t *priv, drm_magic_t magic)
124 * Searches and unlinks the entry in drm_device::magiclist with the magic 124 * Searches and unlinks the entry in drm_device::magiclist with the magic
125 * number hash key, while holding the drm_device::struct_sem lock. 125 * number hash key, while holding the drm_device::struct_sem lock.
126 */ 126 */
127int drm_remove_magic(drm_device_t *dev, drm_magic_t magic) 127static int drm_remove_magic(drm_device_t *dev, drm_magic_t magic)
128{ 128{
129 drm_magic_entry_t *prev = NULL; 129 drm_magic_entry_t *prev = NULL;
130 drm_magic_entry_t *pt; 130 drm_magic_entry_t *pt;
diff --git a/drivers/char/drm/drm_bufs.c b/drivers/char/drm/drm_bufs.c
index 3407380b865a..4c6191d231b8 100644
--- a/drivers/char/drm/drm_bufs.c
+++ b/drivers/char/drm/drm_bufs.c
@@ -356,8 +356,8 @@ static void drm_cleanup_buf_error(drm_device_t *dev, drm_buf_entry_t *entry)
356 * reallocates the buffer list of the same size order to accommodate the new 356 * reallocates the buffer list of the same size order to accommodate the new
357 * buffers. 357 * buffers.
358 */ 358 */
359int drm_addbufs_agp( struct inode *inode, struct file *filp, 359static int drm_addbufs_agp( struct inode *inode, struct file *filp,
360 unsigned int cmd, unsigned long arg ) 360 unsigned int cmd, unsigned long arg )
361{ 361{
362 drm_file_t *priv = filp->private_data; 362 drm_file_t *priv = filp->private_data;
363 drm_device_t *dev = priv->head->dev; 363 drm_device_t *dev = priv->head->dev;
@@ -521,8 +521,8 @@ int drm_addbufs_agp( struct inode *inode, struct file *filp,
521} 521}
522#endif /* __OS_HAS_AGP */ 522#endif /* __OS_HAS_AGP */
523 523
524int drm_addbufs_pci( struct inode *inode, struct file *filp, 524static int drm_addbufs_pci( struct inode *inode, struct file *filp,
525 unsigned int cmd, unsigned long arg ) 525 unsigned int cmd, unsigned long arg )
526{ 526{
527 drm_file_t *priv = filp->private_data; 527 drm_file_t *priv = filp->private_data;
528 drm_device_t *dev = priv->head->dev; 528 drm_device_t *dev = priv->head->dev;
@@ -751,8 +751,8 @@ int drm_addbufs_pci( struct inode *inode, struct file *filp,
751 751
752} 752}
753 753
754int drm_addbufs_sg( struct inode *inode, struct file *filp, 754static int drm_addbufs_sg( struct inode *inode, struct file *filp,
755 unsigned int cmd, unsigned long arg ) 755 unsigned int cmd, unsigned long arg )
756{ 756{
757 drm_file_t *priv = filp->private_data; 757 drm_file_t *priv = filp->private_data;
758 drm_device_t *dev = priv->head->dev; 758 drm_device_t *dev = priv->head->dev;
diff --git a/drivers/char/drm/drm_context.c b/drivers/char/drm/drm_context.c
index fdf661f234ed..a7cfabd1ca2e 100644
--- a/drivers/char/drm/drm_context.c
+++ b/drivers/char/drm/drm_context.c
@@ -84,7 +84,7 @@ failed:
84 * drm_device::context_sareas to accommodate the new entry while holding the 84 * drm_device::context_sareas to accommodate the new entry while holding the
85 * drm_device::struct_sem lock. 85 * drm_device::struct_sem lock.
86 */ 86 */
87int drm_ctxbitmap_next( drm_device_t *dev ) 87static int drm_ctxbitmap_next( drm_device_t *dev )
88{ 88{
89 int bit; 89 int bit;
90 90
@@ -326,7 +326,7 @@ int drm_context_switch( drm_device_t *dev, int old, int new )
326 * hardware lock is held, clears the drm_device::context_flag and wakes up 326 * hardware lock is held, clears the drm_device::context_flag and wakes up
327 * drm_device::context_wait. 327 * drm_device::context_wait.
328 */ 328 */
329int drm_context_switch_complete( drm_device_t *dev, int new ) 329static int drm_context_switch_complete( drm_device_t *dev, int new )
330{ 330{
331 dev->last_context = new; /* PRE/POST: This is the _only_ writer. */ 331 dev->last_context = new; /* PRE/POST: This is the _only_ writer. */
332 dev->last_switch = jiffies; 332 dev->last_switch = jiffies;
diff --git a/drivers/char/drm/drm_drv.c b/drivers/char/drm/drm_drv.c
index 1e37ed0c6b8d..3333c250c4d9 100644
--- a/drivers/char/drm/drm_drv.c
+++ b/drivers/char/drm/drm_drv.c
@@ -51,8 +51,11 @@
51#include "drmP.h" 51#include "drmP.h"
52#include "drm_core.h" 52#include "drm_core.h"
53 53
54static int drm_version(struct inode *inode, struct file *filp,
55 unsigned int cmd, unsigned long arg);
56
54/** Ioctl table */ 57/** Ioctl table */
55drm_ioctl_desc_t drm_ioctls[] = { 58static drm_ioctl_desc_t drm_ioctls[] = {
56 [DRM_IOCTL_NR(DRM_IOCTL_VERSION)] = { drm_version, 0, 0 }, 59 [DRM_IOCTL_NR(DRM_IOCTL_VERSION)] = { drm_version, 0, 0 },
57 [DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = { drm_getunique, 0, 0 }, 60 [DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = { drm_getunique, 0, 0 },
58 [DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)] = { drm_getmagic, 0, 0 }, 61 [DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)] = { drm_getmagic, 0, 0 },
@@ -447,8 +450,8 @@ module_exit( drm_core_exit );
447 * 450 *
448 * Fills in the version information in \p arg. 451 * Fills in the version information in \p arg.
449 */ 452 */
450int drm_version( struct inode *inode, struct file *filp, 453static int drm_version( struct inode *inode, struct file *filp,
451 unsigned int cmd, unsigned long arg ) 454 unsigned int cmd, unsigned long arg )
452{ 455{
453 drm_file_t *priv = filp->private_data; 456 drm_file_t *priv = filp->private_data;
454 drm_device_t *dev = priv->head->dev; 457 drm_device_t *dev = priv->head->dev;
diff --git a/drivers/char/drm/drm_fops.c b/drivers/char/drm/drm_fops.c
index 906794247aeb..10e64fde8d78 100644
--- a/drivers/char/drm/drm_fops.c
+++ b/drivers/char/drm/drm_fops.c
@@ -37,6 +37,8 @@
37#include "drmP.h" 37#include "drmP.h"
38#include <linux/poll.h> 38#include <linux/poll.h>
39 39
40static int drm_open_helper(struct inode *inode, struct file *filp, drm_device_t *dev);
41
40static int drm_setup( drm_device_t *dev ) 42static int drm_setup( drm_device_t *dev )
41{ 43{
42 int i; 44 int i;
@@ -251,7 +253,7 @@ int drm_release( struct inode *inode, struct file *filp )
251 } 253 }
252 } 254 }
253 255
254 if (drm_core_check_feature(dev, DRIVER_HAVE_DMA)) 256 if (drm_core_check_feature(dev, DRIVER_HAVE_DMA) && !dev->driver->release)
255 { 257 {
256 dev->driver->reclaim_buffers(dev, filp); 258 dev->driver->reclaim_buffers(dev, filp);
257 } 259 }
@@ -259,7 +261,7 @@ int drm_release( struct inode *inode, struct file *filp )
259 drm_fasync( -1, filp, 0 ); 261 drm_fasync( -1, filp, 0 );
260 262
261 down( &dev->ctxlist_sem ); 263 down( &dev->ctxlist_sem );
262 if ( !list_empty( &dev->ctxlist->head ) ) { 264 if ( dev->ctxlist && (!list_empty(&dev->ctxlist->head))) {
263 drm_ctx_list_t *pos, *n; 265 drm_ctx_list_t *pos, *n;
264 266
265 list_for_each_entry_safe( pos, n, &dev->ctxlist->head, head ) { 267 list_for_each_entry_safe( pos, n, &dev->ctxlist->head, head ) {
@@ -341,7 +343,7 @@ EXPORT_SYMBOL(drm_release);
341 * Creates and initializes a drm_file structure for the file private data in \p 343 * Creates and initializes a drm_file structure for the file private data in \p
342 * filp and add it into the double linked list in \p dev. 344 * filp and add it into the double linked list in \p dev.
343 */ 345 */
344int drm_open_helper(struct inode *inode, struct file *filp, drm_device_t *dev) 346static int drm_open_helper(struct inode *inode, struct file *filp, drm_device_t *dev)
345{ 347{
346 int minor = iminor(inode); 348 int minor = iminor(inode);
347 drm_file_t *priv; 349 drm_file_t *priv;
@@ -443,9 +445,3 @@ unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait)
443} 445}
444EXPORT_SYMBOL(drm_poll); 446EXPORT_SYMBOL(drm_poll);
445 447
446
447/** No-op. */
448ssize_t drm_read(struct file *filp, char __user *buf, size_t count, loff_t *off)
449{
450 return 0;
451}
diff --git a/drivers/char/drm/drm_irq.c b/drivers/char/drm/drm_irq.c
index 2e236ebcf27b..cdd4aecd25e2 100644
--- a/drivers/char/drm/drm_irq.c
+++ b/drivers/char/drm/drm_irq.c
@@ -89,7 +89,7 @@ int drm_irq_by_busid(struct inode *inode, struct file *filp,
89 * \c drm_driver_irq_preinstall() and \c drm_driver_irq_postinstall() functions 89 * \c drm_driver_irq_preinstall() and \c drm_driver_irq_postinstall() functions
90 * before and after the installation. 90 * before and after the installation.
91 */ 91 */
92int drm_irq_install( drm_device_t *dev ) 92static int drm_irq_install( drm_device_t *dev )
93{ 93{
94 int ret; 94 int ret;
95 unsigned long sh_flags=0; 95 unsigned long sh_flags=0;
diff --git a/drivers/char/drm/drm_lock.c b/drivers/char/drm/drm_lock.c
index d0d6fc661625..4702d863bcc6 100644
--- a/drivers/char/drm/drm_lock.c
+++ b/drivers/char/drm/drm_lock.c
@@ -35,6 +35,11 @@
35 35
36#include "drmP.h" 36#include "drmP.h"
37 37
38static int drm_lock_transfer(drm_device_t *dev,
39 __volatile__ unsigned int *lock,
40 unsigned int context);
41static int drm_notifier(void *priv);
42
38/** 43/**
39 * Lock ioctl. 44 * Lock ioctl.
40 * 45 *
@@ -225,8 +230,9 @@ int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context)
225 * Resets the lock file pointer. 230 * Resets the lock file pointer.
226 * Marks the lock as held by the given context, via the \p cmpxchg instruction. 231 * Marks the lock as held by the given context, via the \p cmpxchg instruction.
227 */ 232 */
228int drm_lock_transfer(drm_device_t *dev, 233static int drm_lock_transfer(drm_device_t *dev,
229 __volatile__ unsigned int *lock, unsigned int context) 234 __volatile__ unsigned int *lock,
235 unsigned int context)
230{ 236{
231 unsigned int old, new, prev; 237 unsigned int old, new, prev;
232 238
@@ -282,7 +288,7 @@ int drm_lock_free(drm_device_t *dev,
282 * \return one if the signal should be delivered normally, or zero if the 288 * \return one if the signal should be delivered normally, or zero if the
283 * signal should be blocked. 289 * signal should be blocked.
284 */ 290 */
285int drm_notifier(void *priv) 291static int drm_notifier(void *priv)
286{ 292{
287 drm_sigdata_t *s = (drm_sigdata_t *)priv; 293 drm_sigdata_t *s = (drm_sigdata_t *)priv;
288 unsigned int old, new, prev; 294 unsigned int old, new, prev;
diff --git a/drivers/char/drm/drm_memory.c b/drivers/char/drm/drm_memory.c
index 7f53f756c052..ace3d42f4407 100644
--- a/drivers/char/drm/drm_memory.c
+++ b/drivers/char/drm/drm_memory.c
@@ -65,19 +65,6 @@ int drm_mem_info(char *buf, char **start, off_t offset,
65 return 0; 65 return 0;
66} 66}
67 67
68/** Wrapper around kmalloc() */
69void *drm_calloc(size_t nmemb, size_t size, int area)
70{
71 void *addr;
72
73 addr = kmalloc(size * nmemb, GFP_KERNEL);
74 if (addr != NULL)
75 memset((void *)addr, 0, size * nmemb);
76
77 return addr;
78}
79EXPORT_SYMBOL(drm_calloc);
80
81/** Wrapper around kmalloc() and kfree() */ 68/** Wrapper around kmalloc() and kfree() */
82void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area) 69void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area)
83{ 70{
diff --git a/drivers/char/drm/drm_pciids.h b/drivers/char/drm/drm_pciids.h
index 11c6950158b3..70ca4fa55c9d 100644
--- a/drivers/char/drm/drm_pciids.h
+++ b/drivers/char/drm/drm_pciids.h
@@ -223,3 +223,10 @@
223 {0x8086, 0x2772, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 223 {0x8086, 0x2772, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
224 {0, 0, 0} 224 {0, 0, 0}
225 225
226#define viadrv_PCI_IDS \
227 {0x1106, 0x3022, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
228 {0x1106, 0x3122, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
229 {0x1106, 0x7205, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
230 {0x1106, 0x7204, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
231 {0, 0, 0}
232
diff --git a/drivers/char/drm/drm_proc.c b/drivers/char/drm/drm_proc.c
index 6e06e8c6a516..4774087d2e9e 100644
--- a/drivers/char/drm/drm_proc.c
+++ b/drivers/char/drm/drm_proc.c
@@ -57,7 +57,7 @@ static int drm_vma_info(char *buf, char **start, off_t offset,
57/** 57/**
58 * Proc file list. 58 * Proc file list.
59 */ 59 */
60struct drm_proc_list { 60static struct drm_proc_list {
61 const char *name; /**< file name */ 61 const char *name; /**< file name */
62 int (*f)(char *, char **, off_t, int, int *, void *); /**< proc callback*/ 62 int (*f)(char *, char **, off_t, int, int *, void *); /**< proc callback*/
63} drm_proc_list[] = { 63} drm_proc_list[] = {
diff --git a/drivers/char/drm/drm_stub.c b/drivers/char/drm/drm_stub.c
index 8ccbdef7bb3e..48829a1a086a 100644
--- a/drivers/char/drm/drm_stub.c
+++ b/drivers/char/drm/drm_stub.c
@@ -157,52 +157,6 @@ int drm_stub_open(struct inode *inode, struct file *filp)
157 return err; 157 return err;
158} 158}
159 159
160
161/**
162 * Register.
163 *
164 * \param pdev - PCI device structure
165 * \param ent entry from the PCI ID table with device type flags
166 * \return zero on success or a negative number on failure.
167 *
168 * Attempt to gets inter module "drm" information. If we are first
169 * then register the character device and inter module information.
170 * Try and register, if we fail to register, backout previous work.
171 */
172int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
173 struct drm_driver *driver)
174{
175 drm_device_t *dev;
176 int ret;
177
178 DRM_DEBUG("\n");
179
180 dev = drm_calloc(1, sizeof(*dev), DRM_MEM_STUB);
181 if (!dev)
182 return -ENOMEM;
183
184 pci_enable_device(pdev);
185
186 if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
187 printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
188 goto err_g1;
189 }
190 if ((ret = drm_get_head(dev, &dev->primary)))
191 goto err_g1;
192
193 /* postinit is a required function to display the signon banner */
194 /* drivers add secondary heads here if needed */
195 if ((ret = dev->driver->postinit(dev, ent->driver_data)))
196 goto err_g1;
197
198 return 0;
199
200err_g1:
201 drm_free(dev, sizeof(*dev), DRM_MEM_STUB);
202 return ret;
203}
204EXPORT_SYMBOL(drm_get_dev);
205
206/** 160/**
207 * Get a secondary minor number. 161 * Get a secondary minor number.
208 * 162 *
@@ -214,7 +168,7 @@ EXPORT_SYMBOL(drm_get_dev);
214 * create the proc init entry via proc_init(). This routines assigns 168 * create the proc init entry via proc_init(). This routines assigns
215 * minor numbers to secondary heads of multi-headed cards 169 * minor numbers to secondary heads of multi-headed cards
216 */ 170 */
217int drm_get_head(drm_device_t *dev, drm_head_t *head) 171static int drm_get_head(drm_device_t *dev, drm_head_t *head)
218{ 172{
219 drm_head_t **heads = drm_heads; 173 drm_head_t **heads = drm_heads;
220 int ret; 174 int ret;
@@ -262,6 +216,50 @@ err_g1:
262 return ret; 216 return ret;
263} 217}
264 218
219/**
220 * Register.
221 *
222 * \param pdev - PCI device structure
223 * \param ent entry from the PCI ID table with device type flags
224 * \return zero on success or a negative number on failure.
225 *
226 * Attempt to gets inter module "drm" information. If we are first
227 * then register the character device and inter module information.
228 * Try and register, if we fail to register, backout previous work.
229 */
230int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
231 struct drm_driver *driver)
232{
233 drm_device_t *dev;
234 int ret;
235
236 DRM_DEBUG("\n");
237
238 dev = drm_calloc(1, sizeof(*dev), DRM_MEM_STUB);
239 if (!dev)
240 return -ENOMEM;
241
242 pci_enable_device(pdev);
243
244 if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
245 printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
246 goto err_g1;
247 }
248 if ((ret = drm_get_head(dev, &dev->primary)))
249 goto err_g1;
250
251 /* postinit is a required function to display the signon banner */
252 /* drivers add secondary heads here if needed */
253 if ((ret = dev->driver->postinit(dev, ent->driver_data)))
254 goto err_g1;
255
256 return 0;
257
258err_g1:
259 drm_free(dev, sizeof(*dev), DRM_MEM_STUB);
260 return ret;
261}
262EXPORT_SYMBOL(drm_get_dev);
265 263
266/** 264/**
267 * Put a device minor number. 265 * Put a device minor number.
diff --git a/drivers/char/drm/drm_vm.c b/drivers/char/drm/drm_vm.c
index fc72f30f312b..621220f3f372 100644
--- a/drivers/char/drm/drm_vm.c
+++ b/drivers/char/drm/drm_vm.c
@@ -38,6 +38,8 @@
38#include <linux/efi.h> 38#include <linux/efi.h>
39#endif 39#endif
40 40
41static void drm_vm_open(struct vm_area_struct *vma);
42static void drm_vm_close(struct vm_area_struct *vma);
41 43
42/** 44/**
43 * \c nopage method for AGP virtual memory. 45 * \c nopage method for AGP virtual memory.
@@ -163,7 +165,7 @@ static __inline__ struct page *drm_do_vm_shm_nopage(struct vm_area_struct *vma,
163 * Deletes map information if we are the last 165 * Deletes map information if we are the last
164 * person to close a mapping and it's not in the global maplist. 166 * person to close a mapping and it's not in the global maplist.
165 */ 167 */
166void drm_vm_shm_close(struct vm_area_struct *vma) 168static void drm_vm_shm_close(struct vm_area_struct *vma)
167{ 169{
168 drm_file_t *priv = vma->vm_file->private_data; 170 drm_file_t *priv = vma->vm_file->private_data;
169 drm_device_t *dev = priv->head->dev; 171 drm_device_t *dev = priv->head->dev;
@@ -399,7 +401,7 @@ static struct vm_operations_struct drm_vm_sg_ops = {
399 * Create a new drm_vma_entry structure as the \p vma private data entry and 401 * Create a new drm_vma_entry structure as the \p vma private data entry and
400 * add it to drm_device::vmalist. 402 * add it to drm_device::vmalist.
401 */ 403 */
402void drm_vm_open(struct vm_area_struct *vma) 404static void drm_vm_open(struct vm_area_struct *vma)
403{ 405{
404 drm_file_t *priv = vma->vm_file->private_data; 406 drm_file_t *priv = vma->vm_file->private_data;
405 drm_device_t *dev = priv->head->dev; 407 drm_device_t *dev = priv->head->dev;
@@ -428,7 +430,7 @@ void drm_vm_open(struct vm_area_struct *vma)
428 * Search the \p vma private data entry in drm_device::vmalist, unlink it, and 430 * Search the \p vma private data entry in drm_device::vmalist, unlink it, and
429 * free it. 431 * free it.
430 */ 432 */
431void drm_vm_close(struct vm_area_struct *vma) 433static void drm_vm_close(struct vm_area_struct *vma)
432{ 434{
433 drm_file_t *priv = vma->vm_file->private_data; 435 drm_file_t *priv = vma->vm_file->private_data;
434 drm_device_t *dev = priv->head->dev; 436 drm_device_t *dev = priv->head->dev;
@@ -463,7 +465,7 @@ void drm_vm_close(struct vm_area_struct *vma)
463 * Sets the virtual memory area operations structure to vm_dma_ops, the file 465 * Sets the virtual memory area operations structure to vm_dma_ops, the file
464 * pointer, and calls vm_open(). 466 * pointer, and calls vm_open().
465 */ 467 */
466int drm_mmap_dma(struct file *filp, struct vm_area_struct *vma) 468static int drm_mmap_dma(struct file *filp, struct vm_area_struct *vma)
467{ 469{
468 drm_file_t *priv = filp->private_data; 470 drm_file_t *priv = filp->private_data;
469 drm_device_t *dev; 471 drm_device_t *dev;
diff --git a/drivers/char/drm/i810_dma.c b/drivers/char/drm/i810_dma.c
index 24857cc6c23b..18e0b7622893 100644
--- a/drivers/char/drm/i810_dma.c
+++ b/drivers/char/drm/i810_dma.c
@@ -90,16 +90,7 @@ static int i810_freelist_put(drm_device_t *dev, drm_buf_t *buf)
90 return 0; 90 return 0;
91} 91}
92 92
93static struct file_operations i810_buffer_fops = { 93static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
94 .open = drm_open,
95 .flush = drm_flush,
96 .release = drm_release,
97 .ioctl = drm_ioctl,
98 .mmap = i810_mmap_buffers,
99 .fasync = drm_fasync,
100};
101
102int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
103{ 94{
104 drm_file_t *priv = filp->private_data; 95 drm_file_t *priv = filp->private_data;
105 drm_device_t *dev; 96 drm_device_t *dev;
@@ -126,6 +117,15 @@ int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
126 return 0; 117 return 0;
127} 118}
128 119
120static struct file_operations i810_buffer_fops = {
121 .open = drm_open,
122 .flush = drm_flush,
123 .release = drm_release,
124 .ioctl = drm_ioctl,
125 .mmap = i810_mmap_buffers,
126 .fasync = drm_fasync,
127};
128
129static int i810_map_buffer(drm_buf_t *buf, struct file *filp) 129static int i810_map_buffer(drm_buf_t *buf, struct file *filp)
130{ 130{
131 drm_file_t *priv = filp->private_data; 131 drm_file_t *priv = filp->private_data;
@@ -1003,8 +1003,8 @@ void i810_reclaim_buffers(drm_device_t *dev, struct file *filp)
1003 } 1003 }
1004} 1004}
1005 1005
1006int i810_flush_ioctl(struct inode *inode, struct file *filp, 1006static int i810_flush_ioctl(struct inode *inode, struct file *filp,
1007 unsigned int cmd, unsigned long arg) 1007 unsigned int cmd, unsigned long arg)
1008{ 1008{
1009 drm_file_t *priv = filp->private_data; 1009 drm_file_t *priv = filp->private_data;
1010 drm_device_t *dev = priv->head->dev; 1010 drm_device_t *dev = priv->head->dev;
diff --git a/drivers/char/drm/i810_drv.h b/drivers/char/drm/i810_drv.h
index fa23ca454e57..1b40538d1725 100644
--- a/drivers/char/drm/i810_drv.h
+++ b/drivers/char/drm/i810_drv.h
@@ -115,7 +115,6 @@ typedef struct drm_i810_private {
115 115
116 /* i810_dma.c */ 116 /* i810_dma.c */
117extern void i810_reclaim_buffers(drm_device_t *dev, struct file *filp); 117extern void i810_reclaim_buffers(drm_device_t *dev, struct file *filp);
118extern int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma);
119 118
120extern int i810_driver_dma_quiescent(drm_device_t *dev); 119extern int i810_driver_dma_quiescent(drm_device_t *dev);
121extern void i810_driver_release(drm_device_t *dev, struct file *filp); 120extern void i810_driver_release(drm_device_t *dev, struct file *filp);
diff --git a/drivers/char/drm/i830_dma.c b/drivers/char/drm/i830_dma.c
index 98adccf8e434..dc7733035864 100644
--- a/drivers/char/drm/i830_dma.c
+++ b/drivers/char/drm/i830_dma.c
@@ -92,16 +92,7 @@ static int i830_freelist_put(drm_device_t *dev, drm_buf_t *buf)
92 return 0; 92 return 0;
93} 93}
94 94
95static struct file_operations i830_buffer_fops = { 95static int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
96 .open = drm_open,
97 .flush = drm_flush,
98 .release = drm_release,
99 .ioctl = drm_ioctl,
100 .mmap = i830_mmap_buffers,
101 .fasync = drm_fasync,
102};
103
104int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
105{ 96{
106 drm_file_t *priv = filp->private_data; 97 drm_file_t *priv = filp->private_data;
107 drm_device_t *dev; 98 drm_device_t *dev;
@@ -128,6 +119,15 @@ int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
128 return 0; 119 return 0;
129} 120}
130 121
122static struct file_operations i830_buffer_fops = {
123 .open = drm_open,
124 .flush = drm_flush,
125 .release = drm_release,
126 .ioctl = drm_ioctl,
127 .mmap = i830_mmap_buffers,
128 .fasync = drm_fasync,
129};
130
131static int i830_map_buffer(drm_buf_t *buf, struct file *filp) 131static int i830_map_buffer(drm_buf_t *buf, struct file *filp)
132{ 132{
133 drm_file_t *priv = filp->private_data; 133 drm_file_t *priv = filp->private_data;
diff --git a/drivers/char/drm/i830_drv.c b/drivers/char/drm/i830_drv.c
index aa80ad6a5ee0..bc36be76b8b2 100644
--- a/drivers/char/drm/i830_drv.c
+++ b/drivers/char/drm/i830_drv.c
@@ -40,7 +40,7 @@
40 40
41#include "drm_pciids.h" 41#include "drm_pciids.h"
42 42
43int postinit( struct drm_device *dev, unsigned long flags ) 43static int postinit( struct drm_device *dev, unsigned long flags )
44{ 44{
45 dev->counters += 4; 45 dev->counters += 4;
46 dev->types[6] = _DRM_STAT_IRQ; 46 dev->types[6] = _DRM_STAT_IRQ;
diff --git a/drivers/char/drm/i830_drv.h b/drivers/char/drm/i830_drv.h
index d4b2d093d6ab..df7746131dea 100644
--- a/drivers/char/drm/i830_drv.h
+++ b/drivers/char/drm/i830_drv.h
@@ -123,8 +123,6 @@ typedef struct drm_i830_private {
123/* i830_dma.c */ 123/* i830_dma.c */
124extern void i830_reclaim_buffers(drm_device_t *dev, struct file *filp); 124extern void i830_reclaim_buffers(drm_device_t *dev, struct file *filp);
125 125
126extern int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma);
127
128/* i830_irq.c */ 126/* i830_irq.c */
129extern int i830_irq_emit( struct inode *inode, struct file *filp, 127extern int i830_irq_emit( struct inode *inode, struct file *filp,
130 unsigned int cmd, unsigned long arg ); 128 unsigned int cmd, unsigned long arg );
diff --git a/drivers/char/drm/i830_irq.c b/drivers/char/drm/i830_irq.c
index 6d7729ffe2dc..a5923e5d0a77 100644
--- a/drivers/char/drm/i830_irq.c
+++ b/drivers/char/drm/i830_irq.c
@@ -54,8 +54,7 @@ irqreturn_t i830_driver_irq_handler( DRM_IRQ_ARGS )
54 return IRQ_HANDLED; 54 return IRQ_HANDLED;
55} 55}
56 56
57 57static int i830_emit_irq(drm_device_t *dev)
58int i830_emit_irq(drm_device_t *dev)
59{ 58{
60 drm_i830_private_t *dev_priv = dev->dev_private; 59 drm_i830_private_t *dev_priv = dev->dev_private;
61 RING_LOCALS; 60 RING_LOCALS;
@@ -73,7 +72,7 @@ int i830_emit_irq(drm_device_t *dev)
73} 72}
74 73
75 74
76int i830_wait_irq(drm_device_t *dev, int irq_nr) 75static int i830_wait_irq(drm_device_t *dev, int irq_nr)
77{ 76{
78 drm_i830_private_t *dev_priv = 77 drm_i830_private_t *dev_priv =
79 (drm_i830_private_t *)dev->dev_private; 78 (drm_i830_private_t *)dev->dev_private;
diff --git a/drivers/char/drm/i915_dma.c b/drivers/char/drm/i915_dma.c
index b5903f9f1423..acf9e52a9507 100644
--- a/drivers/char/drm/i915_dma.c
+++ b/drivers/char/drm/i915_dma.c
@@ -32,23 +32,6 @@
32#include "i915_drm.h" 32#include "i915_drm.h"
33#include "i915_drv.h" 33#include "i915_drv.h"
34 34
35drm_ioctl_desc_t i915_ioctls[] = {
36 [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, 1, 1},
37 [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, 1, 0},
38 [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, 1, 0},
39 [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, 1, 0},
40 [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, 1, 0},
41 [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, 1, 0},
42 [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, 1, 0},
43 [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, 1, 1},
44 [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, 1, 0},
45 [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, 1, 0},
46 [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, 1, 1},
47 [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, 1, 0}
48};
49
50int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
51
52/* Really want an OS-independent resettable timer. Would like to have 35/* Really want an OS-independent resettable timer. Would like to have
53 * this loop run for (eg) 3 sec, but have the timer reset every time 36 * this loop run for (eg) 3 sec, but have the timer reset every time
54 * the head pointer changes, so that EBUSY only happens if the ring 37 * the head pointer changes, so that EBUSY only happens if the ring
@@ -95,7 +78,7 @@ void i915_kernel_lost_context(drm_device_t * dev)
95 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; 78 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
96} 79}
97 80
98int i915_dma_cleanup(drm_device_t * dev) 81static int i915_dma_cleanup(drm_device_t * dev)
99{ 82{
100 /* Make sure interrupts are disabled here because the uninstall ioctl 83 /* Make sure interrupts are disabled here because the uninstall ioctl
101 * may not have been called from userspace and after dev_private 84 * may not have been called from userspace and after dev_private
@@ -247,7 +230,7 @@ static int i915_resume(drm_device_t * dev)
247 return 0; 230 return 0;
248} 231}
249 232
250int i915_dma_init(DRM_IOCTL_ARGS) 233static int i915_dma_init(DRM_IOCTL_ARGS)
251{ 234{
252 DRM_DEVICE; 235 DRM_DEVICE;
253 drm_i915_private_t *dev_priv; 236 drm_i915_private_t *dev_priv;
@@ -558,7 +541,7 @@ static int i915_quiescent(drm_device_t * dev)
558 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__); 541 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
559} 542}
560 543
561int i915_flush_ioctl(DRM_IOCTL_ARGS) 544static int i915_flush_ioctl(DRM_IOCTL_ARGS)
562{ 545{
563 DRM_DEVICE; 546 DRM_DEVICE;
564 547
@@ -567,7 +550,7 @@ int i915_flush_ioctl(DRM_IOCTL_ARGS)
567 return i915_quiescent(dev); 550 return i915_quiescent(dev);
568} 551}
569 552
570int i915_batchbuffer(DRM_IOCTL_ARGS) 553static int i915_batchbuffer(DRM_IOCTL_ARGS)
571{ 554{
572 DRM_DEVICE; 555 DRM_DEVICE;
573 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 556 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -601,7 +584,7 @@ int i915_batchbuffer(DRM_IOCTL_ARGS)
601 return ret; 584 return ret;
602} 585}
603 586
604int i915_cmdbuffer(DRM_IOCTL_ARGS) 587static int i915_cmdbuffer(DRM_IOCTL_ARGS)
605{ 588{
606 DRM_DEVICE; 589 DRM_DEVICE;
607 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 590 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -637,18 +620,7 @@ int i915_cmdbuffer(DRM_IOCTL_ARGS)
637 return 0; 620 return 0;
638} 621}
639 622
640int i915_do_cleanup_pageflip(drm_device_t * dev) 623static int i915_flip_bufs(DRM_IOCTL_ARGS)
641{
642 drm_i915_private_t *dev_priv = dev->dev_private;
643
644 DRM_DEBUG("%s\n", __FUNCTION__);
645 if (dev_priv->current_page != 0)
646 i915_dispatch_flip(dev);
647
648 return 0;
649}
650
651int i915_flip_bufs(DRM_IOCTL_ARGS)
652{ 624{
653 DRM_DEVICE; 625 DRM_DEVICE;
654 626
@@ -659,7 +631,7 @@ int i915_flip_bufs(DRM_IOCTL_ARGS)
659 return i915_dispatch_flip(dev); 631 return i915_dispatch_flip(dev);
660} 632}
661 633
662int i915_getparam(DRM_IOCTL_ARGS) 634static int i915_getparam(DRM_IOCTL_ARGS)
663{ 635{
664 DRM_DEVICE; 636 DRM_DEVICE;
665 drm_i915_private_t *dev_priv = dev->dev_private; 637 drm_i915_private_t *dev_priv = dev->dev_private;
@@ -694,7 +666,7 @@ int i915_getparam(DRM_IOCTL_ARGS)
694 return 0; 666 return 0;
695} 667}
696 668
697int i915_setparam(DRM_IOCTL_ARGS) 669static int i915_setparam(DRM_IOCTL_ARGS)
698{ 670{
699 DRM_DEVICE; 671 DRM_DEVICE;
700 drm_i915_private_t *dev_priv = dev->dev_private; 672 drm_i915_private_t *dev_priv = dev->dev_private;
@@ -743,3 +715,19 @@ void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp)
743 } 715 }
744} 716}
745 717
718drm_ioctl_desc_t i915_ioctls[] = {
719 [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, 1, 1},
720 [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, 1, 0},
721 [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, 1, 0},
722 [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, 1, 0},
723 [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, 1, 0},
724 [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, 1, 0},
725 [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, 1, 0},
726 [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, 1, 1},
727 [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, 1, 0},
728 [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, 1, 0},
729 [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, 1, 1},
730 [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, 1, 0}
731};
732
733int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
diff --git a/drivers/char/drm/i915_drv.c b/drivers/char/drm/i915_drv.c
index e6a9e1d1d283..1f59d3fc79bc 100644
--- a/drivers/char/drm/i915_drv.c
+++ b/drivers/char/drm/i915_drv.c
@@ -34,7 +34,7 @@
34 34
35#include "drm_pciids.h" 35#include "drm_pciids.h"
36 36
37int postinit( struct drm_device *dev, unsigned long flags ) 37static int postinit( struct drm_device *dev, unsigned long flags )
38{ 38{
39 dev->counters += 4; 39 dev->counters += 4;
40 dev->types[6] = _DRM_STAT_IRQ; 40 dev->types[6] = _DRM_STAT_IRQ;
@@ -97,6 +97,9 @@ static struct drm_driver driver = {
97 .mmap = drm_mmap, 97 .mmap = drm_mmap,
98 .poll = drm_poll, 98 .poll = drm_poll,
99 .fasync = drm_fasync, 99 .fasync = drm_fasync,
100#ifdef CONFIG_COMPAT
101 .compat_ioctl = i915_compat_ioctl,
102#endif
100 }, 103 },
101 .pci_driver = { 104 .pci_driver = {
102 .name = DRIVER_NAME, 105 .name = DRIVER_NAME,
diff --git a/drivers/char/drm/i915_drv.h b/drivers/char/drm/i915_drv.h
index fa940d64b85d..9c37d2367dd5 100644
--- a/drivers/char/drm/i915_drv.h
+++ b/drivers/char/drm/i915_drv.h
@@ -99,14 +99,6 @@ typedef struct drm_i915_private {
99} drm_i915_private_t; 99} drm_i915_private_t;
100 100
101 /* i915_dma.c */ 101 /* i915_dma.c */
102extern int i915_dma_init(DRM_IOCTL_ARGS);
103extern int i915_dma_cleanup(drm_device_t * dev);
104extern int i915_flush_ioctl(DRM_IOCTL_ARGS);
105extern int i915_batchbuffer(DRM_IOCTL_ARGS);
106extern int i915_flip_bufs(DRM_IOCTL_ARGS);
107extern int i915_getparam(DRM_IOCTL_ARGS);
108extern int i915_setparam(DRM_IOCTL_ARGS);
109extern int i915_cmdbuffer(DRM_IOCTL_ARGS);
110extern void i915_kernel_lost_context(drm_device_t * dev); 102extern void i915_kernel_lost_context(drm_device_t * dev);
111extern void i915_driver_pretakedown(drm_device_t *dev); 103extern void i915_driver_pretakedown(drm_device_t *dev);
112extern void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp); 104extern void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp);
@@ -114,8 +106,6 @@ extern void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp);
114/* i915_irq.c */ 106/* i915_irq.c */
115extern int i915_irq_emit(DRM_IOCTL_ARGS); 107extern int i915_irq_emit(DRM_IOCTL_ARGS);
116extern int i915_irq_wait(DRM_IOCTL_ARGS); 108extern int i915_irq_wait(DRM_IOCTL_ARGS);
117extern int i915_wait_irq(drm_device_t * dev, int irq_nr);
118extern int i915_emit_irq(drm_device_t * dev);
119 109
120extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 110extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
121extern void i915_driver_irq_preinstall(drm_device_t *dev); 111extern void i915_driver_irq_preinstall(drm_device_t *dev);
@@ -130,6 +120,10 @@ extern void i915_mem_takedown(struct mem_block **heap);
130extern void i915_mem_release(drm_device_t * dev, 120extern void i915_mem_release(drm_device_t * dev,
131 DRMFILE filp, struct mem_block *heap); 121 DRMFILE filp, struct mem_block *heap);
132 122
123extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
124 unsigned long arg);
125
126
133#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, reg) 127#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, reg)
134#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, reg, val) 128#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, reg, val)
135#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, reg) 129#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, reg)
diff --git a/drivers/char/drm/i915_ioc32.c b/drivers/char/drm/i915_ioc32.c
new file mode 100644
index 000000000000..fe009e1b3a3f
--- /dev/null
+++ b/drivers/char/drm/i915_ioc32.c
@@ -0,0 +1,221 @@
1/**
2 * \file i915_ioc32.c
3 *
4 * 32-bit ioctl compatibility routines for the i915 DRM.
5 *
6 * \author Alan Hourihane <alanh@fairlite.demon.co.uk>
7 *
8 *
9 * Copyright (C) Paul Mackerras 2005
10 * Copyright (C) Alan Hourihane 2005
11 * All Rights Reserved.
12 *
13 * Permission is hereby granted, free of charge, to any person obtaining a
14 * copy of this software and associated documentation files (the "Software"),
15 * to deal in the Software without restriction, including without limitation
16 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
17 * and/or sell copies of the Software, and to permit persons to whom the
18 * Software is furnished to do so, subject to the following conditions:
19 *
20 * The above copyright notice and this permission notice (including the next
21 * paragraph) shall be included in all copies or substantial portions of the
22 * Software.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
25 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
26 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
27 * THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
28 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
29 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 * IN THE SOFTWARE.
31 */
32#include <linux/compat.h>
33#include <linux/ioctl32.h>
34
35#include "drmP.h"
36#include "drm.h"
37#include "i915_drm.h"
38
39typedef struct _drm_i915_batchbuffer32 {
40 int start; /* agp offset */
41 int used; /* nr bytes in use */
42 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
43 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
44 int num_cliprects; /* mulitpass with multiple cliprects? */
45 u32 cliprects; /* pointer to userspace cliprects */
46} drm_i915_batchbuffer32_t;
47
48static int compat_i915_batchbuffer(struct file *file, unsigned int cmd,
49 unsigned long arg)
50{
51 drm_i915_batchbuffer32_t batchbuffer32;
52 drm_i915_batchbuffer_t __user *batchbuffer;
53
54 if (copy_from_user(&batchbuffer32, (void __user *)arg, sizeof(batchbuffer32)))
55 return -EFAULT;
56
57 batchbuffer = compat_alloc_user_space(sizeof(*batchbuffer));
58 if (!access_ok(VERIFY_WRITE, batchbuffer, sizeof(*batchbuffer))
59 || __put_user(batchbuffer32.start, &batchbuffer->start)
60 || __put_user(batchbuffer32.used, &batchbuffer->used)
61 || __put_user(batchbuffer32.DR1, &batchbuffer->DR1)
62 || __put_user(batchbuffer32.DR4, &batchbuffer->DR4)
63 || __put_user(batchbuffer32.num_cliprects, &batchbuffer->num_cliprects)
64 || __put_user((int __user *)(unsigned long)batchbuffer32.cliprects,
65 &batchbuffer->cliprects))
66 return -EFAULT;
67
68 return drm_ioctl(file->f_dentry->d_inode, file,
69 DRM_IOCTL_I915_BATCHBUFFER, (unsigned long) batchbuffer);
70}
71
72typedef struct _drm_i915_cmdbuffer32 {
73 u32 buf; /* pointer to userspace command buffer */
74 int sz; /* nr bytes in buf */
75 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
76 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
77 int num_cliprects; /* mulitpass with multiple cliprects? */
78 u32 cliprects; /* pointer to userspace cliprects */
79} drm_i915_cmdbuffer32_t;
80
81static int compat_i915_cmdbuffer(struct file *file, unsigned int cmd,
82 unsigned long arg)
83{
84 drm_i915_cmdbuffer32_t cmdbuffer32;
85 drm_i915_cmdbuffer_t __user *cmdbuffer;
86
87 if (copy_from_user(&cmdbuffer32, (void __user *)arg, sizeof(cmdbuffer32)))
88 return -EFAULT;
89
90 cmdbuffer = compat_alloc_user_space(sizeof(*cmdbuffer));
91 if (!access_ok(VERIFY_WRITE, cmdbuffer, sizeof(*cmdbuffer))
92 || __put_user((int __user *)(unsigned long)cmdbuffer32.buf,
93 &cmdbuffer->buf)
94 || __put_user(cmdbuffer32.sz, &cmdbuffer->sz)
95 || __put_user(cmdbuffer32.DR1, &cmdbuffer->DR1)
96 || __put_user(cmdbuffer32.DR4, &cmdbuffer->DR4)
97 || __put_user(cmdbuffer32.num_cliprects, &cmdbuffer->num_cliprects)
98 || __put_user((int __user *)(unsigned long)cmdbuffer32.cliprects,
99 &cmdbuffer->cliprects))
100 return -EFAULT;
101
102 return drm_ioctl(file->f_dentry->d_inode, file,
103 DRM_IOCTL_I915_CMDBUFFER, (unsigned long) cmdbuffer);
104}
105
106typedef struct drm_i915_irq_emit32 {
107 u32 irq_seq;
108} drm_i915_irq_emit32_t;
109
110static int compat_i915_irq_emit(struct file *file, unsigned int cmd,
111 unsigned long arg)
112{
113 drm_i915_irq_emit32_t req32;
114 drm_i915_irq_emit_t __user *request;
115
116 if (copy_from_user(&req32, (void __user *) arg, sizeof(req32)))
117 return -EFAULT;
118
119 request = compat_alloc_user_space(sizeof(*request));
120 if (!access_ok(VERIFY_WRITE, request, sizeof(*request))
121 || __put_user((int __user *)(unsigned long)req32.irq_seq,
122 &request->irq_seq))
123 return -EFAULT;
124
125 return drm_ioctl(file->f_dentry->d_inode, file,
126 DRM_IOCTL_I915_IRQ_EMIT, (unsigned long) request);
127}
128typedef struct drm_i915_getparam32 {
129 int param;
130 u32 value;
131} drm_i915_getparam32_t;
132
133static int compat_i915_getparam(struct file *file, unsigned int cmd,
134 unsigned long arg)
135{
136 drm_i915_getparam32_t req32;
137 drm_i915_getparam_t __user *request;
138
139 if (copy_from_user(&req32, (void __user *) arg, sizeof(req32)))
140 return -EFAULT;
141
142 request = compat_alloc_user_space(sizeof(*request));
143 if (!access_ok(VERIFY_WRITE, request, sizeof(*request))
144 || __put_user(req32.param, &request->param)
145 || __put_user((void __user *)(unsigned long)req32.value,
146 &request->value))
147 return -EFAULT;
148
149 return drm_ioctl(file->f_dentry->d_inode, file,
150 DRM_IOCTL_I915_GETPARAM, (unsigned long) request);
151}
152
153typedef struct drm_i915_mem_alloc32 {
154 int region;
155 int alignment;
156 int size;
157 u32 region_offset; /* offset from start of fb or agp */
158} drm_i915_mem_alloc32_t;
159
160static int compat_i915_alloc(struct file *file, unsigned int cmd,
161 unsigned long arg)
162{
163 drm_i915_mem_alloc32_t req32;
164 drm_i915_mem_alloc_t __user *request;
165
166 if (copy_from_user(&req32, (void __user *) arg, sizeof(req32)))
167 return -EFAULT;
168
169 request = compat_alloc_user_space(sizeof(*request));
170 if (!access_ok(VERIFY_WRITE, request, sizeof(*request))
171 || __put_user(req32.region, &request->region)
172 || __put_user(req32.alignment, &request->alignment)
173 || __put_user(req32.size, &request->size)
174 || __put_user((void __user *)(unsigned long)req32.region_offset,
175 &request->region_offset))
176 return -EFAULT;
177
178 return drm_ioctl(file->f_dentry->d_inode, file,
179 DRM_IOCTL_I915_ALLOC, (unsigned long) request);
180}
181
182
183drm_ioctl_compat_t *i915_compat_ioctls[] = {
184 [DRM_I915_BATCHBUFFER] = compat_i915_batchbuffer,
185 [DRM_I915_CMDBUFFER] = compat_i915_cmdbuffer,
186 [DRM_I915_GETPARAM] = compat_i915_getparam,
187 [DRM_I915_IRQ_EMIT] = compat_i915_irq_emit,
188 [DRM_I915_ALLOC] = compat_i915_alloc
189};
190
191/**
192 * Called whenever a 32-bit process running under a 64-bit kernel
193 * performs an ioctl on /dev/dri/card<n>.
194 *
195 * \param filp file pointer.
196 * \param cmd command.
197 * \param arg user argument.
198 * \return zero on success or negative number on failure.
199 */
200long i915_compat_ioctl(struct file *filp, unsigned int cmd,
201 unsigned long arg)
202{
203 unsigned int nr = DRM_IOCTL_NR(cmd);
204 drm_ioctl_compat_t *fn = NULL;
205 int ret;
206
207 if (nr < DRM_COMMAND_BASE)
208 return drm_compat_ioctl(filp, cmd, arg);
209
210 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(i915_compat_ioctls))
211 fn = i915_compat_ioctls[nr - DRM_COMMAND_BASE];
212
213 lock_kernel(); /* XXX for now */
214 if (fn != NULL)
215 ret = (*fn)(filp, cmd, arg);
216 else
217 ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg);
218 unlock_kernel();
219
220 return ret;
221}
diff --git a/drivers/char/drm/i915_irq.c b/drivers/char/drm/i915_irq.c
index a101cc9cfd7e..4fa448ee846b 100644
--- a/drivers/char/drm/i915_irq.c
+++ b/drivers/char/drm/i915_irq.c
@@ -56,7 +56,7 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
56 return IRQ_HANDLED; 56 return IRQ_HANDLED;
57} 57}
58 58
59int i915_emit_irq(drm_device_t * dev) 59static int i915_emit_irq(drm_device_t * dev)
60{ 60{
61 drm_i915_private_t *dev_priv = dev->dev_private; 61 drm_i915_private_t *dev_priv = dev->dev_private;
62 u32 ret; 62 u32 ret;
@@ -76,7 +76,7 @@ int i915_emit_irq(drm_device_t * dev)
76 return ret; 76 return ret;
77} 77}
78 78
79int i915_wait_irq(drm_device_t * dev, int irq_nr) 79static int i915_wait_irq(drm_device_t * dev, int irq_nr)
80{ 80{
81 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 81 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82 int ret = 0; 82 int ret = 0;
diff --git a/drivers/char/drm/mga_drv.c b/drivers/char/drm/mga_drv.c
index 22dab3e9d92a..844cca9cb29d 100644
--- a/drivers/char/drm/mga_drv.c
+++ b/drivers/char/drm/mga_drv.c
@@ -101,6 +101,9 @@ static struct drm_driver driver = {
101 .mmap = drm_mmap, 101 .mmap = drm_mmap,
102 .poll = drm_poll, 102 .poll = drm_poll,
103 .fasync = drm_fasync, 103 .fasync = drm_fasync,
104#ifdef CONFIG_COMPAT
105 .compat_ioctl = mga_compat_ioctl,
106#endif
104 }, 107 },
105 .pci_driver = { 108 .pci_driver = {
106 .name = DRIVER_NAME, 109 .name = DRIVER_NAME,
diff --git a/drivers/char/drm/mga_drv.h b/drivers/char/drm/mga_drv.h
index 1d84a1eb34db..9412e2816eb7 100644
--- a/drivers/char/drm/mga_drv.h
+++ b/drivers/char/drm/mga_drv.h
@@ -137,6 +137,8 @@ extern irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS );
137extern void mga_driver_irq_preinstall( drm_device_t *dev ); 137extern void mga_driver_irq_preinstall( drm_device_t *dev );
138extern void mga_driver_irq_postinstall( drm_device_t *dev ); 138extern void mga_driver_irq_postinstall( drm_device_t *dev );
139extern void mga_driver_irq_uninstall( drm_device_t *dev ); 139extern void mga_driver_irq_uninstall( drm_device_t *dev );
140extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
141 unsigned long arg);
140 142
141#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER() 143#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER()
142 144
diff --git a/drivers/char/drm/mga_ioc32.c b/drivers/char/drm/mga_ioc32.c
new file mode 100644
index 000000000000..bc745cfa2095
--- /dev/null
+++ b/drivers/char/drm/mga_ioc32.c
@@ -0,0 +1,167 @@
1/**
2 * \file mga_ioc32.c
3 *
4 * 32-bit ioctl compatibility routines for the MGA DRM.
5 *
6 * \author Dave Airlie <airlied@linux.ie> with code from patches by Egbert Eich
7 *
8 *
9 * Copyright (C) Paul Mackerras 2005
10 * Copyright (C) Egbert Eich 2003,2004
11 * Copyright (C) Dave Airlie 2005
12 * All Rights Reserved.
13 *
14 * Permission is hereby granted, free of charge, to any person obtaining a
15 * copy of this software and associated documentation files (the "Software"),
16 * to deal in the Software without restriction, including without limitation
17 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
18 * and/or sell copies of the Software, and to permit persons to whom the
19 * Software is furnished to do so, subject to the following conditions:
20 *
21 * The above copyright notice and this permission notice (including the next
22 * paragraph) shall be included in all copies or substantial portions of the
23 * Software.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
26 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
27 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
28 * THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
29 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
30 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 * IN THE SOFTWARE.
32 */
33#include <linux/compat.h>
34#include <linux/ioctl32.h>
35
36#include "drmP.h"
37#include "drm.h"
38#include "mga_drm.h"
39
40typedef struct drm32_mga_init {
41 int func;
42 u32 sarea_priv_offset;
43 int chipset;
44 int sgram;
45 unsigned int maccess;
46 unsigned int fb_cpp;
47 unsigned int front_offset, front_pitch;
48 unsigned int back_offset, back_pitch;
49 unsigned int depth_cpp;
50 unsigned int depth_offset, depth_pitch;
51 unsigned int texture_offset[MGA_NR_TEX_HEAPS];
52 unsigned int texture_size[MGA_NR_TEX_HEAPS];
53 u32 fb_offset;
54 u32 mmio_offset;
55 u32 status_offset;
56 u32 warp_offset;
57 u32 primary_offset;
58 u32 buffers_offset;
59} drm_mga_init32_t;
60
61static int compat_mga_init(struct file *file, unsigned int cmd,
62 unsigned long arg)
63{
64 drm_mga_init32_t init32;
65 drm_mga_init_t __user *init;
66 int err = 0, i;
67
68 if (copy_from_user(&init32, (void __user *)arg, sizeof(init32)))
69 return -EFAULT;
70
71 init = compat_alloc_user_space(sizeof(*init));
72 if (!access_ok(VERIFY_WRITE, init, sizeof(*init))
73 || __put_user(init32.func, &init->func)
74 || __put_user(init32.sarea_priv_offset, &init->sarea_priv_offset)
75 || __put_user(init32.chipset, &init->chipset)
76 || __put_user(init32.sgram, &init->sgram)
77 || __put_user(init32.maccess, &init->maccess)
78 || __put_user(init32.fb_cpp, &init->fb_cpp)
79 || __put_user(init32.front_offset, &init->front_offset)
80 || __put_user(init32.front_pitch, &init->front_pitch)
81 || __put_user(init32.back_offset, &init->back_offset)
82 || __put_user(init32.back_pitch, &init->back_pitch)
83 || __put_user(init32.depth_cpp, &init->depth_cpp)
84 || __put_user(init32.depth_offset, &init->depth_offset)
85 || __put_user(init32.depth_pitch, &init->depth_pitch)
86 || __put_user(init32.fb_offset, &init->fb_offset)
87 || __put_user(init32.mmio_offset, &init->mmio_offset)
88 || __put_user(init32.status_offset, &init->status_offset)
89 || __put_user(init32.warp_offset, &init->warp_offset)
90 || __put_user(init32.primary_offset, &init->primary_offset)
91 || __put_user(init32.buffers_offset, &init->buffers_offset))
92 return -EFAULT;
93
94 for (i=0; i<MGA_NR_TEX_HEAPS; i++)
95 {
96 err |= __put_user(init32.texture_offset[i], &init->texture_offset[i]);
97 err |= __put_user(init32.texture_size[i], &init->texture_size[i]);
98 }
99 if (err)
100 return -EFAULT;
101
102 return drm_ioctl(file->f_dentry->d_inode, file,
103 DRM_IOCTL_MGA_INIT, (unsigned long) init);
104}
105
106
107typedef struct drm_mga_getparam32 {
108 int param;
109 u32 value;
110} drm_mga_getparam32_t;
111
112
113static int compat_mga_getparam(struct file *file, unsigned int cmd,
114 unsigned long arg)
115{
116 drm_mga_getparam32_t getparam32;
117 drm_mga_getparam_t __user *getparam;
118
119 if (copy_from_user(&getparam32, (void __user *)arg, sizeof(getparam32)))
120 return -EFAULT;
121
122 getparam = compat_alloc_user_space(sizeof(*getparam));
123 if (!access_ok(VERIFY_WRITE, getparam, sizeof(*getparam))
124 || __put_user(getparam32.param, &getparam->param)
125 || __put_user((void __user *)(unsigned long)getparam32.value, &getparam->value))
126 return -EFAULT;
127
128 return drm_ioctl(file->f_dentry->d_inode, file,
129 DRM_IOCTL_MGA_GETPARAM, (unsigned long)getparam);
130}
131
132drm_ioctl_compat_t *mga_compat_ioctls[] = {
133 [DRM_MGA_INIT] = compat_mga_init,
134 [DRM_MGA_GETPARAM] = compat_mga_getparam,
135};
136
137/**
138 * Called whenever a 32-bit process running under a 64-bit kernel
139 * performs an ioctl on /dev/dri/card<n>.
140 *
141 * \param filp file pointer.
142 * \param cmd command.
143 * \param arg user argument.
144 * \return zero on success or negative number on failure.
145 */
146long mga_compat_ioctl(struct file *filp, unsigned int cmd,
147 unsigned long arg)
148{
149 unsigned int nr = DRM_IOCTL_NR(cmd);
150 drm_ioctl_compat_t *fn = NULL;
151 int ret;
152
153 if (nr < DRM_COMMAND_BASE)
154 return drm_compat_ioctl(filp, cmd, arg);
155
156 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(mga_compat_ioctls))
157 fn = mga_compat_ioctls[nr - DRM_COMMAND_BASE];
158
159 lock_kernel(); /* XXX for now */
160 if (fn != NULL)
161 ret = (*fn)(filp, cmd, arg);
162 else
163 ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg);
164 unlock_kernel();
165
166 return ret;
167}
diff --git a/drivers/char/drm/r128_drv.c b/drivers/char/drm/r128_drv.c
index ced63810237b..bc446da1b210 100644
--- a/drivers/char/drm/r128_drv.c
+++ b/drivers/char/drm/r128_drv.c
@@ -96,6 +96,9 @@ static struct drm_driver driver = {
96 .mmap = drm_mmap, 96 .mmap = drm_mmap,
97 .poll = drm_poll, 97 .poll = drm_poll,
98 .fasync = drm_fasync, 98 .fasync = drm_fasync,
99#ifdef CONFIG_COMPAT
100 .compat_ioctl = r128_compat_ioctl,
101#endif
99 }, 102 },
100 .pci_driver = { 103 .pci_driver = {
101 .name = DRIVER_NAME, 104 .name = DRIVER_NAME,
diff --git a/drivers/char/drm/r128_drv.h b/drivers/char/drm/r128_drv.h
index cf1aa5df459e..0fb687c9505e 100644
--- a/drivers/char/drm/r128_drv.h
+++ b/drivers/char/drm/r128_drv.h
@@ -156,6 +156,9 @@ extern void r128_driver_irq_uninstall( drm_device_t *dev );
156extern void r128_driver_pretakedown(drm_device_t *dev); 156extern void r128_driver_pretakedown(drm_device_t *dev);
157extern void r128_driver_prerelease(drm_device_t *dev, DRMFILE filp); 157extern void r128_driver_prerelease(drm_device_t *dev, DRMFILE filp);
158 158
159extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
160 unsigned long arg);
161
159/* Register definitions, register access macros and drmAddMap constants 162/* Register definitions, register access macros and drmAddMap constants
160 * for Rage 128 kernel driver. 163 * for Rage 128 kernel driver.
161 */ 164 */
diff --git a/drivers/char/drm/r128_ioc32.c b/drivers/char/drm/r128_ioc32.c
new file mode 100644
index 000000000000..60598ef9475a
--- /dev/null
+++ b/drivers/char/drm/r128_ioc32.c
@@ -0,0 +1,219 @@
1/**
2 * \file r128_ioc32.c
3 *
4 * 32-bit ioctl compatibility routines for the R128 DRM.
5 *
6 * \author Dave Airlie <airlied@linux.ie> with code from patches by Egbert Eich
7 *
8 * Copyright (C) Paul Mackerras 2005
9 * Copyright (C) Egbert Eich 2003,2004
10 * Copyright (C) Dave Airlie 2005
11 * All Rights Reserved.
12 *
13 * Permission is hereby granted, free of charge, to any person obtaining a
14 * copy of this software and associated documentation files (the "Software"),
15 * to deal in the Software without restriction, including without limitation
16 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
17 * and/or sell copies of the Software, and to permit persons to whom the
18 * Software is furnished to do so, subject to the following conditions:
19 *
20 * The above copyright notice and this permission notice (including the next
21 * paragraph) shall be included in all copies or substantial portions of the
22 * Software.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
25 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
26 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
27 * THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
28 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
29 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 * IN THE SOFTWARE.
31 */
32#include <linux/compat.h>
33#include <linux/ioctl32.h>
34
35#include "drmP.h"
36#include "drm.h"
37#include "r128_drm.h"
38
39typedef struct drm_r128_init32 {
40 int func;
41 unsigned int sarea_priv_offset;
42 int is_pci;
43 int cce_mode;
44 int cce_secure;
45 int ring_size;
46 int usec_timeout;
47
48 unsigned int fb_bpp;
49 unsigned int front_offset, front_pitch;
50 unsigned int back_offset, back_pitch;
51 unsigned int depth_bpp;
52 unsigned int depth_offset, depth_pitch;
53 unsigned int span_offset;
54
55 unsigned int fb_offset;
56 unsigned int mmio_offset;
57 unsigned int ring_offset;
58 unsigned int ring_rptr_offset;
59 unsigned int buffers_offset;
60 unsigned int agp_textures_offset;
61} drm_r128_init32_t;
62
63static int compat_r128_init(struct file *file, unsigned int cmd,
64 unsigned long arg)
65{
66 drm_r128_init32_t init32;
67 drm_r128_init_t __user *init;
68
69 if (copy_from_user(&init32, (void __user *)arg, sizeof(init32)))
70 return -EFAULT;
71
72 init = compat_alloc_user_space(sizeof(*init));
73 if (!access_ok(VERIFY_WRITE, init, sizeof(*init))
74 || __put_user(init32.func, &init->func)
75 || __put_user(init32.sarea_priv_offset, &init->sarea_priv_offset)
76 || __put_user(init32.is_pci, &init->is_pci)
77 || __put_user(init32.cce_mode, &init->cce_mode)
78 || __put_user(init32.cce_secure, &init->cce_secure)
79 || __put_user(init32.ring_size, &init->ring_size)
80 || __put_user(init32.usec_timeout, &init->usec_timeout)
81 || __put_user(init32.fb_bpp, &init->fb_bpp)
82 || __put_user(init32.front_offset, &init->front_offset)
83 || __put_user(init32.front_pitch, &init->front_pitch)
84 || __put_user(init32.back_offset, &init->back_offset)
85 || __put_user(init32.back_pitch, &init->back_pitch)
86 || __put_user(init32.depth_bpp, &init->depth_bpp)
87 || __put_user(init32.depth_offset, &init->depth_offset)
88 || __put_user(init32.depth_pitch, &init->depth_pitch)
89 || __put_user(init32.span_offset, &init->span_offset)
90 || __put_user(init32.fb_offset, &init->fb_offset)
91 || __put_user(init32.mmio_offset, &init->mmio_offset)
92 || __put_user(init32.ring_offset, &init->ring_offset)
93 || __put_user(init32.ring_rptr_offset, &init->ring_rptr_offset)
94 || __put_user(init32.buffers_offset, &init->buffers_offset)
95 || __put_user(init32.agp_textures_offset, &init->agp_textures_offset))
96 return -EFAULT;
97
98 return drm_ioctl(file->f_dentry->d_inode, file,
99 DRM_IOCTL_R128_INIT, (unsigned long)init);
100}
101
102
103typedef struct drm_r128_depth32 {
104 int func;
105 int n;
106 u32 x;
107 u32 y;
108 u32 buffer;
109 u32 mask;
110} drm_r128_depth32_t;
111
112static int compat_r128_depth(struct file *file, unsigned int cmd,
113 unsigned long arg)
114{
115 drm_r128_depth32_t depth32;
116 drm_r128_depth_t __user *depth;
117
118 if (copy_from_user(&depth32, (void __user *)arg, sizeof(depth32)))
119 return -EFAULT;
120
121 depth = compat_alloc_user_space(sizeof(*depth));
122 if (!access_ok(VERIFY_WRITE, depth, sizeof(*depth))
123 || __put_user(depth32.func, &depth->func)
124 || __put_user(depth32.n, &depth->n)
125 || __put_user((int __user *)(unsigned long)depth32.x, &depth->x)
126 || __put_user((int __user *)(unsigned long)depth32.y, &depth->y)
127 || __put_user((unsigned int __user *)(unsigned long)depth32.buffer, &depth->buffer)
128 || __put_user((unsigned char __user *)(unsigned long)depth32.mask, &depth->mask))
129 return -EFAULT;
130
131 return drm_ioctl(file->f_dentry->d_inode, file,
132 DRM_IOCTL_R128_DEPTH, (unsigned long)depth);
133
134}
135
136typedef struct drm_r128_stipple32 {
137 u32 mask;
138} drm_r128_stipple32_t;
139
140static int compat_r128_stipple(struct file *file, unsigned int cmd,
141 unsigned long arg)
142{
143 drm_r128_stipple32_t stipple32;
144 drm_r128_stipple_t __user *stipple;
145
146 if (copy_from_user(&stipple32, (void __user *)arg, sizeof(stipple32)))
147 return -EFAULT;
148
149 stipple = compat_alloc_user_space(sizeof(*stipple));
150 if (!access_ok(VERIFY_WRITE, stipple, sizeof(*stipple))
151 || __put_user((unsigned int __user *)(unsigned long)stipple32.mask, &stipple->mask))
152 return -EFAULT;
153
154 return drm_ioctl(file->f_dentry->d_inode, file,
155 DRM_IOCTL_R128_STIPPLE, (unsigned long)stipple);
156}
157
158typedef struct drm_r128_getparam32 {
159 int param;
160 u32 value;
161} drm_r128_getparam32_t;
162
163static int compat_r128_getparam(struct file *file, unsigned int cmd,
164 unsigned long arg)
165{
166 drm_r128_getparam32_t getparam32;
167 drm_r128_getparam_t __user *getparam;
168
169 if (copy_from_user(&getparam32, (void __user *)arg, sizeof(getparam32)))
170 return -EFAULT;
171
172 getparam = compat_alloc_user_space(sizeof(*getparam));
173 if (!access_ok(VERIFY_WRITE, getparam, sizeof(*getparam))
174 || __put_user(getparam32.param, &getparam->param)
175 || __put_user((void __user *)(unsigned long)getparam32.value, &getparam->value))
176 return -EFAULT;
177
178 return drm_ioctl(file->f_dentry->d_inode, file,
179 DRM_IOCTL_R128_GETPARAM, (unsigned long)getparam);
180}
181
182drm_ioctl_compat_t *r128_compat_ioctls[] = {
183 [DRM_R128_INIT] = compat_r128_init,
184 [DRM_R128_DEPTH] = compat_r128_depth,
185 [DRM_R128_STIPPLE] = compat_r128_stipple,
186 [DRM_R128_GETPARAM] = compat_r128_getparam,
187};
188
189/**
190 * Called whenever a 32-bit process running under a 64-bit kernel
191 * performs an ioctl on /dev/dri/card<n>.
192 *
193 * \param filp file pointer.
194 * \param cmd command.
195 * \param arg user argument.
196 * \return zero on success or negative number on failure.
197 */
198long r128_compat_ioctl(struct file *filp, unsigned int cmd,
199 unsigned long arg)
200{
201 unsigned int nr = DRM_IOCTL_NR(cmd);
202 drm_ioctl_compat_t *fn = NULL;
203 int ret;
204
205 if (nr < DRM_COMMAND_BASE)
206 return drm_compat_ioctl(filp, cmd, arg);
207
208 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(r128_compat_ioctls))
209 fn = r128_compat_ioctls[nr - DRM_COMMAND_BASE];
210
211 lock_kernel(); /* XXX for now */
212 if (fn != NULL)
213 ret = (*fn)(filp, cmd, arg);
214 else
215 ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg);
216 unlock_kernel();
217
218 return ret;
219}
diff --git a/drivers/char/drm/r128_state.c b/drivers/char/drm/r128_state.c
index 53af69162829..426a71c049d9 100644
--- a/drivers/char/drm/r128_state.c
+++ b/drivers/char/drm/r128_state.c
@@ -1307,7 +1307,7 @@ static int r128_do_init_pageflip( drm_device_t *dev )
1307 return 0; 1307 return 0;
1308} 1308}
1309 1309
1310int r128_do_cleanup_pageflip( drm_device_t *dev ) 1310static int r128_do_cleanup_pageflip( drm_device_t *dev )
1311{ 1311{
1312 drm_r128_private_t *dev_priv = dev->dev_private; 1312 drm_r128_private_t *dev_priv = dev->dev_private;
1313 DRM_DEBUG( "\n" ); 1313 DRM_DEBUG( "\n" );
diff --git a/drivers/char/drm/via_3d_reg.h b/drivers/char/drm/via_3d_reg.h
new file mode 100644
index 000000000000..cf61bb514db1
--- /dev/null
+++ b/drivers/char/drm/via_3d_reg.h
@@ -0,0 +1,1651 @@
1/*
2 * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef VIA_3D_REG_H
26#define VIA_3D_REG_H
27#define HC_REG_BASE 0x0400
28
29#define HC_REG_TRANS_SPACE 0x0040
30
31#define HC_ParaN_MASK 0xffffffff
32#define HC_Para_MASK 0x00ffffff
33#define HC_SubA_MASK 0xff000000
34#define HC_SubA_SHIFT 24
35/* Transmission Setting
36 */
37#define HC_REG_TRANS_SET 0x003c
38#define HC_ParaSubType_MASK 0xff000000
39#define HC_ParaType_MASK 0x00ff0000
40#define HC_ParaOS_MASK 0x0000ff00
41#define HC_ParaAdr_MASK 0x000000ff
42#define HC_ParaSubType_SHIFT 24
43#define HC_ParaType_SHIFT 16
44#define HC_ParaOS_SHIFT 8
45#define HC_ParaAdr_SHIFT 0
46
47#define HC_ParaType_CmdVdata 0x0000
48#define HC_ParaType_NotTex 0x0001
49#define HC_ParaType_Tex 0x0002
50#define HC_ParaType_Palette 0x0003
51#define HC_ParaType_PreCR 0x0010
52#define HC_ParaType_Auto 0x00fe
53
54/* Transmission Space
55 */
56#define HC_REG_Hpara0 0x0040
57#define HC_REG_HpataAF 0x02fc
58
59/* Read
60 */
61#define HC_REG_HREngSt 0x0000
62#define HC_REG_HRFIFOempty 0x0004
63#define HC_REG_HRFIFOfull 0x0008
64#define HC_REG_HRErr 0x000c
65#define HC_REG_FIFOstatus 0x0010
66/* HC_REG_HREngSt 0x0000
67 */
68#define HC_HDASZC_MASK 0x00010000
69#define HC_HSGEMI_MASK 0x0000f000
70#define HC_HLGEMISt_MASK 0x00000f00
71#define HC_HCRSt_MASK 0x00000080
72#define HC_HSE0St_MASK 0x00000040
73#define HC_HSE1St_MASK 0x00000020
74#define HC_HPESt_MASK 0x00000010
75#define HC_HXESt_MASK 0x00000008
76#define HC_HBESt_MASK 0x00000004
77#define HC_HE2St_MASK 0x00000002
78#define HC_HE3St_MASK 0x00000001
79/* HC_REG_HRFIFOempty 0x0004
80 */
81#define HC_HRZDempty_MASK 0x00000010
82#define HC_HRTXAempty_MASK 0x00000008
83#define HC_HRTXDempty_MASK 0x00000004
84#define HC_HWZDempty_MASK 0x00000002
85#define HC_HWCDempty_MASK 0x00000001
86/* HC_REG_HRFIFOfull 0x0008
87 */
88#define HC_HRZDfull_MASK 0x00000010
89#define HC_HRTXAfull_MASK 0x00000008
90#define HC_HRTXDfull_MASK 0x00000004
91#define HC_HWZDfull_MASK 0x00000002
92#define HC_HWCDfull_MASK 0x00000001
93/* HC_REG_HRErr 0x000c
94 */
95#define HC_HAGPCMErr_MASK 0x80000000
96#define HC_HAGPCMErrC_MASK 0x70000000
97/* HC_REG_FIFOstatus 0x0010
98 */
99#define HC_HRFIFOATall_MASK 0x80000000
100#define HC_HRFIFOATbusy_MASK 0x40000000
101#define HC_HRATFGMDo_MASK 0x00000100
102#define HC_HRATFGMDi_MASK 0x00000080
103#define HC_HRATFRZD_MASK 0x00000040
104#define HC_HRATFRTXA_MASK 0x00000020
105#define HC_HRATFRTXD_MASK 0x00000010
106#define HC_HRATFWZD_MASK 0x00000008
107#define HC_HRATFWCD_MASK 0x00000004
108#define HC_HRATTXTAG_MASK 0x00000002
109#define HC_HRATTXCH_MASK 0x00000001
110
111/* AGP Command Setting
112 */
113#define HC_SubA_HAGPBstL 0x0060
114#define HC_SubA_HAGPBendL 0x0061
115#define HC_SubA_HAGPCMNT 0x0062
116#define HC_SubA_HAGPBpL 0x0063
117#define HC_SubA_HAGPBpH 0x0064
118/* HC_SubA_HAGPCMNT 0x0062
119 */
120#define HC_HAGPCMNT_MASK 0x00800000
121#define HC_HCmdErrClr_MASK 0x00400000
122#define HC_HAGPBendH_MASK 0x0000ff00
123#define HC_HAGPBstH_MASK 0x000000ff
124#define HC_HAGPBendH_SHIFT 8
125#define HC_HAGPBstH_SHIFT 0
126/* HC_SubA_HAGPBpL 0x0063
127 */
128#define HC_HAGPBpL_MASK 0x00fffffc
129#define HC_HAGPBpID_MASK 0x00000003
130#define HC_HAGPBpID_PAUSE 0x00000000
131#define HC_HAGPBpID_JUMP 0x00000001
132#define HC_HAGPBpID_STOP 0x00000002
133/* HC_SubA_HAGPBpH 0x0064
134 */
135#define HC_HAGPBpH_MASK 0x00ffffff
136
137/* Miscellaneous Settings
138 */
139#define HC_SubA_HClipTB 0x0070
140#define HC_SubA_HClipLR 0x0071
141#define HC_SubA_HFPClipTL 0x0072
142#define HC_SubA_HFPClipBL 0x0073
143#define HC_SubA_HFPClipLL 0x0074
144#define HC_SubA_HFPClipRL 0x0075
145#define HC_SubA_HFPClipTBH 0x0076
146#define HC_SubA_HFPClipLRH 0x0077
147#define HC_SubA_HLP 0x0078
148#define HC_SubA_HLPRF 0x0079
149#define HC_SubA_HSolidCL 0x007a
150#define HC_SubA_HPixGC 0x007b
151#define HC_SubA_HSPXYOS 0x007c
152#define HC_SubA_HVertexCNT 0x007d
153
154#define HC_HClipT_MASK 0x00fff000
155#define HC_HClipT_SHIFT 12
156#define HC_HClipB_MASK 0x00000fff
157#define HC_HClipB_SHIFT 0
158#define HC_HClipL_MASK 0x00fff000
159#define HC_HClipL_SHIFT 12
160#define HC_HClipR_MASK 0x00000fff
161#define HC_HClipR_SHIFT 0
162#define HC_HFPClipBH_MASK 0x0000ff00
163#define HC_HFPClipBH_SHIFT 8
164#define HC_HFPClipTH_MASK 0x000000ff
165#define HC_HFPClipTH_SHIFT 0
166#define HC_HFPClipRH_MASK 0x0000ff00
167#define HC_HFPClipRH_SHIFT 8
168#define HC_HFPClipLH_MASK 0x000000ff
169#define HC_HFPClipLH_SHIFT 0
170#define HC_HSolidCH_MASK 0x000000ff
171#define HC_HPixGC_MASK 0x00800000
172#define HC_HSPXOS_MASK 0x00fff000
173#define HC_HSPXOS_SHIFT 12
174#define HC_HSPYOS_MASK 0x00000fff
175
176/* Command
177 * Command A
178 */
179#define HC_HCmdHeader_MASK 0xfe000000 /*0xffe00000 */
180#define HC_HE3Fire_MASK 0x00100000
181#define HC_HPMType_MASK 0x000f0000
182#define HC_HEFlag_MASK 0x0000e000
183#define HC_HShading_MASK 0x00001c00
184#define HC_HPMValidN_MASK 0x00000200
185#define HC_HPLEND_MASK 0x00000100
186#define HC_HVCycle_MASK 0x000000ff
187#define HC_HVCycle_Style_MASK 0x000000c0
188#define HC_HVCycle_ChgA_MASK 0x00000030
189#define HC_HVCycle_ChgB_MASK 0x0000000c
190#define HC_HVCycle_ChgC_MASK 0x00000003
191#define HC_HPMType_Point 0x00000000
192#define HC_HPMType_Line 0x00010000
193#define HC_HPMType_Tri 0x00020000
194#define HC_HPMType_TriWF 0x00040000
195#define HC_HEFlag_NoAA 0x00000000
196#define HC_HEFlag_ab 0x00008000
197#define HC_HEFlag_bc 0x00004000
198#define HC_HEFlag_ca 0x00002000
199#define HC_HShading_Solid 0x00000000
200#define HC_HShading_FlatA 0x00000400
201#define HC_HShading_FlatB 0x00000800
202#define HC_HShading_FlatC 0x00000c00
203#define HC_HShading_Gouraud 0x00001000
204#define HC_HVCycle_Full 0x00000000
205#define HC_HVCycle_AFP 0x00000040
206#define HC_HVCycle_One 0x000000c0
207#define HC_HVCycle_NewA 0x00000000
208#define HC_HVCycle_AA 0x00000010
209#define HC_HVCycle_AB 0x00000020
210#define HC_HVCycle_AC 0x00000030
211#define HC_HVCycle_NewB 0x00000000
212#define HC_HVCycle_BA 0x00000004
213#define HC_HVCycle_BB 0x00000008
214#define HC_HVCycle_BC 0x0000000c
215#define HC_HVCycle_NewC 0x00000000
216#define HC_HVCycle_CA 0x00000001
217#define HC_HVCycle_CB 0x00000002
218#define HC_HVCycle_CC 0x00000003
219
220/* Command B
221 */
222#define HC_HLPrst_MASK 0x00010000
223#define HC_HLLastP_MASK 0x00008000
224#define HC_HVPMSK_MASK 0x00007f80
225#define HC_HBFace_MASK 0x00000040
226#define HC_H2nd1VT_MASK 0x0000003f
227#define HC_HVPMSK_X 0x00004000
228#define HC_HVPMSK_Y 0x00002000
229#define HC_HVPMSK_Z 0x00001000
230#define HC_HVPMSK_W 0x00000800
231#define HC_HVPMSK_Cd 0x00000400
232#define HC_HVPMSK_Cs 0x00000200
233#define HC_HVPMSK_S 0x00000100
234#define HC_HVPMSK_T 0x00000080
235
236/* Enable Setting
237 */
238#define HC_SubA_HEnable 0x0000
239#define HC_HenTXEnvMap_MASK 0x00200000
240#define HC_HenVertexCNT_MASK 0x00100000
241#define HC_HenCPUDAZ_MASK 0x00080000
242#define HC_HenDASZWC_MASK 0x00040000
243#define HC_HenFBCull_MASK 0x00020000
244#define HC_HenCW_MASK 0x00010000
245#define HC_HenAA_MASK 0x00008000
246#define HC_HenST_MASK 0x00004000
247#define HC_HenZT_MASK 0x00002000
248#define HC_HenZW_MASK 0x00001000
249#define HC_HenAT_MASK 0x00000800
250#define HC_HenAW_MASK 0x00000400
251#define HC_HenSP_MASK 0x00000200
252#define HC_HenLP_MASK 0x00000100
253#define HC_HenTXCH_MASK 0x00000080
254#define HC_HenTXMP_MASK 0x00000040
255#define HC_HenTXPP_MASK 0x00000020
256#define HC_HenTXTR_MASK 0x00000010
257#define HC_HenCS_MASK 0x00000008
258#define HC_HenFOG_MASK 0x00000004
259#define HC_HenABL_MASK 0x00000002
260#define HC_HenDT_MASK 0x00000001
261
262/* Z Setting
263 */
264#define HC_SubA_HZWBBasL 0x0010
265#define HC_SubA_HZWBBasH 0x0011
266#define HC_SubA_HZWBType 0x0012
267#define HC_SubA_HZBiasL 0x0013
268#define HC_SubA_HZWBend 0x0014
269#define HC_SubA_HZWTMD 0x0015
270#define HC_SubA_HZWCDL 0x0016
271#define HC_SubA_HZWCTAGnum 0x0017
272#define HC_SubA_HZCYNum 0x0018
273#define HC_SubA_HZWCFire 0x0019
274/* HC_SubA_HZWBType
275 */
276#define HC_HZWBType_MASK 0x00800000
277#define HC_HZBiasedWB_MASK 0x00400000
278#define HC_HZONEasFF_MASK 0x00200000
279#define HC_HZOONEasFF_MASK 0x00100000
280#define HC_HZWBFM_MASK 0x00030000
281#define HC_HZWBLoc_MASK 0x0000c000
282#define HC_HZWBPit_MASK 0x00003fff
283#define HC_HZWBFM_16 0x00000000
284#define HC_HZWBFM_32 0x00020000
285#define HC_HZWBFM_24 0x00030000
286#define HC_HZWBLoc_Local 0x00000000
287#define HC_HZWBLoc_SyS 0x00004000
288/* HC_SubA_HZWBend
289 */
290#define HC_HZWBend_MASK 0x00ffe000
291#define HC_HZBiasH_MASK 0x000000ff
292#define HC_HZWBend_SHIFT 10
293/* HC_SubA_HZWTMD
294 */
295#define HC_HZWTMD_MASK 0x00070000
296#define HC_HEBEBias_MASK 0x00007f00
297#define HC_HZNF_MASK 0x000000ff
298#define HC_HZWTMD_NeverPass 0x00000000
299#define HC_HZWTMD_LT 0x00010000
300#define HC_HZWTMD_EQ 0x00020000
301#define HC_HZWTMD_LE 0x00030000
302#define HC_HZWTMD_GT 0x00040000
303#define HC_HZWTMD_NE 0x00050000
304#define HC_HZWTMD_GE 0x00060000
305#define HC_HZWTMD_AllPass 0x00070000
306#define HC_HEBEBias_SHIFT 8
307/* HC_SubA_HZWCDL 0x0016
308 */
309#define HC_HZWCDL_MASK 0x00ffffff
310/* HC_SubA_HZWCTAGnum 0x0017
311 */
312#define HC_HZWCTAGnum_MASK 0x00ff0000
313#define HC_HZWCTAGnum_SHIFT 16
314#define HC_HZWCDH_MASK 0x000000ff
315#define HC_HZWCDH_SHIFT 0
316/* HC_SubA_HZCYNum 0x0018
317 */
318#define HC_HZCYNum_MASK 0x00030000
319#define HC_HZCYNum_SHIFT 16
320#define HC_HZWCQWnum_MASK 0x00003fff
321#define HC_HZWCQWnum_SHIFT 0
322/* HC_SubA_HZWCFire 0x0019
323 */
324#define HC_ZWCFire_MASK 0x00010000
325#define HC_HZWCQWnumLast_MASK 0x00003fff
326#define HC_HZWCQWnumLast_SHIFT 0
327
328/* Stencil Setting
329 */
330#define HC_SubA_HSTREF 0x0023
331#define HC_SubA_HSTMD 0x0024
332/* HC_SubA_HSBFM
333 */
334#define HC_HSBFM_MASK 0x00030000
335#define HC_HSBLoc_MASK 0x0000c000
336#define HC_HSBPit_MASK 0x00003fff
337/* HC_SubA_HSTREF
338 */
339#define HC_HSTREF_MASK 0x00ff0000
340#define HC_HSTOPMSK_MASK 0x0000ff00
341#define HC_HSTBMSK_MASK 0x000000ff
342#define HC_HSTREF_SHIFT 16
343#define HC_HSTOPMSK_SHIFT 8
344/* HC_SubA_HSTMD
345 */
346#define HC_HSTMD_MASK 0x00070000
347#define HC_HSTOPSF_MASK 0x000001c0
348#define HC_HSTOPSPZF_MASK 0x00000038
349#define HC_HSTOPSPZP_MASK 0x00000007
350#define HC_HSTMD_NeverPass 0x00000000
351#define HC_HSTMD_LT 0x00010000
352#define HC_HSTMD_EQ 0x00020000
353#define HC_HSTMD_LE 0x00030000
354#define HC_HSTMD_GT 0x00040000
355#define HC_HSTMD_NE 0x00050000
356#define HC_HSTMD_GE 0x00060000
357#define HC_HSTMD_AllPass 0x00070000
358#define HC_HSTOPSF_KEEP 0x00000000
359#define HC_HSTOPSF_ZERO 0x00000040
360#define HC_HSTOPSF_REPLACE 0x00000080
361#define HC_HSTOPSF_INCRSAT 0x000000c0
362#define HC_HSTOPSF_DECRSAT 0x00000100
363#define HC_HSTOPSF_INVERT 0x00000140
364#define HC_HSTOPSF_INCR 0x00000180
365#define HC_HSTOPSF_DECR 0x000001c0
366#define HC_HSTOPSPZF_KEEP 0x00000000
367#define HC_HSTOPSPZF_ZERO 0x00000008
368#define HC_HSTOPSPZF_REPLACE 0x00000010
369#define HC_HSTOPSPZF_INCRSAT 0x00000018
370#define HC_HSTOPSPZF_DECRSAT 0x00000020
371#define HC_HSTOPSPZF_INVERT 0x00000028
372#define HC_HSTOPSPZF_INCR 0x00000030
373#define HC_HSTOPSPZF_DECR 0x00000038
374#define HC_HSTOPSPZP_KEEP 0x00000000
375#define HC_HSTOPSPZP_ZERO 0x00000001
376#define HC_HSTOPSPZP_REPLACE 0x00000002
377#define HC_HSTOPSPZP_INCRSAT 0x00000003
378#define HC_HSTOPSPZP_DECRSAT 0x00000004
379#define HC_HSTOPSPZP_INVERT 0x00000005
380#define HC_HSTOPSPZP_INCR 0x00000006
381#define HC_HSTOPSPZP_DECR 0x00000007
382
383/* Alpha Setting
384 */
385#define HC_SubA_HABBasL 0x0030
386#define HC_SubA_HABBasH 0x0031
387#define HC_SubA_HABFM 0x0032
388#define HC_SubA_HATMD 0x0033
389#define HC_SubA_HABLCsat 0x0034
390#define HC_SubA_HABLCop 0x0035
391#define HC_SubA_HABLAsat 0x0036
392#define HC_SubA_HABLAop 0x0037
393#define HC_SubA_HABLRCa 0x0038
394#define HC_SubA_HABLRFCa 0x0039
395#define HC_SubA_HABLRCbias 0x003a
396#define HC_SubA_HABLRCb 0x003b
397#define HC_SubA_HABLRFCb 0x003c
398#define HC_SubA_HABLRAa 0x003d
399#define HC_SubA_HABLRAb 0x003e
400/* HC_SubA_HABFM
401 */
402#define HC_HABFM_MASK 0x00030000
403#define HC_HABLoc_MASK 0x0000c000
404#define HC_HABPit_MASK 0x000007ff
405/* HC_SubA_HATMD
406 */
407#define HC_HATMD_MASK 0x00000700
408#define HC_HATREF_MASK 0x000000ff
409#define HC_HATMD_NeverPass 0x00000000
410#define HC_HATMD_LT 0x00000100
411#define HC_HATMD_EQ 0x00000200
412#define HC_HATMD_LE 0x00000300
413#define HC_HATMD_GT 0x00000400
414#define HC_HATMD_NE 0x00000500
415#define HC_HATMD_GE 0x00000600
416#define HC_HATMD_AllPass 0x00000700
417/* HC_SubA_HABLCsat
418 */
419#define HC_HABLCsat_MASK 0x00010000
420#define HC_HABLCa_MASK 0x0000fc00
421#define HC_HABLCa_C_MASK 0x0000c000
422#define HC_HABLCa_OPC_MASK 0x00003c00
423#define HC_HABLFCa_MASK 0x000003f0
424#define HC_HABLFCa_C_MASK 0x00000300
425#define HC_HABLFCa_OPC_MASK 0x000000f0
426#define HC_HABLCbias_MASK 0x0000000f
427#define HC_HABLCbias_C_MASK 0x00000008
428#define HC_HABLCbias_OPC_MASK 0x00000007
429/*-- Define the input color.
430 */
431#define HC_XC_Csrc 0x00000000
432#define HC_XC_Cdst 0x00000001
433#define HC_XC_Asrc 0x00000002
434#define HC_XC_Adst 0x00000003
435#define HC_XC_Fog 0x00000004
436#define HC_XC_HABLRC 0x00000005
437#define HC_XC_minSrcDst 0x00000006
438#define HC_XC_maxSrcDst 0x00000007
439#define HC_XC_mimAsrcInvAdst 0x00000008
440#define HC_XC_OPC 0x00000000
441#define HC_XC_InvOPC 0x00000010
442#define HC_XC_OPCp5 0x00000020
443/*-- Define the input Alpha
444 */
445#define HC_XA_OPA 0x00000000
446#define HC_XA_InvOPA 0x00000010
447#define HC_XA_OPAp5 0x00000020
448#define HC_XA_0 0x00000000
449#define HC_XA_Asrc 0x00000001
450#define HC_XA_Adst 0x00000002
451#define HC_XA_Fog 0x00000003
452#define HC_XA_minAsrcFog 0x00000004
453#define HC_XA_minAsrcAdst 0x00000005
454#define HC_XA_maxAsrcFog 0x00000006
455#define HC_XA_maxAsrcAdst 0x00000007
456#define HC_XA_HABLRA 0x00000008
457#define HC_XA_minAsrcInvAdst 0x00000008
458#define HC_XA_HABLFRA 0x00000009
459/*--
460 */
461#define HC_HABLCa_OPC (HC_XC_OPC << 10)
462#define HC_HABLCa_InvOPC (HC_XC_InvOPC << 10)
463#define HC_HABLCa_OPCp5 (HC_XC_OPCp5 << 10)
464#define HC_HABLCa_Csrc (HC_XC_Csrc << 10)
465#define HC_HABLCa_Cdst (HC_XC_Cdst << 10)
466#define HC_HABLCa_Asrc (HC_XC_Asrc << 10)
467#define HC_HABLCa_Adst (HC_XC_Adst << 10)
468#define HC_HABLCa_Fog (HC_XC_Fog << 10)
469#define HC_HABLCa_HABLRCa (HC_XC_HABLRC << 10)
470#define HC_HABLCa_minSrcDst (HC_XC_minSrcDst << 10)
471#define HC_HABLCa_maxSrcDst (HC_XC_maxSrcDst << 10)
472#define HC_HABLFCa_OPC (HC_XC_OPC << 4)
473#define HC_HABLFCa_InvOPC (HC_XC_InvOPC << 4)
474#define HC_HABLFCa_OPCp5 (HC_XC_OPCp5 << 4)
475#define HC_HABLFCa_Csrc (HC_XC_Csrc << 4)
476#define HC_HABLFCa_Cdst (HC_XC_Cdst << 4)
477#define HC_HABLFCa_Asrc (HC_XC_Asrc << 4)
478#define HC_HABLFCa_Adst (HC_XC_Adst << 4)
479#define HC_HABLFCa_Fog (HC_XC_Fog << 4)
480#define HC_HABLFCa_HABLRCa (HC_XC_HABLRC << 4)
481#define HC_HABLFCa_minSrcDst (HC_XC_minSrcDst << 4)
482#define HC_HABLFCa_maxSrcDst (HC_XC_maxSrcDst << 4)
483#define HC_HABLFCa_mimAsrcInvAdst (HC_XC_mimAsrcInvAdst << 4)
484#define HC_HABLCbias_HABLRCbias 0x00000000
485#define HC_HABLCbias_Asrc 0x00000001
486#define HC_HABLCbias_Adst 0x00000002
487#define HC_HABLCbias_Fog 0x00000003
488#define HC_HABLCbias_Cin 0x00000004
489/* HC_SubA_HABLCop 0x0035
490 */
491#define HC_HABLdot_MASK 0x00010000
492#define HC_HABLCop_MASK 0x00004000
493#define HC_HABLCb_MASK 0x00003f00
494#define HC_HABLCb_C_MASK 0x00003000
495#define HC_HABLCb_OPC_MASK 0x00000f00
496#define HC_HABLFCb_MASK 0x000000fc
497#define HC_HABLFCb_C_MASK 0x000000c0
498#define HC_HABLFCb_OPC_MASK 0x0000003c
499#define HC_HABLCshift_MASK 0x00000003
500#define HC_HABLCb_OPC (HC_XC_OPC << 8)
501#define HC_HABLCb_InvOPC (HC_XC_InvOPC << 8)
502#define HC_HABLCb_OPCp5 (HC_XC_OPCp5 << 8)
503#define HC_HABLCb_Csrc (HC_XC_Csrc << 8)
504#define HC_HABLCb_Cdst (HC_XC_Cdst << 8)
505#define HC_HABLCb_Asrc (HC_XC_Asrc << 8)
506#define HC_HABLCb_Adst (HC_XC_Adst << 8)
507#define HC_HABLCb_Fog (HC_XC_Fog << 8)
508#define HC_HABLCb_HABLRCa (HC_XC_HABLRC << 8)
509#define HC_HABLCb_minSrcDst (HC_XC_minSrcDst << 8)
510#define HC_HABLCb_maxSrcDst (HC_XC_maxSrcDst << 8)
511#define HC_HABLFCb_OPC (HC_XC_OPC << 2)
512#define HC_HABLFCb_InvOPC (HC_XC_InvOPC << 2)
513#define HC_HABLFCb_OPCp5 (HC_XC_OPCp5 << 2)
514#define HC_HABLFCb_Csrc (HC_XC_Csrc << 2)
515#define HC_HABLFCb_Cdst (HC_XC_Cdst << 2)
516#define HC_HABLFCb_Asrc (HC_XC_Asrc << 2)
517#define HC_HABLFCb_Adst (HC_XC_Adst << 2)
518#define HC_HABLFCb_Fog (HC_XC_Fog << 2)
519#define HC_HABLFCb_HABLRCb (HC_XC_HABLRC << 2)
520#define HC_HABLFCb_minSrcDst (HC_XC_minSrcDst << 2)
521#define HC_HABLFCb_maxSrcDst (HC_XC_maxSrcDst << 2)
522#define HC_HABLFCb_mimAsrcInvAdst (HC_XC_mimAsrcInvAdst << 2)
523/* HC_SubA_HABLAsat 0x0036
524 */
525#define HC_HABLAsat_MASK 0x00010000
526#define HC_HABLAa_MASK 0x0000fc00
527#define HC_HABLAa_A_MASK 0x0000c000
528#define HC_HABLAa_OPA_MASK 0x00003c00
529#define HC_HABLFAa_MASK 0x000003f0
530#define HC_HABLFAa_A_MASK 0x00000300
531#define HC_HABLFAa_OPA_MASK 0x000000f0
532#define HC_HABLAbias_MASK 0x0000000f
533#define HC_HABLAbias_A_MASK 0x00000008
534#define HC_HABLAbias_OPA_MASK 0x00000007
535#define HC_HABLAa_OPA (HC_XA_OPA << 10)
536#define HC_HABLAa_InvOPA (HC_XA_InvOPA << 10)
537#define HC_HABLAa_OPAp5 (HC_XA_OPAp5 << 10)
538#define HC_HABLAa_0 (HC_XA_0 << 10)
539#define HC_HABLAa_Asrc (HC_XA_Asrc << 10)
540#define HC_HABLAa_Adst (HC_XA_Adst << 10)
541#define HC_HABLAa_Fog (HC_XA_Fog << 10)
542#define HC_HABLAa_minAsrcFog (HC_XA_minAsrcFog << 10)
543#define HC_HABLAa_minAsrcAdst (HC_XA_minAsrcAdst << 10)
544#define HC_HABLAa_maxAsrcFog (HC_XA_maxAsrcFog << 10)
545#define HC_HABLAa_maxAsrcAdst (HC_XA_maxAsrcAdst << 10)
546#define HC_HABLAa_HABLRA (HC_XA_HABLRA << 10)
547#define HC_HABLFAa_OPA (HC_XA_OPA << 4)
548#define HC_HABLFAa_InvOPA (HC_XA_InvOPA << 4)
549#define HC_HABLFAa_OPAp5 (HC_XA_OPAp5 << 4)
550#define HC_HABLFAa_0 (HC_XA_0 << 4)
551#define HC_HABLFAa_Asrc (HC_XA_Asrc << 4)
552#define HC_HABLFAa_Adst (HC_XA_Adst << 4)
553#define HC_HABLFAa_Fog (HC_XA_Fog << 4)
554#define HC_HABLFAa_minAsrcFog (HC_XA_minAsrcFog << 4)
555#define HC_HABLFAa_minAsrcAdst (HC_XA_minAsrcAdst << 4)
556#define HC_HABLFAa_maxAsrcFog (HC_XA_maxAsrcFog << 4)
557#define HC_HABLFAa_maxAsrcAdst (HC_XA_maxAsrcAdst << 4)
558#define HC_HABLFAa_minAsrcInvAdst (HC_XA_minAsrcInvAdst << 4)
559#define HC_HABLFAa_HABLFRA (HC_XA_HABLFRA << 4)
560#define HC_HABLAbias_HABLRAbias 0x00000000
561#define HC_HABLAbias_Asrc 0x00000001
562#define HC_HABLAbias_Adst 0x00000002
563#define HC_HABLAbias_Fog 0x00000003
564#define HC_HABLAbias_Aaa 0x00000004
565/* HC_SubA_HABLAop 0x0037
566 */
567#define HC_HABLAop_MASK 0x00004000
568#define HC_HABLAb_MASK 0x00003f00
569#define HC_HABLAb_OPA_MASK 0x00000f00
570#define HC_HABLFAb_MASK 0x000000fc
571#define HC_HABLFAb_OPA_MASK 0x0000003c
572#define HC_HABLAshift_MASK 0x00000003
573#define HC_HABLAb_OPA (HC_XA_OPA << 8)
574#define HC_HABLAb_InvOPA (HC_XA_InvOPA << 8)
575#define HC_HABLAb_OPAp5 (HC_XA_OPAp5 << 8)
576#define HC_HABLAb_0 (HC_XA_0 << 8)
577#define HC_HABLAb_Asrc (HC_XA_Asrc << 8)
578#define HC_HABLAb_Adst (HC_XA_Adst << 8)
579#define HC_HABLAb_Fog (HC_XA_Fog << 8)
580#define HC_HABLAb_minAsrcFog (HC_XA_minAsrcFog << 8)
581#define HC_HABLAb_minAsrcAdst (HC_XA_minAsrcAdst << 8)
582#define HC_HABLAb_maxAsrcFog (HC_XA_maxAsrcFog << 8)
583#define HC_HABLAb_maxAsrcAdst (HC_XA_maxAsrcAdst << 8)
584#define HC_HABLAb_HABLRA (HC_XA_HABLRA << 8)
585#define HC_HABLFAb_OPA (HC_XA_OPA << 2)
586#define HC_HABLFAb_InvOPA (HC_XA_InvOPA << 2)
587#define HC_HABLFAb_OPAp5 (HC_XA_OPAp5 << 2)
588#define HC_HABLFAb_0 (HC_XA_0 << 2)
589#define HC_HABLFAb_Asrc (HC_XA_Asrc << 2)
590#define HC_HABLFAb_Adst (HC_XA_Adst << 2)
591#define HC_HABLFAb_Fog (HC_XA_Fog << 2)
592#define HC_HABLFAb_minAsrcFog (HC_XA_minAsrcFog << 2)
593#define HC_HABLFAb_minAsrcAdst (HC_XA_minAsrcAdst << 2)
594#define HC_HABLFAb_maxAsrcFog (HC_XA_maxAsrcFog << 2)
595#define HC_HABLFAb_maxAsrcAdst (HC_XA_maxAsrcAdst << 2)
596#define HC_HABLFAb_minAsrcInvAdst (HC_XA_minAsrcInvAdst << 2)
597#define HC_HABLFAb_HABLFRA (HC_XA_HABLFRA << 2)
598/* HC_SubA_HABLRAa 0x003d
599 */
600#define HC_HABLRAa_MASK 0x00ff0000
601#define HC_HABLRFAa_MASK 0x0000ff00
602#define HC_HABLRAbias_MASK 0x000000ff
603#define HC_HABLRAa_SHIFT 16
604#define HC_HABLRFAa_SHIFT 8
605/* HC_SubA_HABLRAb 0x003e
606 */
607#define HC_HABLRAb_MASK 0x0000ff00
608#define HC_HABLRFAb_MASK 0x000000ff
609#define HC_HABLRAb_SHIFT 8
610
611/* Destination Setting
612 */
613#define HC_SubA_HDBBasL 0x0040
614#define HC_SubA_HDBBasH 0x0041
615#define HC_SubA_HDBFM 0x0042
616#define HC_SubA_HFBBMSKL 0x0043
617#define HC_SubA_HROP 0x0044
618/* HC_SubA_HDBFM 0x0042
619 */
620#define HC_HDBFM_MASK 0x001f0000
621#define HC_HDBLoc_MASK 0x0000c000
622#define HC_HDBPit_MASK 0x00003fff
623#define HC_HDBFM_RGB555 0x00000000
624#define HC_HDBFM_RGB565 0x00010000
625#define HC_HDBFM_ARGB4444 0x00020000
626#define HC_HDBFM_ARGB1555 0x00030000
627#define HC_HDBFM_BGR555 0x00040000
628#define HC_HDBFM_BGR565 0x00050000
629#define HC_HDBFM_ABGR4444 0x00060000
630#define HC_HDBFM_ABGR1555 0x00070000
631#define HC_HDBFM_ARGB0888 0x00080000
632#define HC_HDBFM_ARGB8888 0x00090000
633#define HC_HDBFM_ABGR0888 0x000a0000
634#define HC_HDBFM_ABGR8888 0x000b0000
635#define HC_HDBLoc_Local 0x00000000
636#define HC_HDBLoc_Sys 0x00004000
637/* HC_SubA_HROP 0x0044
638 */
639#define HC_HROP_MASK 0x00000f00
640#define HC_HFBBMSKH_MASK 0x000000ff
641#define HC_HROP_BLACK 0x00000000
642#define HC_HROP_DPon 0x00000100
643#define HC_HROP_DPna 0x00000200
644#define HC_HROP_Pn 0x00000300
645#define HC_HROP_PDna 0x00000400
646#define HC_HROP_Dn 0x00000500
647#define HC_HROP_DPx 0x00000600
648#define HC_HROP_DPan 0x00000700
649#define HC_HROP_DPa 0x00000800
650#define HC_HROP_DPxn 0x00000900
651#define HC_HROP_D 0x00000a00
652#define HC_HROP_DPno 0x00000b00
653#define HC_HROP_P 0x00000c00
654#define HC_HROP_PDno 0x00000d00
655#define HC_HROP_DPo 0x00000e00
656#define HC_HROP_WHITE 0x00000f00
657
658/* Fog Setting
659 */
660#define HC_SubA_HFogLF 0x0050
661#define HC_SubA_HFogCL 0x0051
662#define HC_SubA_HFogCH 0x0052
663#define HC_SubA_HFogStL 0x0053
664#define HC_SubA_HFogStH 0x0054
665#define HC_SubA_HFogOOdMF 0x0055
666#define HC_SubA_HFogOOdEF 0x0056
667#define HC_SubA_HFogEndL 0x0057
668#define HC_SubA_HFogDenst 0x0058
669/* HC_SubA_FogLF 0x0050
670 */
671#define HC_FogLF_MASK 0x00000010
672#define HC_FogEq_MASK 0x00000008
673#define HC_FogMD_MASK 0x00000007
674#define HC_FogMD_LocalFog 0x00000000
675#define HC_FogMD_LinearFog 0x00000002
676#define HC_FogMD_ExponentialFog 0x00000004
677#define HC_FogMD_Exponential2Fog 0x00000005
678/* #define HC_FogMD_FogTable 0x00000003 */
679
680/* HC_SubA_HFogDenst 0x0058
681 */
682#define HC_FogDenst_MASK 0x001fff00
683#define HC_FogEndL_MASK 0x000000ff
684
685/* Texture subtype definitions
686 */
687#define HC_SubType_Tex0 0x00000000
688#define HC_SubType_Tex1 0x00000001
689#define HC_SubType_TexGeneral 0x000000fe
690
691/* Attribute of texture n
692 */
693#define HC_SubA_HTXnL0BasL 0x0000
694#define HC_SubA_HTXnL1BasL 0x0001
695#define HC_SubA_HTXnL2BasL 0x0002
696#define HC_SubA_HTXnL3BasL 0x0003
697#define HC_SubA_HTXnL4BasL 0x0004
698#define HC_SubA_HTXnL5BasL 0x0005
699#define HC_SubA_HTXnL6BasL 0x0006
700#define HC_SubA_HTXnL7BasL 0x0007
701#define HC_SubA_HTXnL8BasL 0x0008
702#define HC_SubA_HTXnL9BasL 0x0009
703#define HC_SubA_HTXnLaBasL 0x000a
704#define HC_SubA_HTXnLbBasL 0x000b
705#define HC_SubA_HTXnLcBasL 0x000c
706#define HC_SubA_HTXnLdBasL 0x000d
707#define HC_SubA_HTXnLeBasL 0x000e
708#define HC_SubA_HTXnLfBasL 0x000f
709#define HC_SubA_HTXnL10BasL 0x0010
710#define HC_SubA_HTXnL11BasL 0x0011
711#define HC_SubA_HTXnL012BasH 0x0020
712#define HC_SubA_HTXnL345BasH 0x0021
713#define HC_SubA_HTXnL678BasH 0x0022
714#define HC_SubA_HTXnL9abBasH 0x0023
715#define HC_SubA_HTXnLcdeBasH 0x0024
716#define HC_SubA_HTXnLf1011BasH 0x0025
717#define HC_SubA_HTXnL0Pit 0x002b
718#define HC_SubA_HTXnL1Pit 0x002c
719#define HC_SubA_HTXnL2Pit 0x002d
720#define HC_SubA_HTXnL3Pit 0x002e
721#define HC_SubA_HTXnL4Pit 0x002f
722#define HC_SubA_HTXnL5Pit 0x0030
723#define HC_SubA_HTXnL6Pit 0x0031
724#define HC_SubA_HTXnL7Pit 0x0032
725#define HC_SubA_HTXnL8Pit 0x0033
726#define HC_SubA_HTXnL9Pit 0x0034
727#define HC_SubA_HTXnLaPit 0x0035
728#define HC_SubA_HTXnLbPit 0x0036
729#define HC_SubA_HTXnLcPit 0x0037
730#define HC_SubA_HTXnLdPit 0x0038
731#define HC_SubA_HTXnLePit 0x0039
732#define HC_SubA_HTXnLfPit 0x003a
733#define HC_SubA_HTXnL10Pit 0x003b
734#define HC_SubA_HTXnL11Pit 0x003c
735#define HC_SubA_HTXnL0_5WE 0x004b
736#define HC_SubA_HTXnL6_bWE 0x004c
737#define HC_SubA_HTXnLc_11WE 0x004d
738#define HC_SubA_HTXnL0_5HE 0x0051
739#define HC_SubA_HTXnL6_bHE 0x0052
740#define HC_SubA_HTXnLc_11HE 0x0053
741#define HC_SubA_HTXnL0OS 0x0077
742#define HC_SubA_HTXnTB 0x0078
743#define HC_SubA_HTXnMPMD 0x0079
744#define HC_SubA_HTXnCLODu 0x007a
745#define HC_SubA_HTXnFM 0x007b
746#define HC_SubA_HTXnTRCH 0x007c
747#define HC_SubA_HTXnTRCL 0x007d
748#define HC_SubA_HTXnTBC 0x007e
749#define HC_SubA_HTXnTRAH 0x007f
750#define HC_SubA_HTXnTBLCsat 0x0080
751#define HC_SubA_HTXnTBLCop 0x0081
752#define HC_SubA_HTXnTBLMPfog 0x0082
753#define HC_SubA_HTXnTBLAsat 0x0083
754#define HC_SubA_HTXnTBLRCa 0x0085
755#define HC_SubA_HTXnTBLRCb 0x0086
756#define HC_SubA_HTXnTBLRCc 0x0087
757#define HC_SubA_HTXnTBLRCbias 0x0088
758#define HC_SubA_HTXnTBLRAa 0x0089
759#define HC_SubA_HTXnTBLRFog 0x008a
760#define HC_SubA_HTXnBumpM00 0x0090
761#define HC_SubA_HTXnBumpM01 0x0091
762#define HC_SubA_HTXnBumpM10 0x0092
763#define HC_SubA_HTXnBumpM11 0x0093
764#define HC_SubA_HTXnLScale 0x0094
765#define HC_SubA_HTXSMD 0x0000
766/* HC_SubA_HTXnL012BasH 0x0020
767 */
768#define HC_HTXnL0BasH_MASK 0x000000ff
769#define HC_HTXnL1BasH_MASK 0x0000ff00
770#define HC_HTXnL2BasH_MASK 0x00ff0000
771#define HC_HTXnL1BasH_SHIFT 8
772#define HC_HTXnL2BasH_SHIFT 16
773/* HC_SubA_HTXnL345BasH 0x0021
774 */
775#define HC_HTXnL3BasH_MASK 0x000000ff
776#define HC_HTXnL4BasH_MASK 0x0000ff00
777#define HC_HTXnL5BasH_MASK 0x00ff0000
778#define HC_HTXnL4BasH_SHIFT 8
779#define HC_HTXnL5BasH_SHIFT 16
780/* HC_SubA_HTXnL678BasH 0x0022
781 */
782#define HC_HTXnL6BasH_MASK 0x000000ff
783#define HC_HTXnL7BasH_MASK 0x0000ff00
784#define HC_HTXnL8BasH_MASK 0x00ff0000
785#define HC_HTXnL7BasH_SHIFT 8
786#define HC_HTXnL8BasH_SHIFT 16
787/* HC_SubA_HTXnL9abBasH 0x0023
788 */
789#define HC_HTXnL9BasH_MASK 0x000000ff
790#define HC_HTXnLaBasH_MASK 0x0000ff00
791#define HC_HTXnLbBasH_MASK 0x00ff0000
792#define HC_HTXnLaBasH_SHIFT 8
793#define HC_HTXnLbBasH_SHIFT 16
794/* HC_SubA_HTXnLcdeBasH 0x0024
795 */
796#define HC_HTXnLcBasH_MASK 0x000000ff
797#define HC_HTXnLdBasH_MASK 0x0000ff00
798#define HC_HTXnLeBasH_MASK 0x00ff0000
799#define HC_HTXnLdBasH_SHIFT 8
800#define HC_HTXnLeBasH_SHIFT 16
801/* HC_SubA_HTXnLcdeBasH 0x0025
802 */
803#define HC_HTXnLfBasH_MASK 0x000000ff
804#define HC_HTXnL10BasH_MASK 0x0000ff00
805#define HC_HTXnL11BasH_MASK 0x00ff0000
806#define HC_HTXnL10BasH_SHIFT 8
807#define HC_HTXnL11BasH_SHIFT 16
808/* HC_SubA_HTXnL0Pit 0x002b
809 */
810#define HC_HTXnLnPit_MASK 0x00003fff
811#define HC_HTXnEnPit_MASK 0x00080000
812#define HC_HTXnLnPitE_MASK 0x00f00000
813#define HC_HTXnLnPitE_SHIFT 20
814/* HC_SubA_HTXnL0_5WE 0x004b
815 */
816#define HC_HTXnL0WE_MASK 0x0000000f
817#define HC_HTXnL1WE_MASK 0x000000f0
818#define HC_HTXnL2WE_MASK 0x00000f00
819#define HC_HTXnL3WE_MASK 0x0000f000
820#define HC_HTXnL4WE_MASK 0x000f0000
821#define HC_HTXnL5WE_MASK 0x00f00000
822#define HC_HTXnL1WE_SHIFT 4
823#define HC_HTXnL2WE_SHIFT 8
824#define HC_HTXnL3WE_SHIFT 12
825#define HC_HTXnL4WE_SHIFT 16
826#define HC_HTXnL5WE_SHIFT 20
827/* HC_SubA_HTXnL6_bWE 0x004c
828 */
829#define HC_HTXnL6WE_MASK 0x0000000f
830#define HC_HTXnL7WE_MASK 0x000000f0
831#define HC_HTXnL8WE_MASK 0x00000f00
832#define HC_HTXnL9WE_MASK 0x0000f000
833#define HC_HTXnLaWE_MASK 0x000f0000
834#define HC_HTXnLbWE_MASK 0x00f00000
835#define HC_HTXnL7WE_SHIFT 4
836#define HC_HTXnL8WE_SHIFT 8
837#define HC_HTXnL9WE_SHIFT 12
838#define HC_HTXnLaWE_SHIFT 16
839#define HC_HTXnLbWE_SHIFT 20
840/* HC_SubA_HTXnLc_11WE 0x004d
841 */
842#define HC_HTXnLcWE_MASK 0x0000000f
843#define HC_HTXnLdWE_MASK 0x000000f0
844#define HC_HTXnLeWE_MASK 0x00000f00
845#define HC_HTXnLfWE_MASK 0x0000f000
846#define HC_HTXnL10WE_MASK 0x000f0000
847#define HC_HTXnL11WE_MASK 0x00f00000
848#define HC_HTXnLdWE_SHIFT 4
849#define HC_HTXnLeWE_SHIFT 8
850#define HC_HTXnLfWE_SHIFT 12
851#define HC_HTXnL10WE_SHIFT 16
852#define HC_HTXnL11WE_SHIFT 20
853/* HC_SubA_HTXnL0_5HE 0x0051
854 */
855#define HC_HTXnL0HE_MASK 0x0000000f
856#define HC_HTXnL1HE_MASK 0x000000f0
857#define HC_HTXnL2HE_MASK 0x00000f00
858#define HC_HTXnL3HE_MASK 0x0000f000
859#define HC_HTXnL4HE_MASK 0x000f0000
860#define HC_HTXnL5HE_MASK 0x00f00000
861#define HC_HTXnL1HE_SHIFT 4
862#define HC_HTXnL2HE_SHIFT 8
863#define HC_HTXnL3HE_SHIFT 12
864#define HC_HTXnL4HE_SHIFT 16
865#define HC_HTXnL5HE_SHIFT 20
866/* HC_SubA_HTXnL6_bHE 0x0052
867 */
868#define HC_HTXnL6HE_MASK 0x0000000f
869#define HC_HTXnL7HE_MASK 0x000000f0
870#define HC_HTXnL8HE_MASK 0x00000f00
871#define HC_HTXnL9HE_MASK 0x0000f000
872#define HC_HTXnLaHE_MASK 0x000f0000
873#define HC_HTXnLbHE_MASK 0x00f00000
874#define HC_HTXnL7HE_SHIFT 4
875#define HC_HTXnL8HE_SHIFT 8
876#define HC_HTXnL9HE_SHIFT 12
877#define HC_HTXnLaHE_SHIFT 16
878#define HC_HTXnLbHE_SHIFT 20
879/* HC_SubA_HTXnLc_11HE 0x0053
880 */
881#define HC_HTXnLcHE_MASK 0x0000000f
882#define HC_HTXnLdHE_MASK 0x000000f0
883#define HC_HTXnLeHE_MASK 0x00000f00
884#define HC_HTXnLfHE_MASK 0x0000f000
885#define HC_HTXnL10HE_MASK 0x000f0000
886#define HC_HTXnL11HE_MASK 0x00f00000
887#define HC_HTXnLdHE_SHIFT 4
888#define HC_HTXnLeHE_SHIFT 8
889#define HC_HTXnLfHE_SHIFT 12
890#define HC_HTXnL10HE_SHIFT 16
891#define HC_HTXnL11HE_SHIFT 20
892/* HC_SubA_HTXnL0OS 0x0077
893 */
894#define HC_HTXnL0OS_MASK 0x003ff000
895#define HC_HTXnLVmax_MASK 0x00000fc0
896#define HC_HTXnLVmin_MASK 0x0000003f
897#define HC_HTXnL0OS_SHIFT 12
898#define HC_HTXnLVmax_SHIFT 6
899/* HC_SubA_HTXnTB 0x0078
900 */
901#define HC_HTXnTB_MASK 0x00f00000
902#define HC_HTXnFLSe_MASK 0x0000e000
903#define HC_HTXnFLSs_MASK 0x00001c00
904#define HC_HTXnFLTe_MASK 0x00000380
905#define HC_HTXnFLTs_MASK 0x00000070
906#define HC_HTXnFLDs_MASK 0x0000000f
907#define HC_HTXnTB_NoTB 0x00000000
908#define HC_HTXnTB_TBC_S 0x00100000
909#define HC_HTXnTB_TBC_T 0x00200000
910#define HC_HTXnTB_TB_S 0x00400000
911#define HC_HTXnTB_TB_T 0x00800000
912#define HC_HTXnFLSe_Nearest 0x00000000
913#define HC_HTXnFLSe_Linear 0x00002000
914#define HC_HTXnFLSe_NonLinear 0x00004000
915#define HC_HTXnFLSe_Sharp 0x00008000
916#define HC_HTXnFLSe_Flat_Gaussian_Cubic 0x0000c000
917#define HC_HTXnFLSs_Nearest 0x00000000
918#define HC_HTXnFLSs_Linear 0x00000400
919#define HC_HTXnFLSs_NonLinear 0x00000800
920#define HC_HTXnFLSs_Flat_Gaussian_Cubic 0x00001800
921#define HC_HTXnFLTe_Nearest 0x00000000
922#define HC_HTXnFLTe_Linear 0x00000080
923#define HC_HTXnFLTe_NonLinear 0x00000100
924#define HC_HTXnFLTe_Sharp 0x00000180
925#define HC_HTXnFLTe_Flat_Gaussian_Cubic 0x00000300
926#define HC_HTXnFLTs_Nearest 0x00000000
927#define HC_HTXnFLTs_Linear 0x00000010
928#define HC_HTXnFLTs_NonLinear 0x00000020
929#define HC_HTXnFLTs_Flat_Gaussian_Cubic 0x00000060
930#define HC_HTXnFLDs_Tex0 0x00000000
931#define HC_HTXnFLDs_Nearest 0x00000001
932#define HC_HTXnFLDs_Linear 0x00000002
933#define HC_HTXnFLDs_NonLinear 0x00000003
934#define HC_HTXnFLDs_Dither 0x00000004
935#define HC_HTXnFLDs_ConstLOD 0x00000005
936#define HC_HTXnFLDs_Ani 0x00000006
937#define HC_HTXnFLDs_AniDither 0x00000007
938/* HC_SubA_HTXnMPMD 0x0079
939 */
940#define HC_HTXnMPMD_SMASK 0x00070000
941#define HC_HTXnMPMD_TMASK 0x00380000
942#define HC_HTXnLODDTf_MASK 0x00000007
943#define HC_HTXnXY2ST_MASK 0x00000008
944#define HC_HTXnMPMD_Tsingle 0x00000000
945#define HC_HTXnMPMD_Tclamp 0x00080000
946#define HC_HTXnMPMD_Trepeat 0x00100000
947#define HC_HTXnMPMD_Tmirror 0x00180000
948#define HC_HTXnMPMD_Twrap 0x00200000
949#define HC_HTXnMPMD_Ssingle 0x00000000
950#define HC_HTXnMPMD_Sclamp 0x00010000
951#define HC_HTXnMPMD_Srepeat 0x00020000
952#define HC_HTXnMPMD_Smirror 0x00030000
953#define HC_HTXnMPMD_Swrap 0x00040000
954/* HC_SubA_HTXnCLODu 0x007a
955 */
956#define HC_HTXnCLODu_MASK 0x000ffc00
957#define HC_HTXnCLODd_MASK 0x000003ff
958#define HC_HTXnCLODu_SHIFT 10
959/* HC_SubA_HTXnFM 0x007b
960 */
961#define HC_HTXnFM_MASK 0x00ff0000
962#define HC_HTXnLoc_MASK 0x00000003
963#define HC_HTXnFM_INDEX 0x00000000
964#define HC_HTXnFM_Intensity 0x00080000
965#define HC_HTXnFM_Lum 0x00100000
966#define HC_HTXnFM_Alpha 0x00180000
967#define HC_HTXnFM_DX 0x00280000
968#define HC_HTXnFM_ARGB16 0x00880000
969#define HC_HTXnFM_ARGB32 0x00980000
970#define HC_HTXnFM_ABGR16 0x00a80000
971#define HC_HTXnFM_ABGR32 0x00b80000
972#define HC_HTXnFM_RGBA16 0x00c80000
973#define HC_HTXnFM_RGBA32 0x00d80000
974#define HC_HTXnFM_BGRA16 0x00e80000
975#define HC_HTXnFM_BGRA32 0x00f80000
976#define HC_HTXnFM_BUMPMAP 0x00380000
977#define HC_HTXnFM_Index1 (HC_HTXnFM_INDEX | 0x00000000)
978#define HC_HTXnFM_Index2 (HC_HTXnFM_INDEX | 0x00010000)
979#define HC_HTXnFM_Index4 (HC_HTXnFM_INDEX | 0x00020000)
980#define HC_HTXnFM_Index8 (HC_HTXnFM_INDEX | 0x00030000)
981#define HC_HTXnFM_T1 (HC_HTXnFM_Intensity | 0x00000000)
982#define HC_HTXnFM_T2 (HC_HTXnFM_Intensity | 0x00010000)
983#define HC_HTXnFM_T4 (HC_HTXnFM_Intensity | 0x00020000)
984#define HC_HTXnFM_T8 (HC_HTXnFM_Intensity | 0x00030000)
985#define HC_HTXnFM_L1 (HC_HTXnFM_Lum | 0x00000000)
986#define HC_HTXnFM_L2 (HC_HTXnFM_Lum | 0x00010000)
987#define HC_HTXnFM_L4 (HC_HTXnFM_Lum | 0x00020000)
988#define HC_HTXnFM_L8 (HC_HTXnFM_Lum | 0x00030000)
989#define HC_HTXnFM_AL44 (HC_HTXnFM_Lum | 0x00040000)
990#define HC_HTXnFM_AL88 (HC_HTXnFM_Lum | 0x00050000)
991#define HC_HTXnFM_A1 (HC_HTXnFM_Alpha | 0x00000000)
992#define HC_HTXnFM_A2 (HC_HTXnFM_Alpha | 0x00010000)
993#define HC_HTXnFM_A4 (HC_HTXnFM_Alpha | 0x00020000)
994#define HC_HTXnFM_A8 (HC_HTXnFM_Alpha | 0x00030000)
995#define HC_HTXnFM_DX1 (HC_HTXnFM_DX | 0x00010000)
996#define HC_HTXnFM_DX23 (HC_HTXnFM_DX | 0x00020000)
997#define HC_HTXnFM_DX45 (HC_HTXnFM_DX | 0x00030000)
998#define HC_HTXnFM_RGB555 (HC_HTXnFM_ARGB16 | 0x00000000)
999#define HC_HTXnFM_RGB565 (HC_HTXnFM_ARGB16 | 0x00010000)
1000#define HC_HTXnFM_ARGB1555 (HC_HTXnFM_ARGB16 | 0x00020000)
1001#define HC_HTXnFM_ARGB4444 (HC_HTXnFM_ARGB16 | 0x00030000)
1002#define HC_HTXnFM_ARGB0888 (HC_HTXnFM_ARGB32 | 0x00000000)
1003#define HC_HTXnFM_ARGB8888 (HC_HTXnFM_ARGB32 | 0x00010000)
1004#define HC_HTXnFM_BGR555 (HC_HTXnFM_ABGR16 | 0x00000000)
1005#define HC_HTXnFM_BGR565 (HC_HTXnFM_ABGR16 | 0x00010000)
1006#define HC_HTXnFM_ABGR1555 (HC_HTXnFM_ABGR16 | 0x00020000)
1007#define HC_HTXnFM_ABGR4444 (HC_HTXnFM_ABGR16 | 0x00030000)
1008#define HC_HTXnFM_ABGR0888 (HC_HTXnFM_ABGR32 | 0x00000000)
1009#define HC_HTXnFM_ABGR8888 (HC_HTXnFM_ABGR32 | 0x00010000)
1010#define HC_HTXnFM_RGBA5550 (HC_HTXnFM_RGBA16 | 0x00000000)
1011#define HC_HTXnFM_RGBA5551 (HC_HTXnFM_RGBA16 | 0x00020000)
1012#define HC_HTXnFM_RGBA4444 (HC_HTXnFM_RGBA16 | 0x00030000)
1013#define HC_HTXnFM_RGBA8880 (HC_HTXnFM_RGBA32 | 0x00000000)
1014#define HC_HTXnFM_RGBA8888 (HC_HTXnFM_RGBA32 | 0x00010000)
1015#define HC_HTXnFM_BGRA5550 (HC_HTXnFM_BGRA16 | 0x00000000)
1016#define HC_HTXnFM_BGRA5551 (HC_HTXnFM_BGRA16 | 0x00020000)
1017#define HC_HTXnFM_BGRA4444 (HC_HTXnFM_BGRA16 | 0x00030000)
1018#define HC_HTXnFM_BGRA8880 (HC_HTXnFM_BGRA32 | 0x00000000)
1019#define HC_HTXnFM_BGRA8888 (HC_HTXnFM_BGRA32 | 0x00010000)
1020#define HC_HTXnFM_VU88 (HC_HTXnFM_BUMPMAP | 0x00000000)
1021#define HC_HTXnFM_LVU655 (HC_HTXnFM_BUMPMAP | 0x00010000)
1022#define HC_HTXnFM_LVU888 (HC_HTXnFM_BUMPMAP | 0x00020000)
1023#define HC_HTXnLoc_Local 0x00000000
1024#define HC_HTXnLoc_Sys 0x00000002
1025#define HC_HTXnLoc_AGP 0x00000003
1026/* HC_SubA_HTXnTRAH 0x007f
1027 */
1028#define HC_HTXnTRAH_MASK 0x00ff0000
1029#define HC_HTXnTRAL_MASK 0x0000ff00
1030#define HC_HTXnTBA_MASK 0x000000ff
1031#define HC_HTXnTRAH_SHIFT 16
1032#define HC_HTXnTRAL_SHIFT 8
1033/* HC_SubA_HTXnTBLCsat 0x0080
1034 *-- Define the input texture.
1035 */
1036#define HC_XTC_TOPC 0x00000000
1037#define HC_XTC_InvTOPC 0x00000010
1038#define HC_XTC_TOPCp5 0x00000020
1039#define HC_XTC_Cbias 0x00000000
1040#define HC_XTC_InvCbias 0x00000010
1041#define HC_XTC_0 0x00000000
1042#define HC_XTC_Dif 0x00000001
1043#define HC_XTC_Spec 0x00000002
1044#define HC_XTC_Tex 0x00000003
1045#define HC_XTC_Cur 0x00000004
1046#define HC_XTC_Adif 0x00000005
1047#define HC_XTC_Fog 0x00000006
1048#define HC_XTC_Atex 0x00000007
1049#define HC_XTC_Acur 0x00000008
1050#define HC_XTC_HTXnTBLRC 0x00000009
1051#define HC_XTC_Ctexnext 0x0000000a
1052/*--
1053 */
1054#define HC_HTXnTBLCsat_MASK 0x00800000
1055#define HC_HTXnTBLCa_MASK 0x000fc000
1056#define HC_HTXnTBLCb_MASK 0x00001f80
1057#define HC_HTXnTBLCc_MASK 0x0000003f
1058#define HC_HTXnTBLCa_TOPC (HC_XTC_TOPC << 14)
1059#define HC_HTXnTBLCa_InvTOPC (HC_XTC_InvTOPC << 14)
1060#define HC_HTXnTBLCa_TOPCp5 (HC_XTC_TOPCp5 << 14)
1061#define HC_HTXnTBLCa_0 (HC_XTC_0 << 14)
1062#define HC_HTXnTBLCa_Dif (HC_XTC_Dif << 14)
1063#define HC_HTXnTBLCa_Spec (HC_XTC_Spec << 14)
1064#define HC_HTXnTBLCa_Tex (HC_XTC_Tex << 14)
1065#define HC_HTXnTBLCa_Cur (HC_XTC_Cur << 14)
1066#define HC_HTXnTBLCa_Adif (HC_XTC_Adif << 14)
1067#define HC_HTXnTBLCa_Fog (HC_XTC_Fog << 14)
1068#define HC_HTXnTBLCa_Atex (HC_XTC_Atex << 14)
1069#define HC_HTXnTBLCa_Acur (HC_XTC_Acur << 14)
1070#define HC_HTXnTBLCa_HTXnTBLRC (HC_XTC_HTXnTBLRC << 14)
1071#define HC_HTXnTBLCa_Ctexnext (HC_XTC_Ctexnext << 14)
1072#define HC_HTXnTBLCb_TOPC (HC_XTC_TOPC << 7)
1073#define HC_HTXnTBLCb_InvTOPC (HC_XTC_InvTOPC << 7)
1074#define HC_HTXnTBLCb_TOPCp5 (HC_XTC_TOPCp5 << 7)
1075#define HC_HTXnTBLCb_0 (HC_XTC_0 << 7)
1076#define HC_HTXnTBLCb_Dif (HC_XTC_Dif << 7)
1077#define HC_HTXnTBLCb_Spec (HC_XTC_Spec << 7)
1078#define HC_HTXnTBLCb_Tex (HC_XTC_Tex << 7)
1079#define HC_HTXnTBLCb_Cur (HC_XTC_Cur << 7)
1080#define HC_HTXnTBLCb_Adif (HC_XTC_Adif << 7)
1081#define HC_HTXnTBLCb_Fog (HC_XTC_Fog << 7)
1082#define HC_HTXnTBLCb_Atex (HC_XTC_Atex << 7)
1083#define HC_HTXnTBLCb_Acur (HC_XTC_Acur << 7)
1084#define HC_HTXnTBLCb_HTXnTBLRC (HC_XTC_HTXnTBLRC << 7)
1085#define HC_HTXnTBLCb_Ctexnext (HC_XTC_Ctexnext << 7)
1086#define HC_HTXnTBLCc_TOPC (HC_XTC_TOPC << 0)
1087#define HC_HTXnTBLCc_InvTOPC (HC_XTC_InvTOPC << 0)
1088#define HC_HTXnTBLCc_TOPCp5 (HC_XTC_TOPCp5 << 0)
1089#define HC_HTXnTBLCc_0 (HC_XTC_0 << 0)
1090#define HC_HTXnTBLCc_Dif (HC_XTC_Dif << 0)
1091#define HC_HTXnTBLCc_Spec (HC_XTC_Spec << 0)
1092#define HC_HTXnTBLCc_Tex (HC_XTC_Tex << 0)
1093#define HC_HTXnTBLCc_Cur (HC_XTC_Cur << 0)
1094#define HC_HTXnTBLCc_Adif (HC_XTC_Adif << 0)
1095#define HC_HTXnTBLCc_Fog (HC_XTC_Fog << 0)
1096#define HC_HTXnTBLCc_Atex (HC_XTC_Atex << 0)
1097#define HC_HTXnTBLCc_Acur (HC_XTC_Acur << 0)
1098#define HC_HTXnTBLCc_HTXnTBLRC (HC_XTC_HTXnTBLRC << 0)
1099#define HC_HTXnTBLCc_Ctexnext (HC_XTC_Ctexnext << 0)
1100/* HC_SubA_HTXnTBLCop 0x0081
1101 */
1102#define HC_HTXnTBLdot_MASK 0x00c00000
1103#define HC_HTXnTBLCop_MASK 0x00380000
1104#define HC_HTXnTBLCbias_MASK 0x0007c000
1105#define HC_HTXnTBLCshift_MASK 0x00001800
1106#define HC_HTXnTBLAop_MASK 0x00000380
1107#define HC_HTXnTBLAbias_MASK 0x00000078
1108#define HC_HTXnTBLAshift_MASK 0x00000003
1109#define HC_HTXnTBLCop_Add 0x00000000
1110#define HC_HTXnTBLCop_Sub 0x00080000
1111#define HC_HTXnTBLCop_Min 0x00100000
1112#define HC_HTXnTBLCop_Max 0x00180000
1113#define HC_HTXnTBLCop_Mask 0x00200000
1114#define HC_HTXnTBLCbias_Cbias (HC_XTC_Cbias << 14)
1115#define HC_HTXnTBLCbias_InvCbias (HC_XTC_InvCbias << 14)
1116#define HC_HTXnTBLCbias_0 (HC_XTC_0 << 14)
1117#define HC_HTXnTBLCbias_Dif (HC_XTC_Dif << 14)
1118#define HC_HTXnTBLCbias_Spec (HC_XTC_Spec << 14)
1119#define HC_HTXnTBLCbias_Tex (HC_XTC_Tex << 14)
1120#define HC_HTXnTBLCbias_Cur (HC_XTC_Cur << 14)
1121#define HC_HTXnTBLCbias_Adif (HC_XTC_Adif << 14)
1122#define HC_HTXnTBLCbias_Fog (HC_XTC_Fog << 14)
1123#define HC_HTXnTBLCbias_Atex (HC_XTC_Atex << 14)
1124#define HC_HTXnTBLCbias_Acur (HC_XTC_Acur << 14)
1125#define HC_HTXnTBLCbias_HTXnTBLRC (HC_XTC_HTXnTBLRC << 14)
1126#define HC_HTXnTBLCshift_1 0x00000000
1127#define HC_HTXnTBLCshift_2 0x00000800
1128#define HC_HTXnTBLCshift_No 0x00001000
1129#define HC_HTXnTBLCshift_DotP 0x00001800
1130/*=* John Sheng [2003.7.18] texture combine *=*/
1131#define HC_HTXnTBLDOT3 0x00080000
1132#define HC_HTXnTBLDOT4 0x000C0000
1133
1134#define HC_HTXnTBLAop_Add 0x00000000
1135#define HC_HTXnTBLAop_Sub 0x00000080
1136#define HC_HTXnTBLAop_Min 0x00000100
1137#define HC_HTXnTBLAop_Max 0x00000180
1138#define HC_HTXnTBLAop_Mask 0x00000200
1139#define HC_HTXnTBLAbias_Inv 0x00000040
1140#define HC_HTXnTBLAbias_Adif 0x00000000
1141#define HC_HTXnTBLAbias_Fog 0x00000008
1142#define HC_HTXnTBLAbias_Acur 0x00000010
1143#define HC_HTXnTBLAbias_HTXnTBLRAbias 0x00000018
1144#define HC_HTXnTBLAbias_Atex 0x00000020
1145#define HC_HTXnTBLAshift_1 0x00000000
1146#define HC_HTXnTBLAshift_2 0x00000001
1147#define HC_HTXnTBLAshift_No 0x00000002
1148/* #define HC_HTXnTBLAshift_DotP 0x00000003 */
1149/* HC_SubA_HTXnTBLMPFog 0x0082
1150 */
1151#define HC_HTXnTBLMPfog_MASK 0x00e00000
1152#define HC_HTXnTBLMPfog_0 0x00000000
1153#define HC_HTXnTBLMPfog_Adif 0x00200000
1154#define HC_HTXnTBLMPfog_Fog 0x00400000
1155#define HC_HTXnTBLMPfog_Atex 0x00600000
1156#define HC_HTXnTBLMPfog_Acur 0x00800000
1157#define HC_HTXnTBLMPfog_GHTXnTBLRFog 0x00a00000
1158/* HC_SubA_HTXnTBLAsat 0x0083
1159 *-- Define the texture alpha input.
1160 */
1161#define HC_XTA_TOPA 0x00000000
1162#define HC_XTA_InvTOPA 0x00000008
1163#define HC_XTA_TOPAp5 0x00000010
1164#define HC_XTA_Adif 0x00000000
1165#define HC_XTA_Fog 0x00000001
1166#define HC_XTA_Acur 0x00000002
1167#define HC_XTA_HTXnTBLRA 0x00000003
1168#define HC_XTA_Atex 0x00000004
1169#define HC_XTA_Atexnext 0x00000005
1170/*--
1171 */
1172#define HC_HTXnTBLAsat_MASK 0x00800000
1173#define HC_HTXnTBLAMB_MASK 0x00700000
1174#define HC_HTXnTBLAa_MASK 0x0007c000
1175#define HC_HTXnTBLAb_MASK 0x00000f80
1176#define HC_HTXnTBLAc_MASK 0x0000001f
1177#define HC_HTXnTBLAMB_SHIFT 20
1178#define HC_HTXnTBLAa_TOPA (HC_XTA_TOPA << 14)
1179#define HC_HTXnTBLAa_InvTOPA (HC_XTA_InvTOPA << 14)
1180#define HC_HTXnTBLAa_TOPAp5 (HC_XTA_TOPAp5 << 14)
1181#define HC_HTXnTBLAa_Adif (HC_XTA_Adif << 14)
1182#define HC_HTXnTBLAa_Fog (HC_XTA_Fog << 14)
1183#define HC_HTXnTBLAa_Acur (HC_XTA_Acur << 14)
1184#define HC_HTXnTBLAa_HTXnTBLRA (HC_XTA_HTXnTBLRA << 14)
1185#define HC_HTXnTBLAa_Atex (HC_XTA_Atex << 14)
1186#define HC_HTXnTBLAa_Atexnext (HC_XTA_Atexnext << 14)
1187#define HC_HTXnTBLAb_TOPA (HC_XTA_TOPA << 7)
1188#define HC_HTXnTBLAb_InvTOPA (HC_XTA_InvTOPA << 7)
1189#define HC_HTXnTBLAb_TOPAp5 (HC_XTA_TOPAp5 << 7)
1190#define HC_HTXnTBLAb_Adif (HC_XTA_Adif << 7)
1191#define HC_HTXnTBLAb_Fog (HC_XTA_Fog << 7)
1192#define HC_HTXnTBLAb_Acur (HC_XTA_Acur << 7)
1193#define HC_HTXnTBLAb_HTXnTBLRA (HC_XTA_HTXnTBLRA << 7)
1194#define HC_HTXnTBLAb_Atex (HC_XTA_Atex << 7)
1195#define HC_HTXnTBLAb_Atexnext (HC_XTA_Atexnext << 7)
1196#define HC_HTXnTBLAc_TOPA (HC_XTA_TOPA << 0)
1197#define HC_HTXnTBLAc_InvTOPA (HC_XTA_InvTOPA << 0)
1198#define HC_HTXnTBLAc_TOPAp5 (HC_XTA_TOPAp5 << 0)
1199#define HC_HTXnTBLAc_Adif (HC_XTA_Adif << 0)
1200#define HC_HTXnTBLAc_Fog (HC_XTA_Fog << 0)
1201#define HC_HTXnTBLAc_Acur (HC_XTA_Acur << 0)
1202#define HC_HTXnTBLAc_HTXnTBLRA (HC_XTA_HTXnTBLRA << 0)
1203#define HC_HTXnTBLAc_Atex (HC_XTA_Atex << 0)
1204#define HC_HTXnTBLAc_Atexnext (HC_XTA_Atexnext << 0)
1205/* HC_SubA_HTXnTBLRAa 0x0089
1206 */
1207#define HC_HTXnTBLRAa_MASK 0x00ff0000
1208#define HC_HTXnTBLRAb_MASK 0x0000ff00
1209#define HC_HTXnTBLRAc_MASK 0x000000ff
1210#define HC_HTXnTBLRAa_SHIFT 16
1211#define HC_HTXnTBLRAb_SHIFT 8
1212#define HC_HTXnTBLRAc_SHIFT 0
1213/* HC_SubA_HTXnTBLRFog 0x008a
1214 */
1215#define HC_HTXnTBLRFog_MASK 0x0000ff00
1216#define HC_HTXnTBLRAbias_MASK 0x000000ff
1217#define HC_HTXnTBLRFog_SHIFT 8
1218#define HC_HTXnTBLRAbias_SHIFT 0
1219/* HC_SubA_HTXnLScale 0x0094
1220 */
1221#define HC_HTXnLScale_MASK 0x0007fc00
1222#define HC_HTXnLOff_MASK 0x000001ff
1223#define HC_HTXnLScale_SHIFT 10
1224/* HC_SubA_HTXSMD 0x0000
1225 */
1226#define HC_HTXSMD_MASK 0x00000080
1227#define HC_HTXTMD_MASK 0x00000040
1228#define HC_HTXNum_MASK 0x00000038
1229#define HC_HTXTRMD_MASK 0x00000006
1230#define HC_HTXCHCLR_MASK 0x00000001
1231#define HC_HTXNum_SHIFT 3
1232
1233/* Texture Palette n
1234 */
1235#define HC_SubType_TexPalette0 0x00000000
1236#define HC_SubType_TexPalette1 0x00000001
1237#define HC_SubType_FogTable 0x00000010
1238#define HC_SubType_Stipple 0x00000014
1239/* HC_SubA_TexPalette0 0x0000
1240 */
1241#define HC_HTPnA_MASK 0xff000000
1242#define HC_HTPnR_MASK 0x00ff0000
1243#define HC_HTPnG_MASK 0x0000ff00
1244#define HC_HTPnB_MASK 0x000000ff
1245/* HC_SubA_FogTable 0x0010
1246 */
1247#define HC_HFPn3_MASK 0xff000000
1248#define HC_HFPn2_MASK 0x00ff0000
1249#define HC_HFPn1_MASK 0x0000ff00
1250#define HC_HFPn_MASK 0x000000ff
1251#define HC_HFPn3_SHIFT 24
1252#define HC_HFPn2_SHIFT 16
1253#define HC_HFPn1_SHIFT 8
1254
1255/* Auto Testing & Security
1256 */
1257#define HC_SubA_HenFIFOAT 0x0000
1258#define HC_SubA_HFBDrawFirst 0x0004
1259#define HC_SubA_HFBBasL 0x0005
1260#define HC_SubA_HFBDst 0x0006
1261/* HC_SubA_HenFIFOAT 0x0000
1262 */
1263#define HC_HenFIFOAT_MASK 0x00000020
1264#define HC_HenGEMILock_MASK 0x00000010
1265#define HC_HenFBASwap_MASK 0x00000008
1266#define HC_HenOT_MASK 0x00000004
1267#define HC_HenCMDQ_MASK 0x00000002
1268#define HC_HenTXCTSU_MASK 0x00000001
1269/* HC_SubA_HFBDrawFirst 0x0004
1270 */
1271#define HC_HFBDrawFirst_MASK 0x00000800
1272#define HC_HFBQueue_MASK 0x00000400
1273#define HC_HFBLock_MASK 0x00000200
1274#define HC_HEOF_MASK 0x00000100
1275#define HC_HFBBasH_MASK 0x000000ff
1276
1277/* GEMI Setting
1278 */
1279#define HC_SubA_HTArbRCM 0x0008
1280#define HC_SubA_HTArbRZ 0x000a
1281#define HC_SubA_HTArbWZ 0x000b
1282#define HC_SubA_HTArbRTX 0x000c
1283#define HC_SubA_HTArbRCW 0x000d
1284#define HC_SubA_HTArbE2 0x000e
1285#define HC_SubA_HArbRQCM 0x0010
1286#define HC_SubA_HArbWQCM 0x0011
1287#define HC_SubA_HGEMITout 0x0020
1288#define HC_SubA_HFthRTXD 0x0040
1289#define HC_SubA_HFthRTXA 0x0044
1290#define HC_SubA_HCMDQstL 0x0050
1291#define HC_SubA_HCMDQendL 0x0051
1292#define HC_SubA_HCMDQLen 0x0052
1293/* HC_SubA_HTArbRCM 0x0008
1294 */
1295#define HC_HTArbRCM_MASK 0x0000ffff
1296/* HC_SubA_HTArbRZ 0x000a
1297 */
1298#define HC_HTArbRZ_MASK 0x0000ffff
1299/* HC_SubA_HTArbWZ 0x000b
1300 */
1301#define HC_HTArbWZ_MASK 0x0000ffff
1302/* HC_SubA_HTArbRTX 0x000c
1303 */
1304#define HC_HTArbRTX_MASK 0x0000ffff
1305/* HC_SubA_HTArbRCW 0x000d
1306 */
1307#define HC_HTArbRCW_MASK 0x0000ffff
1308/* HC_SubA_HTArbE2 0x000e
1309 */
1310#define HC_HTArbE2_MASK 0x0000ffff
1311/* HC_SubA_HArbRQCM 0x0010
1312 */
1313#define HC_HTArbRQCM_MASK 0x0000ffff
1314/* HC_SubA_HArbWQCM 0x0011
1315 */
1316#define HC_HArbWQCM_MASK 0x0000ffff
1317/* HC_SubA_HGEMITout 0x0020
1318 */
1319#define HC_HGEMITout_MASK 0x000f0000
1320#define HC_HNPArbZC_MASK 0x0000ffff
1321#define HC_HGEMITout_SHIFT 16
1322/* HC_SubA_HFthRTXD 0x0040
1323 */
1324#define HC_HFthRTXD_MASK 0x00ff0000
1325#define HC_HFthRZD_MASK 0x0000ff00
1326#define HC_HFthWZD_MASK 0x000000ff
1327#define HC_HFthRTXD_SHIFT 16
1328#define HC_HFthRZD_SHIFT 8
1329/* HC_SubA_HFthRTXA 0x0044
1330 */
1331#define HC_HFthRTXA_MASK 0x000000ff
1332
1333/******************************************************************************
1334** Define the Halcyon Internal register access constants. For simulator only.
1335******************************************************************************/
1336#define HC_SIMA_HAGPBstL 0x0000
1337#define HC_SIMA_HAGPBendL 0x0001
1338#define HC_SIMA_HAGPCMNT 0x0002
1339#define HC_SIMA_HAGPBpL 0x0003
1340#define HC_SIMA_HAGPBpH 0x0004
1341#define HC_SIMA_HClipTB 0x0005
1342#define HC_SIMA_HClipLR 0x0006
1343#define HC_SIMA_HFPClipTL 0x0007
1344#define HC_SIMA_HFPClipBL 0x0008
1345#define HC_SIMA_HFPClipLL 0x0009
1346#define HC_SIMA_HFPClipRL 0x000a
1347#define HC_SIMA_HFPClipTBH 0x000b
1348#define HC_SIMA_HFPClipLRH 0x000c
1349#define HC_SIMA_HLP 0x000d
1350#define HC_SIMA_HLPRF 0x000e
1351#define HC_SIMA_HSolidCL 0x000f
1352#define HC_SIMA_HPixGC 0x0010
1353#define HC_SIMA_HSPXYOS 0x0011
1354#define HC_SIMA_HCmdA 0x0012
1355#define HC_SIMA_HCmdB 0x0013
1356#define HC_SIMA_HEnable 0x0014
1357#define HC_SIMA_HZWBBasL 0x0015
1358#define HC_SIMA_HZWBBasH 0x0016
1359#define HC_SIMA_HZWBType 0x0017
1360#define HC_SIMA_HZBiasL 0x0018
1361#define HC_SIMA_HZWBend 0x0019
1362#define HC_SIMA_HZWTMD 0x001a
1363#define HC_SIMA_HZWCDL 0x001b
1364#define HC_SIMA_HZWCTAGnum 0x001c
1365#define HC_SIMA_HZCYNum 0x001d
1366#define HC_SIMA_HZWCFire 0x001e
1367/* #define HC_SIMA_HSBBasL 0x001d */
1368/* #define HC_SIMA_HSBBasH 0x001e */
1369/* #define HC_SIMA_HSBFM 0x001f */
1370#define HC_SIMA_HSTREF 0x0020
1371#define HC_SIMA_HSTMD 0x0021
1372#define HC_SIMA_HABBasL 0x0022
1373#define HC_SIMA_HABBasH 0x0023
1374#define HC_SIMA_HABFM 0x0024
1375#define HC_SIMA_HATMD 0x0025
1376#define HC_SIMA_HABLCsat 0x0026
1377#define HC_SIMA_HABLCop 0x0027
1378#define HC_SIMA_HABLAsat 0x0028
1379#define HC_SIMA_HABLAop 0x0029
1380#define HC_SIMA_HABLRCa 0x002a
1381#define HC_SIMA_HABLRFCa 0x002b
1382#define HC_SIMA_HABLRCbias 0x002c
1383#define HC_SIMA_HABLRCb 0x002d
1384#define HC_SIMA_HABLRFCb 0x002e
1385#define HC_SIMA_HABLRAa 0x002f
1386#define HC_SIMA_HABLRAb 0x0030
1387#define HC_SIMA_HDBBasL 0x0031
1388#define HC_SIMA_HDBBasH 0x0032
1389#define HC_SIMA_HDBFM 0x0033
1390#define HC_SIMA_HFBBMSKL 0x0034
1391#define HC_SIMA_HROP 0x0035
1392#define HC_SIMA_HFogLF 0x0036
1393#define HC_SIMA_HFogCL 0x0037
1394#define HC_SIMA_HFogCH 0x0038
1395#define HC_SIMA_HFogStL 0x0039
1396#define HC_SIMA_HFogStH 0x003a
1397#define HC_SIMA_HFogOOdMF 0x003b
1398#define HC_SIMA_HFogOOdEF 0x003c
1399#define HC_SIMA_HFogEndL 0x003d
1400#define HC_SIMA_HFogDenst 0x003e
1401/*---- start of texture 0 setting ----
1402 */
1403#define HC_SIMA_HTX0L0BasL 0x0040
1404#define HC_SIMA_HTX0L1BasL 0x0041
1405#define HC_SIMA_HTX0L2BasL 0x0042
1406#define HC_SIMA_HTX0L3BasL 0x0043
1407#define HC_SIMA_HTX0L4BasL 0x0044
1408#define HC_SIMA_HTX0L5BasL 0x0045
1409#define HC_SIMA_HTX0L6BasL 0x0046
1410#define HC_SIMA_HTX0L7BasL 0x0047
1411#define HC_SIMA_HTX0L8BasL 0x0048
1412#define HC_SIMA_HTX0L9BasL 0x0049
1413#define HC_SIMA_HTX0LaBasL 0x004a
1414#define HC_SIMA_HTX0LbBasL 0x004b
1415#define HC_SIMA_HTX0LcBasL 0x004c
1416#define HC_SIMA_HTX0LdBasL 0x004d
1417#define HC_SIMA_HTX0LeBasL 0x004e
1418#define HC_SIMA_HTX0LfBasL 0x004f
1419#define HC_SIMA_HTX0L10BasL 0x0050
1420#define HC_SIMA_HTX0L11BasL 0x0051
1421#define HC_SIMA_HTX0L012BasH 0x0052
1422#define HC_SIMA_HTX0L345BasH 0x0053
1423#define HC_SIMA_HTX0L678BasH 0x0054
1424#define HC_SIMA_HTX0L9abBasH 0x0055
1425#define HC_SIMA_HTX0LcdeBasH 0x0056
1426#define HC_SIMA_HTX0Lf1011BasH 0x0057
1427#define HC_SIMA_HTX0L0Pit 0x0058
1428#define HC_SIMA_HTX0L1Pit 0x0059
1429#define HC_SIMA_HTX0L2Pit 0x005a
1430#define HC_SIMA_HTX0L3Pit 0x005b
1431#define HC_SIMA_HTX0L4Pit 0x005c
1432#define HC_SIMA_HTX0L5Pit 0x005d
1433#define HC_SIMA_HTX0L6Pit 0x005e
1434#define HC_SIMA_HTX0L7Pit 0x005f
1435#define HC_SIMA_HTX0L8Pit 0x0060
1436#define HC_SIMA_HTX0L9Pit 0x0061
1437#define HC_SIMA_HTX0LaPit 0x0062
1438#define HC_SIMA_HTX0LbPit 0x0063
1439#define HC_SIMA_HTX0LcPit 0x0064
1440#define HC_SIMA_HTX0LdPit 0x0065
1441#define HC_SIMA_HTX0LePit 0x0066
1442#define HC_SIMA_HTX0LfPit 0x0067
1443#define HC_SIMA_HTX0L10Pit 0x0068
1444#define HC_SIMA_HTX0L11Pit 0x0069
1445#define HC_SIMA_HTX0L0_5WE 0x006a
1446#define HC_SIMA_HTX0L6_bWE 0x006b
1447#define HC_SIMA_HTX0Lc_11WE 0x006c
1448#define HC_SIMA_HTX0L0_5HE 0x006d
1449#define HC_SIMA_HTX0L6_bHE 0x006e
1450#define HC_SIMA_HTX0Lc_11HE 0x006f
1451#define HC_SIMA_HTX0L0OS 0x0070
1452#define HC_SIMA_HTX0TB 0x0071
1453#define HC_SIMA_HTX0MPMD 0x0072
1454#define HC_SIMA_HTX0CLODu 0x0073
1455#define HC_SIMA_HTX0FM 0x0074
1456#define HC_SIMA_HTX0TRCH 0x0075
1457#define HC_SIMA_HTX0TRCL 0x0076
1458#define HC_SIMA_HTX0TBC 0x0077
1459#define HC_SIMA_HTX0TRAH 0x0078
1460#define HC_SIMA_HTX0TBLCsat 0x0079
1461#define HC_SIMA_HTX0TBLCop 0x007a
1462#define HC_SIMA_HTX0TBLMPfog 0x007b
1463#define HC_SIMA_HTX0TBLAsat 0x007c
1464#define HC_SIMA_HTX0TBLRCa 0x007d
1465#define HC_SIMA_HTX0TBLRCb 0x007e
1466#define HC_SIMA_HTX0TBLRCc 0x007f
1467#define HC_SIMA_HTX0TBLRCbias 0x0080
1468#define HC_SIMA_HTX0TBLRAa 0x0081
1469#define HC_SIMA_HTX0TBLRFog 0x0082
1470#define HC_SIMA_HTX0BumpM00 0x0083
1471#define HC_SIMA_HTX0BumpM01 0x0084
1472#define HC_SIMA_HTX0BumpM10 0x0085
1473#define HC_SIMA_HTX0BumpM11 0x0086
1474#define HC_SIMA_HTX0LScale 0x0087
1475/*---- end of texture 0 setting ---- 0x008f
1476 */
1477#define HC_SIMA_TX0TX1_OFF 0x0050
1478/*---- start of texture 1 setting ----
1479 */
1480#define HC_SIMA_HTX1L0BasL (HC_SIMA_HTX0L0BasL + HC_SIMA_TX0TX1_OFF)
1481#define HC_SIMA_HTX1L1BasL (HC_SIMA_HTX0L1BasL + HC_SIMA_TX0TX1_OFF)
1482#define HC_SIMA_HTX1L2BasL (HC_SIMA_HTX0L2BasL + HC_SIMA_TX0TX1_OFF)
1483#define HC_SIMA_HTX1L3BasL (HC_SIMA_HTX0L3BasL + HC_SIMA_TX0TX1_OFF)
1484#define HC_SIMA_HTX1L4BasL (HC_SIMA_HTX0L4BasL + HC_SIMA_TX0TX1_OFF)
1485#define HC_SIMA_HTX1L5BasL (HC_SIMA_HTX0L5BasL + HC_SIMA_TX0TX1_OFF)
1486#define HC_SIMA_HTX1L6BasL (HC_SIMA_HTX0L6BasL + HC_SIMA_TX0TX1_OFF)
1487#define HC_SIMA_HTX1L7BasL (HC_SIMA_HTX0L7BasL + HC_SIMA_TX0TX1_OFF)
1488#define HC_SIMA_HTX1L8BasL (HC_SIMA_HTX0L8BasL + HC_SIMA_TX0TX1_OFF)
1489#define HC_SIMA_HTX1L9BasL (HC_SIMA_HTX0L9BasL + HC_SIMA_TX0TX1_OFF)
1490#define HC_SIMA_HTX1LaBasL (HC_SIMA_HTX0LaBasL + HC_SIMA_TX0TX1_OFF)
1491#define HC_SIMA_HTX1LbBasL (HC_SIMA_HTX0LbBasL + HC_SIMA_TX0TX1_OFF)
1492#define HC_SIMA_HTX1LcBasL (HC_SIMA_HTX0LcBasL + HC_SIMA_TX0TX1_OFF)
1493#define HC_SIMA_HTX1LdBasL (HC_SIMA_HTX0LdBasL + HC_SIMA_TX0TX1_OFF)
1494#define HC_SIMA_HTX1LeBasL (HC_SIMA_HTX0LeBasL + HC_SIMA_TX0TX1_OFF)
1495#define HC_SIMA_HTX1LfBasL (HC_SIMA_HTX0LfBasL + HC_SIMA_TX0TX1_OFF)
1496#define HC_SIMA_HTX1L10BasL (HC_SIMA_HTX0L10BasL + HC_SIMA_TX0TX1_OFF)
1497#define HC_SIMA_HTX1L11BasL (HC_SIMA_HTX0L11BasL + HC_SIMA_TX0TX1_OFF)
1498#define HC_SIMA_HTX1L012BasH (HC_SIMA_HTX0L012BasH + HC_SIMA_TX0TX1_OFF)
1499#define HC_SIMA_HTX1L345BasH (HC_SIMA_HTX0L345BasH + HC_SIMA_TX0TX1_OFF)
1500#define HC_SIMA_HTX1L678BasH (HC_SIMA_HTX0L678BasH + HC_SIMA_TX0TX1_OFF)
1501#define HC_SIMA_HTX1L9abBasH (HC_SIMA_HTX0L9abBasH + HC_SIMA_TX0TX1_OFF)
1502#define HC_SIMA_HTX1LcdeBasH (HC_SIMA_HTX0LcdeBasH + HC_SIMA_TX0TX1_OFF)
1503#define HC_SIMA_HTX1Lf1011BasH (HC_SIMA_HTX0Lf1011BasH + HC_SIMA_TX0TX1_OFF)
1504#define HC_SIMA_HTX1L0Pit (HC_SIMA_HTX0L0Pit + HC_SIMA_TX0TX1_OFF)
1505#define HC_SIMA_HTX1L1Pit (HC_SIMA_HTX0L1Pit + HC_SIMA_TX0TX1_OFF)
1506#define HC_SIMA_HTX1L2Pit (HC_SIMA_HTX0L2Pit + HC_SIMA_TX0TX1_OFF)
1507#define HC_SIMA_HTX1L3Pit (HC_SIMA_HTX0L3Pit + HC_SIMA_TX0TX1_OFF)
1508#define HC_SIMA_HTX1L4Pit (HC_SIMA_HTX0L4Pit + HC_SIMA_TX0TX1_OFF)
1509#define HC_SIMA_HTX1L5Pit (HC_SIMA_HTX0L5Pit + HC_SIMA_TX0TX1_OFF)
1510#define HC_SIMA_HTX1L6Pit (HC_SIMA_HTX0L6Pit + HC_SIMA_TX0TX1_OFF)
1511#define HC_SIMA_HTX1L7Pit (HC_SIMA_HTX0L7Pit + HC_SIMA_TX0TX1_OFF)
1512#define HC_SIMA_HTX1L8Pit (HC_SIMA_HTX0L8Pit + HC_SIMA_TX0TX1_OFF)
1513#define HC_SIMA_HTX1L9Pit (HC_SIMA_HTX0L9Pit + HC_SIMA_TX0TX1_OFF)
1514#define HC_SIMA_HTX1LaPit (HC_SIMA_HTX0LaPit + HC_SIMA_TX0TX1_OFF)
1515#define HC_SIMA_HTX1LbPit (HC_SIMA_HTX0LbPit + HC_SIMA_TX0TX1_OFF)
1516#define HC_SIMA_HTX1LcPit (HC_SIMA_HTX0LcPit + HC_SIMA_TX0TX1_OFF)
1517#define HC_SIMA_HTX1LdPit (HC_SIMA_HTX0LdPit + HC_SIMA_TX0TX1_OFF)
1518#define HC_SIMA_HTX1LePit (HC_SIMA_HTX0LePit + HC_SIMA_TX0TX1_OFF)
1519#define HC_SIMA_HTX1LfPit (HC_SIMA_HTX0LfPit + HC_SIMA_TX0TX1_OFF)
1520#define HC_SIMA_HTX1L10Pit (HC_SIMA_HTX0L10Pit + HC_SIMA_TX0TX1_OFF)
1521#define HC_SIMA_HTX1L11Pit (HC_SIMA_HTX0L11Pit + HC_SIMA_TX0TX1_OFF)
1522#define HC_SIMA_HTX1L0_5WE (HC_SIMA_HTX0L0_5WE + HC_SIMA_TX0TX1_OFF)
1523#define HC_SIMA_HTX1L6_bWE (HC_SIMA_HTX0L6_bWE + HC_SIMA_TX0TX1_OFF)
1524#define HC_SIMA_HTX1Lc_11WE (HC_SIMA_HTX0Lc_11WE + HC_SIMA_TX0TX1_OFF)
1525#define HC_SIMA_HTX1L0_5HE (HC_SIMA_HTX0L0_5HE + HC_SIMA_TX0TX1_OFF)
1526#define HC_SIMA_HTX1L6_bHE (HC_SIMA_HTX0L6_bHE + HC_SIMA_TX0TX1_OFF)
1527#define HC_SIMA_HTX1Lc_11HE (HC_SIMA_HTX0Lc_11HE + HC_SIMA_TX0TX1_OFF)
1528#define HC_SIMA_HTX1L0OS (HC_SIMA_HTX0L0OS + HC_SIMA_TX0TX1_OFF)
1529#define HC_SIMA_HTX1TB (HC_SIMA_HTX0TB + HC_SIMA_TX0TX1_OFF)
1530#define HC_SIMA_HTX1MPMD (HC_SIMA_HTX0MPMD + HC_SIMA_TX0TX1_OFF)
1531#define HC_SIMA_HTX1CLODu (HC_SIMA_HTX0CLODu + HC_SIMA_TX0TX1_OFF)
1532#define HC_SIMA_HTX1FM (HC_SIMA_HTX0FM + HC_SIMA_TX0TX1_OFF)
1533#define HC_SIMA_HTX1TRCH (HC_SIMA_HTX0TRCH + HC_SIMA_TX0TX1_OFF)
1534#define HC_SIMA_HTX1TRCL (HC_SIMA_HTX0TRCL + HC_SIMA_TX0TX1_OFF)
1535#define HC_SIMA_HTX1TBC (HC_SIMA_HTX0TBC + HC_SIMA_TX0TX1_OFF)
1536#define HC_SIMA_HTX1TRAH (HC_SIMA_HTX0TRAH + HC_SIMA_TX0TX1_OFF)
1537#define HC_SIMA_HTX1LTC (HC_SIMA_HTX0LTC + HC_SIMA_TX0TX1_OFF)
1538#define HC_SIMA_HTX1LTA (HC_SIMA_HTX0LTA + HC_SIMA_TX0TX1_OFF)
1539#define HC_SIMA_HTX1TBLCsat (HC_SIMA_HTX0TBLCsat + HC_SIMA_TX0TX1_OFF)
1540#define HC_SIMA_HTX1TBLCop (HC_SIMA_HTX0TBLCop + HC_SIMA_TX0TX1_OFF)
1541#define HC_SIMA_HTX1TBLMPfog (HC_SIMA_HTX0TBLMPfog + HC_SIMA_TX0TX1_OFF)
1542#define HC_SIMA_HTX1TBLAsat (HC_SIMA_HTX0TBLAsat + HC_SIMA_TX0TX1_OFF)
1543#define HC_SIMA_HTX1TBLRCa (HC_SIMA_HTX0TBLRCa + HC_SIMA_TX0TX1_OFF)
1544#define HC_SIMA_HTX1TBLRCb (HC_SIMA_HTX0TBLRCb + HC_SIMA_TX0TX1_OFF)
1545#define HC_SIMA_HTX1TBLRCc (HC_SIMA_HTX0TBLRCc + HC_SIMA_TX0TX1_OFF)
1546#define HC_SIMA_HTX1TBLRCbias (HC_SIMA_HTX0TBLRCbias + HC_SIMA_TX0TX1_OFF)
1547#define HC_SIMA_HTX1TBLRAa (HC_SIMA_HTX0TBLRAa + HC_SIMA_TX0TX1_OFF)
1548#define HC_SIMA_HTX1TBLRFog (HC_SIMA_HTX0TBLRFog + HC_SIMA_TX0TX1_OFF)
1549#define HC_SIMA_HTX1BumpM00 (HC_SIMA_HTX0BumpM00 + HC_SIMA_TX0TX1_OFF)
1550#define HC_SIMA_HTX1BumpM01 (HC_SIMA_HTX0BumpM01 + HC_SIMA_TX0TX1_OFF)
1551#define HC_SIMA_HTX1BumpM10 (HC_SIMA_HTX0BumpM10 + HC_SIMA_TX0TX1_OFF)
1552#define HC_SIMA_HTX1BumpM11 (HC_SIMA_HTX0BumpM11 + HC_SIMA_TX0TX1_OFF)
1553#define HC_SIMA_HTX1LScale (HC_SIMA_HTX0LScale + HC_SIMA_TX0TX1_OFF)
1554/*---- end of texture 1 setting ---- 0xaf
1555 */
1556#define HC_SIMA_HTXSMD 0x00b0
1557#define HC_SIMA_HenFIFOAT 0x00b1
1558#define HC_SIMA_HFBDrawFirst 0x00b2
1559#define HC_SIMA_HFBBasL 0x00b3
1560#define HC_SIMA_HTArbRCM 0x00b4
1561#define HC_SIMA_HTArbRZ 0x00b5
1562#define HC_SIMA_HTArbWZ 0x00b6
1563#define HC_SIMA_HTArbRTX 0x00b7
1564#define HC_SIMA_HTArbRCW 0x00b8
1565#define HC_SIMA_HTArbE2 0x00b9
1566#define HC_SIMA_HGEMITout 0x00ba
1567#define HC_SIMA_HFthRTXD 0x00bb
1568#define HC_SIMA_HFthRTXA 0x00bc
1569/* Define the texture palette 0
1570 */
1571#define HC_SIMA_HTP0 0x0100
1572#define HC_SIMA_HTP1 0x0200
1573#define HC_SIMA_FOGTABLE 0x0300
1574#define HC_SIMA_STIPPLE 0x0400
1575#define HC_SIMA_HE3Fire 0x0440
1576#define HC_SIMA_TRANS_SET 0x0441
1577#define HC_SIMA_HREngSt 0x0442
1578#define HC_SIMA_HRFIFOempty 0x0443
1579#define HC_SIMA_HRFIFOfull 0x0444
1580#define HC_SIMA_HRErr 0x0445
1581#define HC_SIMA_FIFOstatus 0x0446
1582
1583/******************************************************************************
1584** Define the AGP command header.
1585******************************************************************************/
1586#define HC_ACMD_MASK 0xfe000000
1587#define HC_ACMD_SUB_MASK 0x0c000000
1588#define HC_ACMD_HCmdA 0xee000000
1589#define HC_ACMD_HCmdB 0xec000000
1590#define HC_ACMD_HCmdC 0xea000000
1591#define HC_ACMD_H1 0xf0000000
1592#define HC_ACMD_H2 0xf2000000
1593#define HC_ACMD_H3 0xf4000000
1594#define HC_ACMD_H4 0xf6000000
1595
1596#define HC_ACMD_H1IO_MASK 0x000001ff
1597#define HC_ACMD_H2IO1_MASK 0x001ff000
1598#define HC_ACMD_H2IO2_MASK 0x000001ff
1599#define HC_ACMD_H2IO1_SHIFT 12
1600#define HC_ACMD_H2IO2_SHIFT 0
1601#define HC_ACMD_H3IO_MASK 0x000001ff
1602#define HC_ACMD_H3COUNT_MASK 0x01fff000
1603#define HC_ACMD_H3COUNT_SHIFT 12
1604#define HC_ACMD_H4ID_MASK 0x000001ff
1605#define HC_ACMD_H4COUNT_MASK 0x01fffe00
1606#define HC_ACMD_H4COUNT_SHIFT 9
1607
1608/********************************************************************************
1609** Define Header
1610********************************************************************************/
1611#define HC_HEADER2 0xF210F110
1612
1613/********************************************************************************
1614** Define Dummy Value
1615********************************************************************************/
1616#define HC_DUMMY 0xCCCCCCCC
1617/********************************************************************************
1618** Define for DMA use
1619********************************************************************************/
1620#define HALCYON_HEADER2 0XF210F110
1621#define HALCYON_FIRECMD 0XEE100000
1622#define HALCYON_FIREMASK 0XFFF00000
1623#define HALCYON_CMDB 0XEC000000
1624#define HALCYON_CMDBMASK 0XFFFE0000
1625#define HALCYON_SUB_ADDR0 0X00000000
1626#define HALCYON_HEADER1MASK 0XFFFFFC00
1627#define HALCYON_HEADER1 0XF0000000
1628#define HC_SubA_HAGPBstL 0x0060
1629#define HC_SubA_HAGPBendL 0x0061
1630#define HC_SubA_HAGPCMNT 0x0062
1631#define HC_SubA_HAGPBpL 0x0063
1632#define HC_SubA_HAGPBpH 0x0064
1633#define HC_HAGPCMNT_MASK 0x00800000
1634#define HC_HCmdErrClr_MASK 0x00400000
1635#define HC_HAGPBendH_MASK 0x0000ff00
1636#define HC_HAGPBstH_MASK 0x000000ff
1637#define HC_HAGPBendH_SHIFT 8
1638#define HC_HAGPBstH_SHIFT 0
1639#define HC_HAGPBpL_MASK 0x00fffffc
1640#define HC_HAGPBpID_MASK 0x00000003
1641#define HC_HAGPBpID_PAUSE 0x00000000
1642#define HC_HAGPBpID_JUMP 0x00000001
1643#define HC_HAGPBpID_STOP 0x00000002
1644#define HC_HAGPBpH_MASK 0x00ffffff
1645
1646
1647#define VIA_VIDEO_HEADER5 0xFE040000
1648#define VIA_VIDEO_HEADER6 0xFE050000
1649#define VIA_VIDEO_HEADER7 0xFE060000
1650#define VIA_VIDEOMASK 0xFFFF0000
1651#endif
diff --git a/drivers/char/drm/via_dma.c b/drivers/char/drm/via_dma.c
new file mode 100644
index 000000000000..82f839451622
--- /dev/null
+++ b/drivers/char/drm/via_dma.c
@@ -0,0 +1,741 @@
1/* via_dma.c -- DMA support for the VIA Unichrome/Pro
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
7 * All Rights Reserved.
8 *
9 * Copyright 2004 The Unichrome project.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sub license,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the
20 * next paragraph) shall be included in all copies or substantial portions
21 * of the Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
26 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
27 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
28 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
29 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 *
31 * Authors:
32 * Tungsten Graphics,
33 * Erdi Chen,
34 * Thomas Hellstrom.
35 */
36
37#include "drmP.h"
38#include "drm.h"
39#include "via_drm.h"
40#include "via_drv.h"
41#include "via_3d_reg.h"
42
43#define CMDBUF_ALIGNMENT_SIZE (0x100)
44#define CMDBUF_ALIGNMENT_MASK (0x0ff)
45
46/* defines for VIA 3D registers */
47#define VIA_REG_STATUS 0x400
48#define VIA_REG_TRANSET 0x43C
49#define VIA_REG_TRANSPACE 0x440
50
51/* VIA_REG_STATUS(0x400): Engine Status */
52#define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */
53#define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */
54#define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */
55#define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */
56
57#define SetReg2DAGP(nReg, nData) { \
58 *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1; \
59 *((uint32_t *)(vb) + 1) = (nData); \
60 vb = ((uint32_t *)vb) + 2; \
61 dev_priv->dma_low +=8; \
62}
63
64#define via_flush_write_combine() DRM_MEMORYBARRIER()
65
66#define VIA_OUT_RING_QW(w1,w2) \
67 *vb++ = (w1); \
68 *vb++ = (w2); \
69 dev_priv->dma_low += 8;
70
71static void via_cmdbuf_start(drm_via_private_t * dev_priv);
72static void via_cmdbuf_pause(drm_via_private_t * dev_priv);
73static void via_cmdbuf_reset(drm_via_private_t * dev_priv);
74static void via_cmdbuf_rewind(drm_via_private_t * dev_priv);
75static int via_wait_idle(drm_via_private_t * dev_priv);
76static void via_pad_cache(drm_via_private_t *dev_priv, int qwords);
77
78
79/*
80 * Free space in command buffer.
81 */
82
83static uint32_t
84via_cmdbuf_space(drm_via_private_t *dev_priv)
85{
86 uint32_t agp_base = dev_priv->dma_offset +
87 (uint32_t) dev_priv->agpAddr;
88 uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
89
90 return ((hw_addr <= dev_priv->dma_low) ?
91 (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :
92 (hw_addr - dev_priv->dma_low));
93}
94
95/*
96 * How much does the command regulator lag behind?
97 */
98
99static uint32_t
100via_cmdbuf_lag(drm_via_private_t *dev_priv)
101{
102 uint32_t agp_base = dev_priv->dma_offset +
103 (uint32_t) dev_priv->agpAddr;
104 uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
105
106 return ((hw_addr <= dev_priv->dma_low) ?
107 (dev_priv->dma_low - hw_addr) :
108 (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr));
109}
110
111/*
112 * Check that the given size fits in the buffer, otherwise wait.
113 */
114
115static inline int
116via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
117{
118 uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
119 uint32_t cur_addr, hw_addr, next_addr;
120 volatile uint32_t *hw_addr_ptr;
121 uint32_t count;
122 hw_addr_ptr = dev_priv->hw_addr_ptr;
123 cur_addr = dev_priv->dma_low;
124 next_addr = cur_addr + size + 512*1024;
125 count = 1000000;
126 do {
127 hw_addr = *hw_addr_ptr - agp_base;
128 if (count-- == 0) {
129 DRM_ERROR("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n",
130 hw_addr, cur_addr, next_addr);
131 return -1;
132 }
133 } while ((cur_addr < hw_addr) && (next_addr >= hw_addr));
134 return 0;
135}
136
137
138/*
139 * Checks whether buffer head has reach the end. Rewind the ring buffer
140 * when necessary.
141 *
142 * Returns virtual pointer to ring buffer.
143 */
144
145static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv,
146 unsigned int size)
147{
148 if ((dev_priv->dma_low + size + 4*CMDBUF_ALIGNMENT_SIZE) > dev_priv->dma_high) {
149 via_cmdbuf_rewind(dev_priv);
150 }
151 if (via_cmdbuf_wait(dev_priv, size) != 0) {
152 return NULL;
153 }
154
155 return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
156}
157
158int via_dma_cleanup(drm_device_t * dev)
159{
160 if (dev->dev_private) {
161 drm_via_private_t *dev_priv =
162 (drm_via_private_t *) dev->dev_private;
163
164 if (dev_priv->ring.virtual_start) {
165 via_cmdbuf_reset(dev_priv);
166
167 drm_core_ioremapfree(&dev_priv->ring.map, dev);
168 dev_priv->ring.virtual_start = NULL;
169 }
170
171 }
172
173 return 0;
174}
175
176static int via_initialize(drm_device_t * dev,
177 drm_via_private_t * dev_priv,
178 drm_via_dma_init_t * init)
179{
180 if (!dev_priv || !dev_priv->mmio) {
181 DRM_ERROR("via_dma_init called before via_map_init\n");
182 return DRM_ERR(EFAULT);
183 }
184
185 if (dev_priv->ring.virtual_start != NULL) {
186 DRM_ERROR("%s called again without calling cleanup\n",
187 __FUNCTION__);
188 return DRM_ERR(EFAULT);
189 }
190
191 if (!dev->agp || !dev->agp->base) {
192 DRM_ERROR("%s called with no agp memory available\n",
193 __FUNCTION__);
194 return DRM_ERR(EFAULT);
195 }
196
197 dev_priv->ring.map.offset = dev->agp->base + init->offset;
198 dev_priv->ring.map.size = init->size;
199 dev_priv->ring.map.type = 0;
200 dev_priv->ring.map.flags = 0;
201 dev_priv->ring.map.mtrr = 0;
202
203 drm_core_ioremap(&dev_priv->ring.map, dev);
204
205 if (dev_priv->ring.map.handle == NULL) {
206 via_dma_cleanup(dev);
207 DRM_ERROR("can not ioremap virtual address for"
208 " ring buffer\n");
209 return DRM_ERR(ENOMEM);
210 }
211
212 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
213
214 dev_priv->dma_ptr = dev_priv->ring.virtual_start;
215 dev_priv->dma_low = 0;
216 dev_priv->dma_high = init->size;
217 dev_priv->dma_wrap = init->size;
218 dev_priv->dma_offset = init->offset;
219 dev_priv->last_pause_ptr = NULL;
220 dev_priv->hw_addr_ptr = dev_priv->mmio->handle + init->reg_pause_addr;
221
222 via_cmdbuf_start(dev_priv);
223
224 return 0;
225}
226
227int via_dma_init(DRM_IOCTL_ARGS)
228{
229 DRM_DEVICE;
230 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
231 drm_via_dma_init_t init;
232 int retcode = 0;
233
234 DRM_COPY_FROM_USER_IOCTL(init, (drm_via_dma_init_t *) data,
235 sizeof(init));
236
237 switch (init.func) {
238 case VIA_INIT_DMA:
239 if (!capable(CAP_SYS_ADMIN))
240 retcode = DRM_ERR(EPERM);
241 else
242 retcode = via_initialize(dev, dev_priv, &init);
243 break;
244 case VIA_CLEANUP_DMA:
245 if (!capable(CAP_SYS_ADMIN))
246 retcode = DRM_ERR(EPERM);
247 else
248 retcode = via_dma_cleanup(dev);
249 break;
250 case VIA_DMA_INITIALIZED:
251 retcode = (dev_priv->ring.virtual_start != NULL) ?
252 0: DRM_ERR( EFAULT );
253 break;
254 default:
255 retcode = DRM_ERR(EINVAL);
256 break;
257 }
258
259 return retcode;
260}
261
262
263
264static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd)
265{
266 drm_via_private_t *dev_priv;
267 uint32_t *vb;
268 int ret;
269
270 dev_priv = (drm_via_private_t *) dev->dev_private;
271
272 if (dev_priv->ring.virtual_start == NULL) {
273 DRM_ERROR("%s called without initializing AGP ring buffer.\n",
274 __FUNCTION__);
275 return DRM_ERR(EFAULT);
276 }
277
278 if (cmd->size > VIA_PCI_BUF_SIZE) {
279 return DRM_ERR(ENOMEM);
280 }
281
282
283 if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
284 return DRM_ERR(EFAULT);
285
286 /*
287 * Running this function on AGP memory is dead slow. Therefore
288 * we run it on a temporary cacheable system memory buffer and
289 * copy it to AGP memory when ready.
290 */
291
292
293 if ((ret = via_verify_command_stream((uint32_t *)dev_priv->pci_buf, cmd->size, dev, 1))) {
294 return ret;
295 }
296
297
298 vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size);
299 if (vb == NULL) {
300 return DRM_ERR(EAGAIN);
301 }
302
303 memcpy(vb, dev_priv->pci_buf, cmd->size);
304
305 dev_priv->dma_low += cmd->size;
306
307 /*
308 * Small submissions somehow stalls the CPU. (AGP cache effects?)
309 * pad to greater size.
310 */
311
312 if (cmd->size < 0x100)
313 via_pad_cache(dev_priv,(0x100 - cmd->size) >> 3);
314 via_cmdbuf_pause(dev_priv);
315
316 return 0;
317}
318
319int via_driver_dma_quiescent(drm_device_t * dev)
320{
321 drm_via_private_t *dev_priv = dev->dev_private;
322
323 if (!via_wait_idle(dev_priv)) {
324 return DRM_ERR(EBUSY);
325 }
326 return 0;
327}
328
329int via_flush_ioctl(DRM_IOCTL_ARGS)
330{
331 DRM_DEVICE;
332
333 LOCK_TEST_WITH_RETURN( dev, filp );
334
335 return via_driver_dma_quiescent(dev);
336}
337
338int via_cmdbuffer(DRM_IOCTL_ARGS)
339{
340 DRM_DEVICE;
341 drm_via_cmdbuffer_t cmdbuf;
342 int ret;
343
344 LOCK_TEST_WITH_RETURN( dev, filp );
345
346 DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t *) data,
347 sizeof(cmdbuf));
348
349 DRM_DEBUG("via cmdbuffer, buf %p size %lu\n", cmdbuf.buf, cmdbuf.size);
350
351 ret = via_dispatch_cmdbuffer(dev, &cmdbuf);
352 if (ret) {
353 return ret;
354 }
355
356 return 0;
357}
358
359extern int
360via_parse_command_stream(drm_device_t *dev, const uint32_t * buf, unsigned int size);
361static int via_dispatch_pci_cmdbuffer(drm_device_t * dev,
362 drm_via_cmdbuffer_t * cmd)
363{
364 drm_via_private_t *dev_priv = dev->dev_private;
365 int ret;
366
367 if (cmd->size > VIA_PCI_BUF_SIZE) {
368 return DRM_ERR(ENOMEM);
369 }
370 if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
371 return DRM_ERR(EFAULT);
372
373 if ((ret = via_verify_command_stream((uint32_t *)dev_priv->pci_buf, cmd->size, dev, 0))) {
374 return ret;
375 }
376
377 ret = via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf, cmd->size);
378 return ret;
379}
380
381int via_pci_cmdbuffer(DRM_IOCTL_ARGS)
382{
383 DRM_DEVICE;
384 drm_via_cmdbuffer_t cmdbuf;
385 int ret;
386
387 LOCK_TEST_WITH_RETURN( dev, filp );
388
389 DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t *) data,
390 sizeof(cmdbuf));
391
392 DRM_DEBUG("via_pci_cmdbuffer, buf %p size %lu\n", cmdbuf.buf,
393 cmdbuf.size);
394
395 ret = via_dispatch_pci_cmdbuffer(dev, &cmdbuf);
396 if (ret) {
397 return ret;
398 }
399
400 return 0;
401}
402
403
404static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv,
405 uint32_t * vb, int qw_count)
406{
407 for (; qw_count > 0; --qw_count) {
408 VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY);
409 }
410 return vb;
411}
412
413
414/*
415 * This function is used internally by ring buffer mangement code.
416 *
417 * Returns virtual pointer to ring buffer.
418 */
419static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv)
420{
421 return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
422}
423
424/*
425 * Hooks a segment of data into the tail of the ring-buffer by
426 * modifying the pause address stored in the buffer itself. If
427 * the regulator has already paused, restart it.
428 */
429static int via_hook_segment(drm_via_private_t *dev_priv,
430 uint32_t pause_addr_hi, uint32_t pause_addr_lo,
431 int no_pci_fire)
432{
433 int paused, count;
434 volatile uint32_t *paused_at = dev_priv->last_pause_ptr;
435
436 via_flush_write_combine();
437 while(! *(via_get_dma(dev_priv)-1));
438 *dev_priv->last_pause_ptr = pause_addr_lo;
439 via_flush_write_combine();
440
441 /*
442 * The below statement is inserted to really force the flush.
443 * Not sure it is needed.
444 */
445
446 while(! *dev_priv->last_pause_ptr);
447 dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1;
448 while(! *dev_priv->last_pause_ptr);
449
450
451 paused = 0;
452 count = 20;
453
454 while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--);
455 if ((count <= 8) && (count >= 0)) {
456 uint32_t rgtr, ptr;
457 rgtr = *(dev_priv->hw_addr_ptr);
458 ptr = ((char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) +
459 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4 -
460 CMDBUF_ALIGNMENT_SIZE;
461 if (rgtr <= ptr) {
462 DRM_ERROR("Command regulator\npaused at count %d, address %x, "
463 "while current pause address is %x.\n"
464 "Please mail this message to "
465 "<unichrome-devel@lists.sourceforge.net>\n",
466 count, rgtr, ptr);
467 }
468 }
469
470 if (paused && !no_pci_fire) {
471 uint32_t rgtr,ptr;
472 uint32_t ptr_low;
473
474 count = 1000000;
475 while ((VIA_READ(VIA_REG_STATUS) & VIA_CMD_RGTR_BUSY) && count--);
476
477 rgtr = *(dev_priv->hw_addr_ptr);
478 ptr = ((char *)paused_at - dev_priv->dma_ptr) +
479 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
480
481
482 ptr_low = (ptr > 3*CMDBUF_ALIGNMENT_SIZE) ?
483 ptr - 3*CMDBUF_ALIGNMENT_SIZE : 0;
484 if (rgtr <= ptr && rgtr >= ptr_low) {
485 VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
486 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
487 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
488 }
489 }
490 return paused;
491}
492
493
494
495static int via_wait_idle(drm_via_private_t * dev_priv)
496{
497 int count = 10000000;
498 while (count-- && (VIA_READ(VIA_REG_STATUS) &
499 (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY |
500 VIA_3D_ENG_BUSY))) ;
501 return count;
502}
503
504static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type,
505 uint32_t addr, uint32_t *cmd_addr_hi,
506 uint32_t *cmd_addr_lo,
507 int skip_wait)
508{
509 uint32_t agp_base;
510 uint32_t cmd_addr, addr_lo, addr_hi;
511 uint32_t *vb;
512 uint32_t qw_pad_count;
513
514 if (!skip_wait)
515 via_cmdbuf_wait(dev_priv, 2*CMDBUF_ALIGNMENT_SIZE);
516
517 vb = via_get_dma(dev_priv);
518 VIA_OUT_RING_QW( HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
519 (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);
520 agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
521 qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
522 ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
523
524
525 cmd_addr = (addr) ? addr :
526 agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
527 addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) |
528 (cmd_addr & HC_HAGPBpL_MASK));
529 addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24));
530
531 vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
532 VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi,
533 *cmd_addr_lo = addr_lo);
534 return vb;
535}
536
537
538
539
540static void via_cmdbuf_start(drm_via_private_t * dev_priv)
541{
542 uint32_t pause_addr_lo, pause_addr_hi;
543 uint32_t start_addr, start_addr_lo;
544 uint32_t end_addr, end_addr_lo;
545 uint32_t command;
546 uint32_t agp_base;
547
548
549 dev_priv->dma_low = 0;
550
551 agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
552 start_addr = agp_base;
553 end_addr = agp_base + dev_priv->dma_high;
554
555 start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF));
556 end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
557 command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
558 ((end_addr & 0xff000000) >> 16));
559
560 dev_priv->last_pause_ptr =
561 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,
562 &pause_addr_hi, & pause_addr_lo, 1) - 1;
563
564 via_flush_write_combine();
565 while(! *dev_priv->last_pause_ptr);
566
567 VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
568 VIA_WRITE(VIA_REG_TRANSPACE, command);
569 VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo);
570 VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo);
571
572 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
573 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
574
575 VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
576}
577
578static void via_pad_cache(drm_via_private_t *dev_priv, int qwords)
579{
580 uint32_t *vb;
581
582 via_cmdbuf_wait(dev_priv, qwords + 2);
583 vb = via_get_dma(dev_priv);
584 VIA_OUT_RING_QW( HC_HEADER2, HC_ParaType_NotTex << 16);
585 via_align_buffer(dev_priv,vb,qwords);
586}
587
588static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)
589{
590 uint32_t *vb = via_get_dma(dev_priv);
591 SetReg2DAGP(0x0C, (0 | (0 << 16)));
592 SetReg2DAGP(0x10, 0 | (0 << 16));
593 SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
594}
595
596
597static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
598{
599 uint32_t agp_base;
600 uint32_t pause_addr_lo, pause_addr_hi;
601 uint32_t jump_addr_lo, jump_addr_hi;
602 volatile uint32_t *last_pause_ptr;
603 uint32_t dma_low_save1, dma_low_save2;
604
605 agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
606 via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
607 &jump_addr_lo, 0);
608
609 dev_priv->dma_wrap = dev_priv->dma_low;
610
611
612 /*
613 * Wrap command buffer to the beginning.
614 */
615
616 dev_priv->dma_low = 0;
617 if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) {
618 DRM_ERROR("via_cmdbuf_jump failed\n");
619 }
620
621 via_dummy_bitblt(dev_priv);
622 via_dummy_bitblt(dev_priv);
623
624 last_pause_ptr = via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
625 &pause_addr_lo, 0) -1;
626 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
627 &pause_addr_lo, 0);
628
629 *last_pause_ptr = pause_addr_lo;
630 dma_low_save1 = dev_priv->dma_low;
631
632 /*
633 * Now, set a trap that will pause the regulator if it tries to rerun the old
634 * command buffer. (Which may happen if via_hook_segment detecs a command regulator pause
635 * and reissues the jump command over PCI, while the regulator has already taken the jump
636 * and actually paused at the current buffer end).
637 * There appears to be no other way to detect this condition, since the hw_addr_pointer
638 * does not seem to get updated immediately when a jump occurs.
639 */
640
641 last_pause_ptr = via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
642 &pause_addr_lo, 0) -1;
643 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
644 &pause_addr_lo, 0);
645 *last_pause_ptr = pause_addr_lo;
646
647 dma_low_save2 = dev_priv->dma_low;
648 dev_priv->dma_low = dma_low_save1;
649 via_hook_segment( dev_priv, jump_addr_hi, jump_addr_lo, 0);
650 dev_priv->dma_low = dma_low_save2;
651 via_hook_segment( dev_priv, pause_addr_hi, pause_addr_lo, 0);
652}
653
654
655static void via_cmdbuf_rewind(drm_via_private_t * dev_priv)
656{
657 via_cmdbuf_jump(dev_priv);
658}
659
660static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)
661{
662 uint32_t pause_addr_lo, pause_addr_hi;
663
664 via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0);
665 via_hook_segment( dev_priv, pause_addr_hi, pause_addr_lo, 0);
666}
667
668
669static void via_cmdbuf_pause(drm_via_private_t * dev_priv)
670{
671 via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE);
672}
673
674static void via_cmdbuf_reset(drm_via_private_t * dev_priv)
675{
676 via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP);
677 via_wait_idle(dev_priv);
678}
679
680/*
681 * User interface to the space and lag functions.
682 */
683
684int
685via_cmdbuf_size(DRM_IOCTL_ARGS)
686{
687 DRM_DEVICE;
688 drm_via_cmdbuf_size_t d_siz;
689 int ret = 0;
690 uint32_t tmp_size, count;
691 drm_via_private_t *dev_priv;
692
693 DRM_DEBUG("via cmdbuf_size\n");
694 LOCK_TEST_WITH_RETURN( dev, filp );
695
696 dev_priv = (drm_via_private_t *) dev->dev_private;
697
698 if (dev_priv->ring.virtual_start == NULL) {
699 DRM_ERROR("%s called without initializing AGP ring buffer.\n",
700 __FUNCTION__);
701 return DRM_ERR(EFAULT);
702 }
703
704 DRM_COPY_FROM_USER_IOCTL(d_siz, (drm_via_cmdbuf_size_t *) data,
705 sizeof(d_siz));
706
707
708 count = 1000000;
709 tmp_size = d_siz.size;
710 switch(d_siz.func) {
711 case VIA_CMDBUF_SPACE:
712 while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz.size) && count--) {
713 if (!d_siz.wait) {
714 break;
715 }
716 }
717 if (!count) {
718 DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n");
719 ret = DRM_ERR(EAGAIN);
720 }
721 break;
722 case VIA_CMDBUF_LAG:
723 while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz.size) && count--) {
724 if (!d_siz.wait) {
725 break;
726 }
727 }
728 if (!count) {
729 DRM_ERROR("VIA_CMDBUF_LAG timed out.\n");
730 ret = DRM_ERR(EAGAIN);
731 }
732 break;
733 default:
734 ret = DRM_ERR(EFAULT);
735 }
736 d_siz.size = tmp_size;
737
738 DRM_COPY_TO_USER_IOCTL((drm_via_cmdbuf_size_t *) data, d_siz,
739 sizeof(d_siz));
740 return ret;
741}
diff --git a/drivers/char/drm/via_drm.h b/drivers/char/drm/via_drm.h
new file mode 100644
index 000000000000..4588c9bd1816
--- /dev/null
+++ b/drivers/char/drm/via_drm.h
@@ -0,0 +1,243 @@
1/*
2 * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef _VIA_DRM_H_
25#define _VIA_DRM_H_
26
27/* WARNING: These defines must be the same as what the Xserver uses.
28 * if you change them, you must change the defines in the Xserver.
29 */
30
31#ifndef _VIA_DEFINES_
32#define _VIA_DEFINES_
33
34#ifndef __KERNEL__
35#include "via_drmclient.h"
36#endif
37
38#define VIA_NR_SAREA_CLIPRECTS 8
39#define VIA_NR_XVMC_PORTS 10
40#define VIA_NR_XVMC_LOCKS 5
41#define VIA_MAX_CACHELINE_SIZE 64
42#define XVMCLOCKPTR(saPriv,lockNo) \
43 ((volatile drm_hw_lock_t *)(((((unsigned long) (saPriv)->XvMCLockArea) + \
44 (VIA_MAX_CACHELINE_SIZE - 1)) & \
45 ~(VIA_MAX_CACHELINE_SIZE - 1)) + \
46 VIA_MAX_CACHELINE_SIZE*(lockNo)))
47
48/* Each region is a minimum of 64k, and there are at most 64 of them.
49 */
50#define VIA_NR_TEX_REGIONS 64
51#define VIA_LOG_MIN_TEX_REGION_SIZE 16
52#endif
53
54#define VIA_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */
55#define VIA_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */
56#define VIA_UPLOAD_CTX 0x4
57#define VIA_UPLOAD_BUFFERS 0x8
58#define VIA_UPLOAD_TEX0 0x10
59#define VIA_UPLOAD_TEX1 0x20
60#define VIA_UPLOAD_CLIPRECTS 0x40
61#define VIA_UPLOAD_ALL 0xff
62
63/* VIA specific ioctls */
64#define DRM_VIA_ALLOCMEM 0x00
65#define DRM_VIA_FREEMEM 0x01
66#define DRM_VIA_AGP_INIT 0x02
67#define DRM_VIA_FB_INIT 0x03
68#define DRM_VIA_MAP_INIT 0x04
69#define DRM_VIA_DEC_FUTEX 0x05
70#define NOT_USED
71#define DRM_VIA_DMA_INIT 0x07
72#define DRM_VIA_CMDBUFFER 0x08
73#define DRM_VIA_FLUSH 0x09
74#define DRM_VIA_PCICMD 0x0a
75#define DRM_VIA_CMDBUF_SIZE 0x0b
76#define NOT_USED
77#define DRM_VIA_WAIT_IRQ 0x0d
78
79#define DRM_IOCTL_VIA_ALLOCMEM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t)
80#define DRM_IOCTL_VIA_FREEMEM DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t)
81#define DRM_IOCTL_VIA_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t)
82#define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t)
83#define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t)
84#define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t)
85#define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t)
86#define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
87#define DRM_IOCTL_VIA_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_VIA_FLUSH)
88#define DRM_IOCTL_VIA_PCICMD DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
89#define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \
90 drm_via_cmdbuf_size_t)
91#define DRM_IOCTL_VIA_WAIT_IRQ DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t)
92
93/* Indices into buf.Setup where various bits of state are mirrored per
94 * context and per buffer. These can be fired at the card as a unit,
95 * or in a piecewise fashion as required.
96 */
97
98#define VIA_TEX_SETUP_SIZE 8
99
100/* Flags for clear ioctl
101 */
102#define VIA_FRONT 0x1
103#define VIA_BACK 0x2
104#define VIA_DEPTH 0x4
105#define VIA_STENCIL 0x8
106#define VIDEO 0
107#define AGP 1
108typedef struct {
109 uint32_t offset;
110 uint32_t size;
111} drm_via_agp_t;
112
113typedef struct {
114 uint32_t offset;
115 uint32_t size;
116} drm_via_fb_t;
117
118typedef struct {
119 uint32_t context;
120 uint32_t type;
121 uint32_t size;
122 unsigned long index;
123 unsigned long offset;
124} drm_via_mem_t;
125
126typedef struct _drm_via_init {
127 enum {
128 VIA_INIT_MAP = 0x01,
129 VIA_CLEANUP_MAP = 0x02
130 } func;
131
132 unsigned long sarea_priv_offset;
133 unsigned long fb_offset;
134 unsigned long mmio_offset;
135 unsigned long agpAddr;
136} drm_via_init_t;
137
138typedef struct _drm_via_futex {
139 enum {
140 VIA_FUTEX_WAIT = 0x00,
141 VIA_FUTEX_WAKE = 0X01
142 } func;
143 uint32_t ms;
144 uint32_t lock;
145 uint32_t val;
146} drm_via_futex_t;
147
148typedef struct _drm_via_dma_init {
149 enum {
150 VIA_INIT_DMA = 0x01,
151 VIA_CLEANUP_DMA = 0x02,
152 VIA_DMA_INITIALIZED = 0x03
153 } func;
154
155 unsigned long offset;
156 unsigned long size;
157 unsigned long reg_pause_addr;
158} drm_via_dma_init_t;
159
160typedef struct _drm_via_cmdbuffer {
161 char *buf;
162 unsigned long size;
163} drm_via_cmdbuffer_t;
164
165/* Warning: If you change the SAREA structure you must change the Xserver
166 * structure as well */
167
168typedef struct _drm_via_tex_region {
169 unsigned char next, prev; /* indices to form a circular LRU */
170 unsigned char inUse; /* owned by a client, or free? */
171 int age; /* tracked by clients to update local LRU's */
172} drm_via_tex_region_t;
173
174typedef struct _drm_via_sarea {
175 unsigned int dirty;
176 unsigned int nbox;
177 drm_clip_rect_t boxes[VIA_NR_SAREA_CLIPRECTS];
178 drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
179 int texAge; /* last time texture was uploaded */
180 int ctxOwner; /* last context to upload state */
181 int vertexPrim;
182
183 /*
184 * Below is for XvMC.
185 * We want the lock integers alone on, and aligned to, a cache line.
186 * Therefore this somewhat strange construct.
187 */
188
189 char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
190
191 unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
192 unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
193 unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */
194
195} drm_via_sarea_t;
196
197typedef struct _drm_via_cmdbuf_size {
198 enum {
199 VIA_CMDBUF_SPACE = 0x01,
200 VIA_CMDBUF_LAG = 0x02
201 } func;
202 int wait;
203 uint32_t size;
204} drm_via_cmdbuf_size_t;
205
206typedef enum {
207 VIA_IRQ_ABSOLUTE = 0x0,
208 VIA_IRQ_RELATIVE = 0x1,
209 VIA_IRQ_SIGNAL = 0x10000000,
210 VIA_IRQ_FORCE_SEQUENCE = 0x20000000
211} via_irq_seq_type_t;
212
213#define VIA_IRQ_FLAGS_MASK 0xF0000000
214
215struct drm_via_wait_irq_request{
216 unsigned irq;
217 via_irq_seq_type_t type;
218 uint32_t sequence;
219 uint32_t signal;
220};
221
222typedef union drm_via_irqwait {
223 struct drm_via_wait_irq_request request;
224 struct drm_wait_vblank_reply reply;
225} drm_via_irqwait_t;
226
227#ifdef __KERNEL__
228
229int via_fb_init(DRM_IOCTL_ARGS);
230int via_mem_alloc(DRM_IOCTL_ARGS);
231int via_mem_free(DRM_IOCTL_ARGS);
232int via_agp_init(DRM_IOCTL_ARGS);
233int via_map_init(DRM_IOCTL_ARGS);
234int via_decoder_futex(DRM_IOCTL_ARGS);
235int via_dma_init(DRM_IOCTL_ARGS);
236int via_cmdbuffer(DRM_IOCTL_ARGS);
237int via_flush_ioctl(DRM_IOCTL_ARGS);
238int via_pci_cmdbuffer(DRM_IOCTL_ARGS);
239int via_cmdbuf_size(DRM_IOCTL_ARGS);
240int via_wait_irq(DRM_IOCTL_ARGS);
241
242#endif
243#endif /* _VIA_DRM_H_ */
diff --git a/drivers/char/drm/via_drv.c b/drivers/char/drm/via_drv.c
new file mode 100644
index 000000000000..275eefc79221
--- /dev/null
+++ b/drivers/char/drm/via_drv.c
@@ -0,0 +1,126 @@
1/*
2 * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include <linux/config.h>
26#include "drmP.h"
27#include "via_drm.h"
28#include "via_drv.h"
29
30#include "drm_pciids.h"
31
32static int postinit(struct drm_device *dev, unsigned long flags)
33{
34 DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n",
35 DRIVER_NAME,
36 DRIVER_MAJOR,
37 DRIVER_MINOR,
38 DRIVER_PATCHLEVEL,
39 DRIVER_DATE, dev->primary.minor, pci_pretty_name(dev->pdev)
40 );
41 return 0;
42}
43
44static int version(drm_version_t * version)
45{
46 int len;
47
48 version->version_major = DRIVER_MAJOR;
49 version->version_minor = DRIVER_MINOR;
50 version->version_patchlevel = DRIVER_PATCHLEVEL;
51 DRM_COPY(version->name, DRIVER_NAME);
52 DRM_COPY(version->date, DRIVER_DATE);
53 DRM_COPY(version->desc, DRIVER_DESC);
54 return 0;
55}
56
57static struct pci_device_id pciidlist[] = {
58 viadrv_PCI_IDS
59};
60
61static drm_ioctl_desc_t ioctls[] = {
62 [DRM_IOCTL_NR(DRM_VIA_ALLOCMEM)] = {via_mem_alloc, 1, 0},
63 [DRM_IOCTL_NR(DRM_VIA_FREEMEM)] = {via_mem_free, 1, 0},
64 [DRM_IOCTL_NR(DRM_VIA_AGP_INIT)] = {via_agp_init, 1, 0},
65 [DRM_IOCTL_NR(DRM_VIA_FB_INIT)] = {via_fb_init, 1, 0},
66 [DRM_IOCTL_NR(DRM_VIA_MAP_INIT)] = {via_map_init, 1, 0},
67 [DRM_IOCTL_NR(DRM_VIA_DEC_FUTEX)] = {via_decoder_futex, 1, 0},
68 [DRM_IOCTL_NR(DRM_VIA_DMA_INIT)] = {via_dma_init, 1, 0},
69 [DRM_IOCTL_NR(DRM_VIA_CMDBUFFER)] = {via_cmdbuffer, 1, 0},
70 [DRM_IOCTL_NR(DRM_VIA_FLUSH)] = {via_flush_ioctl, 1, 0},
71 [DRM_IOCTL_NR(DRM_VIA_PCICMD)] = {via_pci_cmdbuffer, 1, 0},
72 [DRM_IOCTL_NR(DRM_VIA_CMDBUF_SIZE)] = {via_cmdbuf_size, 1, 0},
73 [DRM_IOCTL_NR(DRM_VIA_WAIT_IRQ)] = {via_wait_irq, 1, 0}
74};
75
76static struct drm_driver driver = {
77 .driver_features =
78 DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_IRQ |
79 DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL,
80 .context_ctor = via_init_context,
81 .context_dtor = via_final_context,
82 .vblank_wait = via_driver_vblank_wait,
83 .irq_preinstall = via_driver_irq_preinstall,
84 .irq_postinstall = via_driver_irq_postinstall,
85 .irq_uninstall = via_driver_irq_uninstall,
86 .irq_handler = via_driver_irq_handler,
87 .dma_quiescent = via_driver_dma_quiescent,
88 .reclaim_buffers = drm_core_reclaim_buffers,
89 .get_map_ofs = drm_core_get_map_ofs,
90 .get_reg_ofs = drm_core_get_reg_ofs,
91 .postinit = postinit,
92 .version = version,
93 .ioctls = ioctls,
94 .num_ioctls = DRM_ARRAY_SIZE(ioctls),
95 .fops = {
96 .owner = THIS_MODULE,
97 .open = drm_open,
98 .release = drm_release,
99 .ioctl = drm_ioctl,
100 .mmap = drm_mmap,
101 .poll = drm_poll,
102 .fasync = drm_fasync,
103 },
104 .pci_driver = {
105 .name = DRIVER_NAME,
106 .id_table = pciidlist,
107 }
108};
109
110static int __init via_init(void)
111{
112 via_init_command_verifier();
113 return drm_init(&driver);
114}
115
116static void __exit via_exit(void)
117{
118 drm_exit(&driver);
119}
120
121module_init(via_init);
122module_exit(via_exit);
123
124MODULE_AUTHOR(DRIVER_AUTHOR);
125MODULE_DESCRIPTION(DRIVER_DESC);
126MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/char/drm/via_drv.h b/drivers/char/drm/via_drv.h
new file mode 100644
index 000000000000..4eaa8b7c4c96
--- /dev/null
+++ b/drivers/char/drm/via_drv.h
@@ -0,0 +1,118 @@
1/*
2 * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef _VIA_DRV_H_
25#define _VIA_DRV_H_
26
27#define DRIVER_AUTHOR "VIA"
28
29#define DRIVER_NAME "via"
30#define DRIVER_DESC "VIA Unichrome / Pro"
31#define DRIVER_DATE "20050523"
32
33#define DRIVER_MAJOR 2
34#define DRIVER_MINOR 6
35#define DRIVER_PATCHLEVEL 3
36
37#include "via_verifier.h"
38
39#define VIA_PCI_BUF_SIZE 60000
40#define VIA_FIRE_BUF_SIZE 1024
41#define VIA_NUM_IRQS 2
42
43
44
45typedef struct drm_via_ring_buffer {
46 drm_map_t map;
47 char *virtual_start;
48} drm_via_ring_buffer_t;
49
50typedef uint32_t maskarray_t[5];
51
52typedef struct drm_via_irq {
53 atomic_t irq_received;
54 uint32_t pending_mask;
55 uint32_t enable_mask;
56 wait_queue_head_t irq_queue;
57} drm_via_irq_t;
58
59typedef struct drm_via_private {
60 drm_via_sarea_t *sarea_priv;
61 drm_map_t *sarea;
62 drm_map_t *fb;
63 drm_map_t *mmio;
64 unsigned long agpAddr;
65 wait_queue_head_t decoder_queue[VIA_NR_XVMC_LOCKS];
66 char *dma_ptr;
67 unsigned int dma_low;
68 unsigned int dma_high;
69 unsigned int dma_offset;
70 uint32_t dma_wrap;
71 volatile uint32_t *last_pause_ptr;
72 volatile uint32_t *hw_addr_ptr;
73 drm_via_ring_buffer_t ring;
74 struct timeval last_vblank;
75 int last_vblank_valid;
76 unsigned usec_per_vblank;
77 drm_via_state_t hc_state;
78 char pci_buf[VIA_PCI_BUF_SIZE];
79 const uint32_t *fire_offsets[VIA_FIRE_BUF_SIZE];
80 uint32_t num_fire_offsets;
81 int pro_group_a;
82 drm_via_irq_t via_irqs[VIA_NUM_IRQS];
83 unsigned num_irqs;
84 maskarray_t *irq_masks;
85 uint32_t irq_enable_mask;
86 uint32_t irq_pending_mask;
87} drm_via_private_t;
88
89/* VIA MMIO register access */
90#define VIA_BASE ((dev_priv->mmio))
91
92#define VIA_READ(reg) DRM_READ32(VIA_BASE, reg)
93#define VIA_WRITE(reg,val) DRM_WRITE32(VIA_BASE, reg, val)
94#define VIA_READ8(reg) DRM_READ8(VIA_BASE, reg)
95#define VIA_WRITE8(reg,val) DRM_WRITE8(VIA_BASE, reg, val)
96
97extern int via_init_context(drm_device_t * dev, int context);
98extern int via_final_context(drm_device_t * dev, int context);
99
100extern int via_do_cleanup_map(drm_device_t * dev);
101extern int via_map_init(struct inode *inode, struct file *filp,
102 unsigned int cmd, unsigned long arg);
103extern int via_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence);
104
105extern irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS);
106extern void via_driver_irq_preinstall(drm_device_t * dev);
107extern void via_driver_irq_postinstall(drm_device_t * dev);
108extern void via_driver_irq_uninstall(drm_device_t * dev);
109
110extern int via_dma_cleanup(drm_device_t * dev);
111extern void via_init_command_verifier(void);
112extern int via_driver_dma_quiescent(drm_device_t * dev);
113extern void via_init_futex(drm_via_private_t *dev_priv);
114extern void via_cleanup_futex(drm_via_private_t *dev_priv);
115extern void via_release_futex(drm_via_private_t *dev_priv, int context);
116
117
118#endif
diff --git a/drivers/char/drm/via_ds.c b/drivers/char/drm/via_ds.c
new file mode 100644
index 000000000000..daf3df75a20e
--- /dev/null
+++ b/drivers/char/drm/via_ds.c
@@ -0,0 +1,280 @@
1/*
2 * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
4 * Copyright 2000 Silicon Integrated Systems Corp, Inc., HsinChu, Taiwan.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sub license,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25#include <linux/module.h>
26#include <linux/delay.h>
27#include <linux/errno.h>
28#include <linux/kernel.h>
29#include <linux/slab.h>
30#include <linux/poll.h>
31#include <linux/pci.h>
32#include <asm/io.h>
33
34#include "via_ds.h"
35extern unsigned int VIA_DEBUG;
36
37set_t *via_setInit(void)
38{
39 int i;
40 set_t *set;
41 set = (set_t *) drm_alloc(sizeof(set_t), DRM_MEM_DRIVER);
42 for (i = 0; i < SET_SIZE; i++) {
43 set->list[i].free_next = i + 1;
44 set->list[i].alloc_next = -1;
45 }
46 set->list[SET_SIZE - 1].free_next = -1;
47 set->free = 0;
48 set->alloc = -1;
49 set->trace = -1;
50 return set;
51}
52
53int via_setAdd(set_t * set, ITEM_TYPE item)
54{
55 int free = set->free;
56 if (free != -1) {
57 set->list[free].val = item;
58 set->free = set->list[free].free_next;
59 } else {
60 return 0;
61 }
62 set->list[free].alloc_next = set->alloc;
63 set->alloc = free;
64 set->list[free].free_next = -1;
65 return 1;
66}
67
68int via_setDel(set_t * set, ITEM_TYPE item)
69{
70 int alloc = set->alloc;
71 int prev = -1;
72
73 while (alloc != -1) {
74 if (set->list[alloc].val == item) {
75 if (prev != -1)
76 set->list[prev].alloc_next =
77 set->list[alloc].alloc_next;
78 else
79 set->alloc = set->list[alloc].alloc_next;
80 break;
81 }
82 prev = alloc;
83 alloc = set->list[alloc].alloc_next;
84 }
85
86 if (alloc == -1)
87 return 0;
88
89 set->list[alloc].free_next = set->free;
90 set->free = alloc;
91 set->list[alloc].alloc_next = -1;
92
93 return 1;
94}
95
96/* setFirst -> setAdd -> setNext is wrong */
97
98int via_setFirst(set_t * set, ITEM_TYPE * item)
99{
100 if (set->alloc == -1)
101 return 0;
102
103 *item = set->list[set->alloc].val;
104 set->trace = set->list[set->alloc].alloc_next;
105
106 return 1;
107}
108
109int via_setNext(set_t * set, ITEM_TYPE * item)
110{
111 if (set->trace == -1)
112 return 0;
113
114 *item = set->list[set->trace].val;
115 set->trace = set->list[set->trace].alloc_next;
116
117 return 1;
118}
119
120int via_setDestroy(set_t * set)
121{
122 drm_free(set, sizeof(set_t), DRM_MEM_DRIVER);
123
124 return 1;
125}
126
127#define ISFREE(bptr) ((bptr)->free)
128
129#define fprintf(fmt, arg...) do{}while(0)
130
131memHeap_t *via_mmInit(int ofs, int size)
132{
133 PMemBlock blocks;
134
135 if (size <= 0)
136 return 0;
137
138 blocks = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock), DRM_MEM_DRIVER);
139
140 if (blocks) {
141 blocks->ofs = ofs;
142 blocks->size = size;
143 blocks->free = 1;
144 return (memHeap_t *) blocks;
145 } else
146 return 0;
147}
148
149static TMemBlock *SliceBlock(TMemBlock * p,
150 int startofs, int size,
151 int reserved, int alignment)
152{
153 TMemBlock *newblock;
154
155 /* break left */
156 if (startofs > p->ofs) {
157 newblock =
158 (TMemBlock *) drm_calloc(1, sizeof(TMemBlock),
159 DRM_MEM_DRIVER);
160 newblock->ofs = startofs;
161 newblock->size = p->size - (startofs - p->ofs);
162 newblock->free = 1;
163 newblock->next = p->next;
164 p->size -= newblock->size;
165 p->next = newblock;
166 p = newblock;
167 }
168
169 /* break right */
170 if (size < p->size) {
171 newblock =
172 (TMemBlock *) drm_calloc(1, sizeof(TMemBlock),
173 DRM_MEM_DRIVER);
174 newblock->ofs = startofs + size;
175 newblock->size = p->size - size;
176 newblock->free = 1;
177 newblock->next = p->next;
178 p->size = size;
179 p->next = newblock;
180 }
181
182 /* p = middle block */
183 p->align = alignment;
184 p->free = 0;
185 p->reserved = reserved;
186 return p;
187}
188
189PMemBlock via_mmAllocMem(memHeap_t * heap, int size, int align2,
190 int startSearch)
191{
192 int mask, startofs, endofs;
193 TMemBlock *p;
194
195 if (!heap || align2 < 0 || size <= 0)
196 return NULL;
197
198 mask = (1 << align2) - 1;
199 startofs = 0;
200 p = (TMemBlock *) heap;
201
202 while (p) {
203 if (ISFREE(p)) {
204 startofs = (p->ofs + mask) & ~mask;
205
206 if (startofs < startSearch)
207 startofs = startSearch;
208
209 endofs = startofs + size;
210
211 if (endofs <= (p->ofs + p->size))
212 break;
213 }
214
215 p = p->next;
216 }
217
218 if (!p)
219 return NULL;
220
221 p = SliceBlock(p, startofs, size, 0, mask + 1);
222 p->heap = heap;
223
224 return p;
225}
226
227static __inline__ int Join2Blocks(TMemBlock * p)
228{
229 if (p->free && p->next && p->next->free) {
230 TMemBlock *q = p->next;
231 p->size += q->size;
232 p->next = q->next;
233 drm_free(q, sizeof(TMemBlock), DRM_MEM_DRIVER);
234
235 return 1;
236 }
237
238 return 0;
239}
240
241int via_mmFreeMem(PMemBlock b)
242{
243 TMemBlock *p, *prev;
244
245 if (!b)
246 return 0;
247
248 if (!b->heap) {
249 fprintf(stderr, "no heap\n");
250
251 return -1;
252 }
253
254 p = b->heap;
255 prev = NULL;
256
257 while (p && p != b) {
258 prev = p;
259 p = p->next;
260 }
261
262 if (!p || p->free || p->reserved) {
263 if (!p)
264 fprintf(stderr, "block not found in heap\n");
265 else if (p->free)
266 fprintf(stderr, "block already free\n");
267 else
268 fprintf(stderr, "block is reserved\n");
269
270 return -1;
271 }
272
273 p->free = 1;
274 Join2Blocks(p);
275
276 if (prev)
277 Join2Blocks(prev);
278
279 return 0;
280}
diff --git a/drivers/char/drm/via_ds.h b/drivers/char/drm/via_ds.h
new file mode 100644
index 000000000000..be9c7f9f1aee
--- /dev/null
+++ b/drivers/char/drm/via_ds.h
@@ -0,0 +1,104 @@
1/*
2 * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
4 * Copyright 2000 Silicon Integrated Systems Corp, Inc., HsinChu, Taiwan.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sub license,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 */
26#ifndef _via_ds_h_
27#define _via_ds_h_
28
29#include "drmP.h"
30
31/* Set Data Structure */
32#define SET_SIZE 5000
33typedef unsigned long ITEM_TYPE;
34
35typedef struct {
36 ITEM_TYPE val;
37 int alloc_next, free_next;
38} list_item_t;
39
40typedef struct {
41 int alloc;
42 int free;
43 int trace;
44 list_item_t list[SET_SIZE];
45} set_t;
46
47set_t *via_setInit(void);
48int via_setAdd(set_t * set, ITEM_TYPE item);
49int via_setDel(set_t * set, ITEM_TYPE item);
50int via_setFirst(set_t * set, ITEM_TYPE * item);
51int via_setNext(set_t * set, ITEM_TYPE * item);
52int via_setDestroy(set_t * set);
53
54#endif
55
56#ifndef MM_INC
57#define MM_INC
58
59struct mem_block_t {
60 struct mem_block_t *next;
61 struct mem_block_t *heap;
62 int ofs, size;
63 int align;
64 int free:1;
65 int reserved:1;
66};
67typedef struct mem_block_t TMemBlock;
68typedef struct mem_block_t *PMemBlock;
69
70/* a heap is just the first block in a chain */
71typedef struct mem_block_t memHeap_t;
72
73static __inline__ int mmBlockSize(PMemBlock b)
74{
75 return b->size;
76}
77
78static __inline__ int mmOffset(PMemBlock b)
79{
80 return b->ofs;
81}
82
83static __inline__ void mmMarkReserved(PMemBlock b)
84{
85 b->reserved = 1;
86}
87
88/*
89 * input: total size in bytes
90 * return: a heap pointer if OK, NULL if error
91 */
92memHeap_t *via_mmInit(int ofs, int size);
93
94PMemBlock via_mmAllocMem(memHeap_t * heap, int size, int align2,
95 int startSearch);
96
97/*
98 * Free block starts at offset
99 * input: pointer to a block
100 * return: 0 if OK, -1 if error
101 */
102int via_mmFreeMem(PMemBlock b);
103
104#endif
diff --git a/drivers/char/drm/via_irq.c b/drivers/char/drm/via_irq.c
new file mode 100644
index 000000000000..e8027f3a93b0
--- /dev/null
+++ b/drivers/char/drm/via_irq.c
@@ -0,0 +1,339 @@
1/* via_irq.c
2 *
3 * Copyright 2004 BEAM Ltd.
4 * Copyright 2002 Tungsten Graphics, Inc.
5 * Copyright 2005 Thomas Hellstrom.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * BEAM LTD, TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
23 * DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 * Terry Barnaby <terry1@beam.ltd.uk>
30 * Keith Whitwell <keith@tungstengraphics.com>
31 * Thomas Hellstrom <unichrome@shipmail.org>
32 *
33 * This code provides standard DRM access to the Via Unichrome / Pro Vertical blank
34 * interrupt, as well as an infrastructure to handle other interrupts of the chip.
35 * The refresh rate is also calculated for video playback sync purposes.
36 */
37
38#include "drmP.h"
39#include "drm.h"
40#include "via_drm.h"
41#include "via_drv.h"
42
43#define VIA_REG_INTERRUPT 0x200
44
45/* VIA_REG_INTERRUPT */
46#define VIA_IRQ_GLOBAL (1 << 31)
47#define VIA_IRQ_VBLANK_ENABLE (1 << 19)
48#define VIA_IRQ_VBLANK_PENDING (1 << 3)
49#define VIA_IRQ_HQV0_ENABLE (1 << 11)
50#define VIA_IRQ_HQV1_ENABLE (1 << 25)
51#define VIA_IRQ_HQV0_PENDING (1 << 9)
52#define VIA_IRQ_HQV1_PENDING (1 << 10)
53
54/*
55 * Device-specific IRQs go here. This type might need to be extended with
56 * the register if there are multiple IRQ control registers.
57 * Currently we activate the HQV interrupts of Unichrome Pro group A.
58 */
59
60static maskarray_t via_pro_group_a_irqs[] = {
61 {VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x000003D0, 0x00008010, 0x00000000 },
62 {VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010, 0x00000000 }};
63static int via_num_pro_group_a = sizeof(via_pro_group_a_irqs)/sizeof(maskarray_t);
64
65static maskarray_t via_unichrome_irqs[] = {};
66static int via_num_unichrome = sizeof(via_unichrome_irqs)/sizeof(maskarray_t);
67
68
69static unsigned time_diff(struct timeval *now,struct timeval *then)
70{
71 return (now->tv_usec >= then->tv_usec) ?
72 now->tv_usec - then->tv_usec :
73 1000000 - (then->tv_usec - now->tv_usec);
74}
75
76irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)
77{
78 drm_device_t *dev = (drm_device_t *) arg;
79 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
80 u32 status;
81 int handled = 0;
82 struct timeval cur_vblank;
83 drm_via_irq_t *cur_irq = dev_priv->via_irqs;
84 int i;
85
86 status = VIA_READ(VIA_REG_INTERRUPT);
87 if (status & VIA_IRQ_VBLANK_PENDING) {
88 atomic_inc(&dev->vbl_received);
89 if (!(atomic_read(&dev->vbl_received) & 0x0F)) {
90 do_gettimeofday(&cur_vblank);
91 if (dev_priv->last_vblank_valid) {
92 dev_priv->usec_per_vblank =
93 time_diff( &cur_vblank,&dev_priv->last_vblank) >> 4;
94 }
95 dev_priv->last_vblank = cur_vblank;
96 dev_priv->last_vblank_valid = 1;
97 }
98 if (!(atomic_read(&dev->vbl_received) & 0xFF)) {
99 DRM_DEBUG("US per vblank is: %u\n",
100 dev_priv->usec_per_vblank);
101 }
102 DRM_WAKEUP(&dev->vbl_queue);
103 drm_vbl_send_signals(dev);
104 handled = 1;
105 }
106
107
108 for (i=0; i<dev_priv->num_irqs; ++i) {
109 if (status & cur_irq->pending_mask) {
110 atomic_inc( &cur_irq->irq_received );
111 DRM_WAKEUP( &cur_irq->irq_queue );
112 handled = 1;
113 }
114 cur_irq++;
115 }
116
117 /* Acknowlege interrupts */
118 VIA_WRITE(VIA_REG_INTERRUPT, status);
119
120
121 if (handled)
122 return IRQ_HANDLED;
123 else
124 return IRQ_NONE;
125}
126
127static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t * dev_priv)
128{
129 u32 status;
130
131 if (dev_priv) {
132 /* Acknowlege interrupts */
133 status = VIA_READ(VIA_REG_INTERRUPT);
134 VIA_WRITE(VIA_REG_INTERRUPT, status |
135 dev_priv->irq_pending_mask);
136 }
137}
138
139int via_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
140{
141 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
142 unsigned int cur_vblank;
143 int ret = 0;
144
145 DRM_DEBUG("viadrv_vblank_wait\n");
146 if (!dev_priv) {
147 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
148 return -EINVAL;
149 }
150
151 viadrv_acknowledge_irqs(dev_priv);
152
153 /* Assume that the user has missed the current sequence number
154 * by about a day rather than she wants to wait for years
155 * using vertical blanks...
156 */
157
158 DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
159 (((cur_vblank = atomic_read(&dev->vbl_received)) -
160 *sequence) <= (1 << 23)));
161
162 *sequence = cur_vblank;
163 return ret;
164}
165
166static int
167via_driver_irq_wait(drm_device_t * dev, unsigned int irq, int force_sequence,
168 unsigned int *sequence)
169{
170 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
171 unsigned int cur_irq_sequence;
172 drm_via_irq_t *cur_irq = dev_priv->via_irqs;
173 int ret = 0;
174 maskarray_t *masks = dev_priv->irq_masks;
175
176 DRM_DEBUG("%s\n", __FUNCTION__);
177
178 if (!dev_priv) {
179 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
180 return DRM_ERR(EINVAL);
181 }
182
183 if (irq >= dev_priv->num_irqs ) {
184 DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__, irq);
185 return DRM_ERR(EINVAL);
186 }
187
188 cur_irq += irq;
189
190 if (masks[irq][2] && !force_sequence) {
191 DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
192 ((VIA_READ(masks[irq][2]) & masks[irq][3]) == masks[irq][4]));
193 cur_irq_sequence = atomic_read(&cur_irq->irq_received);
194 } else {
195 DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
196 (((cur_irq_sequence = atomic_read(&cur_irq->irq_received)) -
197 *sequence) <= (1 << 23)));
198 }
199 *sequence = cur_irq_sequence;
200 return ret;
201}
202
203
204/*
205 * drm_dma.h hooks
206 */
207
208void via_driver_irq_preinstall(drm_device_t * dev)
209{
210 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
211 u32 status;
212 drm_via_irq_t *cur_irq = dev_priv->via_irqs;
213 int i;
214
215 DRM_DEBUG("driver_irq_preinstall: dev_priv: %p\n", dev_priv);
216 if (dev_priv) {
217
218 dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE;
219 dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING;
220
221 dev_priv->irq_masks = (dev_priv->pro_group_a) ?
222 via_pro_group_a_irqs : via_unichrome_irqs;
223 dev_priv->num_irqs = (dev_priv->pro_group_a) ?
224 via_num_pro_group_a : via_num_unichrome;
225
226 for(i=0; i < dev_priv->num_irqs; ++i) {
227 atomic_set(&cur_irq->irq_received, 0);
228 cur_irq->enable_mask = dev_priv->irq_masks[i][0];
229 cur_irq->pending_mask = dev_priv->irq_masks[i][1];
230 DRM_INIT_WAITQUEUE( &cur_irq->irq_queue );
231 dev_priv->irq_enable_mask |= cur_irq->enable_mask;
232 dev_priv->irq_pending_mask |= cur_irq->pending_mask;
233 cur_irq++;
234
235 DRM_DEBUG("Initializing IRQ %d\n", i);
236 }
237
238 dev_priv->last_vblank_valid = 0;
239
240 // Clear VSync interrupt regs
241 status = VIA_READ(VIA_REG_INTERRUPT);
242 VIA_WRITE(VIA_REG_INTERRUPT, status &
243 ~(dev_priv->irq_enable_mask));
244
245 /* Clear bits if they're already high */
246 viadrv_acknowledge_irqs(dev_priv);
247 }
248}
249
250void via_driver_irq_postinstall(drm_device_t * dev)
251{
252 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
253 u32 status;
254
255 DRM_DEBUG("via_driver_irq_postinstall\n");
256 if (dev_priv) {
257 status = VIA_READ(VIA_REG_INTERRUPT);
258 VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL
259 | dev_priv->irq_enable_mask);
260
261 /* Some magic, oh for some data sheets ! */
262
263 VIA_WRITE8(0x83d4, 0x11);
264 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
265
266 }
267}
268
269void via_driver_irq_uninstall(drm_device_t * dev)
270{
271 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
272 u32 status;
273
274 DRM_DEBUG("driver_irq_uninstall)\n");
275 if (dev_priv) {
276
277 /* Some more magic, oh for some data sheets ! */
278
279 VIA_WRITE8(0x83d4, 0x11);
280 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
281
282 status = VIA_READ(VIA_REG_INTERRUPT);
283 VIA_WRITE(VIA_REG_INTERRUPT, status &
284 ~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask));
285 }
286}
287
288int via_wait_irq(DRM_IOCTL_ARGS)
289{
290 drm_file_t *priv = filp->private_data;
291 drm_device_t *dev = priv->head->dev;
292 drm_via_irqwait_t __user *argp = (void __user *)data;
293 drm_via_irqwait_t irqwait;
294 struct timeval now;
295 int ret = 0;
296 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
297 drm_via_irq_t *cur_irq = dev_priv->via_irqs;
298 int force_sequence;
299
300 if (!dev->irq)
301 return DRM_ERR(EINVAL);
302
303 DRM_COPY_FROM_USER_IOCTL(irqwait, argp, sizeof(irqwait));
304 if (irqwait.request.irq >= dev_priv->num_irqs) {
305 DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__,
306 irqwait.request.irq);
307 return DRM_ERR(EINVAL);
308 }
309
310 cur_irq += irqwait.request.irq;
311
312 switch (irqwait.request.type & ~VIA_IRQ_FLAGS_MASK) {
313 case VIA_IRQ_RELATIVE:
314 irqwait.request.sequence += atomic_read(&cur_irq->irq_received);
315 irqwait.request.type &= ~_DRM_VBLANK_RELATIVE;
316 case VIA_IRQ_ABSOLUTE:
317 break;
318 default:
319 return DRM_ERR(EINVAL);
320 }
321
322 if (irqwait.request.type & VIA_IRQ_SIGNAL) {
323 DRM_ERROR("%s Signals on Via IRQs not implemented yet.\n",
324 __FUNCTION__);
325 return DRM_ERR(EINVAL);
326 }
327
328 force_sequence = (irqwait.request.type & VIA_IRQ_FORCE_SEQUENCE);
329
330 ret = via_driver_irq_wait(dev, irqwait.request.irq, force_sequence,
331 &irqwait.request.sequence);
332 do_gettimeofday(&now);
333 irqwait.reply.tval_sec = now.tv_sec;
334 irqwait.reply.tval_usec = now.tv_usec;
335
336 DRM_COPY_TO_USER_IOCTL(argp, irqwait, sizeof(irqwait));
337
338 return ret;
339}
diff --git a/drivers/char/drm/via_map.c b/drivers/char/drm/via_map.c
new file mode 100644
index 000000000000..0be829b6ec65
--- /dev/null
+++ b/drivers/char/drm/via_map.c
@@ -0,0 +1,110 @@
1/*
2 * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#include "drmP.h"
25#include "via_drm.h"
26#include "via_drv.h"
27
28static int via_do_init_map(drm_device_t * dev, drm_via_init_t * init)
29{
30 drm_via_private_t *dev_priv;
31
32 DRM_DEBUG("%s\n", __FUNCTION__);
33
34 dev_priv = drm_alloc(sizeof(drm_via_private_t), DRM_MEM_DRIVER);
35 if (dev_priv == NULL)
36 return -ENOMEM;
37
38 memset(dev_priv, 0, sizeof(drm_via_private_t));
39
40 DRM_GETSAREA();
41 if (!dev_priv->sarea) {
42 DRM_ERROR("could not find sarea!\n");
43 dev->dev_private = (void *)dev_priv;
44 via_do_cleanup_map(dev);
45 return -EINVAL;
46 }
47
48 dev_priv->fb = drm_core_findmap(dev, init->fb_offset);
49 if (!dev_priv->fb) {
50 DRM_ERROR("could not find framebuffer!\n");
51 dev->dev_private = (void *)dev_priv;
52 via_do_cleanup_map(dev);
53 return -EINVAL;
54 }
55 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
56 if (!dev_priv->mmio) {
57 DRM_ERROR("could not find mmio region!\n");
58 dev->dev_private = (void *)dev_priv;
59 via_do_cleanup_map(dev);
60 return -EINVAL;
61 }
62
63 dev_priv->sarea_priv =
64 (drm_via_sarea_t *) ((u8 *) dev_priv->sarea->handle +
65 init->sarea_priv_offset);
66
67 dev_priv->agpAddr = init->agpAddr;
68
69 via_init_futex( dev_priv );
70 dev_priv->pro_group_a = (dev->pdev->device == 0x3118);
71
72 dev->dev_private = (void *)dev_priv;
73 return 0;
74}
75
76int via_do_cleanup_map(drm_device_t * dev)
77{
78 if (dev->dev_private) {
79
80 drm_via_private_t *dev_priv = dev->dev_private;
81
82 via_dma_cleanup(dev);
83
84 drm_free(dev_priv, sizeof(drm_via_private_t), DRM_MEM_DRIVER);
85 dev->dev_private = NULL;
86 }
87
88 return 0;
89}
90
91int via_map_init(DRM_IOCTL_ARGS)
92{
93 DRM_DEVICE;
94 drm_via_init_t init;
95
96 DRM_DEBUG("%s\n", __FUNCTION__);
97
98 DRM_COPY_FROM_USER_IOCTL(init, (drm_via_init_t *) data, sizeof(init));
99
100 switch (init.func) {
101 case VIA_INIT_MAP:
102 return via_do_init_map(dev, &init);
103 case VIA_CLEANUP_MAP:
104 return via_do_cleanup_map(dev);
105 }
106
107 return -EINVAL;
108}
109
110
diff --git a/drivers/char/drm/via_mm.c b/drivers/char/drm/via_mm.c
new file mode 100644
index 000000000000..c22712f44d42
--- /dev/null
+++ b/drivers/char/drm/via_mm.c
@@ -0,0 +1,358 @@
1/*
2 * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#include "drmP.h"
25#include "via_drm.h"
26#include "via_drv.h"
27#include "via_ds.h"
28#include "via_mm.h"
29
30#define MAX_CONTEXT 100
31
32typedef struct {
33 int used;
34 int context;
35 set_t *sets[2]; /* 0 for frame buffer, 1 for AGP , 2 for System */
36} via_context_t;
37
38static via_context_t global_ppriv[MAX_CONTEXT];
39
40static int via_agp_alloc(drm_via_mem_t * mem);
41static int via_agp_free(drm_via_mem_t * mem);
42static int via_fb_alloc(drm_via_mem_t * mem);
43static int via_fb_free(drm_via_mem_t * mem);
44
45static int add_alloc_set(int context, int type, unsigned int val)
46{
47 int i, retval = 0;
48
49 for (i = 0; i < MAX_CONTEXT; i++) {
50 if (global_ppriv[i].used && global_ppriv[i].context == context) {
51 retval = via_setAdd(global_ppriv[i].sets[type], val);
52 break;
53 }
54 }
55
56 return retval;
57}
58
59static int del_alloc_set(int context, int type, unsigned int val)
60{
61 int i, retval = 0;
62
63 for (i = 0; i < MAX_CONTEXT; i++)
64 if (global_ppriv[i].used && global_ppriv[i].context == context) {
65 retval = via_setDel(global_ppriv[i].sets[type], val);
66 break;
67 }
68
69 return retval;
70}
71
72/* agp memory management */
73static memHeap_t *AgpHeap = NULL;
74
75int via_agp_init(DRM_IOCTL_ARGS)
76{
77 drm_via_agp_t agp;
78
79 DRM_COPY_FROM_USER_IOCTL(agp, (drm_via_agp_t *) data, sizeof(agp));
80
81 AgpHeap = via_mmInit(agp.offset, agp.size);
82
83 DRM_DEBUG("offset = %lu, size = %lu", (unsigned long)agp.offset, (unsigned long)agp.size);
84
85 return 0;
86}
87
88/* fb memory management */
89static memHeap_t *FBHeap = NULL;
90
91int via_fb_init(DRM_IOCTL_ARGS)
92{
93 drm_via_fb_t fb;
94
95 DRM_COPY_FROM_USER_IOCTL(fb, (drm_via_fb_t *) data, sizeof(fb));
96
97 FBHeap = via_mmInit(fb.offset, fb.size);
98
99 DRM_DEBUG("offset = %lu, size = %lu", (unsigned long)fb.offset, (unsigned long)fb.size);
100
101 return 0;
102}
103
104int via_init_context(struct drm_device *dev, int context)
105{
106 int i;
107
108 for (i = 0; i < MAX_CONTEXT; i++)
109 if (global_ppriv[i].used &&
110 (global_ppriv[i].context == context))
111 break;
112
113 if (i >= MAX_CONTEXT) {
114 for (i = 0; i < MAX_CONTEXT; i++) {
115 if (!global_ppriv[i].used) {
116 global_ppriv[i].context = context;
117 global_ppriv[i].used = 1;
118 global_ppriv[i].sets[0] = via_setInit();
119 global_ppriv[i].sets[1] = via_setInit();
120 DRM_DEBUG("init allocation set, socket=%d,"
121 " context = %d\n", i, context);
122 break;
123 }
124 }
125
126 if ((i >= MAX_CONTEXT) || (global_ppriv[i].sets[0] == NULL) ||
127 (global_ppriv[i].sets[1] == NULL)) {
128 return 0;
129 }
130 }
131
132 return 1;
133}
134
135int via_final_context(struct drm_device *dev, int context)
136{
137 int i;
138 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
139
140 for (i = 0; i < MAX_CONTEXT; i++)
141 if (global_ppriv[i].used &&
142 (global_ppriv[i].context == context))
143 break;
144
145 if (i < MAX_CONTEXT) {
146 set_t *set;
147 ITEM_TYPE item;
148 int retval;
149
150 DRM_DEBUG("find socket %d, context = %d\n", i, context);
151
152 /* Video Memory */
153 set = global_ppriv[i].sets[0];
154 retval = via_setFirst(set, &item);
155 while (retval) {
156 DRM_DEBUG("free video memory 0x%lx\n", item);
157 via_mmFreeMem((PMemBlock) item);
158 retval = via_setNext(set, &item);
159 }
160 via_setDestroy(set);
161
162 /* AGP Memory */
163 set = global_ppriv[i].sets[1];
164 retval = via_setFirst(set, &item);
165 while (retval) {
166 DRM_DEBUG("free agp memory 0x%lx\n", item);
167 via_mmFreeMem((PMemBlock) item);
168 retval = via_setNext(set, &item);
169 }
170 via_setDestroy(set);
171 global_ppriv[i].used = 0;
172 }
173 via_release_futex(dev_priv, context);
174
175
176#if defined(__linux__)
177 /* Linux specific until context tracking code gets ported to BSD */
178 /* Last context, perform cleanup */
179 if (dev->ctx_count == 1 && dev->dev_private) {
180 DRM_DEBUG("Last Context\n");
181 if (dev->irq)
182 drm_irq_uninstall(dev);
183
184 via_cleanup_futex(dev_priv);
185 via_do_cleanup_map(dev);
186 }
187#endif
188
189 return 1;
190}
191
192int via_mem_alloc(DRM_IOCTL_ARGS)
193{
194 drm_via_mem_t mem;
195
196 DRM_COPY_FROM_USER_IOCTL(mem, (drm_via_mem_t *) data, sizeof(mem));
197
198 switch (mem.type) {
199 case VIDEO:
200 if (via_fb_alloc(&mem) < 0)
201 return -EFAULT;
202 DRM_COPY_TO_USER_IOCTL((drm_via_mem_t *) data, mem,
203 sizeof(mem));
204 return 0;
205 case AGP:
206 if (via_agp_alloc(&mem) < 0)
207 return -EFAULT;
208 DRM_COPY_TO_USER_IOCTL((drm_via_mem_t *) data, mem,
209 sizeof(mem));
210 return 0;
211 }
212
213 return -EFAULT;
214}
215
216static int via_fb_alloc(drm_via_mem_t * mem)
217{
218 drm_via_mm_t fb;
219 PMemBlock block;
220 int retval = 0;
221
222 if (!FBHeap)
223 return -1;
224
225 fb.size = mem->size;
226 fb.context = mem->context;
227
228 block = via_mmAllocMem(FBHeap, fb.size, 5, 0);
229 if (block) {
230 fb.offset = block->ofs;
231 fb.free = (unsigned long)block;
232 if (!add_alloc_set(fb.context, VIDEO, fb.free)) {
233 DRM_DEBUG("adding to allocation set fails\n");
234 via_mmFreeMem((PMemBlock) fb.free);
235 retval = -1;
236 }
237 } else {
238 fb.offset = 0;
239 fb.size = 0;
240 fb.free = 0;
241 retval = -1;
242 }
243
244 mem->offset = fb.offset;
245 mem->index = fb.free;
246
247 DRM_DEBUG("alloc fb, size = %d, offset = %d\n", fb.size,
248 (int)fb.offset);
249
250 return retval;
251}
252
253static int via_agp_alloc(drm_via_mem_t * mem)
254{
255 drm_via_mm_t agp;
256 PMemBlock block;
257 int retval = 0;
258
259 if (!AgpHeap)
260 return -1;
261
262 agp.size = mem->size;
263 agp.context = mem->context;
264
265 block = via_mmAllocMem(AgpHeap, agp.size, 5, 0);
266 if (block) {
267 agp.offset = block->ofs;
268 agp.free = (unsigned long)block;
269 if (!add_alloc_set(agp.context, AGP, agp.free)) {
270 DRM_DEBUG("adding to allocation set fails\n");
271 via_mmFreeMem((PMemBlock) agp.free);
272 retval = -1;
273 }
274 } else {
275 agp.offset = 0;
276 agp.size = 0;
277 agp.free = 0;
278 }
279
280 mem->offset = agp.offset;
281 mem->index = agp.free;
282
283 DRM_DEBUG("alloc agp, size = %d, offset = %d\n", agp.size,
284 (unsigned int)agp.offset);
285 return retval;
286}
287
288int via_mem_free(DRM_IOCTL_ARGS)
289{
290 drm_via_mem_t mem;
291
292 DRM_COPY_FROM_USER_IOCTL(mem, (drm_via_mem_t *) data, sizeof(mem));
293
294 switch (mem.type) {
295
296 case VIDEO:
297 if (via_fb_free(&mem) == 0)
298 return 0;
299 break;
300 case AGP:
301 if (via_agp_free(&mem) == 0)
302 return 0;
303 break;
304 }
305
306 return -EFAULT;
307}
308
309static int via_fb_free(drm_via_mem_t * mem)
310{
311 drm_via_mm_t fb;
312 int retval = 0;
313
314 if (!FBHeap) {
315 return -1;
316 }
317
318 fb.free = mem->index;
319 fb.context = mem->context;
320
321 if (!fb.free) {
322 return -1;
323
324 }
325
326 via_mmFreeMem((PMemBlock) fb.free);
327
328 if (!del_alloc_set(fb.context, VIDEO, fb.free)) {
329 retval = -1;
330 }
331
332 DRM_DEBUG("free fb, free = %ld\n", fb.free);
333
334 return retval;
335}
336
337static int via_agp_free(drm_via_mem_t * mem)
338{
339 drm_via_mm_t agp;
340
341 int retval = 0;
342
343 agp.free = mem->index;
344 agp.context = mem->context;
345
346 if (!agp.free)
347 return -1;
348
349 via_mmFreeMem((PMemBlock) agp.free);
350
351 if (!del_alloc_set(agp.context, AGP, agp.free)) {
352 retval = -1;
353 }
354
355 DRM_DEBUG("free agp, free = %ld\n", agp.free);
356
357 return retval;
358}
diff --git a/drivers/char/drm/via_mm.h b/drivers/char/drm/via_mm.h
new file mode 100644
index 000000000000..d57efda57c76
--- /dev/null
+++ b/drivers/char/drm/via_mm.h
@@ -0,0 +1,40 @@
1/*
2 * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef _via_drm_mm_h_
25#define _via_drm_mm_h_
26
27typedef struct {
28 unsigned int context;
29 unsigned int size;
30 unsigned long offset;
31 unsigned long free;
32} drm_via_mm_t;
33
34typedef struct {
35 unsigned int size;
36 unsigned long handle;
37 void *virtual;
38} drm_via_dma_t;
39
40#endif
diff --git a/drivers/char/drm/via_verifier.c b/drivers/char/drm/via_verifier.c
new file mode 100644
index 000000000000..07923b0c7a97
--- /dev/null
+++ b/drivers/char/drm/via_verifier.c
@@ -0,0 +1,1061 @@
1/*
2 * Copyright 2004 The Unichrome Project. All Rights Reserved.
3 * Copyright 2005 Thomas Hellstrom. All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S), AND/OR THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Author: Thomas Hellstrom 2004, 2005.
25 * This code was written using docs obtained under NDA from VIA Inc.
26 *
27 * Don't run this code directly on an AGP buffer. Due to cache problems it will
28 * be very slow.
29 */
30
31
32#include "via_3d_reg.h"
33#include "drmP.h"
34#include "drm.h"
35#include "via_drm.h"
36#include "via_verifier.h"
37#include "via_drv.h"
38
39typedef enum{
40 state_command,
41 state_header2,
42 state_header1,
43 state_vheader5,
44 state_vheader6,
45 state_error
46} verifier_state_t;
47
48
49typedef enum{
50 no_check = 0,
51 check_for_header2,
52 check_for_header1,
53 check_for_header2_err,
54 check_for_header1_err,
55 check_for_fire,
56 check_z_buffer_addr0,
57 check_z_buffer_addr1,
58 check_z_buffer_addr_mode,
59 check_destination_addr0,
60 check_destination_addr1,
61 check_destination_addr_mode,
62 check_for_dummy,
63 check_for_dd,
64 check_texture_addr0,
65 check_texture_addr1,
66 check_texture_addr2,
67 check_texture_addr3,
68 check_texture_addr4,
69 check_texture_addr5,
70 check_texture_addr6,
71 check_texture_addr7,
72 check_texture_addr8,
73 check_texture_addr_mode,
74 check_for_vertex_count,
75 check_number_texunits,
76 forbidden_command
77}hazard_t;
78
79/*
80 * Associates each hazard above with a possible multi-command
81 * sequence. For example an address that is split over multiple
82 * commands and that needs to be checked at the first command
83 * that does not include any part of the address.
84 */
85
86static drm_via_sequence_t seqs[] = {
87 no_sequence,
88 no_sequence,
89 no_sequence,
90 no_sequence,
91 no_sequence,
92 no_sequence,
93 z_address,
94 z_address,
95 z_address,
96 dest_address,
97 dest_address,
98 dest_address,
99 no_sequence,
100 no_sequence,
101 tex_address,
102 tex_address,
103 tex_address,
104 tex_address,
105 tex_address,
106 tex_address,
107 tex_address,
108 tex_address,
109 tex_address,
110 tex_address,
111 no_sequence
112};
113
114typedef struct{
115 unsigned int code;
116 hazard_t hz;
117} hz_init_t;
118
119
120
121static hz_init_t init_table1[] = {
122 {0xf2, check_for_header2_err},
123 {0xf0, check_for_header1_err},
124 {0xee, check_for_fire},
125 {0xcc, check_for_dummy},
126 {0xdd, check_for_dd},
127 {0x00, no_check},
128 {0x10, check_z_buffer_addr0},
129 {0x11, check_z_buffer_addr1},
130 {0x12, check_z_buffer_addr_mode},
131 {0x13, no_check},
132 {0x14, no_check},
133 {0x15, no_check},
134 {0x23, no_check},
135 {0x24, no_check},
136 {0x33, no_check},
137 {0x34, no_check},
138 {0x35, no_check},
139 {0x36, no_check},
140 {0x37, no_check},
141 {0x38, no_check},
142 {0x39, no_check},
143 {0x3A, no_check},
144 {0x3B, no_check},
145 {0x3C, no_check},
146 {0x3D, no_check},
147 {0x3E, no_check},
148 {0x40, check_destination_addr0},
149 {0x41, check_destination_addr1},
150 {0x42, check_destination_addr_mode},
151 {0x43, no_check},
152 {0x44, no_check},
153 {0x50, no_check},
154 {0x51, no_check},
155 {0x52, no_check},
156 {0x53, no_check},
157 {0x54, no_check},
158 {0x55, no_check},
159 {0x56, no_check},
160 {0x57, no_check},
161 {0x58, no_check},
162 {0x70, no_check},
163 {0x71, no_check},
164 {0x78, no_check},
165 {0x79, no_check},
166 {0x7A, no_check},
167 {0x7B, no_check},
168 {0x7C, no_check},
169 {0x7D, check_for_vertex_count}
170};
171
172
173
174static hz_init_t init_table2[] = {
175 {0xf2, check_for_header2_err},
176 {0xf0, check_for_header1_err},
177 {0xee, check_for_fire},
178 {0xcc, check_for_dummy},
179 {0x00, check_texture_addr0},
180 {0x01, check_texture_addr0},
181 {0x02, check_texture_addr0},
182 {0x03, check_texture_addr0},
183 {0x04, check_texture_addr0},
184 {0x05, check_texture_addr0},
185 {0x06, check_texture_addr0},
186 {0x07, check_texture_addr0},
187 {0x08, check_texture_addr0},
188 {0x09, check_texture_addr0},
189 {0x20, check_texture_addr1},
190 {0x21, check_texture_addr1},
191 {0x22, check_texture_addr1},
192 {0x23, check_texture_addr4},
193 {0x2B, check_texture_addr3},
194 {0x2C, check_texture_addr3},
195 {0x2D, check_texture_addr3},
196 {0x2E, check_texture_addr3},
197 {0x2F, check_texture_addr3},
198 {0x30, check_texture_addr3},
199 {0x31, check_texture_addr3},
200 {0x32, check_texture_addr3},
201 {0x33, check_texture_addr3},
202 {0x34, check_texture_addr3},
203 {0x4B, check_texture_addr5},
204 {0x4C, check_texture_addr6},
205 {0x51, check_texture_addr7},
206 {0x52, check_texture_addr8},
207 {0x77, check_texture_addr2},
208 {0x78, no_check},
209 {0x79, no_check},
210 {0x7A, no_check},
211 {0x7B, check_texture_addr_mode},
212 {0x7C, no_check},
213 {0x7D, no_check},
214 {0x7E, no_check},
215 {0x7F, no_check},
216 {0x80, no_check},
217 {0x81, no_check},
218 {0x82, no_check},
219 {0x83, no_check},
220 {0x85, no_check},
221 {0x86, no_check},
222 {0x87, no_check},
223 {0x88, no_check},
224 {0x89, no_check},
225 {0x8A, no_check},
226 {0x90, no_check},
227 {0x91, no_check},
228 {0x92, no_check},
229 {0x93, no_check}
230};
231
232static hz_init_t init_table3[] = {
233 {0xf2, check_for_header2_err},
234 {0xf0, check_for_header1_err},
235 {0xcc, check_for_dummy},
236 {0x00, check_number_texunits}
237};
238
239
240static hazard_t table1[256];
241static hazard_t table2[256];
242static hazard_t table3[256];
243
244
245
246static __inline__ int
247eat_words(const uint32_t **buf, const uint32_t *buf_end, unsigned num_words)
248{
249 if ((*buf - buf_end) >= num_words) {
250 *buf += num_words;
251 return 0;
252 }
253 DRM_ERROR("Illegal termination of DMA command buffer\n");
254 return 1;
255}
256
257
258/*
259 * Partially stolen from drm_memory.h
260 */
261
262static __inline__ drm_map_t *
263via_drm_lookup_agp_map (drm_via_state_t *seq, unsigned long offset, unsigned long size,
264 drm_device_t *dev)
265{
266 struct list_head *list;
267 drm_map_list_t *r_list;
268 drm_map_t *map = seq->map_cache;
269
270 if (map && map->offset <= offset && (offset + size) <= (map->offset + map->size)) {
271 return map;
272 }
273
274 list_for_each(list, &dev->maplist->head) {
275 r_list = (drm_map_list_t *) list;
276 map = r_list->map;
277 if (!map)
278 continue;
279 if (map->offset <= offset && (offset + size) <= (map->offset + map->size) &&
280 !(map->flags & _DRM_RESTRICTED) && (map->type == _DRM_AGP)) {
281 seq->map_cache = map;
282 return map;
283 }
284 }
285 return NULL;
286}
287
288
289/*
290 * Require that all AGP texture levels reside in the same AGP map which should
291 * be mappable by the client. This is not a big restriction.
292 * FIXME: To actually enforce this security policy strictly, drm_rmmap
293 * would have to wait for dma quiescent before removing an AGP map.
294 * The via_drm_lookup_agp_map call in reality seems to take
295 * very little CPU time.
296 */
297
298
299static __inline__ int
300finish_current_sequence(drm_via_state_t *cur_seq)
301{
302 switch(cur_seq->unfinished) {
303 case z_address:
304 DRM_DEBUG("Z Buffer start address is 0x%x\n", cur_seq->z_addr);
305 break;
306 case dest_address:
307 DRM_DEBUG("Destination start address is 0x%x\n", cur_seq->d_addr);
308 break;
309 case tex_address:
310 if (cur_seq->agp_texture) {
311 unsigned start = cur_seq->tex_level_lo[cur_seq->texture];
312 unsigned end = cur_seq->tex_level_hi[cur_seq->texture];
313 unsigned long lo=~0, hi=0, tmp;
314 uint32_t *addr, *pitch, *height, tex;
315 unsigned i;
316
317 if (end > 9) end = 9;
318 if (start > 9) start = 9;
319
320 addr =&(cur_seq->t_addr[tex = cur_seq->texture][start]);
321 pitch = &(cur_seq->pitch[tex][start]);
322 height = &(cur_seq->height[tex][start]);
323
324 for (i=start; i<= end; ++i) {
325 tmp = *addr++;
326 if (tmp < lo) lo = tmp;
327 tmp += (*height++ << *pitch++);
328 if (tmp > hi) hi = tmp;
329 }
330
331 if (! via_drm_lookup_agp_map (cur_seq, lo, hi - lo, cur_seq->dev)) {
332 DRM_ERROR("AGP texture is not in allowed map\n");
333 return 2;
334 }
335 }
336 break;
337 default:
338 break;
339 }
340 cur_seq->unfinished = no_sequence;
341 return 0;
342}
343
344static __inline__ int
345investigate_hazard( uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq)
346{
347 register uint32_t tmp, *tmp_addr;
348
349 if (cur_seq->unfinished && (cur_seq->unfinished != seqs[hz])) {
350 int ret;
351 if ((ret = finish_current_sequence(cur_seq))) return ret;
352 }
353
354 switch(hz) {
355 case check_for_header2:
356 if (cmd == HALCYON_HEADER2) return 1;
357 return 0;
358 case check_for_header1:
359 if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) return 1;
360 return 0;
361 case check_for_header2_err:
362 if (cmd == HALCYON_HEADER2) return 1;
363 DRM_ERROR("Illegal DMA HALCYON_HEADER2 command\n");
364 break;
365 case check_for_header1_err:
366 if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) return 1;
367 DRM_ERROR("Illegal DMA HALCYON_HEADER1 command\n");
368 break;
369 case check_for_fire:
370 if ((cmd & HALCYON_FIREMASK) == HALCYON_FIRECMD) return 1;
371 DRM_ERROR("Illegal DMA HALCYON_FIRECMD command\n");
372 break;
373 case check_for_dummy:
374 if (HC_DUMMY == cmd) return 0;
375 DRM_ERROR("Illegal DMA HC_DUMMY command\n");
376 break;
377 case check_for_dd:
378 if (0xdddddddd == cmd) return 0;
379 DRM_ERROR("Illegal DMA 0xdddddddd command\n");
380 break;
381 case check_z_buffer_addr0:
382 cur_seq->unfinished = z_address;
383 cur_seq->z_addr = (cur_seq->z_addr & 0xFF000000) |
384 (cmd & 0x00FFFFFF);
385 return 0;
386 case check_z_buffer_addr1:
387 cur_seq->unfinished = z_address;
388 cur_seq->z_addr = (cur_seq->z_addr & 0x00FFFFFF) |
389 ((cmd & 0xFF) << 24);
390 return 0;
391 case check_z_buffer_addr_mode:
392 cur_seq->unfinished = z_address;
393 if ((cmd & 0x0000C000) == 0) return 0;
394 DRM_ERROR("Attempt to place Z buffer in system memory\n");
395 return 2;
396 case check_destination_addr0:
397 cur_seq->unfinished = dest_address;
398 cur_seq->d_addr = (cur_seq->d_addr & 0xFF000000) |
399 (cmd & 0x00FFFFFF);
400 return 0;
401 case check_destination_addr1:
402 cur_seq->unfinished = dest_address;
403 cur_seq->d_addr = (cur_seq->d_addr & 0x00FFFFFF) |
404 ((cmd & 0xFF) << 24);
405 return 0;
406 case check_destination_addr_mode:
407 cur_seq->unfinished = dest_address;
408 if ((cmd & 0x0000C000) == 0) return 0;
409 DRM_ERROR("Attempt to place 3D drawing buffer in system memory\n");
410 return 2;
411 case check_texture_addr0:
412 cur_seq->unfinished = tex_address;
413 tmp = (cmd >> 24);
414 tmp_addr = &cur_seq->t_addr[cur_seq->texture][tmp];
415 *tmp_addr = (*tmp_addr & 0xFF000000) | (cmd & 0x00FFFFFF);
416 return 0;
417 case check_texture_addr1:
418 cur_seq->unfinished = tex_address;
419 tmp = ((cmd >> 24) - 0x20);
420 tmp += tmp << 1;
421 tmp_addr = &cur_seq->t_addr[cur_seq->texture][tmp];
422 *tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF) << 24);
423 tmp_addr++;
424 *tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF00) << 16);
425 tmp_addr++;
426 *tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF0000) << 8);
427 return 0;
428 case check_texture_addr2:
429 cur_seq->unfinished = tex_address;
430 cur_seq->tex_level_lo[tmp = cur_seq->texture] = cmd & 0x3F;
431 cur_seq->tex_level_hi[tmp] = (cmd & 0xFC0) >> 6;
432 return 0;
433 case check_texture_addr3:
434 cur_seq->unfinished = tex_address;
435 tmp = ((cmd >> 24) - 0x2B);
436 cur_seq->pitch[cur_seq->texture][tmp] = (cmd & 0x00F00000) >> 20;
437 if (!tmp && (cmd & 0x000FFFFF)) {
438 DRM_ERROR("Unimplemented texture level 0 pitch mode.\n");
439 return 2;
440 }
441 return 0;
442 case check_texture_addr4:
443 cur_seq->unfinished = tex_address;
444 tmp_addr = &cur_seq->t_addr[cur_seq->texture][9];
445 *tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF) << 24);
446 return 0;
447 case check_texture_addr5:
448 case check_texture_addr6:
449 cur_seq->unfinished = tex_address;
450 /*
451 * Texture width. We don't care since we have the pitch.
452 */
453 return 0;
454 case check_texture_addr7:
455 cur_seq->unfinished = tex_address;
456 tmp_addr = &(cur_seq->height[cur_seq->texture][0]);
457 tmp_addr[5] = 1 << ((cmd & 0x00F00000) >> 20);
458 tmp_addr[4] = 1 << ((cmd & 0x000F0000) >> 16);
459 tmp_addr[3] = 1 << ((cmd & 0x0000F000) >> 12);
460 tmp_addr[2] = 1 << ((cmd & 0x00000F00) >> 8);
461 tmp_addr[1] = 1 << ((cmd & 0x000000F0) >> 4);
462 tmp_addr[0] = 1 << (cmd & 0x0000000F);
463 return 0;
464 case check_texture_addr8:
465 cur_seq->unfinished = tex_address;
466 tmp_addr = &(cur_seq->height[cur_seq->texture][0]);
467 tmp_addr[9] = 1 << ((cmd & 0x0000F000) >> 12);
468 tmp_addr[8] = 1 << ((cmd & 0x00000F00) >> 8);
469 tmp_addr[7] = 1 << ((cmd & 0x000000F0) >> 4);
470 tmp_addr[6] = 1 << (cmd & 0x0000000F);
471 return 0;
472 case check_texture_addr_mode:
473 cur_seq->unfinished = tex_address;
474 if ( 2 == (tmp = cmd & 0x00000003)) {
475 DRM_ERROR("Attempt to fetch texture from system memory.\n");
476 return 2;
477 }
478 cur_seq->agp_texture = (tmp == 3);
479 cur_seq->tex_palette_size[cur_seq->texture] =
480 (cmd >> 16) & 0x000000007;
481 return 0;
482 case check_for_vertex_count:
483 cur_seq->vertex_count = cmd & 0x0000FFFF;
484 return 0;
485 case check_number_texunits:
486 cur_seq->multitex = (cmd >> 3) & 1;
487 return 0;
488 default:
489 DRM_ERROR("Illegal DMA data: 0x%x\n", cmd);
490 return 2;
491 }
492 return 2;
493}
494
495
496static __inline__ int
497via_check_prim_list(uint32_t const **buffer, const uint32_t *buf_end,
498 drm_via_state_t *cur_seq)
499{
500 drm_via_private_t *dev_priv = (drm_via_private_t *) cur_seq->dev->dev_private;
501 uint32_t a_fire, bcmd , dw_count;
502 int ret = 0;
503 int have_fire;
504 const uint32_t *buf = *buffer;
505
506 while(buf < buf_end) {
507 have_fire = 0;
508 if ((buf_end - buf) < 2) {
509 DRM_ERROR("Unexpected termination of primitive list.\n");
510 ret = 1;
511 break;
512 }
513 if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdB) break;
514 bcmd = *buf++;
515 if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdA) {
516 DRM_ERROR("Expected Vertex List A command, got 0x%x\n",
517 *buf);
518 ret = 1;
519 break;
520 }
521 a_fire = *buf++ | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK;
522
523 /*
524 * How many dwords per vertex ?
525 */
526
527 if (cur_seq->agp && ((bcmd & (0xF << 11)) == 0)) {
528 DRM_ERROR("Illegal B command vertex data for AGP.\n");
529 ret = 1;
530 break;
531 }
532
533 dw_count = 0;
534 if (bcmd & (1 << 7)) dw_count += (cur_seq->multitex) ? 2:1;
535 if (bcmd & (1 << 8)) dw_count += (cur_seq->multitex) ? 2:1;
536 if (bcmd & (1 << 9)) dw_count++;
537 if (bcmd & (1 << 10)) dw_count++;
538 if (bcmd & (1 << 11)) dw_count++;
539 if (bcmd & (1 << 12)) dw_count++;
540 if (bcmd & (1 << 13)) dw_count++;
541 if (bcmd & (1 << 14)) dw_count++;
542
543 while(buf < buf_end) {
544 if (*buf == a_fire) {
545 if (dev_priv->num_fire_offsets >= VIA_FIRE_BUF_SIZE) {
546 DRM_ERROR("Fire offset buffer full.\n");
547 ret = 1;
548 break;
549 }
550 dev_priv->fire_offsets[dev_priv->num_fire_offsets++] = buf;
551 have_fire = 1;
552 buf++;
553 if (buf < buf_end && *buf == a_fire)
554 buf++;
555 break;
556 }
557 if ((*buf == HALCYON_HEADER2) ||
558 ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD)) {
559 DRM_ERROR("Missing Vertex Fire command, "
560 "Stray Vertex Fire command or verifier "
561 "lost sync.\n");
562 ret = 1;
563 break;
564 }
565 if ((ret = eat_words(&buf, buf_end, dw_count)))
566 break;
567 }
568 if (buf >= buf_end && !have_fire) {
569 DRM_ERROR("Missing Vertex Fire command or verifier "
570 "lost sync.\n");
571 ret = 1;
572 break;
573 }
574 if (cur_seq->agp && ((buf - cur_seq->buf_start) & 0x01)) {
575 DRM_ERROR("AGP Primitive list end misaligned.\n");
576 ret = 1;
577 break;
578 }
579 }
580 *buffer = buf;
581 return ret;
582}
583
584
585
586
587
588static __inline__ verifier_state_t
589via_check_header2( uint32_t const **buffer, const uint32_t *buf_end,
590 drm_via_state_t *hc_state)
591{
592 uint32_t cmd;
593 int hz_mode;
594 hazard_t hz;
595 const uint32_t *buf = *buffer;
596 const hazard_t *hz_table;
597
598
599 if ((buf_end - buf) < 2) {
600 DRM_ERROR("Illegal termination of DMA HALCYON_HEADER2 sequence.\n");
601 return state_error;
602 }
603 buf++;
604 cmd = (*buf++ & 0xFFFF0000) >> 16;
605
606 switch(cmd) {
607 case HC_ParaType_CmdVdata:
608 if (via_check_prim_list(&buf, buf_end, hc_state ))
609 return state_error;
610 *buffer = buf;
611 return state_command;
612 case HC_ParaType_NotTex:
613 hz_table = table1;
614 break;
615 case HC_ParaType_Tex:
616 hc_state->texture = 0;
617 hz_table = table2;
618 break;
619 case (HC_ParaType_Tex | (HC_SubType_Tex1 << 8)):
620 hc_state->texture = 1;
621 hz_table = table2;
622 break;
623 case (HC_ParaType_Tex | (HC_SubType_TexGeneral << 8)):
624 hz_table = table3;
625 break;
626 case HC_ParaType_Auto:
627 if (eat_words(&buf, buf_end, 2))
628 return state_error;
629 *buffer = buf;
630 return state_command;
631 case (HC_ParaType_Palette | (HC_SubType_Stipple << 8)):
632 if (eat_words(&buf, buf_end, 32))
633 return state_error;
634 *buffer = buf;
635 return state_command;
636 case (HC_ParaType_Palette | (HC_SubType_TexPalette0 << 8)):
637 case (HC_ParaType_Palette | (HC_SubType_TexPalette1 << 8)):
638 DRM_ERROR("Texture palettes are rejected because of "
639 "lack of info how to determine their size.\n");
640 return state_error;
641 case (HC_ParaType_Palette | (HC_SubType_FogTable << 8)):
642 DRM_ERROR("Fog factor palettes are rejected because of "
643 "lack of info how to determine their size.\n");
644 return state_error;
645 default:
646
647 /*
648 * There are some unimplemented HC_ParaTypes here, that
649 * need to be implemented if the Mesa driver is extended.
650 */
651
652 DRM_ERROR("Invalid or unimplemented HALCYON_HEADER2 "
653 "DMA subcommand: 0x%x. Previous dword: 0x%x\n",
654 cmd, *(buf -2));
655 *buffer = buf;
656 return state_error;
657 }
658
659 while(buf < buf_end) {
660 cmd = *buf++;
661 if ((hz = hz_table[cmd >> 24])) {
662 if ((hz_mode = investigate_hazard(cmd, hz, hc_state))) {
663 if (hz_mode == 1) {
664 buf--;
665 break;
666 }
667 return state_error;
668 }
669 } else if (hc_state->unfinished &&
670 finish_current_sequence(hc_state)) {
671 return state_error;
672 }
673 }
674 if (hc_state->unfinished && finish_current_sequence(hc_state)) {
675 return state_error;
676 }
677 *buffer = buf;
678 return state_command;
679}
680
681static __inline__ verifier_state_t
682via_parse_header2( drm_via_private_t *dev_priv, uint32_t const **buffer, const uint32_t *buf_end,
683 int *fire_count)
684{
685 uint32_t cmd;
686 const uint32_t *buf = *buffer;
687 const uint32_t *next_fire;
688 int burst = 0;
689
690 next_fire = dev_priv->fire_offsets[*fire_count];
691 buf++;
692 cmd = (*buf & 0xFFFF0000) >> 16;
693 VIA_WRITE(HC_REG_TRANS_SET + HC_REG_BASE, *buf++);
694 switch(cmd) {
695 case HC_ParaType_CmdVdata:
696 while ((buf < buf_end) &&
697 (*fire_count < dev_priv->num_fire_offsets) &&
698 (*buf & HC_ACMD_MASK) == HC_ACMD_HCmdB ) {
699 while(buf <= next_fire) {
700 VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE + (burst & 63), *buf++);
701 burst += 4;
702 }
703 if ( ( buf < buf_end ) && ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD))
704 buf++;
705
706 if (++(*fire_count) < dev_priv->num_fire_offsets)
707 next_fire = dev_priv->fire_offsets[*fire_count];
708 }
709 break;
710 default:
711 while(buf < buf_end) {
712
713 if ( *buf == HC_HEADER2 ||
714 (*buf & HALCYON_HEADER1MASK) == HALCYON_HEADER1 ||
715 (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5 ||
716 (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6 ) break;
717
718 VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE + (burst & 63), *buf++);
719 burst +=4;
720 }
721 }
722 *buffer = buf;
723 return state_command;
724}
725
726
727
728static __inline__ int
729verify_mmio_address( uint32_t address)
730{
731 if ((address > 0x3FF) && (address < 0xC00 )) {
732 DRM_ERROR("Invalid VIDEO DMA command. "
733 "Attempt to access 3D- or command burst area.\n");
734 return 1;
735 } else if ((address > 0xCFF) && (address < 0x1300)) {
736 DRM_ERROR("Invalid VIDEO DMA command. "
737 "Attempt to access PCI DMA area.\n");
738 return 1;
739 } else if (address > 0x13FF ) {
740 DRM_ERROR("Invalid VIDEO DMA command. "
741 "Attempt to access VGA registers.\n");
742 return 1;
743 }
744 return 0;
745}
746
747static __inline__ int
748verify_video_tail( uint32_t const **buffer, const uint32_t *buf_end, uint32_t dwords)
749{
750 const uint32_t *buf = *buffer;
751
752 if (buf_end - buf < dwords) {
753 DRM_ERROR("Illegal termination of video command.\n");
754 return 1;
755 }
756 while (dwords--) {
757 if (*buf++) {
758 DRM_ERROR("Illegal video command tail.\n");
759 return 1;
760 }
761 }
762 *buffer = buf;
763 return 0;
764}
765
766
767static __inline__ verifier_state_t
768via_check_header1( uint32_t const **buffer, const uint32_t *buf_end )
769{
770 uint32_t cmd;
771 const uint32_t *buf = *buffer;
772 verifier_state_t ret = state_command;
773
774 while (buf < buf_end) {
775 cmd = *buf;
776 if ((cmd > ((0x3FF >> 2) | HALCYON_HEADER1)) &&
777 (cmd < ((0xC00 >> 2) | HALCYON_HEADER1))) {
778 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
779 break;
780 DRM_ERROR("Invalid HALCYON_HEADER1 command. "
781 "Attempt to access 3D- or command burst area.\n");
782 ret = state_error;
783 break;
784 } else if (cmd > ((0xCFF >> 2) | HALCYON_HEADER1)) {
785 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
786 break;
787 DRM_ERROR("Invalid HALCYON_HEADER1 command. "
788 "Attempt to access VGA registers.\n");
789 ret = state_error;
790 break;
791 } else {
792 buf += 2;
793 }
794 }
795 *buffer = buf;
796 return ret;
797}
798
799static __inline__ verifier_state_t
800via_parse_header1( drm_via_private_t *dev_priv, uint32_t const **buffer, const uint32_t *buf_end )
801{
802 register uint32_t cmd;
803 const uint32_t *buf = *buffer;
804
805 while (buf < buf_end) {
806 cmd = *buf;
807 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1) break;
808 VIA_WRITE( (cmd & ~HALCYON_HEADER1MASK) << 2, *++buf);
809 buf++;
810 }
811 *buffer = buf;
812 return state_command;
813}
814
815static __inline__ verifier_state_t
816via_check_vheader5( uint32_t const **buffer, const uint32_t *buf_end )
817{
818 uint32_t data;
819 const uint32_t *buf = *buffer;
820
821 if (buf_end - buf < 4) {
822 DRM_ERROR("Illegal termination of video header5 command\n");
823 return state_error;
824 }
825
826 data = *buf++ & ~VIA_VIDEOMASK;
827 if (verify_mmio_address(data))
828 return state_error;
829
830 data = *buf++;
831 if (*buf++ != 0x00F50000) {
832 DRM_ERROR("Illegal header5 header data\n");
833 return state_error;
834 }
835 if (*buf++ != 0x00000000) {
836 DRM_ERROR("Illegal header5 header data\n");
837 return state_error;
838 }
839 if (eat_words(&buf, buf_end, data))
840 return state_error;
841 if ((data & 3) && verify_video_tail(&buf, buf_end, 4 - (data & 3)))
842 return state_error;
843 *buffer = buf;
844 return state_command;
845
846}
847
848static __inline__ verifier_state_t
849via_parse_vheader5( drm_via_private_t *dev_priv, uint32_t const **buffer, const uint32_t *buf_end )
850{
851 uint32_t addr, count, i;
852 const uint32_t *buf = *buffer;
853
854 addr = *buf++ & ~VIA_VIDEOMASK;
855 i = count = *buf;
856 buf += 3;
857 while(i--) {
858 VIA_WRITE(addr, *buf++);
859 }
860 if (count & 3) buf += 4 - (count & 3);
861 *buffer = buf;
862 return state_command;
863}
864
865
866static __inline__ verifier_state_t
867via_check_vheader6( uint32_t const **buffer, const uint32_t *buf_end )
868{
869 uint32_t data;
870 const uint32_t *buf = *buffer;
871 uint32_t i;
872
873
874 if (buf_end - buf < 4) {
875 DRM_ERROR("Illegal termination of video header6 command\n");
876 return state_error;
877 }
878 buf++;
879 data = *buf++;
880 if (*buf++ != 0x00F60000) {
881 DRM_ERROR("Illegal header6 header data\n");
882 return state_error;
883 }
884 if (*buf++ != 0x00000000) {
885 DRM_ERROR("Illegal header6 header data\n");
886 return state_error;
887 }
888 if ((buf_end - buf) < (data << 1)) {
889 DRM_ERROR("Illegal termination of video header6 command\n");
890 return state_error;
891 }
892 for (i=0; i<data; ++i) {
893 if (verify_mmio_address(*buf++))
894 return state_error;
895 buf++;
896 }
897 data <<= 1;
898 if ((data & 3) && verify_video_tail(&buf, buf_end, 4 - (data & 3)))
899 return state_error;
900 *buffer = buf;
901 return state_command;
902}
903
904static __inline__ verifier_state_t
905via_parse_vheader6( drm_via_private_t *dev_priv, uint32_t const **buffer, const uint32_t *buf_end )
906{
907
908 uint32_t addr, count, i;
909 const uint32_t *buf = *buffer;
910
911 i = count = *++buf;
912 buf += 3;
913 while(i--) {
914 addr = *buf++;
915 VIA_WRITE(addr, *buf++);
916 }
917 count <<= 1;
918 if (count & 3) buf += 4 - (count & 3);
919 *buffer = buf;
920 return state_command;
921}
922
923
924
925int
926via_verify_command_stream(const uint32_t * buf, unsigned int size, drm_device_t *dev,
927 int agp)
928{
929
930 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
931 drm_via_state_t *hc_state = &dev_priv->hc_state;
932 drm_via_state_t saved_state = *hc_state;
933 uint32_t cmd;
934 const uint32_t *buf_end = buf + ( size >> 2 );
935 verifier_state_t state = state_command;
936 int pro_group_a = dev_priv->pro_group_a;
937
938 hc_state->dev = dev;
939 hc_state->unfinished = no_sequence;
940 hc_state->map_cache = NULL;
941 hc_state->agp = agp;
942 hc_state->buf_start = buf;
943 dev_priv->num_fire_offsets = 0;
944
945 while (buf < buf_end) {
946
947 switch (state) {
948 case state_header2:
949 state = via_check_header2( &buf, buf_end, hc_state );
950 break;
951 case state_header1:
952 state = via_check_header1( &buf, buf_end );
953 break;
954 case state_vheader5:
955 state = via_check_vheader5( &buf, buf_end );
956 break;
957 case state_vheader6:
958 state = via_check_vheader6( &buf, buf_end );
959 break;
960 case state_command:
961 if (HALCYON_HEADER2 == (cmd = *buf))
962 state = state_header2;
963 else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
964 state = state_header1;
965 else if (pro_group_a && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5)
966 state = state_vheader5;
967 else if (pro_group_a && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
968 state = state_vheader6;
969 else {
970 DRM_ERROR("Invalid / Unimplemented DMA HEADER command. 0x%x\n",
971 cmd);
972 state = state_error;
973 }
974 break;
975 case state_error:
976 default:
977 *hc_state = saved_state;
978 return DRM_ERR(EINVAL);
979 }
980 }
981 if (state == state_error) {
982 *hc_state = saved_state;
983 return DRM_ERR(EINVAL);
984 }
985 return 0;
986}
987
988int
989via_parse_command_stream(drm_device_t *dev, const uint32_t * buf, unsigned int size)
990{
991
992 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
993 uint32_t cmd;
994 const uint32_t *buf_end = buf + ( size >> 2 );
995 verifier_state_t state = state_command;
996 int fire_count = 0;
997
998 while (buf < buf_end) {
999
1000 switch (state) {
1001 case state_header2:
1002 state = via_parse_header2( dev_priv, &buf, buf_end, &fire_count );
1003 break;
1004 case state_header1:
1005 state = via_parse_header1( dev_priv, &buf, buf_end );
1006 break;
1007 case state_vheader5:
1008 state = via_parse_vheader5( dev_priv, &buf, buf_end );
1009 break;
1010 case state_vheader6:
1011 state = via_parse_vheader6( dev_priv, &buf, buf_end );
1012 break;
1013 case state_command:
1014 if (HALCYON_HEADER2 == (cmd = *buf))
1015 state = state_header2;
1016 else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
1017 state = state_header1;
1018 else if ((cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5)
1019 state = state_vheader5;
1020 else if ((cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
1021 state = state_vheader6;
1022 else {
1023 DRM_ERROR("Invalid / Unimplemented DMA HEADER command. 0x%x\n",
1024 cmd);
1025 state = state_error;
1026 }
1027 break;
1028 case state_error:
1029 default:
1030 return DRM_ERR(EINVAL);
1031 }
1032 }
1033 if (state == state_error) {
1034 return DRM_ERR(EINVAL);
1035 }
1036 return 0;
1037}
1038
1039
1040
1041static void
1042setup_hazard_table(hz_init_t init_table[], hazard_t table[], int size)
1043{
1044 int i;
1045
1046 for(i=0; i<256; ++i) {
1047 table[i] = forbidden_command;
1048 }
1049
1050 for(i=0; i<size; ++i) {
1051 table[init_table[i].code] = init_table[i].hz;
1052 }
1053}
1054
1055void
1056via_init_command_verifier( void )
1057{
1058 setup_hazard_table(init_table1, table1, sizeof(init_table1) / sizeof(hz_init_t));
1059 setup_hazard_table(init_table2, table2, sizeof(init_table2) / sizeof(hz_init_t));
1060 setup_hazard_table(init_table3, table3, sizeof(init_table3) / sizeof(hz_init_t));
1061}
diff --git a/drivers/char/drm/via_verifier.h b/drivers/char/drm/via_verifier.h
new file mode 100644
index 000000000000..a8e13592620f
--- /dev/null
+++ b/drivers/char/drm/via_verifier.h
@@ -0,0 +1,61 @@
1/*
2 * Copyright 2004 The Unichrome Project. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE UNICHROME PROJECT, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Thomas Hellström 2004.
24 */
25
26#ifndef _VIA_VERIFIER_H_
27#define _VIA_VERIFIER_H_
28
29typedef enum{
30 no_sequence = 0,
31 z_address,
32 dest_address,
33 tex_address
34}drm_via_sequence_t;
35
36
37
38typedef struct{
39 unsigned texture;
40 uint32_t z_addr;
41 uint32_t d_addr;
42 uint32_t t_addr[2][10];
43 uint32_t pitch[2][10];
44 uint32_t height[2][10];
45 uint32_t tex_level_lo[2];
46 uint32_t tex_level_hi[2];
47 uint32_t tex_palette_size[2];
48 drm_via_sequence_t unfinished;
49 int agp_texture;
50 int multitex;
51 drm_device_t *dev;
52 drm_map_t *map_cache;
53 uint32_t vertex_count;
54 int agp;
55 const uint32_t *buf_start;
56} drm_via_state_t;
57
58extern int via_verify_command_stream(const uint32_t * buf, unsigned int size,
59 drm_device_t *dev, int agp);
60
61#endif
diff --git a/drivers/char/drm/via_video.c b/drivers/char/drm/via_video.c
new file mode 100644
index 000000000000..37a61c67b292
--- /dev/null
+++ b/drivers/char/drm/via_video.c
@@ -0,0 +1,97 @@
1/*
2 * Copyright 2005 Thomas Hellstrom. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S), AND/OR THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Thomas Hellstrom 2005.
24 *
25 * Video and XvMC related functions.
26 */
27
28#include "drmP.h"
29#include "via_drm.h"
30#include "via_drv.h"
31
32void
33via_init_futex(drm_via_private_t *dev_priv)
34{
35 unsigned int i;
36
37 DRM_DEBUG("%s\n", __FUNCTION__);
38
39 for (i = 0; i < VIA_NR_XVMC_LOCKS; ++i) {
40 DRM_INIT_WAITQUEUE(&(dev_priv->decoder_queue[i]));
41 XVMCLOCKPTR(dev_priv->sarea_priv, i)->lock = 0;
42 }
43}
44
45void
46via_cleanup_futex(drm_via_private_t *dev_priv)
47{
48}
49
50void
51via_release_futex(drm_via_private_t *dev_priv, int context)
52{
53 unsigned int i;
54 volatile int *lock;
55
56 for (i=0; i < VIA_NR_XVMC_LOCKS; ++i) {
57 lock = (int *) XVMCLOCKPTR(dev_priv->sarea_priv, i);
58 if ( (_DRM_LOCKING_CONTEXT( *lock ) == context)) {
59 if (_DRM_LOCK_IS_HELD( *lock ) && (*lock & _DRM_LOCK_CONT)) {
60 DRM_WAKEUP( &(dev_priv->decoder_queue[i]));
61 }
62 *lock = 0;
63 }
64 }
65}
66
67int
68via_decoder_futex(DRM_IOCTL_ARGS)
69{
70 DRM_DEVICE;
71 drm_via_futex_t fx;
72 volatile int *lock;
73 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
74 drm_via_sarea_t *sAPriv = dev_priv->sarea_priv;
75 int ret = 0;
76
77 DRM_DEBUG("%s\n", __FUNCTION__);
78
79 DRM_COPY_FROM_USER_IOCTL(fx, (drm_via_futex_t *) data, sizeof(fx));
80
81 if (fx.lock > VIA_NR_XVMC_LOCKS)
82 return -EFAULT;
83
84 lock = (int *)XVMCLOCKPTR(sAPriv, fx.lock);
85
86 switch (fx.func) {
87 case VIA_FUTEX_WAIT:
88 DRM_WAIT_ON(ret, dev_priv->decoder_queue[fx.lock],
89 (fx.ms / 10) * (DRM_HZ / 100), *lock != fx.val);
90 return ret;
91 case VIA_FUTEX_WAKE:
92 DRM_WAKEUP(&(dev_priv->decoder_queue[fx.lock]));
93 return 0;
94 }
95 return 0;
96}
97
diff --git a/drivers/ieee1394/Kconfig b/drivers/ieee1394/Kconfig
index 7d58af1ae306..25103a0ef9b3 100644
--- a/drivers/ieee1394/Kconfig
+++ b/drivers/ieee1394/Kconfig
@@ -66,6 +66,18 @@ config IEEE1394_CONFIG_ROM_IP1394
66 with MacOSX and WinXP IP-over-1394), enable this option and the 66 with MacOSX and WinXP IP-over-1394), enable this option and the
67 eth1394 option below. 67 eth1394 option below.
68 68
69config IEEE1394_EXPORT_FULL_API
70 bool "Export all symbols of ieee1394's API"
71 depends on IEEE1394
72 default n
73 help
74 Export all symbols of ieee1394's driver programming interface, even
75 those that are not currently used by the standard IEEE 1394 drivers.
76
77 This option does not affect the interface to userspace applications.
78 Say Y here if you want to compile externally developed drivers that
79 make extended use of ieee1394's API. It is otherwise safe to say N.
80
69comment "Device Drivers" 81comment "Device Drivers"
70 depends on IEEE1394 82 depends on IEEE1394
71 83
diff --git a/drivers/ieee1394/csr.c b/drivers/ieee1394/csr.c
index 1b98684aebcd..149573db91c5 100644
--- a/drivers/ieee1394/csr.c
+++ b/drivers/ieee1394/csr.c
@@ -28,6 +28,7 @@
28#include "hosts.h" 28#include "hosts.h"
29#include "ieee1394.h" 29#include "ieee1394.h"
30#include "highlevel.h" 30#include "highlevel.h"
31#include "ieee1394_core.h"
31 32
32/* Module Parameters */ 33/* Module Parameters */
33/* this module parameter can be used to disable mapping of the FCP registers */ 34/* this module parameter can be used to disable mapping of the FCP registers */
@@ -232,7 +233,7 @@ static void add_host(struct hpsb_host *host)
232 host->csr.generation = 2; 233 host->csr.generation = 2;
233 234
234 bus_info[1] = __constant_cpu_to_be32(0x31333934); 235 bus_info[1] = __constant_cpu_to_be32(0x31333934);
235 bus_info[2] = cpu_to_be32((1 << CSR_IRMC_SHIFT) | 236 bus_info[2] = cpu_to_be32((hpsb_disable_irm ? 0 : 1 << CSR_IRMC_SHIFT) |
236 (1 << CSR_CMC_SHIFT) | 237 (1 << CSR_CMC_SHIFT) |
237 (1 << CSR_ISC_SHIFT) | 238 (1 << CSR_ISC_SHIFT) |
238 (0 << CSR_BMC_SHIFT) | 239 (0 << CSR_BMC_SHIFT) |
diff --git a/drivers/ieee1394/csr1212.c b/drivers/ieee1394/csr1212.c
index 7c4330e2e875..61ddd5d37eff 100644
--- a/drivers/ieee1394/csr1212.c
+++ b/drivers/ieee1394/csr1212.c
@@ -209,7 +209,15 @@ void csr1212_init_local_csr(struct csr1212_csr *csr,
209{ 209{
210 static const int mr_map[] = { 4, 64, 1024, 0 }; 210 static const int mr_map[] = { 4, 64, 1024, 0 };
211 211
212#ifdef __KERNEL__
213 BUG_ON(max_rom & ~0x3);
212 csr->max_rom = mr_map[max_rom]; 214 csr->max_rom = mr_map[max_rom];
215#else
216 if (max_rom & ~0x3) /* caller supplied invalid argument */
217 csr->max_rom = 0;
218 else
219 csr->max_rom = mr_map[max_rom];
220#endif
213 memcpy(csr->bus_info_data, bus_info_data, csr->bus_info_len); 221 memcpy(csr->bus_info_data, bus_info_data, csr->bus_info_len);
214} 222}
215 223
@@ -533,12 +541,15 @@ struct csr1212_keyval *csr1212_new_icon_descriptor_leaf(u_int32_t version,
533 static const int pd[4] = { 0, 4, 16, 256 }; 541 static const int pd[4] = { 0, 4, 16, 256 };
534 static const int cs[16] = { 4, 2 }; 542 static const int cs[16] = { 4, 2 };
535 struct csr1212_keyval *kv; 543 struct csr1212_keyval *kv;
536 int palette_size = pd[palette_depth] * cs[color_space]; 544 int palette_size;
537 int pixel_size = (hscan * vscan + 3) & ~0x3; 545 int pixel_size = (hscan * vscan + 3) & ~0x3;
538 546
539 if ((palette_depth && !palette) || !pixels) 547 if (!pixels || (!palette && palette_depth) ||
548 (palette_depth & ~0x3) || (color_space & ~0xf))
540 return NULL; 549 return NULL;
541 550
551 palette_size = pd[palette_depth] * cs[color_space];
552
542 kv = csr1212_new_descriptor_leaf(1, 0, NULL, 553 kv = csr1212_new_descriptor_leaf(1, 0, NULL,
543 palette_size + pixel_size + 554 palette_size + pixel_size +
544 CSR1212_ICON_DESCRIPTOR_LEAF_OVERHEAD); 555 CSR1212_ICON_DESCRIPTOR_LEAF_OVERHEAD);
@@ -760,9 +771,9 @@ static int csr1212_append_new_cache(struct csr1212_csr *csr, size_t romsize)
760 struct csr1212_csr_rom_cache *cache; 771 struct csr1212_csr_rom_cache *cache;
761 u_int64_t csr_addr; 772 u_int64_t csr_addr;
762 773
763 if (!csr || !csr->ops->allocate_addr_range || 774 if (!csr || !csr->ops || !csr->ops->allocate_addr_range ||
764 !csr->ops->release_addr) 775 !csr->ops->release_addr || csr->max_rom < 1)
765 return CSR1212_ENOMEM; 776 return CSR1212_EINVAL;
766 777
767 /* ROM size must be a multiple of csr->max_rom */ 778 /* ROM size must be a multiple of csr->max_rom */
768 romsize = (romsize + (csr->max_rom - 1)) & ~(csr->max_rom - 1); 779 romsize = (romsize + (csr->max_rom - 1)) & ~(csr->max_rom - 1);
@@ -1145,6 +1156,8 @@ int csr1212_generate_csr_image(struct csr1212_csr *csr)
1145 1156
1146 /* Make sure the Extended ROM leaf is a multiple of 1157 /* Make sure the Extended ROM leaf is a multiple of
1147 * max_rom in size. */ 1158 * max_rom in size. */
1159 if (csr->max_rom < 1)
1160 return CSR1212_EINVAL;
1148 leaf_size = (cache->len + (csr->max_rom - 1)) & 1161 leaf_size = (cache->len + (csr->max_rom - 1)) &
1149 ~(csr->max_rom - 1); 1162 ~(csr->max_rom - 1);
1150 1163
@@ -1409,7 +1422,7 @@ int _csr1212_read_keyval(struct csr1212_csr *csr, struct csr1212_keyval *kv)
1409 u_int32_t *cache_ptr; 1422 u_int32_t *cache_ptr;
1410 u_int16_t kv_len = 0; 1423 u_int16_t kv_len = 0;
1411 1424
1412 if (!csr || !kv) 1425 if (!csr || !kv || csr->max_rom < 1)
1413 return CSR1212_EINVAL; 1426 return CSR1212_EINVAL;
1414 1427
1415 /* First find which cache the data should be in (or go in if not read 1428 /* First find which cache the data should be in (or go in if not read
@@ -1572,7 +1585,7 @@ int csr1212_parse_csr(struct csr1212_csr *csr)
1572 struct csr1212_dentry *dentry; 1585 struct csr1212_dentry *dentry;
1573 int ret; 1586 int ret;
1574 1587
1575 if (!csr || !csr->ops->bus_read) 1588 if (!csr || !csr->ops || !csr->ops->bus_read)
1576 return CSR1212_EINVAL; 1589 return CSR1212_EINVAL;
1577 1590
1578 ret = csr1212_parse_bus_info_block(csr); 1591 ret = csr1212_parse_bus_info_block(csr);
@@ -1581,9 +1594,13 @@ int csr1212_parse_csr(struct csr1212_csr *csr)
1581 1594
1582 if (!csr->ops->get_max_rom) 1595 if (!csr->ops->get_max_rom)
1583 csr->max_rom = mr_map[0]; /* default value */ 1596 csr->max_rom = mr_map[0]; /* default value */
1584 else 1597 else {
1585 csr->max_rom = mr_map[csr->ops->get_max_rom(csr->bus_info_data, 1598 int i = csr->ops->get_max_rom(csr->bus_info_data,
1586 csr->private)]; 1599 csr->private);
1600 if (i & ~0x3)
1601 return CSR1212_EINVAL;
1602 csr->max_rom = mr_map[i];
1603 }
1587 1604
1588 csr->cache_head->layout_head = csr->root_kv; 1605 csr->cache_head->layout_head = csr->root_kv;
1589 csr->cache_head->layout_tail = csr->root_kv; 1606 csr->cache_head->layout_tail = csr->root_kv;
diff --git a/drivers/ieee1394/dma.c b/drivers/ieee1394/dma.c
index 758819d1999d..b79ddb43e746 100644
--- a/drivers/ieee1394/dma.c
+++ b/drivers/ieee1394/dma.c
@@ -158,7 +158,7 @@ static inline int dma_region_find(struct dma_region *dma, unsigned long offset,
158 158
159dma_addr_t dma_region_offset_to_bus(struct dma_region *dma, unsigned long offset) 159dma_addr_t dma_region_offset_to_bus(struct dma_region *dma, unsigned long offset)
160{ 160{
161 unsigned long rem; 161 unsigned long rem = 0;
162 162
163 struct scatterlist *sg = &dma->sglist[dma_region_find(dma, offset, &rem)]; 163 struct scatterlist *sg = &dma->sglist[dma_region_find(dma, offset, &rem)];
164 return sg_dma_address(sg) + rem; 164 return sg_dma_address(sg) + rem;
diff --git a/drivers/ieee1394/eth1394.c b/drivers/ieee1394/eth1394.c
index 654da76bf811..cd53c174ced1 100644
--- a/drivers/ieee1394/eth1394.c
+++ b/drivers/ieee1394/eth1394.c
@@ -89,7 +89,7 @@
89#define TRACE() printk(KERN_ERR "%s:%s[%d] ---- TRACE\n", driver_name, __FUNCTION__, __LINE__) 89#define TRACE() printk(KERN_ERR "%s:%s[%d] ---- TRACE\n", driver_name, __FUNCTION__, __LINE__)
90 90
91static char version[] __devinitdata = 91static char version[] __devinitdata =
92 "$Rev: 1247 $ Ben Collins <bcollins@debian.org>"; 92 "$Rev: 1264 $ Ben Collins <bcollins@debian.org>";
93 93
94struct fragment_info { 94struct fragment_info {
95 struct list_head list; 95 struct list_head list;
@@ -706,7 +706,7 @@ static void ether1394_host_reset (struct hpsb_host *host)
706 return; 706 return;
707 707
708 dev = hi->dev; 708 dev = hi->dev;
709 priv = netdev_priv(dev); 709 priv = (struct eth1394_priv *)netdev_priv(dev);
710 710
711 /* Reset our private host data, but not our mtu */ 711 /* Reset our private host data, but not our mtu */
712 netif_stop_queue (dev); 712 netif_stop_queue (dev);
@@ -1770,7 +1770,7 @@ fail:
1770static void ether1394_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1770static void ether1394_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1771{ 1771{
1772 strcpy (info->driver, driver_name); 1772 strcpy (info->driver, driver_name);
1773 strcpy (info->version, "$Rev: 1247 $"); 1773 strcpy (info->version, "$Rev: 1264 $");
1774 /* FIXME XXX provide sane businfo */ 1774 /* FIXME XXX provide sane businfo */
1775 strcpy (info->bus_info, "ieee1394"); 1775 strcpy (info->bus_info, "ieee1394");
1776} 1776}
diff --git a/drivers/ieee1394/ieee1394_core.c b/drivers/ieee1394/ieee1394_core.c
index 629070b83a33..b248d89de8b4 100644
--- a/drivers/ieee1394/ieee1394_core.c
+++ b/drivers/ieee1394/ieee1394_core.c
@@ -52,7 +52,7 @@
52/* 52/*
53 * Disable the nodemgr detection and config rom reading functionality. 53 * Disable the nodemgr detection and config rom reading functionality.
54 */ 54 */
55static int disable_nodemgr = 0; 55static int disable_nodemgr;
56module_param(disable_nodemgr, int, 0444); 56module_param(disable_nodemgr, int, 0444);
57MODULE_PARM_DESC(disable_nodemgr, "Disable nodemgr functionality."); 57MODULE_PARM_DESC(disable_nodemgr, "Disable nodemgr functionality.");
58 58
@@ -520,6 +520,9 @@ int hpsb_send_packet(struct hpsb_packet *packet)
520 520
521 if (!packet->no_waiter || packet->expect_response) { 521 if (!packet->no_waiter || packet->expect_response) {
522 atomic_inc(&packet->refcnt); 522 atomic_inc(&packet->refcnt);
523 /* Set the initial "sendtime" to 10 seconds from now, to
524 prevent premature expiry. If a packet takes more than
525 10 seconds to hit the wire, we have bigger problems :) */
523 packet->sendtime = jiffies + 10 * HZ; 526 packet->sendtime = jiffies + 10 * HZ;
524 skb_queue_tail(&host->pending_packet_queue, packet->skb); 527 skb_queue_tail(&host->pending_packet_queue, packet->skb);
525 } 528 }
@@ -1223,9 +1226,7 @@ EXPORT_SYMBOL(hpsb_protocol_class);
1223EXPORT_SYMBOL(hpsb_set_packet_complete_task); 1226EXPORT_SYMBOL(hpsb_set_packet_complete_task);
1224EXPORT_SYMBOL(hpsb_alloc_packet); 1227EXPORT_SYMBOL(hpsb_alloc_packet);
1225EXPORT_SYMBOL(hpsb_free_packet); 1228EXPORT_SYMBOL(hpsb_free_packet);
1226EXPORT_SYMBOL(hpsb_send_phy_config);
1227EXPORT_SYMBOL(hpsb_send_packet); 1229EXPORT_SYMBOL(hpsb_send_packet);
1228EXPORT_SYMBOL(hpsb_send_packet_and_wait);
1229EXPORT_SYMBOL(hpsb_reset_bus); 1230EXPORT_SYMBOL(hpsb_reset_bus);
1230EXPORT_SYMBOL(hpsb_bus_reset); 1231EXPORT_SYMBOL(hpsb_bus_reset);
1231EXPORT_SYMBOL(hpsb_selfid_received); 1232EXPORT_SYMBOL(hpsb_selfid_received);
@@ -1233,6 +1234,10 @@ EXPORT_SYMBOL(hpsb_selfid_complete);
1233EXPORT_SYMBOL(hpsb_packet_sent); 1234EXPORT_SYMBOL(hpsb_packet_sent);
1234EXPORT_SYMBOL(hpsb_packet_received); 1235EXPORT_SYMBOL(hpsb_packet_received);
1235EXPORT_SYMBOL_GPL(hpsb_disable_irm); 1236EXPORT_SYMBOL_GPL(hpsb_disable_irm);
1237#ifdef CONFIG_IEEE1394_EXPORT_FULL_API
1238EXPORT_SYMBOL(hpsb_send_phy_config);
1239EXPORT_SYMBOL(hpsb_send_packet_and_wait);
1240#endif
1236 1241
1237/** ieee1394_transactions.c **/ 1242/** ieee1394_transactions.c **/
1238EXPORT_SYMBOL(hpsb_get_tlabel); 1243EXPORT_SYMBOL(hpsb_get_tlabel);
@@ -1262,9 +1267,11 @@ EXPORT_SYMBOL(hpsb_destroy_hostinfo);
1262EXPORT_SYMBOL(hpsb_set_hostinfo_key); 1267EXPORT_SYMBOL(hpsb_set_hostinfo_key);
1263EXPORT_SYMBOL(hpsb_get_hostinfo_bykey); 1268EXPORT_SYMBOL(hpsb_get_hostinfo_bykey);
1264EXPORT_SYMBOL(hpsb_set_hostinfo); 1269EXPORT_SYMBOL(hpsb_set_hostinfo);
1270EXPORT_SYMBOL(highlevel_host_reset);
1271#ifdef CONFIG_IEEE1394_EXPORT_FULL_API
1265EXPORT_SYMBOL(highlevel_add_host); 1272EXPORT_SYMBOL(highlevel_add_host);
1266EXPORT_SYMBOL(highlevel_remove_host); 1273EXPORT_SYMBOL(highlevel_remove_host);
1267EXPORT_SYMBOL(highlevel_host_reset); 1274#endif
1268 1275
1269/** nodemgr.c **/ 1276/** nodemgr.c **/
1270EXPORT_SYMBOL(hpsb_node_fill_packet); 1277EXPORT_SYMBOL(hpsb_node_fill_packet);
@@ -1272,7 +1279,9 @@ EXPORT_SYMBOL(hpsb_node_write);
1272EXPORT_SYMBOL(hpsb_register_protocol); 1279EXPORT_SYMBOL(hpsb_register_protocol);
1273EXPORT_SYMBOL(hpsb_unregister_protocol); 1280EXPORT_SYMBOL(hpsb_unregister_protocol);
1274EXPORT_SYMBOL(ieee1394_bus_type); 1281EXPORT_SYMBOL(ieee1394_bus_type);
1282#ifdef CONFIG_IEEE1394_EXPORT_FULL_API
1275EXPORT_SYMBOL(nodemgr_for_each_host); 1283EXPORT_SYMBOL(nodemgr_for_each_host);
1284#endif
1276 1285
1277/** csr.c **/ 1286/** csr.c **/
1278EXPORT_SYMBOL(hpsb_update_config_rom); 1287EXPORT_SYMBOL(hpsb_update_config_rom);
@@ -1309,19 +1318,21 @@ EXPORT_SYMBOL(hpsb_iso_wake);
1309EXPORT_SYMBOL(hpsb_iso_recv_flush); 1318EXPORT_SYMBOL(hpsb_iso_recv_flush);
1310 1319
1311/** csr1212.c **/ 1320/** csr1212.c **/
1312EXPORT_SYMBOL(csr1212_create_csr);
1313EXPORT_SYMBOL(csr1212_init_local_csr);
1314EXPORT_SYMBOL(csr1212_new_immediate);
1315EXPORT_SYMBOL(csr1212_new_directory); 1321EXPORT_SYMBOL(csr1212_new_directory);
1316EXPORT_SYMBOL(csr1212_associate_keyval);
1317EXPORT_SYMBOL(csr1212_attach_keyval_to_directory); 1322EXPORT_SYMBOL(csr1212_attach_keyval_to_directory);
1318EXPORT_SYMBOL(csr1212_new_string_descriptor_leaf);
1319EXPORT_SYMBOL(csr1212_detach_keyval_from_directory); 1323EXPORT_SYMBOL(csr1212_detach_keyval_from_directory);
1320EXPORT_SYMBOL(csr1212_release_keyval); 1324EXPORT_SYMBOL(csr1212_release_keyval);
1321EXPORT_SYMBOL(csr1212_destroy_csr);
1322EXPORT_SYMBOL(csr1212_read); 1325EXPORT_SYMBOL(csr1212_read);
1323EXPORT_SYMBOL(csr1212_generate_csr_image);
1324EXPORT_SYMBOL(csr1212_parse_keyval); 1326EXPORT_SYMBOL(csr1212_parse_keyval);
1325EXPORT_SYMBOL(csr1212_parse_csr);
1326EXPORT_SYMBOL(_csr1212_read_keyval); 1327EXPORT_SYMBOL(_csr1212_read_keyval);
1327EXPORT_SYMBOL(_csr1212_destroy_keyval); 1328EXPORT_SYMBOL(_csr1212_destroy_keyval);
1329#ifdef CONFIG_IEEE1394_EXPORT_FULL_API
1330EXPORT_SYMBOL(csr1212_create_csr);
1331EXPORT_SYMBOL(csr1212_init_local_csr);
1332EXPORT_SYMBOL(csr1212_new_immediate);
1333EXPORT_SYMBOL(csr1212_associate_keyval);
1334EXPORT_SYMBOL(csr1212_new_string_descriptor_leaf);
1335EXPORT_SYMBOL(csr1212_destroy_csr);
1336EXPORT_SYMBOL(csr1212_generate_csr_image);
1337EXPORT_SYMBOL(csr1212_parse_csr);
1338#endif
diff --git a/drivers/ieee1394/iso.c b/drivers/ieee1394/iso.c
index f05759107f7e..615541b8b90f 100644
--- a/drivers/ieee1394/iso.c
+++ b/drivers/ieee1394/iso.c
@@ -62,10 +62,10 @@ static struct hpsb_iso* hpsb_iso_common_init(struct hpsb_host *host, enum hpsb_i
62 if ((dma_mode < HPSB_ISO_DMA_DEFAULT) || (dma_mode > HPSB_ISO_DMA_PACKET_PER_BUFFER)) 62 if ((dma_mode < HPSB_ISO_DMA_DEFAULT) || (dma_mode > HPSB_ISO_DMA_PACKET_PER_BUFFER))
63 dma_mode=HPSB_ISO_DMA_DEFAULT; 63 dma_mode=HPSB_ISO_DMA_DEFAULT;
64 64
65 if ((irq_interval < 0) || (irq_interval > buf_packets / 4))
66 irq_interval = buf_packets / 4;
65 if (irq_interval == 0) /* really interrupt for each packet*/ 67 if (irq_interval == 0) /* really interrupt for each packet*/
66 irq_interval = 1; 68 irq_interval = 1;
67 else if ((irq_interval < 0) || (irq_interval > buf_packets / 4))
68 irq_interval = buf_packets / 4;
69 69
70 if (channel < -1 || channel >= 64) 70 if (channel < -1 || channel >= 64)
71 return NULL; 71 return NULL;
@@ -106,6 +106,7 @@ static struct hpsb_iso* hpsb_iso_common_init(struct hpsb_host *host, enum hpsb_i
106 } 106 }
107 107
108 atomic_set(&iso->overflows, 0); 108 atomic_set(&iso->overflows, 0);
109 iso->bytes_discarded = 0;
109 iso->flags = 0; 110 iso->flags = 0;
110 iso->prebuffer = 0; 111 iso->prebuffer = 0;
111 112
@@ -241,12 +242,12 @@ int hpsb_iso_xmit_start(struct hpsb_iso *iso, int cycle, int prebuffer)
241 iso->xmit_cycle = cycle; 242 iso->xmit_cycle = cycle;
242 243
243 if (prebuffer < 0) 244 if (prebuffer < 0)
244 prebuffer = iso->buf_packets; 245 prebuffer = iso->buf_packets - 1;
245 else if (prebuffer == 0) 246 else if (prebuffer == 0)
246 prebuffer = 1; 247 prebuffer = 1;
247 248
248 if (prebuffer > iso->buf_packets) 249 if (prebuffer >= iso->buf_packets)
249 prebuffer = iso->buf_packets; 250 prebuffer = iso->buf_packets - 1;
250 251
251 iso->prebuffer = prebuffer; 252 iso->prebuffer = prebuffer;
252 253
@@ -395,7 +396,7 @@ void hpsb_iso_packet_sent(struct hpsb_iso *iso, int cycle, int error)
395} 396}
396 397
397void hpsb_iso_packet_received(struct hpsb_iso *iso, u32 offset, u16 len, 398void hpsb_iso_packet_received(struct hpsb_iso *iso, u32 offset, u16 len,
398 u16 cycle, u8 channel, u8 tag, u8 sy) 399 u16 total_len, u16 cycle, u8 channel, u8 tag, u8 sy)
399{ 400{
400 unsigned long flags; 401 unsigned long flags;
401 spin_lock_irqsave(&iso->lock, flags); 402 spin_lock_irqsave(&iso->lock, flags);
@@ -403,10 +404,13 @@ void hpsb_iso_packet_received(struct hpsb_iso *iso, u32 offset, u16 len,
403 if (iso->n_ready_packets == iso->buf_packets) { 404 if (iso->n_ready_packets == iso->buf_packets) {
404 /* overflow! */ 405 /* overflow! */
405 atomic_inc(&iso->overflows); 406 atomic_inc(&iso->overflows);
407 /* Record size of this discarded packet */
408 iso->bytes_discarded += total_len;
406 } else { 409 } else {
407 struct hpsb_iso_packet_info *info = &iso->infos[iso->pkt_dma]; 410 struct hpsb_iso_packet_info *info = &iso->infos[iso->pkt_dma];
408 info->offset = offset; 411 info->offset = offset;
409 info->len = len; 412 info->len = len;
413 info->total_len = total_len;
410 info->cycle = cycle; 414 info->cycle = cycle;
411 info->channel = channel; 415 info->channel = channel;
412 info->tag = tag; 416 info->tag = tag;
@@ -437,6 +441,17 @@ int hpsb_iso_recv_release_packets(struct hpsb_iso *iso, unsigned int n_packets)
437 441
438 iso->first_packet = (iso->first_packet+1) % iso->buf_packets; 442 iso->first_packet = (iso->first_packet+1) % iso->buf_packets;
439 iso->n_ready_packets--; 443 iso->n_ready_packets--;
444
445 /* release memory from packets discarded when queue was full */
446 if (iso->n_ready_packets == 0) { /* Release only after all prior packets handled */
447 if (iso->bytes_discarded != 0) {
448 struct hpsb_iso_packet_info inf;
449 inf.total_len = iso->bytes_discarded;
450 iso->host->driver->isoctl(iso, RECV_RELEASE,
451 (unsigned long) &inf);
452 iso->bytes_discarded = 0;
453 }
454 }
440 } 455 }
441 spin_unlock_irqrestore(&iso->lock, flags); 456 spin_unlock_irqrestore(&iso->lock, flags);
442 return rv; 457 return rv;
diff --git a/drivers/ieee1394/iso.h b/drivers/ieee1394/iso.h
index fb654d9639a7..3efc60b33a88 100644
--- a/drivers/ieee1394/iso.h
+++ b/drivers/ieee1394/iso.h
@@ -47,6 +47,14 @@ struct hpsb_iso_packet_info {
47 /* 2-bit 'tag' and 4-bit 'sy' fields of the isochronous header */ 47 /* 2-bit 'tag' and 4-bit 'sy' fields of the isochronous header */
48 __u8 tag; 48 __u8 tag;
49 __u8 sy; 49 __u8 sy;
50
51 /*
52 * length in bytes of the packet including header/trailer.
53 * MUST be at structure end, since the first part of this structure is also
54 * defined in raw1394.h (i.e. struct raw1394_iso_packet_info), is copied to
55 * userspace and is accessed there through libraw1394.
56 */
57 __u16 total_len;
50}; 58};
51 59
52enum hpsb_iso_type { HPSB_ISO_RECV = 0, HPSB_ISO_XMIT = 1 }; 60enum hpsb_iso_type { HPSB_ISO_RECV = 0, HPSB_ISO_XMIT = 1 };
@@ -111,6 +119,9 @@ struct hpsb_iso {
111 /* how many times the buffer has overflowed or underflowed */ 119 /* how many times the buffer has overflowed or underflowed */
112 atomic_t overflows; 120 atomic_t overflows;
113 121
122 /* Current number of bytes lost in discarded packets */
123 int bytes_discarded;
124
114 /* private flags to track initialization progress */ 125 /* private flags to track initialization progress */
115#define HPSB_ISO_DRIVER_INIT (1<<0) 126#define HPSB_ISO_DRIVER_INIT (1<<0)
116#define HPSB_ISO_DRIVER_STARTED (1<<1) 127#define HPSB_ISO_DRIVER_STARTED (1<<1)
@@ -193,7 +204,7 @@ void hpsb_iso_packet_sent(struct hpsb_iso *iso, int cycle, int error);
193 204
194/* call after a packet has been received (interrupt context OK) */ 205/* call after a packet has been received (interrupt context OK) */
195void hpsb_iso_packet_received(struct hpsb_iso *iso, u32 offset, u16 len, 206void hpsb_iso_packet_received(struct hpsb_iso *iso, u32 offset, u16 len,
196 u16 cycle, u8 channel, u8 tag, u8 sy); 207 u16 total_len, u16 cycle, u8 channel, u8 tag, u8 sy);
197 208
198/* call to wake waiting processes after buffer space has opened up. */ 209/* call to wake waiting processes after buffer space has opened up. */
199void hpsb_iso_wake(struct hpsb_iso *iso); 210void hpsb_iso_wake(struct hpsb_iso *iso);
diff --git a/drivers/ieee1394/nodemgr.c b/drivers/ieee1394/nodemgr.c
index 9a46c3b44bf8..bebcc47ab06c 100644
--- a/drivers/ieee1394/nodemgr.c
+++ b/drivers/ieee1394/nodemgr.c
@@ -30,7 +30,7 @@
30#include "csr.h" 30#include "csr.h"
31#include "nodemgr.h" 31#include "nodemgr.h"
32 32
33static int ignore_drivers = 0; 33static int ignore_drivers;
34module_param(ignore_drivers, int, 0444); 34module_param(ignore_drivers, int, 0444);
35MODULE_PARM_DESC(ignore_drivers, "Disable automatic probing for drivers."); 35MODULE_PARM_DESC(ignore_drivers, "Disable automatic probing for drivers.");
36 36
diff --git a/drivers/ieee1394/ohci1394.c b/drivers/ieee1394/ohci1394.c
index b3d3d22fde64..a485f47bb21e 100644
--- a/drivers/ieee1394/ohci1394.c
+++ b/drivers/ieee1394/ohci1394.c
@@ -162,7 +162,7 @@ printk(level "%s: " fmt "\n" , OHCI1394_DRIVER_NAME , ## args)
162printk(level "%s: fw-host%d: " fmt "\n" , OHCI1394_DRIVER_NAME, ohci->host->id , ## args) 162printk(level "%s: fw-host%d: " fmt "\n" , OHCI1394_DRIVER_NAME, ohci->host->id , ## args)
163 163
164static char version[] __devinitdata = 164static char version[] __devinitdata =
165 "$Rev: 1250 $ Ben Collins <bcollins@debian.org>"; 165 "$Rev: 1299 $ Ben Collins <bcollins@debian.org>";
166 166
167/* Module Parameters */ 167/* Module Parameters */
168static int phys_dma = 1; 168static int phys_dma = 1;
@@ -483,7 +483,9 @@ static void ohci_initialize(struct ti_ohci *ohci)
483 /* Put some defaults to these undefined bus options */ 483 /* Put some defaults to these undefined bus options */
484 buf = reg_read(ohci, OHCI1394_BusOptions); 484 buf = reg_read(ohci, OHCI1394_BusOptions);
485 buf |= 0x60000000; /* Enable CMC and ISC */ 485 buf |= 0x60000000; /* Enable CMC and ISC */
486 if (!hpsb_disable_irm) 486 if (hpsb_disable_irm)
487 buf &= ~0x80000000;
488 else
487 buf |= 0x80000000; /* Enable IRMC */ 489 buf |= 0x80000000; /* Enable IRMC */
488 buf &= ~0x00ff0000; /* XXX: Set cyc_clk_acc to zero for now */ 490 buf &= ~0x00ff0000; /* XXX: Set cyc_clk_acc to zero for now */
489 buf &= ~0x18000000; /* Disable PMC and BMC */ 491 buf &= ~0x18000000; /* Disable PMC and BMC */
@@ -503,8 +505,12 @@ static void ohci_initialize(struct ti_ohci *ohci)
503 reg_write(ohci, OHCI1394_LinkControlSet, 505 reg_write(ohci, OHCI1394_LinkControlSet,
504 OHCI1394_LinkControl_CycleTimerEnable | 506 OHCI1394_LinkControl_CycleTimerEnable |
505 OHCI1394_LinkControl_CycleMaster); 507 OHCI1394_LinkControl_CycleMaster);
506 set_phy_reg_mask(ohci, 4, PHY_04_LCTRL | 508 i = get_phy_reg(ohci, 4) | PHY_04_LCTRL;
507 (hpsb_disable_irm ? 0 : PHY_04_CONTENDER)); 509 if (hpsb_disable_irm)
510 i &= ~PHY_04_CONTENDER;
511 else
512 i |= PHY_04_CONTENDER;
513 set_phy_reg(ohci, 4, i);
508 514
509 /* Set up self-id dma buffer */ 515 /* Set up self-id dma buffer */
510 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->selfid_buf_bus); 516 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->selfid_buf_bus);
@@ -1566,6 +1572,10 @@ static void ohci_iso_recv_release_block(struct ohci_iso_recv *recv, int block)
1566 1572
1567 struct dma_cmd *next = &recv->block[next_i]; 1573 struct dma_cmd *next = &recv->block[next_i];
1568 struct dma_cmd *prev = &recv->block[prev_i]; 1574 struct dma_cmd *prev = &recv->block[prev_i];
1575
1576 /* ignore out-of-range requests */
1577 if ((block < 0) || (block > recv->nblocks))
1578 return;
1569 1579
1570 /* 'next' becomes the new end of the DMA chain, 1580 /* 'next' becomes the new end of the DMA chain,
1571 so disable branch and enable interrupt */ 1581 so disable branch and enable interrupt */
@@ -1593,19 +1603,8 @@ static void ohci_iso_recv_release_block(struct ohci_iso_recv *recv, int block)
1593static void ohci_iso_recv_bufferfill_release(struct ohci_iso_recv *recv, 1603static void ohci_iso_recv_bufferfill_release(struct ohci_iso_recv *recv,
1594 struct hpsb_iso_packet_info *info) 1604 struct hpsb_iso_packet_info *info)
1595{ 1605{
1596 int len;
1597
1598 /* release the memory where the packet was */ 1606 /* release the memory where the packet was */
1599 len = info->len; 1607 recv->released_bytes += info->total_len;
1600
1601 /* add the wasted space for padding to 4 bytes */
1602 if (len % 4)
1603 len += 4 - (len % 4);
1604
1605 /* add 8 bytes for the OHCI DMA data format overhead */
1606 len += 8;
1607
1608 recv->released_bytes += len;
1609 1608
1610 /* have we released enough memory for one block? */ 1609 /* have we released enough memory for one block? */
1611 while (recv->released_bytes > recv->buf_stride) { 1610 while (recv->released_bytes > recv->buf_stride) {
@@ -1637,7 +1636,7 @@ static void ohci_iso_recv_bufferfill_parse(struct hpsb_iso *iso, struct ohci_iso
1637 /* note: packet layout is as shown in section 10.6.1.1 of the OHCI spec */ 1636 /* note: packet layout is as shown in section 10.6.1.1 of the OHCI spec */
1638 1637
1639 unsigned int offset; 1638 unsigned int offset;
1640 unsigned short len, cycle; 1639 unsigned short len, cycle, total_len;
1641 unsigned char channel, tag, sy; 1640 unsigned char channel, tag, sy;
1642 1641
1643 unsigned char *p = iso->data_buf.kvirt; 1642 unsigned char *p = iso->data_buf.kvirt;
@@ -1688,9 +1687,11 @@ static void ohci_iso_recv_bufferfill_parse(struct hpsb_iso *iso, struct ohci_iso
1688 /* advance to xferStatus/timeStamp */ 1687 /* advance to xferStatus/timeStamp */
1689 recv->dma_offset += len; 1688 recv->dma_offset += len;
1690 1689
1690 total_len = len + 8; /* 8 bytes header+trailer in OHCI packet */
1691 /* payload is padded to 4 bytes */ 1691 /* payload is padded to 4 bytes */
1692 if (len % 4) { 1692 if (len % 4) {
1693 recv->dma_offset += 4 - (len%4); 1693 recv->dma_offset += 4 - (len%4);
1694 total_len += 4 - (len%4);
1694 } 1695 }
1695 1696
1696 /* check for wrap-around */ 1697 /* check for wrap-around */
@@ -1724,7 +1725,7 @@ static void ohci_iso_recv_bufferfill_parse(struct hpsb_iso *iso, struct ohci_iso
1724 recv->dma_offset -= recv->buf_stride*recv->nblocks; 1725 recv->dma_offset -= recv->buf_stride*recv->nblocks;
1725 } 1726 }
1726 1727
1727 hpsb_iso_packet_received(iso, offset, len, cycle, channel, tag, sy); 1728 hpsb_iso_packet_received(iso, offset, len, total_len, cycle, channel, tag, sy);
1728 } 1729 }
1729 1730
1730 if (wake) 1731 if (wake)
@@ -1850,7 +1851,8 @@ static void ohci_iso_recv_packetperbuf_task(struct hpsb_iso *iso, struct ohci_is
1850 tag = hdr[5] >> 6; 1851 tag = hdr[5] >> 6;
1851 sy = hdr[4] & 0xF; 1852 sy = hdr[4] & 0xF;
1852 1853
1853 hpsb_iso_packet_received(iso, offset, packet_len, cycle, channel, tag, sy); 1854 hpsb_iso_packet_received(iso, offset, packet_len,
1855 recv->buf_stride, cycle, channel, tag, sy);
1854 } 1856 }
1855 1857
1856 /* reset the DMA descriptor */ 1858 /* reset the DMA descriptor */
diff --git a/drivers/ieee1394/pcilynx.c b/drivers/ieee1394/pcilynx.c
index bdb3a85cafa6..36074e6eeebb 100644
--- a/drivers/ieee1394/pcilynx.c
+++ b/drivers/ieee1394/pcilynx.c
@@ -76,7 +76,7 @@
76 76
77 77
78/* Module Parameters */ 78/* Module Parameters */
79static int skip_eeprom = 0; 79static int skip_eeprom;
80module_param(skip_eeprom, int, 0444); 80module_param(skip_eeprom, int, 0444);
81MODULE_PARM_DESC(skip_eeprom, "Use generic bus info block instead of serial eeprom (default = 0)."); 81MODULE_PARM_DESC(skip_eeprom, "Use generic bus info block instead of serial eeprom (default = 0).");
82 82
@@ -1422,7 +1422,7 @@ static int __devinit add_card(struct pci_dev *dev,
1422 i = get_phy_reg(lynx, 4); 1422 i = get_phy_reg(lynx, 4);
1423 i |= PHY_04_LCTRL; 1423 i |= PHY_04_LCTRL;
1424 if (hpsb_disable_irm) 1424 if (hpsb_disable_irm)
1425 i &= !PHY_04_CONTENDER; 1425 i &= ~PHY_04_CONTENDER;
1426 else 1426 else
1427 i |= PHY_04_CONTENDER; 1427 i |= PHY_04_CONTENDER;
1428 if (i != -1) set_phy_reg(lynx, 4, i); 1428 if (i != -1) set_phy_reg(lynx, 4, i);
diff --git a/drivers/ieee1394/raw1394.c b/drivers/ieee1394/raw1394.c
index 7419af450bd1..b4fa14793fe5 100644
--- a/drivers/ieee1394/raw1394.c
+++ b/drivers/ieee1394/raw1394.c
@@ -98,7 +98,7 @@ static struct hpsb_address_ops arm_ops = {
98 98
99static void queue_complete_cb(struct pending_request *req); 99static void queue_complete_cb(struct pending_request *req);
100 100
101static struct pending_request *__alloc_pending_request(int flags) 101static struct pending_request *__alloc_pending_request(unsigned int __nocast flags)
102{ 102{
103 struct pending_request *req; 103 struct pending_request *req;
104 104
@@ -2506,9 +2506,12 @@ static int raw1394_iso_send_packets(struct file_info *fi, void __user * uaddr)
2506 if (copy_from_user(&upackets, uaddr, sizeof(upackets))) 2506 if (copy_from_user(&upackets, uaddr, sizeof(upackets)))
2507 return -EFAULT; 2507 return -EFAULT;
2508 2508
2509 if (upackets.n_packets > hpsb_iso_n_ready(fi->iso_handle)) 2509 if (upackets.n_packets >= fi->iso_handle->buf_packets)
2510 return -EINVAL; 2510 return -EINVAL;
2511 2511
2512 if (upackets.n_packets >= hpsb_iso_n_ready(fi->iso_handle))
2513 return -EAGAIN;
2514
2512 /* ensure user-supplied buffer is accessible and big enough */ 2515 /* ensure user-supplied buffer is accessible and big enough */
2513 if (!access_ok(VERIFY_READ, upackets.infos, 2516 if (!access_ok(VERIFY_READ, upackets.infos,
2514 upackets.n_packets * 2517 upackets.n_packets *
diff --git a/drivers/ieee1394/sbp2.c b/drivers/ieee1394/sbp2.c
index 32368f3428ec..fe3e1703fa61 100644
--- a/drivers/ieee1394/sbp2.c
+++ b/drivers/ieee1394/sbp2.c
@@ -81,7 +81,7 @@
81#include "sbp2.h" 81#include "sbp2.h"
82 82
83static char version[] __devinitdata = 83static char version[] __devinitdata =
84 "$Rev: 1219 $ Ben Collins <bcollins@debian.org>"; 84 "$Rev: 1306 $ Ben Collins <bcollins@debian.org>";
85 85
86/* 86/*
87 * Module load parameter definitions 87 * Module load parameter definitions
@@ -104,7 +104,7 @@ MODULE_PARM_DESC(max_speed, "Force max speed (3 = 800mb, 2 = 400mb default, 1 =
104 * down to us at a time (debugging). This might be necessary for very 104 * down to us at a time (debugging). This might be necessary for very
105 * badly behaved sbp2 devices. 105 * badly behaved sbp2 devices.
106 */ 106 */
107static int serialize_io = 0; 107static int serialize_io;
108module_param(serialize_io, int, 0444); 108module_param(serialize_io, int, 0444);
109MODULE_PARM_DESC(serialize_io, "Serialize all I/O coming down from the scsi drivers (default = 0)"); 109MODULE_PARM_DESC(serialize_io, "Serialize all I/O coming down from the scsi drivers (default = 0)");
110 110
@@ -145,7 +145,7 @@ MODULE_PARM_DESC(exclusive_login, "Exclusive login to sbp2 device (default = 1)"
145 * please submit the logged sbp2_firmware_revision value of this device to 145 * please submit the logged sbp2_firmware_revision value of this device to
146 * the linux1394-devel mailing list. 146 * the linux1394-devel mailing list.
147 */ 147 */
148static int force_inquiry_hack = 0; 148static int force_inquiry_hack;
149module_param(force_inquiry_hack, int, 0444); 149module_param(force_inquiry_hack, int, 0444);
150MODULE_PARM_DESC(force_inquiry_hack, "Force SCSI inquiry hack (default = 0)"); 150MODULE_PARM_DESC(force_inquiry_hack, "Force SCSI inquiry hack (default = 0)");
151 151
@@ -2112,6 +2112,102 @@ static int sbp2_send_command(struct scsi_id_instance_data *scsi_id,
2112 */ 2112 */
2113static void sbp2_check_sbp2_command(struct scsi_id_instance_data *scsi_id, unchar *cmd) 2113static void sbp2_check_sbp2_command(struct scsi_id_instance_data *scsi_id, unchar *cmd)
2114{ 2114{
2115 unchar new_cmd[16];
2116 u8 device_type = SBP2_DEVICE_TYPE (scsi_id->sbp2_device_type_and_lun);
2117
2118 SBP2_DEBUG("sbp2_check_sbp2_command");
2119
2120 switch (*cmd) {
2121
2122 case READ_6:
2123
2124 if (sbp2_command_conversion_device_type(device_type)) {
2125
2126 SBP2_DEBUG("Convert READ_6 to READ_10");
2127
2128 /*
2129 * Need to turn read_6 into read_10
2130 */
2131 new_cmd[0] = 0x28;
2132 new_cmd[1] = (cmd[1] & 0xe0);
2133 new_cmd[2] = 0x0;
2134 new_cmd[3] = (cmd[1] & 0x1f);
2135 new_cmd[4] = cmd[2];
2136 new_cmd[5] = cmd[3];
2137 new_cmd[6] = 0x0;
2138 new_cmd[7] = 0x0;
2139 new_cmd[8] = cmd[4];
2140 new_cmd[9] = cmd[5];
2141
2142 memcpy(cmd, new_cmd, 10);
2143
2144 }
2145
2146 break;
2147
2148 case WRITE_6:
2149
2150 if (sbp2_command_conversion_device_type(device_type)) {
2151
2152 SBP2_DEBUG("Convert WRITE_6 to WRITE_10");
2153
2154 /*
2155 * Need to turn write_6 into write_10
2156 */
2157 new_cmd[0] = 0x2a;
2158 new_cmd[1] = (cmd[1] & 0xe0);
2159 new_cmd[2] = 0x0;
2160 new_cmd[3] = (cmd[1] & 0x1f);
2161 new_cmd[4] = cmd[2];
2162 new_cmd[5] = cmd[3];
2163 new_cmd[6] = 0x0;
2164 new_cmd[7] = 0x0;
2165 new_cmd[8] = cmd[4];
2166 new_cmd[9] = cmd[5];
2167
2168 memcpy(cmd, new_cmd, 10);
2169
2170 }
2171
2172 break;
2173
2174 case MODE_SENSE:
2175
2176 if (sbp2_command_conversion_device_type(device_type)) {
2177
2178 SBP2_DEBUG("Convert MODE_SENSE_6 to MODE_SENSE_10");
2179
2180 /*
2181 * Need to turn mode_sense_6 into mode_sense_10
2182 */
2183 new_cmd[0] = 0x5a;
2184 new_cmd[1] = cmd[1];
2185 new_cmd[2] = cmd[2];
2186 new_cmd[3] = 0x0;
2187 new_cmd[4] = 0x0;
2188 new_cmd[5] = 0x0;
2189 new_cmd[6] = 0x0;
2190 new_cmd[7] = 0x0;
2191 new_cmd[8] = cmd[4];
2192 new_cmd[9] = cmd[5];
2193
2194 memcpy(cmd, new_cmd, 10);
2195
2196 }
2197
2198 break;
2199
2200 case MODE_SELECT:
2201
2202 /*
2203 * TODO. Probably need to change mode select to 10 byte version
2204 */
2205
2206 default:
2207 break;
2208 }
2209
2210 return;
2115} 2211}
2116 2212
2117/* 2213/*
@@ -2152,6 +2248,7 @@ static void sbp2_check_sbp2_response(struct scsi_id_instance_data *scsi_id,
2152 struct scsi_cmnd *SCpnt) 2248 struct scsi_cmnd *SCpnt)
2153{ 2249{
2154 u8 *scsi_buf = SCpnt->request_buffer; 2250 u8 *scsi_buf = SCpnt->request_buffer;
2251 u8 device_type = SBP2_DEVICE_TYPE (scsi_id->sbp2_device_type_and_lun);
2155 2252
2156 SBP2_DEBUG("sbp2_check_sbp2_response"); 2253 SBP2_DEBUG("sbp2_check_sbp2_response");
2157 2254
@@ -2176,6 +2273,14 @@ static void sbp2_check_sbp2_response(struct scsi_id_instance_data *scsi_id,
2176 } 2273 }
2177 2274
2178 /* 2275 /*
2276 * Check for Simple Direct Access Device and change it to TYPE_DISK
2277 */
2278 if ((scsi_buf[0] & 0x1f) == TYPE_RBC) {
2279 SBP2_DEBUG("Changing TYPE_RBC to TYPE_DISK");
2280 scsi_buf[0] &= 0xe0;
2281 }
2282
2283 /*
2179 * Fix ansi revision and response data format 2284 * Fix ansi revision and response data format
2180 */ 2285 */
2181 scsi_buf[2] |= 2; 2286 scsi_buf[2] |= 2;
@@ -2183,6 +2288,27 @@ static void sbp2_check_sbp2_response(struct scsi_id_instance_data *scsi_id,
2183 2288
2184 break; 2289 break;
2185 2290
2291 case MODE_SENSE:
2292
2293 if (sbp2_command_conversion_device_type(device_type)) {
2294
2295 SBP2_DEBUG("Modify mode sense response (10 byte version)");
2296
2297 scsi_buf[0] = scsi_buf[1]; /* Mode data length */
2298 scsi_buf[1] = scsi_buf[2]; /* Medium type */
2299 scsi_buf[2] = scsi_buf[3]; /* Device specific parameter */
2300 scsi_buf[3] = scsi_buf[7]; /* Block descriptor length */
2301 memcpy(scsi_buf + 4, scsi_buf + 8, scsi_buf[0]);
2302 }
2303
2304 break;
2305
2306 case MODE_SELECT:
2307
2308 /*
2309 * TODO. Probably need to change mode select to 10 byte version
2310 */
2311
2186 default: 2312 default:
2187 break; 2313 break;
2188 } 2314 }
@@ -2559,8 +2685,7 @@ static void sbp2scsi_complete_command(struct scsi_id_instance_data *scsi_id,
2559static int sbp2scsi_slave_configure (struct scsi_device *sdev) 2685static int sbp2scsi_slave_configure (struct scsi_device *sdev)
2560{ 2686{
2561 blk_queue_dma_alignment(sdev->request_queue, (512 - 1)); 2687 blk_queue_dma_alignment(sdev->request_queue, (512 - 1));
2562 sdev->use_10_for_rw = 1; 2688
2563 sdev->use_10_for_ms = 1;
2564 return 0; 2689 return 0;
2565} 2690}
2566 2691
diff --git a/drivers/isdn/hisax/isdnl1.c b/drivers/isdn/hisax/isdnl1.c
index ac899503a74f..bab356886483 100644
--- a/drivers/isdn/hisax/isdnl1.c
+++ b/drivers/isdn/hisax/isdnl1.c
@@ -279,7 +279,8 @@ BChannel_proc_xmt(struct BCState *bcs)
279 if (test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags)) 279 if (test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags))
280 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL); 280 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
281 if (!test_bit(BC_FLG_ACTIV, &bcs->Flag)) { 281 if (!test_bit(BC_FLG_ACTIV, &bcs->Flag)) {
282 if (!test_bit(BC_FLG_BUSY, &bcs->Flag) && (!skb_queue_len(&bcs->squeue))) { 282 if (!test_bit(BC_FLG_BUSY, &bcs->Flag) &&
283 skb_queue_empty(&bcs->squeue)) {
283 st->l2.l2l1(st, PH_DEACTIVATE | CONFIRM, NULL); 284 st->l2.l2l1(st, PH_DEACTIVATE | CONFIRM, NULL);
284 } 285 }
285 } 286 }
diff --git a/drivers/isdn/hisax/isdnl2.c b/drivers/isdn/hisax/isdnl2.c
index 9022583fd6a0..1615c1a76ab8 100644
--- a/drivers/isdn/hisax/isdnl2.c
+++ b/drivers/isdn/hisax/isdnl2.c
@@ -108,7 +108,8 @@ static int l2addrsize(struct Layer2 *l2);
108static void 108static void
109set_peer_busy(struct Layer2 *l2) { 109set_peer_busy(struct Layer2 *l2) {
110 test_and_set_bit(FLG_PEER_BUSY, &l2->flag); 110 test_and_set_bit(FLG_PEER_BUSY, &l2->flag);
111 if (skb_queue_len(&l2->i_queue) || skb_queue_len(&l2->ui_queue)) 111 if (!skb_queue_empty(&l2->i_queue) ||
112 !skb_queue_empty(&l2->ui_queue))
112 test_and_set_bit(FLG_L2BLOCK, &l2->flag); 113 test_and_set_bit(FLG_L2BLOCK, &l2->flag);
113} 114}
114 115
@@ -754,7 +755,7 @@ l2_restart_multi(struct FsmInst *fi, int event, void *arg)
754 st->l2.l2l3(st, DL_ESTABLISH | INDICATION, NULL); 755 st->l2.l2l3(st, DL_ESTABLISH | INDICATION, NULL);
755 756
756 if ((ST_L2_7==state) || (ST_L2_8 == state)) 757 if ((ST_L2_7==state) || (ST_L2_8 == state))
757 if (skb_queue_len(&st->l2.i_queue) && cansend(st)) 758 if (!skb_queue_empty(&st->l2.i_queue) && cansend(st))
758 st->l2.l2l1(st, PH_PULL | REQUEST, NULL); 759 st->l2.l2l1(st, PH_PULL | REQUEST, NULL);
759} 760}
760 761
@@ -810,7 +811,7 @@ l2_connected(struct FsmInst *fi, int event, void *arg)
810 if (pr != -1) 811 if (pr != -1)
811 st->l2.l2l3(st, pr, NULL); 812 st->l2.l2l3(st, pr, NULL);
812 813
813 if (skb_queue_len(&st->l2.i_queue) && cansend(st)) 814 if (!skb_queue_empty(&st->l2.i_queue) && cansend(st))
814 st->l2.l2l1(st, PH_PULL | REQUEST, NULL); 815 st->l2.l2l1(st, PH_PULL | REQUEST, NULL);
815} 816}
816 817
@@ -1014,7 +1015,7 @@ l2_st7_got_super(struct FsmInst *fi, int event, void *arg)
1014 if(typ != RR) FsmDelTimer(&st->l2.t203, 9); 1015 if(typ != RR) FsmDelTimer(&st->l2.t203, 9);
1015 restart_t200(st, 12); 1016 restart_t200(st, 12);
1016 } 1017 }
1017 if (skb_queue_len(&st->l2.i_queue) && (typ == RR)) 1018 if (!skb_queue_empty(&st->l2.i_queue) && (typ == RR))
1018 st->l2.l2l1(st, PH_PULL | REQUEST, NULL); 1019 st->l2.l2l1(st, PH_PULL | REQUEST, NULL);
1019 } else 1020 } else
1020 nrerrorrecovery(fi); 1021 nrerrorrecovery(fi);
@@ -1120,7 +1121,7 @@ l2_got_iframe(struct FsmInst *fi, int event, void *arg)
1120 return; 1121 return;
1121 } 1122 }
1122 1123
1123 if (skb_queue_len(&st->l2.i_queue) && (fi->state == ST_L2_7)) 1124 if (!skb_queue_empty(&st->l2.i_queue) && (fi->state == ST_L2_7))
1124 st->l2.l2l1(st, PH_PULL | REQUEST, NULL); 1125 st->l2.l2l1(st, PH_PULL | REQUEST, NULL);
1125 if (test_and_clear_bit(FLG_ACK_PEND, &st->l2.flag)) 1126 if (test_and_clear_bit(FLG_ACK_PEND, &st->l2.flag))
1126 enquiry_cr(st, RR, RSP, 0); 1127 enquiry_cr(st, RR, RSP, 0);
@@ -1138,7 +1139,7 @@ l2_got_tei(struct FsmInst *fi, int event, void *arg)
1138 test_and_set_bit(FLG_L3_INIT, &st->l2.flag); 1139 test_and_set_bit(FLG_L3_INIT, &st->l2.flag);
1139 } else 1140 } else
1140 FsmChangeState(fi, ST_L2_4); 1141 FsmChangeState(fi, ST_L2_4);
1141 if (skb_queue_len(&st->l2.ui_queue)) 1142 if (!skb_queue_empty(&st->l2.ui_queue))
1142 tx_ui(st); 1143 tx_ui(st);
1143} 1144}
1144 1145
@@ -1301,7 +1302,7 @@ l2_pull_iqueue(struct FsmInst *fi, int event, void *arg)
1301 FsmDelTimer(&st->l2.t203, 13); 1302 FsmDelTimer(&st->l2.t203, 13);
1302 FsmAddTimer(&st->l2.t200, st->l2.T200, EV_L2_T200, NULL, 11); 1303 FsmAddTimer(&st->l2.t200, st->l2.T200, EV_L2_T200, NULL, 11);
1303 } 1304 }
1304 if (skb_queue_len(&l2->i_queue) && cansend(st)) 1305 if (!skb_queue_empty(&l2->i_queue) && cansend(st))
1305 st->l2.l2l1(st, PH_PULL | REQUEST, NULL); 1306 st->l2.l2l1(st, PH_PULL | REQUEST, NULL);
1306} 1307}
1307 1308
@@ -1347,7 +1348,7 @@ l2_st8_got_super(struct FsmInst *fi, int event, void *arg)
1347 } 1348 }
1348 invoke_retransmission(st, nr); 1349 invoke_retransmission(st, nr);
1349 FsmChangeState(fi, ST_L2_7); 1350 FsmChangeState(fi, ST_L2_7);
1350 if (skb_queue_len(&l2->i_queue) && cansend(st)) 1351 if (!skb_queue_empty(&l2->i_queue) && cansend(st))
1351 st->l2.l2l1(st, PH_PULL | REQUEST, NULL); 1352 st->l2.l2l1(st, PH_PULL | REQUEST, NULL);
1352 } else 1353 } else
1353 nrerrorrecovery(fi); 1354 nrerrorrecovery(fi);
diff --git a/drivers/isdn/hisax/isdnl3.c b/drivers/isdn/hisax/isdnl3.c
index abcc9530eb34..c9917cd2132b 100644
--- a/drivers/isdn/hisax/isdnl3.c
+++ b/drivers/isdn/hisax/isdnl3.c
@@ -302,7 +302,7 @@ release_l3_process(struct l3_process *p)
302 !test_bit(FLG_PTP, &p->st->l2.flag)) { 302 !test_bit(FLG_PTP, &p->st->l2.flag)) {
303 if (p->debug) 303 if (p->debug)
304 l3_debug(p->st, "release_l3_process: last process"); 304 l3_debug(p->st, "release_l3_process: last process");
305 if (!skb_queue_len(&p->st->l3.squeue)) { 305 if (skb_queue_empty(&p->st->l3.squeue)) {
306 if (p->debug) 306 if (p->debug)
307 l3_debug(p->st, "release_l3_process: release link"); 307 l3_debug(p->st, "release_l3_process: release link");
308 if (p->st->protocol != ISDN_PTYPE_NI1) 308 if (p->st->protocol != ISDN_PTYPE_NI1)
diff --git a/drivers/isdn/i4l/isdn_tty.c b/drivers/isdn/i4l/isdn_tty.c
index ad5aa38fb5a6..b37ef1f06b3d 100644
--- a/drivers/isdn/i4l/isdn_tty.c
+++ b/drivers/isdn/i4l/isdn_tty.c
@@ -1223,7 +1223,7 @@ isdn_tty_write(struct tty_struct *tty, const u_char * buf, int count)
1223 total += c; 1223 total += c;
1224 } 1224 }
1225 atomic_dec(&info->xmit_lock); 1225 atomic_dec(&info->xmit_lock);
1226 if ((info->xmit_count) || (skb_queue_len(&info->xmit_queue))) { 1226 if ((info->xmit_count) || !skb_queue_empty(&info->xmit_queue)) {
1227 if (m->mdmreg[REG_DXMT] & BIT_DXMT) { 1227 if (m->mdmreg[REG_DXMT] & BIT_DXMT) {
1228 isdn_tty_senddown(info); 1228 isdn_tty_senddown(info);
1229 isdn_tty_tint(info); 1229 isdn_tty_tint(info);
@@ -1284,7 +1284,7 @@ isdn_tty_flush_chars(struct tty_struct *tty)
1284 1284
1285 if (isdn_tty_paranoia_check(info, tty->name, "isdn_tty_flush_chars")) 1285 if (isdn_tty_paranoia_check(info, tty->name, "isdn_tty_flush_chars"))
1286 return; 1286 return;
1287 if ((info->xmit_count) || (skb_queue_len(&info->xmit_queue))) 1287 if ((info->xmit_count) || !skb_queue_empty(&info->xmit_queue))
1288 isdn_timer_ctrl(ISDN_TIMER_MODEMXMIT, 1); 1288 isdn_timer_ctrl(ISDN_TIMER_MODEMXMIT, 1);
1289} 1289}
1290 1290
diff --git a/drivers/isdn/icn/icn.c b/drivers/isdn/icn/icn.c
index 9fc0c1e03732..e0d1b01cc74c 100644
--- a/drivers/isdn/icn/icn.c
+++ b/drivers/isdn/icn/icn.c
@@ -304,12 +304,12 @@ icn_pollbchan_send(int channel, icn_card * card)
304 isdn_ctrl cmd; 304 isdn_ctrl cmd;
305 305
306 if (!(card->sndcount[channel] || card->xskb[channel] || 306 if (!(card->sndcount[channel] || card->xskb[channel] ||
307 skb_queue_len(&card->spqueue[channel]))) 307 !skb_queue_empty(&card->spqueue[channel])))
308 return; 308 return;
309 if (icn_trymaplock_channel(card, mch)) { 309 if (icn_trymaplock_channel(card, mch)) {
310 while (sbfree && 310 while (sbfree &&
311 (card->sndcount[channel] || 311 (card->sndcount[channel] ||
312 skb_queue_len(&card->spqueue[channel]) || 312 !skb_queue_empty(&card->spqueue[channel]) ||
313 card->xskb[channel])) { 313 card->xskb[channel])) {
314 spin_lock_irqsave(&card->lock, flags); 314 spin_lock_irqsave(&card->lock, flags);
315 if (card->xmit_lock[channel]) { 315 if (card->xmit_lock[channel]) {
diff --git a/drivers/net/hamradio/scc.c b/drivers/net/hamradio/scc.c
index ece1b1a13186..c27e417f32bf 100644
--- a/drivers/net/hamradio/scc.c
+++ b/drivers/net/hamradio/scc.c
@@ -304,7 +304,7 @@ static inline void scc_discard_buffers(struct scc_channel *scc)
304 scc->tx_buff = NULL; 304 scc->tx_buff = NULL;
305 } 305 }
306 306
307 while (skb_queue_len(&scc->tx_queue)) 307 while (!skb_queue_empty(&scc->tx_queue))
308 dev_kfree_skb(skb_dequeue(&scc->tx_queue)); 308 dev_kfree_skb(skb_dequeue(&scc->tx_queue));
309 309
310 spin_unlock_irqrestore(&scc->lock, flags); 310 spin_unlock_irqrestore(&scc->lock, flags);
@@ -1126,8 +1126,7 @@ static void t_dwait(unsigned long channel)
1126 1126
1127 if (scc->stat.tx_state == TXS_WAIT) /* maxkeyup or idle timeout */ 1127 if (scc->stat.tx_state == TXS_WAIT) /* maxkeyup or idle timeout */
1128 { 1128 {
1129 if (skb_queue_len(&scc->tx_queue) == 0) /* nothing to send */ 1129 if (skb_queue_empty(&scc->tx_queue)) { /* nothing to send */
1130 {
1131 scc->stat.tx_state = TXS_IDLE; 1130 scc->stat.tx_state = TXS_IDLE;
1132 netif_wake_queue(scc->dev); /* t_maxkeyup locked it. */ 1131 netif_wake_queue(scc->dev); /* t_maxkeyup locked it. */
1133 return; 1132 return;
diff --git a/drivers/net/ppp_async.c b/drivers/net/ppp_async.c
index 5e48b9ab3045..59e8183c639e 100644
--- a/drivers/net/ppp_async.c
+++ b/drivers/net/ppp_async.c
@@ -364,7 +364,7 @@ ppp_asynctty_receive(struct tty_struct *tty, const unsigned char *buf,
364 spin_lock_irqsave(&ap->recv_lock, flags); 364 spin_lock_irqsave(&ap->recv_lock, flags);
365 ppp_async_input(ap, buf, cflags, count); 365 ppp_async_input(ap, buf, cflags, count);
366 spin_unlock_irqrestore(&ap->recv_lock, flags); 366 spin_unlock_irqrestore(&ap->recv_lock, flags);
367 if (skb_queue_len(&ap->rqueue)) 367 if (!skb_queue_empty(&ap->rqueue))
368 tasklet_schedule(&ap->tsk); 368 tasklet_schedule(&ap->tsk);
369 ap_put(ap); 369 ap_put(ap);
370 if (test_and_clear_bit(TTY_THROTTLED, &tty->flags) 370 if (test_and_clear_bit(TTY_THROTTLED, &tty->flags)
diff --git a/drivers/net/ppp_generic.c b/drivers/net/ppp_generic.c
index ab726ab43798..a32668e88e09 100644
--- a/drivers/net/ppp_generic.c
+++ b/drivers/net/ppp_generic.c
@@ -1237,8 +1237,8 @@ static int ppp_mp_explode(struct ppp *ppp, struct sk_buff *skb)
1237 pch = list_entry(list, struct channel, clist); 1237 pch = list_entry(list, struct channel, clist);
1238 navail += pch->avail = (pch->chan != NULL); 1238 navail += pch->avail = (pch->chan != NULL);
1239 if (pch->avail) { 1239 if (pch->avail) {
1240 if (skb_queue_len(&pch->file.xq) == 0 1240 if (skb_queue_empty(&pch->file.xq) ||
1241 || !pch->had_frag) { 1241 !pch->had_frag) {
1242 pch->avail = 2; 1242 pch->avail = 2;
1243 ++nfree; 1243 ++nfree;
1244 } 1244 }
@@ -1374,8 +1374,8 @@ static int ppp_mp_explode(struct ppp *ppp, struct sk_buff *skb)
1374 1374
1375 /* try to send it down the channel */ 1375 /* try to send it down the channel */
1376 chan = pch->chan; 1376 chan = pch->chan;
1377 if (skb_queue_len(&pch->file.xq) 1377 if (!skb_queue_empty(&pch->file.xq) ||
1378 || !chan->ops->start_xmit(chan, frag)) 1378 !chan->ops->start_xmit(chan, frag))
1379 skb_queue_tail(&pch->file.xq, frag); 1379 skb_queue_tail(&pch->file.xq, frag);
1380 pch->had_frag = 1; 1380 pch->had_frag = 1;
1381 p += flen; 1381 p += flen;
@@ -1412,7 +1412,7 @@ ppp_channel_push(struct channel *pch)
1412 1412
1413 spin_lock_bh(&pch->downl); 1413 spin_lock_bh(&pch->downl);
1414 if (pch->chan != 0) { 1414 if (pch->chan != 0) {
1415 while (skb_queue_len(&pch->file.xq) > 0) { 1415 while (!skb_queue_empty(&pch->file.xq)) {
1416 skb = skb_dequeue(&pch->file.xq); 1416 skb = skb_dequeue(&pch->file.xq);
1417 if (!pch->chan->ops->start_xmit(pch->chan, skb)) { 1417 if (!pch->chan->ops->start_xmit(pch->chan, skb)) {
1418 /* put the packet back and try again later */ 1418 /* put the packet back and try again later */
@@ -1426,7 +1426,7 @@ ppp_channel_push(struct channel *pch)
1426 } 1426 }
1427 spin_unlock_bh(&pch->downl); 1427 spin_unlock_bh(&pch->downl);
1428 /* see if there is anything from the attached unit to be sent */ 1428 /* see if there is anything from the attached unit to be sent */
1429 if (skb_queue_len(&pch->file.xq) == 0) { 1429 if (skb_queue_empty(&pch->file.xq)) {
1430 read_lock_bh(&pch->upl); 1430 read_lock_bh(&pch->upl);
1431 ppp = pch->ppp; 1431 ppp = pch->ppp;
1432 if (ppp != 0) 1432 if (ppp != 0)
diff --git a/drivers/net/ppp_synctty.c b/drivers/net/ppp_synctty.c
index fd9f50180355..4d51c0c8023d 100644
--- a/drivers/net/ppp_synctty.c
+++ b/drivers/net/ppp_synctty.c
@@ -406,7 +406,7 @@ ppp_sync_receive(struct tty_struct *tty, const unsigned char *buf,
406 spin_lock_irqsave(&ap->recv_lock, flags); 406 spin_lock_irqsave(&ap->recv_lock, flags);
407 ppp_sync_input(ap, buf, cflags, count); 407 ppp_sync_input(ap, buf, cflags, count);
408 spin_unlock_irqrestore(&ap->recv_lock, flags); 408 spin_unlock_irqrestore(&ap->recv_lock, flags);
409 if (skb_queue_len(&ap->rqueue)) 409 if (!skb_queue_empty(&ap->rqueue))
410 tasklet_schedule(&ap->tsk); 410 tasklet_schedule(&ap->tsk);
411 sp_put(ap); 411 sp_put(ap);
412 if (test_and_clear_bit(TTY_THROTTLED, &tty->flags) 412 if (test_and_clear_bit(TTY_THROTTLED, &tty->flags)
diff --git a/drivers/net/tun.c b/drivers/net/tun.c
index 7bfee366297b..effab0b9adca 100644
--- a/drivers/net/tun.c
+++ b/drivers/net/tun.c
@@ -215,7 +215,7 @@ static unsigned int tun_chr_poll(struct file *file, poll_table * wait)
215 215
216 poll_wait(file, &tun->read_wait, wait); 216 poll_wait(file, &tun->read_wait, wait);
217 217
218 if (skb_queue_len(&tun->readq)) 218 if (!skb_queue_empty(&tun->readq))
219 mask |= POLLIN | POLLRDNORM; 219 mask |= POLLIN | POLLRDNORM;
220 220
221 return mask; 221 return mask;
diff --git a/drivers/net/wireless/airo.c b/drivers/net/wireless/airo.c
index c12648d8192b..47f3c5d0203d 100644
--- a/drivers/net/wireless/airo.c
+++ b/drivers/net/wireless/airo.c
@@ -2374,7 +2374,7 @@ void stop_airo_card( struct net_device *dev, int freeres )
2374 /* 2374 /*
2375 * Clean out tx queue 2375 * Clean out tx queue
2376 */ 2376 */
2377 if (test_bit(FLAG_MPI, &ai->flags) && skb_queue_len (&ai->txq) > 0) { 2377 if (test_bit(FLAG_MPI, &ai->flags) && !skb_queue_empty(&ai->txq)) {
2378 struct sk_buff *skb = NULL; 2378 struct sk_buff *skb = NULL;
2379 for (;(skb = skb_dequeue(&ai->txq));) 2379 for (;(skb = skb_dequeue(&ai->txq));)
2380 dev_kfree_skb(skb); 2380 dev_kfree_skb(skb);
@@ -3287,7 +3287,7 @@ exitrx:
3287 if (status & EV_TXEXC) 3287 if (status & EV_TXEXC)
3288 get_tx_error(apriv, -1); 3288 get_tx_error(apriv, -1);
3289 spin_lock_irqsave(&apriv->aux_lock, flags); 3289 spin_lock_irqsave(&apriv->aux_lock, flags);
3290 if (skb_queue_len (&apriv->txq)) { 3290 if (!skb_queue_empty(&apriv->txq)) {
3291 spin_unlock_irqrestore(&apriv->aux_lock,flags); 3291 spin_unlock_irqrestore(&apriv->aux_lock,flags);
3292 mpi_send_packet (dev); 3292 mpi_send_packet (dev);
3293 } else { 3293 } else {
diff --git a/drivers/s390/net/claw.c b/drivers/s390/net/claw.c
index 60440dbe3a27..24c0af49c25c 100644
--- a/drivers/s390/net/claw.c
+++ b/drivers/s390/net/claw.c
@@ -428,7 +428,7 @@ claw_pack_skb(struct claw_privbk *privptr)
428 new_skb = NULL; /* assume no dice */ 428 new_skb = NULL; /* assume no dice */
429 pkt_cnt = 0; 429 pkt_cnt = 0;
430 CLAW_DBF_TEXT(4,trace,"PackSKBe"); 430 CLAW_DBF_TEXT(4,trace,"PackSKBe");
431 if (skb_queue_len(&p_ch->collect_queue) > 0) { 431 if (!skb_queue_empty(&p_ch->collect_queue)) {
432 /* some data */ 432 /* some data */
433 held_skb = skb_dequeue(&p_ch->collect_queue); 433 held_skb = skb_dequeue(&p_ch->collect_queue);
434 if (p_env->packing != DO_PACKED) 434 if (p_env->packing != DO_PACKED)
@@ -1254,7 +1254,7 @@ claw_write_next ( struct chbk * p_ch )
1254 privptr = (struct claw_privbk *) dev->priv; 1254 privptr = (struct claw_privbk *) dev->priv;
1255 claw_free_wrt_buf( dev ); 1255 claw_free_wrt_buf( dev );
1256 if ((privptr->write_free_count > 0) && 1256 if ((privptr->write_free_count > 0) &&
1257 (skb_queue_len(&p_ch->collect_queue) > 0)) { 1257 !skb_queue_empty(&p_ch->collect_queue)) {
1258 pk_skb = claw_pack_skb(privptr); 1258 pk_skb = claw_pack_skb(privptr);
1259 while (pk_skb != NULL) { 1259 while (pk_skb != NULL) {
1260 rc = claw_hw_tx( pk_skb, dev,1); 1260 rc = claw_hw_tx( pk_skb, dev,1);
diff --git a/drivers/s390/net/ctctty.c b/drivers/s390/net/ctctty.c
index 3080393e823d..968f2c113efe 100644
--- a/drivers/s390/net/ctctty.c
+++ b/drivers/s390/net/ctctty.c
@@ -156,7 +156,7 @@ ctc_tty_readmodem(ctc_tty_info *info)
156 skb_queue_head(&info->rx_queue, skb); 156 skb_queue_head(&info->rx_queue, skb);
157 else { 157 else {
158 kfree_skb(skb); 158 kfree_skb(skb);
159 ret = skb_queue_len(&info->rx_queue); 159 ret = !skb_queue_empty(&info->rx_queue);
160 } 160 }
161 } 161 }
162 } 162 }
@@ -530,7 +530,7 @@ ctc_tty_write(struct tty_struct *tty, const u_char * buf, int count)
530 total += c; 530 total += c;
531 count -= c; 531 count -= c;
532 } 532 }
533 if (skb_queue_len(&info->tx_queue)) { 533 if (!skb_queue_empty(&info->tx_queue)) {
534 info->lsr &= ~UART_LSR_TEMT; 534 info->lsr &= ~UART_LSR_TEMT;
535 tasklet_schedule(&info->tasklet); 535 tasklet_schedule(&info->tasklet);
536 } 536 }
@@ -594,7 +594,7 @@ ctc_tty_flush_chars(struct tty_struct *tty)
594 return; 594 return;
595 if (ctc_tty_paranoia_check(info, tty->name, "ctc_tty_flush_chars")) 595 if (ctc_tty_paranoia_check(info, tty->name, "ctc_tty_flush_chars"))
596 return; 596 return;
597 if (tty->stopped || tty->hw_stopped || (!skb_queue_len(&info->tx_queue))) 597 if (tty->stopped || tty->hw_stopped || skb_queue_empty(&info->tx_queue))
598 return; 598 return;
599 tasklet_schedule(&info->tasklet); 599 tasklet_schedule(&info->tasklet);
600} 600}
diff --git a/drivers/usb/net/usbnet.c b/drivers/usb/net/usbnet.c
index 8a945f4f3693..576f3b852fce 100644
--- a/drivers/usb/net/usbnet.c
+++ b/drivers/usb/net/usbnet.c
@@ -3227,9 +3227,9 @@ static int usbnet_stop (struct net_device *net)
3227 temp = unlink_urbs (dev, &dev->txq) + unlink_urbs (dev, &dev->rxq); 3227 temp = unlink_urbs (dev, &dev->txq) + unlink_urbs (dev, &dev->rxq);
3228 3228
3229 // maybe wait for deletions to finish. 3229 // maybe wait for deletions to finish.
3230 while (skb_queue_len (&dev->rxq) 3230 while (!skb_queue_empty(&dev->rxq) &&
3231 && skb_queue_len (&dev->txq) 3231 !skb_queue_empty(&dev->txq) &&
3232 && skb_queue_len (&dev->done)) { 3232 !skb_queue_empty(&dev->done)) {
3233 msleep(UNLINK_TIMEOUT_MS); 3233 msleep(UNLINK_TIMEOUT_MS);
3234 if (netif_msg_ifdown (dev)) 3234 if (netif_msg_ifdown (dev))
3235 devdbg (dev, "waited for %d urb completions", temp); 3235 devdbg (dev, "waited for %d urb completions", temp);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-18 09:29:37 -0500