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-rw-r--r--drivers/net/bnx2x_init.h36
-rw-r--r--drivers/net/bnx2x_main.c51
2 files changed, 31 insertions, 56 deletions
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
index 8af27573afe8..5362d5a42acb 100644
--- a/drivers/net/bnx2x_init.h
+++ b/drivers/net/bnx2x_init.h
@@ -22,12 +22,15 @@
22#define INIT_ASIC 0x4 22#define INIT_ASIC 0x4
23#define INIT_HARDWARE 0x7 23#define INIT_HARDWARE 0x7
24 24
25#define STORM_INTMEM_SIZE_E1 (0x5800 / 4) 25#define TSTORM_INTMEM_ADDR TSEM_REG_FAST_MEMORY
26#define STORM_INTMEM_SIZE_E1H (0x10000 / 4) 26#define CSTORM_INTMEM_ADDR CSEM_REG_FAST_MEMORY
27#define TSTORM_INTMEM_ADDR 0x1a0000 27#define XSTORM_INTMEM_ADDR XSEM_REG_FAST_MEMORY
28#define CSTORM_INTMEM_ADDR 0x220000 28#define USTORM_INTMEM_ADDR USEM_REG_FAST_MEMORY
29#define XSTORM_INTMEM_ADDR 0x2a0000 29/* RAM0 size in bytes */
30#define USTORM_INTMEM_ADDR 0x320000 30#define STORM_INTMEM_SIZE_E1 0x5800
31#define STORM_INTMEM_SIZE_E1H 0x10000
32#define STORM_INTMEM_SIZE(bp) ((CHIP_IS_E1H(bp) ? STORM_INTMEM_SIZE_E1H : \
33 STORM_INTMEM_SIZE_E1) / 4)
31 34
32 35
33/* Init operation types and structures */ 36/* Init operation types and structures */
@@ -150,7 +153,6 @@ static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
150 153
151static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len) 154static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len)
152{ 155{
153#ifdef USE_DMAE
154 int offset = 0; 156 int offset = 0;
155 157
156 if (bp->dmae_ready) { 158 if (bp->dmae_ready) {
@@ -164,21 +166,21 @@ static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len)
164 addr + offset, len); 166 addr + offset, len);
165 } else 167 } else
166 bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len); 168 bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len);
167#else
168 bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len);
169#endif
170} 169}
171 170
172static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) 171static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
173{ 172{
174 if ((len * 4) > FW_BUF_SIZE) { 173 u32 buf_len = (((len * 4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len * 4));
175 BNX2X_ERR("LARGE DMAE OPERATION ! addr 0x%x len 0x%x\n", 174 u32 buf_len32 = buf_len / 4;
176 addr, len*4); 175 int i;
177 return;
178 }
179 memset(bp->gunzip_buf, fill, len * 4);
180 176
181 bnx2x_write_big_buf(bp, addr, len); 177 memset(bp->gunzip_buf, fill, buf_len);
178
179 for (i = 0; i < len; i += buf_len32) {
180 u32 cur_len = min(buf_len32, len - i);
181
182 bnx2x_write_big_buf(bp, addr + i * 4, cur_len);
183 }
182} 184}
183 185
184static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data, 186static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data,
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index 46e2492fc9d0..3ef24b9eab3e 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -4223,10 +4223,10 @@ static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
4223{ 4223{
4224 int port = BP_PORT(bp); 4224 int port = BP_PORT(bp);
4225 4225
4226 bnx2x_init_fill(bp, BAR_USTRORM_INTMEM + 4226 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR +
4227 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, 4227 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
4228 sizeof(struct ustorm_status_block)/4); 4228 sizeof(struct ustorm_status_block)/4);
4229 bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM + 4229 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR +
4230 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, 4230 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
4231 sizeof(struct cstorm_status_block)/4); 4231 sizeof(struct cstorm_status_block)/4);
4232} 4232}
@@ -4280,18 +4280,18 @@ static void bnx2x_zero_def_sb(struct bnx2x *bp)
4280{ 4280{
4281 int func = BP_FUNC(bp); 4281 int func = BP_FUNC(bp);
4282 4282
4283 bnx2x_init_fill(bp, BAR_USTRORM_INTMEM + 4283 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR +
4284 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4285 sizeof(struct tstorm_def_status_block)/4);
4286 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR +
4284 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, 4287 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4285 sizeof(struct ustorm_def_status_block)/4); 4288 sizeof(struct ustorm_def_status_block)/4);
4286 bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM + 4289 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR +
4287 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, 4290 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4288 sizeof(struct cstorm_def_status_block)/4); 4291 sizeof(struct cstorm_def_status_block)/4);
4289 bnx2x_init_fill(bp, BAR_XSTRORM_INTMEM + 4292 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR +
4290 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, 4293 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4291 sizeof(struct xstorm_def_status_block)/4); 4294 sizeof(struct xstorm_def_status_block)/4);
4292 bnx2x_init_fill(bp, BAR_TSTRORM_INTMEM +
4293 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4294 sizeof(struct tstorm_def_status_block)/4);
4295} 4295}
4296 4296
4297static void bnx2x_init_def_sb(struct bnx2x *bp, 4297static void bnx2x_init_def_sb(struct bnx2x *bp,
@@ -5615,37 +5615,10 @@ static int bnx2x_init_common(struct bnx2x *bp)
5615 bnx2x_init_block(bp, USDM_COMMON_START, USDM_COMMON_END); 5615 bnx2x_init_block(bp, USDM_COMMON_START, USDM_COMMON_END);
5616 bnx2x_init_block(bp, XSDM_COMMON_START, XSDM_COMMON_END); 5616 bnx2x_init_block(bp, XSDM_COMMON_START, XSDM_COMMON_END);
5617 5617
5618 if (CHIP_IS_E1H(bp)) { 5618 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
5619 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0, 5619 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
5620 STORM_INTMEM_SIZE_E1H/2); 5620 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
5621 bnx2x_init_fill(bp, 5621 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
5622 TSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5623 0, STORM_INTMEM_SIZE_E1H/2);
5624 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
5625 STORM_INTMEM_SIZE_E1H/2);
5626 bnx2x_init_fill(bp,
5627 CSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5628 0, STORM_INTMEM_SIZE_E1H/2);
5629 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
5630 STORM_INTMEM_SIZE_E1H/2);
5631 bnx2x_init_fill(bp,
5632 XSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5633 0, STORM_INTMEM_SIZE_E1H/2);
5634 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
5635 STORM_INTMEM_SIZE_E1H/2);
5636 bnx2x_init_fill(bp,
5637 USTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5638 0, STORM_INTMEM_SIZE_E1H/2);
5639 } else { /* E1 */
5640 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
5641 STORM_INTMEM_SIZE_E1);
5642 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
5643 STORM_INTMEM_SIZE_E1);
5644 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
5645 STORM_INTMEM_SIZE_E1);
5646 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
5647 STORM_INTMEM_SIZE_E1);
5648 }
5649 5622
5650 bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END); 5623 bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END);
5651 bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END); 5624 bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END);