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-rw-r--r--drivers/rtc/rtc-sh.c1
-rw-r--r--drivers/serial/sh-sci.c9
-rw-r--r--drivers/serial/sh-sci.h66
3 files changed, 19 insertions, 57 deletions
diff --git a/drivers/rtc/rtc-sh.c b/drivers/rtc/rtc-sh.c
index e0f91dfce0f5..93ee05eeaeba 100644
--- a/drivers/rtc/rtc-sh.c
+++ b/drivers/rtc/rtc-sh.c
@@ -365,6 +365,7 @@ static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm)
365 /* Reset pre-scaler & stop RTC */ 365 /* Reset pre-scaler & stop RTC */
366 tmp = readb(rtc->regbase + RCR2); 366 tmp = readb(rtc->regbase + RCR2);
367 tmp |= RCR2_RESET; 367 tmp |= RCR2_RESET;
368 tmp &= ~RCR2_START;
368 writeb(tmp, rtc->regbase + RCR2); 369 writeb(tmp, rtc->regbase + RCR2);
369 370
370 writeb(BIN2BCD(tm->tm_sec), rtc->regbase + RSECCNT); 371 writeb(BIN2BCD(tm->tm_sec), rtc->regbase + RSECCNT);
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index 672cd1042539..053fca41b08a 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -12,6 +12,7 @@
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002) 13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 * Removed SH7300 support (Jul 2007).
15 * 16 *
16 * This file is subject to the terms and conditions of the GNU General Public 17 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive 18 * License. See the file "COPYING" in the main directory of this archive
@@ -289,13 +290,7 @@ static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
289#endif 290#endif
290 291
291#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF) 292#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
292#if defined(CONFIG_CPU_SUBTYPE_SH7300) 293#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
293/* SH7300 doesn't use RTS/CTS */
294static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
295{
296 sci_out(port, SCFCR, 0);
297}
298#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
299static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag) 294static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
300{ 295{
301 unsigned int fcr_val = 0; 296 unsigned int fcr_val = 0;
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index 247fb66bf0f4..cf75466ebf57 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -9,6 +9,7 @@
9 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 9 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003). 10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004). 11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
12 * Removed SH7300 support (Jul 2007).
12 */ 13 */
13#include <linux/serial_core.h> 14#include <linux/serial_core.h>
14#include <asm/io.h> 15#include <asm/io.h>
@@ -23,13 +24,10 @@
23#endif 24#endif
24#endif 25#endif
25 26
26#if defined(CONFIG_CPU_SUBTYPE_SH7708) 27#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
27# define SCSPTR 0xffffff7c /* 8 bit */ 28 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
28# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 29 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
29# define SCI_ONLY 30 defined(CONFIG_CPU_SUBTYPE_SH7709)
30#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7706)
33# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ 31# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
34# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ 32# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
35# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 33# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
@@ -73,11 +71,6 @@
73# define SCIF_ORER 0x0001 /* overrun error bit */ 71# define SCIF_ORER 0x0001 /* overrun error bit */
74# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 72# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
75# define SCIF_ONLY 73# define SCIF_ONLY
76#elif defined(CONFIG_CPU_SUBTYPE_SH7300)
77# define SCPCR 0xA4050116 /* 16 bit SCIF */
78# define SCPDR 0xA4050136 /* 16 bit SCIF */
79# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
80# define SCIF_ONLY
81#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 74#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
82# define SCSPTR0 0xA4400000 /* 16 bit SCIF */ 75# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
83# define SCI_NPORTS 2 76# define SCI_NPORTS 2
@@ -86,12 +79,6 @@
86# define PBCR 0xa4050102 79# define PBCR 0xa4050102
87# define SCSCR_INIT(port) 0x3B 80# define SCSCR_INIT(port) 0x3B
88# define SCIF_ONLY 81# define SCIF_ONLY
89#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
90# define SCPDR 0xA4050138 /* 16 bit SCIF */
91# define SCSPTR2 SCPDR
92# define SCIF_ORER 0x0001 /* overrun error bit */
93# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */
94# define SCIF_ONLY
95#elif defined(CONFIG_CPU_SUBTYPE_SH7343) 82#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
96# define SCSPTR0 0xffe00010 /* 16 bit SCIF */ 83# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
97# define SCSPTR1 0xffe10010 /* 16 bit SCIF */ 84# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
@@ -230,7 +217,7 @@
230#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 217#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
231#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 218#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
232 219
233#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 220#if defined(CONFIG_CPU_SUBTYPE_SH7705)
234#define SCIF_ORER 0x0200 221#define SCIF_ORER 0x0200
235#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) 222#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
236#define SCIF_RFDC_MASK 0x007f 223#define SCIF_RFDC_MASK 0x007f
@@ -259,7 +246,7 @@
259# define SCxSR_ERRORS(port) SCIF_ERRORS 246# define SCxSR_ERRORS(port) SCIF_ERRORS
260# define SCxSR_RDxF(port) SCIF_RDF 247# define SCxSR_RDxF(port) SCIF_RDF
261# define SCxSR_TDxE(port) SCIF_TDFE 248# define SCxSR_TDxE(port) SCIF_TDFE
262#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 249#if defined(CONFIG_CPU_SUBTYPE_SH7705)
263# define SCxSR_ORER(port) SCIF_ORER 250# define SCxSR_ORER(port) SCIF_ORER
264#else 251#else
265# define SCxSR_ORER(port) 0x0000 252# define SCxSR_ORER(port) 0x0000
@@ -267,13 +254,13 @@
267# define SCxSR_FER(port) SCIF_FER 254# define SCxSR_FER(port) SCIF_FER
268# define SCxSR_PER(port) SCIF_PER 255# define SCxSR_PER(port) SCIF_PER
269# define SCxSR_BRK(port) SCIF_BRK 256# define SCxSR_BRK(port) SCIF_BRK
270#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 257#if defined(CONFIG_CPU_SUBTYPE_SH7705)
271# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc) 258# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
272# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73) 259# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
273# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf) 260# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
274# define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3) 261# define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
275#else 262#else
276/* SH7705 can also use this, clearing is same between 7705 and 7709 and 7300 */ 263/* SH7705 can also use this, clearing is same between 7705 and 7709 */
277# define SCxSR_RDxF_CLEAR(port) 0x00fc 264# define SCxSR_RDxF_CLEAR(port) 0x00fc
278# define SCxSR_ERROR_CLEAR(port) 0x0073 265# define SCxSR_ERROR_CLEAR(port) 0x0073
279# define SCxSR_TDxE_CLEAR(port) 0x00df 266# define SCxSR_TDxE_CLEAR(port) 0x00df
@@ -375,8 +362,7 @@
375 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) 362 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
376#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ 363#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
377 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 364 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
378#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \ 365#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
379 defined(CONFIG_CPU_SUBTYPE_SH7705)
380#define SCIF_FNS(name, scif_offset, scif_size) \ 366#define SCIF_FNS(name, scif_offset, scif_size) \
381 CPU_SCIF_FNS(name, scif_offset, scif_size) 367 CPU_SCIF_FNS(name, scif_offset, scif_size)
382#else 368#else
@@ -402,8 +388,7 @@
402 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 388 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
403#endif 389#endif
404 390
405#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \ 391#if defined(CONFIG_CPU_SUBTYPE_SH7705)
406 defined(CONFIG_CPU_SUBTYPE_SH7705)
407 392
408SCIF_FNS(SCSMR, 0x00, 16) 393SCIF_FNS(SCSMR, 0x00, 16)
409SCIF_FNS(SCBRR, 0x04, 8) 394SCIF_FNS(SCBRR, 0x04, 8)
@@ -485,16 +470,10 @@ static const struct __attribute__((packed)) {
485}; 470};
486#endif 471#endif
487 472
488#if defined(CONFIG_CPU_SUBTYPE_SH7708) 473#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
489static inline int sci_rxd_in(struct uart_port *port) 474 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
490{ 475 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
491 if (port->mapbase == 0xfffffe80) 476 defined(CONFIG_CPU_SUBTYPE_SH7709)
492 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */
493 return 1;
494}
495#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
496 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
497 defined(CONFIG_CPU_SUBTYPE_SH7706)
498static inline int sci_rxd_in(struct uart_port *port) 477static inline int sci_rxd_in(struct uart_port *port)
499{ 478{
500 if (port->mapbase == 0xfffffe80) 479 if (port->mapbase == 0xfffffe80)
@@ -562,18 +541,6 @@ static inline int sci_rxd_in(struct uart_port *port)
562 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 541 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
563 return 1; 542 return 1;
564} 543}
565#elif defined(CONFIG_CPU_SUBTYPE_SH7300)
566static inline int sci_rxd_in(struct uart_port *port)
567{
568 if (port->mapbase == 0xa4430000)
569 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
570 return 1;
571}
572#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
573static inline int sci_rxd_in(struct uart_port *port)
574{
575 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
576}
577#elif defined(CONFIG_CPU_SUBTYPE_SH7343) 544#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
578static inline int sci_rxd_in(struct uart_port *port) 545static inline int sci_rxd_in(struct uart_port *port)
579{ 546{
@@ -721,8 +688,7 @@ static inline int sci_rxd_in(struct uart_port *port)
721 * -- Mitch Davis - 15 Jul 2000 688 * -- Mitch Davis - 15 Jul 2000
722 */ 689 */
723 690
724#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \ 691#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
725 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
726 defined(CONFIG_CPU_SUBTYPE_SH7785) 692 defined(CONFIG_CPU_SUBTYPE_SH7785)
727#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) 693#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
728#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 694#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 06:26:37 -0500