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-rw-r--r--drivers/net/Kconfig20
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/sky2.c2873
-rw-r--r--drivers/net/sky2.h1931
4 files changed, 4824 insertions, 1 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 96f14ab1c1f5..d8adb4222ca3 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1955,7 +1955,25 @@ config SKGE
1955 1955
1956 It does not support the link failover and network management 1956 It does not support the link failover and network management
1957 features that "portable" vendor supplied sk98lin driver does. 1957 features that "portable" vendor supplied sk98lin driver does.
1958 1958
1959
1960config SKY2
1961 tristate "SysKonnect Yukon2 support (EXPERIMENTAL)"
1962 depends on PCI && EXPERIMENTAL
1963 select CRC32
1964 ---help---
1965 This driver support the Marvell Yukon 2 Gigabit Ethernet adapter.
1966
1967 To compile this driver as a module, choose M here: the module
1968 will be called sky2. This is recommended.
1969
1970config SKY2_EC_A1
1971 bool "Support old Yukon-EC A1 chipset"
1972 depends on SKY2
1973 ---help---
1974 Include support for early revisions of the Yukon EC chipset
1975 that required extra workarounds. If in doubt, say N.
1976
1959config SK98LIN 1977config SK98LIN
1960 tristate "Marvell Yukon Chipset / SysKonnect SK-98xx Support" 1978 tristate "Marvell Yukon Chipset / SysKonnect SK-98xx Support"
1961 depends on PCI 1979 depends on PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 8645c843cf4d..c849afc25c00 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -58,6 +58,7 @@ spidernet-y += spider_net.o spider_net_ethtool.o sungem_phy.o
58obj-$(CONFIG_SPIDER_NET) += spidernet.o 58obj-$(CONFIG_SPIDER_NET) += spidernet.o
59obj-$(CONFIG_TC35815) += tc35815.o 59obj-$(CONFIG_TC35815) += tc35815.o
60obj-$(CONFIG_SKGE) += skge.o 60obj-$(CONFIG_SKGE) += skge.o
61obj-$(CONFIG_SKY2) += sky2.o
61obj-$(CONFIG_SK98LIN) += sk98lin/ 62obj-$(CONFIG_SK98LIN) += sk98lin/
62obj-$(CONFIG_SKFP) += skfp/ 63obj-$(CONFIG_SKFP) += skfp/
63obj-$(CONFIG_VIA_RHINE) += via-rhine.o 64obj-$(CONFIG_VIA_RHINE) += via-rhine.o
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
new file mode 100644
index 000000000000..bc95aacab20f
--- /dev/null
+++ b/drivers/net/sky2.c
@@ -0,0 +1,2873 @@
1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26/*
27 * TODO
28 * - coalescing setting?
29 * - vlan support
30 *
31 * TOTEST
32 * - variable ring size
33 * - speed setting
34 * - power management
35 * - netpoll
36 */
37
38#include <linux/config.h>
39#include <linux/crc32.h>
40#include <linux/kernel.h>
41#include <linux/version.h>
42#include <linux/module.h>
43#include <linux/netdevice.h>
44#include <linux/etherdevice.h>
45#include <linux/ethtool.h>
46#include <linux/pci.h>
47#include <linux/ip.h>
48#include <linux/tcp.h>
49#include <linux/in.h>
50#include <linux/delay.h>
51
52#include <asm/irq.h>
53
54#include "sky2.h"
55
56#define DRV_NAME "sky2"
57#define DRV_VERSION "0.4"
58#define PFX DRV_NAME " "
59
60/*
61 * The Yukon II chipset takes 64 bit command blocks (called list elements)
62 * that are organized into three (receive, transmit, status) different rings
63 * similar to Tigon3. A transmit can require several elements;
64 * a receive requires one (or two if using 64 bit dma).
65 */
66
67#ifdef CONFIG_SKY2_EC_A1
68#define is_ec_a1(hw) \
69 ((hw)->chip_id == CHIP_ID_YUKON_EC && \
70 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
71#else
72#define is_ec_a1(hw) 0
73#endif
74
75#define RX_LE_SIZE 256
76#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
77#define RX_MAX_PENDING (RX_LE_SIZE/2 - 1)
78#define RX_DEF_PENDING 128
79#define RX_COPY_THRESHOLD 128
80
81#define TX_RING_SIZE 512
82#define TX_DEF_PENDING (TX_RING_SIZE - 1)
83#define TX_MIN_PENDING 64
84#define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
85
86#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
87#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
88#define ETH_JUMBO_MTU 9000
89#define TX_WATCHDOG (5 * HZ)
90#define NAPI_WEIGHT 64
91#define PHY_RETRIES 1000
92
93static const u32 default_msg =
94 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
95 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
96 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
97
98static int debug = -1; /* defaults above */
99module_param(debug, int, 0);
100MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
101
102static const struct pci_device_id sky2_id_table[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
120 { 0 }
121};
122
123MODULE_DEVICE_TABLE(pci, sky2_id_table);
124
125/* Avoid conditionals by using array */
126static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
127static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
128
129static const char *yukon_name[] = {
130 [CHIP_ID_YUKON_LITE - CHIP_ID_YUKON] = "Lite", /* 0xb0 */
131 [CHIP_ID_YUKON_LP - CHIP_ID_YUKON] = "LP", /* 0xb2 */
132 [CHIP_ID_YUKON_XL - CHIP_ID_YUKON] = "XL", /* 0xb3 */
133
134 [CHIP_ID_YUKON_EC - CHIP_ID_YUKON] = "EC", /* 0xb6 */
135 [CHIP_ID_YUKON_FE - CHIP_ID_YUKON] = "FE", /* 0xb7 */
136};
137
138
139/* Access to external PHY */
140static void gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
141{
142 int i;
143
144 gma_write16(hw, port, GM_SMI_DATA, val);
145 gma_write16(hw, port, GM_SMI_CTRL,
146 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
147
148 for (i = 0; i < PHY_RETRIES; i++) {
149 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
150 return;
151 udelay(1);
152 }
153 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
154}
155
156static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
157{
158 int i;
159
160 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
161 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
162
163 for (i = 0; i < PHY_RETRIES; i++) {
164 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
165 goto ready;
166 udelay(1);
167 }
168
169 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
170ready:
171 return gma_read16(hw, port, GM_SMI_DATA);
172}
173
174static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
175{
176 u16 reg;
177
178 /* disable all GMAC IRQ's */
179 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
180 /* disable PHY IRQs */
181 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
182
183 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
184 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
185 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
186 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
187
188 reg = gma_read16(hw, port, GM_RX_CTRL);
189 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
190 gma_write16(hw, port, GM_RX_CTRL, reg);
191}
192
193static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
194{
195 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
196 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
197
198 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
199 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
200
201 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
202 PHY_M_EC_MAC_S_MSK);
203 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
204
205 if (hw->chip_id == CHIP_ID_YUKON_EC)
206 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
207 else
208 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
209
210 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
211 }
212
213 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
214 if (hw->copper) {
215 if (hw->chip_id == CHIP_ID_YUKON_FE) {
216 /* enable automatic crossover */
217 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
218 } else {
219 /* disable energy detect */
220 ctrl &= ~PHY_M_PC_EN_DET_MSK;
221
222 /* enable automatic crossover */
223 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
224
225 if (sky2->autoneg == AUTONEG_ENABLE &&
226 hw->chip_id == CHIP_ID_YUKON_XL) {
227 ctrl &= ~PHY_M_PC_DSC_MSK;
228 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
229 }
230 }
231 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
232 } else {
233 /* workaround for deviation #4.88 (CRC errors) */
234 /* disable Automatic Crossover */
235
236 ctrl &= ~PHY_M_PC_MDIX_MSK;
237 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
238
239 if (hw->chip_id == CHIP_ID_YUKON_XL) {
240 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
241 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
242 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
243 ctrl &= ~PHY_M_MAC_MD_MSK;
244 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
245 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
246
247 /* select page 1 to access Fiber registers */
248 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
249 }
250 }
251
252 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
253 if (sky2->autoneg == AUTONEG_DISABLE)
254 ctrl &= ~PHY_CT_ANE;
255 else
256 ctrl |= PHY_CT_ANE;
257
258 ctrl |= PHY_CT_RESET;
259 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
260
261 ctrl = 0;
262 ct1000 = 0;
263 adv = PHY_AN_CSMA;
264
265 if (sky2->autoneg == AUTONEG_ENABLE) {
266 if (hw->copper) {
267 if (sky2->advertising & ADVERTISED_1000baseT_Full)
268 ct1000 |= PHY_M_1000C_AFD;
269 if (sky2->advertising & ADVERTISED_1000baseT_Half)
270 ct1000 |= PHY_M_1000C_AHD;
271 if (sky2->advertising & ADVERTISED_100baseT_Full)
272 adv |= PHY_M_AN_100_FD;
273 if (sky2->advertising & ADVERTISED_100baseT_Half)
274 adv |= PHY_M_AN_100_HD;
275 if (sky2->advertising & ADVERTISED_10baseT_Full)
276 adv |= PHY_M_AN_10_FD;
277 if (sky2->advertising & ADVERTISED_10baseT_Half)
278 adv |= PHY_M_AN_10_HD;
279 } else /* special defines for FIBER (88E1011S only) */
280 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
281
282 /* Set Flow-control capabilities */
283 if (sky2->tx_pause && sky2->rx_pause)
284 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
285 else if (sky2->rx_pause && !sky2->tx_pause)
286 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
287 else if (!sky2->rx_pause && sky2->tx_pause)
288 adv |= PHY_AN_PAUSE_ASYM; /* local */
289
290 /* Restart Auto-negotiation */
291 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
292 } else {
293 /* forced speed/duplex settings */
294 ct1000 = PHY_M_1000C_MSE;
295
296 if (sky2->duplex == DUPLEX_FULL)
297 ctrl |= PHY_CT_DUP_MD;
298
299 switch (sky2->speed) {
300 case SPEED_1000:
301 ctrl |= PHY_CT_SP1000;
302 break;
303 case SPEED_100:
304 ctrl |= PHY_CT_SP100;
305 break;
306 }
307
308 ctrl |= PHY_CT_RESET;
309 }
310
311 if (hw->chip_id != CHIP_ID_YUKON_FE)
312 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
313
314 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
315 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
316
317 /* Setup Phy LED's */
318 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
319 ledover = 0;
320
321 switch (hw->chip_id) {
322 case CHIP_ID_YUKON_FE:
323 /* on 88E3082 these bits are at 11..9 (shifted left) */
324 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
325
326 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
327
328 /* delete ACT LED control bits */
329 ctrl &= ~PHY_M_FELP_LED1_MSK;
330 /* change ACT LED control to blink mode */
331 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
332 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
333 break;
334
335 case CHIP_ID_YUKON_XL:
336 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
337
338 /* select page 3 to access LED control register */
339 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
340
341 /* set LED Function Control register */
342 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
343 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
344 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
345 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
346
347 /* set Polarity Control register */
348 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
349 (PHY_M_POLC_LS1_P_MIX(4) |
350 PHY_M_POLC_IS0_P_MIX(4) |
351 PHY_M_POLC_LOS_CTRL(2) |
352 PHY_M_POLC_INIT_CTRL(2) |
353 PHY_M_POLC_STA1_CTRL(2) |
354 PHY_M_POLC_STA0_CTRL(2)));
355
356 /* restore page register */
357 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
358 break;
359
360 default:
361 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
362 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
363 /* turn off the Rx LED (LED_RX) */
364 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
365 }
366
367 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
368
369 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
370 /* turn on 100 Mbps LED (LED_LINK100) */
371 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
372 }
373
374 if (ledover)
375 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
376
377 /* Enable phy interrupt on autonegotiation complete (or link up) */
378 if (sky2->autoneg == AUTONEG_ENABLE)
379 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
380 else
381 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
382}
383
384static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
385{
386 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
387 u16 reg;
388 int i;
389 const u8 *addr = hw->dev[port]->dev_addr;
390
391 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
392 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
393
394 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
395
396 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
397 /* WA DEV_472 -- looks like crossed wires on port 2 */
398 /* clear GMAC 1 Control reset */
399 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
400 do {
401 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
402 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
403 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
404 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
405 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
406 }
407
408 if (sky2->autoneg == AUTONEG_DISABLE) {
409 reg = gma_read16(hw, port, GM_GP_CTRL);
410 reg |= GM_GPCR_AU_ALL_DIS;
411 gma_write16(hw, port, GM_GP_CTRL, reg);
412 gma_read16(hw, port, GM_GP_CTRL);
413
414 switch (sky2->speed) {
415 case SPEED_1000:
416 reg |= GM_GPCR_SPEED_1000;
417 /* fallthru */
418 case SPEED_100:
419 reg |= GM_GPCR_SPEED_100;
420 }
421
422 if (sky2->duplex == DUPLEX_FULL)
423 reg |= GM_GPCR_DUP_FULL;
424 } else
425 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
426
427 if (!sky2->tx_pause && !sky2->rx_pause) {
428 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
429 reg |=
430 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
431 } else if (sky2->tx_pause && !sky2->rx_pause) {
432 /* disable Rx flow-control */
433 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
434 }
435
436 gma_write16(hw, port, GM_GP_CTRL, reg);
437
438 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
439
440 spin_lock_bh(&hw->phy_lock);
441 sky2_phy_init(hw, port);
442 spin_unlock_bh(&hw->phy_lock);
443
444 /* MIB clear */
445 reg = gma_read16(hw, port, GM_PHY_ADDR);
446 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
447
448 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
449 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
450 gma_write16(hw, port, GM_PHY_ADDR, reg);
451
452 /* transmit control */
453 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
454
455 /* receive control reg: unicast + multicast + no FCS */
456 gma_write16(hw, port, GM_RX_CTRL,
457 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
458
459 /* transmit flow control */
460 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
461
462 /* transmit parameter */
463 gma_write16(hw, port, GM_TX_PARAM,
464 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
465 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
466 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
467 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
468
469 /* serial mode register */
470 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
471 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
472
473 if (hw->dev[port]->mtu > 1500)
474 reg |= GM_SMOD_JUMBO_ENA;
475
476 gma_write16(hw, port, GM_SERIAL_MODE, reg);
477
478 /* virtual address for data */
479 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
480
481 /* physical address: used for pause frames */
482 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
483
484 /* ignore counter overflows */
485 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
486 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
487 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
488
489 /* Configure Rx MAC FIFO */
490 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
491 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
492 GMF_OPER_ON | GMF_RX_F_FL_ON);
493
494 /* Flush Rx MAC FIFO on any flowcontrol or error */
495 reg = GMR_FS_ANY_ERR;
496 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev <= 1)
497 reg = 0; /* WA Dev #4115 */
498
499 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), reg);
500 /* Set threshold to 0xa (64 bytes)
501 * ASF disabled so no need to do WA dev #4.30
502 */
503 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
504
505 /* Configure Tx MAC FIFO */
506 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
507 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
508}
509
510static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
511{
512 u32 end;
513
514 start /= 8;
515 len /= 8;
516 end = start + len - 1;
517
518 pr_debug("sky2_ramset start=%d end=%d\n", start, end);
519
520 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
521 sky2_write32(hw, RB_ADDR(q, RB_START), start);
522 sky2_write32(hw, RB_ADDR(q, RB_END), end);
523 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
524 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
525
526 if (q == Q_R1 || q == Q_R2) {
527 u32 rxup, rxlo;
528
529 rxlo = len/2;
530 rxup = rxlo + len/4;
531 pr_debug(" utpp=%d ltpp=%d\n", rxup, rxlo);
532
533 /* Set thresholds on receive queue's */
534 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
535 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
536 } else {
537 /* Enable store & forward on Tx queue's because
538 * Tx FIFO is only 1K on Yukon
539 */
540 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
541 }
542
543 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
544 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
545}
546
547/* Setup Bus Memory Interface */
548static void sky2_qset(struct sky2_hw *hw, u16 q, u32 wm)
549{
550 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
551 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
552 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
553 sky2_write32(hw, Q_ADDR(q, Q_WM), wm);
554}
555
556/* Setup prefetch unit registers. This is the interface between
557 * hardware and driver list elements
558 */
559static inline void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
560 u64 addr, u32 last)
561{
562 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
563 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
564 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
565 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
566 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
567 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
568
569 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
570}
571
572static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
573{
574 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
575
576 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
577 return le;
578}
579
580/*
581 * This is a workaround code taken from syskonnect sk98lin driver
582 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
583 */
584static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
585 u16 idx, u16 *last, u16 size)
586{
587 if (is_ec_a1(hw) && idx < *last) {
588 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
589
590 if (hwget == 0) {
591 /* Start prefetching again */
592 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
593 goto setnew;
594 }
595
596 if (hwget == size - 1) {
597 /* set watermark to one list element */
598 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
599
600 /* set put index to first list element */
601 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
602 } else /* have hardware go to end of list */
603 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
604 size - 1);
605 } else {
606setnew:
607 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
608 }
609 *last = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX));
610}
611
612
613static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
614{
615 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
616 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
617 return le;
618}
619
620/* Build description to hardware about buffer */
621static inline void sky2_rx_add(struct sky2_port *sky2, struct ring_info *re)
622{
623 struct sky2_rx_le *le;
624 u32 hi = (re->mapaddr >> 16) >> 16;
625
626 re->idx = sky2->rx_put;
627 if (sky2->rx_addr64 != hi) {
628 le = sky2_next_rx(sky2);
629 le->addr = cpu_to_le32(hi);
630 le->ctrl = 0;
631 le->opcode = OP_ADDR64 | HW_OWNER;
632 sky2->rx_addr64 = hi;
633 }
634
635 le = sky2_next_rx(sky2);
636 le->addr = cpu_to_le32((u32) re->mapaddr);
637 le->length = cpu_to_le16(re->maplen);
638 le->ctrl = 0;
639 le->opcode = OP_PACKET | HW_OWNER;
640}
641
642/* Tell receiver about new buffers. */
643static inline void rx_set_put(struct net_device *dev)
644{
645 struct sky2_port *sky2 = netdev_priv(dev);
646
647 if (sky2->rx_last_put != sky2->rx_put)
648 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
649 &sky2->rx_last_put, RX_LE_SIZE);
650}
651
652/* Tell chip where to start receive checksum.
653 * Actually has two checksums, but set both same to avoid possible byte
654 * order problems.
655 */
656static void rx_set_checksum(struct sky2_port *sky2)
657{
658 struct sky2_rx_le *le;
659
660 le = sky2_next_rx(sky2);
661 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
662 le->ctrl = 0;
663 le->opcode = OP_TCPSTART | HW_OWNER;
664
665 sky2_write16(sky2->hw, Y2_QADDR(rxqaddr[sky2->port],
666 PREF_UNIT_PUT_IDX), sky2->rx_put);
667 sky2_read16(sky2->hw, Y2_QADDR(rxqaddr[sky2->port], PREF_UNIT_PUT_IDX));
668 mdelay(1);
669 sky2_write32(sky2->hw,
670 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
671 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
672
673}
674
675
676/* Cleanout receive buffer area, assumes receiver hardware stopped */
677static void sky2_rx_clean(struct sky2_port *sky2)
678{
679 unsigned i;
680
681 memset(sky2->rx_le, 0, RX_LE_BYTES);
682 for (i = 0; i < sky2->rx_pending; i++) {
683 struct ring_info *re = sky2->rx_ring + i;
684
685 if (re->skb) {
686 pci_unmap_single(sky2->hw->pdev,
687 re->mapaddr, re->maplen,
688 PCI_DMA_FROMDEVICE);
689 kfree_skb(re->skb);
690 re->skb = NULL;
691 }
692 }
693}
694
695static inline struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2,
696 unsigned int size,
697 unsigned int gfp_mask)
698{
699 struct sk_buff *skb;
700
701 skb = alloc_skb(size + NET_IP_ALIGN, gfp_mask);
702 if (likely(skb)) {
703 skb->dev = sky2->netdev;
704 skb_reserve(skb, NET_IP_ALIGN);
705 }
706 return skb;
707}
708
709/*
710 * Allocate and setup receiver buffer pool.
711 * In case of 64 bit dma, there are 2X as many list elements
712 * available as ring entries
713 * and need to reserve one list element so we don't wrap around.
714 */
715static int sky2_rx_fill(struct sky2_port *sky2)
716{
717 unsigned i;
718 const unsigned rx_buf_size = sky2->netdev->mtu + ETH_HLEN + 8;
719
720 for (i = 0; i < sky2->rx_pending; i++) {
721 struct ring_info *re = sky2->rx_ring + i;
722
723 re->skb = sky2_rx_alloc(sky2, rx_buf_size, GFP_KERNEL);
724 if (!re->skb)
725 goto nomem;
726
727 re->mapaddr = pci_map_single(sky2->hw->pdev, re->skb->data,
728 rx_buf_size, PCI_DMA_FROMDEVICE);
729 re->maplen = rx_buf_size;
730 sky2_rx_add(sky2, re);
731 }
732
733 return 0;
734nomem:
735 sky2_rx_clean(sky2);
736 return -ENOMEM;
737}
738
739/* Bring up network interface. */
740static int sky2_up(struct net_device *dev)
741{
742 struct sky2_port *sky2 = netdev_priv(dev);
743 struct sky2_hw *hw = sky2->hw;
744 unsigned port = sky2->port;
745 u32 ramsize, rxspace;
746 int err = -ENOMEM;
747
748 if (netif_msg_ifup(sky2))
749 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
750
751 /* must be power of 2 */
752 sky2->tx_le = pci_alloc_consistent(hw->pdev,
753 TX_RING_SIZE *
754 sizeof(struct sky2_tx_le),
755 &sky2->tx_le_map);
756 if (!sky2->tx_le)
757 goto err_out;
758
759 sky2->tx_ring = kmalloc(TX_RING_SIZE * sizeof(struct ring_info),
760 GFP_KERNEL);
761 if (!sky2->tx_ring)
762 goto err_out;
763 sky2->tx_prod = sky2->tx_cons = 0;
764 memset(sky2->tx_ring, 0, TX_RING_SIZE * sizeof(struct ring_info));
765
766 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
767 &sky2->rx_le_map);
768 if (!sky2->rx_le)
769 goto err_out;
770 memset(sky2->rx_le, 0, RX_LE_BYTES);
771
772 sky2->rx_ring = kmalloc(sky2->rx_pending * sizeof(struct ring_info),
773 GFP_KERNEL);
774 if (!sky2->rx_ring)
775 goto err_out;
776
777 sky2_mac_init(hw, port);
778
779 /* Configure RAM buffers */
780 if (hw->chip_id == CHIP_ID_YUKON_FE ||
781 (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
782 ramsize = 4096;
783 else {
784 u8 e0 = sky2_read8(hw, B2_E_0);
785 ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
786 }
787
788 /* 2/3 for Rx */
789 rxspace = (2 * ramsize) / 3;
790 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
791 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
792
793 /* Make sure SyncQ is disabled */
794 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
795 RB_RST_SET);
796
797 sky2_qset(hw, rxqaddr[port], is_pciex(hw) ? 0x80 : 0x600);
798 sky2_qset(hw, txqaddr[port], 0x600);
799
800 sky2->rx_put = sky2->rx_next = 0;
801 sky2_prefetch_init(hw, rxqaddr[port], sky2->rx_le_map, RX_LE_SIZE - 1);
802
803 rx_set_checksum(sky2);
804
805 err = sky2_rx_fill(sky2);
806 if (err)
807 goto err_out;
808
809 /* Give buffers to receiver */
810 sky2_write16(sky2->hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX),
811 sky2->rx_put);
812 sky2->rx_last_put = sky2_read16(sky2->hw,
813 Y2_QADDR(rxqaddr[port],
814 PREF_UNIT_PUT_IDX));
815
816 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
817 TX_RING_SIZE - 1);
818
819 /* Enable interrupts from phy/mac for port */
820 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
821 sky2_write32(hw, B0_IMSK, hw->intr_mask);
822 return 0;
823
824err_out:
825 if (sky2->rx_le)
826 pci_free_consistent(hw->pdev, RX_LE_BYTES,
827 sky2->rx_le, sky2->rx_le_map);
828 if (sky2->tx_le)
829 pci_free_consistent(hw->pdev,
830 TX_RING_SIZE * sizeof(struct sky2_tx_le),
831 sky2->tx_le, sky2->tx_le_map);
832 if (sky2->tx_ring)
833 kfree(sky2->tx_ring);
834 if (sky2->rx_ring)
835 kfree(sky2->rx_ring);
836
837 return err;
838}
839
840/* Modular subtraction in ring */
841static inline int tx_dist(unsigned tail, unsigned head)
842{
843 return (head >= tail ? head : head + TX_RING_SIZE) - tail;
844}
845
846/* Number of list elements available for next tx */
847static inline int tx_avail(const struct sky2_port *sky2)
848{
849 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
850}
851
852/* Estimate of number of transmit list elements required */
853static inline unsigned tx_le_req(const struct sk_buff *skb)
854{
855 unsigned count;
856
857 count = sizeof(dma_addr_t) / sizeof(u32);
858 count += skb_shinfo(skb)->nr_frags * count;
859
860 if (skb_shinfo(skb)->tso_size)
861 ++count;
862
863 if (skb->ip_summed)
864 ++count;
865
866 return count;
867}
868
869/*
870 * Put one packet in ring for transmit.
871 * A single packet can generate multiple list elements, and
872 * the number of ring elements will probably be less than the number
873 * of list elements used.
874 */
875static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
876{
877 struct sky2_port *sky2 = netdev_priv(dev);
878 struct sky2_hw *hw = sky2->hw;
879 struct sky2_tx_le *le;
880 struct ring_info *re;
881 unsigned long flags;
882 unsigned i, len;
883 dma_addr_t mapping;
884 u32 addr64;
885 u16 mss;
886 u8 ctrl;
887
888 local_irq_save(flags);
889 if (!spin_trylock(&sky2->tx_lock)) {
890 local_irq_restore(flags);
891 return NETDEV_TX_LOCKED;
892 }
893
894 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
895 netif_stop_queue(dev);
896 spin_unlock_irqrestore(&sky2->tx_lock, flags);
897
898 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
899 dev->name);
900 return NETDEV_TX_BUSY;
901 }
902
903 if (unlikely(netif_msg_tx_queued(sky2)))
904 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
905 dev->name, sky2->tx_prod, skb->len);
906
907 len = skb_headlen(skb);
908 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
909 addr64 = (mapping >> 16) >> 16;
910
911 re = sky2->tx_ring + sky2->tx_prod;
912
913 /* Send high bits if changed */
914 if (addr64 != sky2->tx_addr64) {
915 le = get_tx_le(sky2);
916 le->tx.addr = cpu_to_le32(addr64);
917 le->ctrl = 0;
918 le->opcode = OP_ADDR64 | HW_OWNER;
919 sky2->tx_addr64 = addr64;
920 }
921
922 /* Check for TCP Segmentation Offload */
923 mss = skb_shinfo(skb)->tso_size;
924 if (mss != 0) {
925 /* just drop the packet if non-linear expansion fails */
926 if (skb_header_cloned(skb) &&
927 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
928 dev_kfree_skb_any(skb);
929 goto out_unlock;
930 }
931
932 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
933 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
934 mss += ETH_HLEN;
935 }
936
937 if (mss != sky2->tx_last_mss) {
938 le = get_tx_le(sky2);
939 le->tx.tso.size = cpu_to_le16(mss);
940 le->tx.tso.rsvd = 0;
941 le->opcode = OP_LRGLEN | HW_OWNER;
942 le->ctrl = 0;
943 sky2->tx_last_mss = mss;
944 }
945
946 /* Handle TCP checksum offload */
947 ctrl = 0;
948 if (skb->ip_summed == CHECKSUM_HW) {
949 u16 hdr = skb->h.raw - skb->data;
950 u16 offset = hdr + skb->csum;
951
952 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
953 if (skb->nh.iph->protocol == IPPROTO_UDP)
954 ctrl |= UDPTCP;
955
956 le = get_tx_le(sky2);
957 le->tx.csum.start = cpu_to_le16(hdr);
958 le->tx.csum.offset = cpu_to_le16(offset);
959 le->length = 0; /* initial checksum value */
960 le->ctrl = 1; /* one packet */
961 le->opcode = OP_TCPLISW | HW_OWNER;
962 }
963
964 le = get_tx_le(sky2);
965 le->tx.addr = cpu_to_le32((u32) mapping);
966 le->length = cpu_to_le16(len);
967 le->ctrl = ctrl;
968 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
969
970 /* Record the transmit mapping info */
971 re->skb = skb;
972 re->mapaddr = mapping;
973 re->maplen = len;
974
975 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
976 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
977 struct ring_info *fre;
978
979 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
980 frag->size, PCI_DMA_TODEVICE);
981 addr64 = (mapping >> 16) >> 16;
982 if (addr64 != sky2->tx_addr64) {
983 le = get_tx_le(sky2);
984 le->tx.addr = cpu_to_le32(addr64);
985 le->ctrl = 0;
986 le->opcode = OP_ADDR64 | HW_OWNER;
987 sky2->tx_addr64 = addr64;
988 }
989
990 le = get_tx_le(sky2);
991 le->tx.addr = cpu_to_le32((u32) mapping);
992 le->length = cpu_to_le16(frag->size);
993 le->ctrl = ctrl;
994 le->opcode = OP_BUFFER | HW_OWNER;
995
996 fre = sky2->tx_ring
997 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
998 fre->skb = NULL;
999 fre->mapaddr = mapping;
1000 fre->maplen = frag->size;
1001 }
1002 re->idx = sky2->tx_prod;
1003 le->ctrl |= EOP;
1004
1005 sky2_put_idx(sky2->hw, txqaddr[sky2->port], sky2->tx_prod,
1006 &sky2->tx_last_put, TX_RING_SIZE);
1007
1008 if (tx_avail(sky2) < MAX_SKB_TX_LE + 1)
1009 netif_stop_queue(dev);
1010
1011out_unlock:
1012 mmiowb();
1013 spin_unlock_irqrestore(&sky2->tx_lock, flags);
1014
1015 dev->trans_start = jiffies;
1016 return NETDEV_TX_OK;
1017}
1018
1019/*
1020 * Free ring elements from starting at tx_cons until "done"
1021 *
1022 * NB: the hardware will tell us about partial completion of multi-part
1023 * buffers; these are defered until completion.
1024 */
1025static void sky2_tx_complete(struct net_device *dev, u16 done)
1026{
1027 struct sky2_port *sky2 = netdev_priv(dev);
1028 unsigned i;
1029
1030 if (netif_msg_tx_done(sky2))
1031 printk(KERN_DEBUG "%s: tx done, upto %u\n", dev->name, done);
1032
1033 spin_lock(&sky2->tx_lock);
1034
1035 while (sky2->tx_cons != done) {
1036 struct ring_info *re = sky2->tx_ring + sky2->tx_cons;
1037 struct sk_buff *skb;
1038
1039 /* Check for partial status */
1040 if (tx_dist(sky2->tx_cons, done)
1041 < tx_dist(sky2->tx_cons, re->idx))
1042 goto out;
1043
1044 skb = re->skb;
1045 pci_unmap_single(sky2->hw->pdev,
1046 re->mapaddr, re->maplen, PCI_DMA_TODEVICE);
1047
1048 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1049 struct ring_info *fre;
1050 fre =
1051 sky2->tx_ring + (sky2->tx_cons + i +
1052 1) % TX_RING_SIZE;
1053 pci_unmap_page(sky2->hw->pdev, fre->mapaddr,
1054 fre->maplen, PCI_DMA_TODEVICE);
1055 }
1056
1057 dev_kfree_skb_any(skb);
1058
1059 sky2->tx_cons = re->idx;
1060 }
1061out:
1062
1063 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1064 netif_wake_queue(dev);
1065 spin_unlock(&sky2->tx_lock);
1066}
1067
1068/* Cleanup all untransmitted buffers, assume transmitter not running */
1069static inline void sky2_tx_clean(struct sky2_port *sky2)
1070{
1071 sky2_tx_complete(sky2->netdev, sky2->tx_prod);
1072}
1073
1074/* Network shutdown */
1075static int sky2_down(struct net_device *dev)
1076{
1077 struct sky2_port *sky2 = netdev_priv(dev);
1078 struct sky2_hw *hw = sky2->hw;
1079 unsigned port = sky2->port;
1080 u16 ctrl;
1081 int i;
1082
1083 if (netif_msg_ifdown(sky2))
1084 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1085
1086 netif_stop_queue(dev);
1087
1088 sky2_phy_reset(hw, port);
1089
1090 /* Stop transmitter */
1091 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1092 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1093
1094 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1095 RB_RST_SET | RB_DIS_OP_MD);
1096
1097 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1098 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1099 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1100
1101 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1102
1103 /* Workaround shared GMAC reset */
1104 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1105 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1106 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1107
1108 /* Disable Force Sync bit and Enable Alloc bit */
1109 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1110 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1111
1112 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1113 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1114 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1115
1116 /* Reset the PCI FIFO of the async Tx queue */
1117 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1118 BMU_RST_SET | BMU_FIFO_RST);
1119
1120 /* Reset the Tx prefetch units */
1121 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1122 PREF_UNIT_RST_SET);
1123
1124 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1125
1126 /*
1127 * The RX Stop command will not work for Yukon-2 if the BMU does not
1128 * reach the end of packet and since we can't make sure that we have
1129 * incoming data, we must reset the BMU while it is not doing a DMA
1130 * transfer. Since it is possible that the RX path is still active,
1131 * the RX RAM buffer will be stopped first, so any possible incoming
1132 * data will not trigger a DMA. After the RAM buffer is stopped, the
1133 * BMU is polled until any DMA in progress is ended and only then it
1134 * will be reset.
1135 */
1136
1137 /* disable the RAM Buffer receive queue */
1138 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_DIS_OP_MD);
1139
1140 for (i = 0; i < 0xffff; i++)
1141 if (sky2_read8(hw, RB_ADDR(rxqaddr[port], Q_RSL))
1142 == sky2_read8(hw, RB_ADDR(rxqaddr[port], Q_RL)))
1143 break;
1144
1145 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR),
1146 BMU_RST_SET | BMU_FIFO_RST);
1147 /* reset the Rx prefetch unit */
1148 sky2_write32(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_CTRL),
1149 PREF_UNIT_RST_SET);
1150
1151 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1152 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1153
1154 /* turn off led's */
1155 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1156
1157 sky2_tx_clean(sky2);
1158 sky2_rx_clean(sky2);
1159
1160 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1161 sky2->rx_le, sky2->rx_le_map);
1162 kfree(sky2->rx_ring);
1163
1164 pci_free_consistent(hw->pdev,
1165 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1166 sky2->tx_le, sky2->tx_le_map);
1167 kfree(sky2->tx_ring);
1168
1169 return 0;
1170}
1171
1172static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1173{
1174 if (!hw->copper)
1175 return SPEED_1000;
1176
1177 if (hw->chip_id == CHIP_ID_YUKON_FE)
1178 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1179
1180 switch (aux & PHY_M_PS_SPEED_MSK) {
1181 case PHY_M_PS_SPEED_1000:
1182 return SPEED_1000;
1183 case PHY_M_PS_SPEED_100:
1184 return SPEED_100;
1185 default:
1186 return SPEED_10;
1187 }
1188}
1189
1190static void sky2_link_up(struct sky2_port *sky2)
1191{
1192 struct sky2_hw *hw = sky2->hw;
1193 unsigned port = sky2->port;
1194 u16 reg;
1195
1196 /* disable Rx GMAC FIFO flush mode */
1197 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RX_F_FL_OFF);
1198
1199 /* Enable Transmit FIFO Underrun */
1200 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1201
1202 reg = gma_read16(hw, port, GM_GP_CTRL);
1203 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1204 reg |= GM_GPCR_DUP_FULL;
1205
1206 /* enable Rx/Tx */
1207 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1208 gma_write16(hw, port, GM_GP_CTRL, reg);
1209 gma_read16(hw, port, GM_GP_CTRL);
1210
1211 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1212
1213 netif_carrier_on(sky2->netdev);
1214 netif_wake_queue(sky2->netdev);
1215
1216 /* Turn on link LED */
1217 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1218 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1219
1220 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1221 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1222
1223 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1224 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1225 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1226 SPEED_10 ? 7 : 0) |
1227 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1228 SPEED_100 ? 7 : 0) |
1229 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1230 SPEED_1000 ? 7 : 0));
1231 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1232 }
1233
1234 if (netif_msg_link(sky2))
1235 printk(KERN_INFO PFX
1236 "%s: Link is up at %d Mbps, %s duplex, flowcontrol %s\n",
1237 sky2->netdev->name, sky2->speed,
1238 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1239 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1240 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1241}
1242
1243static void sky2_link_down(struct sky2_port *sky2)
1244{
1245 struct sky2_hw *hw = sky2->hw;
1246 unsigned port = sky2->port;
1247 u16 reg;
1248
1249 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1250
1251 reg = gma_read16(hw, port, GM_GP_CTRL);
1252 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1253 gma_write16(hw, port, GM_GP_CTRL, reg);
1254 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1255
1256 if (sky2->rx_pause && !sky2->tx_pause) {
1257 /* restore Asymmetric Pause bit */
1258 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1259 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1260 | PHY_M_AN_ASP);
1261 }
1262
1263 sky2_phy_reset(hw, port);
1264
1265 netif_carrier_off(sky2->netdev);
1266 netif_stop_queue(sky2->netdev);
1267
1268 /* Turn on link LED */
1269 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1270
1271 if (netif_msg_link(sky2))
1272 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1273 sky2_phy_init(hw, port);
1274}
1275
1276static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1277{
1278 struct sky2_hw *hw = sky2->hw;
1279 unsigned port = sky2->port;
1280 u16 lpa;
1281
1282 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1283
1284 if (lpa & PHY_M_AN_RF) {
1285 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1286 return -1;
1287 }
1288
1289 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1290 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1291 printk(KERN_ERR PFX "%s: master/slave fault",
1292 sky2->netdev->name);
1293 return -1;
1294 }
1295
1296 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1297 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1298 sky2->netdev->name);
1299 return -1;
1300 }
1301
1302 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1303
1304 sky2->speed = sky2_phy_speed(hw, aux);
1305
1306 /* Pause bits are offset (9..8) */
1307 if (hw->chip_id == CHIP_ID_YUKON_XL)
1308 aux >>= 6;
1309
1310 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1311 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1312
1313 if ((sky2->tx_pause || sky2->rx_pause)
1314 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1315 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1316 else
1317 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1318
1319 return 0;
1320}
1321
1322/*
1323 * Interrrupt from PHY are handled in tasklet (soft irq)
1324 * because accessing phy registers requires spin wait which might
1325 * cause excess interrupt latency.
1326 */
1327static void sky2_phy_task(unsigned long data)
1328{
1329 struct sky2_port *sky2 = (struct sky2_port *)data;
1330 struct sky2_hw *hw = sky2->hw;
1331 u16 istatus, phystat;
1332
1333 spin_lock(&hw->phy_lock);
1334 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1335 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1336
1337 if (netif_msg_intr(sky2))
1338 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1339 sky2->netdev->name, istatus, phystat);
1340
1341 if (istatus & PHY_M_IS_AN_COMPL) {
1342 if (sky2_autoneg_done(sky2, phystat) == 0)
1343 sky2_link_up(sky2);
1344 goto out;
1345 }
1346
1347 if (istatus & PHY_M_IS_LSP_CHANGE)
1348 sky2->speed = sky2_phy_speed(hw, phystat);
1349
1350 if (istatus & PHY_M_IS_DUP_CHANGE)
1351 sky2->duplex =
1352 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1353
1354 if (istatus & PHY_M_IS_LST_CHANGE) {
1355 if (phystat & PHY_M_PS_LINK_UP)
1356 sky2_link_up(sky2);
1357 else
1358 sky2_link_down(sky2);
1359 }
1360out:
1361 spin_unlock(&hw->phy_lock);
1362
1363 local_irq_disable();
1364 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1365 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1366 local_irq_enable();
1367}
1368
1369static void sky2_tx_timeout(struct net_device *dev)
1370{
1371 struct sky2_port *sky2 = netdev_priv(dev);
1372
1373 if (netif_msg_timer(sky2))
1374 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1375
1376 sky2_write32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR), BMU_STOP);
1377 sky2_read32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR));
1378
1379 sky2_tx_clean(sky2);
1380}
1381
1382static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1383{
1384 int err = 0;
1385
1386 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1387 return -EINVAL;
1388
1389 if (netif_running(dev))
1390 sky2_down(dev);
1391
1392 dev->mtu = new_mtu;
1393
1394 if (netif_running(dev))
1395 err = sky2_up(dev);
1396
1397 return err;
1398}
1399
1400/*
1401 * Receive one packet.
1402 * For small packets or errors, just reuse existing skb.
1403 * For larger pakects, get new buffer.
1404 */
1405static struct sk_buff *sky2_receive(struct sky2_hw *hw, unsigned port,
1406 u16 length, u32 status)
1407{
1408 struct net_device *dev = hw->dev[port];
1409 struct sky2_port *sky2 = netdev_priv(dev);
1410 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1411 struct sk_buff *skb, *nskb;
1412 const unsigned int rx_buf_size = dev->mtu + ETH_HLEN + 8;
1413
1414 if (unlikely(netif_msg_rx_status(sky2)))
1415 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1416 dev->name, sky2->rx_next, status, length);
1417
1418 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1419
1420 skb = NULL;
1421 if (!(status & GMR_FS_RX_OK)
1422 || (status & GMR_FS_ANY_ERR)
1423 || (length << 16) != (status & GMR_FS_LEN)
1424 || length > rx_buf_size)
1425 goto error;
1426
1427 if (length < RX_COPY_THRESHOLD) {
1428 nskb = sky2_rx_alloc(sky2, length, GFP_ATOMIC);
1429 if (!nskb)
1430 goto resubmit;
1431
1432 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1433 length, PCI_DMA_FROMDEVICE);
1434 memcpy(nskb->data, re->skb->data, length);
1435 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1436 length, PCI_DMA_FROMDEVICE);
1437 skb = nskb;
1438 } else {
1439 nskb = sky2_rx_alloc(sky2, rx_buf_size, GFP_ATOMIC);
1440 if (!nskb)
1441 goto resubmit;
1442
1443 skb = re->skb;
1444 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1445 re->maplen, PCI_DMA_FROMDEVICE);
1446 prefetch(skb->data);
1447
1448 re->skb = nskb;
1449 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1450 rx_buf_size, PCI_DMA_FROMDEVICE);
1451 re->maplen = rx_buf_size;
1452 }
1453
1454resubmit:
1455 BUG_ON(re->skb == skb);
1456 sky2_rx_add(sky2, re);
1457 return skb;
1458
1459error:
1460 if (status & GMR_FS_GOOD_FC)
1461 goto resubmit;
1462
1463 if (netif_msg_rx_err(sky2))
1464 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1465 sky2->netdev->name, status, length);
1466
1467 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1468 sky2->net_stats.rx_length_errors++;
1469 if (status & GMR_FS_FRAGMENT)
1470 sky2->net_stats.rx_frame_errors++;
1471 if (status & GMR_FS_CRC_ERR)
1472 sky2->net_stats.rx_crc_errors++;
1473 if (status & GMR_FS_RX_FF_OV)
1474 sky2->net_stats.rx_fifo_errors++;
1475 goto resubmit;
1476}
1477
1478/* Transmit ring index in reported status block is encoded as:
1479 *
1480 * | TXS2 | TXA2 | TXS1 | TXA1
1481 */
1482static inline u16 tx_index(u8 port, u32 status, u16 len)
1483{
1484 if (port == 0)
1485 return status & 0xfff;
1486 else
1487 return ((status >> 24) & 0xff) | (len & 0xf) << 8;
1488}
1489
1490/*
1491 * Both ports share the same status interrupt, therefore there is only
1492 * one poll routine.
1493 */
1494static int sky2_poll(struct net_device *dev, int *budget)
1495{
1496 struct sky2_port *sky2 = netdev_priv(dev);
1497 struct sky2_hw *hw = sky2->hw;
1498 unsigned int to_do = min(dev->quota, *budget);
1499 unsigned int work_done = 0;
1500 u16 hwidx;
1501 unsigned char summed[2] = { CHECKSUM_NONE, CHECKSUM_NONE };
1502 unsigned int csum[2];
1503
1504 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1505 rmb();
1506 while (hw->st_idx != hwidx && work_done < to_do) {
1507 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1508 struct sk_buff *skb;
1509 u8 port;
1510 u32 status;
1511 u16 length;
1512
1513 status = le32_to_cpu(le->status);
1514 length = le16_to_cpu(le->length);
1515 port = le->link;
1516
1517 BUG_ON(port >= hw->ports || hw->dev[port] == NULL);
1518
1519 switch (le->opcode & ~HW_OWNER) {
1520 case OP_RXSTAT:
1521 skb = sky2_receive(hw, port, length, status);
1522 if (likely(skb)) {
1523 __skb_put(skb, length);
1524 skb->protocol = eth_type_trans(skb, dev);
1525
1526 /* Add hw checksum if available */
1527 skb->ip_summed = summed[port];
1528 skb->csum = csum[port];
1529
1530 /* Clear for next packet */
1531 csum[port] = 0;
1532 summed[port] = CHECKSUM_NONE;
1533
1534 netif_receive_skb(skb);
1535
1536 dev->last_rx = jiffies;
1537 ++work_done;
1538 }
1539 break;
1540
1541 case OP_RXCHKS:
1542 /* Save computed checksum for next rx */
1543 csum[port] = le16_to_cpu(status & 0xffff);
1544 summed[port] = CHECKSUM_HW;
1545 break;
1546
1547 case OP_TXINDEXLE:
1548 sky2_tx_complete(hw->dev[port],
1549 tx_index(port, status, length));
1550 break;
1551
1552 case OP_RXTIMESTAMP:
1553 break;
1554
1555 default:
1556 if (net_ratelimit())
1557 printk(KERN_WARNING PFX
1558 "unknown status opcode 0x%x\n",
1559 le->opcode);
1560 break;
1561 }
1562
1563 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1564 if (hw->st_idx == hwidx) {
1565 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1566 rmb();
1567 }
1568 }
1569
1570 mmiowb();
1571
1572 if (hw->dev[0])
1573 rx_set_put(hw->dev[0]);
1574
1575 if (hw->dev[1])
1576 rx_set_put(hw->dev[1]);
1577
1578 *budget -= work_done;
1579 dev->quota -= work_done;
1580 if (work_done < to_do) {
1581 /*
1582 * Another chip workaround, need to restart TX timer if status
1583 * LE was handled. WA_DEV_43_418
1584 */
1585 if (is_ec_a1(hw)) {
1586 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1587 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1588 }
1589
1590 hw->intr_mask |= Y2_IS_STAT_BMU;
1591 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1592 sky2_read32(hw, B0_IMSK);
1593 netif_rx_complete(dev);
1594 }
1595
1596 return work_done >= to_do;
1597
1598}
1599
1600static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1601{
1602 struct net_device *dev = hw->dev[port];
1603
1604 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1605 dev->name, status);
1606
1607 if (status & Y2_IS_PAR_RD1) {
1608 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1609 dev->name);
1610 /* Clear IRQ */
1611 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1612 }
1613
1614 if (status & Y2_IS_PAR_WR1) {
1615 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1616 dev->name);
1617
1618 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1619 }
1620
1621 if (status & Y2_IS_PAR_MAC1) {
1622 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1623 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1624 }
1625
1626 if (status & Y2_IS_PAR_RX1) {
1627 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1628 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1629 }
1630
1631 if (status & Y2_IS_TCP_TXA1) {
1632 printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1633 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1634 }
1635}
1636
1637static void sky2_hw_intr(struct sky2_hw *hw)
1638{
1639 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1640
1641 if (status & Y2_IS_TIST_OV)
1642 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1643
1644 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
1645 u16 pci_err;
1646
1647 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
1648 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1649 pci_name(hw->pdev), pci_err);
1650
1651 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1652 pci_write_config_word(hw->pdev, PCI_STATUS,
1653 pci_err | PCI_STATUS_ERROR_BITS);
1654 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1655 }
1656
1657 if (status & Y2_IS_PCI_EXP) {
1658 /* PCI-Express uncorrectable Error occured */
1659 u32 pex_err;
1660
1661 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
1662
1663 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1664 pci_name(hw->pdev), pex_err);
1665
1666 /* clear the interrupt */
1667 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1668 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1669 0xffffffffUL);
1670 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1671
1672 if (pex_err & PEX_FATAL_ERRORS) {
1673 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1674 hwmsk &= ~Y2_IS_PCI_EXP;
1675 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1676 }
1677 }
1678
1679 if (status & Y2_HWE_L1_MASK)
1680 sky2_hw_error(hw, 0, status);
1681 status >>= 8;
1682 if (status & Y2_HWE_L1_MASK)
1683 sky2_hw_error(hw, 1, status);
1684}
1685
1686static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1687{
1688 struct net_device *dev = hw->dev[port];
1689 struct sky2_port *sky2 = netdev_priv(dev);
1690 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1691
1692 if (netif_msg_intr(sky2))
1693 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
1694 dev->name, status);
1695
1696 if (status & GM_IS_RX_FF_OR) {
1697 ++sky2->net_stats.rx_fifo_errors;
1698 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1699 }
1700
1701 if (status & GM_IS_TX_FF_UR) {
1702 ++sky2->net_stats.tx_fifo_errors;
1703 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1704 }
1705}
1706
1707static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1708{
1709 struct net_device *dev = hw->dev[port];
1710 struct sky2_port *sky2 = netdev_priv(dev);
1711
1712 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1713 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1714 tasklet_schedule(&sky2->phy_task);
1715}
1716
1717static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
1718{
1719 struct sky2_hw *hw = dev_id;
1720 u32 status;
1721
1722 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
1723 if (status == 0 || status == ~0)
1724 return IRQ_NONE;
1725
1726 if (status & Y2_IS_HW_ERR)
1727 sky2_hw_intr(hw);
1728
1729 /* Do NAPI for Rx and Tx status */
1730 if ((status & Y2_IS_STAT_BMU) && netif_rx_schedule_test(hw->dev[0])) {
1731 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1732
1733 hw->intr_mask &= ~Y2_IS_STAT_BMU;
1734 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1735 __netif_rx_schedule(hw->dev[0]);
1736 }
1737
1738 if (status & Y2_IS_IRQ_PHY1)
1739 sky2_phy_intr(hw, 0);
1740
1741 if (status & Y2_IS_IRQ_PHY2)
1742 sky2_phy_intr(hw, 1);
1743
1744 if (status & Y2_IS_IRQ_MAC1)
1745 sky2_mac_intr(hw, 0);
1746
1747 if (status & Y2_IS_IRQ_MAC2)
1748 sky2_mac_intr(hw, 1);
1749
1750 sky2_write32(hw, B0_Y2_SP_ICR, 2);
1751
1752 sky2_read32(hw, B0_IMSK);
1753
1754 return IRQ_HANDLED;
1755}
1756
1757#ifdef CONFIG_NET_POLL_CONTROLLER
1758static void sky2_netpoll(struct net_device *dev)
1759{
1760 struct sky2_port *sky2 = netdev_priv(dev);
1761
1762 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
1763}
1764#endif
1765
1766/* Chip internal frequency for clock calculations */
1767static inline u32 sky2_khz(const struct sky2_hw *hw)
1768{
1769 switch (hw->chip_id) {
1770 case CHIP_ID_YUKON_EC:
1771 return 125000; /* 125 Mhz */
1772 case CHIP_ID_YUKON_FE:
1773 return 100000; /* 100 Mhz */
1774 default: /* YUKON_XL */
1775 return 156000; /* 156 Mhz */
1776 }
1777}
1778
1779static inline u32 sky2_ms2clk(const struct sky2_hw *hw, u32 ms)
1780{
1781 return sky2_khz(hw) * ms;
1782}
1783
1784static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
1785{
1786 return (sky2_khz(hw) * us) / 1000;
1787}
1788
1789static int sky2_reset(struct sky2_hw *hw)
1790{
1791 u32 ctst, power;
1792 u16 status;
1793 u8 t8, pmd_type;
1794 int i;
1795
1796 ctst = sky2_read32(hw, B0_CTST);
1797
1798 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1799 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
1800 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
1801 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
1802 pci_name(hw->pdev), hw->chip_id);
1803 return -EOPNOTSUPP;
1804 }
1805
1806 /* ring for status responses */
1807 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
1808 &hw->st_dma);
1809 if (!hw->st_le)
1810 return -ENOMEM;
1811
1812 /* disable ASF */
1813 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
1814 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1815 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
1816 }
1817
1818 /* do a SW reset */
1819 sky2_write8(hw, B0_CTST, CS_RST_SET);
1820 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1821
1822 /* clear PCI errors, if any */
1823 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
1824 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1825 pci_write_config_word(hw->pdev, PCI_STATUS,
1826 status | PCI_STATUS_ERROR_BITS);
1827
1828 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
1829
1830 /* clear any PEX errors */
1831 if (is_pciex(hw)) {
1832 u16 lstat;
1833 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1834 0xffffffffUL);
1835 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
1836 }
1837
1838 pmd_type = sky2_read8(hw, B2_PMD_TYP);
1839 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
1840
1841 hw->ports = 1;
1842 t8 = sky2_read8(hw, B2_Y2_HW_RES);
1843 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
1844 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
1845 ++hw->ports;
1846 }
1847 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
1848
1849 /* switch power to VCC (WA for VAUX problem) */
1850 sky2_write8(hw, B0_POWER_CTRL,
1851 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
1852
1853 /* disable Core Clock Division, */
1854 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
1855
1856 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
1857 /* enable bits are inverted */
1858 sky2_write8(hw, B2_Y2_CLK_GATE,
1859 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1860 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1861 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
1862 else
1863 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
1864
1865 /* Turn off phy power saving */
1866 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &power);
1867 power &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
1868
1869 /* looks like this xl is back asswards .. */
1870 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
1871 power |= PCI_Y2_PHY1_COMA;
1872 if (hw->ports > 1)
1873 power |= PCI_Y2_PHY2_COMA;
1874 }
1875 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, power);
1876
1877 for (i = 0; i < hw->ports; i++) {
1878 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
1879 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
1880 }
1881
1882 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1883
1884 /* Clear I2C IRQ noise */
1885 sky2_write32(hw, B2_I2C_IRQ, 1);
1886
1887 /* turn off hardware timer (unused) */
1888 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
1889 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
1890
1891 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
1892
1893 /* Turn on descriptor polling (every 75us) */
1894 sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75));
1895 sky2_write8(hw, B28_DPT_CTRL, DPT_START);
1896
1897 /* Turn off receive timestamp */
1898 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
1899 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1900
1901 /* enable the Tx Arbiters */
1902 for (i = 0; i < hw->ports; i++)
1903 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
1904
1905 /* Initialize ram interface */
1906 for (i = 0; i < hw->ports; i++) {
1907 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
1908
1909 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
1910 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
1911 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
1912 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
1913 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
1914 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
1915 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
1916 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
1917 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
1918 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
1919 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
1920 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
1921 }
1922
1923 if (is_pciex(hw)) {
1924 u16 pctrl;
1925
1926 /* change Max. Read Request Size to 2048 bytes */
1927 pci_read_config_word(hw->pdev, PEX_DEV_CTRL, &pctrl);
1928 pctrl &= ~PEX_DC_MAX_RRS_MSK;
1929 pctrl |= PEX_DC_MAX_RD_RQ_SIZE(4);
1930
1931
1932 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1933 pci_write_config_word(hw->pdev, PEX_DEV_CTRL, pctrl);
1934 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1935 }
1936
1937 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
1938
1939 spin_lock_bh(&hw->phy_lock);
1940 for (i = 0; i < hw->ports; i++)
1941 sky2_phy_reset(hw, i);
1942 spin_unlock_bh(&hw->phy_lock);
1943
1944 memset(hw->st_le, 0, STATUS_LE_BYTES);
1945 hw->st_idx = 0;
1946
1947 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
1948 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
1949
1950 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
1951 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
1952
1953 /* Set the list last index */
1954 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
1955
1956 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_ms2clk(hw, 10));
1957
1958 /* These status setup values are copied from SysKonnect's driver */
1959 if (is_ec_a1(hw)) {
1960 /* WA for dev. #4.3 */
1961 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
1962
1963 /* set Status-FIFO watermark */
1964 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
1965
1966 /* set Status-FIFO ISR watermark */
1967 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
1968
1969 } else {
1970 sky2_write16(hw, STAT_TX_IDX_TH, 0x000a);
1971
1972 /* set Status-FIFO watermark */
1973 sky2_write8(hw, STAT_FIFO_WM, 0x10);
1974
1975 /* set Status-FIFO ISR watermark */
1976 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
1977 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);
1978
1979 else /* WA 4109 */
1980 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);
1981
1982 sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);
1983 }
1984
1985 /* enable status unit */
1986 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
1987
1988 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1989 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
1990 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
1991
1992 return 0;
1993}
1994
1995static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
1996{
1997 u32 modes;
1998 if (hw->copper) {
1999 modes = SUPPORTED_10baseT_Half
2000 | SUPPORTED_10baseT_Full
2001 | SUPPORTED_100baseT_Half
2002 | SUPPORTED_100baseT_Full
2003 | SUPPORTED_Autoneg | SUPPORTED_TP;
2004
2005 if (hw->chip_id != CHIP_ID_YUKON_FE)
2006 modes |= SUPPORTED_1000baseT_Half
2007 | SUPPORTED_1000baseT_Full;
2008 } else
2009 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2010 | SUPPORTED_Autoneg;
2011 return modes;
2012}
2013
2014static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2015{
2016 struct sky2_port *sky2 = netdev_priv(dev);
2017 struct sky2_hw *hw = sky2->hw;
2018
2019 ecmd->transceiver = XCVR_INTERNAL;
2020 ecmd->supported = sky2_supported_modes(hw);
2021 ecmd->phy_address = PHY_ADDR_MARV;
2022 if (hw->copper) {
2023 ecmd->supported = SUPPORTED_10baseT_Half
2024 | SUPPORTED_10baseT_Full
2025 | SUPPORTED_100baseT_Half
2026 | SUPPORTED_100baseT_Full
2027 | SUPPORTED_1000baseT_Half
2028 | SUPPORTED_1000baseT_Full
2029 | SUPPORTED_Autoneg | SUPPORTED_TP;
2030 ecmd->port = PORT_TP;
2031 } else
2032 ecmd->port = PORT_FIBRE;
2033
2034 ecmd->advertising = sky2->advertising;
2035 ecmd->autoneg = sky2->autoneg;
2036 ecmd->speed = sky2->speed;
2037 ecmd->duplex = sky2->duplex;
2038 return 0;
2039}
2040
2041static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2042{
2043 struct sky2_port *sky2 = netdev_priv(dev);
2044 const struct sky2_hw *hw = sky2->hw;
2045 u32 supported = sky2_supported_modes(hw);
2046
2047 if (ecmd->autoneg == AUTONEG_ENABLE) {
2048 ecmd->advertising = supported;
2049 sky2->duplex = -1;
2050 sky2->speed = -1;
2051 } else {
2052 u32 setting;
2053
2054 switch (ecmd->speed) {
2055 case SPEED_1000:
2056 if (ecmd->duplex == DUPLEX_FULL)
2057 setting = SUPPORTED_1000baseT_Full;
2058 else if (ecmd->duplex == DUPLEX_HALF)
2059 setting = SUPPORTED_1000baseT_Half;
2060 else
2061 return -EINVAL;
2062 break;
2063 case SPEED_100:
2064 if (ecmd->duplex == DUPLEX_FULL)
2065 setting = SUPPORTED_100baseT_Full;
2066 else if (ecmd->duplex == DUPLEX_HALF)
2067 setting = SUPPORTED_100baseT_Half;
2068 else
2069 return -EINVAL;
2070 break;
2071
2072 case SPEED_10:
2073 if (ecmd->duplex == DUPLEX_FULL)
2074 setting = SUPPORTED_10baseT_Full;
2075 else if (ecmd->duplex == DUPLEX_HALF)
2076 setting = SUPPORTED_10baseT_Half;
2077 else
2078 return -EINVAL;
2079 break;
2080 default:
2081 return -EINVAL;
2082 }
2083
2084 if ((setting & supported) == 0)
2085 return -EINVAL;
2086
2087 sky2->speed = ecmd->speed;
2088 sky2->duplex = ecmd->duplex;
2089 }
2090
2091 sky2->autoneg = ecmd->autoneg;
2092 sky2->advertising = ecmd->advertising;
2093
2094 if (netif_running(dev)) {
2095 sky2_down(dev);
2096 sky2_up(dev);
2097 }
2098
2099 return 0;
2100}
2101
2102static void sky2_get_drvinfo(struct net_device *dev,
2103 struct ethtool_drvinfo *info)
2104{
2105 struct sky2_port *sky2 = netdev_priv(dev);
2106
2107 strcpy(info->driver, DRV_NAME);
2108 strcpy(info->version, DRV_VERSION);
2109 strcpy(info->fw_version, "N/A");
2110 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2111}
2112
2113static const struct sky2_stat {
2114 char name[ETH_GSTRING_LEN];
2115 u16 offset;
2116} sky2_stats[] = {
2117 { "tx_bytes", GM_TXO_OK_HI },
2118 { "rx_bytes", GM_RXO_OK_HI },
2119 { "tx_broadcast", GM_TXF_BC_OK },
2120 { "rx_broadcast", GM_RXF_BC_OK },
2121 { "tx_multicast", GM_TXF_MC_OK },
2122 { "rx_multicast", GM_RXF_MC_OK },
2123 { "tx_unicast", GM_TXF_UC_OK },
2124 { "rx_unicast", GM_RXF_UC_OK },
2125 { "tx_mac_pause", GM_TXF_MPAUSE },
2126 { "rx_mac_pause", GM_RXF_MPAUSE },
2127 { "collisions", GM_TXF_SNG_COL },
2128 { "late_collision",GM_TXF_LAT_COL },
2129 { "aborted", GM_TXF_ABO_COL },
2130 { "multi_collisions", GM_TXF_MUL_COL },
2131 { "fifo_underrun", GM_TXE_FIFO_UR },
2132 { "fifo_overflow", GM_RXE_FIFO_OV },
2133 { "rx_toolong", GM_RXF_LNG_ERR },
2134 { "rx_jabber", GM_RXF_JAB_PKT },
2135 { "rx_runt", GM_RXE_FRAG },
2136 { "rx_too_long", GM_RXF_LNG_ERR },
2137 { "rx_fcs_error", GM_RXF_FCS_ERR },
2138};
2139
2140static u32 sky2_get_rx_csum(struct net_device *dev)
2141{
2142 struct sky2_port *sky2 = netdev_priv(dev);
2143
2144 return sky2->rx_csum;
2145}
2146
2147static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2148{
2149 struct sky2_port *sky2 = netdev_priv(dev);
2150
2151 sky2->rx_csum = data;
2152
2153 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2154 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2155
2156 return 0;
2157}
2158
2159static u32 sky2_get_msglevel(struct net_device *netdev)
2160{
2161 struct sky2_port *sky2 = netdev_priv(netdev);
2162 return sky2->msg_enable;
2163}
2164
2165static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2166{
2167 struct sky2_hw *hw = sky2->hw;
2168 unsigned port = sky2->port;
2169 int i;
2170
2171 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2172 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2173 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2174 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2175
2176 for (i = 2; i < count; i++)
2177 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2178}
2179
2180static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2181{
2182 struct sky2_port *sky2 = netdev_priv(netdev);
2183 sky2->msg_enable = value;
2184}
2185
2186static int sky2_get_stats_count(struct net_device *dev)
2187{
2188 return ARRAY_SIZE(sky2_stats);
2189}
2190
2191static void sky2_get_ethtool_stats(struct net_device *dev,
2192 struct ethtool_stats *stats, u64 * data)
2193{
2194 struct sky2_port *sky2 = netdev_priv(dev);
2195
2196 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2197}
2198
2199static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2200{
2201 int i;
2202
2203 switch (stringset) {
2204 case ETH_SS_STATS:
2205 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2206 memcpy(data + i * ETH_GSTRING_LEN,
2207 sky2_stats[i].name, ETH_GSTRING_LEN);
2208 break;
2209 }
2210}
2211
2212/* Use hardware MIB variables for critical path statistics and
2213 * transmit feedback not reported at interrupt.
2214 * Other errors are accounted for in interrupt handler.
2215 */
2216static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2217{
2218 struct sky2_port *sky2 = netdev_priv(dev);
2219 u64 data[13];
2220
2221 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2222
2223 sky2->net_stats.tx_bytes = data[0];
2224 sky2->net_stats.rx_bytes = data[1];
2225 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2226 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2227 sky2->net_stats.multicast = data[5] + data[7];
2228 sky2->net_stats.collisions = data[10];
2229 sky2->net_stats.tx_aborted_errors = data[12];
2230
2231 return &sky2->net_stats;
2232}
2233
2234static int sky2_set_mac_address(struct net_device *dev, void *p)
2235{
2236 struct sky2_port *sky2 = netdev_priv(dev);
2237 struct sockaddr *addr = p;
2238 int err = 0;
2239
2240 if (!is_valid_ether_addr(addr->sa_data))
2241 return -EADDRNOTAVAIL;
2242
2243 sky2_down(dev);
2244 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2245 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
2246 dev->dev_addr, ETH_ALEN);
2247 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
2248 dev->dev_addr, ETH_ALEN);
2249 if (dev->flags & IFF_UP)
2250 err = sky2_up(dev);
2251 return err;
2252}
2253
2254static void sky2_set_multicast(struct net_device *dev)
2255{
2256 struct sky2_port *sky2 = netdev_priv(dev);
2257 struct sky2_hw *hw = sky2->hw;
2258 unsigned port = sky2->port;
2259 struct dev_mc_list *list = dev->mc_list;
2260 u16 reg;
2261 u8 filter[8];
2262
2263 memset(filter, 0, sizeof(filter));
2264
2265 reg = gma_read16(hw, port, GM_RX_CTRL);
2266 reg |= GM_RXCR_UCF_ENA;
2267
2268 if (dev->flags & IFF_PROMISC) /* promiscious */
2269 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2270 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2271 memset(filter, 0xff, sizeof(filter));
2272 else if (dev->mc_count == 0) /* no multicast */
2273 reg &= ~GM_RXCR_MCF_ENA;
2274 else {
2275 int i;
2276 reg |= GM_RXCR_MCF_ENA;
2277
2278 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2279 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2280 filter[bit / 8] |= 1 << (bit % 8);
2281 }
2282 }
2283
2284 gma_write16(hw, port, GM_MC_ADDR_H1,
2285 (u16) filter[0] | ((u16) filter[1] << 8));
2286 gma_write16(hw, port, GM_MC_ADDR_H2,
2287 (u16) filter[2] | ((u16) filter[3] << 8));
2288 gma_write16(hw, port, GM_MC_ADDR_H3,
2289 (u16) filter[4] | ((u16) filter[5] << 8));
2290 gma_write16(hw, port, GM_MC_ADDR_H4,
2291 (u16) filter[6] | ((u16) filter[7] << 8));
2292
2293 gma_write16(hw, port, GM_RX_CTRL, reg);
2294}
2295
2296/* Can have one global because blinking is controlled by
2297 * ethtool and that is always under RTNL mutex
2298 */
2299static inline void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2300{
2301 u16 pg;
2302
2303 spin_lock_bh(&hw->phy_lock);
2304 switch (hw->chip_id) {
2305 case CHIP_ID_YUKON_XL:
2306 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2307 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2308 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2309 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2310 PHY_M_LEDC_INIT_CTRL(7) |
2311 PHY_M_LEDC_STA1_CTRL(7) |
2312 PHY_M_LEDC_STA0_CTRL(7))
2313 : 0);
2314
2315 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2316 break;
2317
2318 default:
2319 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2320 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2321 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2322 PHY_M_LED_MO_10(MO_LED_ON) |
2323 PHY_M_LED_MO_100(MO_LED_ON) |
2324 PHY_M_LED_MO_1000(MO_LED_ON) |
2325 PHY_M_LED_MO_RX(MO_LED_ON)
2326 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2327 PHY_M_LED_MO_10(MO_LED_OFF) |
2328 PHY_M_LED_MO_100(MO_LED_OFF) |
2329 PHY_M_LED_MO_1000(MO_LED_OFF) |
2330 PHY_M_LED_MO_RX(MO_LED_OFF));
2331
2332 }
2333 spin_unlock_bh(&hw->phy_lock);
2334}
2335
2336/* blink LED's for finding board */
2337static int sky2_phys_id(struct net_device *dev, u32 data)
2338{
2339 struct sky2_port *sky2 = netdev_priv(dev);
2340 struct sky2_hw *hw = sky2->hw;
2341 unsigned port = sky2->port;
2342 u16 ledctrl, ledover = 0;
2343 long ms;
2344 int onoff = 1;
2345
2346 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2347 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2348 else
2349 ms = data * 1000;
2350
2351 /* save initial values */
2352 spin_lock_bh(&hw->phy_lock);
2353 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2354 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2355 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2356 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2357 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2358 } else {
2359 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2360 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2361 }
2362 spin_unlock_bh(&hw->phy_lock);
2363
2364 while (ms > 0) {
2365 sky2_led(hw, port, onoff);
2366 onoff = !onoff;
2367
2368 if (msleep_interruptible(250))
2369 break; /* interrupted */
2370 ms -= 250;
2371 }
2372
2373 /* resume regularly scheduled programming */
2374 spin_lock_bh(&hw->phy_lock);
2375 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2376 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2377 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2378 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2379 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2380 } else {
2381 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2382 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2383 }
2384 spin_unlock_bh(&hw->phy_lock);
2385
2386 return 0;
2387}
2388
2389static void sky2_get_pauseparam(struct net_device *dev,
2390 struct ethtool_pauseparam *ecmd)
2391{
2392 struct sky2_port *sky2 = netdev_priv(dev);
2393
2394 ecmd->tx_pause = sky2->tx_pause;
2395 ecmd->rx_pause = sky2->rx_pause;
2396 ecmd->autoneg = sky2->autoneg;
2397}
2398
2399static int sky2_set_pauseparam(struct net_device *dev,
2400 struct ethtool_pauseparam *ecmd)
2401{
2402 struct sky2_port *sky2 = netdev_priv(dev);
2403 int err = 0;
2404
2405 sky2->autoneg = ecmd->autoneg;
2406 sky2->tx_pause = ecmd->tx_pause != 0;
2407 sky2->rx_pause = ecmd->rx_pause != 0;
2408
2409 if (netif_running(dev)) {
2410 sky2_down(dev);
2411 err = sky2_up(dev);
2412 }
2413
2414 return err;
2415}
2416
2417#ifdef CONFIG_PM
2418static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2419{
2420 struct sky2_port *sky2 = netdev_priv(dev);
2421
2422 wol->supported = WAKE_MAGIC;
2423 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2424}
2425
2426static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2427{
2428 struct sky2_port *sky2 = netdev_priv(dev);
2429 struct sky2_hw *hw = sky2->hw;
2430
2431 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2432 return -EOPNOTSUPP;
2433
2434 sky2->wol = wol->wolopts == WAKE_MAGIC;
2435
2436 if (sky2->wol) {
2437 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2438
2439 sky2_write16(hw, WOL_CTRL_STAT,
2440 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2441 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2442 } else
2443 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2444
2445 return 0;
2446}
2447#endif
2448
2449static void sky2_get_ringparam(struct net_device *dev,
2450 struct ethtool_ringparam *ering)
2451{
2452 struct sky2_port *sky2 = netdev_priv(dev);
2453
2454 ering->rx_max_pending = RX_MAX_PENDING;
2455 ering->rx_mini_max_pending = 0;
2456 ering->rx_jumbo_max_pending = 0;
2457 ering->tx_max_pending = TX_RING_SIZE - 1;
2458
2459 ering->rx_pending = sky2->rx_pending;
2460 ering->rx_mini_pending = 0;
2461 ering->rx_jumbo_pending = 0;
2462 ering->tx_pending = sky2->tx_pending;
2463}
2464
2465static int sky2_set_ringparam(struct net_device *dev,
2466 struct ethtool_ringparam *ering)
2467{
2468 struct sky2_port *sky2 = netdev_priv(dev);
2469 int err = 0;
2470
2471 if (ering->rx_pending > RX_MAX_PENDING ||
2472 ering->rx_pending < 8 ||
2473 ering->tx_pending < MAX_SKB_TX_LE ||
2474 ering->tx_pending > TX_RING_SIZE - 1)
2475 return -EINVAL;
2476
2477 if (netif_running(dev))
2478 sky2_down(dev);
2479
2480 sky2->rx_pending = ering->rx_pending;
2481 sky2->tx_pending = ering->tx_pending;
2482
2483 if (netif_running(dev))
2484 err = sky2_up(dev);
2485
2486 return err;
2487}
2488
2489#define SKY2_REGS_LEN 0x1000
2490static int sky2_get_regs_len(struct net_device *dev)
2491{
2492 return SKY2_REGS_LEN;
2493}
2494
2495/*
2496 * Returns copy of control register region
2497 * I/O region is divided into banks and certain regions are unreadable
2498 */
2499static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2500 void *p)
2501{
2502 const struct sky2_port *sky2 = netdev_priv(dev);
2503 unsigned long offs;
2504 const void __iomem *io = sky2->hw->regs;
2505 static const unsigned long bankmap = 0xfff3f305;
2506
2507 regs->version = 1;
2508 for (offs = 0; offs < regs->len; offs += 128) {
2509 u32 len = min_t(u32, 128, regs->len - offs);
2510
2511 if (bankmap & (1 << (offs / 128)))
2512 memcpy_fromio(p + offs, io + offs, len);
2513 else
2514 memset(p + offs, 0, len);
2515 }
2516}
2517
2518static struct ethtool_ops sky2_ethtool_ops = {
2519 .get_settings = sky2_get_settings,
2520 .set_settings = sky2_set_settings,
2521 .get_drvinfo = sky2_get_drvinfo,
2522 .get_msglevel = sky2_get_msglevel,
2523 .set_msglevel = sky2_set_msglevel,
2524 .get_regs_len = sky2_get_regs_len,
2525 .get_regs = sky2_get_regs,
2526 .get_link = ethtool_op_get_link,
2527 .get_sg = ethtool_op_get_sg,
2528 .set_sg = ethtool_op_set_sg,
2529 .get_tx_csum = ethtool_op_get_tx_csum,
2530 .set_tx_csum = ethtool_op_set_tx_csum,
2531 .get_tso = ethtool_op_get_tso,
2532 .set_tso = ethtool_op_set_tso,
2533 .get_rx_csum = sky2_get_rx_csum,
2534 .set_rx_csum = sky2_set_rx_csum,
2535 .get_strings = sky2_get_strings,
2536 .get_ringparam = sky2_get_ringparam,
2537 .set_ringparam = sky2_set_ringparam,
2538 .get_pauseparam = sky2_get_pauseparam,
2539 .set_pauseparam = sky2_set_pauseparam,
2540#ifdef CONFIG_PM
2541 .get_wol = sky2_get_wol,
2542 .set_wol = sky2_set_wol,
2543#endif
2544 .phys_id = sky2_phys_id,
2545 .get_stats_count = sky2_get_stats_count,
2546 .get_ethtool_stats = sky2_get_ethtool_stats,
2547};
2548
2549/* Initialize network device */
2550static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2551 unsigned port, int highmem)
2552{
2553 struct sky2_port *sky2;
2554 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2555
2556 if (!dev) {
2557 printk(KERN_ERR "sky2 etherdev alloc failed");
2558 return NULL;
2559 }
2560
2561 SET_MODULE_OWNER(dev);
2562 SET_NETDEV_DEV(dev, &hw->pdev->dev);
2563 dev->open = sky2_up;
2564 dev->stop = sky2_down;
2565 dev->hard_start_xmit = sky2_xmit_frame;
2566 dev->get_stats = sky2_get_stats;
2567 dev->set_multicast_list = sky2_set_multicast;
2568 dev->set_mac_address = sky2_set_mac_address;
2569 dev->change_mtu = sky2_change_mtu;
2570 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2571 dev->tx_timeout = sky2_tx_timeout;
2572 dev->watchdog_timeo = TX_WATCHDOG;
2573 if (port == 0)
2574 dev->poll = sky2_poll;
2575 dev->weight = NAPI_WEIGHT;
2576#ifdef CONFIG_NET_POLL_CONTROLLER
2577 dev->poll_controller = sky2_netpoll;
2578#endif
2579
2580 sky2 = netdev_priv(dev);
2581 sky2->netdev = dev;
2582 sky2->hw = hw;
2583 sky2->msg_enable = netif_msg_init(debug, default_msg);
2584
2585 spin_lock_init(&sky2->tx_lock);
2586 /* Auto speed and flow control */
2587 sky2->autoneg = AUTONEG_ENABLE;
2588 sky2->tx_pause = 0;
2589 sky2->rx_pause = 1;
2590 sky2->duplex = -1;
2591 sky2->speed = -1;
2592 sky2->advertising = sky2_supported_modes(hw);
2593 sky2->rx_csum = 1;
2594 tasklet_init(&sky2->phy_task, sky2_phy_task, (unsigned long)sky2);
2595 sky2->tx_pending = TX_DEF_PENDING;
2596 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
2597
2598 hw->dev[port] = dev;
2599
2600 sky2->port = port;
2601
2602 dev->features |= NETIF_F_LLTX | NETIF_F_TSO;
2603 if (highmem)
2604 dev->features |= NETIF_F_HIGHDMA;
2605 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
2606
2607 /* read the mac address */
2608 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2609
2610 /* device is off until link detection */
2611 netif_carrier_off(dev);
2612 netif_stop_queue(dev);
2613
2614 return dev;
2615}
2616
2617static inline void sky2_show_addr(struct net_device *dev)
2618{
2619 const struct sky2_port *sky2 = netdev_priv(dev);
2620
2621 if (netif_msg_probe(sky2))
2622 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
2623 dev->name,
2624 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2625 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2626}
2627
2628static int __devinit sky2_probe(struct pci_dev *pdev,
2629 const struct pci_device_id *ent)
2630{
2631 struct net_device *dev, *dev1 = NULL;
2632 struct sky2_hw *hw;
2633 int err, using_dac = 0;
2634
2635 err = pci_enable_device(pdev);
2636 if (err) {
2637 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
2638 pci_name(pdev));
2639 goto err_out;
2640 }
2641
2642 err = pci_request_regions(pdev, DRV_NAME);
2643 if (err) {
2644 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
2645 pci_name(pdev));
2646 goto err_out;
2647 }
2648
2649 pci_set_master(pdev);
2650
2651 if (sizeof(dma_addr_t) > sizeof(u32)) {
2652 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2653 if (!err)
2654 using_dac = 1;
2655 }
2656
2657 if (!using_dac) {
2658 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2659 if (err) {
2660 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
2661 pci_name(pdev));
2662 goto err_out_free_regions;
2663 }
2664 }
2665#ifdef __BIG_ENDIAN
2666 /* byte swap decriptors in hardware */
2667 {
2668 u32 reg;
2669
2670 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
2671 reg |= PCI_REV_DESC;
2672 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
2673 }
2674#endif
2675
2676 err = -ENOMEM;
2677 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
2678 if (!hw) {
2679 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
2680 pci_name(pdev));
2681 goto err_out_free_regions;
2682 }
2683
2684 memset(hw, 0, sizeof(*hw));
2685 hw->pdev = pdev;
2686 spin_lock_init(&hw->phy_lock);
2687
2688 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
2689 if (!hw->regs) {
2690 printk(KERN_ERR PFX "%s: cannot map device registers\n",
2691 pci_name(pdev));
2692 goto err_out_free_hw;
2693 }
2694
2695 err = sky2_reset(hw);
2696 if (err)
2697 goto err_out_iounmap;
2698
2699 printk(KERN_INFO PFX "addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
2700 pci_resource_start(pdev, 0), pdev->irq,
2701 yukon_name[hw->chip_id - CHIP_ID_YUKON],
2702 hw->chip_id, hw->chip_rev);
2703
2704 dev = sky2_init_netdev(hw, 0, using_dac);
2705 if (!dev)
2706 goto err_out_free_pci;
2707
2708 err = register_netdev(dev);
2709 if (err) {
2710 printk(KERN_ERR PFX "%s: cannot register net device\n",
2711 pci_name(pdev));
2712 goto err_out_free_netdev;
2713 }
2714
2715 sky2_show_addr(dev);
2716
2717 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
2718 if (register_netdev(dev1) == 0)
2719 sky2_show_addr(dev1);
2720 else {
2721 /* Failure to register second port need not be fatal */
2722 printk(KERN_WARNING PFX
2723 "register of second port failed\n");
2724 hw->dev[1] = NULL;
2725 free_netdev(dev1);
2726 }
2727 }
2728
2729 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
2730 if (err) {
2731 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
2732 pci_name(pdev), pdev->irq);
2733 goto err_out_unregister;
2734 }
2735
2736 hw->intr_mask = Y2_IS_BASE;
2737 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2738
2739 pci_set_drvdata(pdev, hw);
2740
2741 return 0;
2742
2743err_out_unregister:
2744 if (dev1) {
2745 unregister_netdev(dev1);
2746 free_netdev(dev1);
2747 }
2748 unregister_netdev(dev);
2749err_out_free_netdev:
2750 free_netdev(dev);
2751err_out_free_pci:
2752 sky2_write8(hw, B0_CTST, CS_RST_SET);
2753 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
2754err_out_iounmap:
2755 iounmap(hw->regs);
2756err_out_free_hw:
2757 kfree(hw);
2758err_out_free_regions:
2759 pci_release_regions(pdev);
2760 pci_disable_device(pdev);
2761err_out:
2762 return err;
2763}
2764
2765static void __devexit sky2_remove(struct pci_dev *pdev)
2766{
2767 struct sky2_hw *hw = pci_get_drvdata(pdev);
2768 struct net_device *dev0, *dev1;
2769
2770 if (!hw)
2771 return;
2772
2773 dev0 = hw->dev[0];
2774 dev1 = hw->dev[1];
2775 if (dev1)
2776 unregister_netdev(dev1);
2777 unregister_netdev(dev0);
2778
2779 sky2_write32(hw, B0_IMSK, 0);
2780 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
2781 sky2_write8(hw, B0_CTST, CS_RST_SET);
2782
2783 free_irq(pdev->irq, hw);
2784 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
2785 pci_release_regions(pdev);
2786 pci_disable_device(pdev);
2787
2788 if (dev1)
2789 free_netdev(dev1);
2790 free_netdev(dev0);
2791 iounmap(hw->regs);
2792 kfree(hw);
2793 pci_set_drvdata(pdev, NULL);
2794}
2795
2796#ifdef CONFIG_PM
2797static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
2798{
2799 struct sky2_hw *hw = pci_get_drvdata(pdev);
2800 int i, wol = 0;
2801
2802 for (i = 0; i < 2; i++) {
2803 struct net_device *dev = hw->dev[i];
2804
2805 if (dev) {
2806 struct sky2_port *sky2 = netdev_priv(dev);
2807 if (netif_running(dev)) {
2808 netif_carrier_off(dev);
2809 sky2_down(dev);
2810 }
2811 netif_device_detach(dev);
2812 wol |= sky2->wol;
2813 }
2814 }
2815
2816 pci_save_state(pdev);
2817 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
2818 pci_disable_device(pdev);
2819 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2820
2821 return 0;
2822}
2823
2824static int sky2_resume(struct pci_dev *pdev)
2825{
2826 struct sky2_hw *hw = pci_get_drvdata(pdev);
2827 int i;
2828
2829 pci_set_power_state(pdev, PCI_D0);
2830 pci_restore_state(pdev);
2831 pci_enable_wake(pdev, PCI_D0, 0);
2832
2833 sky2_reset(hw);
2834
2835 for (i = 0; i < 2; i++) {
2836 struct net_device *dev = hw->dev[i];
2837 if (dev) {
2838 netif_device_attach(dev);
2839 if (netif_running(dev))
2840 sky2_up(dev);
2841 }
2842 }
2843 return 0;
2844}
2845#endif
2846
2847static struct pci_driver sky2_driver = {
2848 .name = DRV_NAME,
2849 .id_table = sky2_id_table,
2850 .probe = sky2_probe,
2851 .remove = __devexit_p(sky2_remove),
2852#ifdef CONFIG_PM
2853 .suspend = sky2_suspend,
2854 .resume = sky2_resume,
2855#endif
2856};
2857
2858static int __init sky2_init_module(void)
2859{
2860 return pci_module_init(&sky2_driver);
2861}
2862
2863static void __exit sky2_cleanup_module(void)
2864{
2865 pci_unregister_driver(&sky2_driver);
2866}
2867
2868module_init(sky2_init_module);
2869module_exit(sky2_cleanup_module);
2870
2871MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
2872MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
2873MODULE_LICENSE("GPL");
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
new file mode 100644
index 000000000000..9256303acf76
--- /dev/null
+++ b/drivers/net/sky2.h
@@ -0,0 +1,1931 @@
1/*
2 * Definitions for the new Marvell Yukon 2 driver.
3 */
4#ifndef _SKY2_H
5#define _SKY2_H
6
7/* PCI config registers */
8#define PCI_DEV_REG1 0x40
9#define PCI_DEV_REG2 0x44
10#define PCI_DEV_STATUS 0x7c
11#define PCI_OS_PCI_X (1<<26)
12
13#define PEX_LNK_STAT 0xf2
14#define PEX_UNC_ERR_STAT 0x104
15#define PEX_DEV_CTRL 0xe8
16
17/* Yukon-2 */
18enum pci_dev_reg_1 {
19 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
20 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
21 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
22 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
23 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
24 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
25};
26
27enum pci_dev_reg_2 {
28 PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
29 PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
30 PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
31
32 PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
33 PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
34 PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
35 PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
36
37 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
38};
39
40
41#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
42 PCI_STATUS_SIG_SYSTEM_ERROR | \
43 PCI_STATUS_REC_MASTER_ABORT | \
44 PCI_STATUS_REC_TARGET_ABORT | \
45 PCI_STATUS_PARITY)
46
47enum pex_dev_ctrl {
48 PEX_DC_MAX_RRS_MSK = 7<<12, /* Bit 14..12: Max. Read Request Size */
49 PEX_DC_EN_NO_SNOOP = 1<<11,/* Enable No Snoop */
50 PEX_DC_EN_AUX_POW = 1<<10,/* Enable AUX Power */
51 PEX_DC_EN_PHANTOM = 1<<9, /* Enable Phantom Functions */
52 PEX_DC_EN_EXT_TAG = 1<<8, /* Enable Extended Tag Field */
53 PEX_DC_MAX_PLS_MSK = 7<<5, /* Bit 7.. 5: Max. Payload Size Mask */
54 PEX_DC_EN_REL_ORD = 1<<4, /* Enable Relaxed Ordering */
55 PEX_DC_EN_UNS_RQ_RP = 1<<3, /* Enable Unsupported Request Reporting */
56 PEX_DC_EN_FAT_ER_RP = 1<<2, /* Enable Fatal Error Reporting */
57 PEX_DC_EN_NFA_ER_RP = 1<<1, /* Enable Non-Fatal Error Reporting */
58 PEX_DC_EN_COR_ER_RP = 1<<0, /* Enable Correctable Error Reporting */
59};
60#define PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK)
61
62/* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
63enum pex_err {
64 PEX_UNSUP_REQ = 1<<20, /* Unsupported Request Error */
65
66 PEX_MALFOR_TLP = 1<<18, /* Malformed TLP */
67
68 PEX_UNEXP_COMP = 1<<16, /* Unexpected Completion */
69
70 PEX_COMP_TO = 1<<14, /* Completion Timeout */
71 PEX_FLOW_CTRL_P = 1<<13, /* Flow Control Protocol Error */
72 PEX_POIS_TLP = 1<<12, /* Poisoned TLP */
73
74 PEX_DATA_LINK_P = 1<<4, /* Data Link Protocol Error */
75 PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P),
76};
77
78
79enum csr_regs {
80 B0_RAP = 0x0000,
81 B0_CTST = 0x0004,
82 B0_Y2LED = 0x0005,
83 B0_POWER_CTRL = 0x0007,
84 B0_ISRC = 0x0008,
85 B0_IMSK = 0x000c,
86 B0_HWE_ISRC = 0x0010,
87 B0_HWE_IMSK = 0x0014,
88 B0_SP_ISRC = 0x0018,
89 B0_XM1_IMSK = 0x0020,
90 B0_XM1_ISRC = 0x0028,
91 B0_XM1_PHY_ADDR = 0x0030,
92 B0_XM1_PHY_DATA = 0x0034,
93 B0_XM2_IMSK = 0x0040,
94 B0_XM2_ISRC = 0x0048,
95 B0_XM2_PHY_ADDR = 0x0050,
96 B0_XM2_PHY_DATA = 0x0054,
97 B0_R1_CSR = 0x0060,
98 B0_R2_CSR = 0x0064,
99 B0_XS1_CSR = 0x0068,
100 B0_XA1_CSR = 0x006c,
101 B0_XS2_CSR = 0x0070,
102 B0_XA2_CSR = 0x0074,
103
104 /* Special ISR registers (Yukon-2 only) */
105 B0_Y2_SP_ISRC2 = 0x001c,
106 B0_Y2_SP_ISRC3 = 0x0020,
107 B0_Y2_SP_EISR = 0x0024,
108 B0_Y2_SP_LISR = 0x0028,
109 B0_Y2_SP_ICR = 0x002c,
110
111 B2_MAC_1 = 0x0100,
112 B2_MAC_2 = 0x0108,
113 B2_MAC_3 = 0x0110,
114 B2_CONN_TYP = 0x0118,
115 B2_PMD_TYP = 0x0119,
116 B2_MAC_CFG = 0x011a,
117 B2_CHIP_ID = 0x011b,
118 B2_E_0 = 0x011c,
119 B2_E_1 = 0x011d,
120 B2_E_2 = 0x011e,
121 B2_Y2_CLK_GATE = 0x011d,
122 B2_Y2_HW_RES = 0x011e,
123 B2_E_3 = 0x011f,
124 B2_Y2_CLK_CTRL = 0x0120,
125 B2_LD_CTRL = 0x0128,
126 B2_LD_TEST = 0x0129,
127 B2_TI_INI = 0x0130,
128 B2_TI_VAL = 0x0134,
129 B2_TI_CTRL = 0x0138,
130 B2_TI_TEST = 0x0139,
131 B2_IRQM_INI = 0x0140,
132 B2_IRQM_VAL = 0x0144,
133 B2_IRQM_CTRL = 0x0148,
134 B2_IRQM_TEST = 0x0149,
135 B2_IRQM_MSK = 0x014c,
136 B2_IRQM_HWE_MSK = 0x0150,
137 B2_TST_CTRL1 = 0x0158,
138 B2_TST_CTRL2 = 0x0159,
139 B2_GP_IO = 0x015c,
140 B2_I2C_CTRL = 0x0160,
141 B2_I2C_DATA = 0x0164,
142 B2_I2C_IRQ = 0x0168,
143 B2_I2C_SW = 0x016c,
144 B2_BSC_INI = 0x0170,
145 B2_BSC_VAL = 0x0174,
146 B2_BSC_CTRL = 0x0178,
147 B2_BSC_STAT = 0x0179,
148 B2_BSC_TST = 0x017a,
149
150 B3_RAM_ADDR = 0x0180,
151 B3_RAM_DATA_LO = 0x0184,
152 B3_RAM_DATA_HI = 0x0188,
153
154/* RAM Interface Registers */
155/* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
156/*
157 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
158 * not usable in SW. Please notice these are NOT real timeouts, these are
159 * the number of qWords transferred continuously.
160 */
161#define RAM_BUFFER(port, reg) (reg | (port <<6))
162
163 B3_RI_WTO_R1 = 0x0190,
164 B3_RI_WTO_XA1 = 0x0191,
165 B3_RI_WTO_XS1 = 0x0192,
166 B3_RI_RTO_R1 = 0x0193,
167 B3_RI_RTO_XA1 = 0x0194,
168 B3_RI_RTO_XS1 = 0x0195,
169 B3_RI_WTO_R2 = 0x0196,
170 B3_RI_WTO_XA2 = 0x0197,
171 B3_RI_WTO_XS2 = 0x0198,
172 B3_RI_RTO_R2 = 0x0199,
173 B3_RI_RTO_XA2 = 0x019a,
174 B3_RI_RTO_XS2 = 0x019b,
175 B3_RI_TO_VAL = 0x019c,
176 B3_RI_CTRL = 0x01a0,
177 B3_RI_TEST = 0x01a2,
178 B3_MA_TOINI_RX1 = 0x01b0,
179 B3_MA_TOINI_RX2 = 0x01b1,
180 B3_MA_TOINI_TX1 = 0x01b2,
181 B3_MA_TOINI_TX2 = 0x01b3,
182 B3_MA_TOVAL_RX1 = 0x01b4,
183 B3_MA_TOVAL_RX2 = 0x01b5,
184 B3_MA_TOVAL_TX1 = 0x01b6,
185 B3_MA_TOVAL_TX2 = 0x01b7,
186 B3_MA_TO_CTRL = 0x01b8,
187 B3_MA_TO_TEST = 0x01ba,
188 B3_MA_RCINI_RX1 = 0x01c0,
189 B3_MA_RCINI_RX2 = 0x01c1,
190 B3_MA_RCINI_TX1 = 0x01c2,
191 B3_MA_RCINI_TX2 = 0x01c3,
192 B3_MA_RCVAL_RX1 = 0x01c4,
193 B3_MA_RCVAL_RX2 = 0x01c5,
194 B3_MA_RCVAL_TX1 = 0x01c6,
195 B3_MA_RCVAL_TX2 = 0x01c7,
196 B3_MA_RC_CTRL = 0x01c8,
197 B3_MA_RC_TEST = 0x01ca,
198 B3_PA_TOINI_RX1 = 0x01d0,
199 B3_PA_TOINI_RX2 = 0x01d4,
200 B3_PA_TOINI_TX1 = 0x01d8,
201 B3_PA_TOINI_TX2 = 0x01dc,
202 B3_PA_TOVAL_RX1 = 0x01e0,
203 B3_PA_TOVAL_RX2 = 0x01e4,
204 B3_PA_TOVAL_TX1 = 0x01e8,
205 B3_PA_TOVAL_TX2 = 0x01ec,
206 B3_PA_CTRL = 0x01f0,
207 B3_PA_TEST = 0x01f2,
208
209 Y2_CFG_SPC = 0x1c00,
210};
211
212/* B0_CTST 16 bit Control/Status register */
213enum {
214 Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
215 Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
216 Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
217 Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
218 Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
219 Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
220 Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
221 Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
222
223 CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
224 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
225 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
226 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
227 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
228 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
229 CS_MRST_CLR = 1<<3, /* Clear Master reset */
230 CS_MRST_SET = 1<<2, /* Set Master reset */
231 CS_RST_CLR = 1<<1, /* Clear Software reset */
232 CS_RST_SET = 1, /* Set Software reset */
233};
234
235/* B0_LED 8 Bit LED register */
236enum {
237/* Bit 7.. 2: reserved */
238 LED_STAT_ON = 1<<1, /* Status LED on */
239 LED_STAT_OFF = 1, /* Status LED off */
240};
241
242/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
243enum {
244 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
245 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
246 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
247 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
248 PC_VAUX_ON = 1<<3, /* Switch VAUX On */
249 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
250 PC_VCC_ON = 1<<1, /* Switch VCC On */
251 PC_VCC_OFF = 1<<0, /* Switch VCC Off */
252};
253
254/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
255
256/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
257/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
258/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
259/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
260enum {
261 Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */
262 Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */
263 Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */
264
265 Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */
266 Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */
267 Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */
268 Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */
269
270 Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */
271 Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */
272 Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */
273 Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */
274 Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */
275
276 Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */
277 Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */
278 Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */
279 Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */
280 Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */
281
282 Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU |
283 Y2_IS_POLL_CHK | Y2_IS_TWSI_RDY |
284 Y2_IS_IRQ_SW | Y2_IS_TIMINT,
285 Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 |
286 Y2_IS_CHK_RX1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXS1,
287 Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 |
288 Y2_IS_CHK_RX2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_TXS2,
289};
290
291/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
292enum {
293 IS_ERR_MSK = 0x00003fff,/* All Error bits */
294
295 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
296 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
297 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
298 IS_IRQ_STAT = 1<<10, /* IRQ status exception */
299 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
300 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
301 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
302 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
303 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
304 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
305 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
306 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
307 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
308 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
309};
310
311/* Hardware error interrupt mask for Yukon 2 */
312enum {
313 Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */
314 Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */
315 Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */
316 Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */
317 Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
318 Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
319 /* Link 2 */
320 Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */
321 Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */
322 Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */
323 Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */
324 Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */
325 Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */
326 /* Link 1 */
327 Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */
328 Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */
329 Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */
330 Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */
331 Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */
332 Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */
333
334 Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |
335 Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1,
336 Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
337 Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
338
339 Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
340 Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP |
341 Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
342};
343
344/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
345enum {
346 DPT_START = 1<<1,
347 DPT_STOP = 1<<0,
348};
349
350/* B2_TST_CTRL1 8 bit Test Control Register 1 */
351enum {
352 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
353 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
354 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
355 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
356 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
357 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
358 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
359 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
360};
361
362/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
363enum {
364 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
365 /* Bit 3.. 2: reserved */
366 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
367 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
368};
369
370/* B2_CHIP_ID 8 bit Chip Identification Number */
371enum {
372 CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
373 CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
374 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
375 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
376 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
377 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
378 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
379
380 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
381 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
382 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
383};
384
385/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
386enum {
387 Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactiv (0 = activ) */
388 Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
389 Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
390 Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
391 Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactiv (0 = activ) */
392 Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
393 Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
394 Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
395};
396
397/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
398enum {
399 CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */
400 CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */
401 CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */
402};
403#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
404#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
405
406
407/* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
408enum {
409 Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */
410#define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK)
411 Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */
412 Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */
413#define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
414#define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK)
415 Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */
416 Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */
417};
418
419/* B2_TI_CTRL 8 bit Timer control */
420/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
421enum {
422 TIM_START = 1<<2, /* Start Timer */
423 TIM_STOP = 1<<1, /* Stop Timer */
424 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
425};
426
427/* B2_TI_TEST 8 Bit Timer Test */
428/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
429/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
430enum {
431 TIM_T_ON = 1<<2, /* Test mode on */
432 TIM_T_OFF = 1<<1, /* Test mode off */
433 TIM_T_STEP = 1<<0, /* Test step */
434};
435
436/* B3_RAM_ADDR 32 bit RAM Address, to read or write */
437 /* Bit 31..19: reserved */
438#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
439/* RAM Interface Registers */
440
441/* B3_RI_CTRL 16 bit RAM Iface Control Register */
442enum {
443 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
444 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
445
446 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
447 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
448};
449
450#define SK_RI_TO_53 36 /* RAM interface timeout */
451
452
453/* Port related registers FIFO, and Arbiter */
454#define SK_REG(port,reg) (((port)<<7)+(reg))
455
456/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
457/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
458/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
459/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
460/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
461
462#define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
463
464/* TXA_CTRL 8 bit Tx Arbiter Control Register */
465enum {
466 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
467 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
468 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
469 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
470 TXA_START_RC = 1<<3, /* Start sync Rate Control */
471 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
472 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
473 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
474};
475
476/*
477 * Bank 4 - 5
478 */
479/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
480enum {
481 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
482 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
483 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
484 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
485 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
486 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
487 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
488};
489
490
491enum {
492 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
493 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
494 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
495 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
496 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
497 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
498 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
499 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
500 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
501};
502
503/* Queue Register Offsets, use Q_ADDR() to access */
504enum {
505 B8_Q_REGS = 0x0400, /* base of Queue registers */
506 Q_D = 0x00, /* 8*32 bit Current Descriptor */
507 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
508 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
509 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
510 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
511 Q_BC = 0x30, /* 32 bit Current Byte Counter */
512 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
513 Q_F = 0x38, /* 32 bit Flag Register */
514 Q_T1 = 0x3c, /* 32 bit Test Register 1 */
515 Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
516 Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
517 Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
518 Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
519 Q_T2 = 0x40, /* 32 bit Test Register 2 */
520 Q_T3 = 0x44, /* 32 bit Test Register 3 */
521
522/* Yukon-2 */
523 Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */
524 Q_WM = 0x40, /* 16 bit FIFO Watermark */
525 Q_AL = 0x42, /* 8 bit FIFO Alignment */
526 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
527 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
528 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
529 Q_RL = 0x4a, /* 8 bit FIFO Read Level */
530 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
531 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
532 Q_WL = 0x4e, /* 8 bit FIFO Write Level */
533 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
534};
535#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
536
537
538/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
539enum {
540 Y2_B8_PREF_REGS = 0x0450,
541
542 PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */
543 PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */
544 PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */
545 PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/
546 PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */
547 PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */
548 PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */
549 PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */
550 PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */
551 PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */
552
553 PREF_UNIT_MASK_IDX = 0x0fff,
554};
555#define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg))
556
557/* RAM Buffer Register Offsets */
558enum {
559
560 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
561 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
562 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
563 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
564 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
565 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
566 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
567 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
568 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
569 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
570 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
571 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
572 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
573 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
574};
575
576/* Receive and Transmit Queues */
577enum {
578 Q_R1 = 0x0000, /* Receive Queue 1 */
579 Q_R2 = 0x0080, /* Receive Queue 2 */
580 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
581 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
582 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
583 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
584};
585
586/* Different PHY Types */
587enum {
588 PHY_ADDR_MARV = 0,
589};
590
591#define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
592
593
594enum {
595 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
596 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
597 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
598 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
599
600 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
601
602/* Receive GMAC FIFO (YUKON and Yukon-2) */
603
604 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
605 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
606 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
607 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
608 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
609 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
610
611 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
612 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
613
614 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
615
616 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
617
618 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
619};
620
621
622/* Q_BC 32 bit Current Byte Counter */
623
624/* BMU Control Status Registers */
625/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
626/* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
627/* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
628/* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
629/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
630/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
631/* Q_CSR 32 bit BMU Control/Status Register */
632
633/* Rx BMU Control / Status Registers (Yukon-2) */
634enum {
635 BMU_IDLE = 1<<31, /* BMU Idle State */
636 BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
637 BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */
638
639 BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */
640 BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
641 BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
642 BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
643 BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
644 BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segmen. error (Tx) */
645 BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
646 BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
647 BMU_START = 1<<8, /* Start Rx/Tx Queue */
648 BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */
649 BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */
650 BMU_FIFO_ENA = 1<<5, /* Enable FIFO */
651 BMU_FIFO_RST = 1<<4, /* Reset FIFO */
652 BMU_OP_ON = 1<<3, /* BMU Operational On */
653 BMU_OP_OFF = 1<<2, /* BMU Operational Off */
654 BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */
655 BMU_RST_SET = 1<<0, /* Set BMU Reset */
656
657 BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
658 BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
659 BMU_FIFO_ENA | BMU_OP_ON,
660};
661
662/* Tx BMU Control / Status Registers (Yukon-2) */
663 /* Bit 31: same as for Rx */
664enum {
665 BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
666 BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
667 BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segm. length mism. */
668};
669
670/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
671/* PREF_UNIT_CTRL 32 bit Prefetch Control register */
672enum {
673 PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */
674 PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */
675 PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */
676 PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */
677};
678
679/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
680/* RB_START 32 bit RAM Buffer Start Address */
681/* RB_END 32 bit RAM Buffer End Address */
682/* RB_WP 32 bit RAM Buffer Write Pointer */
683/* RB_RP 32 bit RAM Buffer Read Pointer */
684/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
685/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
686/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
687/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
688/* RB_PC 32 bit RAM Buffer Packet Counter */
689/* RB_LEV 32 bit RAM Buffer Level Register */
690
691#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
692/* RB_TST2 8 bit RAM Buffer Test Register 2 */
693/* RB_TST1 8 bit RAM Buffer Test Register 1 */
694
695/* RB_CTRL 8 bit RAM Buffer Control Register */
696enum {
697 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
698 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
699 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
700 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
701 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
702 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
703};
704
705
706/* Transmit GMAC FIFO (YUKON only) */
707enum {
708 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
709 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
710 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
711
712 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
713 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
714 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
715
716 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
717 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
718 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
719};
720
721/* Descriptor Poll Timer Registers */
722enum {
723 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
724 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
725 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
726
727 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
728};
729
730/* Time Stamp Timer Registers (YUKON only) */
731enum {
732 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
733 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
734 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
735};
736
737/* Polling Unit Registers (Yukon-2 only) */
738enum {
739 POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */
740 POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */
741
742 POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */
743 POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
744};
745
746/* ASF Subsystem Registers (Yukon-2 only) */
747enum {
748 B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
749 B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */
750 B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */
751
752 B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */
753 B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */
754 B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */
755 B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */
756 B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */
757 B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */
758};
759
760/* Status BMU Registers (Yukon-2 only)*/
761enum {
762 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
763 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
764
765 STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */
766 STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */
767 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
768 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
769 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
770 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
771 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
772 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
773
774/* FIFO Control/Status Registers (Yukon-2 only)*/
775 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
776 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
777 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
778 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
779 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
780 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
781 STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
782
783/* Level and ISR Timer Registers (Yukon-2 only)*/
784 STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
785 STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */
786 STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */
787 STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */
788 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
789 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
790 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
791 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
792 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
793 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
794 STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
795 STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
796};
797
798enum {
799 LINKLED_OFF = 0x01,
800 LINKLED_ON = 0x02,
801 LINKLED_LINKSYNC_OFF = 0x04,
802 LINKLED_LINKSYNC_ON = 0x08,
803 LINKLED_BLINK_OFF = 0x10,
804 LINKLED_BLINK_ON = 0x20,
805};
806
807/* GMAC and GPHY Control Registers (YUKON only) */
808enum {
809 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
810 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
811 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
812 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
813 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
814
815/* Wake-up Frame Pattern Match Control Registers (YUKON only) */
816
817 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
818
819 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
820 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
821 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
822 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
823 WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */
824 WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */
825 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
826
827/* WOL Pattern Length Registers (YUKON only) */
828
829 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
830 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
831
832/* WOL Pattern Counter Registers (YUKON only) */
833
834
835 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
836 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
837};
838
839enum {
840 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
841 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
842};
843
844enum {
845 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
846 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
847};
848
849/*
850 * Marvel-PHY Registers, indirect addressed over GMAC
851 */
852enum {
853 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
854 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
855 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
856 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
857 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
858 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
859 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
860 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
861 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
862 /* Marvel-specific registers */
863 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
864 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
865 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
866 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
867 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
868 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
869 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
870 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
871 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
872 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
873 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
874 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
875 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
876 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
877 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
878 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
879 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
880 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
881
882/* for 10/100 Fast Ethernet PHY (88E3082 only) */
883 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
884 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
885 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
886 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
887 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
888};
889
890enum {
891 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
892 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
893 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
894 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
895 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
896 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
897 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
898 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
899 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
900 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
901};
902
903enum {
904 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
905 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
906 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
907};
908
909enum {
910 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
911
912 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
913 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
914 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
915 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
916 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
917 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
918 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
919};
920
921enum {
922 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
923 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
924 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
925};
926
927/* different Marvell PHY Ids */
928enum {
929 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
930
931 PHY_BCOM_ID1_A1 = 0x6041,
932 PHY_BCOM_ID1_B2 = 0x6043,
933 PHY_BCOM_ID1_C0 = 0x6044,
934 PHY_BCOM_ID1_C5 = 0x6047,
935
936 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
937 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
938 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
939 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
940};
941
942/* Advertisement register bits */
943enum {
944 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
945 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
946 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
947
948 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
949 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
950 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
951 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
952 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
953 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
954 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
955 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
956 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
957 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
958 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
959 PHY_AN_100HALF | PHY_AN_100FULL,
960};
961
962/***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
963/***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
964enum {
965 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
966 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
967 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
968 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
969 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
970 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
971 /* Bit 9..8: reserved */
972 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
973};
974
975/** Marvell-Specific */
976enum {
977 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
978 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
979 PHY_M_AN_RF = 1<<13, /* Remote Fault */
980
981 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
982 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
983 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
984 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
985 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
986 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
987 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
988 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
989};
990
991/* special defines for FIBER (88E1011S only) */
992enum {
993 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
994 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
995 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
996 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
997};
998
999/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1000enum {
1001 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1002 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1003 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1004 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1005};
1006
1007/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1008enum {
1009 PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1010 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1011 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1012 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1013 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
1014 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
1015};
1016
1017/***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1018enum {
1019 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1020 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1021 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1022 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
1023 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1024 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
1025 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1026 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
1027 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1028 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
1029 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
1030 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
1031};
1032
1033enum {
1034 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1035 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1036};
1037
1038#define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)
1039
1040enum {
1041 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
1042 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
1043 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1044};
1045
1046/* for 10/100 Fast Ethernet PHY (88E3082 only) */
1047enum {
1048 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1049 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1050 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1051 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1052 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1053
1054 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
1055 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1056
1057 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
1058 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1059};
1060
1061/***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1062enum {
1063 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1064 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
1065 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
1066 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
1067 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
1068 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
1069 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1070 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
1071 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1072 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
1073 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
1074 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
1075 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1076 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
1077 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
1078 PHY_M_PS_JABBER = 1<<0, /* Jabber */
1079};
1080
1081#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1082
1083/* for 10/100 Fast Ethernet PHY (88E3082 only) */
1084enum {
1085 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
1086 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1087};
1088
1089enum {
1090 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1091 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
1092 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1093 PHY_M_IS_AN_PR = 1<<12, /* Page Received */
1094 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1095 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
1096 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
1097 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
1098 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
1099 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
1100 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
1101 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
1102
1103 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
1104 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
1105 PHY_M_IS_JABBER = 1<<0, /* Jabber */
1106
1107 PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
1108 | PHY_M_IS_FIFO_ERROR,
1109 PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1110};
1111
1112
1113/***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1114enum {
1115 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1116 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1117
1118 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1119 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1120 /* (88E1011 only) */
1121 PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
1122 /* (88E1011 only) */
1123 PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
1124 /* (88E1111 only) */
1125 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1126 /* !!! Errata in spec. (1 = disable) */
1127 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1128 PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
1129 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1130 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1131 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1132 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
1133
1134#define PHY_M_EC_M_DSC(x) ((x)<<10 & PHY_M_EC_M_DSC_MSK)
1135 /* 00=1x; 01=2x; 10=3x; 11=4x */
1136#define PHY_M_EC_S_DSC(x) ((x)<<8 & PHY_M_EC_S_DSC_MSK)
1137 /* 00=dis; 01=1x; 10=2x; 11=3x */
1138#define PHY_M_EC_DSC_2(x) ((x)<<9 & PHY_M_EC_M_DSC_MSK2)
1139 /* 000=1x; 001=2x; 010=3x; 011=4x */
1140#define PHY_M_EC_MAC_S(x) ((x)<<4 & PHY_M_EC_MAC_S_MSK)
1141 /* 01X=0; 110=2.5; 111=25 (MHz) */
1142
1143/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1144enum {
1145 PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */
1146 PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */
1147 PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */
1148};
1149/* !!! Errata in spec. (1 = disable) */
1150
1151#define PHY_M_PC_DSC(x) (((x)<<12) & PHY_M_PC_DSC_MSK)
1152 /* 100=5x; 101=6x; 110=7x; 111=8x */
1153enum {
1154 MAC_TX_CLK_0_MHZ = 2,
1155 MAC_TX_CLK_2_5_MHZ = 6,
1156 MAC_TX_CLK_25_MHZ = 7,
1157};
1158
1159/***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1160enum {
1161 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
1162 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1163 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1164 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1165 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1166 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1167 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1168 /* (88E1111 only) */
1169};
1170
1171enum {
1172 PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
1173 /* (88E1011 only) */
1174 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
1175 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1176 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
1177 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1178 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1179};
1180
1181#define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK)
1182
1183/***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/
1184enum {
1185 PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
1186 PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
1187 PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
1188 PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
1189 PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
1190 PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
1191};
1192
1193#define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK)
1194#define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK)
1195#define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK)
1196#define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK)
1197#define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK)
1198#define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK)
1199
1200enum {
1201 PULS_NO_STR = 0,/* no pulse stretching */
1202 PULS_21MS = 1,/* 21 ms to 42 ms */
1203 PULS_42MS = 2,/* 42 ms to 84 ms */
1204 PULS_84MS = 3,/* 84 ms to 170 ms */
1205 PULS_170MS = 4,/* 170 ms to 340 ms */
1206 PULS_340MS = 5,/* 340 ms to 670 ms */
1207 PULS_670MS = 6,/* 670 ms to 1.3 s */
1208 PULS_1300MS = 7,/* 1.3 s to 2.7 s */
1209};
1210
1211#define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK)
1212
1213enum {
1214 BLINK_42MS = 0,/* 42 ms */
1215 BLINK_84MS = 1,/* 84 ms */
1216 BLINK_170MS = 2,/* 170 ms */
1217 BLINK_340MS = 3,/* 340 ms */
1218 BLINK_670MS = 4,/* 670 ms */
1219};
1220
1221/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1222#define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
1223 /* Bit 13..12: reserved */
1224#define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1225#define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
1226#define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
1227#define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
1228#define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
1229#define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1230
1231enum {
1232 MO_LED_NORM = 0,
1233 MO_LED_BLINK = 1,
1234 MO_LED_OFF = 2,
1235 MO_LED_ON = 3,
1236};
1237
1238/***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1239enum {
1240 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
1241 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1242 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1243 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
1244 PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
1245};
1246
1247/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1248enum {
1249 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1250 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
1251 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
1252 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1253 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1254 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
1255 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
1256 /* (88E1111 only) */
1257
1258 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1259 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1260 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1261};
1262
1263/* for 10/100 Fast Ethernet PHY (88E3082 only) */
1264/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1265 /* Bit 15..12: reserved (used internally) */
1266enum {
1267 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1268 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1269 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1270};
1271
1272#define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
1273#define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
1274#define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
1275
1276enum {
1277 LED_PAR_CTRL_COLX = 0x00,
1278 LED_PAR_CTRL_ERROR = 0x01,
1279 LED_PAR_CTRL_DUPLEX = 0x02,
1280 LED_PAR_CTRL_DP_COL = 0x03,
1281 LED_PAR_CTRL_SPEED = 0x04,
1282 LED_PAR_CTRL_LINK = 0x05,
1283 LED_PAR_CTRL_TX = 0x06,
1284 LED_PAR_CTRL_RX = 0x07,
1285 LED_PAR_CTRL_ACT = 0x08,
1286 LED_PAR_CTRL_LNK_RX = 0x09,
1287 LED_PAR_CTRL_LNK_AC = 0x0a,
1288 LED_PAR_CTRL_ACT_BL = 0x0b,
1289 LED_PAR_CTRL_TX_BL = 0x0c,
1290 LED_PAR_CTRL_RX_BL = 0x0d,
1291 LED_PAR_CTRL_COL_BL = 0x0e,
1292 LED_PAR_CTRL_INACT = 0x0f
1293};
1294
1295/*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1296enum {
1297 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
1298 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1299 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1300};
1301
1302/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1303/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1304enum {
1305 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1306 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1307 PHY_M_MAC_MD_COPPER = 5,/* Copper only */
1308 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1309};
1310#define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
1311
1312/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1313enum {
1314 PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
1315 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1316 PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1317 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1318};
1319
1320#define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1321#define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1322#define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1323#define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1324
1325/* GMAC registers */
1326/* Port Registers */
1327enum {
1328 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1329 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1330 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1331 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1332 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1333 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1334 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1335/* Source Address Registers */
1336 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1337 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1338 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1339 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1340 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1341 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1342
1343/* Multicast Address Hash Registers */
1344 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1345 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1346 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1347 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1348
1349/* Interrupt Source Registers */
1350 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1351 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1352 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1353
1354/* Interrupt Mask Registers */
1355 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1356 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1357 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1358
1359/* Serial Management Interface (SMI) Registers */
1360 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1361 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1362 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1363};
1364
1365/* MIB Counters */
1366#define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
1367#define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
1368
1369/*
1370 * MIB Counters base address definitions (low word) -
1371 * use offset 4 for access to high word (32 bit r/o)
1372 */
1373enum {
1374 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
1375 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
1376 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
1377 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
1378 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1379 /* GM_MIB_CNT_BASE + 40: reserved */
1380 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
1381 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
1382 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
1383 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
1384 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
1385 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
1386 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
1387 GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
1388 GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
1389 GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
1390 GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
1391 GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
1392 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
1393 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */
1394 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */
1395 /* GM_MIB_CNT_BASE + 168: reserved */
1396 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */
1397 /* GM_MIB_CNT_BASE + 184: reserved */
1398 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */
1399 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */
1400 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */
1401 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */
1402 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */
1403 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */
1404 GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */
1405 GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
1406 GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
1407 GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
1408 GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
1409 GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
1410 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
1411
1412 GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */
1413 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */
1414 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */
1415 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */
1416 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */
1417 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
1418};
1419
1420/* GMAC Bit Definitions */
1421/* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1422enum {
1423 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
1424 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1425 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1426 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
1427 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1428 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1429 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
1430 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
1431
1432 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1433 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1434 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
1435 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1436 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1437};
1438
1439/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1440enum {
1441 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1442 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1443 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1444 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1445 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1446 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1447 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1448 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
1449 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
1450 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1451 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1452 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
1453 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1454 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1455 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1456};
1457
1458#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1459#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
1460
1461/* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1462enum {
1463 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1464 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1465 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1466 GM_TXCR_COL_THR_MSK = 1<<10, /* Bit 12..10: Collision Threshold */
1467};
1468
1469#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
1470#define TX_COL_DEF 0x04
1471
1472/* GM_RX_CTRL 16 bit r/w Receive Control Register */
1473enum {
1474 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1475 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1476 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1477 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
1478};
1479
1480/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1481enum {
1482 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
1483 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
1484 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
1485 GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */
1486
1487 TX_JAM_LEN_DEF = 0x03,
1488 TX_JAM_IPG_DEF = 0x0b,
1489 TX_IPG_JAM_DEF = 0x1c,
1490 TX_BOF_LIM_DEF = 0x04,
1491};
1492
1493#define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
1494#define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
1495#define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
1496#define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
1497
1498
1499/* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1500enum {
1501 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1502 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
1503 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
1504 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
1505 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1506};
1507
1508#define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1509#define DATA_BLIND_DEF 0x04
1510
1511#define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
1512#define IPG_DATA_DEF 0x1e
1513
1514/* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1515enum {
1516 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
1517 GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
1518 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1519 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
1520 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
1521};
1522
1523#define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
1524#define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
1525
1526/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1527enum {
1528 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1529 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1530};
1531
1532/* Receive Frame Status Encoding */
1533enum {
1534 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
1535 GMR_FS_VLAN = 1<<13, /* VLAN Packet */
1536 GMR_FS_JABBER = 1<<12, /* Jabber Packet */
1537 GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */
1538 GMR_FS_MC = 1<<10, /* Multicast Packet */
1539 GMR_FS_BC = 1<<9, /* Broadcast Packet */
1540 GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */
1541 GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
1542 GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
1543 GMR_FS_MII_ERR = 1<<5, /* MII Error */
1544 GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */
1545 GMR_FS_FRAGMENT = 1<<3, /* Fragment */
1546
1547 GMR_FS_CRC_ERR = 1<<1, /* CRC Error */
1548 GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */
1549
1550 GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
1551 GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
1552 GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
1553 GMR_FS_UN_SIZE | GMR_FS_JABBER,
1554};
1555
1556/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1557enum {
1558 RX_TRUNC_ON = 1<<27, /* enable packet truncation */
1559 RX_TRUNC_OFF = 1<<26, /* disable packet truncation */
1560 RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */
1561 RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */
1562
1563 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
1564 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
1565 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
1566
1567 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
1568 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
1569 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
1570 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1571 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
1572 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
1573 GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */
1574
1575 GMF_OPER_ON = 1<<3, /* Operational Mode On */
1576 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
1577 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
1578 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
1579
1580 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
1581};
1582
1583
1584/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1585enum {
1586 TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */
1587 TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */
1588
1589 GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
1590 GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
1591 GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
1592
1593 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1594 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
1595 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
1596};
1597
1598/* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1599enum {
1600 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
1601 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
1602 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
1603};
1604
1605/* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
1606enum {
1607 Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */
1608 Y2_ASF_RESET = 1<<3, /* ASF system in reset state */
1609 Y2_ASF_RUNNING = 1<<2, /* ASF system operational */
1610 Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */
1611 Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */
1612
1613 Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */
1614 Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */
1615};
1616
1617/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
1618enum {
1619 Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */
1620 Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */
1621};
1622
1623/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
1624enum {
1625 SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */
1626 SC_STAT_OP_ON = 1<<3, /* Operational Mode On */
1627 SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */
1628 SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */
1629 SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */
1630};
1631
1632/* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1633enum {
1634 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
1635 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
1636 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
1637 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
1638 GMC_PAUSE_ON = 1<<3, /* Pause On */
1639 GMC_PAUSE_OFF = 1<<2, /* Pause Off */
1640 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
1641 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
1642};
1643
1644/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1645enum {
1646 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1647 GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
1648 GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
1649 GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
1650 GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
1651 GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
1652 GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
1653 GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
1654 GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
1655 GPC_ANEG_0 = 1<<19, /* ANEG[0] */
1656 GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
1657 GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
1658 GPC_ANEG_3 = 1<<16, /* ANEG[3] */
1659 GPC_ANEG_2 = 1<<15, /* ANEG[2] */
1660 GPC_ANEG_1 = 1<<14, /* ANEG[1] */
1661 GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
1662 GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
1663 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
1664 GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
1665 GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
1666 GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
1667 /* Bits 7..2: reserved */
1668 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
1669 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
1670};
1671
1672/* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
1673/* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
1674enum {
1675 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
1676 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
1677 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
1678 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
1679 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
1680 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
1681
1682#define GMAC_DEF_MSK (GM_IS_TX_FF_UR|GM_IS_RX_FF_OR)
1683
1684/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
1685 /* Bits 15.. 2: reserved */
1686 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
1687 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
1688
1689
1690/* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1691 WOL_CTL_LINK_CHG_OCC = 1<<15,
1692 WOL_CTL_MAGIC_PKT_OCC = 1<<14,
1693 WOL_CTL_PATTERN_OCC = 1<<13,
1694 WOL_CTL_CLEAR_RESULT = 1<<12,
1695 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
1696 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
1697 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
1698 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
1699 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
1700 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
1701 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
1702 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
1703 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
1704 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
1705 WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
1706 WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
1707};
1708
1709#define WOL_CTL_DEFAULT \
1710 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
1711 WOL_CTL_DIS_PME_ON_PATTERN | \
1712 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
1713 WOL_CTL_DIS_LINK_CHG_UNIT | \
1714 WOL_CTL_DIS_PATTERN_UNIT | \
1715 WOL_CTL_DIS_MAGIC_PKT_UNIT)
1716
1717/* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
1718#define WOL_CTL_PATT_ENA(x) (1 << (x))
1719
1720
1721/* Control flags */
1722enum {
1723 UDPTCP = 1<<0,
1724 CALSUM = 1<<1,
1725 WR_SUM = 1<<2,
1726 INIT_SUM= 1<<3,
1727 LOCK_SUM= 1<<4,
1728 INS_VLAN= 1<<5,
1729 FRC_STAT= 1<<6,
1730 EOP = 1<<7,
1731};
1732
1733enum {
1734 HW_OWNER = 1<<7,
1735 OP_TCPWRITE = 0x11,
1736 OP_TCPSTART = 0x12,
1737 OP_TCPINIT = 0x14,
1738 OP_TCPLCK = 0x18,
1739 OP_TCPCHKSUM = OP_TCPSTART,
1740 OP_TCPIS = OP_TCPINIT | OP_TCPSTART,
1741 OP_TCPLW = OP_TCPLCK | OP_TCPWRITE,
1742 OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE,
1743 OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE,
1744
1745 OP_ADDR64 = 0x21,
1746 OP_VLAN = 0x22,
1747 OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN,
1748 OP_LRGLEN = 0x24,
1749 OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN,
1750 OP_BUFFER = 0x40,
1751 OP_PACKET = 0x41,
1752 OP_LARGESEND = 0x43,
1753
1754/* YUKON-2 STATUS opcodes defines */
1755 OP_RXSTAT = 0x60,
1756 OP_RXTIMESTAMP = 0x61,
1757 OP_RXVLAN = 0x62,
1758 OP_RXCHKS = 0x64,
1759 OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN,
1760 OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN,
1761 OP_RSS_HASH = 0x65,
1762 OP_TXINDEXLE = 0x68,
1763};
1764
1765/* Yukon 2 hardware interface
1766 * Not tested on big endian
1767 */
1768struct sky2_tx_le {
1769 union {
1770 u32 addr;
1771 struct {
1772 u16 offset;
1773 u16 start;
1774 } csum __attribute((packed));
1775 struct {
1776 u16 size;
1777 u16 rsvd;
1778 } tso __attribute((packed));
1779 } tx;
1780 u16 length; /* also vlan tag or checksum start */
1781 u8 ctrl;
1782 u8 opcode;
1783} __attribute((packed));
1784
1785struct sky2_rx_le {
1786 u32 addr;
1787 u16 length;
1788 u8 ctrl;
1789 u8 opcode;
1790} __attribute((packed));;
1791
1792struct sky2_status_le {
1793 u32 status; /* also checksum */
1794 u16 length; /* also vlan tag */
1795 u8 link;
1796 u8 opcode;
1797} __attribute((packed));
1798
1799struct ring_info {
1800 struct sk_buff *skb;
1801 dma_addr_t mapaddr;
1802 u16 maplen;
1803 u16 idx;
1804};
1805
1806struct sky2_port {
1807 struct sky2_hw *hw;
1808 struct net_device *netdev;
1809 unsigned port;
1810 u32 msg_enable;
1811
1812 struct ring_info *tx_ring;
1813 struct sky2_tx_le *tx_le;
1814 spinlock_t tx_lock;
1815 u32 tx_addr64;
1816 u16 tx_cons; /* next le to check */
1817 u16 tx_prod; /* next le to use */
1818 u16 tx_pending;
1819 u16 tx_last_put;
1820 u16 tx_last_mss;
1821
1822 struct ring_info *rx_ring;
1823 struct sky2_rx_le *rx_le;
1824 u32 rx_addr64;
1825 u16 rx_next; /* next re to check */
1826 u16 rx_put; /* next le index to use */
1827 u16 rx_pending;
1828 u16 rx_last_put;
1829
1830 dma_addr_t rx_le_map;
1831 dma_addr_t tx_le_map;
1832 u32 advertising; /* ADVERTISED_ bits */
1833 u16 speed; /* SPEED_1000, SPEED_100, ... */
1834 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
1835 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
1836 u8 rx_pause;
1837 u8 tx_pause;
1838 u8 rx_csum;
1839 u8 wol;
1840
1841 struct tasklet_struct phy_task;
1842 struct net_device_stats net_stats;
1843};
1844
1845struct sky2_hw {
1846 void __iomem *regs;
1847 struct pci_dev *pdev;
1848 u32 intr_mask;
1849 struct net_device *dev[2];
1850
1851 u8 chip_id;
1852 u8 chip_rev;
1853 u8 copper;
1854 u8 ports;
1855
1856 struct sky2_status_le *st_le;
1857 u32 st_idx;
1858 dma_addr_t st_dma;
1859
1860 spinlock_t phy_lock;
1861};
1862
1863/* Register accessor for memory mapped device */
1864static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
1865{
1866 return readl(hw->regs + reg);
1867}
1868
1869static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
1870{
1871 return readw(hw->regs + reg);
1872}
1873
1874static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
1875{
1876 return readb(hw->regs + reg);
1877}
1878
1879/* This should probably go away, bus based tweeks suck */
1880static inline int is_pciex(const struct sky2_hw *hw)
1881{
1882 u32 status;
1883 pci_read_config_dword(hw->pdev, PCI_DEV_STATUS, &status);
1884 return (status & PCI_OS_PCI_X) == 0;
1885}
1886
1887static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
1888{
1889 writel(val, hw->regs + reg);
1890}
1891
1892static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
1893{
1894 writew(val, hw->regs + reg);
1895}
1896
1897static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
1898{
1899 writeb(val, hw->regs + reg);
1900}
1901
1902/* Yukon PHY related registers */
1903#define SK_GMAC_REG(port,reg) \
1904 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
1905#define GM_PHY_RETRIES 100
1906
1907static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg)
1908{
1909 return sky2_read16(hw, SK_GMAC_REG(port,reg));
1910}
1911
1912static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
1913{
1914 unsigned base = SK_GMAC_REG(port, reg);
1915 return (u32) sky2_read16(hw, base)
1916 | (u32) sky2_read16(hw, base+4) << 16;
1917}
1918
1919static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
1920{
1921 sky2_write16(hw, SK_GMAC_REG(port,r), v);
1922}
1923
1924static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
1925 const u8 *addr)
1926{
1927 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
1928 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
1929 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
1930}
1931#endif
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