aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pcmcia/o2micro.h34
1 files changed, 27 insertions, 7 deletions
diff --git a/drivers/pcmcia/o2micro.h b/drivers/pcmcia/o2micro.h
index b1f6e3d9ee06..a234ce1967a3 100644
--- a/drivers/pcmcia/o2micro.h
+++ b/drivers/pcmcia/o2micro.h
@@ -120,11 +120,16 @@
120#define O2_MODE_E_LED_OUT 0x08 120#define O2_MODE_E_LED_OUT 0x08
121#define O2_MODE_E_SKTA_ACTV 0x10 121#define O2_MODE_E_SKTA_ACTV 0x10
122 122
123#define O2_RESERVED1 0x94
124#define O2_RESERVED2 0xD4
125#define O2_RES_READ_PREFETCH 0x02
126#define O2_RES_WRITE_BURST 0x08
127
123static int o2micro_override(struct yenta_socket *socket) 128static int o2micro_override(struct yenta_socket *socket)
124{ 129{
125 /* 130 /*
126 * 'reserved' register at 0x94/D4. chaning it to 0xCA (8 bit) enables 131 * 'reserved' register at 0x94/D4. allows setting read prefetch and write
127 * read prefetching which for example makes the RME Hammerfall DSP 132 * bursting. read prefetching for example makes the RME Hammerfall DSP
128 * working. for some bridges it is at 0x94, for others at 0xD4. it's 133 * working. for some bridges it is at 0x94, for others at 0xD4. it's
129 * ok to write to both registers on all O2 bridges. 134 * ok to write to both registers on all O2 bridges.
130 * from Eric Still, 02Micro. 135 * from Eric Still, 02Micro.
@@ -132,20 +137,35 @@ static int o2micro_override(struct yenta_socket *socket)
132 u8 a, b; 137 u8 a, b;
133 138
134 if (PCI_FUNC(socket->dev->devfn) == 0) { 139 if (PCI_FUNC(socket->dev->devfn) == 0) {
135 a = config_readb(socket, 0x94); 140 a = config_readb(socket, O2_RESERVED1);
136 b = config_readb(socket, 0xD4); 141 b = config_readb(socket, O2_RESERVED2);
137 142
138 printk(KERN_INFO "Yenta O2: res at 0x94/0xD4: %02x/%02x\n", a, b); 143 printk(KERN_INFO "Yenta O2: res at 0x94/0xD4: %02x/%02x\n", a, b);
139 144
140 switch (socket->dev->device) { 145 switch (socket->dev->device) {
146 /*
147 * older bridges have problems with both read prefetch and write
148 * bursting depending on the combination of the chipset, bridge
149 * and the cardbus card. so disable them to be on the safe side.
150 */
151 case PCI_DEVICE_ID_O2_6729:
152 case PCI_DEVICE_ID_O2_6730:
153 case PCI_DEVICE_ID_O2_6812:
141 case PCI_DEVICE_ID_O2_6832: 154 case PCI_DEVICE_ID_O2_6832:
142 printk(KERN_INFO "Yenta O2: old bridge, not enabling read prefetch / write burst\n"); 155 case PCI_DEVICE_ID_O2_6836:
156 printk(KERN_INFO "Yenta O2: old bridge, disabling read prefetch/write burst\n");
157 config_writeb(socket, O2_RESERVED1,
158 a & ~(O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST));
159 config_writeb(socket, O2_RESERVED2,
160 b & ~(O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST));
143 break; 161 break;
144 162
145 default: 163 default:
146 printk(KERN_INFO "Yenta O2: enabling read prefetch/write burst\n"); 164 printk(KERN_INFO "Yenta O2: enabling read prefetch/write burst\n");
147 config_writeb(socket, 0x94, a | 0x0a); 165 config_writeb(socket, O2_RESERVED1,
148 config_writeb(socket, 0xD4, b | 0x0a); 166 a | O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST);
167 config_writeb(socket, O2_RESERVED2,
168 b | O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST);
149 } 169 }
150 } 170 }
151 171